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proj_single_cycle.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2022.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="61" Path="D:/lab2_miniRV/proj_single_cycle.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
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<Option Name="Id" Val="c7409b1ddabf4fa18ec9204b6edbe050"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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<Option Name="SimulatorInstallDirVCS" Val=""/>
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<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
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<Option Name="SimulatorVersionModelSim" Val="2022.2"/>
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<Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
<Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
<Option Name="SimulatorVersionRiviera" Val="2022.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
<Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
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<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="WTXSimLaunchSim" Val="40"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="32"/>
<Option Name="WTModelSimExportSim" Val="32"/>
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<Option Name="WTIesExportSim" Val="9"/>
<Option Name="WTVcsExportSim" Val="32"/>
<Option Name="WTRivieraExportSim" Val="32"/>
<Option Name="WTActivehdlExportSim" Val="32"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/defines.vh">
<FileInfo>
<Attr Name="IsGlobalInclude" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
<Attr Name="IsVisible" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/DRAM1/DRAM1.xci">
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<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/DRAM0/DRAM0.xci">
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</File>
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<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/ALU.v">
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<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
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</File>
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</File>
<File Path="$PSRCDIR/sources_1/new/Controller.v">
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<Attr Name="UsedIn" Val="simulation"/>
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</File>
<File Path="$PSRCDIR/sources_1/new/DM.v">
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<Attr Name="UsedIn" Val="simulation"/>
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</File>
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<FileInfo>
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</File>
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<Attr Name="UsedIn" Val="simulation"/>
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</File>
<File Path="$PSRCDIR/sources_1/new/Switches.v">
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</File>
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</File>
<File Path="$PSRCDIR/sources_1/new/myCPU.v">
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<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
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<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Buttons.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/calculator.coe">
<FileInfo>
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<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/controller.coe">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/inst_rom.coe">
<FileInfo>
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</FileInfo>
</File>
<File Path="$PPRDIR/data_ram.coe">
<FileInfo>
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<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/data_ram_0.coe">
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<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/data_ram_1.coe">
<FileInfo>
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<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
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<FileInfo>
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<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
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<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="miniRV_SoC"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/miniRV_clock.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/constrs_1/new/miniRV_SoC.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/miniRV_SoC.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/miniRV_sim.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="miniRV_sim"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<File Path="$PSRCDIR/utils_1/imports/impl_1/miniRV_SoC_routed.dcp">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedInSteps" Val="impl_1"/>
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/utils_1/imports/synth_1/miniRV_SoC.dcp">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedInSteps" Val="synth_1"/>
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="cpuclk" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cpuclk" RelGenDir="$PGENDIR/cpuclk">
<File Path="$PSRCDIR/sources_1/ip/cpuclk/cpuclk.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="cpuclk"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="Controller_ROM" Type="BlockSrcs" RelSrcDir="$PSRCDIR/Controller_ROM" RelGenDir="$PGENDIR/Controller_ROM">
<File Path="$PSRCDIR/sources_1/ip/Controller_ROM/Controller_ROM.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="Controller_ROM"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="DRAM2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/DRAM2" RelGenDir="$PGENDIR/DRAM2">
<File Path="$PSRCDIR/sources_1/ip/DRAM2/DRAM2.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="DRAM2"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
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<File Path="$PSRCDIR/sources_1/ip/DRAM3/DRAM3.xci">
<FileInfo>
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</File>
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<Option Name="dataflowViewerSettings" Val="min_width=16"/>
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</Config>
</FileSet>
</FileSets>
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<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="19">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tfgg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/miniRV_SoC.dcp" WriteIncrSynthDcp="true" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
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</Strategy>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
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<RQSFiles/>
</Run>
<Run Id="cpuclk_synth_1" Type="Ft3:Synth" SrcSet="cpuclk" Part="xc7a100tfgg484-1" ConstrsSet="cpuclk" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cpuclk_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cpuclk_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cpuclk_synth_1">
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