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README.md

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This repository is an archive of an old project. It was an attempt to implement a CIC, an UIGR and a D4 patch in Verilog but I never took the time to finish this project.

  • the code is ugly (that was my first Verilog project)
  • the code is not commented
  • the project has been tested on a Cyclone FPGA
  • i used Quartus Prime to synthesize the project