diff --git a/OSC136H.m b/OSC136H.m index bef996c..46a881e 100755 --- a/OSC136H.m +++ b/OSC136H.m @@ -103,7 +103,8 @@ function WriteToWireIn(this, endpoint, begin, write_length, value) % Configure % Takes a filename as a path to the bitfile, and loads it onto the % FPGA. The desired bitfile is titled 'config.bit'. - function Configure(this, filename) + function ret = Configure(this, filename) + ret = -1; ec = calllib('okFrontPanel', 'okFrontPanel_ConfigureFPGA', this.dev, filename); if ec ~= "ok_NoError" fprintf('Error loading bitfile\n') @@ -125,6 +126,7 @@ function Configure(this, filename) calllib('okFrontPanel', 'okPLL22150_SetOutputEnable', pll, 1, 1); calllib('okFrontPanel', 'okFrontPanel_SetPLL22150Configuration', this.dev, pll); + ret = 0; end % Gets list of serial numbers for all connected boards @@ -170,6 +172,29 @@ function Configure(this, filename) % this.WriteToWireIn(hex2dec('17'), 0, 16, 0); end + function ec = ConnectToFirst(this) + % For now, all this function does is connect to the first + % available board. + ec = 0; + serial = this.GetBoardSerials(); + this.dev = calllib('okFrontPanel', 'okFrontPanel_Construct'); + calllib('okFrontPanel', 'okFrontPanel_OpenBySerial', this.dev, serial); + open = calllib('okFrontPanel', 'okFrontPanel_IsOpen', this.dev); + if ~open + fprintf('Failed to open board\n') + ec = -1; + return + end + fprintf('Successfully opened board\n') +% this.Configure('OSC1_LITE_Control.bit'); + pause(0.5); + if this.Configure('OSC1_LITE_Control.bit') == -1 || this.SysReset() == -1 || this.SetControlReg() == -1 + fprintf('Failed to initialize.\n') + return + end + this.WriteToWireIn(hex2dec('17'), 0, 16, 0); + end + function SetAllZero(this) this.WriteToWireIn(hex2dec('00'), 0, 16, 0); this.WriteToWireIn(hex2dec('01'), 0, 16, 1); @@ -182,7 +207,7 @@ function SetAllHigh(this) this.WriteToWireIn(hex2dec('00'), 0, 16, 0); this.WriteToWireIn(hex2dec('01'), 0, 16, 1); for channel = 0: 11 - this.WriteToWireIn(hex2dec('03') + channel, 0, 16, 2^14); + this.WriteToWireIn(hex2dec('03') + channel, 0, 16, 2731); end end @@ -360,7 +385,7 @@ function MatTrigger(this, cus_time) success_ret = calllib('okFrontPanel', 'okFrontPanel_WriteToPipeIn', this.dev, hex2dec('80'), 2 * SIZE, data_out); fprintf('Success %d \n', success_ret); - this.WriteToWireIn(hex2dec('00'), 0, 16, 2 ^ (channel + 1)); % switch to pipe mode + this.WriteToWireIn(hex2dec('00'), 0, 16, 2^16-2); % switch to pipe mode this.WriteToWireIn(hex2dec('01'), 0, 16, 1); % switch to write mode persistent buf pv; diff --git a/OSC1_LITE_Control.bit b/OSC1_LITE_Control.bit index ec5a857..b99c6be 100755 Binary files a/OSC1_LITE_Control.bit and b/OSC1_LITE_Control.bit differ diff --git a/OSCGUI.m b/OSCGUI.m index 849f1a0..0c89657 100755 --- a/OSCGUI.m +++ b/OSCGUI.m @@ -353,9 +353,9 @@ function CreatePipePanel(this) align(cancel_button,'Center','None'); ax1 = axes('units','normalized','Parent',this.pipe_f,'position',[0.045 0.078 0.447 0.447],'Visible','off'); - myImage = imread('cus_waveform_inst.jpg'); +% myImage = imread('cus_waveform_inst.jpg'); axes(ax1); - imshow(myImage); +% imshow(myImage); end function SaveParameterCallback(this, source, eventdata) diff --git a/project_LITE/project_LITE/17.cache/wt/gui_resources.wdf b/project_LITE/project_LITE/17.cache/wt/gui_resources.wdf index e012e28..320970f 100755 --- a/project_LITE/project_LITE/17.cache/wt/gui_resources.wdf +++ b/project_LITE/project_LITE/17.cache/wt/gui_resources.wdf @@ -1,6 +1,7 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:626173656469616c6f675f63616e63656c:3631:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:626173656469616c6f675f6f6b:3736:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:626173656469616c6f675f63616e63656c:3634:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:626173656469616c6f675f6f6b:3830:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:626173656469616c6f675f796573:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:636d646d73676469616c6f675f6d65737361676573:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:636d646d73676469616c6f675f6f6b:3138:00:00 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:636d646d73676469616c6f675f6f70656e5f6d657373616765735f76696577:32:00:00 @@ -16,9 +17,9 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6578707265706f72747472656570616e656c5f6578705f7265706f72745f747265655f7461626c65:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3133:00:00 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6578706c6f72656168656164766965775f6c61756e63685f73656c65637465645f72756e73:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:333336:00:00 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70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:686163676374616262656470616e655f7461626265645f70616e65:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:68636f6465656469746f725f636c6f7365:35:00:00 @@ -29,6 +30,7 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d61696e6d656e756d67725f68656c70:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d61696e6d656e756d67725f6f70656e5f726563656e745f66696c65:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d61696e6d656e756d67725f6f70656e5f726563656e745f70726f6a656374:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d657373616765776974686f7074696f6e6469616c6f675f646f6e745f73686f775f746869735f6469616c6f675f616761696e:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:3333:00:00 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d7367766965775f637269746963616c5f7761726e696e6773:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d7367766965775f696e666f726d6174696f6e5f6d65737361676573:34:00:00 @@ -41,6 +43,7 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3330:00:00 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f636f70795f6970:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f637573746f6d697a655f636f7265:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f6c6f675f77696e646f77:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f6d6573736167655f77696e646f77:32:00:00 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a/project_LITE/project_LITE/17.cache/wt/java_command_handlers.wdf +++ b/project_LITE/project_LITE/17.cache/wt/java_command_handlers.wdf @@ -8,19 +8,19 @@ version:1 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69707861637466696c65:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:3131:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:35:00:00 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70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b73796e746865736973:31:00:00 -eof:2885758028 +eof:3924594294 diff --git a/project_LITE/project_LITE/17.cache/wt/project.wpc b/project_LITE/project_LITE/17.cache/wt/project.wpc index aff2543..248f7d4 100755 --- a/project_LITE/project_LITE/17.cache/wt/project.wpc +++ b/project_LITE/project_LITE/17.cache/wt/project.wpc @@ -1,4 +1,4 @@ version:1 -57656254616c6b5472616e736d697373696f6e417474656d70746564:51 -6d6f64655f636f756e7465727c4755494d6f6465:27 +57656254616c6b5472616e736d697373696f6e417474656d70746564:52 +6d6f64655f636f756e7465727c4755494d6f6465:28 eof: diff --git a/project_LITE/project_LITE/17.cache/wt/synthesis.wdf b/project_LITE/project_LITE/17.cache/wt/synthesis.wdf index 771f3aa..587d439 100755 --- a/project_LITE/project_LITE/17.cache/wt/synthesis.wdf +++ b/project_LITE/project_LITE/17.cache/wt/synthesis.wdf @@ -34,6 +34,6 @@ version:1 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a/project_LITE/project_LITE/17.cache/wt/webtalk_pa.xml +++ b/project_LITE/project_LITE/17.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
@@ -26,16 +26,16 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + @@ -43,8 +43,9 @@ This means code written to parse this file will need to be revisited each subseq - - + + + @@ -60,9 +61,9 @@ This means code written to parse this file will need to be revisited each subseq - - - + + + @@ -73,6 +74,7 @@ This means code written to parse this file will need to be revisited each subseq + @@ -85,6 +87,7 @@ This means code written to parse this file will need to be revisited each subseq + diff --git a/project_LITE/project_LITE/17.runs/.jobs/vrs_config_59.xml b/project_LITE/project_LITE/17.runs/.jobs/vrs_config_59.xml new file mode 100755 index 0000000..63919dc --- /dev/null +++ b/project_LITE/project_LITE/17.runs/.jobs/vrs_config_59.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/project_LITE/project_LITE/17.runs/.jobs/vrs_config_60.xml b/project_LITE/project_LITE/17.runs/.jobs/vrs_config_60.xml new file mode 100755 index 0000000..63919dc --- /dev/null +++ b/project_LITE/project_LITE/17.runs/.jobs/vrs_config_60.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/project_LITE/project_LITE/17.runs/impl_1/.init_design.begin.rst b/project_LITE/project_LITE/17.runs/impl_1/.init_design.begin.rst index 20324bd..3689f84 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/.init_design.begin.rst +++ b/project_LITE/project_LITE/17.runs/impl_1/.init_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_LITE/project_LITE/17.runs/impl_1/.opt_design.begin.rst b/project_LITE/project_LITE/17.runs/impl_1/.opt_design.begin.rst index 20324bd..3689f84 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/.opt_design.begin.rst +++ b/project_LITE/project_LITE/17.runs/impl_1/.opt_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_LITE/project_LITE/17.runs/impl_1/.place_design.begin.rst b/project_LITE/project_LITE/17.runs/impl_1/.place_design.begin.rst index 20324bd..3689f84 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/.place_design.begin.rst +++ b/project_LITE/project_LITE/17.runs/impl_1/.place_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_LITE/project_LITE/17.runs/impl_1/.route_design.begin.rst b/project_LITE/project_LITE/17.runs/impl_1/.route_design.begin.rst index 20324bd..3689f84 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/.route_design.begin.rst +++ b/project_LITE/project_LITE/17.runs/impl_1/.route_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_LITE/project_LITE/17.runs/impl_1/.vivado.begin.rst b/project_LITE/project_LITE/17.runs/impl_1/.vivado.begin.rst index 74bcd71..2e79051 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/.vivado.begin.rst +++ b/project_LITE/project_LITE/17.runs/impl_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_LITE/project_LITE/17.runs/impl_1/.write_bitstream.begin.rst b/project_LITE/project_LITE/17.runs/impl_1/.write_bitstream.begin.rst index 20324bd..3689f84 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/.write_bitstream.begin.rst +++ b/project_LITE/project_LITE/17.runs/impl_1/.write_bitstream.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control.bit b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control.bit deleted file mode 100755 index ec5a857..0000000 Binary files a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control.bit and /dev/null differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control.vdi b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control.vdi index 823cf48..286ba5a 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control.vdi +++ b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control.vdi @@ -2,8 +2,8 @@ # Vivado v2017.2 (64-bit) # SW Build 1909853 on Thu Jun 15 18:39:09 MDT 2017 # IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 -# Start of session at: Tue Feb 26 23:48:47 2019 -# Process ID: 46356 +# Start of session at: Tue Mar 19 18:59:33 2019 +# Process ID: 44628 # Current directory: C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/impl_1 # Command line: vivado.exe -log OSC1_LITE_Control.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source OSC1_LITE_Control.tcl -notrace # Log file: C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control.vdi @@ -37,7 +37,7 @@ INFO: [Project 1-111] Unisim Transformation Summary: RAM128X1S => RAM128X1S (MUXF7, RAMS64E, RAMS64E): 8 instances RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 4 instances -link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 548.047 ; gain = 269.277 +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 547.402 ; gain = 269.234 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a15t-ftg256' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a15t-ftg256' @@ -50,7 +50,7 @@ report_drc (run_mandatory_drcs) completed successfully INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.639 . Memory (MB): peak = 555.684 ; gain = 7.637 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.629 . Memory (MB): peak = 556.043 ; gain = 8.641 WARNING: [Constraints 18-96] Setting input delay on a clock pin 'hi_in[0]' is not supported, ignoring it [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc:62] WARNING: [Constraints 18-96] Setting input delay on a clock pin 'hi_in[0]' is not supported, ignoring it [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc:63] INFO: [Timing 38-35] Done setting XDC timing constraints. @@ -61,42 +61,42 @@ Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 1a82c521a +Phase 1 Retarget | Checksum: 1845d7467 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.158 . Memory (MB): peak = 1046.324 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 2 cells and removed 66 cells +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 1045.680 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 2 cells and removed 67 cells Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 1aaed84c9 +Phase 2 Constant propagation | Checksum: 177ed596e -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.257 . Memory (MB): peak = 1046.324 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.254 . Memory (MB): peak = 1045.680 ; gain = 0.000 INFO: [Opt 31-389] Phase Constant propagation created 76 cells and removed 77 cells Phase 3 Sweep -Phase 3 Sweep | Checksum: 266f4e701 +Phase 3 Sweep | Checksum: e32de73f -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.327 . Memory (MB): peak = 1046.324 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.322 . Memory (MB): peak = 1045.680 ; gain = 0.000 INFO: [Opt 31-389] Phase Sweep created 11 cells and removed 0 cells Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: 266f4e701 +Phase 4 BUFG optimization | Checksum: e32de73f -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.397 . Memory (MB): peak = 1046.324 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.391 . Memory (MB): peak = 1045.680 ; gain = 0.000 INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 266f4e701 +Phase 5 Shift Register Optimization | Checksum: e32de73f -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.404 . Memory (MB): peak = 1046.324 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.399 . Memory (MB): peak = 1045.680 ; gain = 0.000 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1046.324 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 266f4e701 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1045.680 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: e32de73f -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.423 . Memory (MB): peak = 1046.324 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.416 . Memory (MB): peak = 1045.680 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. @@ -117,20 +117,20 @@ INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 18 newly gated: 0 Total Ports: 38 Number of Flops added for Enable Generation: 3 -Ending PowerOpt Patch Enables Task | Checksum: 1ad897823 +Ending PowerOpt Patch Enables Task | Checksum: 260b35149 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Ending Power Optimization Task | Checksum: 1ad897823 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Ending Power Optimization Task | Checksum: 260b35149 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1247.527 ; gain = 201.203 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1247.879 ; gain = 202.199 28 Infos, 14 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1247.527 ; gain = 699.480 +opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 1247.879 ; gain = 700.477 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1247.879 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_opt.dcp' has been generated. Command: report_drc -file OSC1_LITE_Control_drc_opted.rpt INFO: [DRC 23-27] Running DRC with 2 threads @@ -181,86 +181,86 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 161fcd502 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 18b9a3b4a -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1247.879 ; gain = 0.000 WARNING: [Constraints 18-96] Setting input delay on a clock pin 'hi_in[0]' is not supported, ignoring it [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc:62] WARNING: [Constraints 18-96] Setting input delay on a clock pin 'hi_in[0]' is not supported, ignoring it [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc:63] INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Constraints 18-96] Setting input delay on a clock pin 'hi_in[0]' is not supported, ignoring it [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc:62] WARNING: [Constraints 18-96] Setting input delay on a clock pin 'hi_in[0]' is not supported, ignoring it [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc:63] INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 16e8bdae +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 9f21476c -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 7a13381b +Phase 1.3 Build Placer Netlist Model | Checksum: dd897aae -Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 7a13381b +Phase 1.4 Constrain Clocks/Macros | Checksum: dd897aae -Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 7a13381b +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: dd897aae -Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 2 Global Placement -Phase 2 Global Placement | Checksum: 1575c98f9 +Phase 2 Global Placement | Checksum: 161ea7302 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1575c98f9 +Phase 3.1 Commit Multi Column Macros | Checksum: 161ea7302 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 14ca29543 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d299fe5f -Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 14364e2bb +Phase 3.3 Area Swap Optimization | Checksum: 1c065a22a -Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 14364e2bb +Phase 3.4 Pipeline Register Optimization | Checksum: 1c065a22a -Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3.5 Timing Path Optimizer -Phase 3.5 Timing Path Optimizer | Checksum: 138095cda +Phase 3.5 Timing Path Optimizer | Checksum: 17e484897 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3.6 Small Shape Detail Placement -Phase 3.6 Small Shape Detail Placement | Checksum: 142dc307f +Phase 3.6 Small Shape Detail Placement | Checksum: 1150f4aff -Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3.7 Re-assign LUT pins -Phase 3.7 Re-assign LUT pins | Checksum: 20c5de9e4 +Phase 3.7 Re-assign LUT pins | Checksum: 14525aa86 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3.8 Pipeline Register Optimization -Phase 3.8 Pipeline Register Optimization | Checksum: 20c5de9e4 +Phase 3.8 Pipeline Register Optimization | Checksum: 14525aa86 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 20c5de9e4 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 14525aa86 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up @@ -270,54 +270,54 @@ WARNING: [Constraints 18-96] Setting input delay on a clock pin 'hi_in[0]' is no INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 214a915e2 +Post Placement Optimization Initialization | Checksum: 11c17ef76 Phase 4.1.1.1 BUFG Insertion INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs INFO: [Place 46-41] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason. -Phase 4.1.1.1 BUFG Insertion | Checksum: 214a915e2 +Phase 4.1.1.1 BUFG Insertion | Checksum: 11c17ef76 -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=6.488. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 1f6251c1c +Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.879 ; gain = 0.000 +INFO: [Place 30-746] Post Placement Timing Summary WNS=6.539. For the most accurate timing information please run report_timing. +Phase 4.1.1 Post Placement Optimization | Checksum: 11c5cb6bd -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 1f6251c1c +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 4.1 Post Commit Optimization | Checksum: 11c5cb6bd -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 1f6251c1c +Phase 4.2 Post Placement Cleanup | Checksum: 11c5cb6bd -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 1f6251c1c +Phase 4.3 Placer Reporting | Checksum: 11c5cb6bd -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 4.4 Final Placement Cleanup -Phase 4.4 Final Placement Cleanup | Checksum: 1ee1ec375 +Phase 4.4 Final Placement Cleanup | Checksum: 1c5593bbf -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ee1ec375 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c5593bbf -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Ending Placer Task | Checksum: 1e0381668 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Ending Placer Task | Checksum: 14ec85742 -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 47 Infos, 41 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 1247.527 ; gain = 0.000 +place_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.219 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.222 . Memory (MB): peak = 1247.879 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_placed.dcp' has been generated. -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 1247.527 ; gain = 0.000 -report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1247.527 ; gain = 0.000 -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1247.527 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 1247.879 ; gain = 0.000 +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1247.879 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1247.879 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a15t-ftg256' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a15t-ftg256' @@ -331,106 +331,106 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: f7cfd457 ConstDB: 0 ShapeSum: e8684211 RouteDB: 0 +Checksum: PlaceDB: 610971b1 ConstDB: 0 ShapeSum: edbee591 RouteDB: 0 Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: ce9f5ced +Phase 1 Build RT Design | Checksum: cf2ab54c -Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 2 Router Initialization Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: ce9f5ced +Phase 2.1 Create Timer | Checksum: cf2ab54c -Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: ce9f5ced +Phase 2.2 Fix Topology Constraints | Checksum: cf2ab54c -Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: ce9f5ced +Phase 2.3 Pre Route Cleanup | Checksum: cf2ab54c -Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.879 ; gain = 0.000 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 24b10bc53 +Phase 2.4 Update Timing | Checksum: 14230ddb3 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 1247.527 ; gain = 0.000 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.428 | TNS=0.000 | WHS=-0.301 | THS=-40.864| +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1247.879 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.825 | TNS=0.000 | WHS=-0.268 | THS=-32.833| -Phase 2 Router Initialization | Checksum: 209af61fd +Phase 2 Router Initialization | Checksum: 1ee0c9a73 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 1a29fc651 +Phase 3 Initial Routing | Checksum: c324d9b7 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 270 - Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 294 + Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.044 | TNS=0.000 | WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.824 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 4.1 Global Iteration 0 | Checksum: 227ecdcf0 +Phase 4.1 Global Iteration 0 | Checksum: 14f66a31b -Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:21 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.044 | TNS=0.000 | WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.824 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 4.2 Global Iteration 1 | Checksum: 1b6d530ce +Phase 4.2 Global Iteration 1 | Checksum: 11a732228 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 4 Rip-up And Reroute | Checksum: 1b6d530ce +Time (s): cpu = 00:00:21 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 4 Rip-up And Reroute | Checksum: 11a732228 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:21 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 1b6d530ce +Phase 5.1 Delay CleanUp | Checksum: 11a732228 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:21 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 1b6d530ce +Phase 5.2 Clock Skew Optimization | Checksum: 11a732228 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 5 Delay and Skew Optimization | Checksum: 1b6d530ce +Time (s): cpu = 00:00:21 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 5 Delay and Skew Optimization | Checksum: 11a732228 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:21 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: ffd9e20b +Phase 6.1.1 Update Timing | Checksum: a1403f47 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.044 | TNS=0.000 | WHS=0.054 | THS=0.000 | +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.824 | TNS=0.000 | WHS=0.106 | THS=0.000 | -Phase 6.1 Hold Fix Iter | Checksum: e8854e5f +Phase 6.1 Hold Fix Iter | Checksum: 115dda551 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 6 Post Hold Fix | Checksum: e8854e5f +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 6 Post Hold Fix | Checksum: 115dda551 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 0.865742 % - Global Horizontal Routing Utilization = 1.01171 % + Global Vertical Routing Utilization = 0.838795 % + Global Horizontal Routing Utilization = 0.989198 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -439,42 +439,42 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 7 Route finalize | Checksum: 10818e42a +Phase 7 Route finalize | Checksum: f00684ef -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 10818e42a +Phase 8 Verifying routed nets | Checksum: f00684ef -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 9083587e +Phase 9 Depositing Routes | Checksum: 188d5b631 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=6.044 | TNS=0.000 | WHS=0.054 | THS=0.000 | +INFO: [Route 35-57] Estimated Timing Summary | WNS=6.824 | TNS=0.000 | WHS=0.106 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 9083587e +Phase 10 Post Router Timing | Checksum: 188d5b631 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 INFO: [Route 35-16] Router Completed Successfully -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 Routing Is Done. 60 Infos, 41 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 1247.527 ; gain = 0.000 +route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 1247.879 ; gain = 0.000 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.290 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.296 . Memory (MB): peak = 1247.879 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_routed.dcp' has been generated. Command: report_drc -file OSC1_LITE_Control_drc_routed.rpt -pb OSC1_LITE_Control_drc_routed.pb -rpx OSC1_LITE_Control_drc_routed.rpx INFO: [DRC 23-27] Running DRC with 2 threads @@ -546,12 +546,12 @@ Loading route data... Processing options... Creating bitmap... Creating bitstream... -Bitstream compression saved 11789856 bits. +Bitstream compression saved 12204480 bits. Writing bitstream ./OSC1_LITE_Control.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). -INFO: [Common 17-186] 'C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Feb 26 23:50:00 2019. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. +INFO: [Common 17-186] 'C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 19 19:00:48 2019. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 79 Infos, 67 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 1542.754 ; gain = 295.227 -INFO: [Common 17-206] Exiting Vivado at Tue Feb 26 23:50:00 2019... +write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1552.297 ; gain = 304.418 +INFO: [Common 17-206] Exiting Vivado at Tue Mar 19 19:00:48 2019... diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_clock_utilization_routed.rpt b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_clock_utilization_routed.rpt index a68f283..b173722 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_clock_utilization_routed.rpt +++ b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_clock_utilization_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -| Date : Tue Feb 26 23:49:46 2019 +| Date : Tue Mar 19 19:00:33 2019 | Host : EECS-TOYODA running 64-bit major release (build 9200) | Command : report_clock_utilization -file OSC1_LITE_Control_clock_utilization_routed.rpt | Design : OSC1_LITE_Control @@ -69,8 +69,8 @@ Table of Contents +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+---------------------------------------------+-----------------------------+ | src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X0Y0 | X0Y0 | 1 | 0 | 20.830 | mmcm0_clk0 | okHI/mmcm0/CLKOUT0 | okHI/mmcm0_clk0 | | src0 | g4 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X0Y0 | X0Y0 | 1 | 0 | 20.830 | mmcm0_clkfb | okHI/mmcm0/CLKFBOUT | okHI/mmcm0_clkfb | -| src1 | g1 | LUT6/O | None | SLICE_X36Y44 | X1Y0 | 1 | 0 | | | sclk_OBUF_BUFG[0]_inst_i_1/O | sclk_OBUF[0] | -| src2 | g2 | LUT5/O | None | SLICE_X36Y44 | X1Y0 | 1 | 0 | | | dac_spi0[0]/spi_pipe_clk_BUFG[0]_inst_i_1/O | dac_spi0[0]/spi_pipe_clk[0] | +| src1 | g1 | LUT6/O | None | SLICE_X36Y45 | X1Y0 | 1 | 0 | | | sclk_OBUF_BUFG[0]_inst_i_1/O | sclk_OBUF[0] | +| src2 | g2 | LUT5/O | None | SLICE_X36Y45 | X1Y0 | 1 | 0 | | | dac_spi0[0]/spi_pipe_clk_BUFG[0]_inst_i_1/O | dac_spi0[0]/spi_pipe_clk[0] | | src3 | g3 | IBUF/O | IOB_X0Y26 | IOB_X0Y26 | X0Y0 | 1 | 1 | | | clk_IBUF_inst/O | clk_IBUF | +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+---------------------------------------------+-----------------------------+ * Clock Loads column represents the clock pin loads (pin count) @@ -83,7 +83,7 @@ Table of Contents +----------+-----------------+------------+-------------------+--------------+-------------+-----------------+--------------+-------+-------------------------------------------------------------------+----------------------------------------------------------+ | Local Id | Driver Type/Pin | Constraint | Site/BEL | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +----------+-----------------+------------+-------------------+--------------+-------------+-----------------+--------------+-------+-------------------------------------------------------------------+----------------------------------------------------------+ -| 0 | FDPE/Q | None | SLICE_X29Y35/B5FF | X0Y0 | 1 | 3 | | | okHI/core0/core0/a0/d0/lc4da648cb12eeeb24e4d199c1195ed93_reg[4]/Q | okHI/core0/core0/a0/d0/l380f95c05ffaf9f64e84defb5d30e949 | +| 0 | FDPE/Q | None | SLICE_X29Y36/B5FF | X0Y0 | 1 | 3 | | | okHI/core0/core0/a0/d0/lc4da648cb12eeeb24e4d199c1195ed93_reg[4]/Q | okHI/core0/core0/a0/d0/l380f95c05ffaf9f64e84defb5d30e949 | +----------+-----------------+------------+-------------------+--------------+-------------+-----------------+--------------+-------+-------------------------------------------------------------------+----------------------------------------------------------+ * Local Clocks in this context represents only clocks driven by non-global buffers ** Clock Loads column represents the clock pin loads (pin count) @@ -98,9 +98,9 @@ Table of Contents +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -| X0Y0 | 5 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 16 | 50 | 32 | 50 | 1051 | 1200 | 400 | 400 | 1 | 20 | 8 | 10 | 0 | 20 | -| X1Y0 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1 | 1500 | 0 | 450 | 0 | 40 | 8 | 20 | 0 | 20 | -| X0Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 139 | 1200 | 61 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X0Y0 | 5 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 16 | 50 | 32 | 50 | 1156 | 1200 | 426 | 400 | 1 | 20 | 4 | 10 | 0 | 20 | +| X1Y0 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 27 | 1500 | 2 | 450 | 0 | 40 | 12 | 20 | 0 | 20 | +| X0Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 8 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | | X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | @@ -134,13 +134,13 @@ Table of Contents **** GT Loads column represents load cell count of GT types -+----+------+----+ -| | X0 | X1 | -+----+------+----+ -| Y2 | 0 | 0 | -| Y1 | 139 | 0 | -| Y0 | 939 | 8 | -+----+------+----+ ++----+-------+-----+ +| | X0 | X1 | ++----+-------+-----+ +| Y2 | 0 | 0 | +| Y1 | 8 | 0 | +| Y0 | 1049 | 29 | ++----+-------+-----+ 8. Device Cell Placement Summary for Global Clock g1 @@ -161,8 +161,8 @@ Table of Contents | | X0 | X1 | +----+-----+----+ | Y2 | 0 | 0 | -| Y1 | 7 | 4 | -| Y0 | 72 | 1 | +| Y1 | 7 | 1 | +| Y0 | 73 | 3 | +----+-----+----+ @@ -180,13 +180,13 @@ Table of Contents **** GT Loads column represents load cell count of GT types -+----+-----+----+ -| | X0 | X1 | -+----+-----+----+ -| Y2 | 0 | 0 | -| Y1 | 0 | 0 | -| Y0 | 54 | 8 | -+----+-----+----+ ++----+-----+-----+ +| | X0 | X1 | ++----+-----+-----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 39 | 23 | ++----+-----+-----+ 10. Device Cell Placement Summary for Global Clock g3 @@ -238,15 +238,15 @@ Table of Contents 12. Clock Region Cell Placement per Global Clock: Region X0Y0 ------------------------------------------------------------- -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-----------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-----------------------+ -| g0 | n/a | BUFG/O | None | 939 | 0 | 928 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | okHI/ti_clk | -| g1 | n/a | BUFG/O | None | 71 | 1 | 71 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sclk_OBUF_BUFG[0] | -| g2 | n/a | BUFG/O | None | 54 | 0 | 45 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | spi_pipe_clk_BUFG[0] | -| g3 | n/a | BUFG/O | None | 7 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | -| g4 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | okHI/mmcm0_clkfb_bufg | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-----------------------+ ++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------+ +| g0 | n/a | BUFG/O | None | 1049 | 0 | 1043 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | okHI/ti_clk | +| g1 | n/a | BUFG/O | None | 71 | 2 | 71 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sclk_OBUF_BUFG[0] | +| g2 | n/a | BUFG/O | None | 39 | 0 | 35 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | spi_pipe_clk_BUFG[0] | +| g3 | n/a | BUFG/O | None | 7 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | +| g4 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | okHI/mmcm0_clkfb_bufg | ++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts @@ -258,9 +258,9 @@ Table of Contents +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------+ -| g0 | n/a | BUFG/O | None | 8 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | okHI/ti_clk | -| g1 | n/a | BUFG/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sclk_OBUF_BUFG[0] | -| g2 | n/a | BUFG/O | None | 8 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | spi_pipe_clk_BUFG[0] | +| g0 | n/a | BUFG/O | None | 29 | 0 | 16 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | okHI/ti_clk | +| g1 | n/a | BUFG/O | None | 1 | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sclk_OBUF_BUFG[0] | +| g2 | n/a | BUFG/O | None | 23 | 0 | 10 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | spi_pipe_clk_BUFG[0] | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) @@ -270,12 +270,12 @@ Table of Contents 14. Clock Region Cell Placement per Global Clock: Region X0Y1 ------------------------------------------------------------- -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 139 | 0 | 139 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | okHI/ti_clk | -| g1 | n/a | BUFG/O | None | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sclk_OBUF_BUFG[0] | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------+ ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ +| g0 | n/a | BUFG/O | None | 8 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | okHI/ti_clk | +| g1 | n/a | BUFG/O | None | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sclk_OBUF_BUFG[0] | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts @@ -287,7 +287,7 @@ Table of Contents +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ -| g1 | n/a | BUFG/O | None | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sclk_OBUF_BUFG[0] | +| g1 | n/a | BUFG/O | None | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sclk_OBUF_BUFG[0] | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) @@ -303,18 +303,18 @@ set_property LOC BUFGCTRL_X0Y4 [get_cells okHI/mmcm0fb_bufg] set_property LOC BUFGCTRL_X0Y3 [get_cells clk_IBUF_BUFG_inst] # Location of IO Primitives which is load of clock spine -set_property LOC IOB_X0Y2 [get_cells sclk_OBUF[9]_inst] -set_property LOC IOB_X1Y60 [get_cells sclk_OBUF[8]_inst] -set_property LOC IOB_X1Y70 [get_cells sclk_OBUF[7]_inst] -set_property LOC IOB_X1Y84 [get_cells sclk_OBUF[6]_inst] -set_property LOC IOB_X0Y97 [get_cells sclk_OBUF[5]_inst] -set_property LOC IOB_X0Y95 [get_cells sclk_OBUF[4]_inst] -set_property LOC IOB_X0Y70 [get_cells sclk_OBUF[3]_inst] -set_property LOC IOB_X0Y58 [get_cells sclk_OBUF[2]_inst] -set_property LOC IOB_X0Y86 [get_cells sclk_OBUF[1]_inst] -set_property LOC IOB_X0Y51 [get_cells sclk_OBUF[11]_inst] -set_property LOC IOB_X1Y76 [get_cells sclk_OBUF[10]_inst] -set_property LOC IOB_X0Y85 [get_cells sclk_OBUF[0]_inst] +set_property LOC IOB_X0Y70 [get_cells sclk_OBUF[9]_inst] +set_property LOC IOB_X0Y58 [get_cells sclk_OBUF[8]_inst] +set_property LOC IOB_X0Y51 [get_cells sclk_OBUF[7]_inst] +set_property LOC IOB_X0Y9 [get_cells sclk_OBUF[6]_inst] +set_property LOC IOB_X1Y75 [get_cells sclk_OBUF[5]_inst] +set_property LOC IOB_X0Y90 [get_cells sclk_OBUF[4]_inst] +set_property LOC IOB_X0Y84 [get_cells sclk_OBUF[3]_inst] +set_property LOC IOB_X1Y33 [get_cells sclk_OBUF[2]_inst] +set_property LOC IOB_X1Y32 [get_cells sclk_OBUF[1]_inst] +set_property LOC IOB_X0Y97 [get_cells sclk_OBUF[11]_inst] +set_property LOC IOB_X0Y85 [get_cells sclk_OBUF[10]_inst] +set_property LOC IOB_X0Y3 [get_cells sclk_OBUF[0]_inst] # Location of clock ports set_property LOC IOB_X0Y26 [get_ports clk] diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_control_sets_placed.rpt b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_control_sets_placed.rpt index 0f7c301..f1f63bc 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_control_sets_placed.rpt +++ b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_control_sets_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -| Date : Tue Feb 26 23:49:22 2019 +| Date : Tue Mar 19 19:00:08 2019 | Host : EECS-TOYODA running 64-bit major release (build 9200) | Command : report_control_sets -verbose -file OSC1_LITE_Control_control_sets_placed.rpt | Design : OSC1_LITE_Control @@ -33,12 +33,12 @@ Table of Contents +--------------+-----------------------+------------------------+-----------------+--------------+ | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | +--------------+-----------------------+------------------------+-----------------+--------------+ -| No | No | No | 163 | 62 | +| No | No | No | 163 | 63 | | No | No | Yes | 35 | 16 | -| No | Yes | No | 110 | 49 | -| Yes | No | No | 110 | 41 | -| Yes | No | Yes | 144 | 34 | -| Yes | Yes | No | 581 | 190 | +| No | Yes | No | 110 | 51 | +| Yes | No | No | 110 | 40 | +| Yes | No | Yes | 144 | 39 | +| Yes | Yes | No | 581 | 189 | +--------------+-----------------------+------------------------+-----------------+--------------+ @@ -48,84 +48,84 @@ Table of Contents +-----------------------+------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------------+----------------+ | Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | +-----------------------+------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------------+----------------+ -| ~sclk_OBUF_BUFG[0] | | dac_spi0[1]/latch_i_1__4_n_0 | 1 | 1 | -| ~sclk_OBUF_BUFG[0] | | dac_spi0[5]/latch_i_1__10_n_0 | 1 | 1 | -| ~sclk_OBUF_BUFG[0] | | dac_spi0[6]/latch_i_1__0_n_0 | 1 | 1 | +| ~sclk_OBUF_BUFG[0] | | dac_spi0[2]/latch_i_1__2_n_0 | 1 | 1 | +| ~sclk_OBUF_BUFG[0] | | dac_spi0[6]/latch_i_1_n_0 | 1 | 1 | | ~sclk_OBUF_BUFG[0] | | dac_spi0[7]/latch_i_1__9_n_0 | 1 | 1 | | ~sclk_OBUF_BUFG[0] | | dac_spi0[8]/latch_i_1__8_n_0 | 1 | 1 | -| ~sclk_OBUF_BUFG[0] | | dac_spi0[0]/latch_i_1__5_n_0 | 1 | 1 | -| ~sclk_OBUF_BUFG[0] | | dac_spi0[10]/latch_i_1__7_n_0 | 1 | 1 | -| ~sclk_OBUF_BUFG[0] | | dac_spi0[11]/latch_i_1__6_n_0 | 1 | 1 | -| ~sclk_OBUF_BUFG[0] | | dac_spi0[9]/latch_i_1_n_0 | 1 | 1 | -| okHI/ti_clk | wi02/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 1 | 1 | -| ~sclk_OBUF_BUFG[0] | | dac_spi0[2]/latch_i_1__3_n_0 | 1 | 1 | -| ~sclk_OBUF_BUFG[0] | | dac_spi0[3]/latch_i_1__2_n_0 | 1 | 1 | +| ~sclk_OBUF_BUFG[0] | | dac_spi0[0]/latch_i_1__4_n_0 | 1 | 1 | +| ~sclk_OBUF_BUFG[0] | | dac_spi0[10]/latch_i_1__6_n_0 | 1 | 1 | +| ~sclk_OBUF_BUFG[0] | | dac_spi0[11]/latch_i_1__5_n_0 | 1 | 1 | +| ~sclk_OBUF_BUFG[0] | | dac_spi0[9]/latch_i_1__7_n_0 | 1 | 1 | +| ~sclk_OBUF_BUFG[0] | | dac_spi0[1]/latch_i_1__3_n_0 | 1 | 1 | +| ~sclk_OBUF_BUFG[0] | | dac_spi0[3]/latch_i_1__10_n_0 | 1 | 1 | | ~sclk_OBUF_BUFG[0] | | dac_spi0[4]/latch_i_1__1_n_0 | 1 | 1 | +| ~sclk_OBUF_BUFG[0] | | dac_spi0[5]/latch_i_1__0_n_0 | 1 | 1 | +| okHI/ti_clk | | okHI/core0/core0/a0/cb0/U0/ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1_n_0 | 1 | 1 | +| okHI/ti_clk | wi02/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 1 | 1 | | okHI/ti_clk | | okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_rd_reg2 | 1 | 1 | | okHI/ti_clk | | okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_wr_reg2 | 1 | 1 | -| okHI/ti_clk | | okHI/core0/core0/a0/cb0/U0/ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1_n_0 | 1 | 1 | -| okHI/ti_clk | okHI/core0/core0/a0/pc0/CE | okHI/core0/core0/a0/pc0/R | 2 | 2 | | okHI/ti_clk | | okHI/core0/core0/a0/cb0/U0/RD_RST | 1 | 2 | +| okHI/ti_clk | okHI/core0/core0/a0/pc0/CE | okHI/core0/core0/a0/pc0/R | 1 | 2 | | okHI/ti_clk | | okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_d2 | 1 | 2 | | okHI/ti_clk | | okHI/core0/core0/a0/cb0/U0/ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 | 1 | 2 | | okHI/ti_clk | wi01/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 1 | 3 | -| okHI/ti_clk | wi17/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 1 | 3 | | okHI/ti_clk | | okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 | 2 | 3 | +| okHI/ti_clk | wi17/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 1 | 3 | +| okHI/ti_clk | okHI/core0/core0/FSM_sequential_l8ff940a6bfc33211f22a7ff95e39fe60[3]_i_1_n_0 | | 1 | 4 | | okHI/ti_clk | okHI/core0/core0/a0/l90ce46b343647bab4d280b5afc506219 | okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 | 1 | 4 | | okHI/ti_clk | okHI/core0/core0/l885bbeb94996347da66a8546671e4990[19]_i_1_n_0 | | 1 | 4 | -| okHI/ti_clk | okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_2_n_0 | okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1_n_0 | 1 | 4 | +| okHI/ti_clk | okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[3]_i_1_n_0 | | 2 | 4 | | okHI/ti_clk | | okHI/core0/core0/ld307737e57d50d07f937891de086bf8e_i_1_n_0 | 1 | 4 | -| okHI/ti_clk | okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[3]_i_1_n_0 | | 1 | 4 | -| okHI/ti_clk | okHI/core0/core0/FSM_sequential_l8ff940a6bfc33211f22a7ff95e39fe60[3]_i_1_n_0 | | 2 | 4 | -| okHI/ti_clk | okHI/core0/core0/FSM_sequential_l6d7b501652de6ba8ba55082874707b2a[4]_i_1_n_0 | okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 | 3 | 5 | -| okHI/ti_clk | okHI/core0/core0/a0/d0/lfd4ae1d2a2f83cc540ba2af5c1891381 | okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 | 1 | 6 | +| okHI/ti_clk | okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_2_n_0 | okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1_n_0 | 1 | 4 | +| okHI/ti_clk | okHI/core0/core0/FSM_sequential_l6d7b501652de6ba8ba55082874707b2a[4]_i_1_n_0 | okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 | 4 | 5 | +| okHI/ti_clk | okHI/core0/core0/a0/d0/lfd4ae1d2a2f83cc540ba2af5c1891381 | okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 | 2 | 6 | | okHI/ti_clk | | okHI/core0/core0/a0/pc0/R | 3 | 6 | | clk_IBUF_BUFG | | wi00/ep_dataout[0] | 2 | 7 | -| okHI/ti_clk | okHI/core0/core0/l92ae5a5037b0cc87c9562f3e505d14cf[6]_i_1_n_0 | | 3 | 7 | | okHI/ti_clk | | okHI/core0/core0/a0/l62a5479e7989ce7f4d5507c695cc69cf | 2 | 7 | -| okHI/ti_clk | okHI/core0/core0/l885bbeb94996347da66a8546671e4990[15]_i_1_n_0 | | 1 | 8 | -| okHI/ti_clk | okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157[7]_i_1_n_0 | | 4 | 8 | -| okHI/ti_clk | | okHI/core0/core0/a0/l770e51175fa898662b06f9e3b71c7bff[7] | 2 | 8 | +| okHI/ti_clk | okHI/core0/core0/l92ae5a5037b0cc87c9562f3e505d14cf[6]_i_1_n_0 | | 3 | 7 | +| okHI/ti_clk | | okHI/core0/core0/a0/l770e51175fa898662b06f9e3b71c7bff[7] | 3 | 8 | | okHI/ti_clk | okHI/core0/core0/lbe59f904be1e8440c2d6333521aaa29a[7]_i_1_n_0 | | 3 | 8 | -| okHI/ti_clk | okHI/core0/core0/a0/l37dbd1aafb403530c46407234a8f7286 | | 1 | 8 | +| okHI/ti_clk | okHI/core0/core0/l885bbeb94996347da66a8546671e4990[15]_i_1_n_0 | | 2 | 8 | +| okHI/ti_clk | okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157[7]_i_1_n_0 | | 3 | 8 | | okHI/ti_clk | okHI/core0/core0/l885bbeb94996347da66a8546671e4990[7]_i_1_n_0 | | 1 | 8 | +| okHI/ti_clk | okHI/core0/core0/a0/l37dbd1aafb403530c46407234a8f7286 | | 1 | 8 | | okHI/ti_clk | okHI/core0/core0/l18905be285ee66e0e6fb566993b0399b | okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 | 5 | 11 | | okHI/ti_clk | okHI/core0/core0/le4c4532ac06490aa5cc2f8d669975cdc[10]_i_1_n_0 | | 4 | 11 | -| okHI/ti_clk | okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/p_7_out | okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rd_rst_i | 3 | 12 | +| okHI/ti_clk | okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_into_logic | okHI/core0/core0/a0/cb0/U0/wr_rst_reg | 3 | 12 | | okHI/ti_clk | okHI/core0/core0/a0/pc0/I3 | okHI/core0/core0/a0/pc0/R | 3 | 12 | -| okHI/ti_clk | okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_into_logic | okHI/core0/core0/a0/cb0/U0/wr_rst_reg | 2 | 12 | +| okHI/ti_clk | okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/p_7_out | okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rd_rst_i | 3 | 12 | | spi_pipe_clk_BUFG[0] | | | 5 | 13 | -| okHI/ti_clk | | okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 | 7 | 13 | -| okHI/ti_clk | wi00/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 7 | 13 | -| spi_pipe_clk_BUFG[0] | | my_amp_pipe/read_counter[15]_i_1_n_0 | 4 | 16 | +| okHI/ti_clk | | okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 | 6 | 13 | +| okHI/ti_clk | wi00/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 5 | 13 | +| spi_pipe_clk_BUFG[0] | | my_amp_pipe/read_counter[15]_i_1_n_0 | 3 | 16 | | spi_pipe_clk_BUFG[0] | my_amp_pipe/next_complete_pulse_counter | my_amp_pipe/complete_pulse_counter | 3 | 16 | -| okHI/ti_clk | okHI/core0/core0/a0/pc0/WE | | 2 | 16 | | okHI/ti_clk | my_amp_pipe/write_counter[0]_i_2_n_0 | my_amp_pipe/write_counter[0]_i_1_n_0 | 4 | 16 | -| okHI/ti_clk | wi07/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 3 | 16 | -| okHI/ti_clk | wi08/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 2 | 16 | +| okHI/ti_clk | wi08/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 4 | 16 | +| okHI/ti_clk | wi0a/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 3 | 16 | +| okHI/ti_clk | pi80/ep_dataout[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 6 | 16 | +| okHI/ti_clk | wi15/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 4 | 16 | +| okHI/ti_clk | wi09/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 4 | 16 | | okHI/ti_clk | okHI/core0/core0/a0/pc0/I3 | | 2 | 16 | +| okHI/ti_clk | wi0e/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 5 | 16 | +| okHI/ti_clk | okHI/core0/core0/a0/pc0/WE | | 2 | 16 | | okHI/ti_clk | okHI/core0/core0/a0/pc0/spm_enable_flop_n_0 | | 4 | 16 | -| okHI/ti_clk | wi09/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 2 | 16 | -| okHI/ti_clk | wi0a/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 3 | 16 | +| okHI/ti_clk | wi0d/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 6 | 16 | +| okHI/ti_clk | wi16/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 6 | 16 | +| okHI/ti_clk | wi07/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 3 | 16 | +| okHI/ti_clk | wi05/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 4 | 16 | +| okHI/ti_clk | wi06/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 3 | 16 | +| okHI/ti_clk | okHI/core0/core0/lab8c81cec3709c0416d0acf79f37f087[15]_i_1_n_0 | | 6 | 16 | +| okHI/ti_clk | wi04/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 4 | 16 | +| okHI/ti_clk | wi03/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 5 | 16 | +| okHI/ti_clk | wi0c/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 3 | 16 | | okHI/ti_clk | wi0b/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 4 | 16 | -| okHI/ti_clk | wi0c/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 5 | 16 | -| okHI/ti_clk | wi0d/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 3 | 16 | -| okHI/ti_clk | wi0e/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 3 | 16 | -| okHI/ti_clk | wi15/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 5 | 16 | -| okHI/ti_clk | wi16/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 8 | 16 | -| okHI/ti_clk | wi04/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 5 | 16 | -| okHI/ti_clk | wi05/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 3 | 16 | -| okHI/ti_clk | wi06/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 5 | 16 | -| okHI/ti_clk | okHI/core0/core0/lab8c81cec3709c0416d0acf79f37f087[15]_i_1_n_0 | | 7 | 16 | -| okHI/ti_clk | wi03/ep_datahold[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 2 | 16 | -| okHI/ti_clk | pi80/ep_dataout[15]_i_1_n_0 | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 5 | 16 | -| okHI/ti_clk | okHI/core0/core0/l4f8cd1ab062f5571ff66db47e3d281bf[19]_i_1_n_0 | okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 | 5 | 21 | +| okHI/ti_clk | okHI/core0/core0/l4f8cd1ab062f5571ff66db47e3d281bf[19]_i_1_n_0 | okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 | 6 | 21 | | okHI/ti_clk | okHI/core0/core0/l84a7b0e1b51dfdd46f041d49e77ce017[23]_i_1_n_0 | | 13 | 24 | | okHI/ti_clk | okHI/core0/core0/l0c94b19b36beba84283b1c1a65aa73f3[0]_i_1_n_0 | okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 | 8 | 32 | -| okHI/ti_clk | okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30 | okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 | 14 | 57 | -| ~sclk_OBUF_BUFG[0] | | wi00/ep_dataout[0] | 24 | 60 | -| okHI/ti_clk | | | 57 | 150 | -| okHI/ti_clk | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[28] | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 101 | 255 | +| okHI/ti_clk | okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30 | okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 | 16 | 57 | +| ~sclk_OBUF_BUFG[0] | | wi00/ep_dataout[0] | 27 | 60 | +| okHI/ti_clk | | | 58 | 150 | +| okHI/ti_clk | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[28] | okHI/core0/core0/lfc9af733ef9b7e7ec2ccb35c062a12d3[25] | 96 | 255 | +-----------------------+------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------------+----------------+ diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_drc_opted.rpt b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_drc_opted.rpt index fb2dffb..e098a2e 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_drc_opted.rpt +++ b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_drc_opted.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -| Date : Tue Feb 26 23:49:14 2019 +| Date : Tue Mar 19 19:00:01 2019 | Host : EECS-TOYODA running 64-bit major release (build 9200) | Command : report_drc -file OSC1_LITE_Control_drc_opted.rpt | Design : OSC1_LITE_Control diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_drc_routed.rpt b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_drc_routed.rpt index 716f6bf..7a61bee 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_drc_routed.rpt +++ b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -| Date : Tue Feb 26 23:49:43 2019 +| Date : Tue Mar 19 19:00:29 2019 | Host : EECS-TOYODA running 64-bit major release (build 9200) | Command : report_drc -file OSC1_LITE_Control_drc_routed.rpt -pb OSC1_LITE_Control_drc_routed.pb -rpx OSC1_LITE_Control_drc_routed.rpx | Design : OSC1_LITE_Control diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_drc_routed.rpx b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_drc_routed.rpx index 8ba13ac..b978815 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_drc_routed.rpx and b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_drc_routed.rpx differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_io_placed.rpt b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_io_placed.rpt index e6a1d09..b70146a 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_io_placed.rpt +++ b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_io_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -| Date : Tue Feb 26 23:49:22 2019 +| Date : Tue Mar 19 19:00:08 2019 | Host : EECS-TOYODA running 64-bit major release (build 9200) | Command : report_io -file OSC1_LITE_Control_io_placed.rpt | Design : OSC1_LITE_Control @@ -25,7 +25,7 @@ Table of Contents +---------------+ | Total User IO | +---------------+ -| 98 | +| 97 | +---------------+ @@ -36,71 +36,71 @@ Table of Contents | Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | +------------+--------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+ | A1 | | | GND | GND | | | | | | | 0.0 | | | | | | -| A2 | din[10] | High Range | IO_L8N_T1_AD14N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| A3 | din[6] | High Range | IO_L4N_T0_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| A2 | latch[4] | High Range | IO_L8N_T1_AD14N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| A3 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | A4 | led[7] | High Range | IO_L3N_T0_DQS_AD5N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | A5 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | A6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | A7 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | -| A8 | sdo_bit[4] | High Range | IO_L2P_T0_AD8P_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | -| A9 | sclk[4] | High Range | IO_L2N_T0_AD8N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| A10 | din[5] | High Range | IO_L3N_T0_DQS_AD1N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| A8 | sdo_bit[5] | High Range | IO_L2P_T0_AD8P_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | +| A9 | clear[5] | High Range | IO_L2N_T0_AD8N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| A10 | din[11] | High Range | IO_L3N_T0_DQS_AD1N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | A11 | | | GND | GND | | | | | | | 0.0 | | | | | | -| A12 | clear[0] | High Range | IO_L5N_T0_AD9N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| A13 | sclk[1] | High Range | IO_L7P_T1_AD2P_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| A14 | sclk[0] | High Range | IO_L7N_T1_AD2N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| A15 | sdo_bit[0] | High Range | IO_L9N_T1_DQS_AD3N_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | +| A12 | clear[10] | High Range | IO_L5N_T0_AD9N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| A13 | sdo_bit[3] | High Range | IO_L7P_T1_AD2P_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | +| A14 | sclk[10] | High Range | IO_L7N_T1_AD2N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| A15 | sdo_bit[10] | High Range | IO_L9N_T1_DQS_AD3N_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | A16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | -| B1 | sdo_bit[10] | High Range | IO_L9N_T1_DQS_AD7N_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | -| B2 | sclk[6] | High Range | IO_L8P_T1_AD14P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| B1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | +| B2 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | B3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | B4 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | B5 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | B6 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | B7 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | B8 | | | GND | GND | | | | | | | 0.0 | | | | | | -| B9 | latch[4] | High Range | IO_L3P_T0_DQS_AD1P_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| B10 | clear[4] | High Range | IO_L4P_T0_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| B9 | latch[5] | High Range | IO_L3P_T0_DQS_AD1P_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| B10 | sdo_bit[4] | High Range | IO_L4P_T0_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | B11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | -| B12 | clear[1] | High Range | IO_L5P_T0_AD9P_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| B12 | sclk[4] | High Range | IO_L5P_T0_AD9P_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | B13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | -| B14 | din[0] | High Range | IO_L8N_T1_AD10N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| B15 | clear[10] | High Range | IO_L9P_T1_DQS_AD3P_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| B16 | clear[3] | High Range | IO_L10N_T1_AD11N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| C1 | clear[7] | High Range | IO_L9P_T1_DQS_AD7P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| C2 | latch[6] | High Range | IO_L7N_T1_AD6N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| B14 | din[10] | High Range | IO_L8N_T1_AD10N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| B15 | latch[3] | High Range | IO_L9P_T1_DQS_AD3P_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| B16 | clear[9] | High Range | IO_L10N_T1_AD11N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| C1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | +| C2 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | C3 | led[5] | High Range | IO_L7P_T1_AD6P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| C4 | sdo_bit[6] | High Range | IO_L12N_T1_MRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| C4 | sclk[5] | High Range | IO_L12N_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | C6 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | C7 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | -| C8 | din[4] | High Range | IO_L1P_T0_AD0P_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| C9 | sclk[5] | High Range | IO_L1N_T0_AD0N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| C8 | din[5] | High Range | IO_L1P_T0_AD0P_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| C9 | sclk[11] | High Range | IO_L1N_T0_AD0N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | C10 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | -| C11 | sdo_bit[5] | High Range | IO_L11P_T1_SRCC_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | -| C12 | latch[1] | High Range | IO_L11N_T1_SRCC_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| C11 | sdo_bit[11] | High Range | IO_L11P_T1_SRCC_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | +| C12 | clear[4] | High Range | IO_L11N_T1_SRCC_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | C13 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | -| C14 | sdo_bit[1] | High Range | IO_L8P_T1_AD10P_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | +| C14 | sclk[3] | High Range | IO_L8P_T1_AD10P_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | C15 | | | GND | GND | | | | | | | 0.0 | | | | | | -| C16 | latch[10] | High Range | IO_L10P_T1_AD11P_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| D1 | clear[6] | High Range | IO_L10N_T1_AD15N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| C16 | clear[3] | High Range | IO_L10P_T1_AD11P_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| D1 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | D2 | | | GND | GND | | | | | | | 0.0 | | | | | | | D3 | led[4] | High Range | IO_L11N_T1_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| D4 | sclk[10] | High Range | IO_L12P_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| D4 | din[4] | High Range | IO_L12P_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | D5 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | D6 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | D7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | D8 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | -| D9 | clear[5] | High Range | IO_L6N_T0_VREF_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| D10 | latch[5] | High Range | IO_0_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| D9 | clear[11] | High Range | IO_L6N_T0_VREF_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| D10 | latch[11] | High Range | IO_0_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | D11 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | D13 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | -| D14 | sclk[3] | High Range | IO_L15P_T2_DQS_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| D15 | latch[3] | High Range | IO_L15N_T2_DQS_ADV_B_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| D16 | clear[11] | High Range | IO_L17N_T2_A25_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| E1 | sdo_bit[8] | High Range | IO_L15N_T2_DQS_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | -| E2 | latch[7] | High Range | IO_L10P_T1_AD15P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| D14 | sclk[9] | High Range | IO_L15P_T2_DQS_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| D15 | latch[9] | High Range | IO_L15N_T2_DQS_ADV_B_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| D16 | sdo_bit[7] | High Range | IO_L17N_T2_A25_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | +| E1 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | +| E2 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | E3 | led[2] | High Range | IO_L11P_T1_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | E4 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | E5 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | @@ -110,13 +110,13 @@ Table of Contents | E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | E10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | E11 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | -| E12 | din[2] | High Range | IO_L13P_T2_MRCC_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| E13 | din[1] | High Range | IO_L13N_T2_MRCC_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| E12 | sdo_bit[8] | High Range | IO_L13P_T2_MRCC_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | +| E13 | din[3] | High Range | IO_L13N_T2_MRCC_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | E14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | -| E15 | din[3] | High Range | IO_L18N_T2_A23_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| E16 | latch[11] | High Range | IO_L17P_T2_A26_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| E15 | din[9] | High Range | IO_L18N_T2_A23_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| E16 | din[7] | High Range | IO_L17P_T2_A26_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | F1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | -| F2 | sclk[7] | High Range | IO_L15P_T2_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| F2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | F3 | led[1] | High Range | IO_L14N_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | F4 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | F5 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | @@ -127,12 +127,12 @@ Table of Contents | F10 | | | GND | GND | | | | | | | 0.0 | | | | | | | F11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | F12 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | -| F13 | latch[0] | High Range | IO_L16N_T2_A27_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| F14 | sdo_bit[3] | High Range | IO_L21N_T3_DQS_A18_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | -| F15 | sdo_bit[2] | High Range | IO_L18P_T2_A24_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | +| F13 | latch[10] | High Range | IO_L16N_T2_A27_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| F14 | sdo_bit[9] | High Range | IO_L21N_T3_DQS_A18_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | +| F15 | din[8] | High Range | IO_L18P_T2_A24_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | F16 | | | GND | GND | | | | | | | 0.0 | | | | | | -| G1 | din[7] | High Range | IO_L17N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| G2 | din[8] | High Range | IO_L17P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | +| G2 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | G3 | | | GND | GND | | | | | | | 0.0 | | | | | | | G4 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | G5 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | @@ -144,11 +144,11 @@ Table of Contents | G11 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | G12 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | G13 | | | GND | GND | | | | | | | 0.0 | | | | | | -| G14 | sclk[2] | High Range | IO_L21P_T3_DQS_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| G15 | sclk[11] | High Range | IO_L24N_T3_RS0_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| G16 | clear[2] | High Range | IO_L22N_T3_A16_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| H1 | sdo_bit[7] | High Range | IO_L20N_T3_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | -| H2 | sclk[8] | High Range | IO_L20P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G14 | sclk[8] | High Range | IO_L21P_T3_DQS_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G15 | sclk[7] | High Range | IO_L24N_T3_RS0_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G16 | clear[8] | High Range | IO_L22N_T3_A16_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H1 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | +| H2 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | H3 | led[6] | High Range | IO_L21N_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | H4 | led[3] | High Range | IO_L18N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | H5 | led[0] | High Range | IO_L18P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | @@ -159,13 +159,13 @@ Table of Contents | H10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | H11 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | H12 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | -| H13 | sdo_bit[11] | High Range | IO_L20N_T3_A19_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | -| H14 | din[11] | High Range | IO_L24P_T3_RS1_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H13 | clear[7] | High Range | IO_L20N_T3_A19_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H14 | latch[7] | High Range | IO_L24P_T3_RS1_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | H15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | -| H16 | latch[2] | High Range | IO_L22P_T3_A17_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H16 | latch[8] | High Range | IO_L22P_T3_A17_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | J1 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | J2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | -| J3 | latch[8] | High Range | IO_L21P_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J3 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | J4 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | J5 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | J6 | | | VCCINT | VCCINT | | | | | | | | | | | | | @@ -179,7 +179,7 @@ Table of Contents | J14 | hi_inout[14] | High Range | IO_L1N_T0_D01_DIN_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | J15 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | J16 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | -| K1 | clear[8] | High Range | IO_L22P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K1 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | K2 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | K3 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | K4 | | | GND | GND | | | | | | | 0.0 | | | | | | @@ -213,7 +213,7 @@ Table of Contents | L16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | M1 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | M2 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | -| M3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | +| M3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | M4 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | M5 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | M6 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | @@ -230,9 +230,9 @@ Table of Contents | N1 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | N2 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | N3 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | -| N4 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | +| N4 | sdo_bit[1] | High Range | IO_L6N_T0_VREF_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | N5 | | | GND | GND | | | | | | | 0.0 | | | | | | -| N6 | clear[9] | High Range | IO_L19N_T3_A09_D25_VREF_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N6 | clear[1] | High Range | IO_L19N_T3_A09_D25_VREF_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | N7 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | N8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | N9 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | @@ -245,12 +245,12 @@ Table of Contents | N16 | hi_inout[5] | High Range | IO_L7N_T1_D10_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | P1 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | P2 | | | GND | GND | | | | | | | 0.0 | | | | | | -| P3 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | -| P4 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | -| P5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | +| P3 | din[2] | High Range | IO_L5N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P4 | din[1] | High Range | IO_L5P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P5 | latch[1] | High Range | IO_L10P_T1_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | P6 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | P7 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | -| P8 | latch[9] | High Range | IO_L20P_T3_A08_D24_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P8 | din[0] | High Range | IO_L20P_T3_A08_D24_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | P9 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | P10 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | P11 | hi_in[6] | High Range | IO_L14N_T2_SRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | @@ -260,13 +260,13 @@ Table of Contents | P15 | hi_inout[4] | High Range | IO_L8P_T1_D11_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | P16 | hi_inout[3] | High Range | IO_L8N_T1_D12_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | R1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | -| R2 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | -| R3 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | -| R4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | -| R5 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | -| R6 | sclk[9] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| R7 | din[9] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| R8 | sdo_bit[9] | High Range | IO_L20N_T3_A07_D23_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | +| R2 | sdo_bit[2] | High Range | IO_L7P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| R3 | latch[2] | High Range | IO_L8P_T1_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| R5 | sdo_bit[0] | High Range | IO_L23P_T3_A03_D19_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | +| R6 | latch[0] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R7 | clear[6] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R8 | sclk[6] | High Range | IO_L20N_T3_A07_D23_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | R9 | | | GND | GND | | | | | | | 0.0 | | | | | | | R10 | hi_in[7] | High Range | IO_L17P_T2_A14_D30_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | R11 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | @@ -275,16 +275,16 @@ Table of Contents | R14 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | R15 | hi_out[0] | High Range | IO_L9P_T1_DQS_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | R16 | hi_inout[2] | High Range | IO_L9N_T1_DQS_D13_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| T1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | -| T2 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | -| T3 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | -| T4 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | -| T5 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | +| T1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| T2 | sclk[2] | High Range | IO_L8N_T1_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| T3 | clear[2] | High Range | IO_L9N_T1_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| T4 | sclk[1] | High Range | IO_L9P_T1_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| T5 | sclk[0] | High Range | IO_L23N_T3_A02_D18_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | T6 | | | GND | GND | | | | | | | 0.0 | | | | | | -| T7 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | -| T8 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | -| T9 | khan | High Range | IO_L22P_T3_A05_D21_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | -| T10 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | +| T7 | latch[6] | High Range | IO_L21P_T3_DQS_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| T8 | sdo_bit[6] | High Range | IO_L21N_T3_DQS_A06_D22_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | +| T9 | clear[0] | High Range | IO_L22P_T3_A05_D21_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| T10 | din[6] | High Range | IO_L22N_T3_A04_D20_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | T11 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | T12 | hi_in[5] | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | T13 | hi_in[4] | High Range | IO_L16N_T2_A15_D31_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_methodology_drc_routed.rpt b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_methodology_drc_routed.rpt index 53c1895..664db44 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_methodology_drc_routed.rpt +++ b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_methodology_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -| Date : Tue Feb 26 23:49:45 2019 +| Date : Tue Mar 19 19:00:31 2019 | Host : EECS-TOYODA running 64-bit major release (build 9200) | Command : report_methodology -file OSC1_LITE_Control_methodology_drc_routed.rpt -rpx OSC1_LITE_Control_methodology_drc_routed.rpx | Design : OSC1_LITE_Control @@ -23,13 +23,12 @@ Table of Contents Floorplan: design_1 Design limits: Max violations: - Violations found: 210 + Violations found: 207 +-----------+----------+---------------------------------------------------+------------+ | Rule | Severity | Description | Violations | +-----------+----------+---------------------------------------------------+------------+ | TIMING-17 | Warning | Non-clocked sequential cell | 142 | -| TIMING-18 | Warning | Missing input or output delay | 46 | -| XDCC-5 | Warning | User Non-Timing constraint/property overwritten | 2 | +| TIMING-18 | Warning | Missing input or output delay | 45 | | XDCH-1 | Warning | Hold option missing in multicycle path constraint | 2 | | XDCH-2 | Warning | Same min and max delay values on IO port | 18 | +-----------+----------+---------------------------------------------------+------------+ @@ -873,123 +872,104 @@ Related violations: TIMING-18#26 Warning Missing input or output delay -An output delay is missing on khan relative to clock(s) okHostClk -Related violations: - -TIMING-18#27 Warning -Missing input or output delay An output delay is missing on led[0] relative to clock(s) okHostClk Related violations: -TIMING-18#28 Warning +TIMING-18#27 Warning Missing input or output delay An output delay is missing on led[1] relative to clock(s) okHostClk Related violations: -TIMING-18#29 Warning +TIMING-18#28 Warning Missing input or output delay An output delay is missing on led[2] relative to clock(s) okHostClk Related violations: -TIMING-18#30 Warning +TIMING-18#29 Warning Missing input or output delay An output delay is missing on led[3] relative to clock(s) okHostClk Related violations: -TIMING-18#31 Warning +TIMING-18#30 Warning Missing input or output delay An output delay is missing on led[4] relative to clock(s) okHostClk Related violations: -TIMING-18#32 Warning +TIMING-18#31 Warning Missing input or output delay An output delay is missing on led[5] relative to clock(s) okHostClk Related violations: -TIMING-18#33 Warning +TIMING-18#32 Warning Missing input or output delay An output delay is missing on led[6] relative to clock(s) okHostClk Related violations: -TIMING-18#34 Warning +TIMING-18#33 Warning Missing input or output delay An output delay is missing on led[7] relative to clock(s) okHostClk Related violations: -TIMING-18#35 Warning +TIMING-18#34 Warning Missing input or output delay An output delay is missing on sclk[0] relative to clock(s) okHostClk Related violations: -TIMING-18#36 Warning +TIMING-18#35 Warning Missing input or output delay An output delay is missing on sclk[10] relative to clock(s) okHostClk Related violations: -TIMING-18#37 Warning +TIMING-18#36 Warning Missing input or output delay An output delay is missing on sclk[11] relative to clock(s) okHostClk Related violations: -TIMING-18#38 Warning +TIMING-18#37 Warning Missing input or output delay An output delay is missing on sclk[1] relative to clock(s) okHostClk Related violations: -TIMING-18#39 Warning +TIMING-18#38 Warning Missing input or output delay An output delay is missing on sclk[2] relative to clock(s) okHostClk Related violations: -TIMING-18#40 Warning +TIMING-18#39 Warning Missing input or output delay An output delay is missing on sclk[3] relative to clock(s) okHostClk Related violations: -TIMING-18#41 Warning +TIMING-18#40 Warning Missing input or output delay An output delay is missing on sclk[4] relative to clock(s) okHostClk Related violations: -TIMING-18#42 Warning +TIMING-18#41 Warning Missing input or output delay An output delay is missing on sclk[5] relative to clock(s) okHostClk Related violations: -TIMING-18#43 Warning +TIMING-18#42 Warning Missing input or output delay An output delay is missing on sclk[6] relative to clock(s) okHostClk Related violations: -TIMING-18#44 Warning +TIMING-18#43 Warning Missing input or output delay An output delay is missing on sclk[7] relative to clock(s) okHostClk Related violations: -TIMING-18#45 Warning +TIMING-18#44 Warning Missing input or output delay An output delay is missing on sclk[8] relative to clock(s) okHostClk Related violations: -TIMING-18#46 Warning +TIMING-18#45 Warning Missing input or output delay An output delay is missing on sclk[9] relative to clock(s) okHostClk Related violations: -XDCC-5#1 Warning -User Non-Timing constraint/property overwritten -A new XDC property PACKAGE_PIN on khan overrides a previous user property. -New Source: C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc (Line: 331) -Previous Source: C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc (Line: 315) -Related violations: - -XDCC-5#2 Warning -User Non-Timing constraint/property overwritten -A new XDC property PACKAGE_PIN on latch[10] overrides a previous user property. -New Source: C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc (Line: 475) -Previous Source: C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc (Line: 275) -Related violations: - XDCH-1#1 Warning Hold option missing in multicycle path constraint A multicycle constraint has been set to override the setup relationship, but no multicycle constraint has been defined to change the hold relationship. As a result, the default hold for those paths is derived from the setup and may not be evaluated as expected. diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_methodology_drc_routed.rpx b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_methodology_drc_routed.rpx index 63d3d17..b826da4 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_methodology_drc_routed.rpx and b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_methodology_drc_routed.rpx differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_opt.dcp b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_opt.dcp index 5197553..18b501e 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_opt.dcp and b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_opt.dcp differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_placed.dcp b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_placed.dcp index 32bc891..5e88191 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_placed.dcp and b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_placed.dcp differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_power_routed.rpt b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_power_routed.rpt index 33cf23f..60c35f6 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_power_routed.rpt +++ b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_power_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -| Date : Tue Feb 26 23:49:46 2019 +| Date : Tue Mar 19 19:00:33 2019 | Host : EECS-TOYODA running 64-bit major release (build 9200) | Command : report_power -file OSC1_LITE_Control_power_routed.rpt -pb OSC1_LITE_Control_power_summary_routed.pb -rpx OSC1_LITE_Control_power_routed.rpx | Design : OSC1_LITE_Control @@ -50,18 +50,18 @@ Table of Contents | On-Chip | Power (W) | Used | Available | Utilization (%) | +--------------------------+-----------+----------+-----------+-----------------+ | Clocks | 0.002 | 5 | --- | --- | -| Slice Logic | 0.003 | 2754 | --- | --- | -| LUT as Logic | 0.002 | 1188 | 10400 | 11.42 | +| Slice Logic | 0.002 | 2731 | --- | --- | +| LUT as Logic | 0.002 | 1163 | 10400 | 11.18 | | LUT as Distributed RAM | <0.001 | 32 | 9600 | 0.33 | | Register | <0.001 | 1143 | 20800 | 5.50 | | CARRY4 | <0.001 | 50 | 8150 | 0.61 | | BUFG | <0.001 | 3 | 32 | 9.38 | | F7/F8 Muxes | <0.001 | 8 | 32600 | 0.02 | | Others | 0.000 | 87 | --- | --- | -| Signals | 0.003 | 2558 | --- | --- | +| Signals | 0.002 | 2537 | --- | --- | | Block RAM | <0.001 | 17.5 | 25 | 70.00 | | MMCM | 0.103 | 1 | 5 | 20.00 | -| I/O | 0.020 | 86 | 170 | 50.59 | +| I/O | 0.020 | 85 | 170 | 50.00 | | Static Power | 0.073 | | | | | Total | 0.203 | | | | +--------------------------+-----------+----------+-----------+-----------------+ @@ -198,7 +198,7 @@ Table of Contents | prim_noinit.ram | <0.001 | | ramloop[9].ram.r | <0.001 | | prim_noinit.ram | <0.001 | -| okHI | 0.115 | +| okHI | 0.114 | | core0 | 0.005 | | core0 | 0.005 | | a0/cb0 | <0.001 | diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_power_routed.rpx b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_power_routed.rpx index 029a842..2a3cb4b 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_power_routed.rpx and b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_power_routed.rpx differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_power_summary_routed.pb b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_power_summary_routed.pb index fe16b67..e447fe9 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_power_summary_routed.pb and b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_power_summary_routed.pb differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_route_status.pb b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_route_status.pb index 48f8b36..f12899b 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_route_status.pb and b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_route_status.pb differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_route_status.rpt b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_route_status.rpt index 5a0b5e0..b4eb39c 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_route_status.rpt +++ b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_route_status.rpt @@ -1,11 +1,11 @@ Design Route Status : # nets : ------------------------------------------- : ----------- : - # of logical nets.......................... : 3157 : - # of nets not needing routing.......... : 592 : - # of internally routed nets........ : 592 : - # of routable nets..................... : 2565 : - # of fully routed nets............. : 2565 : + # of logical nets.......................... : 3133 : + # of nets not needing routing.......... : 589 : + # of internally routed nets........ : 589 : + # of routable nets..................... : 2544 : + # of fully routed nets............. : 2544 : # of nets with routing errors.......... : 0 : ------------------------------------------- : ----------- : diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_routed.dcp b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_routed.dcp index 01c4fc3..01eff8f 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_routed.dcp and b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_routed.dcp differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_timing_summary_routed.rpt b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_timing_summary_routed.rpt index 0c2439d..ba22c60 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_timing_summary_routed.rpt +++ b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_timing_summary_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -| Date : Tue Feb 26 23:49:47 2019 +| Date : Tue Mar 19 19:00:33 2019 | Host : EECS-TOYODA running 64-bit major release (build 9200) | Command : report_timing_summary -warn_on_violation -max_paths 10 -file OSC1_LITE_Control_timing_summary_routed.rpt -rpx OSC1_LITE_Control_timing_summary_routed.rpx | Design : OSC1_LITE_Control @@ -113,7 +113,7 @@ Table of Contents 6. checking no_output_delay --------------------------- - There are 55 ports with no output delay specified. (HIGH) + There are 54 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint @@ -158,7 +158,7 @@ Table of Contents WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 6.046 0.000 0 3425 0.056 0.000 0 3425 5.415 0.000 0 1141 + 6.825 0.000 0 3425 0.121 0.000 0 3425 5.415 0.000 0 1141 All user specified timing constraints are met. @@ -184,7 +184,7 @@ okHostClk {0.000 10.415} 20.830 48.008 Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- okHostClk 5.415 0.000 0 1 - mmcm0_clk0 11.037 0.000 0 3199 0.056 0.000 0 3199 9.165 0.000 0 1137 + mmcm0_clk0 11.082 0.000 0 3199 0.121 0.000 0 3199 9.165 0.000 0 1137 mmcm0_clkfb 18.675 0.000 0 3 @@ -195,7 +195,7 @@ okHostClk From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -mmcm0_clk0 okHostClk 6.444 0.000 0 17 9.804 0.000 0 17 +mmcm0_clk0 okHostClk 6.825 0.000 0 17 9.804 0.000 0 17 okHostClk mmcm0_clk0 7.032 0.000 0 86 0.533 0.000 0 86 @@ -206,8 +206,8 @@ okHostClk mmcm0_clk0 7.032 0.000 0 Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -**async_default** mmcm0_clk0 mmcm0_clk0 16.919 0.000 0 100 0.467 0.000 0 100 -**async_default** okHostClk mmcm0_clk0 6.046 0.000 0 132 1.763 0.000 0 132 +**async_default** mmcm0_clk0 mmcm0_clk0 16.929 0.000 0 100 0.383 0.000 0 100 +**async_default** okHostClk mmcm0_clk0 6.843 0.000 0 132 1.823 0.000 0 132 ------------------------------------------------------------------------------------------------ @@ -247,15 +247,15 @@ High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 5.000 10.415 From Clock: mmcm0_clk0 To Clock: mmcm0_clk0 -Setup : 0 Failing Endpoints, Worst Slack 11.037ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.056ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 11.082ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.121ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 9.165ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 11.037ns (required time - arrival time) +Slack (MET) : 11.082ns (required time - arrival time) Source: okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK (rising edge-triggered cell RAMB18E1 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Destination: okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[4]/R @@ -263,11 +263,11 @@ Slack (MET) : 11.037ns (required time - arrival time) Path Group: mmcm0_clk0 Path Type: Setup (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 9.150ns (logic 3.537ns (38.654%) route 5.613ns (61.346%)) + Data Path Delay: 9.105ns (logic 3.543ns (38.913%) route 5.562ns (61.087%)) Logic Levels: 5 (LUT2=1 LUT3=1 LUT5=1 LUT6=1 RAMD32=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.483ns = ( 19.607 - 21.090 ) - Source Clock Delay (SCD): -0.838ns = ( -0.577 - 0.260 ) + Destination Clock Delay (DCD): -1.487ns = ( 19.603 - 21.090 ) + Source Clock Delay (SCD): -0.842ns = ( -0.581 - 0.260 ) Clock Pessimism Removal (CPR): 0.577ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -286,24 +286,24 @@ Slack (MET) : 11.037ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.613 -0.577 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - RAMB18_X0Y19 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - ------------------------------------------------------------------- ------------------- - RAMB18_X0Y19 RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[7]) - 2.454 1.877 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DOADO[7] - net (fo=23, routed) 1.653 3.530 okHI/core0/core0/a0/pc0/upper_reg_banks/ADDRA3 - SLICE_X10Y46 RAMD32 (Prop_ramd32_RADR3_O) - 0.150 3.680 f okHI/core0/core0/a0/pc0/upper_reg_banks/RAMA/O - net (fo=3, routed) 1.101 4.781 okHI/core0/core0/a0/pc0/data_path_loop[4].output_data.sy_kk_mux_lut/I0 - SLICE_X11Y46 LUT5 (Prop_lut5_I0_O) 0.358 5.139 f okHI/core0/core0/a0/pc0/data_path_loop[4].output_data.sy_kk_mux_lut/LUT5/O - net (fo=20, routed) 0.881 6.020 okHI/core0/core0/a0/l91f05f26d7832afb9cfdc67ea9d72301[4] - SLICE_X9Y46 LUT6 (Prop_lut6_I0_O) 0.327 6.347 f okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2/O - net (fo=4, routed) 0.816 7.163 okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2_n_0 - SLICE_X7Y44 LUT3 (Prop_lut3_I0_O) 0.124 7.287 r okHI/core0/core0/ld307737e57d50d07f937891de086bf8e_i_3/O - net (fo=11, routed) 0.585 7.873 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_2_n_0 - SLICE_X8Y45 LUT2 (Prop_lut2_I1_O) 0.124 7.997 r okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1/O - net (fo=4, routed) 0.577 8.573 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1_n_0 - SLICE_X8Y45 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[4]/R + net (fo=1135, routed) 1.609 -0.581 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + RAMB18_X0Y15 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK + ------------------------------------------------------------------- ------------------- + RAMB18_X0Y15 RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[5]) + 2.454 1.873 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DOADO[5] + net (fo=14, routed) 2.053 3.926 okHI/core0/core0/a0/pc0/upper_reg_banks/ADDRC1 + SLICE_X10Y37 RAMD32 (Prop_ramd32_RADR1_O) + 0.153 4.079 f okHI/core0/core0/a0/pc0/upper_reg_banks/RAMC/O + net (fo=3, routed) 0.834 4.913 okHI/core0/core0/a0/pc0/data_path_loop[6].output_data.sy_kk_mux_lut/I0 + SLICE_X11Y35 LUT5 (Prop_lut5_I0_O) 0.356 5.269 f okHI/core0/core0/a0/pc0/data_path_loop[6].output_data.sy_kk_mux_lut/LUT5/O + net (fo=28, routed) 1.085 6.354 okHI/core0/core0/a0/l91f05f26d7832afb9cfdc67ea9d72301[6] + SLICE_X10Y35 LUT6 (Prop_lut6_I3_O) 0.332 6.686 f okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2/O + net (fo=4, routed) 0.631 7.317 okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2_n_0 + SLICE_X8Y35 LUT3 (Prop_lut3_I0_O) 0.124 7.441 r okHI/core0/core0/ld307737e57d50d07f937891de086bf8e_i_3/O + net (fo=11, routed) 0.311 7.752 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_2_n_0 + SLICE_X8Y35 LUT2 (Prop_lut2_I1_O) 0.124 7.876 r okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1/O + net (fo=4, routed) 0.648 8.524 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1_n_0 + SLICE_X8Y37 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[4]/R ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -316,18 +316,18 @@ Slack (MET) : 11.037ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.450 19.607 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X8Y45 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[4]/C - clock pessimism 0.577 20.184 - clock uncertainty -0.050 20.134 - SLICE_X8Y45 FDRE (Setup_fdre_C_R) -0.524 19.610 okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[4] + net (fo=1135, routed) 1.446 19.603 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X8Y37 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[4]/C + clock pessimism 0.577 20.180 + clock uncertainty -0.050 20.130 + SLICE_X8Y37 FDRE (Setup_fdre_C_R) -0.524 19.606 okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[4] ------------------------------------------------------------------- - required time 19.610 - arrival time -8.573 + required time 19.606 + arrival time -8.524 ------------------------------------------------------------------- - slack 11.037 + slack 11.082 -Slack (MET) : 11.037ns (required time - arrival time) +Slack (MET) : 11.082ns (required time - arrival time) Source: okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK (rising edge-triggered cell RAMB18E1 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Destination: okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[5]/R @@ -335,11 +335,11 @@ Slack (MET) : 11.037ns (required time - arrival time) Path Group: mmcm0_clk0 Path Type: Setup (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 9.150ns (logic 3.537ns (38.654%) route 5.613ns (61.346%)) + Data Path Delay: 9.105ns (logic 3.543ns (38.913%) route 5.562ns (61.087%)) Logic Levels: 5 (LUT2=1 LUT3=1 LUT5=1 LUT6=1 RAMD32=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.483ns = ( 19.607 - 21.090 ) - Source Clock Delay (SCD): -0.838ns = ( -0.577 - 0.260 ) + Destination Clock Delay (DCD): -1.487ns = ( 19.603 - 21.090 ) + Source Clock Delay (SCD): -0.842ns = ( -0.581 - 0.260 ) Clock Pessimism Removal (CPR): 0.577ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -358,24 +358,24 @@ Slack (MET) : 11.037ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.613 -0.577 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - RAMB18_X0Y19 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - ------------------------------------------------------------------- ------------------- - RAMB18_X0Y19 RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[7]) - 2.454 1.877 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DOADO[7] - net (fo=23, routed) 1.653 3.530 okHI/core0/core0/a0/pc0/upper_reg_banks/ADDRA3 - SLICE_X10Y46 RAMD32 (Prop_ramd32_RADR3_O) - 0.150 3.680 f okHI/core0/core0/a0/pc0/upper_reg_banks/RAMA/O - net (fo=3, routed) 1.101 4.781 okHI/core0/core0/a0/pc0/data_path_loop[4].output_data.sy_kk_mux_lut/I0 - SLICE_X11Y46 LUT5 (Prop_lut5_I0_O) 0.358 5.139 f okHI/core0/core0/a0/pc0/data_path_loop[4].output_data.sy_kk_mux_lut/LUT5/O - net (fo=20, routed) 0.881 6.020 okHI/core0/core0/a0/l91f05f26d7832afb9cfdc67ea9d72301[4] - SLICE_X9Y46 LUT6 (Prop_lut6_I0_O) 0.327 6.347 f okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2/O - net (fo=4, routed) 0.816 7.163 okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2_n_0 - SLICE_X7Y44 LUT3 (Prop_lut3_I0_O) 0.124 7.287 r okHI/core0/core0/ld307737e57d50d07f937891de086bf8e_i_3/O - net (fo=11, routed) 0.585 7.873 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_2_n_0 - SLICE_X8Y45 LUT2 (Prop_lut2_I1_O) 0.124 7.997 r okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1/O - net (fo=4, routed) 0.577 8.573 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1_n_0 - SLICE_X8Y45 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[5]/R + net (fo=1135, routed) 1.609 -0.581 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + RAMB18_X0Y15 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK + ------------------------------------------------------------------- ------------------- + RAMB18_X0Y15 RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[5]) + 2.454 1.873 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DOADO[5] + net (fo=14, routed) 2.053 3.926 okHI/core0/core0/a0/pc0/upper_reg_banks/ADDRC1 + SLICE_X10Y37 RAMD32 (Prop_ramd32_RADR1_O) + 0.153 4.079 f okHI/core0/core0/a0/pc0/upper_reg_banks/RAMC/O + net (fo=3, routed) 0.834 4.913 okHI/core0/core0/a0/pc0/data_path_loop[6].output_data.sy_kk_mux_lut/I0 + SLICE_X11Y35 LUT5 (Prop_lut5_I0_O) 0.356 5.269 f okHI/core0/core0/a0/pc0/data_path_loop[6].output_data.sy_kk_mux_lut/LUT5/O + net (fo=28, routed) 1.085 6.354 okHI/core0/core0/a0/l91f05f26d7832afb9cfdc67ea9d72301[6] + SLICE_X10Y35 LUT6 (Prop_lut6_I3_O) 0.332 6.686 f okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2/O + net (fo=4, routed) 0.631 7.317 okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2_n_0 + SLICE_X8Y35 LUT3 (Prop_lut3_I0_O) 0.124 7.441 r okHI/core0/core0/ld307737e57d50d07f937891de086bf8e_i_3/O + net (fo=11, routed) 0.311 7.752 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_2_n_0 + SLICE_X8Y35 LUT2 (Prop_lut2_I1_O) 0.124 7.876 r okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1/O + net (fo=4, routed) 0.648 8.524 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1_n_0 + SLICE_X8Y37 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[5]/R ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -388,18 +388,18 @@ Slack (MET) : 11.037ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.450 19.607 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X8Y45 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[5]/C - clock pessimism 0.577 20.184 - clock uncertainty -0.050 20.134 - SLICE_X8Y45 FDRE (Setup_fdre_C_R) -0.524 19.610 okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[5] + net (fo=1135, routed) 1.446 19.603 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X8Y37 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[5]/C + clock pessimism 0.577 20.180 + clock uncertainty -0.050 20.130 + SLICE_X8Y37 FDRE (Setup_fdre_C_R) -0.524 19.606 okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[5] ------------------------------------------------------------------- - required time 19.610 - arrival time -8.573 + required time 19.606 + arrival time -8.524 ------------------------------------------------------------------- - slack 11.037 + slack 11.082 -Slack (MET) : 11.037ns (required time - arrival time) +Slack (MET) : 11.082ns (required time - arrival time) Source: okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK (rising edge-triggered cell RAMB18E1 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Destination: okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[6]/R @@ -407,11 +407,11 @@ Slack (MET) : 11.037ns (required time - arrival time) Path Group: mmcm0_clk0 Path Type: Setup (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 9.150ns (logic 3.537ns (38.654%) route 5.613ns (61.346%)) + Data Path Delay: 9.105ns (logic 3.543ns (38.913%) route 5.562ns (61.087%)) Logic Levels: 5 (LUT2=1 LUT3=1 LUT5=1 LUT6=1 RAMD32=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.483ns = ( 19.607 - 21.090 ) - Source Clock Delay (SCD): -0.838ns = ( -0.577 - 0.260 ) + Destination Clock Delay (DCD): -1.487ns = ( 19.603 - 21.090 ) + Source Clock Delay (SCD): -0.842ns = ( -0.581 - 0.260 ) Clock Pessimism Removal (CPR): 0.577ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -430,24 +430,24 @@ Slack (MET) : 11.037ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.613 -0.577 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - RAMB18_X0Y19 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - ------------------------------------------------------------------- ------------------- - RAMB18_X0Y19 RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[7]) - 2.454 1.877 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DOADO[7] - net (fo=23, routed) 1.653 3.530 okHI/core0/core0/a0/pc0/upper_reg_banks/ADDRA3 - SLICE_X10Y46 RAMD32 (Prop_ramd32_RADR3_O) - 0.150 3.680 f okHI/core0/core0/a0/pc0/upper_reg_banks/RAMA/O - net (fo=3, routed) 1.101 4.781 okHI/core0/core0/a0/pc0/data_path_loop[4].output_data.sy_kk_mux_lut/I0 - SLICE_X11Y46 LUT5 (Prop_lut5_I0_O) 0.358 5.139 f okHI/core0/core0/a0/pc0/data_path_loop[4].output_data.sy_kk_mux_lut/LUT5/O - net (fo=20, routed) 0.881 6.020 okHI/core0/core0/a0/l91f05f26d7832afb9cfdc67ea9d72301[4] - SLICE_X9Y46 LUT6 (Prop_lut6_I0_O) 0.327 6.347 f okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2/O - net (fo=4, routed) 0.816 7.163 okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2_n_0 - SLICE_X7Y44 LUT3 (Prop_lut3_I0_O) 0.124 7.287 r okHI/core0/core0/ld307737e57d50d07f937891de086bf8e_i_3/O - net (fo=11, routed) 0.585 7.873 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_2_n_0 - SLICE_X8Y45 LUT2 (Prop_lut2_I1_O) 0.124 7.997 r okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1/O - net (fo=4, routed) 0.577 8.573 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1_n_0 - SLICE_X8Y45 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[6]/R + net (fo=1135, routed) 1.609 -0.581 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + RAMB18_X0Y15 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK + ------------------------------------------------------------------- ------------------- + RAMB18_X0Y15 RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[5]) + 2.454 1.873 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DOADO[5] + net (fo=14, routed) 2.053 3.926 okHI/core0/core0/a0/pc0/upper_reg_banks/ADDRC1 + SLICE_X10Y37 RAMD32 (Prop_ramd32_RADR1_O) + 0.153 4.079 f okHI/core0/core0/a0/pc0/upper_reg_banks/RAMC/O + net (fo=3, routed) 0.834 4.913 okHI/core0/core0/a0/pc0/data_path_loop[6].output_data.sy_kk_mux_lut/I0 + SLICE_X11Y35 LUT5 (Prop_lut5_I0_O) 0.356 5.269 f okHI/core0/core0/a0/pc0/data_path_loop[6].output_data.sy_kk_mux_lut/LUT5/O + net (fo=28, routed) 1.085 6.354 okHI/core0/core0/a0/l91f05f26d7832afb9cfdc67ea9d72301[6] + SLICE_X10Y35 LUT6 (Prop_lut6_I3_O) 0.332 6.686 f okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2/O + net (fo=4, routed) 0.631 7.317 okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2_n_0 + SLICE_X8Y35 LUT3 (Prop_lut3_I0_O) 0.124 7.441 r okHI/core0/core0/ld307737e57d50d07f937891de086bf8e_i_3/O + net (fo=11, routed) 0.311 7.752 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_2_n_0 + SLICE_X8Y35 LUT2 (Prop_lut2_I1_O) 0.124 7.876 r okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1/O + net (fo=4, routed) 0.648 8.524 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1_n_0 + SLICE_X8Y37 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[6]/R ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -460,18 +460,18 @@ Slack (MET) : 11.037ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.450 19.607 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X8Y45 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[6]/C - clock pessimism 0.577 20.184 - clock uncertainty -0.050 20.134 - SLICE_X8Y45 FDRE (Setup_fdre_C_R) -0.524 19.610 okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[6] + net (fo=1135, routed) 1.446 19.603 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X8Y37 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[6]/C + clock pessimism 0.577 20.180 + clock uncertainty -0.050 20.130 + SLICE_X8Y37 FDRE (Setup_fdre_C_R) -0.524 19.606 okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[6] ------------------------------------------------------------------- - required time 19.610 - arrival time -8.573 + required time 19.606 + arrival time -8.524 ------------------------------------------------------------------- - slack 11.037 + slack 11.082 -Slack (MET) : 11.037ns (required time - arrival time) +Slack (MET) : 11.082ns (required time - arrival time) Source: okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK (rising edge-triggered cell RAMB18E1 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Destination: okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[7]/R @@ -479,11 +479,11 @@ Slack (MET) : 11.037ns (required time - arrival time) Path Group: mmcm0_clk0 Path Type: Setup (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 9.150ns (logic 3.537ns (38.654%) route 5.613ns (61.346%)) + Data Path Delay: 9.105ns (logic 3.543ns (38.913%) route 5.562ns (61.087%)) Logic Levels: 5 (LUT2=1 LUT3=1 LUT5=1 LUT6=1 RAMD32=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.483ns = ( 19.607 - 21.090 ) - Source Clock Delay (SCD): -0.838ns = ( -0.577 - 0.260 ) + Destination Clock Delay (DCD): -1.487ns = ( 19.603 - 21.090 ) + Source Clock Delay (SCD): -0.842ns = ( -0.581 - 0.260 ) Clock Pessimism Removal (CPR): 0.577ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -502,24 +502,24 @@ Slack (MET) : 11.037ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.613 -0.577 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - RAMB18_X0Y19 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - ------------------------------------------------------------------- ------------------- - RAMB18_X0Y19 RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[7]) - 2.454 1.877 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DOADO[7] - net (fo=23, routed) 1.653 3.530 okHI/core0/core0/a0/pc0/upper_reg_banks/ADDRA3 - SLICE_X10Y46 RAMD32 (Prop_ramd32_RADR3_O) - 0.150 3.680 f okHI/core0/core0/a0/pc0/upper_reg_banks/RAMA/O - net (fo=3, routed) 1.101 4.781 okHI/core0/core0/a0/pc0/data_path_loop[4].output_data.sy_kk_mux_lut/I0 - SLICE_X11Y46 LUT5 (Prop_lut5_I0_O) 0.358 5.139 f okHI/core0/core0/a0/pc0/data_path_loop[4].output_data.sy_kk_mux_lut/LUT5/O - net (fo=20, routed) 0.881 6.020 okHI/core0/core0/a0/l91f05f26d7832afb9cfdc67ea9d72301[4] - SLICE_X9Y46 LUT6 (Prop_lut6_I0_O) 0.327 6.347 f okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2/O - net (fo=4, routed) 0.816 7.163 okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2_n_0 - SLICE_X7Y44 LUT3 (Prop_lut3_I0_O) 0.124 7.287 r okHI/core0/core0/ld307737e57d50d07f937891de086bf8e_i_3/O - net (fo=11, routed) 0.585 7.873 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_2_n_0 - SLICE_X8Y45 LUT2 (Prop_lut2_I1_O) 0.124 7.997 r okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1/O - net (fo=4, routed) 0.577 8.573 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1_n_0 - SLICE_X8Y45 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[7]/R + net (fo=1135, routed) 1.609 -0.581 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + RAMB18_X0Y15 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK + ------------------------------------------------------------------- ------------------- + RAMB18_X0Y15 RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[5]) + 2.454 1.873 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DOADO[5] + net (fo=14, routed) 2.053 3.926 okHI/core0/core0/a0/pc0/upper_reg_banks/ADDRC1 + SLICE_X10Y37 RAMD32 (Prop_ramd32_RADR1_O) + 0.153 4.079 f okHI/core0/core0/a0/pc0/upper_reg_banks/RAMC/O + net (fo=3, routed) 0.834 4.913 okHI/core0/core0/a0/pc0/data_path_loop[6].output_data.sy_kk_mux_lut/I0 + SLICE_X11Y35 LUT5 (Prop_lut5_I0_O) 0.356 5.269 f okHI/core0/core0/a0/pc0/data_path_loop[6].output_data.sy_kk_mux_lut/LUT5/O + net (fo=28, routed) 1.085 6.354 okHI/core0/core0/a0/l91f05f26d7832afb9cfdc67ea9d72301[6] + SLICE_X10Y35 LUT6 (Prop_lut6_I3_O) 0.332 6.686 f okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2/O + net (fo=4, routed) 0.631 7.317 okHI/core0/core0/l37dbd1aafb403530c46407234a8f7286[7]_i_2_n_0 + SLICE_X8Y35 LUT3 (Prop_lut3_I0_O) 0.124 7.441 r okHI/core0/core0/ld307737e57d50d07f937891de086bf8e_i_3/O + net (fo=11, routed) 0.311 7.752 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_2_n_0 + SLICE_X8Y35 LUT2 (Prop_lut2_I1_O) 0.124 7.876 r okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1/O + net (fo=4, routed) 0.648 8.524 okHI/core0/core0/leeb76b405f165a9b4ab0606f3ea0b3c4[7]_i_1_n_0 + SLICE_X8Y37 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[7]/R ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -532,30 +532,30 @@ Slack (MET) : 11.037ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.450 19.607 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X8Y45 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[7]/C - clock pessimism 0.577 20.184 - clock uncertainty -0.050 20.134 - SLICE_X8Y45 FDRE (Setup_fdre_C_R) -0.524 19.610 okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[7] + net (fo=1135, routed) 1.446 19.603 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X8Y37 FDRE r okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[7]/C + clock pessimism 0.577 20.180 + clock uncertainty -0.050 20.130 + SLICE_X8Y37 FDRE (Setup_fdre_C_R) -0.524 19.606 okHI/core0/core0/a0/leeb76b405f165a9b4ab0606f3ea0b3c4_reg[7] ------------------------------------------------------------------- - required time 19.610 - arrival time -8.573 + required time 19.606 + arrival time -8.524 ------------------------------------------------------------------- - slack 11.037 + slack 11.082 -Slack (MET) : 11.218ns (required time - arrival time) - Source: okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - (rising edge-triggered cell RAMB18E1 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/pc0/internal_reset_flop/D +Slack (MET) : 11.088ns (required time - arrival time) + Source: okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/C + (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: okHI/delays[15].fdreout0/D (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Setup (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 9.508ns (logic 4.277ns (44.984%) route 5.231ns (55.016%)) - Logic Levels: 6 (CARRY4=2 LUT5=1 LUT6=3) - Clock Path Skew: -0.082ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.483ns = ( 19.607 - 21.090 ) - Source Clock Delay (SCD): -0.838ns = ( -0.577 - 0.260 ) + Data Path Delay: 8.643ns (logic 1.464ns (16.938%) route 7.179ns (83.062%)) + Logic Levels: 6 (LUT2=2 LUT3=1 LUT4=2 LUT6=1) + Clock Path Skew: -0.007ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.399ns = ( 19.692 - 21.090 ) + Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -574,27 +574,24 @@ Slack (MET) : 11.218ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.613 -0.577 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - RAMB18_X0Y19 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - ------------------------------------------------------------------- ------------------- - RAMB18_X0Y19 RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[14]) - 2.454 1.877 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DOADO[14] - net (fo=22, routed) 2.724 4.601 okHI/core0/core0/a0/pc0/move_type_lut/I2 - SLICE_X12Y46 LUT6 (Prop_lut6_I2_O) 0.124 4.725 f okHI/core0/core0/a0/pc0/move_type_lut/LUT6/O - net (fo=4, routed) 0.916 5.641 okHI/core0/core0/a0/pc0/push_pop_lut/I2 - SLICE_X12Y46 LUT5 (Prop_lut5_I2_O) 0.150 5.791 f okHI/core0/core0/a0/pc0/push_pop_lut/LUT5/O - net (fo=5, routed) 0.615 6.406 okHI/core0/core0/a0/pc0/push_pop_lut_n_0 - SLICE_X13Y45 LUT6 (Prop_lut6_I1_O) 0.355 6.761 r okHI/core0/core0/a0/pc0/stack_loop[1].upper_stack.stack_pointer_lut/O - net (fo=1, routed) 0.000 6.761 okHI/core0/core0/a0/pc0/stack_loop[1].upper_stack.stack_pointer_lut_n_1 - SLICE_X13Y45 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 7.311 r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.stack_muxcy_CARRY4/CO[3] - net (fo=1, routed) 0.000 7.311 okHI/core0/core0/a0/pc0/stack_loop[3].upper_stack.stack_muxcy_n_0 - SLICE_X13Y46 CARRY4 (Prop_carry4_CI_CO[0]) - 0.271 7.582 r okHI/core0/core0/a0/pc0/stack_loop[4].upper_stack.stack_muxcy_CARRY4/CO[0] - net (fo=2, routed) 0.975 8.558 okHI/core0/core0/a0/pc0/reset_lut/I2 - SLICE_X15Y44 LUT6 (Prop_lut6_I2_O) 0.373 8.931 r okHI/core0/core0/a0/pc0/reset_lut/LUT6/O - net (fo=1, routed) 0.000 8.931 okHI/core0/core0/a0/pc0/reset_lut_n_1 - SLICE_X15Y44 FDRE r okHI/core0/core0/a0/pc0/internal_reset_flop/D + net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y27 FDRE r okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X3Y27 FDRE (Prop_fdre_C_Q) 0.456 -0.113 r okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/Q + net (fo=23, routed) 0.693 0.580 poa0/ok1[23] + SLICE_X5Y28 LUT2 (Prop_lut2_I1_O) 0.152 0.732 f poa0/ok2[15]_INST_0_i_1/O + net (fo=17, routed) 0.700 1.433 poa0/ok2[15]_INST_0_i_1_n_0 + SLICE_X5Y28 LUT4 (Prop_lut4_I2_O) 0.332 1.765 r poa0/ep_read_INST_0/O + net (fo=24, routed) 1.296 3.061 my_amp_pipe/ep_read + SLICE_X31Y25 LUT2 (Prop_lut2_I0_O) 0.124 3.185 r my_amp_pipe/read_counter[15]_i_3/O + net (fo=12, routed) 1.049 4.233 my_amp_pipe/read_counter[15]_i_3_n_0 + SLICE_X31Y22 LUT6 (Prop_lut6_I4_O) 0.124 4.357 r my_amp_pipe/poa0_i_1/O + net (fo=13, routed) 1.579 5.936 poa0/ep_datain[15] + SLICE_X5Y33 LUT4 (Prop_lut4_I3_O) 0.124 6.060 r poa0/ok2[15]_INST_0/O + net (fo=1, routed) 0.808 6.868 okHI/core0/core0/la1327f79b34bfbd40dd43a268139b612[15] + SLICE_X1Y33 LUT3 (Prop_lut3_I1_O) 0.152 7.020 r okHI/core0/core0/le78b033d3a3b15350c4085b407bdacef[15]_INST_0/O + net (fo=1, routed) 1.054 8.074 okHI/okCH[18] + OLOGIC_X0Y48 FDRE r okHI/delays[15].fdreout0/D ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -607,30 +604,30 @@ Slack (MET) : 11.218ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.450 19.607 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X15Y44 FDRE r okHI/core0/core0/a0/pc0/internal_reset_flop/C - clock pessimism 0.563 20.170 - clock uncertainty -0.050 20.120 - SLICE_X15Y44 FDRE (Setup_fdre_C_D) 0.029 20.149 okHI/core0/core0/a0/pc0/internal_reset_flop + net (fo=1135, routed) 1.535 19.692 okHI/ti_clk + OLOGIC_X0Y48 FDRE r okHI/delays[15].fdreout0/C + clock pessimism 0.563 20.255 + clock uncertainty -0.050 20.204 + OLOGIC_X0Y48 FDRE (Setup_fdre_C_D) -1.042 19.162 okHI/delays[15].fdreout0 ------------------------------------------------------------------- - required time 20.149 - arrival time -8.931 + required time 19.162 + arrival time -8.074 ------------------------------------------------------------------- - slack 11.218 + slack 11.088 -Slack (MET) : 11.238ns (required time - arrival time) - Source: okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - (rising edge-triggered cell RAMB18E1 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/pc0/run_flop/D +Slack (MET) : 11.410ns (required time - arrival time) + Source: okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/C + (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: okHI/delays[5].fdreout0/D (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Setup (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 9.534ns (logic 4.303ns (45.134%) route 5.231ns (54.866%)) - Logic Levels: 6 (CARRY4=2 LUT5=2 LUT6=2) - Clock Path Skew: -0.082ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.483ns = ( 19.607 - 21.090 ) - Source Clock Delay (SCD): -0.838ns = ( -0.577 - 0.260 ) + Data Path Delay: 8.322ns (logic 1.464ns (17.592%) route 6.858ns (82.408%)) + Logic Levels: 6 (LUT2=2 LUT3=1 LUT4=2 LUT6=1) + Clock Path Skew: -0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.404ns = ( 19.687 - 21.090 ) + Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -649,27 +646,24 @@ Slack (MET) : 11.238ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.613 -0.577 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - RAMB18_X0Y19 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - ------------------------------------------------------------------- ------------------- - RAMB18_X0Y19 RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[14]) - 2.454 1.877 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DOADO[14] - net (fo=22, routed) 2.724 4.601 okHI/core0/core0/a0/pc0/move_type_lut/I2 - SLICE_X12Y46 LUT6 (Prop_lut6_I2_O) 0.124 4.725 f okHI/core0/core0/a0/pc0/move_type_lut/LUT6/O - net (fo=4, routed) 0.916 5.641 okHI/core0/core0/a0/pc0/push_pop_lut/I2 - SLICE_X12Y46 LUT5 (Prop_lut5_I2_O) 0.150 5.791 f okHI/core0/core0/a0/pc0/push_pop_lut/LUT5/O - net (fo=5, routed) 0.615 6.406 okHI/core0/core0/a0/pc0/push_pop_lut_n_0 - SLICE_X13Y45 LUT6 (Prop_lut6_I1_O) 0.355 6.761 r okHI/core0/core0/a0/pc0/stack_loop[1].upper_stack.stack_pointer_lut/O - net (fo=1, routed) 0.000 6.761 okHI/core0/core0/a0/pc0/stack_loop[1].upper_stack.stack_pointer_lut_n_1 - SLICE_X13Y45 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 7.311 r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.stack_muxcy_CARRY4/CO[3] - net (fo=1, routed) 0.000 7.311 okHI/core0/core0/a0/pc0/stack_loop[3].upper_stack.stack_muxcy_n_0 - SLICE_X13Y46 CARRY4 (Prop_carry4_CI_CO[0]) - 0.271 7.582 f okHI/core0/core0/a0/pc0/stack_loop[4].upper_stack.stack_muxcy_CARRY4/CO[0] - net (fo=2, routed) 0.975 8.558 okHI/core0/core0/a0/pc0/reset_lut/I2 - SLICE_X15Y44 LUT5 (Prop_lut5_I2_O) 0.399 8.957 r okHI/core0/core0/a0/pc0/reset_lut/LUT5/O - net (fo=1, routed) 0.000 8.957 okHI/core0/core0/a0/pc0/D - SLICE_X15Y44 FDRE r okHI/core0/core0/a0/pc0/run_flop/D + net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y27 FDRE r okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X3Y27 FDRE (Prop_fdre_C_Q) 0.456 -0.113 r okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/Q + net (fo=23, routed) 0.693 0.580 poa0/ok1[23] + SLICE_X5Y28 LUT2 (Prop_lut2_I1_O) 0.152 0.732 f poa0/ok2[15]_INST_0_i_1/O + net (fo=17, routed) 0.700 1.433 poa0/ok2[15]_INST_0_i_1_n_0 + SLICE_X5Y28 LUT4 (Prop_lut4_I2_O) 0.332 1.765 r poa0/ep_read_INST_0/O + net (fo=24, routed) 1.296 3.061 my_amp_pipe/ep_read + SLICE_X31Y25 LUT2 (Prop_lut2_I0_O) 0.124 3.185 r my_amp_pipe/read_counter[15]_i_3/O + net (fo=12, routed) 0.927 4.112 my_amp_pipe/read_counter[15]_i_3_n_0 + SLICE_X33Y22 LUT6 (Prop_lut6_I4_O) 0.124 4.236 r my_amp_pipe/poa0_i_11/O + net (fo=13, routed) 1.803 6.039 poa0/ep_datain[5] + SLICE_X3Y33 LUT4 (Prop_lut4_I3_O) 0.124 6.163 r poa0/ok2[5]_INST_0/O + net (fo=1, routed) 0.789 6.953 okHI/core0/core0/la1327f79b34bfbd40dd43a268139b612[5] + SLICE_X1Y33 LUT3 (Prop_lut3_I0_O) 0.152 7.105 r okHI/core0/core0/le78b033d3a3b15350c4085b407bdacef[5]_INST_0/O + net (fo=1, routed) 0.648 7.753 okHI/okCH[8] + OLOGIC_X0Y35 FDRE r okHI/delays[5].fdreout0/D ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -682,30 +676,30 @@ Slack (MET) : 11.238ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.450 19.607 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X15Y44 FDRE r okHI/core0/core0/a0/pc0/run_flop/C - clock pessimism 0.563 20.170 - clock uncertainty -0.050 20.120 - SLICE_X15Y44 FDRE (Setup_fdre_C_D) 0.075 20.195 okHI/core0/core0/a0/pc0/run_flop + net (fo=1135, routed) 1.530 19.687 okHI/ti_clk + OLOGIC_X0Y35 FDRE r okHI/delays[5].fdreout0/C + clock pessimism 0.563 20.250 + clock uncertainty -0.050 20.199 + OLOGIC_X0Y35 FDRE (Setup_fdre_C_D) -1.036 19.163 okHI/delays[5].fdreout0 ------------------------------------------------------------------- - required time 20.195 - arrival time -8.957 + required time 19.163 + arrival time -7.753 ------------------------------------------------------------------- - slack 11.238 + slack 11.410 -Slack (MET) : 11.677ns (required time - arrival time) - Source: okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - (rising edge-triggered cell RAMB18E1 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/pc0/address_loop[9].pc_flop/D +Slack (MET) : 11.460ns (required time - arrival time) + Source: okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/C + (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: okHI/delays[12].fdreout0/D (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Setup (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 9.084ns (logic 4.292ns (47.250%) route 4.792ns (52.750%)) - Logic Levels: 6 (CARRY4=3 LUT5=2 LUT6=1) - Clock Path Skew: -0.081ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( 19.608 - 21.090 ) - Source Clock Delay (SCD): -0.838ns = ( -0.577 - 0.260 ) + Data Path Delay: 8.276ns (logic 1.430ns (17.279%) route 6.846ns (82.721%)) + Logic Levels: 6 (LUT2=2 LUT3=1 LUT4=2 LUT6=1) + Clock Path Skew: -0.008ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.400ns = ( 19.691 - 21.090 ) + Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -724,28 +718,24 @@ Slack (MET) : 11.677ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.613 -0.577 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - RAMB18_X0Y19 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - ------------------------------------------------------------------- ------------------- - RAMB18_X0Y19 RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[14]) - 2.454 1.877 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DOADO[14] - net (fo=22, routed) 2.724 4.601 okHI/core0/core0/a0/pc0/move_type_lut/I2 - SLICE_X12Y46 LUT5 (Prop_lut5_I2_O) 0.150 4.751 f okHI/core0/core0/a0/pc0/move_type_lut/LUT5/O - net (fo=2, routed) 0.848 5.599 okHI/core0/core0/a0/pc0/pc_mode1_lut/I1 - SLICE_X12Y46 LUT5 (Prop_lut5_I1_O) 0.377 5.976 r okHI/core0/core0/a0/pc0/pc_mode1_lut/LUT5/O - net (fo=13, routed) 1.219 7.195 okHI/core0/core0/a0/pc0/pc_mode1_lut_n_0 - SLICE_X11Y43 LUT6 (Prop_lut6_I3_O) 0.331 7.526 r okHI/core0/core0/a0/pc0/address_loop[0].lsb_pc.high_int_vector.pc_lut/O - net (fo=1, routed) 0.000 7.526 okHI/core0/core0/a0/pc0/address_loop[0].lsb_pc.high_int_vector.pc_lut_n_0 - SLICE_X11Y43 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 8.058 r okHI/core0/core0/a0/pc0/address_loop[0].lsb_pc.pc_muxcy_CARRY4/CO[3] - net (fo=1, routed) 0.000 8.058 okHI/core0/core0/a0/pc0/address_loop[3].upper_pc.mid_pc.pc_muxcy_n_0 - SLICE_X11Y44 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 8.172 r okHI/core0/core0/a0/pc0/address_loop[4].upper_pc.mid_pc.pc_muxcy_CARRY4/CO[3] - net (fo=1, routed) 0.000 8.172 okHI/core0/core0/a0/pc0/address_loop[7].upper_pc.mid_pc.pc_muxcy_n_0 - SLICE_X11Y45 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 8.506 r okHI/core0/core0/a0/pc0/address_loop[8].upper_pc.mid_pc.pc_muxcy_CARRY4/O[1] - net (fo=1, routed) 0.000 8.506 okHI/core0/core0/a0/pc0/address_loop[9].upper_pc.pc_xorcy_n_0 - SLICE_X11Y45 FDRE r okHI/core0/core0/a0/pc0/address_loop[9].pc_flop/D + net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y27 FDRE r okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X3Y27 FDRE (Prop_fdre_C_Q) 0.456 -0.113 r okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/Q + net (fo=23, routed) 0.693 0.580 poa0/ok1[23] + SLICE_X5Y28 LUT2 (Prop_lut2_I1_O) 0.152 0.732 f poa0/ok2[15]_INST_0_i_1/O + net (fo=17, routed) 0.700 1.433 poa0/ok2[15]_INST_0_i_1_n_0 + SLICE_X5Y28 LUT4 (Prop_lut4_I2_O) 0.332 1.765 r poa0/ep_read_INST_0/O + net (fo=24, routed) 1.296 3.061 my_amp_pipe/ep_read + SLICE_X31Y25 LUT2 (Prop_lut2_I0_O) 0.124 3.185 r my_amp_pipe/read_counter[15]_i_3/O + net (fo=12, routed) 1.191 4.375 my_amp_pipe/read_counter[15]_i_3_n_0 + SLICE_X34Y23 LUT6 (Prop_lut6_I4_O) 0.124 4.499 r my_amp_pipe/poa0_i_4/O + net (fo=13, routed) 1.497 5.996 poa0/ep_datain[12] + SLICE_X3Y31 LUT4 (Prop_lut4_I3_O) 0.124 6.120 r poa0/ok2[12]_INST_0/O + net (fo=1, routed) 0.423 6.543 okHI/core0/core0/la1327f79b34bfbd40dd43a268139b612[12] + SLICE_X0Y31 LUT3 (Prop_lut3_I1_O) 0.118 6.661 r okHI/core0/core0/le78b033d3a3b15350c4085b407bdacef[12]_INST_0/O + net (fo=1, routed) 1.046 7.707 okHI/okCH[15] + OLOGIC_X0Y45 FDRE r okHI/delays[12].fdreout0/D ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -758,30 +748,30 @@ Slack (MET) : 11.677ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X11Y45 FDRE r okHI/core0/core0/a0/pc0/address_loop[9].pc_flop/C - clock pessimism 0.563 20.171 - clock uncertainty -0.050 20.121 - SLICE_X11Y45 FDRE (Setup_fdre_C_D) 0.062 20.183 okHI/core0/core0/a0/pc0/address_loop[9].pc_flop + net (fo=1135, routed) 1.534 19.691 okHI/ti_clk + OLOGIC_X0Y45 FDRE r okHI/delays[12].fdreout0/C + clock pessimism 0.563 20.254 + clock uncertainty -0.050 20.203 + OLOGIC_X0Y45 FDRE (Setup_fdre_C_D) -1.036 19.167 okHI/delays[12].fdreout0 ------------------------------------------------------------------- - required time 20.183 - arrival time -8.506 + required time 19.167 + arrival time -7.707 ------------------------------------------------------------------- - slack 11.677 + slack 11.460 -Slack (MET) : 11.698ns (required time - arrival time) - Source: okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - (rising edge-triggered cell RAMB18E1 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/pc0/address_loop[11].pc_flop/D +Slack (MET) : 11.531ns (required time - arrival time) + Source: okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/C + (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: okHI/delays[3].fdreout0/D (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Setup (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 9.063ns (logic 4.271ns (47.128%) route 4.792ns (52.872%)) - Logic Levels: 6 (CARRY4=3 LUT5=2 LUT6=1) - Clock Path Skew: -0.081ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( 19.608 - 21.090 ) - Source Clock Delay (SCD): -0.838ns = ( -0.577 - 0.260 ) + Data Path Delay: 8.194ns (logic 1.464ns (17.867%) route 6.730ns (82.133%)) + Logic Levels: 6 (LUT2=1 LUT3=2 LUT4=2 LUT6=1) + Clock Path Skew: -0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.405ns = ( 19.686 - 21.090 ) + Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -800,28 +790,24 @@ Slack (MET) : 11.698ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.613 -0.577 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - RAMB18_X0Y19 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - ------------------------------------------------------------------- ------------------- - RAMB18_X0Y19 RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[14]) - 2.454 1.877 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DOADO[14] - net (fo=22, routed) 2.724 4.601 okHI/core0/core0/a0/pc0/move_type_lut/I2 - SLICE_X12Y46 LUT5 (Prop_lut5_I2_O) 0.150 4.751 f okHI/core0/core0/a0/pc0/move_type_lut/LUT5/O - net (fo=2, routed) 0.848 5.599 okHI/core0/core0/a0/pc0/pc_mode1_lut/I1 - SLICE_X12Y46 LUT5 (Prop_lut5_I1_O) 0.377 5.976 r okHI/core0/core0/a0/pc0/pc_mode1_lut/LUT5/O - net (fo=13, routed) 1.219 7.195 okHI/core0/core0/a0/pc0/pc_mode1_lut_n_0 - SLICE_X11Y43 LUT6 (Prop_lut6_I3_O) 0.331 7.526 r okHI/core0/core0/a0/pc0/address_loop[0].lsb_pc.high_int_vector.pc_lut/O - net (fo=1, routed) 0.000 7.526 okHI/core0/core0/a0/pc0/address_loop[0].lsb_pc.high_int_vector.pc_lut_n_0 - SLICE_X11Y43 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 8.058 r okHI/core0/core0/a0/pc0/address_loop[0].lsb_pc.pc_muxcy_CARRY4/CO[3] - net (fo=1, routed) 0.000 8.058 okHI/core0/core0/a0/pc0/address_loop[3].upper_pc.mid_pc.pc_muxcy_n_0 - SLICE_X11Y44 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 8.172 r okHI/core0/core0/a0/pc0/address_loop[4].upper_pc.mid_pc.pc_muxcy_CARRY4/CO[3] - net (fo=1, routed) 0.000 8.172 okHI/core0/core0/a0/pc0/address_loop[7].upper_pc.mid_pc.pc_muxcy_n_0 - SLICE_X11Y45 CARRY4 (Prop_carry4_CI_O[3]) - 0.313 8.485 r okHI/core0/core0/a0/pc0/address_loop[8].upper_pc.mid_pc.pc_muxcy_CARRY4/O[3] - net (fo=1, routed) 0.000 8.485 okHI/core0/core0/a0/pc0/address_loop[11].upper_pc.pc_xorcy_n_0 - SLICE_X11Y45 FDRE r okHI/core0/core0/a0/pc0/address_loop[11].pc_flop/D + net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y27 FDRE r okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X3Y27 FDRE (Prop_fdre_C_Q) 0.456 -0.113 r okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/Q + net (fo=23, routed) 0.693 0.580 poa0/ok1[23] + SLICE_X5Y28 LUT2 (Prop_lut2_I1_O) 0.152 0.732 f poa0/ok2[15]_INST_0_i_1/O + net (fo=17, routed) 0.700 1.433 poa0/ok2[15]_INST_0_i_1_n_0 + SLICE_X5Y28 LUT4 (Prop_lut4_I2_O) 0.332 1.765 r poa0/ep_read_INST_0/O + net (fo=24, routed) 1.445 3.210 my_amp_pipe/ep_read + SLICE_X31Y25 LUT3 (Prop_lut3_I2_O) 0.124 3.334 r my_amp_pipe/poa0_i_28/O + net (fo=5, routed) 0.752 4.085 my_amp_pipe/poa0_i_28_n_0 + SLICE_X34Y21 LUT6 (Prop_lut6_I3_O) 0.124 4.209 r my_amp_pipe/poa0_i_13/O + net (fo=13, routed) 1.834 6.043 poa0/ep_datain[3] + SLICE_X3Y32 LUT4 (Prop_lut4_I3_O) 0.124 6.167 r poa0/ok2[3]_INST_0/O + net (fo=1, routed) 0.792 6.959 okHI/core0/core0/la1327f79b34bfbd40dd43a268139b612[3] + SLICE_X0Y32 LUT3 (Prop_lut3_I1_O) 0.152 7.111 r okHI/core0/core0/le78b033d3a3b15350c4085b407bdacef[3]_INST_0/O + net (fo=1, routed) 0.514 7.625 okHI/okCH[6] + OLOGIC_X0Y33 FDRE r okHI/delays[3].fdreout0/D ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -834,30 +820,30 @@ Slack (MET) : 11.698ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X11Y45 FDRE r okHI/core0/core0/a0/pc0/address_loop[11].pc_flop/C - clock pessimism 0.563 20.171 - clock uncertainty -0.050 20.121 - SLICE_X11Y45 FDRE (Setup_fdre_C_D) 0.062 20.183 okHI/core0/core0/a0/pc0/address_loop[11].pc_flop + net (fo=1135, routed) 1.529 19.686 okHI/ti_clk + OLOGIC_X0Y33 FDRE r okHI/delays[3].fdreout0/C + clock pessimism 0.563 20.249 + clock uncertainty -0.050 20.198 + OLOGIC_X0Y33 FDRE (Setup_fdre_C_D) -1.042 19.156 okHI/delays[3].fdreout0 ------------------------------------------------------------------- - required time 20.183 - arrival time -8.485 + required time 19.156 + arrival time -7.625 ------------------------------------------------------------------- - slack 11.698 + slack 11.531 -Slack (MET) : 11.772ns (required time - arrival time) - Source: okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - (rising edge-triggered cell RAMB18E1 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/pc0/address_loop[10].pc_flop/D +Slack (MET) : 11.657ns (required time - arrival time) + Source: okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/C + (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: okHI/delays[10].fdreout0/D (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Setup (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 8.989ns (logic 4.197ns (46.692%) route 4.792ns (53.308%)) - Logic Levels: 6 (CARRY4=3 LUT5=2 LUT6=1) - Clock Path Skew: -0.081ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( 19.608 - 21.090 ) - Source Clock Delay (SCD): -0.838ns = ( -0.577 - 0.260 ) + Data Path Delay: 8.280ns (logic 1.436ns (17.342%) route 6.844ns (82.658%)) + Logic Levels: 6 (LUT2=2 LUT3=1 LUT4=2 LUT6=1) + Clock Path Skew: -0.009ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.401ns = ( 19.690 - 21.090 ) + Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -876,28 +862,24 @@ Slack (MET) : 11.772ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.613 -0.577 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - RAMB18_X0Y19 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - ------------------------------------------------------------------- ------------------- - RAMB18_X0Y19 RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[14]) - 2.454 1.877 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DOADO[14] - net (fo=22, routed) 2.724 4.601 okHI/core0/core0/a0/pc0/move_type_lut/I2 - SLICE_X12Y46 LUT5 (Prop_lut5_I2_O) 0.150 4.751 f okHI/core0/core0/a0/pc0/move_type_lut/LUT5/O - net (fo=2, routed) 0.848 5.599 okHI/core0/core0/a0/pc0/pc_mode1_lut/I1 - SLICE_X12Y46 LUT5 (Prop_lut5_I1_O) 0.377 5.976 r okHI/core0/core0/a0/pc0/pc_mode1_lut/LUT5/O - net (fo=13, routed) 1.219 7.195 okHI/core0/core0/a0/pc0/pc_mode1_lut_n_0 - SLICE_X11Y43 LUT6 (Prop_lut6_I3_O) 0.331 7.526 r okHI/core0/core0/a0/pc0/address_loop[0].lsb_pc.high_int_vector.pc_lut/O - net (fo=1, routed) 0.000 7.526 okHI/core0/core0/a0/pc0/address_loop[0].lsb_pc.high_int_vector.pc_lut_n_0 - SLICE_X11Y43 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 8.058 r okHI/core0/core0/a0/pc0/address_loop[0].lsb_pc.pc_muxcy_CARRY4/CO[3] - net (fo=1, routed) 0.000 8.058 okHI/core0/core0/a0/pc0/address_loop[3].upper_pc.mid_pc.pc_muxcy_n_0 - SLICE_X11Y44 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 8.172 r okHI/core0/core0/a0/pc0/address_loop[4].upper_pc.mid_pc.pc_muxcy_CARRY4/CO[3] - net (fo=1, routed) 0.000 8.172 okHI/core0/core0/a0/pc0/address_loop[7].upper_pc.mid_pc.pc_muxcy_n_0 - SLICE_X11Y45 CARRY4 (Prop_carry4_CI_O[2]) - 0.239 8.411 r okHI/core0/core0/a0/pc0/address_loop[8].upper_pc.mid_pc.pc_muxcy_CARRY4/O[2] - net (fo=1, routed) 0.000 8.411 okHI/core0/core0/a0/pc0/address_loop[10].upper_pc.pc_xorcy_n_0 - SLICE_X11Y45 FDRE r okHI/core0/core0/a0/pc0/address_loop[10].pc_flop/D + net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y27 FDRE r okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X3Y27 FDRE (Prop_fdre_C_Q) 0.456 -0.113 r okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/Q + net (fo=23, routed) 0.693 0.580 poa0/ok1[23] + SLICE_X5Y28 LUT2 (Prop_lut2_I1_O) 0.152 0.732 f poa0/ok2[15]_INST_0_i_1/O + net (fo=17, routed) 0.700 1.433 poa0/ok2[15]_INST_0_i_1_n_0 + SLICE_X5Y28 LUT4 (Prop_lut4_I2_O) 0.332 1.765 r poa0/ep_read_INST_0/O + net (fo=24, routed) 1.296 3.061 my_amp_pipe/ep_read + SLICE_X31Y25 LUT2 (Prop_lut2_I0_O) 0.124 3.185 r my_amp_pipe/read_counter[15]_i_3/O + net (fo=12, routed) 0.805 3.990 my_amp_pipe/read_counter[15]_i_3_n_0 + SLICE_X33Y23 LUT6 (Prop_lut6_I5_O) 0.124 4.114 r my_amp_pipe/poa0_i_24/O + net (fo=13, routed) 1.839 5.953 poa0/ep_datain[10] + SLICE_X1Y31 LUT4 (Prop_lut4_I3_O) 0.124 6.077 r poa0/ok2[10]_INST_0/O + net (fo=1, routed) 0.659 6.735 okHI/core0/core0/la1327f79b34bfbd40dd43a268139b612[10] + SLICE_X0Y31 LUT3 (Prop_lut3_I0_O) 0.124 6.859 r okHI/core0/core0/le78b033d3a3b15350c4085b407bdacef[10]_INST_0/O + net (fo=1, routed) 0.852 7.712 okHI/okCH[13] + OLOGIC_X0Y41 FDRE r okHI/delays[10].fdreout0/D ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -910,30 +892,30 @@ Slack (MET) : 11.772ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X11Y45 FDRE r okHI/core0/core0/a0/pc0/address_loop[10].pc_flop/C - clock pessimism 0.563 20.171 - clock uncertainty -0.050 20.121 - SLICE_X11Y45 FDRE (Setup_fdre_C_D) 0.062 20.183 okHI/core0/core0/a0/pc0/address_loop[10].pc_flop + net (fo=1135, routed) 1.533 19.690 okHI/ti_clk + OLOGIC_X0Y41 FDRE r okHI/delays[10].fdreout0/C + clock pessimism 0.563 20.253 + clock uncertainty -0.050 20.202 + OLOGIC_X0Y41 FDRE (Setup_fdre_C_D) -0.834 19.368 okHI/delays[10].fdreout0 ------------------------------------------------------------------- - required time 20.183 - arrival time -8.411 + required time 19.368 + arrival time -7.712 ------------------------------------------------------------------- - slack 11.772 + slack 11.657 -Slack (MET) : 11.788ns (required time - arrival time) - Source: okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - (rising edge-triggered cell RAMB18E1 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/pc0/address_loop[8].pc_flop/D +Slack (MET) : 11.694ns (required time - arrival time) + Source: okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/C + (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: okHI/delays[9].fdreout0/D (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Setup (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 8.973ns (logic 4.181ns (46.597%) route 4.792ns (53.403%)) - Logic Levels: 6 (CARRY4=3 LUT5=2 LUT6=1) - Clock Path Skew: -0.081ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( 19.608 - 21.090 ) - Source Clock Delay (SCD): -0.838ns = ( -0.577 - 0.260 ) + Data Path Delay: 8.039ns (logic 1.462ns (18.187%) route 6.577ns (81.813%)) + Logic Levels: 6 (LUT2=2 LUT3=1 LUT4=2 LUT6=1) + Clock Path Skew: -0.009ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.401ns = ( 19.690 - 21.090 ) + Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -952,28 +934,24 @@ Slack (MET) : 11.788ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.613 -0.577 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - RAMB18_X0Y19 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK - ------------------------------------------------------------------- ------------------- - RAMB18_X0Y19 RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[14]) - 2.454 1.877 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DOADO[14] - net (fo=22, routed) 2.724 4.601 okHI/core0/core0/a0/pc0/move_type_lut/I2 - SLICE_X12Y46 LUT5 (Prop_lut5_I2_O) 0.150 4.751 f okHI/core0/core0/a0/pc0/move_type_lut/LUT5/O - net (fo=2, routed) 0.848 5.599 okHI/core0/core0/a0/pc0/pc_mode1_lut/I1 - SLICE_X12Y46 LUT5 (Prop_lut5_I1_O) 0.377 5.976 r okHI/core0/core0/a0/pc0/pc_mode1_lut/LUT5/O - net (fo=13, routed) 1.219 7.195 okHI/core0/core0/a0/pc0/pc_mode1_lut_n_0 - SLICE_X11Y43 LUT6 (Prop_lut6_I3_O) 0.331 7.526 r okHI/core0/core0/a0/pc0/address_loop[0].lsb_pc.high_int_vector.pc_lut/O - net (fo=1, routed) 0.000 7.526 okHI/core0/core0/a0/pc0/address_loop[0].lsb_pc.high_int_vector.pc_lut_n_0 - SLICE_X11Y43 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 8.058 r okHI/core0/core0/a0/pc0/address_loop[0].lsb_pc.pc_muxcy_CARRY4/CO[3] - net (fo=1, routed) 0.000 8.058 okHI/core0/core0/a0/pc0/address_loop[3].upper_pc.mid_pc.pc_muxcy_n_0 - SLICE_X11Y44 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 8.172 r okHI/core0/core0/a0/pc0/address_loop[4].upper_pc.mid_pc.pc_muxcy_CARRY4/CO[3] - net (fo=1, routed) 0.000 8.172 okHI/core0/core0/a0/pc0/address_loop[7].upper_pc.mid_pc.pc_muxcy_n_0 - SLICE_X11Y45 CARRY4 (Prop_carry4_CI_O[0]) - 0.223 8.395 r okHI/core0/core0/a0/pc0/address_loop[8].upper_pc.mid_pc.pc_muxcy_CARRY4/O[0] - net (fo=1, routed) 0.000 8.395 okHI/core0/core0/a0/pc0/address_loop[8].upper_pc.pc_xorcy_n_0 - SLICE_X11Y45 FDRE r okHI/core0/core0/a0/pc0/address_loop[8].pc_flop/D + net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y27 FDRE r okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X3Y27 FDRE (Prop_fdre_C_Q) 0.456 -0.113 r okHI/core0/core0/l9f43dc9d3787a4c1395542a254aee157_reg[7]/Q + net (fo=23, routed) 0.693 0.580 poa0/ok1[23] + SLICE_X5Y28 LUT2 (Prop_lut2_I1_O) 0.152 0.732 f poa0/ok2[15]_INST_0_i_1/O + net (fo=17, routed) 0.700 1.433 poa0/ok2[15]_INST_0_i_1_n_0 + SLICE_X5Y28 LUT4 (Prop_lut4_I2_O) 0.332 1.765 r poa0/ep_read_INST_0/O + net (fo=24, routed) 1.296 3.061 my_amp_pipe/ep_read + SLICE_X31Y25 LUT2 (Prop_lut2_I0_O) 0.124 3.185 r my_amp_pipe/read_counter[15]_i_3/O + net (fo=12, routed) 0.840 4.024 my_amp_pipe/read_counter[15]_i_3_n_0 + SLICE_X31Y22 LUT6 (Prop_lut6_I4_O) 0.124 4.148 r my_amp_pipe/poa0_i_7/O + net (fo=13, routed) 1.522 5.670 poa0/ep_datain[9] + SLICE_X2Y32 LUT4 (Prop_lut4_I3_O) 0.124 5.794 r poa0/ok2[9]_INST_0/O + net (fo=1, routed) 0.680 6.474 okHI/core0/core0/la1327f79b34bfbd40dd43a268139b612[9] + SLICE_X2Y32 LUT3 (Prop_lut3_I0_O) 0.150 6.624 r okHI/core0/core0/le78b033d3a3b15350c4085b407bdacef[9]_INST_0/O + net (fo=1, routed) 0.846 7.470 okHI/okCH[12] + OLOGIC_X0Y40 FDRE r okHI/delays[9].fdreout0/D ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -986,16 +964,16 @@ Slack (MET) : 11.788ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X11Y45 FDRE r okHI/core0/core0/a0/pc0/address_loop[8].pc_flop/C - clock pessimism 0.563 20.171 - clock uncertainty -0.050 20.121 - SLICE_X11Y45 FDRE (Setup_fdre_C_D) 0.062 20.183 okHI/core0/core0/a0/pc0/address_loop[8].pc_flop + net (fo=1135, routed) 1.533 19.690 okHI/ti_clk + OLOGIC_X0Y40 FDRE r okHI/delays[9].fdreout0/C + clock pessimism 0.563 20.253 + clock uncertainty -0.050 20.202 + OLOGIC_X0Y40 FDRE (Setup_fdre_C_D) -1.038 19.164 okHI/delays[9].fdreout0 ------------------------------------------------------------------- - required time 20.183 - arrival time -8.395 + required time 19.164 + arrival time -7.470 ------------------------------------------------------------------- - slack 11.788 + slack 11.694 @@ -1003,20 +981,20 @@ Slack (MET) : 11.788ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.056ns (arrival time - required time) - Source: okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[10]/C - (rising edge-triggered cell FDCE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/des0/lee850ccdc8e3a4cfe18e16eca8aa053c_reg[18]/D +Slack (MET) : 0.121ns (arrival time - required time) + Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/D + (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.444ns (logic 0.209ns (47.094%) route 0.235ns (52.906%)) - Logic Levels: 1 (LUT4=1) - Clock Path Skew: 0.268ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.793ns = ( -0.533 - 0.260 ) - Source Clock Delay (SCD): -0.554ns = ( -0.294 - 0.260 ) - Clock Pessimism Removal (CPR): -0.507ns + Data Path Delay: 0.254ns (logic 0.186ns (73.141%) route 0.068ns (26.859%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.769ns = ( -0.509 - 0.260 ) + Source Clock Delay (SCD): -0.531ns = ( -0.271 - 0.260 ) + Clock Pessimism Removal (CPR): -0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1030,14 +1008,14 @@ Slack (MET) : 0.056ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.567 -0.294 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X10Y49 FDCE r okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[10]/C + net (fo=1135, routed) 0.590 -0.271 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X3Y33 FDRE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X10Y49 FDCE (Prop_fdce_C_Q) 0.164 -0.130 r okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[10]/Q - net (fo=2, routed) 0.235 0.105 okHI/core0/core0/le5e2e6110dd7478b8ed0143f21b04d30[10] - SLICE_X10Y51 LUT4 (Prop_lut4_I0_O) 0.045 0.150 r okHI/core0/core0/lee850ccdc8e3a4cfe18e16eca8aa053c[18]_i_1/O - net (fo=2, routed) 0.000 0.150 okHI/core0/core0/a0/lc51cc989dfe3deb69373fc00081012cc[10] - SLICE_X10Y51 FDRE r okHI/core0/core0/a0/des0/lee850ccdc8e3a4cfe18e16eca8aa053c_reg[18]/D + SLICE_X3Y33 FDRE (Prop_fdre_C_Q) 0.141 -0.130 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg/Q + net (fo=2, routed) 0.068 -0.062 okHI/core0/core0/a0/cb0/U0/wr_rst_asreg_d1 + SLICE_X2Y33 LUT2 (Prop_lut2_I1_O) 0.045 -0.017 r okHI/core0/core0/a0/cb0/U0/ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1/O + net (fo=1, routed) 0.000 -0.017 okHI/core0/core0/a0/cb0/U0/ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 + SLICE_X2Y33 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/D ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -1050,30 +1028,30 @@ Slack (MET) : 0.056ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.834 -0.533 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X10Y51 FDRE r okHI/core0/core0/a0/des0/lee850ccdc8e3a4cfe18e16eca8aa053c_reg[18]/C - clock pessimism 0.507 -0.026 - SLICE_X10Y51 FDRE (Hold_fdre_C_D) 0.120 0.094 okHI/core0/core0/a0/des0/lee850ccdc8e3a4cfe18e16eca8aa053c_reg[18] + net (fo=1135, routed) 0.859 -0.509 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X2Y33 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/C + clock pessimism 0.251 -0.258 + SLICE_X2Y33 FDPE (Hold_fdpe_C_D) 0.120 -0.138 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ------------------------------------------------------------------- - required time -0.094 - arrival time 0.150 + required time 0.138 + arrival time -0.017 ------------------------------------------------------------------- - slack 0.056 + slack 0.121 -Slack (MET) : 0.059ns (arrival time - required time) - Source: okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C - (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/pc0/stack_ram_high/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) +Slack (MET) : 0.122ns (arrival time - required time) + Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/C + (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/D + (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.382ns (logic 0.141ns (36.959%) route 0.241ns (63.041%)) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.792ns = ( -0.532 - 0.260 ) - Source Clock Delay (SCD): -0.555ns = ( -0.295 - 0.260 ) - Clock Pessimism Removal (CPR): -0.250ns + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.770ns = ( -0.510 - 0.260 ) + Source Clock Delay (SCD): -0.532ns = ( -0.272 - 0.260 ) + Clock Pessimism Removal (CPR): -0.238ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1087,12 +1065,12 @@ Slack (MET) : 0.059ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.566 -0.295 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y45 FDRE r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C + net (fo=1135, routed) 0.589 -0.272 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X5Y34 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.154 r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/Q - net (fo=30, routed) 0.241 0.086 okHI/core0/core0/a0/pc0/stack_ram_high/ADDRD0 - SLICE_X12Y45 RAMD32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMA/WADR0 + SLICE_X5Y34 FDPE (Prop_fdpe_C_Q) 0.141 -0.131 r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/Q + net (fo=1, routed) 0.056 -0.075 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_rd_reg1 + SLICE_X5Y34 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/D ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -1105,31 +1083,30 @@ Slack (MET) : 0.059ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.836 -0.532 okHI/core0/core0/a0/pc0/stack_ram_high/WCLK - SLICE_X12Y45 RAMD32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMA/CLK - clock pessimism 0.250 -0.282 - SLICE_X12Y45 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 0.028 okHI/core0/core0/a0/pc0/stack_ram_high/RAMA + net (fo=1135, routed) 0.858 -0.510 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X5Y34 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/C + clock pessimism 0.238 -0.272 + SLICE_X5Y34 FDPE (Hold_fdpe_C_D) 0.075 -0.197 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg ------------------------------------------------------------------- - required time -0.028 - arrival time 0.086 + required time 0.197 + arrival time -0.075 ------------------------------------------------------------------- - slack 0.059 + slack 0.122 -Slack (MET) : 0.059ns (arrival time - required time) - Source: okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C - (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/pc0/stack_ram_high/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) +Slack (MET) : 0.126ns (arrival time - required time) + Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg1_reg/C + (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/D + (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.382ns (logic 0.141ns (36.959%) route 0.241ns (63.041%)) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.792ns = ( -0.532 - 0.260 ) - Source Clock Delay (SCD): -0.555ns = ( -0.295 - 0.260 ) - Clock Pessimism Removal (CPR): -0.250ns + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.770ns = ( -0.510 - 0.260 ) + Source Clock Delay (SCD): -0.532ns = ( -0.272 - 0.260 ) + Clock Pessimism Removal (CPR): -0.238ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1143,12 +1120,12 @@ Slack (MET) : 0.059ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.566 -0.295 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y45 FDRE r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C + net (fo=1135, routed) 0.589 -0.272 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X5Y34 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.154 r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/Q - net (fo=30, routed) 0.241 0.086 okHI/core0/core0/a0/pc0/stack_ram_high/ADDRD0 - SLICE_X12Y45 RAMD32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMA_D1/WADR0 + SLICE_X5Y34 FDPE (Prop_fdpe_C_Q) 0.141 -0.131 r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg1_reg/Q + net (fo=1, routed) 0.056 -0.075 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_wr_reg1 + SLICE_X5Y34 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/D ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -1161,31 +1138,30 @@ Slack (MET) : 0.059ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.836 -0.532 okHI/core0/core0/a0/pc0/stack_ram_high/WCLK - SLICE_X12Y45 RAMD32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMA_D1/CLK - clock pessimism 0.250 -0.282 - SLICE_X12Y45 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 0.028 okHI/core0/core0/a0/pc0/stack_ram_high/RAMA_D1 + net (fo=1135, routed) 0.858 -0.510 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X5Y34 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C + clock pessimism 0.238 -0.272 + SLICE_X5Y34 FDPE (Hold_fdpe_C_D) 0.071 -0.201 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg ------------------------------------------------------------------- - required time -0.028 - arrival time 0.086 + required time 0.201 + arrival time -0.075 ------------------------------------------------------------------- - slack 0.059 + slack 0.126 -Slack (MET) : 0.059ns (arrival time - required time) - Source: okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C +Slack (MET) : 0.127ns (arrival time - required time) + Source: okHI/core0/core0/a0/pc0/address_loop[6].pc_flop/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/pc0/stack_ram_high/RAMB/WADR0 + Destination: okHI/core0/core0/a0/pc0/stack_ram_high/RAMB/I (rising edge-triggered cell RAMD32 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.382ns (logic 0.141ns (36.959%) route 0.241ns (63.041%)) + Data Path Delay: 0.288ns (logic 0.164ns (56.884%) route 0.124ns (43.116%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.792ns = ( -0.532 - 0.260 ) - Source Clock Delay (SCD): -0.555ns = ( -0.295 - 0.260 ) - Clock Pessimism Removal (CPR): -0.250ns + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.797ns = ( -0.537 - 0.260 ) + Source Clock Delay (SCD): -0.559ns = ( -0.299 - 0.260 ) + Clock Pessimism Removal (CPR): -0.253ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1199,12 +1175,12 @@ Slack (MET) : 0.059ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.566 -0.295 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y45 FDRE r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C + net (fo=1135, routed) 0.562 -0.299 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X12Y36 FDRE r okHI/core0/core0/a0/pc0/address_loop[6].pc_flop/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.154 r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/Q - net (fo=30, routed) 0.241 0.086 okHI/core0/core0/a0/pc0/stack_ram_high/ADDRD0 - SLICE_X12Y45 RAMD32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMB/WADR0 + SLICE_X12Y36 FDRE (Prop_fdre_C_Q) 0.164 -0.135 r okHI/core0/core0/a0/pc0/address_loop[6].pc_flop/Q + net (fo=3, routed) 0.124 -0.011 okHI/core0/core0/a0/pc0/stack_ram_high/DIB0 + SLICE_X14Y36 RAMD32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMB/I ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -1217,31 +1193,31 @@ Slack (MET) : 0.059ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.836 -0.532 okHI/core0/core0/a0/pc0/stack_ram_high/WCLK - SLICE_X12Y45 RAMD32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMB/CLK - clock pessimism 0.250 -0.282 - SLICE_X12Y45 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 0.028 okHI/core0/core0/a0/pc0/stack_ram_high/RAMB + net (fo=1135, routed) 0.831 -0.537 okHI/core0/core0/a0/pc0/stack_ram_high/WCLK + SLICE_X14Y36 RAMD32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMB/CLK + clock pessimism 0.253 -0.284 + SLICE_X14Y36 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.138 okHI/core0/core0/a0/pc0/stack_ram_high/RAMB ------------------------------------------------------------------- - required time -0.028 - arrival time 0.086 + required time 0.138 + arrival time -0.011 ------------------------------------------------------------------- - slack 0.059 + slack 0.127 -Slack (MET) : 0.059ns (arrival time - required time) - Source: okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C +Slack (MET) : 0.134ns (arrival time - required time) + Source: okHI/core0/core0/a0/pc0/address_loop[2].pc_flop/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/pc0/stack_ram_high/RAMB_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: okHI/core0/core0/a0/pc0/stack_ram_low/RAMD/I + (rising edge-triggered cell RAMS32 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.382ns (logic 0.141ns (36.959%) route 0.241ns (63.041%)) + Data Path Delay: 0.293ns (logic 0.164ns (56.067%) route 0.129ns (43.933%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.792ns = ( -0.532 - 0.260 ) - Source Clock Delay (SCD): -0.555ns = ( -0.295 - 0.260 ) - Clock Pessimism Removal (CPR): -0.250ns + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.797ns = ( -0.537 - 0.260 ) + Source Clock Delay (SCD): -0.559ns = ( -0.299 - 0.260 ) + Clock Pessimism Removal (CPR): -0.253ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1255,12 +1231,12 @@ Slack (MET) : 0.059ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.566 -0.295 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y45 FDRE r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C + net (fo=1135, routed) 0.562 -0.299 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X12Y35 FDRE r okHI/core0/core0/a0/pc0/address_loop[2].pc_flop/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.154 r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/Q - net (fo=30, routed) 0.241 0.086 okHI/core0/core0/a0/pc0/stack_ram_high/ADDRD0 - SLICE_X12Y45 RAMD32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMB_D1/WADR0 + SLICE_X12Y35 FDRE (Prop_fdre_C_Q) 0.164 -0.135 r okHI/core0/core0/a0/pc0/address_loop[2].pc_flop/Q + net (fo=3, routed) 0.129 -0.007 okHI/core0/core0/a0/pc0/stack_ram_low/DID0 + SLICE_X14Y35 RAMS32 r okHI/core0/core0/a0/pc0/stack_ram_low/RAMD/I ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -1273,31 +1249,31 @@ Slack (MET) : 0.059ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.836 -0.532 okHI/core0/core0/a0/pc0/stack_ram_high/WCLK - SLICE_X12Y45 RAMD32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMB_D1/CLK - clock pessimism 0.250 -0.282 - SLICE_X12Y45 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 0.028 okHI/core0/core0/a0/pc0/stack_ram_high/RAMB_D1 + net (fo=1135, routed) 0.831 -0.537 okHI/core0/core0/a0/pc0/stack_ram_low/WCLK + SLICE_X14Y35 RAMS32 r okHI/core0/core0/a0/pc0/stack_ram_low/RAMD/CLK + clock pessimism 0.253 -0.284 + SLICE_X14Y35 RAMS32 (Hold_rams32_CLK_I) + 0.144 -0.140 okHI/core0/core0/a0/pc0/stack_ram_low/RAMD ------------------------------------------------------------------- - required time -0.028 - arrival time 0.086 + required time 0.140 + arrival time -0.007 ------------------------------------------------------------------- - slack 0.059 + slack 0.134 -Slack (MET) : 0.059ns (arrival time - required time) - Source: okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C +Slack (MET) : 0.139ns (arrival time - required time) + Source: okHI/core0/core0/a0/pc0/address_loop[10].pc_flop/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/pc0/stack_ram_high/RAMC/WADR0 - (rising edge-triggered cell RAMD32 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DIADI[0] + (rising edge-triggered cell RAMB18E1 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.382ns (logic 0.141ns (36.959%) route 0.241ns (63.041%)) + Data Path Delay: 0.514ns (logic 0.164ns (31.897%) route 0.350ns (68.103%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.792ns = ( -0.532 - 0.260 ) - Source Clock Delay (SCD): -0.555ns = ( -0.295 - 0.260 ) - Clock Pessimism Removal (CPR): -0.250ns + Clock Path Skew: 0.079ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.752ns = ( -0.491 - 0.260 ) + Source Clock Delay (SCD): -0.558ns = ( -0.298 - 0.260 ) + Clock Pessimism Removal (CPR): -0.273ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1311,12 +1287,12 @@ Slack (MET) : 0.059ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.566 -0.295 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y45 FDRE r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C + net (fo=1135, routed) 0.563 -0.298 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X12Y37 FDRE r okHI/core0/core0/a0/pc0/address_loop[10].pc_flop/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.154 r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/Q - net (fo=30, routed) 0.241 0.086 okHI/core0/core0/a0/pc0/stack_ram_high/ADDRD0 - SLICE_X12Y45 RAMD32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMC/WADR0 + SLICE_X12Y37 FDRE (Prop_fdre_C_Q) 0.164 -0.134 r okHI/core0/core0/a0/pc0/address_loop[10].pc_flop/Q + net (fo=3, routed) 0.350 0.216 okHI/core0/core0/a0/ld431942cac34e5a074e76137c9872d1c[10] + RAMB18_X0Y15 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/DIADI[0] ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -1329,31 +1305,31 @@ Slack (MET) : 0.059ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.836 -0.532 okHI/core0/core0/a0/pc0/stack_ram_high/WCLK - SLICE_X12Y45 RAMD32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMC/CLK - clock pessimism 0.250 -0.282 - SLICE_X12Y45 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 0.028 okHI/core0/core0/a0/pc0/stack_ram_high/RAMC + net (fo=1135, routed) 0.876 -0.491 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + RAMB18_X0Y15 RAMB18E1 r okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom/CLKARDCLK + clock pessimism 0.273 -0.219 + RAMB18_X0Y15 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_DIADI[0]) + 0.296 0.077 okHI/core0/core0/a0/pm0/ram_1k_generate.v6.kcpsm6_rom ------------------------------------------------------------------- - required time -0.028 - arrival time 0.086 + required time -0.077 + arrival time 0.216 ------------------------------------------------------------------- - slack 0.059 + slack 0.139 -Slack (MET) : 0.059ns (arrival time - required time) - Source: okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C - (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/pc0/stack_ram_high/RAMC_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) +Slack (MET) : 0.149ns (arrival time - required time) + Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/C + (rising edge-triggered cell FDCE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/D + (rising edge-triggered cell FDCE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.382ns (logic 0.141ns (36.959%) route 0.241ns (63.041%)) + Data Path Delay: 0.220ns (logic 0.141ns (64.033%) route 0.079ns (35.967%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.792ns = ( -0.532 - 0.260 ) - Source Clock Delay (SCD): -0.555ns = ( -0.295 - 0.260 ) - Clock Pessimism Removal (CPR): -0.250ns + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.770ns = ( -0.510 - 0.260 ) + Source Clock Delay (SCD): -0.532ns = ( -0.272 - 0.260 ) + Clock Pessimism Removal (CPR): -0.238ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1367,12 +1343,12 @@ Slack (MET) : 0.059ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.566 -0.295 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y45 FDRE r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C + net (fo=1135, routed) 0.589 -0.272 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X7Y34 FDCE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.154 r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/Q - net (fo=30, routed) 0.241 0.086 okHI/core0/core0/a0/pc0/stack_ram_high/ADDRD0 - SLICE_X12Y45 RAMD32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMC_D1/WADR0 + SLICE_X7Y34 FDCE (Prop_fdce_C_Q) 0.141 -0.131 r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/Q + net (fo=6, routed) 0.079 -0.052 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/p_12_out[2] + SLICE_X7Y34 FDCE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -1385,31 +1361,30 @@ Slack (MET) : 0.059ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.836 -0.532 okHI/core0/core0/a0/pc0/stack_ram_high/WCLK - SLICE_X12Y45 RAMD32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMC_D1/CLK - clock pessimism 0.250 -0.282 - SLICE_X12Y45 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 0.028 okHI/core0/core0/a0/pc0/stack_ram_high/RAMC_D1 + net (fo=1135, routed) 0.858 -0.510 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X7Y34 FDCE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/C + clock pessimism 0.238 -0.272 + SLICE_X7Y34 FDCE (Hold_fdce_C_D) 0.071 -0.201 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2] ------------------------------------------------------------------- - required time -0.028 - arrival time 0.086 + required time 0.201 + arrival time -0.052 ------------------------------------------------------------------- - slack 0.059 + slack 0.149 -Slack (MET) : 0.059ns (arrival time - required time) - Source: okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C +Slack (MET) : 0.152ns (arrival time - required time) + Source: wi0b/ep_datahold_reg[9]/C + (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: wi0b/ep_dataout_reg[9]/D (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/pc0/stack_ram_high/RAMD/ADR0 - (rising edge-triggered cell RAMS32 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.382ns (logic 0.141ns (36.959%) route 0.241ns (63.041%)) + Data Path Delay: 0.254ns (logic 0.141ns (55.533%) route 0.113ns (44.467%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.792ns = ( -0.532 - 0.260 ) - Source Clock Delay (SCD): -0.555ns = ( -0.295 - 0.260 ) - Clock Pessimism Removal (CPR): -0.250ns + Clock Path Skew: 0.032ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.779ns = ( -0.519 - 0.260 ) + Source Clock Delay (SCD): -0.538ns = ( -0.278 - 0.260 ) + Clock Pessimism Removal (CPR): -0.273ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1423,12 +1398,12 @@ Slack (MET) : 0.059ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.566 -0.295 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y45 FDRE r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C + net (fo=1135, routed) 0.583 -0.278 wi0b/ok1[24] + SLICE_X3Y23 FDRE r wi0b/ep_datahold_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.154 r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/Q - net (fo=30, routed) 0.241 0.086 okHI/core0/core0/a0/pc0/stack_ram_high/ADDRD0 - SLICE_X12Y45 RAMS32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMD/ADR0 + SLICE_X3Y23 FDRE (Prop_fdre_C_Q) 0.141 -0.137 r wi0b/ep_datahold_reg[9]/Q + net (fo=1, routed) 0.113 -0.024 wi0b/ep_datahold[9] + SLICE_X5Y23 FDRE r wi0b/ep_dataout_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -1441,31 +1416,30 @@ Slack (MET) : 0.059ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.836 -0.532 okHI/core0/core0/a0/pc0/stack_ram_high/WCLK - SLICE_X12Y45 RAMS32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMD/CLK - clock pessimism 0.250 -0.282 - SLICE_X12Y45 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 0.028 okHI/core0/core0/a0/pc0/stack_ram_high/RAMD + net (fo=1135, routed) 0.849 -0.519 wi0b/ok1[24] + SLICE_X5Y23 FDRE r wi0b/ep_dataout_reg[9]/C + clock pessimism 0.273 -0.246 + SLICE_X5Y23 FDRE (Hold_fdre_C_D) 0.070 -0.176 wi0b/ep_dataout_reg[9] ------------------------------------------------------------------- - required time -0.028 - arrival time 0.086 + required time 0.176 + arrival time -0.024 ------------------------------------------------------------------- - slack 0.059 + slack 0.152 -Slack (MET) : 0.059ns (arrival time - required time) - Source: okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C +Slack (MET) : 0.152ns (arrival time - required time) + Source: wi08/ep_datahold_reg[1]/C + (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: wi08/ep_dataout_reg[1]/D (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/pc0/stack_ram_high/RAMD_D1/ADR0 - (rising edge-triggered cell RAMS32 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.382ns (logic 0.141ns (36.959%) route 0.241ns (63.041%)) + Data Path Delay: 0.258ns (logic 0.141ns (54.595%) route 0.117ns (45.405%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.792ns = ( -0.532 - 0.260 ) - Source Clock Delay (SCD): -0.555ns = ( -0.295 - 0.260 ) - Clock Pessimism Removal (CPR): -0.250ns + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.775ns = ( -0.515 - 0.260 ) + Source Clock Delay (SCD): -0.538ns = ( -0.278 - 0.260 ) + Clock Pessimism Removal (CPR): -0.273ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1479,12 +1453,12 @@ Slack (MET) : 0.059ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.566 -0.295 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y45 FDRE r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/C + net (fo=1135, routed) 0.583 -0.278 wi08/ok1[24] + SLICE_X4Y22 FDRE r wi08/ep_datahold_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.154 r okHI/core0/core0/a0/pc0/stack_loop[0].lsb_stack.pointer_flop/Q - net (fo=30, routed) 0.241 0.086 okHI/core0/core0/a0/pc0/stack_ram_high/ADDRD0 - SLICE_X12Y45 RAMS32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMD_D1/ADR0 + SLICE_X4Y22 FDRE (Prop_fdre_C_Q) 0.141 -0.137 r wi08/ep_datahold_reg[1]/Q + net (fo=1, routed) 0.117 -0.020 wi08/ep_datahold[1] + SLICE_X3Y22 FDRE r wi08/ep_dataout_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -1497,31 +1471,30 @@ Slack (MET) : 0.059ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.836 -0.532 okHI/core0/core0/a0/pc0/stack_ram_high/WCLK - SLICE_X12Y45 RAMS32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMD_D1/CLK - clock pessimism 0.250 -0.282 - SLICE_X12Y45 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 0.028 okHI/core0/core0/a0/pc0/stack_ram_high/RAMD_D1 + net (fo=1135, routed) 0.853 -0.515 wi08/ok1[24] + SLICE_X3Y22 FDRE r wi08/ep_dataout_reg[1]/C + clock pessimism 0.273 -0.242 + SLICE_X3Y22 FDRE (Hold_fdre_C_D) 0.070 -0.172 wi08/ep_dataout_reg[1] ------------------------------------------------------------------- - required time -0.028 - arrival time 0.086 + required time 0.172 + arrival time -0.020 ------------------------------------------------------------------- - slack 0.059 + slack 0.152 -Slack (MET) : 0.068ns (arrival time - required time) - Source: okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[8]/C - (rising edge-triggered cell FDCE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[9]/D - (rising edge-triggered cell FDCE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) +Slack (MET) : 0.152ns (arrival time - required time) + Source: okHI/core0/core0/a0/pc0/address_loop[11].pc_flop/C + (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) + Destination: okHI/core0/core0/a0/pc0/stack_ram_high/RAMD_D1/I + (rising edge-triggered cell RAMS32 clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: mmcm0_clk0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.339ns (logic 0.148ns (43.688%) route 0.191ns (56.312%)) + Data Path Delay: 0.287ns (logic 0.164ns (57.089%) route 0.123ns (42.911%)) Logic Levels: 0 - Clock Path Skew: 0.272ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.791ns = ( -0.531 - 0.260 ) - Source Clock Delay (SCD): -0.556ns = ( -0.296 - 0.260 ) - Clock Pessimism Removal (CPR): -0.507ns + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.797ns = ( -0.537 - 0.260 ) + Source Clock Delay (SCD): -0.558ns = ( -0.298 - 0.260 ) + Clock Pessimism Removal (CPR): -0.253ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1535,12 +1508,12 @@ Slack (MET) : 0.068ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.565 -0.296 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X10Y50 FDCE r okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[8]/C + net (fo=1135, routed) 0.563 -0.298 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X12Y37 FDRE r okHI/core0/core0/a0/pc0/address_loop[11].pc_flop/C ------------------------------------------------------------------- ------------------- - SLICE_X10Y50 FDCE (Prop_fdce_C_Q) 0.148 -0.148 r okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[8]/Q - net (fo=2, routed) 0.191 0.043 okHI/core0/core0/le5e2e6110dd7478b8ed0143f21b04d30[8] - SLICE_X10Y49 FDCE r okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[9]/D + SLICE_X12Y37 FDRE (Prop_fdre_C_Q) 0.164 -0.134 r okHI/core0/core0/a0/pc0/address_loop[11].pc_flop/Q + net (fo=3, routed) 0.123 -0.011 okHI/core0/core0/a0/pc0/stack_ram_high/DID1 + SLICE_X14Y36 RAMS32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMD_D1/I ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -1553,15 +1526,16 @@ Slack (MET) : 0.068ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.837 -0.531 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X10Y49 FDCE r okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[9]/C - clock pessimism 0.507 -0.024 - SLICE_X10Y49 FDCE (Hold_fdce_C_D) -0.001 -0.025 okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[9] + net (fo=1135, routed) 0.831 -0.537 okHI/core0/core0/a0/pc0/stack_ram_high/WCLK + SLICE_X14Y36 RAMS32 r okHI/core0/core0/a0/pc0/stack_ram_high/RAMD_D1/CLK + clock pessimism 0.253 -0.284 + SLICE_X14Y36 RAMS32 (Hold_rams32_CLK_I) + 0.121 -0.163 okHI/core0/core0/a0/pc0/stack_ram_high/RAMD_D1 ------------------------------------------------------------------- - required time 0.025 - arrival time 0.043 + required time 0.163 + arrival time -0.011 ------------------------------------------------------------------- - slack 0.068 + slack 0.152 @@ -1575,37 +1549,37 @@ Period(ns): 20.830 Sources: { okHI/mmcm0/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.830 17.886 RAMB18_X0Y18 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.830 17.886 RAMB18_X0Y18 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB18_X0Y8 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB36_X0Y6 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB36_X0Y7 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB36_X0Y3 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB36_X0Y2 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB36_X2Y2 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB36_X1Y0 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB36_X1Y1 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.830 17.886 RAMB18_X0Y14 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.830 17.886 RAMB18_X0Y14 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB18_X2Y8 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB36_X2Y5 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB36_X2Y6 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB36_X1Y3 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB36_X1Y7 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB36_X1Y0 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB36_X0Y2 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.830 18.254 RAMB36_X0Y4 my_amp_pipe/memory/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 20.830 192.530 MMCME2_ADV_X0Y0 okHI/mmcm0/CLKOUT0 -Low Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y44 okHI/core0/core0/a0/pc0/data_path_loop[0].medium_spm.spm_ram/HIGH/CLK -Low Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y44 okHI/core0/core0/a0/pc0/data_path_loop[0].medium_spm.spm_ram/LOW/CLK -Low Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y44 okHI/core0/core0/a0/pc0/data_path_loop[1].medium_spm.spm_ram/HIGH/CLK -Low Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y44 okHI/core0/core0/a0/pc0/data_path_loop[1].medium_spm.spm_ram/LOW/CLK -Low Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y45 okHI/core0/core0/a0/pc0/data_path_loop[2].medium_spm.spm_ram/HIGH/CLK -Low Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y45 okHI/core0/core0/a0/pc0/data_path_loop[2].medium_spm.spm_ram/LOW/CLK -Low Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y45 okHI/core0/core0/a0/pc0/data_path_loop[3].medium_spm.spm_ram/HIGH/CLK -Low Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y45 okHI/core0/core0/a0/pc0/data_path_loop[3].medium_spm.spm_ram/LOW/CLK -Low Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X10Y43 okHI/core0/core0/a0/pc0/data_path_loop[6].medium_spm.spm_ram/HIGH/CLK -Low Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X10Y43 okHI/core0/core0/a0/pc0/data_path_loop[6].medium_spm.spm_ram/LOW/CLK -High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y44 okHI/core0/core0/a0/pc0/data_path_loop[0].medium_spm.spm_ram/HIGH/CLK -High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y44 okHI/core0/core0/a0/pc0/data_path_loop[0].medium_spm.spm_ram/LOW/CLK -High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y44 okHI/core0/core0/a0/pc0/data_path_loop[1].medium_spm.spm_ram/HIGH/CLK -High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y44 okHI/core0/core0/a0/pc0/data_path_loop[1].medium_spm.spm_ram/LOW/CLK -High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y45 okHI/core0/core0/a0/pc0/data_path_loop[2].medium_spm.spm_ram/HIGH/CLK -High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y45 okHI/core0/core0/a0/pc0/data_path_loop[2].medium_spm.spm_ram/LOW/CLK -High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y45 okHI/core0/core0/a0/pc0/data_path_loop[3].medium_spm.spm_ram/HIGH/CLK -High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y45 okHI/core0/core0/a0/pc0/data_path_loop[3].medium_spm.spm_ram/LOW/CLK -High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X8Y46 okHI/core0/core0/a0/pc0/data_path_loop[4].medium_spm.spm_ram/HIGH/CLK -High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X8Y46 okHI/core0/core0/a0/pc0/data_path_loop[4].medium_spm.spm_ram/LOW/CLK +Low Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y38 okHI/core0/core0/a0/pc0/data_path_loop[4].medium_spm.spm_ram/HIGH/CLK +Low Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y38 okHI/core0/core0/a0/pc0/data_path_loop[4].medium_spm.spm_ram/LOW/CLK +Low Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y38 okHI/core0/core0/a0/pc0/data_path_loop[5].medium_spm.spm_ram/HIGH/CLK +Low Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y38 okHI/core0/core0/a0/pc0/data_path_loop[5].medium_spm.spm_ram/LOW/CLK +Low Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y37 okHI/core0/core0/a0/pc0/data_path_loop[6].medium_spm.spm_ram/HIGH/CLK +Low Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y37 okHI/core0/core0/a0/pc0/data_path_loop[6].medium_spm.spm_ram/LOW/CLK +Low Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y37 okHI/core0/core0/a0/pc0/data_path_loop[7].medium_spm.spm_ram/HIGH/CLK +Low Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X6Y37 okHI/core0/core0/a0/pc0/data_path_loop[7].medium_spm.spm_ram/LOW/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.415 9.165 SLICE_X10Y36 okHI/core0/core0/a0/pc0/lower_reg_banks/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.415 9.165 SLICE_X10Y36 okHI/core0/core0/a0/pc0/lower_reg_banks/RAMA_D1/CLK +High Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X8Y38 okHI/core0/core0/a0/pc0/data_path_loop[0].medium_spm.spm_ram/HIGH/CLK +High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X8Y38 okHI/core0/core0/a0/pc0/data_path_loop[0].medium_spm.spm_ram/HIGH/CLK +High Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X8Y38 okHI/core0/core0/a0/pc0/data_path_loop[0].medium_spm.spm_ram/LOW/CLK +High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X8Y38 okHI/core0/core0/a0/pc0/data_path_loop[0].medium_spm.spm_ram/LOW/CLK +High Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X8Y38 okHI/core0/core0/a0/pc0/data_path_loop[1].medium_spm.spm_ram/HIGH/CLK +High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X8Y38 okHI/core0/core0/a0/pc0/data_path_loop[1].medium_spm.spm_ram/HIGH/CLK +High Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X8Y38 okHI/core0/core0/a0/pc0/data_path_loop[1].medium_spm.spm_ram/LOW/CLK +High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X8Y38 okHI/core0/core0/a0/pc0/data_path_loop[1].medium_spm.spm_ram/LOW/CLK +High Pulse Width Slow RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X10Y38 okHI/core0/core0/a0/pc0/data_path_loop[2].medium_spm.spm_ram/HIGH/CLK +High Pulse Width Fast RAMS64E/CLK n/a 1.250 10.415 9.165 SLICE_X10Y38 okHI/core0/core0/a0/pc0/data_path_loop[2].medium_spm.spm_ram/HIGH/CLK @@ -1639,14 +1613,14 @@ Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 20.830 From Clock: mmcm0_clk0 To Clock: okHostClk -Setup : 0 Failing Endpoints, Worst Slack 6.444ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 6.825ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 9.804ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 6.444ns (required time - arrival time) +Slack (MET) : 6.825ns (required time - arrival time) Source: okHI/core0/core0/l59874d0ad0412d80424d66b41f47de0c_reg/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Destination: hi_out[0] @@ -1654,12 +1628,12 @@ Slack (MET) : 6.444ns (required time - arrival time) Path Group: okHostClk Path Type: Max at Slow Process Corner Requirement: 20.570ns (okHostClk rise@20.830ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 5.920ns (logic 4.060ns (68.587%) route 1.860ns (31.413%)) + Data Path Delay: 5.531ns (logic 3.998ns (72.284%) route 1.533ns (27.716%)) Logic Levels: 1 (OBUF=1) Output Delay: 8.900ns - Clock Path Skew: 0.829ns (DCD - SCD + CPR) + Clock Path Skew: 0.821ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.000ns = ( 20.830 - 20.830 ) - Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) + Source Clock Delay (SCD): -0.821ns = ( -0.561 - 0.260 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -1678,13 +1652,13 @@ Slack (MET) : 6.444ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X2Y27 FDRE r okHI/core0/core0/l59874d0ad0412d80424d66b41f47de0c_reg/C + net (fo=1135, routed) 1.629 -0.561 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X0Y32 FDRE r okHI/core0/core0/l59874d0ad0412d80424d66b41f47de0c_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y27 FDRE (Prop_fdre_C_Q) 0.518 -0.051 r okHI/core0/core0/l59874d0ad0412d80424d66b41f47de0c_reg/Q - net (fo=1, routed) 1.860 1.809 okHI/okCH[0] - R15 OBUF (Prop_obuf_I_O) 3.542 5.351 r okHI/obuf0/O - net (fo=0) 0.000 5.351 hi_out[0] + SLICE_X0Y32 FDRE (Prop_fdre_C_Q) 0.456 -0.105 r okHI/core0/core0/l59874d0ad0412d80424d66b41f47de0c_reg/Q + net (fo=1, routed) 1.533 1.428 okHI/okCH[0] + R15 OBUF (Prop_obuf_I_O) 3.542 4.971 r okHI/obuf0/O + net (fo=0) 0.000 4.971 hi_out[0] R15 r hi_out[0] (OUT) ------------------------------------------------------------------- ------------------- @@ -1695,9 +1669,9 @@ Slack (MET) : 6.444ns (required time - arrival time) output delay -8.900 11.796 ------------------------------------------------------------------- required time 11.796 - arrival time -5.351 + arrival time -4.971 ------------------------------------------------------------------- - slack 6.444 + slack 6.825 Slack (MET) : 7.882ns (required time - arrival time) Source: okHI/delays[6].fdreout1/C @@ -3841,26 +3815,26 @@ Path Group: **async_default** From Clock: mmcm0_clk0 To Clock: mmcm0_clk0 -Setup : 0 Failing Endpoints, Worst Slack 16.919ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.467ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 16.929ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.383ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 16.919ns (required time - arrival time) +Slack (MET) : 16.929ns (required time - arrival time) Source: okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l90ce46b343647bab4d280b5afc506219_reg/CLR + Destination: okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[5]/PRE (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 3.450ns (logic 0.642ns (18.606%) route 2.808ns (81.394%)) + Data Path Delay: 3.397ns (logic 0.580ns (17.072%) route 2.817ns (82.928%)) Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.091ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.483ns = ( 19.607 - 21.090 ) - Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) + Clock Path Skew: -0.092ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.485ns = ( 19.605 - 21.090 ) + Source Clock Delay (SCD): -0.830ns = ( -0.570 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -3879,14 +3853,14 @@ Slack (MET) : 16.919ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X2Y27 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C + net (fo=1135, routed) 1.620 -0.570 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y26 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y27 FDRE (Prop_fdre_C_Q) 0.518 -0.051 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q - net (fo=1, routed) 0.475 0.425 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 - SLICE_X2Y27 LUT5 (Prop_lut5_I0_O) 0.124 0.549 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.333 2.882 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X14Y46 FDCE f okHI/core0/core0/a0/l90ce46b343647bab4d280b5afc506219_reg/CLR + SLICE_X3Y26 FDRE (Prop_fdre_C_Q) 0.456 -0.114 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q + net (fo=1, routed) 0.860 0.747 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 + SLICE_X3Y26 LUT5 (Prop_lut5_I0_O) 0.124 0.871 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 1.957 2.828 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X14Y40 FDPE f okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[5]/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -3899,30 +3873,30 @@ Slack (MET) : 16.919ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.450 19.607 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X14Y46 FDCE r okHI/core0/core0/a0/l90ce46b343647bab4d280b5afc506219_reg/C - clock pessimism 0.563 20.170 - clock uncertainty -0.050 20.120 - SLICE_X14Y46 FDCE (Recov_fdce_C_CLR) -0.319 19.801 okHI/core0/core0/a0/l90ce46b343647bab4d280b5afc506219_reg + net (fo=1135, routed) 1.448 19.605 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X14Y40 FDPE r okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[5]/C + clock pessimism 0.563 20.168 + clock uncertainty -0.050 20.118 + SLICE_X14Y40 FDPE (Recov_fdpe_C_PRE) -0.361 19.757 okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[5] ------------------------------------------------------------------- - required time 19.801 - arrival time -2.882 + required time 19.757 + arrival time -2.828 ------------------------------------------------------------------- - slack 16.919 + slack 16.929 -Slack (MET) : 16.970ns (required time - arrival time) +Slack (MET) : 16.929ns (required time - arrival time) Source: okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l8733ba0cb25077d8c78e1b1549a80eef_reg/CLR + Destination: okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[8]/PRE (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 3.314ns (logic 0.642ns (19.370%) route 2.672ns (80.630%)) + Data Path Delay: 3.397ns (logic 0.580ns (17.072%) route 2.817ns (82.928%)) Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( 19.608 - 21.090 ) - Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) + Clock Path Skew: -0.092ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.485ns = ( 19.605 - 21.090 ) + Source Clock Delay (SCD): -0.830ns = ( -0.570 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -3941,14 +3915,14 @@ Slack (MET) : 16.970ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X2Y27 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C + net (fo=1135, routed) 1.620 -0.570 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y26 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y27 FDRE (Prop_fdre_C_Q) 0.518 -0.051 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q - net (fo=1, routed) 0.475 0.425 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 - SLICE_X2Y27 LUT5 (Prop_lut5_I0_O) 0.124 0.549 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.197 2.746 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X13Y48 FDCE f okHI/core0/core0/a0/l8733ba0cb25077d8c78e1b1549a80eef_reg/CLR + SLICE_X3Y26 FDRE (Prop_fdre_C_Q) 0.456 -0.114 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q + net (fo=1, routed) 0.860 0.747 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 + SLICE_X3Y26 LUT5 (Prop_lut5_I0_O) 0.124 0.871 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 1.957 2.828 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X14Y40 FDPE f okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[8]/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -3961,18 +3935,18 @@ Slack (MET) : 16.970ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y48 FDCE r okHI/core0/core0/a0/l8733ba0cb25077d8c78e1b1549a80eef_reg/C - clock pessimism 0.563 20.171 - clock uncertainty -0.050 20.121 - SLICE_X13Y48 FDCE (Recov_fdce_C_CLR) -0.405 19.716 okHI/core0/core0/a0/l8733ba0cb25077d8c78e1b1549a80eef_reg + net (fo=1135, routed) 1.448 19.605 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X14Y40 FDPE r okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[8]/C + clock pessimism 0.563 20.168 + clock uncertainty -0.050 20.118 + SLICE_X14Y40 FDPE (Recov_fdpe_C_PRE) -0.361 19.757 okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[8] ------------------------------------------------------------------- - required time 19.716 - arrival time -2.746 + required time 19.757 + arrival time -2.828 ------------------------------------------------------------------- - slack 16.970 + slack 16.929 -Slack (MET) : 16.982ns (required time - arrival time) +Slack (MET) : 17.146ns (required time - arrival time) Source: okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Destination: okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[1]/CLR @@ -3980,11 +3954,11 @@ Slack (MET) : 16.982ns (required time - arrival time) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 3.346ns (logic 0.642ns (19.185%) route 2.704ns (80.815%)) + Data Path Delay: 3.181ns (logic 0.580ns (18.235%) route 2.601ns (81.765%)) Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( 19.608 - 21.090 ) - Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) + Clock Path Skew: -0.092ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.485ns = ( 19.605 - 21.090 ) + Source Clock Delay (SCD): -0.830ns = ( -0.570 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -4003,14 +3977,14 @@ Slack (MET) : 16.982ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X2Y27 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C + net (fo=1135, routed) 1.620 -0.570 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y26 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y27 FDRE (Prop_fdre_C_Q) 0.518 -0.051 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q - net (fo=1, routed) 0.475 0.425 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 - SLICE_X2Y27 LUT5 (Prop_lut5_I0_O) 0.124 0.549 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.229 2.778 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X14Y49 FDCE f okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[1]/CLR + SLICE_X3Y26 FDRE (Prop_fdre_C_Q) 0.456 -0.114 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q + net (fo=1, routed) 0.860 0.747 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 + SLICE_X3Y26 LUT5 (Prop_lut5_I0_O) 0.124 0.871 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 1.740 2.611 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X8Y40 FDCE f okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4023,18 +3997,18 @@ Slack (MET) : 16.982ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X14Y49 FDCE r okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[1]/C - clock pessimism 0.563 20.171 - clock uncertainty -0.050 20.121 - SLICE_X14Y49 FDCE (Recov_fdce_C_CLR) -0.361 19.760 okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[1] + net (fo=1135, routed) 1.448 19.605 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X8Y40 FDCE r okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[1]/C + clock pessimism 0.563 20.168 + clock uncertainty -0.050 20.118 + SLICE_X8Y40 FDCE (Recov_fdce_C_CLR) -0.361 19.757 okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[1] ------------------------------------------------------------------- - required time 19.760 - arrival time -2.778 + required time 19.757 + arrival time -2.611 ------------------------------------------------------------------- - slack 16.982 + slack 17.146 -Slack (MET) : 16.982ns (required time - arrival time) +Slack (MET) : 17.146ns (required time - arrival time) Source: okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Destination: okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[3]/CLR @@ -4042,11 +4016,11 @@ Slack (MET) : 16.982ns (required time - arrival time) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 3.346ns (logic 0.642ns (19.185%) route 2.704ns (80.815%)) + Data Path Delay: 3.181ns (logic 0.580ns (18.235%) route 2.601ns (81.765%)) Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( 19.608 - 21.090 ) - Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) + Clock Path Skew: -0.092ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.485ns = ( 19.605 - 21.090 ) + Source Clock Delay (SCD): -0.830ns = ( -0.570 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -4065,14 +4039,14 @@ Slack (MET) : 16.982ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X2Y27 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C + net (fo=1135, routed) 1.620 -0.570 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y26 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y27 FDRE (Prop_fdre_C_Q) 0.518 -0.051 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q - net (fo=1, routed) 0.475 0.425 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 - SLICE_X2Y27 LUT5 (Prop_lut5_I0_O) 0.124 0.549 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.229 2.778 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X14Y49 FDCE f okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[3]/CLR + SLICE_X3Y26 FDRE (Prop_fdre_C_Q) 0.456 -0.114 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q + net (fo=1, routed) 0.860 0.747 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 + SLICE_X3Y26 LUT5 (Prop_lut5_I0_O) 0.124 0.871 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 1.740 2.611 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X8Y40 FDCE f okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4085,30 +4059,30 @@ Slack (MET) : 16.982ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X14Y49 FDCE r okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[3]/C - clock pessimism 0.563 20.171 - clock uncertainty -0.050 20.121 - SLICE_X14Y49 FDCE (Recov_fdce_C_CLR) -0.361 19.760 okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[3] + net (fo=1135, routed) 1.448 19.605 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X8Y40 FDCE r okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[3]/C + clock pessimism 0.563 20.168 + clock uncertainty -0.050 20.118 + SLICE_X8Y40 FDCE (Recov_fdce_C_CLR) -0.361 19.757 okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[3] ------------------------------------------------------------------- - required time 19.760 - arrival time -2.778 + required time 19.757 + arrival time -2.611 ------------------------------------------------------------------- - slack 16.982 + slack 17.146 -Slack (MET) : 17.016ns (required time - arrival time) +Slack (MET) : 17.172ns (required time - arrival time) Source: okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[0]/PRE + Destination: okHI/core0/core0/a0/le7badcf1256ff8aabbffe7a6a1b38b5f_reg/CLR (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 3.314ns (logic 0.642ns (19.370%) route 2.672ns (80.630%)) + Data Path Delay: 3.110ns (logic 0.580ns (18.650%) route 2.530ns (81.350%)) Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( 19.608 - 21.090 ) - Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) + Clock Path Skew: -0.093ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.486ns = ( 19.604 - 21.090 ) + Source Clock Delay (SCD): -0.830ns = ( -0.570 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -4127,14 +4101,14 @@ Slack (MET) : 17.016ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X2Y27 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C + net (fo=1135, routed) 1.620 -0.570 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y26 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y27 FDRE (Prop_fdre_C_Q) 0.518 -0.051 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q - net (fo=1, routed) 0.475 0.425 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 - SLICE_X2Y27 LUT5 (Prop_lut5_I0_O) 0.124 0.549 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.197 2.746 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X13Y48 FDPE f okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[0]/PRE + SLICE_X3Y26 FDRE (Prop_fdre_C_Q) 0.456 -0.114 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q + net (fo=1, routed) 0.860 0.747 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 + SLICE_X3Y26 LUT5 (Prop_lut5_I0_O) 0.124 0.871 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 1.670 2.540 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X13Y38 FDCE f okHI/core0/core0/a0/le7badcf1256ff8aabbffe7a6a1b38b5f_reg/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4147,30 +4121,30 @@ Slack (MET) : 17.016ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y48 FDPE r okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[0]/C - clock pessimism 0.563 20.171 - clock uncertainty -0.050 20.121 - SLICE_X13Y48 FDPE (Recov_fdpe_C_PRE) -0.359 19.762 okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[0] + net (fo=1135, routed) 1.447 19.604 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X13Y38 FDCE r okHI/core0/core0/a0/le7badcf1256ff8aabbffe7a6a1b38b5f_reg/C + clock pessimism 0.563 20.167 + clock uncertainty -0.050 20.117 + SLICE_X13Y38 FDCE (Recov_fdce_C_CLR) -0.405 19.712 okHI/core0/core0/a0/le7badcf1256ff8aabbffe7a6a1b38b5f_reg ------------------------------------------------------------------- - required time 19.762 - arrival time -2.746 + required time 19.712 + arrival time -2.540 ------------------------------------------------------------------- - slack 17.016 + slack 17.172 -Slack (MET) : 17.016ns (required time - arrival time) +Slack (MET) : 17.188ns (required time - arrival time) Source: okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[13]/PRE + Destination: okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[0]/CLR (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 3.314ns (logic 0.642ns (19.370%) route 2.672ns (80.630%)) + Data Path Delay: 3.181ns (logic 0.580ns (18.235%) route 2.601ns (81.765%)) Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( 19.608 - 21.090 ) - Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) + Clock Path Skew: -0.092ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.485ns = ( 19.605 - 21.090 ) + Source Clock Delay (SCD): -0.830ns = ( -0.570 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -4189,14 +4163,14 @@ Slack (MET) : 17.016ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X2Y27 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C + net (fo=1135, routed) 1.620 -0.570 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y26 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y27 FDRE (Prop_fdre_C_Q) 0.518 -0.051 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q - net (fo=1, routed) 0.475 0.425 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 - SLICE_X2Y27 LUT5 (Prop_lut5_I0_O) 0.124 0.549 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.197 2.746 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X13Y48 FDPE f okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[13]/PRE + SLICE_X3Y26 FDRE (Prop_fdre_C_Q) 0.456 -0.114 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q + net (fo=1, routed) 0.860 0.747 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 + SLICE_X3Y26 LUT5 (Prop_lut5_I0_O) 0.124 0.871 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 1.740 2.611 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X8Y40 FDCE f okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4209,30 +4183,30 @@ Slack (MET) : 17.016ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y48 FDPE r okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[13]/C - clock pessimism 0.563 20.171 - clock uncertainty -0.050 20.121 - SLICE_X13Y48 FDPE (Recov_fdpe_C_PRE) -0.359 19.762 okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[13] + net (fo=1135, routed) 1.448 19.605 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X8Y40 FDCE r okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[0]/C + clock pessimism 0.563 20.168 + clock uncertainty -0.050 20.118 + SLICE_X8Y40 FDCE (Recov_fdce_C_CLR) -0.319 19.799 okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[0] ------------------------------------------------------------------- - required time 19.762 - arrival time -2.746 + required time 19.799 + arrival time -2.611 ------------------------------------------------------------------- - slack 17.016 + slack 17.188 -Slack (MET) : 17.016ns (required time - arrival time) +Slack (MET) : 17.188ns (required time - arrival time) Source: okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[1]/PRE + Destination: okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[2]/CLR (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 3.314ns (logic 0.642ns (19.370%) route 2.672ns (80.630%)) + Data Path Delay: 3.181ns (logic 0.580ns (18.235%) route 2.601ns (81.765%)) Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( 19.608 - 21.090 ) - Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) + Clock Path Skew: -0.092ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.485ns = ( 19.605 - 21.090 ) + Source Clock Delay (SCD): -0.830ns = ( -0.570 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -4251,14 +4225,14 @@ Slack (MET) : 17.016ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X2Y27 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C + net (fo=1135, routed) 1.620 -0.570 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y26 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y27 FDRE (Prop_fdre_C_Q) 0.518 -0.051 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q - net (fo=1, routed) 0.475 0.425 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 - SLICE_X2Y27 LUT5 (Prop_lut5_I0_O) 0.124 0.549 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.197 2.746 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X13Y48 FDPE f okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[1]/PRE + SLICE_X3Y26 FDRE (Prop_fdre_C_Q) 0.456 -0.114 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q + net (fo=1, routed) 0.860 0.747 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 + SLICE_X3Y26 LUT5 (Prop_lut5_I0_O) 0.124 0.871 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 1.740 2.611 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X8Y40 FDCE f okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4271,30 +4245,30 @@ Slack (MET) : 17.016ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y48 FDPE r okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[1]/C - clock pessimism 0.563 20.171 - clock uncertainty -0.050 20.121 - SLICE_X13Y48 FDPE (Recov_fdpe_C_PRE) -0.359 19.762 okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[1] + net (fo=1135, routed) 1.448 19.605 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X8Y40 FDCE r okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[2]/C + clock pessimism 0.563 20.168 + clock uncertainty -0.050 20.118 + SLICE_X8Y40 FDCE (Recov_fdce_C_CLR) -0.319 19.799 okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[2] ------------------------------------------------------------------- - required time 19.762 - arrival time -2.746 + required time 19.799 + arrival time -2.611 ------------------------------------------------------------------- - slack 17.016 + slack 17.188 -Slack (MET) : 17.016ns (required time - arrival time) +Slack (MET) : 17.194ns (required time - arrival time) Source: okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[6]/PRE + Destination: okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[3]/PRE (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 3.314ns (logic 0.642ns (19.370%) route 2.672ns (80.630%)) + Data Path Delay: 3.133ns (logic 0.580ns (18.511%) route 2.553ns (81.489%)) Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( 19.608 - 21.090 ) - Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.484ns = ( 19.606 - 21.090 ) + Source Clock Delay (SCD): -0.830ns = ( -0.570 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -4313,14 +4287,14 @@ Slack (MET) : 17.016ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X2Y27 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C + net (fo=1135, routed) 1.620 -0.570 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y26 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y27 FDRE (Prop_fdre_C_Q) 0.518 -0.051 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q - net (fo=1, routed) 0.475 0.425 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 - SLICE_X2Y27 LUT5 (Prop_lut5_I0_O) 0.124 0.549 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.197 2.746 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X13Y48 FDPE f okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[6]/PRE + SLICE_X3Y26 FDRE (Prop_fdre_C_Q) 0.456 -0.114 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q + net (fo=1, routed) 0.860 0.747 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 + SLICE_X3Y26 LUT5 (Prop_lut5_I0_O) 0.124 0.871 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 1.693 2.564 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X14Y41 FDPE f okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[3]/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4333,30 +4307,30 @@ Slack (MET) : 17.016ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y48 FDPE r okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[6]/C - clock pessimism 0.563 20.171 - clock uncertainty -0.050 20.121 - SLICE_X13Y48 FDPE (Recov_fdpe_C_PRE) -0.359 19.762 okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[6] + net (fo=1135, routed) 1.449 19.606 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X14Y41 FDPE r okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[3]/C + clock pessimism 0.563 20.169 + clock uncertainty -0.050 20.119 + SLICE_X14Y41 FDPE (Recov_fdpe_C_PRE) -0.361 19.758 okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[3] ------------------------------------------------------------------- - required time 19.762 - arrival time -2.746 + required time 19.758 + arrival time -2.564 ------------------------------------------------------------------- - slack 17.016 + slack 17.194 -Slack (MET) : 17.024ns (required time - arrival time) +Slack (MET) : 17.218ns (required time - arrival time) Source: okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[0]/CLR + Destination: okHI/core0/core0/a0/l3ef837e59a131545b35a9a1962086cbf_reg/PRE (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 3.346ns (logic 0.642ns (19.185%) route 2.704ns (80.815%)) + Data Path Delay: 3.110ns (logic 0.580ns (18.650%) route 2.530ns (81.350%)) Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( 19.608 - 21.090 ) - Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) + Clock Path Skew: -0.093ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.486ns = ( 19.604 - 21.090 ) + Source Clock Delay (SCD): -0.830ns = ( -0.570 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -4375,14 +4349,14 @@ Slack (MET) : 17.024ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X2Y27 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C + net (fo=1135, routed) 1.620 -0.570 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y26 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y27 FDRE (Prop_fdre_C_Q) 0.518 -0.051 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q - net (fo=1, routed) 0.475 0.425 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 - SLICE_X2Y27 LUT5 (Prop_lut5_I0_O) 0.124 0.549 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.229 2.778 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X14Y49 FDCE f okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[0]/CLR + SLICE_X3Y26 FDRE (Prop_fdre_C_Q) 0.456 -0.114 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q + net (fo=1, routed) 0.860 0.747 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 + SLICE_X3Y26 LUT5 (Prop_lut5_I0_O) 0.124 0.871 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 1.670 2.540 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X13Y38 FDPE f okHI/core0/core0/a0/l3ef837e59a131545b35a9a1962086cbf_reg/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4395,30 +4369,30 @@ Slack (MET) : 17.024ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X14Y49 FDCE r okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[0]/C - clock pessimism 0.563 20.171 - clock uncertainty -0.050 20.121 - SLICE_X14Y49 FDCE (Recov_fdce_C_CLR) -0.319 19.802 okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[0] + net (fo=1135, routed) 1.447 19.604 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X13Y38 FDPE r okHI/core0/core0/a0/l3ef837e59a131545b35a9a1962086cbf_reg/C + clock pessimism 0.563 20.167 + clock uncertainty -0.050 20.117 + SLICE_X13Y38 FDPE (Recov_fdpe_C_PRE) -0.359 19.758 okHI/core0/core0/a0/l3ef837e59a131545b35a9a1962086cbf_reg ------------------------------------------------------------------- - required time 19.802 - arrival time -2.778 + required time 19.758 + arrival time -2.540 ------------------------------------------------------------------- - slack 17.024 + slack 17.218 -Slack (MET) : 17.024ns (required time - arrival time) +Slack (MET) : 17.294ns (required time - arrival time) Source: okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C (rising edge-triggered cell FDRE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[2]/CLR + Destination: okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[17]/PRE (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.830ns (mmcm0_clk0 rise@21.090ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 3.346ns (logic 0.642ns (19.185%) route 2.704ns (80.815%)) + Data Path Delay: 3.033ns (logic 0.580ns (19.121%) route 2.453ns (80.879%)) Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( 19.608 - 21.090 ) - Source Clock Delay (SCD): -0.829ns = ( -0.569 - 0.260 ) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.484ns = ( 19.606 - 21.090 ) + Source Clock Delay (SCD): -0.830ns = ( -0.570 - 0.260 ) Clock Pessimism Removal (CPR): 0.563ns Clock Uncertainty: 0.050ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -4437,14 +4411,14 @@ Slack (MET) : 17.024ns (required time - arrival time) -6.965 -3.952 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.666 -2.286 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -2.190 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.621 -0.569 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X2Y27 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C + net (fo=1135, routed) 1.620 -0.570 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X3Y26 FDRE r okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y27 FDRE (Prop_fdre_C_Q) 0.518 -0.051 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q - net (fo=1, routed) 0.475 0.425 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 - SLICE_X2Y27 LUT5 (Prop_lut5_I0_O) 0.124 0.549 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.229 2.778 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X14Y49 FDCE f okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[2]/CLR + SLICE_X3Y26 FDRE (Prop_fdre_C_Q) 0.456 -0.114 f okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5_reg/Q + net (fo=1, routed) 0.860 0.747 okHI/core0/core0/a0/lc6c6ff624aff6ea81df719a632099fd5 + SLICE_X3Y26 LUT5 (Prop_lut5_I0_O) 0.124 0.871 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 1.593 2.464 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X8Y41 FDPE f okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[17]/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4457,16 +4431,16 @@ Slack (MET) : 17.024ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X14Y49 FDCE r okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[2]/C - clock pessimism 0.563 20.171 - clock uncertainty -0.050 20.121 - SLICE_X14Y49 FDCE (Recov_fdce_C_CLR) -0.319 19.802 okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[2] + net (fo=1135, routed) 1.449 19.606 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X8Y41 FDPE r okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[17]/C + clock pessimism 0.563 20.169 + clock uncertainty -0.050 20.119 + SLICE_X8Y41 FDPE (Recov_fdpe_C_PRE) -0.361 19.758 okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[17] ------------------------------------------------------------------- - required time 19.802 - arrival time -2.778 + required time 19.758 + arrival time -2.464 ------------------------------------------------------------------- - slack 17.024 + slack 17.294 @@ -4474,7 +4448,7 @@ Slack (MET) : 17.024ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.467ns (arrival time - required time) +Slack (MET) : 0.383ns (arrival time - required time) Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_reg/PRE @@ -4482,12 +4456,12 @@ Slack (MET) : 0.467ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.405ns (logic 0.141ns (34.857%) route 0.264ns (65.143%)) + Data Path Delay: 0.327ns (logic 0.141ns (43.069%) route 0.186ns (56.931%)) Logic Levels: 0 - Clock Path Skew: 0.009ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.793ns = ( -0.533 - 0.260 ) - Source Clock Delay (SCD): -0.529ns = ( -0.269 - 0.260 ) - Clock Pessimism Removal (CPR): -0.273ns + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.770ns = ( -0.510 - 0.260 ) + Source Clock Delay (SCD): -0.533ns = ( -0.273 - 0.260 ) + Clock Pessimism Removal (CPR): -0.252ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -4501,12 +4475,12 @@ Slack (MET) : 0.467ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.592 -0.269 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X7Y41 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C + net (fo=1135, routed) 0.588 -0.273 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X7Y33 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y41 FDPE (Prop_fdpe_C_Q) 0.141 -0.128 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q - net (fo=2, routed) 0.264 0.135 okHI/core0/core0/a0/cb0/U0/RD_RST - SLICE_X10Y41 FDPE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_reg/PRE + SLICE_X7Y33 FDPE (Prop_fdpe_C_Q) 0.141 -0.132 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q + net (fo=2, routed) 0.186 0.054 okHI/core0/core0/a0/cb0/U0/RD_RST + SLICE_X6Y34 FDPE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_reg/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4519,17 +4493,17 @@ Slack (MET) : 0.467ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.835 -0.533 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X10Y41 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_reg/C - clock pessimism 0.273 -0.260 - SLICE_X10Y41 FDPE (Remov_fdpe_C_PRE) -0.071 -0.331 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_reg + net (fo=1135, routed) 0.858 -0.510 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X6Y34 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_reg/C + clock pessimism 0.252 -0.258 + SLICE_X6Y34 FDPE (Remov_fdpe_C_PRE) -0.071 -0.329 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_reg ------------------------------------------------------------------- - required time 0.331 - arrival time 0.135 + required time 0.329 + arrival time 0.054 ------------------------------------------------------------------- - slack 0.467 + slack 0.383 -Slack (MET) : 0.467ns (arrival time - required time) +Slack (MET) : 0.383ns (arrival time - required time) Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_reg/PRE @@ -4537,12 +4511,12 @@ Slack (MET) : 0.467ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.405ns (logic 0.141ns (34.857%) route 0.264ns (65.143%)) + Data Path Delay: 0.327ns (logic 0.141ns (43.069%) route 0.186ns (56.931%)) Logic Levels: 0 - Clock Path Skew: 0.009ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.793ns = ( -0.533 - 0.260 ) - Source Clock Delay (SCD): -0.529ns = ( -0.269 - 0.260 ) - Clock Pessimism Removal (CPR): -0.273ns + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.770ns = ( -0.510 - 0.260 ) + Source Clock Delay (SCD): -0.533ns = ( -0.273 - 0.260 ) + Clock Pessimism Removal (CPR): -0.252ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -4556,12 +4530,12 @@ Slack (MET) : 0.467ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.592 -0.269 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X7Y41 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C + net (fo=1135, routed) 0.588 -0.273 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X7Y33 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y41 FDPE (Prop_fdpe_C_Q) 0.141 -0.128 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q - net (fo=2, routed) 0.264 0.135 okHI/core0/core0/a0/cb0/U0/RD_RST - SLICE_X10Y41 FDPE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_reg/PRE + SLICE_X7Y33 FDPE (Prop_fdpe_C_Q) 0.141 -0.132 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q + net (fo=2, routed) 0.186 0.054 okHI/core0/core0/a0/cb0/U0/RD_RST + SLICE_X6Y34 FDPE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_reg/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4574,30 +4548,30 @@ Slack (MET) : 0.467ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.835 -0.533 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X10Y41 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_reg/C - clock pessimism 0.273 -0.260 - SLICE_X10Y41 FDPE (Remov_fdpe_C_PRE) -0.071 -0.331 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_reg + net (fo=1135, routed) 0.858 -0.510 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X6Y34 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_reg/C + clock pessimism 0.252 -0.258 + SLICE_X6Y34 FDPE (Remov_fdpe_C_PRE) -0.071 -0.329 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_reg ------------------------------------------------------------------- - required time 0.331 - arrival time 0.135 + required time 0.329 + arrival time 0.054 ------------------------------------------------------------------- - slack 0.467 + slack 0.383 -Slack (MET) : 0.472ns (arrival time - required time) - Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/C +Slack (MET) : 0.390ns (arrival time - required time) + Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/PRE + Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/PRE (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.417ns (logic 0.186ns (44.634%) route 0.231ns (55.366%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.765ns = ( -0.505 - 0.260 ) - Source Clock Delay (SCD): -0.529ns = ( -0.269 - 0.260 ) - Clock Pessimism Removal (CPR): -0.252ns + Data Path Delay: 0.281ns (logic 0.148ns (52.672%) route 0.133ns (47.328%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.797ns = ( -0.537 - 0.260 ) + Source Clock Delay (SCD): -0.559ns = ( -0.299 - 0.260 ) + Clock Pessimism Removal (CPR): -0.253ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -4611,14 +4585,12 @@ Slack (MET) : 0.472ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.592 -0.269 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X7Y42 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/C + net (fo=1135, routed) 0.562 -0.299 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X8Y34 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y42 FDPE (Prop_fdpe_C_Q) 0.141 -0.128 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/Q - net (fo=3, routed) 0.114 -0.014 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg - SLICE_X6Y42 LUT2 (Prop_lut2_I0_O) 0.045 0.031 f okHI/core0/core0/a0/cb0/U0/ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1/O - net (fo=1, routed) 0.116 0.148 okHI/core0/core0/a0/cb0/U0/ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1_n_0 - SLICE_X6Y41 FDPE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/PRE + SLICE_X8Y34 FDPE (Prop_fdpe_C_Q) 0.148 -0.151 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q + net (fo=3, routed) 0.133 -0.018 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_d2 + SLICE_X8Y35 FDPE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4631,30 +4603,30 @@ Slack (MET) : 0.472ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.863 -0.505 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X6Y41 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/C - clock pessimism 0.252 -0.253 - SLICE_X6Y41 FDPE (Remov_fdpe_C_PRE) -0.071 -0.324 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2] + net (fo=1135, routed) 0.831 -0.537 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X8Y35 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/C + clock pessimism 0.253 -0.284 + SLICE_X8Y35 FDPE (Remov_fdpe_C_PRE) -0.124 -0.408 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg ------------------------------------------------------------------- - required time 0.324 - arrival time 0.148 + required time 0.408 + arrival time -0.018 ------------------------------------------------------------------- - slack 0.472 + slack 0.390 -Slack (MET) : 0.473ns (arrival time - required time) +Slack (MET) : 0.390ns (arrival time - required time) Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/PRE + Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/PRE (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.360ns (logic 0.128ns (35.547%) route 0.232ns (64.453%)) + Data Path Delay: 0.281ns (logic 0.148ns (52.672%) route 0.133ns (47.328%)) Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.793ns = ( -0.533 - 0.260 ) - Source Clock Delay (SCD): -0.556ns = ( -0.296 - 0.260 ) - Clock Pessimism Removal (CPR): -0.273ns + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.797ns = ( -0.537 - 0.260 ) + Source Clock Delay (SCD): -0.559ns = ( -0.299 - 0.260 ) + Clock Pessimism Removal (CPR): -0.253ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -4668,12 +4640,12 @@ Slack (MET) : 0.473ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.565 -0.296 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X9Y40 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C + net (fo=1135, routed) 0.562 -0.299 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X8Y34 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X9Y40 FDPE (Prop_fdpe_C_Q) 0.128 -0.168 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q - net (fo=3, routed) 0.232 0.064 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_d2 - SLICE_X11Y41 FDPE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/PRE + SLICE_X8Y34 FDPE (Prop_fdpe_C_Q) 0.148 -0.151 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q + net (fo=3, routed) 0.133 -0.018 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_d2 + SLICE_X8Y35 FDPE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4686,29 +4658,29 @@ Slack (MET) : 0.473ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.835 -0.533 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X11Y41 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/C - clock pessimism 0.273 -0.260 - SLICE_X11Y41 FDPE (Remov_fdpe_C_PRE) -0.149 -0.409 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg + net (fo=1135, routed) 0.831 -0.537 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X8Y35 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/C + clock pessimism 0.253 -0.284 + SLICE_X8Y35 FDPE (Remov_fdpe_C_PRE) -0.124 -0.408 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg ------------------------------------------------------------------- - required time 0.409 - arrival time 0.064 + required time 0.408 + arrival time -0.018 ------------------------------------------------------------------- - slack 0.473 + slack 0.390 -Slack (MET) : 0.473ns (arrival time - required time) - Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C +Slack (MET) : 0.452ns (arrival time - required time) + Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/PRE + Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.360ns (logic 0.128ns (35.547%) route 0.232ns (64.453%)) + Data Path Delay: 0.364ns (logic 0.128ns (35.118%) route 0.236ns (64.882%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.793ns = ( -0.533 - 0.260 ) - Source Clock Delay (SCD): -0.556ns = ( -0.296 - 0.260 ) + Destination Clock Delay (DCD): -0.769ns = ( -0.509 - 0.260 ) + Source Clock Delay (SCD): -0.532ns = ( -0.272 - 0.260 ) Clock Pessimism Removal (CPR): -0.273ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -4723,12 +4695,12 @@ Slack (MET) : 0.473ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.565 -0.296 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X9Y40 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C + net (fo=1135, routed) 0.589 -0.272 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X5Y34 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X9Y40 FDPE (Prop_fdpe_C_Q) 0.128 -0.168 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q - net (fo=3, routed) 0.232 0.064 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_d2 - SLICE_X11Y41 FDPE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/PRE + SLICE_X5Y34 FDPE (Prop_fdpe_C_Q) 0.128 -0.144 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/Q + net (fo=1, routed) 0.236 0.092 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_wr_reg2 + SLICE_X2Y33 FDPE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4741,29 +4713,29 @@ Slack (MET) : 0.473ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.835 -0.533 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X11Y41 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/C - clock pessimism 0.273 -0.260 - SLICE_X11Y41 FDPE (Remov_fdpe_C_PRE) -0.149 -0.409 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg + net (fo=1135, routed) 0.859 -0.509 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X2Y33 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/C + clock pessimism 0.273 -0.236 + SLICE_X2Y33 FDPE (Remov_fdpe_C_PRE) -0.124 -0.360 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ------------------------------------------------------------------- - required time 0.409 - arrival time 0.064 + required time 0.360 + arrival time 0.092 ------------------------------------------------------------------- - slack 0.473 + slack 0.452 -Slack (MET) : 0.486ns (arrival time - required time) - Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C +Slack (MET) : 0.500ns (arrival time - required time) + Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/C (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE + Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/PRE (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.354ns (logic 0.128ns (36.170%) route 0.226ns (63.830%)) + Data Path Delay: 0.364ns (logic 0.128ns (35.174%) route 0.236ns (64.826%)) Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.765ns = ( -0.505 - 0.260 ) - Source Clock Delay (SCD): -0.529ns = ( -0.269 - 0.260 ) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.771ns = ( -0.511 - 0.260 ) + Source Clock Delay (SCD): -0.532ns = ( -0.272 - 0.260 ) Clock Pessimism Removal (CPR): -0.252ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -4778,12 +4750,12 @@ Slack (MET) : 0.486ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.592 -0.269 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X4Y42 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C + net (fo=1135, routed) 0.589 -0.272 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X5Y34 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X4Y42 FDPE (Prop_fdpe_C_Q) 0.128 -0.141 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/Q - net (fo=1, routed) 0.226 0.085 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_wr_reg2 - SLICE_X7Y42 FDPE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE + SLICE_X5Y34 FDPE (Prop_fdpe_C_Q) 0.128 -0.144 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/Q + net (fo=1, routed) 0.236 0.092 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_rd_reg2 + SLICE_X5Y33 FDPE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4796,29 +4768,29 @@ Slack (MET) : 0.486ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.863 -0.505 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X7Y42 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/C - clock pessimism 0.252 -0.253 - SLICE_X7Y42 FDPE (Remov_fdpe_C_PRE) -0.148 -0.401 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg + net (fo=1135, routed) 0.857 -0.511 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X5Y33 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/C + clock pessimism 0.252 -0.259 + SLICE_X5Y33 FDPE (Remov_fdpe_C_PRE) -0.149 -0.408 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ------------------------------------------------------------------- - required time 0.401 - arrival time 0.085 + required time 0.408 + arrival time 0.092 ------------------------------------------------------------------- - slack 0.486 + slack 0.500 -Slack (MET) : 0.490ns (arrival time - required time) - Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/C +Slack (MET) : 0.523ns (arrival time - required time) + Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/C (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR + Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/CLR (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.432ns (logic 0.141ns (32.626%) route 0.291ns (67.374%)) + Data Path Delay: 0.438ns (logic 0.164ns (37.453%) route 0.274ns (62.547%)) Logic Levels: 0 - Clock Path Skew: 0.009ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.793ns = ( -0.533 - 0.260 ) - Source Clock Delay (SCD): -0.529ns = ( -0.269 - 0.260 ) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.799ns = ( -0.539 - 0.260 ) + Source Clock Delay (SCD): -0.533ns = ( -0.273 - 0.260 ) Clock Pessimism Removal (CPR): -0.273ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -4833,12 +4805,12 @@ Slack (MET) : 0.490ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.592 -0.269 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X7Y41 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/C + net (fo=1135, routed) 0.588 -0.273 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X6Y33 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y41 FDPE (Prop_fdpe_C_Q) 0.141 -0.128 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/Q - net (fo=14, routed) 0.291 0.163 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rd_rst_i - SLICE_X8Y41 FDCE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR + SLICE_X6Y33 FDPE (Prop_fdpe_C_Q) 0.164 -0.109 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/Q + net (fo=12, routed) 0.274 0.165 okHI/core0/core0/a0/cb0/U0/wr_rst_reg + SLICE_X9Y33 FDCE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4851,29 +4823,29 @@ Slack (MET) : 0.490ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.835 -0.533 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X8Y41 FDCE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/C - clock pessimism 0.273 -0.260 - SLICE_X8Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.327 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0] + net (fo=1135, routed) 0.829 -0.539 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X9Y33 FDCE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C + clock pessimism 0.273 -0.266 + SLICE_X9Y33 FDCE (Remov_fdce_C_CLR) -0.092 -0.358 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1] ------------------------------------------------------------------- - required time 0.327 - arrival time 0.163 + required time 0.358 + arrival time 0.165 ------------------------------------------------------------------- - slack 0.490 + slack 0.523 -Slack (MET) : 0.490ns (arrival time - required time) - Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/C +Slack (MET) : 0.523ns (arrival time - required time) + Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/C (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR + Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/CLR (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.432ns (logic 0.141ns (32.626%) route 0.291ns (67.374%)) + Data Path Delay: 0.438ns (logic 0.164ns (37.453%) route 0.274ns (62.547%)) Logic Levels: 0 - Clock Path Skew: 0.009ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.793ns = ( -0.533 - 0.260 ) - Source Clock Delay (SCD): -0.529ns = ( -0.269 - 0.260 ) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.799ns = ( -0.539 - 0.260 ) + Source Clock Delay (SCD): -0.533ns = ( -0.273 - 0.260 ) Clock Pessimism Removal (CPR): -0.273ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -4888,12 +4860,12 @@ Slack (MET) : 0.490ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.592 -0.269 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X7Y41 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/C + net (fo=1135, routed) 0.588 -0.273 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X6Y33 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y41 FDPE (Prop_fdpe_C_Q) 0.141 -0.128 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/Q - net (fo=14, routed) 0.291 0.163 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rd_rst_i - SLICE_X8Y41 FDCE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR + SLICE_X6Y33 FDPE (Prop_fdpe_C_Q) 0.164 -0.109 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/Q + net (fo=12, routed) 0.274 0.165 okHI/core0/core0/a0/cb0/U0/wr_rst_reg + SLICE_X9Y33 FDCE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4906,29 +4878,29 @@ Slack (MET) : 0.490ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.835 -0.533 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X8Y41 FDCE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/C - clock pessimism 0.273 -0.260 - SLICE_X8Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.327 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1] + net (fo=1135, routed) 0.829 -0.539 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X9Y33 FDCE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/C + clock pessimism 0.273 -0.266 + SLICE_X9Y33 FDCE (Remov_fdce_C_CLR) -0.092 -0.358 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3] ------------------------------------------------------------------- - required time 0.327 - arrival time 0.163 + required time 0.358 + arrival time 0.165 ------------------------------------------------------------------- - slack 0.490 + slack 0.523 -Slack (MET) : 0.490ns (arrival time - required time) - Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/C +Slack (MET) : 0.523ns (arrival time - required time) + Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/C (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR + Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]/CLR (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.432ns (logic 0.141ns (32.626%) route 0.291ns (67.374%)) + Data Path Delay: 0.438ns (logic 0.164ns (37.453%) route 0.274ns (62.547%)) Logic Levels: 0 - Clock Path Skew: 0.009ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.793ns = ( -0.533 - 0.260 ) - Source Clock Delay (SCD): -0.529ns = ( -0.269 - 0.260 ) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.799ns = ( -0.539 - 0.260 ) + Source Clock Delay (SCD): -0.533ns = ( -0.273 - 0.260 ) Clock Pessimism Removal (CPR): -0.273ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -4943,12 +4915,12 @@ Slack (MET) : 0.490ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.592 -0.269 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X7Y41 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/C + net (fo=1135, routed) 0.588 -0.273 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X6Y33 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y41 FDPE (Prop_fdpe_C_Q) 0.141 -0.128 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/Q - net (fo=14, routed) 0.291 0.163 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rd_rst_i - SLICE_X8Y41 FDCE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR + SLICE_X6Y33 FDPE (Prop_fdpe_C_Q) 0.164 -0.109 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/Q + net (fo=12, routed) 0.274 0.165 okHI/core0/core0/a0/cb0/U0/wr_rst_reg + SLICE_X9Y33 FDCE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -4961,29 +4933,29 @@ Slack (MET) : 0.490ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.835 -0.533 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X8Y41 FDCE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/C - clock pessimism 0.273 -0.260 - SLICE_X8Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.327 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2] + net (fo=1135, routed) 0.829 -0.539 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X9Y33 FDCE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]/C + clock pessimism 0.273 -0.266 + SLICE_X9Y33 FDCE (Remov_fdce_C_CLR) -0.092 -0.358 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1] ------------------------------------------------------------------- - required time 0.327 - arrival time 0.163 + required time 0.358 + arrival time 0.165 ------------------------------------------------------------------- - slack 0.490 + slack 0.523 -Slack (MET) : 0.490ns (arrival time - required time) - Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/C +Slack (MET) : 0.523ns (arrival time - required time) + Source: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/C (rising edge-triggered cell FDPE clocked by mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) - Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR + Destination: okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/CLR (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mmcm0_clk0 rise@0.260ns - mmcm0_clk0 rise@0.260ns) - Data Path Delay: 0.432ns (logic 0.141ns (32.626%) route 0.291ns (67.374%)) + Data Path Delay: 0.438ns (logic 0.164ns (37.453%) route 0.274ns (62.547%)) Logic Levels: 0 - Clock Path Skew: 0.009ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.793ns = ( -0.533 - 0.260 ) - Source Clock Delay (SCD): -0.529ns = ( -0.269 - 0.260 ) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.799ns = ( -0.539 - 0.260 ) + Source Clock Delay (SCD): -0.533ns = ( -0.273 - 0.260 ) Clock Pessimism Removal (CPR): -0.273ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -4998,12 +4970,12 @@ Slack (MET) : 0.490ns (arrival time - required time) -2.362 -1.376 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.489 -0.887 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.861 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.592 -0.269 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X7Y41 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/C + net (fo=1135, routed) 0.588 -0.273 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X6Y33 FDPE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y41 FDPE (Prop_fdpe_C_Q) 0.141 -0.128 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/Q - net (fo=14, routed) 0.291 0.163 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rd_rst_i - SLICE_X8Y41 FDCE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR + SLICE_X6Y33 FDPE (Prop_fdpe_C_Q) 0.164 -0.109 f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/Q + net (fo=12, routed) 0.274 0.165 okHI/core0/core0/a0/cb0/U0/wr_rst_reg + SLICE_X9Y33 FDCE f okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5016,15 +4988,15 @@ Slack (MET) : 0.490ns (arrival time - required time) -3.145 -1.930 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 -1.397 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.368 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.835 -0.533 okHI/core0/core0/a0/cb0/U0/clk - SLICE_X8Y41 FDCE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/C - clock pessimism 0.273 -0.260 - SLICE_X8Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.327 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1] + net (fo=1135, routed) 0.829 -0.539 okHI/core0/core0/a0/cb0/U0/clk + SLICE_X9Y33 FDCE r okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/C + clock pessimism 0.273 -0.266 + SLICE_X9Y33 FDCE (Remov_fdce_C_CLR) -0.092 -0.358 okHI/core0/core0/a0/cb0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3] ------------------------------------------------------------------- - required time 0.327 - arrival time 0.163 + required time 0.358 + arrival time 0.165 ------------------------------------------------------------------- - slack 0.490 + slack 0.523 @@ -5035,26 +5007,26 @@ Path Group: **async_default** From Clock: okHostClk To Clock: mmcm0_clk0 -Setup : 0 Failing Endpoints, Worst Slack 6.046ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 1.763ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 6.843ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 1.823ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 6.046ns (required time - arrival time) - Source: hi_in[4] +Slack (MET) : 6.843ns (required time - arrival time) + Source: hi_in[7] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l90ce46b343647bab4d280b5afc506219_reg/CLR + Destination: okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[5]/PRE (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 21.090ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@0.000ns) - Data Path Delay: 6.407ns (logic 1.624ns (25.349%) route 4.783ns (74.651%)) + Data Path Delay: 5.567ns (logic 1.642ns (29.504%) route 3.925ns (70.496%)) Logic Levels: 2 (IBUF=1 LUT5=1) Input Delay: 6.700ns - Clock Path Skew: -1.483ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.483ns = ( -1.223 - 0.260 ) + Clock Path Skew: -1.485ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.485ns = ( -1.225 - 0.260 ) Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5068,13 +5040,13 @@ Slack (MET) : 6.046ns (required time - arrival time) (clock okHostClk rise edge) 0.000 0.000 r input delay 6.700 6.700 - T13 0.000 6.700 f hi_in[4] (IN) - net (fo=0) 0.000 6.700 hi_in[4] - T13 IBUF (Prop_ibuf_I_O) 1.500 8.200 f hi_in_IBUF[4]_inst/O - net (fo=12, routed) 2.450 10.650 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] - SLICE_X2Y27 LUT5 (Prop_lut5_I1_O) 0.124 10.774 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.333 13.107 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X14Y46 FDCE f okHI/core0/core0/a0/l90ce46b343647bab4d280b5afc506219_reg/CLR + R10 0.000 6.700 f hi_in[7] (IN) + net (fo=0) 0.000 6.700 hi_in[7] + R10 IBUF (Prop_ibuf_I_O) 1.518 8.218 f hi_in_IBUF[7]_inst/O + net (fo=11, routed) 1.967 10.186 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[3] + SLICE_X3Y26 LUT5 (Prop_lut5_I4_O) 0.124 10.310 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 1.957 12.267 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X14Y40 FDPE f okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[5]/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5087,30 +5059,30 @@ Slack (MET) : 6.046ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.450 19.607 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X14Y46 FDCE r okHI/core0/core0/a0/l90ce46b343647bab4d280b5afc506219_reg/C - clock pessimism 0.000 19.607 - clock uncertainty -0.134 19.473 - SLICE_X14Y46 FDCE (Recov_fdce_C_CLR) -0.319 19.154 okHI/core0/core0/a0/l90ce46b343647bab4d280b5afc506219_reg + net (fo=1135, routed) 1.448 19.605 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X14Y40 FDPE r okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[5]/C + clock pessimism 0.000 19.605 + clock uncertainty -0.134 19.471 + SLICE_X14Y40 FDPE (Recov_fdpe_C_PRE) -0.361 19.110 okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[5] ------------------------------------------------------------------- - required time 19.154 - arrival time -13.107 + required time 19.110 + arrival time -12.267 ------------------------------------------------------------------- - slack 6.046 + slack 6.843 -Slack (MET) : 6.098ns (required time - arrival time) - Source: hi_in[4] +Slack (MET) : 6.843ns (required time - arrival time) + Source: hi_in[7] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l8733ba0cb25077d8c78e1b1549a80eef_reg/CLR + Destination: okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[8]/PRE (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 21.090ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@0.000ns) - Data Path Delay: 6.271ns (logic 1.624ns (25.899%) route 4.647ns (74.101%)) + Data Path Delay: 5.567ns (logic 1.642ns (29.504%) route 3.925ns (70.496%)) Logic Levels: 2 (IBUF=1 LUT5=1) Input Delay: 6.700ns - Clock Path Skew: -1.482ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( -1.222 - 0.260 ) + Clock Path Skew: -1.485ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.485ns = ( -1.225 - 0.260 ) Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5124,13 +5096,13 @@ Slack (MET) : 6.098ns (required time - arrival time) (clock okHostClk rise edge) 0.000 0.000 r input delay 6.700 6.700 - T13 0.000 6.700 f hi_in[4] (IN) - net (fo=0) 0.000 6.700 hi_in[4] - T13 IBUF (Prop_ibuf_I_O) 1.500 8.200 f hi_in_IBUF[4]_inst/O - net (fo=12, routed) 2.450 10.650 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] - SLICE_X2Y27 LUT5 (Prop_lut5_I1_O) 0.124 10.774 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.197 12.971 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X13Y48 FDCE f okHI/core0/core0/a0/l8733ba0cb25077d8c78e1b1549a80eef_reg/CLR + R10 0.000 6.700 f hi_in[7] (IN) + net (fo=0) 0.000 6.700 hi_in[7] + R10 IBUF (Prop_ibuf_I_O) 1.518 8.218 f hi_in_IBUF[7]_inst/O + net (fo=11, routed) 1.967 10.186 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[3] + SLICE_X3Y26 LUT5 (Prop_lut5_I4_O) 0.124 10.310 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 1.957 12.267 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X14Y40 FDPE f okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[8]/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5143,30 +5115,30 @@ Slack (MET) : 6.098ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y48 FDCE r okHI/core0/core0/a0/l8733ba0cb25077d8c78e1b1549a80eef_reg/C - clock pessimism 0.000 19.608 - clock uncertainty -0.134 19.474 - SLICE_X13Y48 FDCE (Recov_fdce_C_CLR) -0.405 19.069 okHI/core0/core0/a0/l8733ba0cb25077d8c78e1b1549a80eef_reg + net (fo=1135, routed) 1.448 19.605 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X14Y40 FDPE r okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[8]/C + clock pessimism 0.000 19.605 + clock uncertainty -0.134 19.471 + SLICE_X14Y40 FDPE (Recov_fdpe_C_PRE) -0.361 19.110 okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[8] ------------------------------------------------------------------- - required time 19.069 - arrival time -12.971 + required time 19.110 + arrival time -12.267 ------------------------------------------------------------------- - slack 6.098 + slack 6.843 -Slack (MET) : 6.110ns (required time - arrival time) - Source: hi_in[4] +Slack (MET) : 6.879ns (required time - arrival time) + Source: hi_in[5] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[1]/CLR + Destination: okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[32]/CLR (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 21.090ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@0.000ns) - Data Path Delay: 6.303ns (logic 1.624ns (25.767%) route 4.679ns (74.233%)) - Logic Levels: 2 (IBUF=1 LUT5=1) + Data Path Delay: 5.489ns (logic 1.639ns (29.852%) route 3.850ns (70.148%)) + Logic Levels: 2 (IBUF=1 LUT4=1) Input Delay: 6.700ns - Clock Path Skew: -1.482ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( -1.222 - 0.260 ) + Clock Path Skew: -1.483ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.483ns = ( -1.223 - 0.260 ) Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5180,13 +5152,13 @@ Slack (MET) : 6.110ns (required time - arrival time) (clock okHostClk rise edge) 0.000 0.000 r input delay 6.700 6.700 - T13 0.000 6.700 f hi_in[4] (IN) - net (fo=0) 0.000 6.700 hi_in[4] - T13 IBUF (Prop_ibuf_I_O) 1.500 8.200 f hi_in_IBUF[4]_inst/O - net (fo=12, routed) 2.450 10.650 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] - SLICE_X2Y27 LUT5 (Prop_lut5_I1_O) 0.124 10.774 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.229 13.003 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X14Y49 FDCE f okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[1]/CLR + T12 0.000 6.700 f hi_in[5] (IN) + net (fo=0) 0.000 6.700 hi_in[5] + T12 IBUF (Prop_ibuf_I_O) 1.515 8.215 f hi_in_IBUF[5]_inst/O + net (fo=12, routed) 1.967 10.182 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[1] + SLICE_X3Y28 LUT4 (Prop_lut4_I1_O) 0.124 10.306 f okHI/core0/core0/l008c72ad3b3ec61be52cde84a395c4fa_i_1/O + net (fo=93, routed) 1.883 12.189 okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 + SLICE_X13Y44 FDCE f okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5199,30 +5171,30 @@ Slack (MET) : 6.110ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X14Y49 FDCE r okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[1]/C - clock pessimism 0.000 19.608 - clock uncertainty -0.134 19.474 - SLICE_X14Y49 FDCE (Recov_fdce_C_CLR) -0.361 19.113 okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[1] + net (fo=1135, routed) 1.450 19.607 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X13Y44 FDCE r okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[32]/C + clock pessimism 0.000 19.607 + clock uncertainty -0.134 19.473 + SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 19.068 okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[32] ------------------------------------------------------------------- - required time 19.113 - arrival time -13.003 + required time 19.068 + arrival time -12.189 ------------------------------------------------------------------- - slack 6.110 + slack 6.879 -Slack (MET) : 6.110ns (required time - arrival time) - Source: hi_in[4] +Slack (MET) : 6.879ns (required time - arrival time) + Source: hi_in[5] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[3]/CLR + Destination: okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[33]/CLR (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 21.090ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@0.000ns) - Data Path Delay: 6.303ns (logic 1.624ns (25.767%) route 4.679ns (74.233%)) - Logic Levels: 2 (IBUF=1 LUT5=1) + Data Path Delay: 5.489ns (logic 1.639ns (29.852%) route 3.850ns (70.148%)) + Logic Levels: 2 (IBUF=1 LUT4=1) Input Delay: 6.700ns - Clock Path Skew: -1.482ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( -1.222 - 0.260 ) + Clock Path Skew: -1.483ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.483ns = ( -1.223 - 0.260 ) Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5236,13 +5208,13 @@ Slack (MET) : 6.110ns (required time - arrival time) (clock okHostClk rise edge) 0.000 0.000 r input delay 6.700 6.700 - T13 0.000 6.700 f hi_in[4] (IN) - net (fo=0) 0.000 6.700 hi_in[4] - T13 IBUF (Prop_ibuf_I_O) 1.500 8.200 f hi_in_IBUF[4]_inst/O - net (fo=12, routed) 2.450 10.650 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] - SLICE_X2Y27 LUT5 (Prop_lut5_I1_O) 0.124 10.774 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.229 13.003 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X14Y49 FDCE f okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[3]/CLR + T12 0.000 6.700 f hi_in[5] (IN) + net (fo=0) 0.000 6.700 hi_in[5] + T12 IBUF (Prop_ibuf_I_O) 1.515 8.215 f hi_in_IBUF[5]_inst/O + net (fo=12, routed) 1.967 10.182 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[1] + SLICE_X3Y28 LUT4 (Prop_lut4_I1_O) 0.124 10.306 f okHI/core0/core0/l008c72ad3b3ec61be52cde84a395c4fa_i_1/O + net (fo=93, routed) 1.883 12.189 okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 + SLICE_X13Y44 FDCE f okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[33]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5255,30 +5227,30 @@ Slack (MET) : 6.110ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X14Y49 FDCE r okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[3]/C - clock pessimism 0.000 19.608 - clock uncertainty -0.134 19.474 - SLICE_X14Y49 FDCE (Recov_fdce_C_CLR) -0.361 19.113 okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[3] + net (fo=1135, routed) 1.450 19.607 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X13Y44 FDCE r okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[33]/C + clock pessimism 0.000 19.607 + clock uncertainty -0.134 19.473 + SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 19.068 okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[33] ------------------------------------------------------------------- - required time 19.113 - arrival time -13.003 + required time 19.068 + arrival time -12.189 ------------------------------------------------------------------- - slack 6.110 + slack 6.879 -Slack (MET) : 6.144ns (required time - arrival time) - Source: hi_in[4] +Slack (MET) : 6.879ns (required time - arrival time) + Source: hi_in[5] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[0]/PRE + Destination: okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[34]/CLR (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 21.090ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@0.000ns) - Data Path Delay: 6.271ns (logic 1.624ns (25.899%) route 4.647ns (74.101%)) - Logic Levels: 2 (IBUF=1 LUT5=1) + Data Path Delay: 5.489ns (logic 1.639ns (29.852%) route 3.850ns (70.148%)) + Logic Levels: 2 (IBUF=1 LUT4=1) Input Delay: 6.700ns - Clock Path Skew: -1.482ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( -1.222 - 0.260 ) + Clock Path Skew: -1.483ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.483ns = ( -1.223 - 0.260 ) Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5292,13 +5264,13 @@ Slack (MET) : 6.144ns (required time - arrival time) (clock okHostClk rise edge) 0.000 0.000 r input delay 6.700 6.700 - T13 0.000 6.700 f hi_in[4] (IN) - net (fo=0) 0.000 6.700 hi_in[4] - T13 IBUF (Prop_ibuf_I_O) 1.500 8.200 f hi_in_IBUF[4]_inst/O - net (fo=12, routed) 2.450 10.650 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] - SLICE_X2Y27 LUT5 (Prop_lut5_I1_O) 0.124 10.774 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.197 12.971 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X13Y48 FDPE f okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[0]/PRE + T12 0.000 6.700 f hi_in[5] (IN) + net (fo=0) 0.000 6.700 hi_in[5] + T12 IBUF (Prop_ibuf_I_O) 1.515 8.215 f hi_in_IBUF[5]_inst/O + net (fo=12, routed) 1.967 10.182 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[1] + SLICE_X3Y28 LUT4 (Prop_lut4_I1_O) 0.124 10.306 f okHI/core0/core0/l008c72ad3b3ec61be52cde84a395c4fa_i_1/O + net (fo=93, routed) 1.883 12.189 okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 + SLICE_X13Y44 FDCE f okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[34]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5311,30 +5283,30 @@ Slack (MET) : 6.144ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y48 FDPE r okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[0]/C - clock pessimism 0.000 19.608 - clock uncertainty -0.134 19.474 - SLICE_X13Y48 FDPE (Recov_fdpe_C_PRE) -0.359 19.115 okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[0] + net (fo=1135, routed) 1.450 19.607 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X13Y44 FDCE r okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[34]/C + clock pessimism 0.000 19.607 + clock uncertainty -0.134 19.473 + SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 19.068 okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[34] ------------------------------------------------------------------- - required time 19.115 - arrival time -12.971 + required time 19.068 + arrival time -12.189 ------------------------------------------------------------------- - slack 6.144 + slack 6.879 -Slack (MET) : 6.144ns (required time - arrival time) - Source: hi_in[4] +Slack (MET) : 6.976ns (required time - arrival time) + Source: hi_in[5] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[13]/PRE + Destination: okHI/core0/core0/a0/d0/ldacb858842bc61590e084bcd54c8e356_reg/CLR (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 21.090ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@0.000ns) - Data Path Delay: 6.271ns (logic 1.624ns (25.899%) route 4.647ns (74.101%)) - Logic Levels: 2 (IBUF=1 LUT5=1) + Data Path Delay: 5.388ns (logic 1.639ns (30.408%) route 3.750ns (69.592%)) + Logic Levels: 2 (IBUF=1 LUT4=1) Input Delay: 6.700ns - Clock Path Skew: -1.482ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( -1.222 - 0.260 ) + Clock Path Skew: -1.486ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.486ns = ( -1.226 - 0.260 ) Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5348,13 +5320,13 @@ Slack (MET) : 6.144ns (required time - arrival time) (clock okHostClk rise edge) 0.000 0.000 r input delay 6.700 6.700 - T13 0.000 6.700 f hi_in[4] (IN) - net (fo=0) 0.000 6.700 hi_in[4] - T13 IBUF (Prop_ibuf_I_O) 1.500 8.200 f hi_in_IBUF[4]_inst/O - net (fo=12, routed) 2.450 10.650 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] - SLICE_X2Y27 LUT5 (Prop_lut5_I1_O) 0.124 10.774 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.197 12.971 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X13Y48 FDPE f okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[13]/PRE + T12 0.000 6.700 f hi_in[5] (IN) + net (fo=0) 0.000 6.700 hi_in[5] + T12 IBUF (Prop_ibuf_I_O) 1.515 8.215 f hi_in_IBUF[5]_inst/O + net (fo=12, routed) 1.967 10.182 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[1] + SLICE_X3Y28 LUT4 (Prop_lut4_I1_O) 0.124 10.306 f okHI/core0/core0/l008c72ad3b3ec61be52cde84a395c4fa_i_1/O + net (fo=93, routed) 1.783 12.088 okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 + SLICE_X28Y45 FDCE f okHI/core0/core0/a0/d0/ldacb858842bc61590e084bcd54c8e356_reg/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5367,30 +5339,30 @@ Slack (MET) : 6.144ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y48 FDPE r okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[13]/C - clock pessimism 0.000 19.608 - clock uncertainty -0.134 19.474 - SLICE_X13Y48 FDPE (Recov_fdpe_C_PRE) -0.359 19.115 okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[13] + net (fo=1135, routed) 1.447 19.604 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X28Y45 FDCE r okHI/core0/core0/a0/d0/ldacb858842bc61590e084bcd54c8e356_reg/C + clock pessimism 0.000 19.604 + clock uncertainty -0.134 19.470 + SLICE_X28Y45 FDCE (Recov_fdce_C_CLR) -0.405 19.065 okHI/core0/core0/a0/d0/ldacb858842bc61590e084bcd54c8e356_reg ------------------------------------------------------------------- - required time 19.115 - arrival time -12.971 + required time 19.065 + arrival time -12.088 ------------------------------------------------------------------- - slack 6.144 + slack 6.976 -Slack (MET) : 6.144ns (required time - arrival time) - Source: hi_in[4] +Slack (MET) : 6.976ns (required time - arrival time) + Source: hi_in[5] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[1]/PRE + Destination: okHI/core0/core0/a0/d0/lec61d789983ad94d0f1db17087e3c034_reg/CLR (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 21.090ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@0.000ns) - Data Path Delay: 6.271ns (logic 1.624ns (25.899%) route 4.647ns (74.101%)) - Logic Levels: 2 (IBUF=1 LUT5=1) + Data Path Delay: 5.388ns (logic 1.639ns (30.408%) route 3.750ns (69.592%)) + Logic Levels: 2 (IBUF=1 LUT4=1) Input Delay: 6.700ns - Clock Path Skew: -1.482ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( -1.222 - 0.260 ) + Clock Path Skew: -1.486ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.486ns = ( -1.226 - 0.260 ) Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5404,13 +5376,13 @@ Slack (MET) : 6.144ns (required time - arrival time) (clock okHostClk rise edge) 0.000 0.000 r input delay 6.700 6.700 - T13 0.000 6.700 f hi_in[4] (IN) - net (fo=0) 0.000 6.700 hi_in[4] - T13 IBUF (Prop_ibuf_I_O) 1.500 8.200 f hi_in_IBUF[4]_inst/O - net (fo=12, routed) 2.450 10.650 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] - SLICE_X2Y27 LUT5 (Prop_lut5_I1_O) 0.124 10.774 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.197 12.971 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X13Y48 FDPE f okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[1]/PRE + T12 0.000 6.700 f hi_in[5] (IN) + net (fo=0) 0.000 6.700 hi_in[5] + T12 IBUF (Prop_ibuf_I_O) 1.515 8.215 f hi_in_IBUF[5]_inst/O + net (fo=12, routed) 1.967 10.182 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[1] + SLICE_X3Y28 LUT4 (Prop_lut4_I1_O) 0.124 10.306 f okHI/core0/core0/l008c72ad3b3ec61be52cde84a395c4fa_i_1/O + net (fo=93, routed) 1.783 12.088 okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 + SLICE_X28Y45 FDCE f okHI/core0/core0/a0/d0/lec61d789983ad94d0f1db17087e3c034_reg/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5423,30 +5395,30 @@ Slack (MET) : 6.144ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y48 FDPE r okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[1]/C - clock pessimism 0.000 19.608 - clock uncertainty -0.134 19.474 - SLICE_X13Y48 FDPE (Recov_fdpe_C_PRE) -0.359 19.115 okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[1] + net (fo=1135, routed) 1.447 19.604 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X28Y45 FDCE r okHI/core0/core0/a0/d0/lec61d789983ad94d0f1db17087e3c034_reg/C + clock pessimism 0.000 19.604 + clock uncertainty -0.134 19.470 + SLICE_X28Y45 FDCE (Recov_fdce_C_CLR) -0.405 19.065 okHI/core0/core0/a0/d0/lec61d789983ad94d0f1db17087e3c034_reg ------------------------------------------------------------------- - required time 19.115 - arrival time -12.971 + required time 19.065 + arrival time -12.088 ------------------------------------------------------------------- - slack 6.144 + slack 6.976 -Slack (MET) : 6.144ns (required time - arrival time) - Source: hi_in[4] +Slack (MET) : 7.000ns (required time - arrival time) + Source: hi_in[5] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[6]/PRE + Destination: okHI/core0/core0/a0/d0/lfd4ae1d2a2f83cc540ba2af5c1891381_reg[1]/CLR (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 21.090ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@0.000ns) - Data Path Delay: 6.271ns (logic 1.624ns (25.899%) route 4.647ns (74.101%)) - Logic Levels: 2 (IBUF=1 LUT5=1) + Data Path Delay: 5.412ns (logic 1.639ns (30.277%) route 3.773ns (69.723%)) + Logic Levels: 2 (IBUF=1 LUT4=1) Input Delay: 6.700ns - Clock Path Skew: -1.482ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( -1.222 - 0.260 ) + Clock Path Skew: -1.483ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.483ns = ( -1.223 - 0.260 ) Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5460,13 +5432,13 @@ Slack (MET) : 6.144ns (required time - arrival time) (clock okHostClk rise edge) 0.000 0.000 r input delay 6.700 6.700 - T13 0.000 6.700 f hi_in[4] (IN) - net (fo=0) 0.000 6.700 hi_in[4] - T13 IBUF (Prop_ibuf_I_O) 1.500 8.200 f hi_in_IBUF[4]_inst/O - net (fo=12, routed) 2.450 10.650 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] - SLICE_X2Y27 LUT5 (Prop_lut5_I1_O) 0.124 10.774 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.197 12.971 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X13Y48 FDPE f okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[6]/PRE + T12 0.000 6.700 f hi_in[5] (IN) + net (fo=0) 0.000 6.700 hi_in[5] + T12 IBUF (Prop_ibuf_I_O) 1.515 8.215 f hi_in_IBUF[5]_inst/O + net (fo=12, routed) 1.967 10.182 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[1] + SLICE_X3Y28 LUT4 (Prop_lut4_I1_O) 0.124 10.306 f okHI/core0/core0/l008c72ad3b3ec61be52cde84a395c4fa_i_1/O + net (fo=93, routed) 1.806 12.112 okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 + SLICE_X14Y46 FDCE f okHI/core0/core0/a0/d0/lfd4ae1d2a2f83cc540ba2af5c1891381_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5479,30 +5451,30 @@ Slack (MET) : 6.144ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X13Y48 FDPE r okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[6]/C - clock pessimism 0.000 19.608 - clock uncertainty -0.134 19.474 - SLICE_X13Y48 FDPE (Recov_fdpe_C_PRE) -0.359 19.115 okHI/core0/core0/a0/l4f8cd1ab062f5571ff66db47e3d281bf_reg[6] + net (fo=1135, routed) 1.450 19.607 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X14Y46 FDCE r okHI/core0/core0/a0/d0/lfd4ae1d2a2f83cc540ba2af5c1891381_reg[1]/C + clock pessimism 0.000 19.607 + clock uncertainty -0.134 19.473 + SLICE_X14Y46 FDCE (Recov_fdce_C_CLR) -0.361 19.112 okHI/core0/core0/a0/d0/lfd4ae1d2a2f83cc540ba2af5c1891381_reg[1] ------------------------------------------------------------------- - required time 19.115 - arrival time -12.971 + required time 19.112 + arrival time -12.112 ------------------------------------------------------------------- - slack 6.144 + slack 7.000 -Slack (MET) : 6.152ns (required time - arrival time) - Source: hi_in[4] +Slack (MET) : 7.000ns (required time - arrival time) + Source: hi_in[5] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[0]/CLR + Destination: okHI/core0/core0/a0/d0/lfd4ae1d2a2f83cc540ba2af5c1891381_reg[2]/PRE (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 21.090ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@0.000ns) - Data Path Delay: 6.303ns (logic 1.624ns (25.767%) route 4.679ns (74.233%)) - Logic Levels: 2 (IBUF=1 LUT5=1) + Data Path Delay: 5.412ns (logic 1.639ns (30.277%) route 3.773ns (69.723%)) + Logic Levels: 2 (IBUF=1 LUT4=1) Input Delay: 6.700ns - Clock Path Skew: -1.482ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( -1.222 - 0.260 ) + Clock Path Skew: -1.483ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.483ns = ( -1.223 - 0.260 ) Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5516,13 +5488,13 @@ Slack (MET) : 6.152ns (required time - arrival time) (clock okHostClk rise edge) 0.000 0.000 r input delay 6.700 6.700 - T13 0.000 6.700 f hi_in[4] (IN) - net (fo=0) 0.000 6.700 hi_in[4] - T13 IBUF (Prop_ibuf_I_O) 1.500 8.200 f hi_in_IBUF[4]_inst/O - net (fo=12, routed) 2.450 10.650 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] - SLICE_X2Y27 LUT5 (Prop_lut5_I1_O) 0.124 10.774 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.229 13.003 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X14Y49 FDCE f okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[0]/CLR + T12 0.000 6.700 f hi_in[5] (IN) + net (fo=0) 0.000 6.700 hi_in[5] + T12 IBUF (Prop_ibuf_I_O) 1.515 8.215 f hi_in_IBUF[5]_inst/O + net (fo=12, routed) 1.967 10.182 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[1] + SLICE_X3Y28 LUT4 (Prop_lut4_I1_O) 0.124 10.306 f okHI/core0/core0/l008c72ad3b3ec61be52cde84a395c4fa_i_1/O + net (fo=93, routed) 1.806 12.112 okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 + SLICE_X14Y46 FDPE f okHI/core0/core0/a0/d0/lfd4ae1d2a2f83cc540ba2af5c1891381_reg[2]/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5535,30 +5507,30 @@ Slack (MET) : 6.152ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X14Y49 FDCE r okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[0]/C - clock pessimism 0.000 19.608 - clock uncertainty -0.134 19.474 - SLICE_X14Y49 FDCE (Recov_fdce_C_CLR) -0.319 19.155 okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[0] + net (fo=1135, routed) 1.450 19.607 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X14Y46 FDPE r okHI/core0/core0/a0/d0/lfd4ae1d2a2f83cc540ba2af5c1891381_reg[2]/C + clock pessimism 0.000 19.607 + clock uncertainty -0.134 19.473 + SLICE_X14Y46 FDPE (Recov_fdpe_C_PRE) -0.361 19.112 okHI/core0/core0/a0/d0/lfd4ae1d2a2f83cc540ba2af5c1891381_reg[2] ------------------------------------------------------------------- - required time 19.155 - arrival time -13.003 + required time 19.112 + arrival time -12.112 ------------------------------------------------------------------- - slack 6.152 + slack 7.000 -Slack (MET) : 6.152ns (required time - arrival time) - Source: hi_in[4] +Slack (MET) : 7.002ns (required time - arrival time) + Source: hi_in[5] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[2]/CLR + Destination: okHI/core0/core0/a0/d0/lfd4ae1d2a2f83cc540ba2af5c1891381_reg[3]/PRE (recovery check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 21.090ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@0.000ns) - Data Path Delay: 6.303ns (logic 1.624ns (25.767%) route 4.679ns (74.233%)) - Logic Levels: 2 (IBUF=1 LUT5=1) + Data Path Delay: 5.412ns (logic 1.639ns (30.277%) route 3.773ns (69.723%)) + Logic Levels: 2 (IBUF=1 LUT4=1) Input Delay: 6.700ns - Clock Path Skew: -1.482ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.482ns = ( -1.222 - 0.260 ) + Clock Path Skew: -1.483ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.483ns = ( -1.223 - 0.260 ) Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5572,13 +5544,13 @@ Slack (MET) : 6.152ns (required time - arrival time) (clock okHostClk rise edge) 0.000 0.000 r input delay 6.700 6.700 - T13 0.000 6.700 f hi_in[4] (IN) - net (fo=0) 0.000 6.700 hi_in[4] - T13 IBUF (Prop_ibuf_I_O) 1.500 8.200 f hi_in_IBUF[4]_inst/O - net (fo=12, routed) 2.450 10.650 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] - SLICE_X2Y27 LUT5 (Prop_lut5_I1_O) 0.124 10.774 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 2.229 13.003 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X14Y49 FDCE f okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[2]/CLR + T12 0.000 6.700 f hi_in[5] (IN) + net (fo=0) 0.000 6.700 hi_in[5] + T12 IBUF (Prop_ibuf_I_O) 1.515 8.215 f hi_in_IBUF[5]_inst/O + net (fo=12, routed) 1.967 10.182 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[1] + SLICE_X3Y28 LUT4 (Prop_lut4_I1_O) 0.124 10.306 f okHI/core0/core0/l008c72ad3b3ec61be52cde84a395c4fa_i_1/O + net (fo=93, routed) 1.806 12.112 okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 + SLICE_X15Y46 FDPE f okHI/core0/core0/a0/d0/lfd4ae1d2a2f83cc540ba2af5c1891381_reg[3]/PRE ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5591,16 +5563,16 @@ Slack (MET) : 6.152ns (required time - arrival time) -7.221 16.479 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 1.587 18.066 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 18.157 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 1.451 19.608 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X14Y49 FDCE r okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[2]/C - clock pessimism 0.000 19.608 - clock uncertainty -0.134 19.474 - SLICE_X14Y49 FDCE (Recov_fdce_C_CLR) -0.319 19.155 okHI/core0/core0/a0/l9ca09c625f64b90bed25f2b6c26f6e53_reg[2] + net (fo=1135, routed) 1.450 19.607 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X15Y46 FDPE r okHI/core0/core0/a0/d0/lfd4ae1d2a2f83cc540ba2af5c1891381_reg[3]/C + clock pessimism 0.000 19.607 + clock uncertainty -0.134 19.473 + SLICE_X15Y46 FDPE (Recov_fdpe_C_PRE) -0.359 19.114 okHI/core0/core0/a0/d0/lfd4ae1d2a2f83cc540ba2af5c1891381_reg[3] ------------------------------------------------------------------- - required time 19.155 - arrival time -13.003 + required time 19.114 + arrival time -12.112 ------------------------------------------------------------------- - slack 6.152 + slack 7.002 @@ -5608,19 +5580,19 @@ Slack (MET) : 6.152ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 1.763ns (arrival time - required time) - Source: hi_in[6] +Slack (MET) : 1.823ns (arrival time - required time) + Source: hi_in[4] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[0]/CLR + Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[20]/CLR (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.260ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@20.830ns) - Data Path Delay: 1.302ns (logic 0.341ns (26.227%) route 0.960ns (73.773%)) + Data Path Delay: 1.328ns (logic 0.313ns (23.561%) route 1.015ns (76.439%)) Logic Levels: 2 (IBUF=1 LUT5=1) Input Delay: 0.000ns - Clock Path Skew: -0.764ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.764ns = ( -0.504 - 0.260 ) + Clock Path Skew: -0.798ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.798ns = ( -0.538 - 0.260 ) Source Clock Delay (SCD): 0.000ns = ( 20.830 - 20.830 ) Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5634,13 +5606,13 @@ Slack (MET) : 1.763ns (arrival time - required time) (clock okHostClk rise edge) 20.830 20.830 r input delay 0.000 20.830 - P11 0.000 20.830 f hi_in[6] (IN) - net (fo=0) 0.000 20.830 hi_in[6] - P11 IBUF (Prop_ibuf_I_O) 0.296 21.126 f hi_in_IBUF[6]_inst/O - net (fo=11, routed) 0.578 21.704 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[2] - SLICE_X2Y27 LUT5 (Prop_lut5_I3_O) 0.045 21.749 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 0.382 22.132 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X3Y38 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[0]/CLR + T13 0.000 20.830 f hi_in[4] (IN) + net (fo=0) 0.000 20.830 hi_in[4] + T13 IBUF (Prop_ibuf_I_O) 0.268 21.098 f hi_in_IBUF[4]_inst/O + net (fo=12, routed) 0.526 21.624 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] + SLICE_X3Y26 LUT5 (Prop_lut5_I1_O) 0.045 21.669 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 0.489 22.158 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X13Y34 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5653,30 +5625,30 @@ Slack (MET) : 1.763ns (arrival time - required time) -3.145 18.900 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 19.433 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 19.462 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.864 20.326 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X3Y38 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[0]/C - clock pessimism 0.000 20.326 - clock uncertainty 0.134 20.460 - SLICE_X3Y38 FDCE (Remov_fdce_C_CLR) -0.092 20.368 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[0] + net (fo=1135, routed) 0.830 20.292 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X13Y34 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[20]/C + clock pessimism 0.000 20.292 + clock uncertainty 0.134 20.426 + SLICE_X13Y34 FDCE (Remov_fdce_C_CLR) -0.092 20.334 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[20] ------------------------------------------------------------------- - required time -20.368 - arrival time 22.132 + required time -20.334 + arrival time 22.158 ------------------------------------------------------------------- - slack 1.763 + slack 1.823 -Slack (MET) : 1.763ns (arrival time - required time) - Source: hi_in[6] +Slack (MET) : 1.823ns (arrival time - required time) + Source: hi_in[4] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[1]/CLR + Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[21]/CLR (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.260ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@20.830ns) - Data Path Delay: 1.302ns (logic 0.341ns (26.227%) route 0.960ns (73.773%)) + Data Path Delay: 1.328ns (logic 0.313ns (23.561%) route 1.015ns (76.439%)) Logic Levels: 2 (IBUF=1 LUT5=1) Input Delay: 0.000ns - Clock Path Skew: -0.764ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.764ns = ( -0.504 - 0.260 ) + Clock Path Skew: -0.798ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.798ns = ( -0.538 - 0.260 ) Source Clock Delay (SCD): 0.000ns = ( 20.830 - 20.830 ) Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5690,13 +5662,13 @@ Slack (MET) : 1.763ns (arrival time - required time) (clock okHostClk rise edge) 20.830 20.830 r input delay 0.000 20.830 - P11 0.000 20.830 f hi_in[6] (IN) - net (fo=0) 0.000 20.830 hi_in[6] - P11 IBUF (Prop_ibuf_I_O) 0.296 21.126 f hi_in_IBUF[6]_inst/O - net (fo=11, routed) 0.578 21.704 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[2] - SLICE_X2Y27 LUT5 (Prop_lut5_I3_O) 0.045 21.749 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 0.382 22.132 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X3Y38 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[1]/CLR + T13 0.000 20.830 f hi_in[4] (IN) + net (fo=0) 0.000 20.830 hi_in[4] + T13 IBUF (Prop_ibuf_I_O) 0.268 21.098 f hi_in_IBUF[4]_inst/O + net (fo=12, routed) 0.526 21.624 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] + SLICE_X3Y26 LUT5 (Prop_lut5_I1_O) 0.045 21.669 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 0.489 22.158 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X13Y34 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5709,30 +5681,30 @@ Slack (MET) : 1.763ns (arrival time - required time) -3.145 18.900 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 19.433 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 19.462 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.864 20.326 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X3Y38 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[1]/C - clock pessimism 0.000 20.326 - clock uncertainty 0.134 20.460 - SLICE_X3Y38 FDCE (Remov_fdce_C_CLR) -0.092 20.368 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[1] + net (fo=1135, routed) 0.830 20.292 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X13Y34 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[21]/C + clock pessimism 0.000 20.292 + clock uncertainty 0.134 20.426 + SLICE_X13Y34 FDCE (Remov_fdce_C_CLR) -0.092 20.334 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[21] ------------------------------------------------------------------- - required time -20.368 - arrival time 22.132 + required time -20.334 + arrival time 22.158 ------------------------------------------------------------------- - slack 1.763 + slack 1.823 -Slack (MET) : 1.763ns (arrival time - required time) - Source: hi_in[6] +Slack (MET) : 1.823ns (arrival time - required time) + Source: hi_in[4] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[2]/CLR + Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[22]/CLR (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.260ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@20.830ns) - Data Path Delay: 1.302ns (logic 0.341ns (26.227%) route 0.960ns (73.773%)) + Data Path Delay: 1.328ns (logic 0.313ns (23.561%) route 1.015ns (76.439%)) Logic Levels: 2 (IBUF=1 LUT5=1) Input Delay: 0.000ns - Clock Path Skew: -0.764ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.764ns = ( -0.504 - 0.260 ) + Clock Path Skew: -0.798ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.798ns = ( -0.538 - 0.260 ) Source Clock Delay (SCD): 0.000ns = ( 20.830 - 20.830 ) Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5746,13 +5718,13 @@ Slack (MET) : 1.763ns (arrival time - required time) (clock okHostClk rise edge) 20.830 20.830 r input delay 0.000 20.830 - P11 0.000 20.830 f hi_in[6] (IN) - net (fo=0) 0.000 20.830 hi_in[6] - P11 IBUF (Prop_ibuf_I_O) 0.296 21.126 f hi_in_IBUF[6]_inst/O - net (fo=11, routed) 0.578 21.704 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[2] - SLICE_X2Y27 LUT5 (Prop_lut5_I3_O) 0.045 21.749 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 0.382 22.132 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X3Y38 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[2]/CLR + T13 0.000 20.830 f hi_in[4] (IN) + net (fo=0) 0.000 20.830 hi_in[4] + T13 IBUF (Prop_ibuf_I_O) 0.268 21.098 f hi_in_IBUF[4]_inst/O + net (fo=12, routed) 0.526 21.624 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] + SLICE_X3Y26 LUT5 (Prop_lut5_I1_O) 0.045 21.669 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 0.489 22.158 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X13Y34 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[22]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5765,30 +5737,30 @@ Slack (MET) : 1.763ns (arrival time - required time) -3.145 18.900 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 19.433 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 19.462 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.864 20.326 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X3Y38 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[2]/C - clock pessimism 0.000 20.326 - clock uncertainty 0.134 20.460 - SLICE_X3Y38 FDCE (Remov_fdce_C_CLR) -0.092 20.368 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[2] + net (fo=1135, routed) 0.830 20.292 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X13Y34 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[22]/C + clock pessimism 0.000 20.292 + clock uncertainty 0.134 20.426 + SLICE_X13Y34 FDCE (Remov_fdce_C_CLR) -0.092 20.334 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[22] ------------------------------------------------------------------- - required time -20.368 - arrival time 22.132 + required time -20.334 + arrival time 22.158 ------------------------------------------------------------------- - slack 1.763 + slack 1.823 -Slack (MET) : 1.763ns (arrival time - required time) - Source: hi_in[6] +Slack (MET) : 1.823ns (arrival time - required time) + Source: hi_in[4] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[3]/CLR + Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[23]/CLR (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.260ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@20.830ns) - Data Path Delay: 1.302ns (logic 0.341ns (26.227%) route 0.960ns (73.773%)) + Data Path Delay: 1.328ns (logic 0.313ns (23.561%) route 1.015ns (76.439%)) Logic Levels: 2 (IBUF=1 LUT5=1) Input Delay: 0.000ns - Clock Path Skew: -0.764ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.764ns = ( -0.504 - 0.260 ) + Clock Path Skew: -0.798ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.798ns = ( -0.538 - 0.260 ) Source Clock Delay (SCD): 0.000ns = ( 20.830 - 20.830 ) Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5802,13 +5774,13 @@ Slack (MET) : 1.763ns (arrival time - required time) (clock okHostClk rise edge) 20.830 20.830 r input delay 0.000 20.830 - P11 0.000 20.830 f hi_in[6] (IN) - net (fo=0) 0.000 20.830 hi_in[6] - P11 IBUF (Prop_ibuf_I_O) 0.296 21.126 f hi_in_IBUF[6]_inst/O - net (fo=11, routed) 0.578 21.704 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[2] - SLICE_X2Y27 LUT5 (Prop_lut5_I3_O) 0.045 21.749 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 0.382 22.132 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X3Y38 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[3]/CLR + T13 0.000 20.830 f hi_in[4] (IN) + net (fo=0) 0.000 20.830 hi_in[4] + T13 IBUF (Prop_ibuf_I_O) 0.268 21.098 f hi_in_IBUF[4]_inst/O + net (fo=12, routed) 0.526 21.624 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] + SLICE_X3Y26 LUT5 (Prop_lut5_I1_O) 0.045 21.669 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 0.489 22.158 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X13Y34 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5821,30 +5793,30 @@ Slack (MET) : 1.763ns (arrival time - required time) -3.145 18.900 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 19.433 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 19.462 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.864 20.326 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X3Y38 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[3]/C - clock pessimism 0.000 20.326 - clock uncertainty 0.134 20.460 - SLICE_X3Y38 FDCE (Remov_fdce_C_CLR) -0.092 20.368 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[3] + net (fo=1135, routed) 0.830 20.292 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X13Y34 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[23]/C + clock pessimism 0.000 20.292 + clock uncertainty 0.134 20.426 + SLICE_X13Y34 FDCE (Remov_fdce_C_CLR) -0.092 20.334 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[23] ------------------------------------------------------------------- - required time -20.368 - arrival time 22.132 + required time -20.334 + arrival time 22.158 ------------------------------------------------------------------- - slack 1.763 + slack 1.823 -Slack (MET) : 1.811ns (arrival time - required time) - Source: hi_in[6] +Slack (MET) : 1.835ns (arrival time - required time) + Source: hi_in[4] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[10]/CLR + Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[4]/CLR (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.260ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@20.830ns) - Data Path Delay: 1.351ns (logic 0.341ns (25.274%) route 1.009ns (74.726%)) + Data Path Delay: 1.336ns (logic 0.313ns (23.422%) route 1.023ns (76.578%)) Logic Levels: 2 (IBUF=1 LUT5=1) Input Delay: 0.000ns - Clock Path Skew: -0.763ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.763ns = ( -0.503 - 0.260 ) + Clock Path Skew: -0.802ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.802ns = ( -0.542 - 0.260 ) Source Clock Delay (SCD): 0.000ns = ( 20.830 - 20.830 ) Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5858,13 +5830,13 @@ Slack (MET) : 1.811ns (arrival time - required time) (clock okHostClk rise edge) 20.830 20.830 r input delay 0.000 20.830 - P11 0.000 20.830 f hi_in[6] (IN) - net (fo=0) 0.000 20.830 hi_in[6] - P11 IBUF (Prop_ibuf_I_O) 0.296 21.126 f hi_in_IBUF[6]_inst/O - net (fo=11, routed) 0.578 21.704 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[2] - SLICE_X2Y27 LUT5 (Prop_lut5_I3_O) 0.045 21.749 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 0.432 22.181 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X3Y40 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[10]/CLR + T13 0.000 20.830 f hi_in[4] (IN) + net (fo=0) 0.000 20.830 hi_in[4] + T13 IBUF (Prop_ibuf_I_O) 0.268 21.098 f hi_in_IBUF[4]_inst/O + net (fo=12, routed) 0.526 21.624 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] + SLICE_X3Y26 LUT5 (Prop_lut5_I1_O) 0.045 21.669 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 0.497 22.166 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X13Y30 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5877,30 +5849,30 @@ Slack (MET) : 1.811ns (arrival time - required time) -3.145 18.900 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 19.433 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 19.462 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.865 20.327 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X3Y40 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[10]/C - clock pessimism 0.000 20.327 - clock uncertainty 0.134 20.461 - SLICE_X3Y40 FDCE (Remov_fdce_C_CLR) -0.092 20.369 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[10] + net (fo=1135, routed) 0.826 20.288 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X13Y30 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[4]/C + clock pessimism 0.000 20.288 + clock uncertainty 0.134 20.422 + SLICE_X13Y30 FDCE (Remov_fdce_C_CLR) -0.092 20.330 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[4] ------------------------------------------------------------------- - required time -20.369 - arrival time 22.181 + required time -20.330 + arrival time 22.166 ------------------------------------------------------------------- - slack 1.811 + slack 1.835 -Slack (MET) : 1.811ns (arrival time - required time) - Source: hi_in[6] +Slack (MET) : 1.835ns (arrival time - required time) + Source: hi_in[4] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[11]/CLR + Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[5]/CLR (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.260ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@20.830ns) - Data Path Delay: 1.351ns (logic 0.341ns (25.274%) route 1.009ns (74.726%)) + Data Path Delay: 1.336ns (logic 0.313ns (23.422%) route 1.023ns (76.578%)) Logic Levels: 2 (IBUF=1 LUT5=1) Input Delay: 0.000ns - Clock Path Skew: -0.763ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.763ns = ( -0.503 - 0.260 ) + Clock Path Skew: -0.802ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.802ns = ( -0.542 - 0.260 ) Source Clock Delay (SCD): 0.000ns = ( 20.830 - 20.830 ) Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5914,13 +5886,13 @@ Slack (MET) : 1.811ns (arrival time - required time) (clock okHostClk rise edge) 20.830 20.830 r input delay 0.000 20.830 - P11 0.000 20.830 f hi_in[6] (IN) - net (fo=0) 0.000 20.830 hi_in[6] - P11 IBUF (Prop_ibuf_I_O) 0.296 21.126 f hi_in_IBUF[6]_inst/O - net (fo=11, routed) 0.578 21.704 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[2] - SLICE_X2Y27 LUT5 (Prop_lut5_I3_O) 0.045 21.749 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 0.432 22.181 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X3Y40 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[11]/CLR + T13 0.000 20.830 f hi_in[4] (IN) + net (fo=0) 0.000 20.830 hi_in[4] + T13 IBUF (Prop_ibuf_I_O) 0.268 21.098 f hi_in_IBUF[4]_inst/O + net (fo=12, routed) 0.526 21.624 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] + SLICE_X3Y26 LUT5 (Prop_lut5_I1_O) 0.045 21.669 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 0.497 22.166 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X13Y30 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5933,30 +5905,30 @@ Slack (MET) : 1.811ns (arrival time - required time) -3.145 18.900 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 19.433 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 19.462 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.865 20.327 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X3Y40 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[11]/C - clock pessimism 0.000 20.327 - clock uncertainty 0.134 20.461 - SLICE_X3Y40 FDCE (Remov_fdce_C_CLR) -0.092 20.369 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[11] + net (fo=1135, routed) 0.826 20.288 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X13Y30 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[5]/C + clock pessimism 0.000 20.288 + clock uncertainty 0.134 20.422 + SLICE_X13Y30 FDCE (Remov_fdce_C_CLR) -0.092 20.330 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[5] ------------------------------------------------------------------- - required time -20.369 - arrival time 22.181 + required time -20.330 + arrival time 22.166 ------------------------------------------------------------------- - slack 1.811 + slack 1.835 -Slack (MET) : 1.811ns (arrival time - required time) - Source: hi_in[6] +Slack (MET) : 1.835ns (arrival time - required time) + Source: hi_in[4] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[8]/CLR + Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[6]/CLR (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.260ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@20.830ns) - Data Path Delay: 1.351ns (logic 0.341ns (25.274%) route 1.009ns (74.726%)) + Data Path Delay: 1.336ns (logic 0.313ns (23.422%) route 1.023ns (76.578%)) Logic Levels: 2 (IBUF=1 LUT5=1) Input Delay: 0.000ns - Clock Path Skew: -0.763ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.763ns = ( -0.503 - 0.260 ) + Clock Path Skew: -0.802ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.802ns = ( -0.542 - 0.260 ) Source Clock Delay (SCD): 0.000ns = ( 20.830 - 20.830 ) Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -5970,13 +5942,13 @@ Slack (MET) : 1.811ns (arrival time - required time) (clock okHostClk rise edge) 20.830 20.830 r input delay 0.000 20.830 - P11 0.000 20.830 f hi_in[6] (IN) - net (fo=0) 0.000 20.830 hi_in[6] - P11 IBUF (Prop_ibuf_I_O) 0.296 21.126 f hi_in_IBUF[6]_inst/O - net (fo=11, routed) 0.578 21.704 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[2] - SLICE_X2Y27 LUT5 (Prop_lut5_I3_O) 0.045 21.749 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 0.432 22.181 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X3Y40 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[8]/CLR + T13 0.000 20.830 f hi_in[4] (IN) + net (fo=0) 0.000 20.830 hi_in[4] + T13 IBUF (Prop_ibuf_I_O) 0.268 21.098 f hi_in_IBUF[4]_inst/O + net (fo=12, routed) 0.526 21.624 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] + SLICE_X3Y26 LUT5 (Prop_lut5_I1_O) 0.045 21.669 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 0.497 22.166 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X13Y30 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -5989,30 +5961,30 @@ Slack (MET) : 1.811ns (arrival time - required time) -3.145 18.900 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 19.433 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 19.462 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.865 20.327 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X3Y40 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[8]/C - clock pessimism 0.000 20.327 - clock uncertainty 0.134 20.461 - SLICE_X3Y40 FDCE (Remov_fdce_C_CLR) -0.092 20.369 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[8] + net (fo=1135, routed) 0.826 20.288 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X13Y30 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[6]/C + clock pessimism 0.000 20.288 + clock uncertainty 0.134 20.422 + SLICE_X13Y30 FDCE (Remov_fdce_C_CLR) -0.092 20.330 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[6] ------------------------------------------------------------------- - required time -20.369 - arrival time 22.181 + required time -20.330 + arrival time 22.166 ------------------------------------------------------------------- - slack 1.811 + slack 1.835 -Slack (MET) : 1.811ns (arrival time - required time) - Source: hi_in[6] +Slack (MET) : 1.835ns (arrival time - required time) + Source: hi_in[4] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[9]/CLR + Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[7]/CLR (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.260ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@20.830ns) - Data Path Delay: 1.351ns (logic 0.341ns (25.274%) route 1.009ns (74.726%)) + Data Path Delay: 1.336ns (logic 0.313ns (23.422%) route 1.023ns (76.578%)) Logic Levels: 2 (IBUF=1 LUT5=1) Input Delay: 0.000ns - Clock Path Skew: -0.763ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.763ns = ( -0.503 - 0.260 ) + Clock Path Skew: -0.802ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.802ns = ( -0.542 - 0.260 ) Source Clock Delay (SCD): 0.000ns = ( 20.830 - 20.830 ) Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -6026,13 +5998,13 @@ Slack (MET) : 1.811ns (arrival time - required time) (clock okHostClk rise edge) 20.830 20.830 r input delay 0.000 20.830 - P11 0.000 20.830 f hi_in[6] (IN) - net (fo=0) 0.000 20.830 hi_in[6] - P11 IBUF (Prop_ibuf_I_O) 0.296 21.126 f hi_in_IBUF[6]_inst/O - net (fo=11, routed) 0.578 21.704 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[2] - SLICE_X2Y27 LUT5 (Prop_lut5_I3_O) 0.045 21.749 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 0.432 22.181 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X3Y40 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[9]/CLR + T13 0.000 20.830 f hi_in[4] (IN) + net (fo=0) 0.000 20.830 hi_in[4] + T13 IBUF (Prop_ibuf_I_O) 0.268 21.098 f hi_in_IBUF[4]_inst/O + net (fo=12, routed) 0.526 21.624 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[0] + SLICE_X3Y26 LUT5 (Prop_lut5_I1_O) 0.045 21.669 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O + net (fo=60, routed) 0.497 22.166 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 + SLICE_X13Y30 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -6045,30 +6017,30 @@ Slack (MET) : 1.811ns (arrival time - required time) -3.145 18.900 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 19.433 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 19.462 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.865 20.327 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X3Y40 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[9]/C - clock pessimism 0.000 20.327 - clock uncertainty 0.134 20.461 - SLICE_X3Y40 FDCE (Remov_fdce_C_CLR) -0.092 20.369 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[9] + net (fo=1135, routed) 0.826 20.288 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X13Y30 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[7]/C + clock pessimism 0.000 20.288 + clock uncertainty 0.134 20.422 + SLICE_X13Y30 FDCE (Remov_fdce_C_CLR) -0.092 20.330 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[7] ------------------------------------------------------------------- - required time -20.369 - arrival time 22.181 + required time -20.330 + arrival time 22.166 ------------------------------------------------------------------- - slack 1.811 + slack 1.835 -Slack (MET) : 1.844ns (arrival time - required time) +Slack (MET) : 1.853ns (arrival time - required time) Source: hi_in[6] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[24]/CLR + Destination: okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[20]/CLR (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.260ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@20.830ns) - Data Path Delay: 1.385ns (logic 0.341ns (24.655%) route 1.043ns (75.345%)) - Logic Levels: 2 (IBUF=1 LUT5=1) + Data Path Delay: 1.416ns (logic 0.341ns (24.108%) route 1.075ns (75.892%)) + Logic Levels: 2 (IBUF=1 LUT4=1) Input Delay: 0.000ns - Clock Path Skew: -0.762ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.762ns = ( -0.502 - 0.260 ) + Clock Path Skew: -0.764ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.764ns = ( -0.504 - 0.260 ) Source Clock Delay (SCD): 0.000ns = ( 20.830 - 20.830 ) Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -6085,10 +6057,10 @@ Slack (MET) : 1.844ns (arrival time - required time) P11 0.000 20.830 f hi_in[6] (IN) net (fo=0) 0.000 20.830 hi_in[6] P11 IBUF (Prop_ibuf_I_O) 0.296 21.126 f hi_in_IBUF[6]_inst/O - net (fo=11, routed) 0.578 21.704 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[2] - SLICE_X2Y27 LUT5 (Prop_lut5_I3_O) 0.045 21.749 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 0.465 22.215 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X3Y44 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[24]/CLR + net (fo=11, routed) 0.585 21.711 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[2] + SLICE_X3Y28 LUT4 (Prop_lut4_I2_O) 0.045 21.756 f okHI/core0/core0/l008c72ad3b3ec61be52cde84a395c4fa_i_1/O + net (fo=93, routed) 0.490 22.246 okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 + SLICE_X6Y46 FDCE f okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -6101,30 +6073,30 @@ Slack (MET) : 1.844ns (arrival time - required time) -3.145 18.900 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 19.433 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 19.462 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.866 20.328 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X3Y44 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[24]/C - clock pessimism 0.000 20.328 - clock uncertainty 0.134 20.462 - SLICE_X3Y44 FDCE (Remov_fdce_C_CLR) -0.092 20.370 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[24] + net (fo=1135, routed) 0.864 20.326 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X6Y46 FDCE r okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[20]/C + clock pessimism 0.000 20.326 + clock uncertainty 0.134 20.460 + SLICE_X6Y46 FDCE (Remov_fdce_C_CLR) -0.067 20.393 okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[20] ------------------------------------------------------------------- - required time -20.370 - arrival time 22.215 + required time -20.393 + arrival time 22.246 ------------------------------------------------------------------- - slack 1.844 + slack 1.853 -Slack (MET) : 1.844ns (arrival time - required time) +Slack (MET) : 1.853ns (arrival time - required time) Source: hi_in[6] (input port clocked by okHostClk {rise@0.000ns fall@10.415ns period=20.830ns}) - Destination: okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[25]/CLR + Destination: okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[21]/CLR (removal check against rising-edge clock mmcm0_clk0 {rise@0.260ns fall@10.675ns period=20.830ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.260ns (mmcm0_clk0 rise@21.090ns - okHostClk rise@20.830ns) - Data Path Delay: 1.385ns (logic 0.341ns (24.655%) route 1.043ns (75.345%)) - Logic Levels: 2 (IBUF=1 LUT5=1) + Data Path Delay: 1.416ns (logic 0.341ns (24.108%) route 1.075ns (75.892%)) + Logic Levels: 2 (IBUF=1 LUT4=1) Input Delay: 0.000ns - Clock Path Skew: -0.762ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.762ns = ( -0.502 - 0.260 ) + Clock Path Skew: -0.764ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.764ns = ( -0.504 - 0.260 ) Source Clock Delay (SCD): 0.000ns = ( 20.830 - 20.830 ) Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.134ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -6141,10 +6113,10 @@ Slack (MET) : 1.844ns (arrival time - required time) P11 0.000 20.830 f hi_in[6] (IN) net (fo=0) 0.000 20.830 hi_in[6] P11 IBUF (Prop_ibuf_I_O) 0.296 21.126 f hi_in_IBUF[6]_inst/O - net (fo=11, routed) 0.578 21.704 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[2] - SLICE_X2Y27 LUT5 (Prop_lut5_I3_O) 0.045 21.749 f okHI/core0/core0/l9ca09c625f64b90bed25f2b6c26f6e53[3]_i_2/O - net (fo=60, routed) 0.465 22.215 okHI/core0/core0/a0/lc12c7095b9bc056c60880aeb6055afb1 - SLICE_X3Y44 FDCE f okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[25]/CLR + net (fo=11, routed) 0.585 21.711 okHI/core0/core0/l53f03e7bfee57ef62086f575f0ec7cf5[2] + SLICE_X3Y28 LUT4 (Prop_lut4_I2_O) 0.045 21.756 f okHI/core0/core0/l008c72ad3b3ec61be52cde84a395c4fa_i_1/O + net (fo=93, routed) 0.490 22.246 okHI/core0/core0/lab4325c385c0fcaa4cd26acd21308822 + SLICE_X6Y46 FDCE f okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm0_clk0 rise edge) @@ -6157,16 +6129,16 @@ Slack (MET) : 1.844ns (arrival time - required time) -3.145 18.900 r okHI/mmcm0/CLKOUT0 net (fo=1, routed) 0.534 19.433 okHI/mmcm0_clk0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 19.462 r okHI/mmcm0_bufg/O - net (fo=1135, routed) 0.866 20.328 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff - SLICE_X3Y44 FDCE r okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[25]/C - clock pessimism 0.000 20.328 - clock uncertainty 0.134 20.462 - SLICE_X3Y44 FDCE (Remov_fdce_C_CLR) -0.092 20.370 okHI/core0/core0/a0/l0c94b19b36beba84283b1c1a65aa73f3_reg[25] + net (fo=1135, routed) 0.864 20.326 okHI/core0/core0/lec70dee01afd7ab45446d779af5292ff + SLICE_X6Y46 FDCE r okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[21]/C + clock pessimism 0.000 20.326 + clock uncertainty 0.134 20.460 + SLICE_X6Y46 FDCE (Remov_fdce_C_CLR) -0.067 20.393 okHI/core0/core0/a0/d0/le5e2e6110dd7478b8ed0143f21b04d30_reg[21] ------------------------------------------------------------------- - required time -20.370 - arrival time 22.215 + required time -20.393 + arrival time 22.246 ------------------------------------------------------------------- - slack 1.844 + slack 1.853 diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_timing_summary_routed.rpx b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_timing_summary_routed.rpx index 4336dfa..bb584ee 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_timing_summary_routed.rpx and b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_timing_summary_routed.rpx differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_utilization_placed.pb b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_utilization_placed.pb index dfb8a75..167f5a5 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_utilization_placed.pb and b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_utilization_placed.pb differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_utilization_placed.rpt b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_utilization_placed.rpt index ba1d792..b5c4350 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_utilization_placed.rpt +++ b/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_utilization_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -| Date : Tue Feb 26 23:49:22 2019 +| Date : Tue Mar 19 19:00:08 2019 | Host : EECS-TOYODA running 64-bit major release (build 9200) | Command : report_utilization -file OSC1_LITE_Control_utilization_placed.rpt -pb OSC1_LITE_Control_utilization_placed.pb | Design : OSC1_LITE_Control @@ -31,8 +31,8 @@ Table of Contents +----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------------------+------+-------+-----------+-------+ -| Slice LUTs | 1220 | 0 | 10400 | 11.73 | -| LUT as Logic | 1188 | 0 | 10400 | 11.42 | +| Slice LUTs | 1195 | 0 | 10400 | 11.49 | +| LUT as Logic | 1163 | 0 | 10400 | 11.18 | | LUT as Memory | 32 | 0 | 9600 | 0.33 | | LUT as Distributed RAM | 32 | 0 | | | | LUT as Shift Register | 0 | 0 | | | @@ -69,23 +69,23 @@ Table of Contents +-------------------------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------------------------+------+-------+-----------+-------+ -| Slice | 464 | 0 | 8150 | 5.69 | -| SLICEL | 281 | 0 | | | -| SLICEM | 183 | 0 | | | -| LUT as Logic | 1188 | 0 | 10400 | 11.42 | +| Slice | 460 | 0 | 8150 | 5.64 | +| SLICEL | 290 | 0 | | | +| SLICEM | 170 | 0 | | | +| LUT as Logic | 1163 | 0 | 10400 | 11.18 | | using O5 output only | 2 | | | | -| using O6 output only | 959 | | | | -| using O5 and O6 | 227 | | | | +| using O6 output only | 932 | | | | +| using O5 and O6 | 229 | | | | | LUT as Memory | 32 | 0 | 9600 | 0.33 | | LUT as Distributed RAM | 32 | 0 | | | | using O5 output only | 0 | | | | | using O6 output only | 16 | | | | | using O5 and O6 | 16 | | | | | LUT as Shift Register | 0 | 0 | | | -| LUT Flip Flop Pairs | 329 | 0 | 10400 | 3.16 | -| fully used LUT-FF pairs | 53 | | | | -| LUT-FF pairs with one unused LUT output | 236 | | | | -| LUT-FF pairs with one unused Flip Flop | 250 | | | | +| LUT Flip Flop Pairs | 322 | 0 | 10400 | 3.10 | +| fully used LUT-FF pairs | 54 | | | | +| LUT-FF pairs with one unused LUT output | 224 | | | | +| LUT-FF pairs with one unused Flip Flop | 246 | | | | | Unique Control Sets | 78 | | | | +-------------------------------------------+------+-------+-----------+-------+ * Note: Review the Control Sets Report for more information regarding control sets. @@ -122,9 +122,9 @@ Table of Contents +-----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 86 | 86 | 170 | 50.59 | -| IOB Master Pads | 42 | | | | -| IOB Slave Pads | 42 | | | | +| Bonded IOB | 85 | 85 | 170 | 50.00 | +| IOB Master Pads | 38 | | | | +| IOB Slave Pads | 45 | | | | | IOB Flip Flops | 48 | 48 | | | | Bonded IPADs | 0 | 0 | 2 | 0.00 | | PHY_CONTROL | 0 | 0 | 5 | 0.00 | @@ -185,13 +185,13 @@ Table of Contents | Ref Name | Used | Functional Category | +------------+------+---------------------+ | FDRE | 1009 | Flop & Latch | -| LUT6 | 625 | LUT | -| LUT5 | 271 | LUT | -| LUT4 | 198 | LUT | -| LUT2 | 142 | LUT | +| LUT6 | 600 | LUT | +| LUT5 | 268 | LUT | +| LUT4 | 200 | LUT | +| LUT3 | 140 | LUT | +| LUT2 | 138 | LUT | | FDCE | 138 | Flop & Latch | -| LUT3 | 133 | LUT | -| OBUF | 60 | IO | +| OBUF | 59 | IO | | CARRY4 | 50 | CarryLogic | | LUT1 | 46 | LUT | | FDPE | 44 | Flop & Latch | diff --git a/project_LITE/project_LITE/17.runs/impl_1/gen_run.xml b/project_LITE/project_LITE/17.runs/impl_1/gen_run.xml index 1eb4d17..6d953b3 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/gen_run.xml +++ b/project_LITE/project_LITE/17.runs/impl_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/project_LITE/project_LITE/17.runs/impl_1/init_design.pb b/project_LITE/project_LITE/17.runs/impl_1/init_design.pb index d986d2c..0bef85b 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/init_design.pb and b/project_LITE/project_LITE/17.runs/impl_1/init_design.pb differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/opt_design.pb b/project_LITE/project_LITE/17.runs/impl_1/opt_design.pb index f22f1e5..02d6be5 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/opt_design.pb and b/project_LITE/project_LITE/17.runs/impl_1/opt_design.pb differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/place_design.pb b/project_LITE/project_LITE/17.runs/impl_1/place_design.pb index cd796a0..a0ebc1a 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/place_design.pb and b/project_LITE/project_LITE/17.runs/impl_1/place_design.pb differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/route_design.pb b/project_LITE/project_LITE/17.runs/impl_1/route_design.pb index d3a871d..39fd3a2 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/route_design.pb and b/project_LITE/project_LITE/17.runs/impl_1/route_design.pb differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/runme.log b/project_LITE/project_LITE/17.runs/impl_1/runme.log index 212b7da..ff8ee25 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/runme.log +++ b/project_LITE/project_LITE/17.runs/impl_1/runme.log @@ -36,7 +36,7 @@ INFO: [Project 1-111] Unisim Transformation Summary: RAM128X1S => RAM128X1S (MUXF7, RAMS64E, RAMS64E): 8 instances RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 4 instances -link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 548.047 ; gain = 269.277 +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 547.402 ; gain = 269.234 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a15t-ftg256' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a15t-ftg256' @@ -49,7 +49,7 @@ report_drc (run_mandatory_drcs) completed successfully INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.639 . Memory (MB): peak = 555.684 ; gain = 7.637 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.629 . Memory (MB): peak = 556.043 ; gain = 8.641 WARNING: [Constraints 18-96] Setting input delay on a clock pin 'hi_in[0]' is not supported, ignoring it [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc:62] WARNING: [Constraints 18-96] Setting input delay on a clock pin 'hi_in[0]' is not supported, ignoring it [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc:63] INFO: [Timing 38-35] Done setting XDC timing constraints. @@ -60,42 +60,42 @@ Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 1a82c521a +Phase 1 Retarget | Checksum: 1845d7467 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.158 . Memory (MB): peak = 1046.324 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 2 cells and removed 66 cells +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 1045.680 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 2 cells and removed 67 cells Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 1aaed84c9 +Phase 2 Constant propagation | Checksum: 177ed596e -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.257 . Memory (MB): peak = 1046.324 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.254 . Memory (MB): peak = 1045.680 ; gain = 0.000 INFO: [Opt 31-389] Phase Constant propagation created 76 cells and removed 77 cells Phase 3 Sweep -Phase 3 Sweep | Checksum: 266f4e701 +Phase 3 Sweep | Checksum: e32de73f -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.327 . Memory (MB): peak = 1046.324 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.322 . Memory (MB): peak = 1045.680 ; gain = 0.000 INFO: [Opt 31-389] Phase Sweep created 11 cells and removed 0 cells Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: 266f4e701 +Phase 4 BUFG optimization | Checksum: e32de73f -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.397 . Memory (MB): peak = 1046.324 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.391 . Memory (MB): peak = 1045.680 ; gain = 0.000 INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 266f4e701 +Phase 5 Shift Register Optimization | Checksum: e32de73f -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.404 . Memory (MB): peak = 1046.324 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.399 . Memory (MB): peak = 1045.680 ; gain = 0.000 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1046.324 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 266f4e701 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1045.680 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: e32de73f -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.423 . Memory (MB): peak = 1046.324 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.416 . Memory (MB): peak = 1045.680 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. @@ -116,20 +116,20 @@ INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 18 newly gated: 0 Total Ports: 38 Number of Flops added for Enable Generation: 3 -Ending PowerOpt Patch Enables Task | Checksum: 1ad897823 +Ending PowerOpt Patch Enables Task | Checksum: 260b35149 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Ending Power Optimization Task | Checksum: 1ad897823 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Ending Power Optimization Task | Checksum: 260b35149 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1247.527 ; gain = 201.203 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1247.879 ; gain = 202.199 28 Infos, 14 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1247.527 ; gain = 699.480 +opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 1247.879 ; gain = 700.477 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1247.879 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_opt.dcp' has been generated. Command: report_drc -file OSC1_LITE_Control_drc_opted.rpt INFO: [DRC 23-27] Running DRC with 2 threads @@ -180,86 +180,86 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 161fcd502 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 18b9a3b4a -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1247.879 ; gain = 0.000 WARNING: [Constraints 18-96] Setting input delay on a clock pin 'hi_in[0]' is not supported, ignoring it [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc:62] WARNING: [Constraints 18-96] Setting input delay on a clock pin 'hi_in[0]' is not supported, ignoring it [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc:63] INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Constraints 18-96] Setting input delay on a clock pin 'hi_in[0]' is not supported, ignoring it [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc:62] WARNING: [Constraints 18-96] Setting input delay on a clock pin 'hi_in[0]' is not supported, ignoring it [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc:63] INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 16e8bdae +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 9f21476c -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 7a13381b +Phase 1.3 Build Placer Netlist Model | Checksum: dd897aae -Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 7a13381b +Phase 1.4 Constrain Clocks/Macros | Checksum: dd897aae -Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 7a13381b +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: dd897aae -Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 2 Global Placement -Phase 2 Global Placement | Checksum: 1575c98f9 +Phase 2 Global Placement | Checksum: 161ea7302 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1575c98f9 +Phase 3.1 Commit Multi Column Macros | Checksum: 161ea7302 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 14ca29543 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d299fe5f -Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 14364e2bb +Phase 3.3 Area Swap Optimization | Checksum: 1c065a22a -Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 14364e2bb +Phase 3.4 Pipeline Register Optimization | Checksum: 1c065a22a -Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3.5 Timing Path Optimizer -Phase 3.5 Timing Path Optimizer | Checksum: 138095cda +Phase 3.5 Timing Path Optimizer | Checksum: 17e484897 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3.6 Small Shape Detail Placement -Phase 3.6 Small Shape Detail Placement | Checksum: 142dc307f +Phase 3.6 Small Shape Detail Placement | Checksum: 1150f4aff -Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3.7 Re-assign LUT pins -Phase 3.7 Re-assign LUT pins | Checksum: 20c5de9e4 +Phase 3.7 Re-assign LUT pins | Checksum: 14525aa86 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3.8 Pipeline Register Optimization -Phase 3.8 Pipeline Register Optimization | Checksum: 20c5de9e4 +Phase 3.8 Pipeline Register Optimization | Checksum: 14525aa86 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 20c5de9e4 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 14525aa86 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up @@ -269,54 +269,54 @@ WARNING: [Constraints 18-96] Setting input delay on a clock pin 'hi_in[0]' is no INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 214a915e2 +Post Placement Optimization Initialization | Checksum: 11c17ef76 Phase 4.1.1.1 BUFG Insertion INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs INFO: [Place 46-41] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason. -Phase 4.1.1.1 BUFG Insertion | Checksum: 214a915e2 +Phase 4.1.1.1 BUFG Insertion | Checksum: 11c17ef76 -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=6.488. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 1f6251c1c +Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 1247.879 ; gain = 0.000 +INFO: [Place 30-746] Post Placement Timing Summary WNS=6.539. For the most accurate timing information please run report_timing. +Phase 4.1.1 Post Placement Optimization | Checksum: 11c5cb6bd -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 1f6251c1c +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 4.1 Post Commit Optimization | Checksum: 11c5cb6bd -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 1f6251c1c +Phase 4.2 Post Placement Cleanup | Checksum: 11c5cb6bd -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 1f6251c1c +Phase 4.3 Placer Reporting | Checksum: 11c5cb6bd -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 4.4 Final Placement Cleanup -Phase 4.4 Final Placement Cleanup | Checksum: 1ee1ec375 +Phase 4.4 Final Placement Cleanup | Checksum: 1c5593bbf -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ee1ec375 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c5593bbf -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Ending Placer Task | Checksum: 1e0381668 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Ending Placer Task | Checksum: 14ec85742 -Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 47 Infos, 41 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 1247.527 ; gain = 0.000 +place_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 1247.879 ; gain = 0.000 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.219 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.222 . Memory (MB): peak = 1247.879 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_placed.dcp' has been generated. -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 1247.527 ; gain = 0.000 -report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1247.527 ; gain = 0.000 -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1247.527 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 1247.879 ; gain = 0.000 +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1247.879 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1247.879 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a15t-ftg256' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a15t-ftg256' @@ -330,106 +330,106 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: f7cfd457 ConstDB: 0 ShapeSum: e8684211 RouteDB: 0 +Checksum: PlaceDB: 610971b1 ConstDB: 0 ShapeSum: edbee591 RouteDB: 0 Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: ce9f5ced +Phase 1 Build RT Design | Checksum: cf2ab54c -Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 2 Router Initialization Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: ce9f5ced +Phase 2.1 Create Timer | Checksum: cf2ab54c -Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: ce9f5ced +Phase 2.2 Fix Topology Constraints | Checksum: cf2ab54c -Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: ce9f5ced +Phase 2.3 Pre Route Cleanup | Checksum: cf2ab54c -Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1247.879 ; gain = 0.000 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 24b10bc53 +Phase 2.4 Update Timing | Checksum: 14230ddb3 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 1247.527 ; gain = 0.000 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.428 | TNS=0.000 | WHS=-0.301 | THS=-40.864| +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1247.879 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.825 | TNS=0.000 | WHS=-0.268 | THS=-32.833| -Phase 2 Router Initialization | Checksum: 209af61fd +Phase 2 Router Initialization | Checksum: 1ee0c9a73 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 1a29fc651 +Phase 3 Initial Routing | Checksum: c324d9b7 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 270 - Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 294 + Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.044 | TNS=0.000 | WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.824 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 4.1 Global Iteration 0 | Checksum: 227ecdcf0 +Phase 4.1 Global Iteration 0 | Checksum: 14f66a31b -Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:21 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.044 | TNS=0.000 | WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.824 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 4.2 Global Iteration 1 | Checksum: 1b6d530ce +Phase 4.2 Global Iteration 1 | Checksum: 11a732228 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 4 Rip-up And Reroute | Checksum: 1b6d530ce +Time (s): cpu = 00:00:21 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 4 Rip-up And Reroute | Checksum: 11a732228 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:21 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 1b6d530ce +Phase 5.1 Delay CleanUp | Checksum: 11a732228 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:21 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 1b6d530ce +Phase 5.2 Clock Skew Optimization | Checksum: 11a732228 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 5 Delay and Skew Optimization | Checksum: 1b6d530ce +Time (s): cpu = 00:00:21 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 5 Delay and Skew Optimization | Checksum: 11a732228 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:21 ; elapsed = 00:00:17 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: ffd9e20b +Phase 6.1.1 Update Timing | Checksum: a1403f47 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.044 | TNS=0.000 | WHS=0.054 | THS=0.000 | +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.824 | TNS=0.000 | WHS=0.106 | THS=0.000 | -Phase 6.1 Hold Fix Iter | Checksum: e8854e5f +Phase 6.1 Hold Fix Iter | Checksum: 115dda551 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 -Phase 6 Post Hold Fix | Checksum: e8854e5f +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 +Phase 6 Post Hold Fix | Checksum: 115dda551 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 0.865742 % - Global Horizontal Routing Utilization = 1.01171 % + Global Vertical Routing Utilization = 0.838795 % + Global Horizontal Routing Utilization = 0.989198 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -438,42 +438,42 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 7 Route finalize | Checksum: 10818e42a +Phase 7 Route finalize | Checksum: f00684ef -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 10818e42a +Phase 8 Verifying routed nets | Checksum: f00684ef -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 9083587e +Phase 9 Depositing Routes | Checksum: 188d5b631 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=6.044 | TNS=0.000 | WHS=0.054 | THS=0.000 | +INFO: [Route 35-57] Estimated Timing Summary | WNS=6.824 | TNS=0.000 | WHS=0.106 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 9083587e +Phase 10 Post Router Timing | Checksum: 188d5b631 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 INFO: [Route 35-16] Router Completed Successfully -Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1247.879 ; gain = 0.000 Routing Is Done. 60 Infos, 41 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 1247.527 ; gain = 0.000 +route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 1247.879 ; gain = 0.000 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.290 . Memory (MB): peak = 1247.527 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.296 . Memory (MB): peak = 1247.879 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control_routed.dcp' has been generated. Command: report_drc -file OSC1_LITE_Control_drc_routed.rpt -pb OSC1_LITE_Control_drc_routed.pb -rpx OSC1_LITE_Control_drc_routed.rpx INFO: [DRC 23-27] Running DRC with 2 threads @@ -545,12 +545,12 @@ Loading route data... Processing options... Creating bitmap... Creating bitstream... -Bitstream compression saved 11789856 bits. +Bitstream compression saved 12204480 bits. Writing bitstream ./OSC1_LITE_Control.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). -INFO: [Common 17-186] 'C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Feb 26 23:50:00 2019. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. +INFO: [Common 17-186] 'C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 19 19:00:48 2019. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 79 Infos, 67 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 1542.754 ; gain = 295.227 -INFO: [Common 17-206] Exiting Vivado at Tue Feb 26 23:50:00 2019... +write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1552.297 ; gain = 304.418 +INFO: [Common 17-206] Exiting Vivado at Tue Mar 19 19:00:48 2019... diff --git a/project_LITE/project_LITE/17.runs/impl_1/usage_statistics_webtalk.html b/project_LITE/project_LITE/17.runs/impl_1/usage_statistics_webtalk.html index 024523e..edc87ba 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/usage_statistics_webtalk.html +++ b/project_LITE/project_LITE/17.runs/impl_1/usage_statistics_webtalk.html @@ -4,11 +4,11 @@ software_version_and_target_device betaFALSE build_version1909853 - date_generatedTue Feb 26 23:49:59 2019 + date_generatedTue Mar 19 19:00:46 2019 os_platformWIN64 product_versionVivado v2017.2 (64-bit) project_ide01f3dc1d4d1413e83d79e6bb536698a - project_iteration51 + project_iteration52 random_id33e93362255e57b6a09d416d451fb9c5 registration_id210948875_0_0_032 route_designTRUE @@ -40,16 +40,16 @@ newiplocationhandler=1 newproject=1 openipxactfile=1 - openproject=10 + openproject=11 recustomizecore=5 - runbitgen=69 + runbitgen=71 runimplementation=1 runnoiseanalysis=1 savefileproxyhandler=6 saveprojectas=1 showcompatiblefamilies=1 showproductguide=1 - showview=19 + showview=20 timingconstraintswizard=1 toolssettings=6 updatesourcefiles=3 @@ -58,7 +58,7 @@ - +
other_data
guimode=27
guimode=28
@@ -105,15 +105,15 @@ - - - - - - + + + + + + - + @@ -135,15 +135,15 @@ - - - - - - + + + + + + - + @@ -317,10 +317,9 @@
project_data
fdre=999 gnd=49 ibuf=26
lut1=110lut2=122lut3=92lut4=215
lut5=276lut6=674
lut1=111lut2=118lut3=99lut4=217
lut5=273lut6=649 mmcme2_adv=1 muxf7=8
obuf=60
obuf=59 obuft=17 ramb18e1=3 ramb36e1=16gnd=49 ibuf=9
iobuf=17lut1=110lut2=122lut3=92
lut4=215lut5=226lut6=624lut1=111lut2=118lut3=99
lut4=217lut5=223lut6=599 lut6_2=50
mmcme2_adv=1obuf=60obuf=59 ram128x1s=8 ram32m=4
ramb18e1=3
- - + - +
results
timing-17=142timing-18=46xdcc-5=2timing-18=45 xdch-1=2
xdch-2=18xdch-2=18

@@ -354,7 +353,7 @@ board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.000128 - clocks=0.002310 + clocks=0.002326 confidence_level_clock_activity=Medium confidence_level_design_state=High confidence_level_device_models=High @@ -366,17 +365,17 @@ devstatic=0.072816 die=xc7a15tftg256-1 dsp_output_toggle=12.500000 - dynamic=0.130385 + dynamic=0.130263 effective_thetaja=4.9 enable_probability=0.990000 family=artix7 ff_toggle=12.500000 flow_state=routed heatsink=medium (Medium Profile) - i/o=0.019793 + i/o=0.019852 input_toggle=12.500000 junction_temp=26.0 (C) - logic=0.002566 + logic=0.002490 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000 @@ -388,7 +387,7 @@ mmcm=0.103040 netlist_net_matched=NA off-chip_power=0.000000 - on-chip_power=0.203201 + on-chip_power=0.203078 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000 @@ -402,7 +401,7 @@ read_saif=False set/reset_probability=0.000000 signal_rate=False - signals=0.002548 + signals=0.002426 simulation_file=None speedgrade=-1 static_prob=False @@ -419,21 +418,21 @@ vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000 - vccaux_dynamic_current=0.057841 + vccaux_dynamic_current=0.057843 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.012632 - vccaux_total_current=0.070472 + vccaux_total_current=0.070475 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000010 vccbram_static_current=0.000580 vccbram_total_current=0.000590 vccbram_voltage=1.000000 - vccint_dynamic_current=0.008206 - vccint_static_current=0.010200 - vccint_total_current=0.018406 + vccint_dynamic_current=0.008025 + vccint_static_current=0.010199 + vccint_total_current=0.018224 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 @@ -455,9 +454,9 @@ vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000 - vcco33_dynamic_current=0.005471 + vcco33_dynamic_current=0.005488 vcco33_static_current=0.001000 - vcco33_total_current=0.006471 + vcco33_total_current=0.006488 vcco33_voltage=3.300000 version=2017.2 @@ -588,21 +587,21 @@ lut1_functional_category=LUT lut1_used=46 lut2_functional_category=LUT - lut2_used=142 + lut2_used=138 lut3_functional_category=LUT - lut3_used=133 + lut3_used=140 lut4_functional_category=LUT - lut4_used=198 + lut4_used=200 lut5_functional_category=LUT - lut5_used=271 + lut5_used=268 lut6_functional_category=LUT - lut6_used=625 + lut6_used=600 mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 muxf7_functional_category=MuxFx muxf7_used=8 obuf_functional_category=IO - obuf_used=60 + obuf_used=59 obuft_functional_category=IO obuft_used=17 ramb18e1_functional_category=Block Memory @@ -632,8 +631,8 @@ lut_as_distributed_ram_used=32 lut_as_logic_available=10400 lut_as_logic_fixed=0 - lut_as_logic_used=1188 - lut_as_logic_util_percentage=11.42 + lut_as_logic_used=1163 + lut_as_logic_util_percentage=11.18 lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=32 @@ -650,20 +649,20 @@ register_as_latch_util_percentage=0.00 slice_luts_available=10400 slice_luts_fixed=0 - slice_luts_used=1220 - slice_luts_util_percentage=11.73 + slice_luts_used=1195 + slice_luts_util_percentage=11.49 slice_registers_available=20800 slice_registers_fixed=0 slice_registers_used=1143 slice_registers_util_percentage=5.50 fully_used_lut_ff_pairs_fixed=5.50 - fully_used_lut_ff_pairs_used=53 + fully_used_lut_ff_pairs_used=54 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=32 lut_as_logic_available=10400 lut_as_logic_fixed=0 - lut_as_logic_used=1188 - lut_as_logic_util_percentage=11.42 + lut_as_logic_used=1163 + lut_as_logic_util_percentage=11.18 lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=32 @@ -671,21 +670,21 @@ lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 - lut_ff_pairs_with_one_unused_flip_flop_used=250 - lut_ff_pairs_with_one_unused_lut_output_fixed=250 - lut_ff_pairs_with_one_unused_lut_output_used=236 + lut_ff_pairs_with_one_unused_flip_flop_used=246 + lut_ff_pairs_with_one_unused_lut_output_fixed=246 + lut_ff_pairs_with_one_unused_lut_output_used=224 lut_flip_flop_pairs_available=10400 lut_flip_flop_pairs_fixed=0 - lut_flip_flop_pairs_used=329 - lut_flip_flop_pairs_util_percentage=3.16 + lut_flip_flop_pairs_used=322 + lut_flip_flop_pairs_util_percentage=3.10 slice_available=8150 slice_fixed=0 - slice_used=464 - slice_util_percentage=5.69 + slice_used=460 + slice_util_percentage=5.64 slicel_fixed=0 - slicel_used=281 + slicel_used=290 slicem_fixed=0 - slicem_used=183 + slicem_used=170 unique_control_sets_used=78 using_o5_and_o6_fixed=78 using_o5_and_o6_used=16 @@ -742,7 +741,7 @@ - + @@ -752,15 +751,15 @@ - + - - - - - + + + + + @@ -815,8 +814,8 @@ - - + +
usage
actual_expansions=2772573
actual_expansions=2686625 bogomips=0 bram18=3 bram36=16ctrls=78
dsp=0 effort=2estimated_expansions=2643330estimated_expansions=2572134 ff=1191
global_clocks=5 high_fanout_nets=2iob=86lut=1345
movable_instances=2927nets=3241pins=19837iob=85lut=1321
movable_instances=2903nets=3217pins=19668 pll=0
router_runtime=0.000000 router_timing_driven=1
usage
elapsed=00:01:22s hls_ip=0memory_gain=446.660MBmemory_peak=725.402MBmemory_gain=445.867MBmemory_peak=725.047MB

diff --git a/project_LITE/project_LITE/17.runs/impl_1/usage_statistics_webtalk.xml b/project_LITE/project_LITE/17.runs/impl_1/usage_statistics_webtalk.xml index b3404cf..65e4542 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/usage_statistics_webtalk.xml +++ b/project_LITE/project_LITE/17.runs/impl_1/usage_statistics_webtalk.xml @@ -1,14 +1,14 @@ - +
- + - + @@ -167,8 +167,7 @@
- - +
@@ -197,7 +196,7 @@ - + @@ -209,17 +208,17 @@ - + - + - + @@ -231,7 +230,7 @@ - + @@ -245,7 +244,7 @@ - + @@ -262,21 +261,21 @@ - + - + - - - + + + @@ -298,9 +297,9 @@ - + - +
@@ -415,21 +414,21 @@ - + - + - + - + - + - + @@ -453,7 +452,7 @@ - + @@ -462,10 +461,10 @@ - - - - + + + + @@ -479,13 +478,13 @@ - - - + + + - - + + @@ -498,18 +497,18 @@ - - + + - - + + - + - + @@ -559,7 +558,7 @@
- + @@ -569,15 +568,15 @@ - + - - - - - + + + + + @@ -625,8 +624,8 @@
- - + +
@@ -639,15 +638,15 @@ - - - - - - + + + + + + - + @@ -666,15 +665,15 @@ - - - - - - + + + + + + - + @@ -693,16 +692,16 @@ - + - + - + @@ -710,7 +709,7 @@
- +
diff --git a/project_LITE/project_LITE/17.runs/impl_1/vivado.jou b/project_LITE/project_LITE/17.runs/impl_1/vivado.jou index afd8dca..feedefc 100755 --- a/project_LITE/project_LITE/17.runs/impl_1/vivado.jou +++ b/project_LITE/project_LITE/17.runs/impl_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2017.2 (64-bit) # SW Build 1909853 on Thu Jun 15 18:39:09 MDT 2017 # IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 -# Start of session at: Tue Feb 26 23:48:47 2019 -# Process ID: 46356 +# Start of session at: Tue Mar 19 18:59:33 2019 +# Process ID: 44628 # Current directory: C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/impl_1 # Command line: vivado.exe -log OSC1_LITE_Control.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source OSC1_LITE_Control.tcl -notrace # Log file: C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/impl_1/OSC1_LITE_Control.vdi diff --git a/project_LITE/project_LITE/17.runs/impl_1/vivado.pb b/project_LITE/project_LITE/17.runs/impl_1/vivado.pb index 7590418..0ec0dfc 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/vivado.pb and b/project_LITE/project_LITE/17.runs/impl_1/vivado.pb differ diff --git a/project_LITE/project_LITE/17.runs/impl_1/write_bitstream.pb b/project_LITE/project_LITE/17.runs/impl_1/write_bitstream.pb index fe11082..b3fb67d 100755 Binary files a/project_LITE/project_LITE/17.runs/impl_1/write_bitstream.pb and b/project_LITE/project_LITE/17.runs/impl_1/write_bitstream.pb differ diff --git a/project_LITE/project_LITE/17.runs/synth_1/.Xil/OSC1_LITE_Control_propImpl.xdc b/project_LITE/project_LITE/17.runs/synth_1/.Xil/OSC1_LITE_Control_propImpl.xdc index 3b08d2d..6c95f40 100755 --- a/project_LITE/project_LITE/17.runs/synth_1/.Xil/OSC1_LITE_Control_propImpl.xdc +++ b/project_LITE/project_LITE/17.runs/synth_1/.Xil/OSC1_LITE_Control_propImpl.xdc @@ -57,140 +57,126 @@ set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ set_property PACKAGE_PIN M15 [get_ports {hi_aa}] set_property src_info {type:XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN N14 [get_ports {clk}] -set_property src_info {type:XDC file:1 line:91 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN H1 [get_ports {sdo_bit[7]}] -set_property src_info {type:XDC file:1 line:95 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN H2 [get_ports {sclk[8]}] -set_property src_info {type:XDC file:1 line:99 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN G1 [get_ports {din[7]}] -set_property src_info {type:XDC file:1 line:103 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN G2 [get_ports {din[8]}] -set_property src_info {type:XDC file:1 line:107 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN F2 [get_ports {sclk[7]}] -set_property src_info {type:XDC file:1 line:111 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN E1 [get_ports {sdo_bit[8]}] -set_property src_info {type:XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN E2 [get_ports {latch[7]}] -set_property src_info {type:XDC file:1 line:119 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN D1 [get_ports {clear[6]}] -set_property src_info {type:XDC file:1 line:123 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN C1 [get_ports {clear[7]}] -set_property src_info {type:XDC file:1 line:127 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN C2 [get_ports {latch[6]}] -set_property src_info {type:XDC file:1 line:131 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN B1 [get_ports {sdo_bit[10]}] -set_property src_info {type:XDC file:1 line:135 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN B2 [get_ports {sclk[6]}] set_property src_info {type:XDC file:1 line:139 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN A2 [get_ports {din[10]}] -set_property src_info {type:XDC file:1 line:143 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN A3 [get_ports {din[6]}] +set_property PACKAGE_PIN A2 [get_ports {latch[4]}] set_property src_info {type:XDC file:1 line:147 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN D4 [get_ports {sclk[10]}] +set_property PACKAGE_PIN D4 [get_ports {din[4]}] set_property src_info {type:XDC file:1 line:151 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN C4 [get_ports {sdo_bit[6]}] -set_property src_info {type:XDC file:1 line:183 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN J3 [get_ports {latch[8]}] -set_property src_info {type:XDC file:1 line:191 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN K1 [get_ports {clear[8]}] +set_property PACKAGE_PIN C4 [get_ports {sclk[5]}] +set_property src_info {type:XDC file:1 line:259 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R2 [get_ports {sdo_bit[2]}] +set_property src_info {type:XDC file:1 line:263 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P3 [get_ports {din[2]}] +set_property src_info {type:XDC file:1 line:267 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN T2 [get_ports {sclk[2]}] +set_property src_info {type:XDC file:1 line:271 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R3 [get_ports {latch[2]}] set_property src_info {type:XDC file:1 line:275 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN T3 [get_ports {latch[10]}] +set_property PACKAGE_PIN T3 [get_ports {clear[2]}] +set_property src_info {type:XDC file:1 line:279 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN N4 [get_ports {sdo_bit[1]}] set_property src_info {type:XDC file:1 line:291 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN P4 [get_ports {khan}] +set_property PACKAGE_PIN P4 [get_ports {din[1]}] set_property src_info {type:XDC file:1 line:295 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN T4 [get_ports {khan}] +set_property PACKAGE_PIN T4 [get_ports {sclk[1]}] set_property src_info {type:XDC file:1 line:299 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN P5 [get_ports {khan}] +set_property PACKAGE_PIN P5 [get_ports {latch[1]}] set_property src_info {type:XDC file:1 line:303 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN N6 [get_ports {clear[9]}] +set_property PACKAGE_PIN N6 [get_ports {clear[1]}] set_property src_info {type:XDC file:1 line:307 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN R5 [get_ports {khan}] +set_property PACKAGE_PIN R5 [get_ports {sdo_bit[0]}] set_property src_info {type:XDC file:1 line:311 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN P8 [get_ports {latch[9]}] +set_property PACKAGE_PIN P8 [get_ports {din[0]}] set_property src_info {type:XDC file:1 line:315 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN T5 [get_ports {khan}] +set_property PACKAGE_PIN T5 [get_ports {sclk[0]}] set_property src_info {type:XDC file:1 line:319 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN R6 [get_ports {sclk[9]}] +set_property PACKAGE_PIN R6 [get_ports {latch[0]}] set_property src_info {type:XDC file:1 line:331 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN T9 [get_ports {khan}] +set_property PACKAGE_PIN T9 [get_ports {clear[0]}] set_property src_info {type:XDC file:1 line:335 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN R7 [get_ports {din[9]}] +set_property PACKAGE_PIN R7 [get_ports {clear[6]}] +set_property src_info {type:XDC file:1 line:339 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN T7 [get_ports {latch[6]}] set_property src_info {type:XDC file:1 line:343 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN R8 [get_ports {sdo_bit[9]}] +set_property PACKAGE_PIN R8 [get_ports {sclk[6]}] +set_property src_info {type:XDC file:1 line:347 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN T8 [get_ports {sdo_bit[6]}] +set_property src_info {type:XDC file:1 line:351 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN T10 [get_ports {din[6]}] set_property src_info {type:XDC file:1 line:371 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN A8 [get_ports {sdo_bit[4]}] +set_property PACKAGE_PIN A8 [get_ports {sdo_bit[5]}] set_property src_info {type:XDC file:1 line:375 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN D9 [get_ports {clear[5]}] +set_property PACKAGE_PIN D9 [get_ports {clear[11]}] set_property src_info {type:XDC file:1 line:379 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN C8 [get_ports {din[4]}] +set_property PACKAGE_PIN C8 [get_ports {din[5]}] set_property src_info {type:XDC file:1 line:383 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN D10 [get_ports {latch[5]}] +set_property PACKAGE_PIN D10 [get_ports {latch[11]}] set_property src_info {type:XDC file:1 line:387 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN A9 [get_ports {sclk[4]}] +set_property PACKAGE_PIN A9 [get_ports {clear[5]}] set_property src_info {type:XDC file:1 line:391 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN C9 [get_ports {sclk[5]}] +set_property PACKAGE_PIN C9 [get_ports {sclk[11]}] set_property src_info {type:XDC file:1 line:403 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN B9 [get_ports {latch[4]}] +set_property PACKAGE_PIN B9 [get_ports {latch[5]}] set_property src_info {type:XDC file:1 line:407 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN A10 [get_ports {din[5]}] +set_property PACKAGE_PIN A10 [get_ports {din[11]}] set_property src_info {type:XDC file:1 line:411 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN B10 [get_ports {clear[4]}] +set_property PACKAGE_PIN B10 [get_ports {sdo_bit[4]}] set_property src_info {type:XDC file:1 line:415 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN C11 [get_ports {sdo_bit[5]}] +set_property PACKAGE_PIN C11 [get_ports {sdo_bit[11]}] set_property src_info {type:XDC file:1 line:419 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN B12 [get_ports {clear[1]}] +set_property PACKAGE_PIN B12 [get_ports {sclk[4]}] set_property src_info {type:XDC file:1 line:423 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN A12 [get_ports {clear[0]}] +set_property PACKAGE_PIN A12 [get_ports {clear[10]}] set_property src_info {type:XDC file:1 line:427 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN C12 [get_ports {latch[1]}] +set_property PACKAGE_PIN C12 [get_ports {clear[4]}] set_property src_info {type:XDC file:1 line:431 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN F13 [get_ports {latch[0]}] +set_property PACKAGE_PIN F13 [get_ports {latch[10]}] set_property src_info {type:XDC file:1 line:443 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN A13 [get_ports {sclk[1]}] +set_property PACKAGE_PIN A13 [get_ports {sdo_bit[3]}] set_property src_info {type:XDC file:1 line:447 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN A14 [get_ports {sclk[0]}] +set_property PACKAGE_PIN A14 [get_ports {sclk[10]}] set_property src_info {type:XDC file:1 line:451 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN E13 [get_ports {din[1]}] +set_property PACKAGE_PIN E13 [get_ports {din[3]}] set_property src_info {type:XDC file:1 line:455 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN B14 [get_ports {din[0]}] +set_property PACKAGE_PIN B14 [get_ports {din[10]}] set_property src_info {type:XDC file:1 line:459 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN C14 [get_ports {sdo_bit[1]}] +set_property PACKAGE_PIN C14 [get_ports {sclk[3]}] set_property src_info {type:XDC file:1 line:463 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN A15 [get_ports {sdo_bit[0]}] +set_property PACKAGE_PIN A15 [get_ports {sdo_bit[10]}] set_property src_info {type:XDC file:1 line:467 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN B15 [get_ports {clear[10]}] +set_property PACKAGE_PIN B15 [get_ports {latch[3]}] set_property src_info {type:XDC file:1 line:471 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN B16 [get_ports {clear[3]}] +set_property PACKAGE_PIN B16 [get_ports {clear[9]}] set_property src_info {type:XDC file:1 line:475 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN C16 [get_ports {latch[10]}] +set_property PACKAGE_PIN C16 [get_ports {clear[3]}] set_property src_info {type:XDC file:1 line:479 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN D15 [get_ports {latch[3]}] +set_property PACKAGE_PIN D15 [get_ports {latch[9]}] set_property src_info {type:XDC file:1 line:491 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN D16 [get_ports {clear[11]}] +set_property PACKAGE_PIN D16 [get_ports {sdo_bit[7]}] set_property src_info {type:XDC file:1 line:495 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN D14 [get_ports {sclk[3]}] +set_property PACKAGE_PIN D14 [get_ports {sclk[9]}] set_property src_info {type:XDC file:1 line:499 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN E16 [get_ports {latch[11]}] +set_property PACKAGE_PIN E16 [get_ports {din[7]}] set_property src_info {type:XDC file:1 line:503 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN E15 [get_ports {din[3]}] +set_property PACKAGE_PIN E15 [get_ports {din[9]}] set_property src_info {type:XDC file:1 line:507 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN G15 [get_ports {sclk[11]}] +set_property PACKAGE_PIN G15 [get_ports {sclk[7]}] set_property src_info {type:XDC file:1 line:511 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN F14 [get_ports {sdo_bit[3]}] +set_property PACKAGE_PIN F14 [get_ports {sdo_bit[9]}] set_property src_info {type:XDC file:1 line:515 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN H14 [get_ports {din[11]}] +set_property PACKAGE_PIN H14 [get_ports {latch[7]}] set_property src_info {type:XDC file:1 line:519 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN G16 [get_ports {clear[2]}] +set_property PACKAGE_PIN G16 [get_ports {clear[8]}] set_property src_info {type:XDC file:1 line:531 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN H13 [get_ports {sdo_bit[11]}] +set_property PACKAGE_PIN H13 [get_ports {clear[7]}] set_property src_info {type:XDC file:1 line:535 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN H16 [get_ports {latch[2]}] +set_property PACKAGE_PIN H16 [get_ports {latch[8]}] set_property src_info {type:XDC file:1 line:539 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN F15 [get_ports {sdo_bit[2]}] +set_property PACKAGE_PIN F15 [get_ports {din[8]}] set_property src_info {type:XDC file:1 line:543 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN G14 [get_ports {sclk[2]}] +set_property PACKAGE_PIN G14 [get_ports {sclk[8]}] set_property src_info {type:XDC file:1 line:547 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN E12 [get_ports {din[2]}] +set_property PACKAGE_PIN E12 [get_ports {sdo_bit[8]}] set_property src_info {type:XDC file:1 line:563 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN H5 [get_ports {led[0]}] set_property src_info {type:XDC file:1 line:564 export:INPUT save:INPUT read:READ} [current_design] diff --git a/project_LITE/project_LITE/17.runs/synth_1/.vivado.begin.rst b/project_LITE/project_LITE/17.runs/synth_1/.vivado.begin.rst index 255e2fe..969ee88 100755 --- a/project_LITE/project_LITE/17.runs/synth_1/.vivado.begin.rst +++ b/project_LITE/project_LITE/17.runs/synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control.dcp b/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control.dcp index c9bd1f0..2508ae3 100755 Binary files a/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control.dcp and b/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control.dcp differ diff --git a/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control.vds b/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control.vds index e75aa54..50a7498 100755 --- a/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control.vds +++ b/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control.vds @@ -2,8 +2,8 @@ # Vivado v2017.2 (64-bit) # SW Build 1909853 on Thu Jun 15 18:39:09 MDT 2017 # IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 -# Start of session at: Tue Feb 26 23:47:12 2019 -# Process ID: 45796 +# Start of session at: Tue Mar 19 18:57:56 2019 +# Process ID: 38872 # Current directory: C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/synth_1 # Command line: vivado.exe -log OSC1_LITE_Control.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source OSC1_LITE_Control.tcl # Log file: C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control.vds @@ -15,9 +15,9 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a15t-ftg256' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a15t-ftg256' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 43724 +INFO: Helper process launched with PID 42052 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 363.270 ; gain = 82.898 +Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 363.848 ; gain = 83.035 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'OSC1_LITE_Control' [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/sources_1/imports/imports/OSC1_LITE_one_channel_control.v:4] INFO: [Synth 8-638] synthesizing module 'spi_controller' [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/sources_1/imports/imports/DAC_spi_master.v:7] @@ -774,7 +774,7 @@ WARNING: [Synth 8-3331] design fifo_generator_v13_1_1 has unconnected port s_axi WARNING: [Synth 8-3331] design fifo_generator_v13_1_1 has unconnected port s_axi_awaddr[15] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:52 ; elapsed = 00:00:53 . Memory (MB): peak = 572.246 ; gain = 291.875 +Finished RTL Elaboration : Time (s): cpu = 00:00:52 ; elapsed = 00:00:53 . Memory (MB): peak = 572.820 ; gain = 292.008 --------------------------------------------------------------------------------- Report Check Netlist: @@ -784,7 +784,7 @@ Report Check Netlist: |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:52 ; elapsed = 00:00:53 . Memory (MB): peak = 572.246 ; gain = 291.875 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:53 ; elapsed = 00:00:53 . Memory (MB): peak = 572.820 ; gain = 292.008 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 126 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds @@ -821,29 +821,29 @@ INFO: [Project 1-111] Unisim Transformation Summary: RAM128X1S => RAM128X1S (RAMS64E, RAMS64E, MUXF7): 8 instances RAM32M => RAM32M (RAMS32, RAMS32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32): 4 instances -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 719.043 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 719.633 ; gain = 0.000 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 719.043 ; gain = 438.672 +Finished Constraint Validation : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 719.633 ; gain = 438.820 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a15tftg256-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 719.043 ; gain = 438.672 +Finished Loading Part and Timing Information : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 719.633 ; gain = 438.820 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for my_amp_pipe/memory. (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 719.043 ; gain = 438.672 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 719.633 ; gain = 438.820 --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element counter_reg was removed. [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/sources_1/imports/imports/DAC_spi_master.v:42] WARNING: [Synth 8-6014] Unused sequential element write_counter_reg was removed. [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/sources_1/imports/imports/amp_pipe.v:57] WARNING: [Synth 8-6014] Unused sequential element clk_counter_reg was removed. [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/sources_1/imports/imports/OSC1_LITE_one_channel_control.v:87] --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 719.043 ; gain = 438.672 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 719.633 ; gain = 438.820 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -996,7 +996,7 @@ WARNING: [Synth 8-3332] Sequential element (ep_datahold_reg[9]) is unused and wi WARNING: [Synth 8-3332] Sequential element (ep_dataout_reg[10]) is unused and will be removed from module okWireIn. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:07 ; elapsed = 00:01:09 . Memory (MB): peak = 719.043 ; gain = 438.672 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:07 ; elapsed = 00:01:09 . Memory (MB): peak = 719.633 ; gain = 438.820 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -1008,13 +1008,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:16 ; elapsed = 00:01:18 . Memory (MB): peak = 719.043 ; gain = 438.672 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:16 ; elapsed = 00:01:18 . Memory (MB): peak = 719.633 ; gain = 438.820 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:01:16 ; elapsed = 00:01:18 . Memory (MB): peak = 719.043 ; gain = 438.672 +Finished Timing Optimization : Time (s): cpu = 00:01:16 ; elapsed = 00:01:18 . Memory (MB): peak = 719.633 ; gain = 438.820 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -1026,7 +1026,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:01:17 ; elapsed = 00:01:19 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished Technology Mapping : Time (s): cpu = 00:01:17 ; elapsed = 00:01:19 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -1050,7 +1050,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:01:17 ; elapsed = 00:01:19 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished IO Insertion : Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- Report Check Netlist: @@ -1063,7 +1063,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:01:17 ; elapsed = 00:01:20 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished Renaming Generated Instances : Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -1075,25 +1075,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished Renaming Generated Ports : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished Handling Custom Attributes : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished Renaming Generated Nets : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -1112,12 +1112,12 @@ Report Cell Usage: |1 |BUFG | 5| |2 |CARRY4 | 49| |3 |DNA_PORT | 1| -|4 |LUT1 | 110| -|5 |LUT2 | 122| -|6 |LUT3 | 92| -|7 |LUT4 | 215| -|8 |LUT5 | 226| -|9 |LUT6 | 624| +|4 |LUT1 | 111| +|5 |LUT2 | 118| +|6 |LUT3 | 99| +|7 |LUT4 | 217| +|8 |LUT5 | 223| +|9 |LUT6 | 599| |10 |LUT6_2 | 50| |11 |MMCME2_BASE | 1| |12 |RAM128X1S | 8| @@ -1133,14 +1133,14 @@ Report Cell Usage: |22 |IBUF | 8| |23 |IBUFG | 1| |24 |IOBUF | 17| -|25 |OBUF | 60| +|25 |OBUF | 59| +------+------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished Writing Synthesis Report : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1318 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:01:13 . Memory (MB): peak = 725.402 ; gain = 298.234 -Synthesis Optimization Complete : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.402 ; gain = 445.031 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:01:13 . Memory (MB): peak = 725.047 ; gain = 297.422 +Synthesis Optimization Complete : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.047 ; gain = 444.234 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 158 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds @@ -1158,7 +1158,7 @@ INFO: [Project 1-111] Unisim Transformation Summary: 687 Infos, 214 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:01:19 ; elapsed = 00:01:23 . Memory (MB): peak = 725.738 ; gain = 446.996 +synth_design: Time (s): cpu = 00:01:20 ; elapsed = 00:01:24 . Memory (MB): peak = 725.074 ; gain = 445.895 INFO: [Common 17-1381] The checkpoint 'C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control.dcp' has been generated. -report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 725.738 ; gain = 0.000 -INFO: [Common 17-206] Exiting Vivado at Tue Feb 26 23:48:41 2019... +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 725.074 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Tue Mar 19 18:59:26 2019... diff --git a/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control_utilization_synth.pb b/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control_utilization_synth.pb index 421b2c9..680978f 100755 Binary files a/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control_utilization_synth.pb and b/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control_utilization_synth.pb differ diff --git a/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control_utilization_synth.rpt b/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control_utilization_synth.rpt index d588b13..c5162f2 100755 --- a/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control_utilization_synth.rpt +++ b/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -| Date : Tue Feb 26 23:48:41 2019 +| Date : Tue Mar 19 18:59:26 2019 | Host : EECS-TOYODA running 64-bit major release (build 9200) | Command : report_utilization -file OSC1_LITE_Control_utilization_synth.rpt -pb OSC1_LITE_Control_utilization_synth.pb | Design : OSC1_LITE_Control @@ -30,8 +30,8 @@ Table of Contents +----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 1284 | 0 | 10400 | 12.35 | -| LUT as Logic | 1252 | 0 | 10400 | 12.04 | +| Slice LUTs* | 1261 | 0 | 10400 | 12.13 | +| LUT as Logic | 1229 | 0 | 10400 | 11.82 | | LUT as Memory | 32 | 0 | 9600 | 0.33 | | LUT as Distributed RAM | 32 | 0 | | | | LUT as Shift Register | 0 | 0 | | | @@ -94,7 +94,7 @@ Table of Contents +-----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 86 | 0 | 170 | 50.59 | +| Bonded IOB | 85 | 0 | 170 | 50.00 | | Bonded IPADs | 0 | 0 | 2 | 0.00 | | PHY_CONTROL | 0 | 0 | 5 | 0.00 | | PHASER_REF | 0 | 0 | 5 | 0.00 | @@ -151,14 +151,14 @@ Table of Contents | Ref Name | Used | Functional Category | +------------+------+---------------------+ | FDRE | 999 | Flop & Latch | -| LUT6 | 674 | LUT | -| LUT5 | 276 | LUT | -| LUT4 | 215 | LUT | +| LUT6 | 649 | LUT | +| LUT5 | 273 | LUT | +| LUT4 | 217 | LUT | | FDCE | 135 | Flop & Latch | -| LUT2 | 122 | LUT | -| LUT1 | 110 | LUT | -| LUT3 | 92 | LUT | -| OBUF | 60 | IO | +| LUT2 | 118 | LUT | +| LUT1 | 111 | LUT | +| LUT3 | 99 | LUT | +| OBUF | 59 | IO | | CARRY4 | 50 | CarryLogic | | FDPE | 44 | Flop & Latch | | IBUF | 26 | IO | diff --git a/project_LITE/project_LITE/17.runs/synth_1/gen_run.xml b/project_LITE/project_LITE/17.runs/synth_1/gen_run.xml index 10d65fa..5c8dbee 100755 --- a/project_LITE/project_LITE/17.runs/synth_1/gen_run.xml +++ b/project_LITE/project_LITE/17.runs/synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/project_LITE/project_LITE/17.runs/synth_1/runme.log b/project_LITE/project_LITE/17.runs/synth_1/runme.log index 78660b5..4b05de1 100755 --- a/project_LITE/project_LITE/17.runs/synth_1/runme.log +++ b/project_LITE/project_LITE/17.runs/synth_1/runme.log @@ -14,9 +14,9 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a15t-ftg256' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a15t-ftg256' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 43724 +INFO: Helper process launched with PID 42052 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 363.270 ; gain = 82.898 +Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 363.848 ; gain = 83.035 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'OSC1_LITE_Control' [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/sources_1/imports/imports/OSC1_LITE_one_channel_control.v:4] INFO: [Synth 8-638] synthesizing module 'spi_controller' [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/sources_1/imports/imports/DAC_spi_master.v:7] @@ -773,7 +773,7 @@ WARNING: [Synth 8-3331] design fifo_generator_v13_1_1 has unconnected port s_axi WARNING: [Synth 8-3331] design fifo_generator_v13_1_1 has unconnected port s_axi_awaddr[15] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:52 ; elapsed = 00:00:53 . Memory (MB): peak = 572.246 ; gain = 291.875 +Finished RTL Elaboration : Time (s): cpu = 00:00:52 ; elapsed = 00:00:53 . Memory (MB): peak = 572.820 ; gain = 292.008 --------------------------------------------------------------------------------- Report Check Netlist: @@ -783,7 +783,7 @@ Report Check Netlist: |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:52 ; elapsed = 00:00:53 . Memory (MB): peak = 572.246 ; gain = 291.875 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:53 ; elapsed = 00:00:53 . Memory (MB): peak = 572.820 ; gain = 292.008 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 126 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds @@ -820,29 +820,29 @@ INFO: [Project 1-111] Unisim Transformation Summary: RAM128X1S => RAM128X1S (RAMS64E, RAMS64E, MUXF7): 8 instances RAM32M => RAM32M (RAMS32, RAMS32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32): 4 instances -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 719.043 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 719.633 ; gain = 0.000 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 719.043 ; gain = 438.672 +Finished Constraint Validation : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 719.633 ; gain = 438.820 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a15tftg256-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 719.043 ; gain = 438.672 +Finished Loading Part and Timing Information : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 719.633 ; gain = 438.820 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for my_amp_pipe/memory. (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 719.043 ; gain = 438.672 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 719.633 ; gain = 438.820 --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element counter_reg was removed. [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/sources_1/imports/imports/DAC_spi_master.v:42] WARNING: [Synth 8-6014] Unused sequential element write_counter_reg was removed. [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/sources_1/imports/imports/amp_pipe.v:57] WARNING: [Synth 8-6014] Unused sequential element clk_counter_reg was removed. [C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.srcs/sources_1/imports/imports/OSC1_LITE_one_channel_control.v:87] --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 719.043 ; gain = 438.672 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 719.633 ; gain = 438.820 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -995,7 +995,7 @@ WARNING: [Synth 8-3332] Sequential element (ep_datahold_reg[9]) is unused and wi WARNING: [Synth 8-3332] Sequential element (ep_dataout_reg[10]) is unused and will be removed from module okWireIn. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:07 ; elapsed = 00:01:09 . Memory (MB): peak = 719.043 ; gain = 438.672 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:07 ; elapsed = 00:01:09 . Memory (MB): peak = 719.633 ; gain = 438.820 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -1007,13 +1007,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:16 ; elapsed = 00:01:18 . Memory (MB): peak = 719.043 ; gain = 438.672 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:16 ; elapsed = 00:01:18 . Memory (MB): peak = 719.633 ; gain = 438.820 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:01:16 ; elapsed = 00:01:18 . Memory (MB): peak = 719.043 ; gain = 438.672 +Finished Timing Optimization : Time (s): cpu = 00:01:16 ; elapsed = 00:01:18 . Memory (MB): peak = 719.633 ; gain = 438.820 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -1025,7 +1025,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:01:17 ; elapsed = 00:01:19 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished Technology Mapping : Time (s): cpu = 00:01:17 ; elapsed = 00:01:19 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -1049,7 +1049,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:01:17 ; elapsed = 00:01:19 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished IO Insertion : Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- Report Check Netlist: @@ -1062,7 +1062,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:01:17 ; elapsed = 00:01:20 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished Renaming Generated Instances : Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -1074,25 +1074,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished Renaming Generated Ports : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished Handling Custom Attributes : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished Renaming Generated Nets : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -1111,12 +1111,12 @@ Report Cell Usage: |1 |BUFG | 5| |2 |CARRY4 | 49| |3 |DNA_PORT | 1| -|4 |LUT1 | 110| -|5 |LUT2 | 122| -|6 |LUT3 | 92| -|7 |LUT4 | 215| -|8 |LUT5 | 226| -|9 |LUT6 | 624| +|4 |LUT1 | 111| +|5 |LUT2 | 118| +|6 |LUT3 | 99| +|7 |LUT4 | 217| +|8 |LUT5 | 223| +|9 |LUT6 | 599| |10 |LUT6_2 | 50| |11 |MMCME2_BASE | 1| |12 |RAM128X1S | 8| @@ -1132,14 +1132,14 @@ Report Cell Usage: |22 |IBUF | 8| |23 |IBUFG | 1| |24 |IOBUF | 17| -|25 |OBUF | 60| +|25 |OBUF | 59| +------+------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.402 ; gain = 445.031 +Finished Writing Synthesis Report : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.047 ; gain = 444.234 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1318 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:01:13 . Memory (MB): peak = 725.402 ; gain = 298.234 -Synthesis Optimization Complete : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.402 ; gain = 445.031 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:01:13 . Memory (MB): peak = 725.047 ; gain = 297.422 +Synthesis Optimization Complete : Time (s): cpu = 00:01:18 ; elapsed = 00:01:20 . Memory (MB): peak = 725.047 ; gain = 444.234 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 158 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds @@ -1157,7 +1157,7 @@ INFO: [Project 1-111] Unisim Transformation Summary: 687 Infos, 214 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:01:19 ; elapsed = 00:01:23 . Memory (MB): peak = 725.738 ; gain = 446.996 +synth_design: Time (s): cpu = 00:01:20 ; elapsed = 00:01:24 . Memory (MB): peak = 725.074 ; gain = 445.895 INFO: [Common 17-1381] The checkpoint 'C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control.dcp' has been generated. -report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 725.738 ; gain = 0.000 -INFO: [Common 17-206] Exiting Vivado at Tue Feb 26 23:48:41 2019... +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 725.074 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Tue Mar 19 18:59:26 2019... diff --git a/project_LITE/project_LITE/17.runs/synth_1/vivado.jou b/project_LITE/project_LITE/17.runs/synth_1/vivado.jou index d3057ae..348a222 100755 --- a/project_LITE/project_LITE/17.runs/synth_1/vivado.jou +++ b/project_LITE/project_LITE/17.runs/synth_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2017.2 (64-bit) # SW Build 1909853 on Thu Jun 15 18:39:09 MDT 2017 # IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 -# Start of session at: Tue Feb 26 23:47:12 2019 -# Process ID: 45796 +# Start of session at: Tue Mar 19 18:57:56 2019 +# Process ID: 38872 # Current directory: C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/synth_1 # Command line: vivado.exe -log OSC1_LITE_Control.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source OSC1_LITE_Control.tcl # Log file: C:/Users/yoongroup/Documents/Adam/vivado/project_LITE/project_LITE/17.runs/synth_1/OSC1_LITE_Control.vds diff --git a/project_LITE/project_LITE/17.runs/synth_1/vivado.pb b/project_LITE/project_LITE/17.runs/synth_1/vivado.pb index 077b676..80c32df 100755 Binary files a/project_LITE/project_LITE/17.runs/synth_1/vivado.pb and b/project_LITE/project_LITE/17.runs/synth_1/vivado.pb differ diff --git a/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc b/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc index 791e9d8..0aa9e8a 100755 --- a/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc +++ b/project_LITE/project_LITE/17.srcs/constrs_1/imports/Desktop/xem7001.xdc @@ -88,464 +88,464 @@ set_property PACKAGE_PIN N14 [get_ports {clk}] #set_property IOSTANDARD [get_ports {}] # JP1-3 -set_property PACKAGE_PIN H1 [get_ports {sdo_bit[7]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[7]}] +#set_property PACKAGE_PIN H1 [get_ports {sdo_bit[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[7]}] -# JP1-4 -set_property PACKAGE_PIN H2 [get_ports {sclk[8]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sclk[8]}] +## JP1-4 +#set_property PACKAGE_PIN H2 [get_ports {sclk[8]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sclk[8]}] -# JP1-5 -set_property PACKAGE_PIN G1 [get_ports {din[7]}] -set_property IOSTANDARD LVCMOS33 [get_ports {din[7]}] +## JP1-5 +#set_property PACKAGE_PIN G1 [get_ports {din[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {din[7]}] -# JP1-6 -set_property PACKAGE_PIN G2 [get_ports {din[8]}] -set_property IOSTANDARD LVCMOS33 [get_ports {din[8]}] +## JP1-6 +#set_property PACKAGE_PIN G2 [get_ports {din[8]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {din[8]}] -# JP1-7 -set_property PACKAGE_PIN F2 [get_ports {sclk[7]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sclk[7]}] +## JP1-7 +#set_property PACKAGE_PIN F2 [get_ports {sclk[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sclk[7]}] -# JP1-8 -set_property PACKAGE_PIN E1 [get_ports {sdo_bit[8]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[8]}] +## JP1-8 +#set_property PACKAGE_PIN E1 [get_ports {sdo_bit[8]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[8]}] -# JP1-9 -set_property PACKAGE_PIN E2 [get_ports {latch[7]}] -set_property IOSTANDARD LVCMOS33 [get_ports {latch[7]}] +## JP1-9 +#set_property PACKAGE_PIN E2 [get_ports {latch[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {latch[7]}] -# JP1-10 -set_property PACKAGE_PIN D1 [get_ports {clear[6]}] -set_property IOSTANDARD LVCMOS33 [get_ports {clear[6]}] +## JP1-10 +#set_property PACKAGE_PIN D1 [get_ports {clear[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {clear[6]}] -# JP1-11 -set_property PACKAGE_PIN C1 [get_ports {clear[7]}] -set_property IOSTANDARD LVCMOS33 [get_ports {clear[7]}] +## JP1-11 +#set_property PACKAGE_PIN C1 [get_ports {clear[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {clear[7]}] -## JP1-12 -set_property PACKAGE_PIN C2 [get_ports {latch[6]}] -set_property IOSTANDARD LVCMOS33 [get_ports {latch[6]}] +### JP1-12 +#set_property PACKAGE_PIN C2 [get_ports {latch[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {latch[6]}] -## JP1-13 -set_property PACKAGE_PIN B1 [get_ports {sdo_bit[10]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[10]}] +### JP1-13 +#set_property PACKAGE_PIN B1 [get_ports {sdo_bit[10]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[10]}] -## JP1-14 -set_property PACKAGE_PIN B2 [get_ports {sclk[6]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sclk[6]}] +### JP1-14 +#set_property PACKAGE_PIN B2 [get_ports {sclk[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sclk[6]}] -## JP1-15 -set_property PACKAGE_PIN A2 [get_ports {din[10]}] -set_property IOSTANDARD LVCMOS33 [get_ports {din[10]}] +### JP1-15 +set_property PACKAGE_PIN A2 [get_ports {latch[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {latch[4]}] -## JP1-16 -set_property PACKAGE_PIN A3 [get_ports {din[6]}] -set_property IOSTANDARD LVCMOS33 [get_ports {din[6]}] +### JP1-16 +#set_property PACKAGE_PIN A3 [get_ports {din[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {din[6]}] -## JP1-17 -set_property PACKAGE_PIN D4 [get_ports {sclk[10]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sclk[10]}] +### JP1-17 +set_property PACKAGE_PIN D4 [get_ports {din[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[4]}] -## JP1-18 -set_property PACKAGE_PIN C4 [get_ports {sdo_bit[6]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[6]}] +### JP1-18 +set_property PACKAGE_PIN C4 [get_ports {sclk[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sclk[5]}] -## JP1-19 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP1-19 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP1-20 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP1-20 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP2-1 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP2-1 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP2-2 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP2-2 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP2-3 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD LVCMOS33 [get_ports {}] +### JP2-3 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD LVCMOS33 [get_ports {}] -## JP2-4 -##set_property PACKAGE_PIN P10 [get_ports {}] -##set_property IOSTANDARD LVCMOS33 [get_ports {}] +### JP2-4 +###set_property PACKAGE_PIN P10 [get_ports {}] +###set_property IOSTANDARD LVCMOS33 [get_ports {}] -## JP2-5 -#set_property PACKAGE_PIN J1 [get_ports {extrigin[24]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[24]}] +### JP2-5 +##set_property PACKAGE_PIN J1 [get_ports {extrigin[24]}] +##set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[24]}] -## JP2-6 -set_property PACKAGE_PIN J3 [get_ports {latch[8]}] -set_property IOSTANDARD LVCMOS33 [get_ports {latch[8]}] +### JP2-6 +#set_property PACKAGE_PIN J3 [get_ports {latch[8]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {latch[8]}] -## JP2-7 -#set_property PACKAGE_PIN K2 [get_ports {extrigin[26]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[26]}] +### JP2-7 +##set_property PACKAGE_PIN K2 [get_ports {extrigin[26]}] +##set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[26]}] -## JP2-8 -set_property PACKAGE_PIN K1 [get_ports {clear[8]}] -set_property IOSTANDARD LVCMOS33 [get_ports {clear[8]}] +### JP2-8 +#set_property PACKAGE_PIN K1 [get_ports {clear[8]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {clear[8]}] -## JP2-9 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP2-9 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP2-10 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP2-10 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP2-11 -#set_property PACKAGE_PIN L2 [get_ports {extrigin[28]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[28]}] +### JP2-11 +##set_property PACKAGE_PIN L2 [get_ports {extrigin[28]}] +##set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[28]}] -## JP2-12 -#set_property PACKAGE_PIN K3 [get_ports {extrigin[29]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[29]}] +### JP2-12 +##set_property PACKAGE_PIN K3 [get_ports {extrigin[29]}] +##set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[29]}] -## JP2-13 -#set_property PACKAGE_PIN L3 [get_ports {extrigin[30]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[30]}] +### JP2-13 +##set_property PACKAGE_PIN L3 [get_ports {extrigin[30]}] +##set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[30]}] -## JP2-14 -#set_property PACKAGE_PIN M1 [get_ports {extrigin[31]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[31]}] +### JP2-14 +##set_property PACKAGE_PIN M1 [get_ports {extrigin[31]}] +##set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[31]}] -## JP2-15 -#set_property PACKAGE_PIN M2 [get_ports {extrigin[32]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[32]}] +### JP2-15 +##set_property PACKAGE_PIN M2 [get_ports {extrigin[32]}] +##set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[32]}] -## JP2-16 -#set_property PACKAGE_PIN L4 [get_ports {extrigin[33]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[33]}] +### JP2-16 +##set_property PACKAGE_PIN L4 [get_ports {extrigin[33]}] +##set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[33]}] -## JP2-17 -#set_property PACKAGE_PIN M4 [get_ports {extrigin[34]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[34]}] +### JP2-17 +##set_property PACKAGE_PIN M4 [get_ports {extrigin[34]}] +##set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[34]}] -## JP2-18 -#set_property PACKAGE_PIN N1 [get_ports {extrigin[35]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[35]}] +### JP2-18 +##set_property PACKAGE_PIN N1 [get_ports {extrigin[35]}] +##set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[35]}] -## JP2-19 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP2-19 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP2-20 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP2-20 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP2-21 -#set_property PACKAGE_PIN N2 [get_ports {extrigin[12]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[12]}] +### JP2-21 +##set_property PACKAGE_PIN N2 [get_ports {extrigin[12]}] +##set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[12]}] -## JP2-22 -#set_property PACKAGE_PIN N3 [get_ports {extrigin[13]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[13]}] +### JP2-22 +##set_property PACKAGE_PIN N3 [get_ports {extrigin[13]}] +##set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[13]}] -## JP2-23 -#set_property PACKAGE_PIN P1 [get_ports {extrigin[14]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[14]}] +### JP2-23 +##set_property PACKAGE_PIN P1 [get_ports {extrigin[14]}] +##set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[14]}] -## JP2-24 -#set_property PACKAGE_PIN R1 [get_ports {extrigin[15]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[15]}] +### JP2-24 +##set_property PACKAGE_PIN R1 [get_ports {extrigin[15]}] +##set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[15]}] -## JP2-25 -#set_property PACKAGE_PIN R2 [get_ports {extrigin[16]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[16]}] +### JP2-25 +set_property PACKAGE_PIN R2 [get_ports {sdo_bit[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[2]}] -## JP2-26 -#set_property PACKAGE_PIN P3 [get_ports {extrigin[17]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[17]}] +### JP2-26 +set_property PACKAGE_PIN P3 [get_ports {din[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[2]}] -## JP2-27 -#set_property PACKAGE_PIN T2 [get_ports {clear[10]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {clear[10]}] +### JP2-27 +set_property PACKAGE_PIN T2 [get_ports {sclk[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sclk[2]}] -## JP2-28 -#set_property PACKAGE_PIN R3 [get_ports {extrigin[19]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[19]}] +### JP2-28 +set_property PACKAGE_PIN R3 [get_ports {latch[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {latch[2]}] -## JP2-29 -set_property PACKAGE_PIN T3 [get_ports {latch[10]}] -set_property IOSTANDARD LVCMOS33 [get_ports {latch[10]}] +### JP2-29 +set_property PACKAGE_PIN T3 [get_ports {clear[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {clear[2]}] -## JP2-30 -#set_property PACKAGE_PIN N4 [get_ports {extrigin[21]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[21]}] +### JP2-30 +set_property PACKAGE_PIN N4 [get_ports {sdo_bit[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[1]}] -## JP2-31 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP2-31 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP2-32 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP2-32 +#set_property PACKAGE_PIN [get_ports {}] +#set_property IOSTANDARD [get_ports {}] -## JP2-33 -set_property PACKAGE_PIN P4 [get_ports {khan}] -set_property IOSTANDARD LVCMOS33 [get_ports {khan}] +### JP2-33 +set_property PACKAGE_PIN P4 [get_ports {din[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[1]}] -## JP2-34 -set_property PACKAGE_PIN T4 [get_ports {khan}] -set_property IOSTANDARD LVCMOS33 [get_ports {khan}] +### JP2-34 +set_property PACKAGE_PIN T4 [get_ports {sclk[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sclk[1]}] -## JP2-35 -set_property PACKAGE_PIN P5 [get_ports {khan}] -set_property IOSTANDARD LVCMOS33 [get_ports {khan}] +### JP2-35 +set_property PACKAGE_PIN P5 [get_ports {latch[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {latch[1]}] -## JP2-36 -set_property PACKAGE_PIN N6 [get_ports {clear[9]}] -set_property IOSTANDARD LVCMOS33 [get_ports {clear[9]}] +### JP2-36 +set_property PACKAGE_PIN N6 [get_ports {clear[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {clear[1]}] -## JP2-37 -set_property PACKAGE_PIN R5 [get_ports {khan}] -set_property IOSTANDARD LVCMOS33 [get_ports {khan}] +### JP2-37 +set_property PACKAGE_PIN R5 [get_ports {sdo_bit[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[0]}] -## JP2-38 -set_property PACKAGE_PIN P8 [get_ports {latch[9]}] -set_property IOSTANDARD LVCMOS33 [get_ports {latch[9]}] +### JP2-38 +set_property PACKAGE_PIN P8 [get_ports {din[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[0]}] -## JP2-39 -set_property PACKAGE_PIN T5 [get_ports {khan}] -set_property IOSTANDARD LVCMOS33 [get_ports {khan}] +### JP2-39 +set_property PACKAGE_PIN T5 [get_ports {sclk[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sclk[0]}] -## JP2-40 -set_property PACKAGE_PIN R6 [get_ports {sclk[9]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sclk[9]}] +### JP2-40 +set_property PACKAGE_PIN R6 [get_ports {latch[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {latch[0]}] -## JP2-41 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP2-41 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP2-42 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP2-42 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP2-43 -set_property PACKAGE_PIN T9 [get_ports {khan}] -set_property IOSTANDARD LVCMOS33 [get_ports {khan}] +### JP2-43 +set_property PACKAGE_PIN T9 [get_ports {clear[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {clear[0]}] -## JP2-44 -set_property PACKAGE_PIN R7 [get_ports {din[9]}] -set_property IOSTANDARD LVCMOS33 [get_ports {din[9]}] +### JP2-44 +set_property PACKAGE_PIN R7 [get_ports {clear[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {clear[6]}] -## JP2-45 -#set_property PACKAGE_PIN T7 [get_ports {extrigin[8]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[8]}] +### JP2-45 +set_property PACKAGE_PIN T7 [get_ports {latch[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {latch[6]}] -## JP2-46 -set_property PACKAGE_PIN R8 [get_ports {sdo_bit[9]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[9]}] +### JP2-46 +set_property PACKAGE_PIN R8 [get_ports {sclk[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sclk[6]}] -## JP2-47 -#set_property PACKAGE_PIN T8 [get_ports {extrigin[10]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[10]}] +### JP2-47 +set_property PACKAGE_PIN T8 [get_ports {sdo_bit[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[6]}] -## JP2-48 -#set_property PACKAGE_PIN T10 [get_ports {extrigin[11]}] -#set_property IOSTANDARD LVCMOS33 [get_ports {extrigin[11]}] +### JP2-48 +set_property PACKAGE_PIN T10 [get_ports {din[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[6]}] -## JP2-49 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP2-49 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP2-50 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP2-50 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP3-1 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP3-1 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP3-2 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP3-2 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP3-3 -set_property PACKAGE_PIN A8 [get_ports {sdo_bit[4]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[4]}] +### JP3-3 +set_property PACKAGE_PIN A8 [get_ports {sdo_bit[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[5]}] -## JP3-4 -set_property PACKAGE_PIN D9 [get_ports {clear[5]}] -set_property IOSTANDARD LVCMOS33 [get_ports {clear[5]}] +### JP3-4 +set_property PACKAGE_PIN D9 [get_ports {clear[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {clear[11]}] -## JP3-5 -set_property PACKAGE_PIN C8 [get_ports {din[4]}] -set_property IOSTANDARD LVCMOS33 [get_ports {din[4]}] +### JP3-5 +set_property PACKAGE_PIN C8 [get_ports {din[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[5]}] -## JP3-6 -set_property PACKAGE_PIN D10 [get_ports {latch[5]}] -set_property IOSTANDARD LVCMOS33 [get_ports {latch[5]}] +### JP3-6 +set_property PACKAGE_PIN D10 [get_ports {latch[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {latch[11]}] -## JP3-7 -set_property PACKAGE_PIN A9 [get_ports {sclk[4]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sclk[4]}] +### JP3-7 +set_property PACKAGE_PIN A9 [get_ports {clear[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {clear[5]}] -## JP3-8 -set_property PACKAGE_PIN C9 [get_ports {sclk[5]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sclk[5]}] +### JP3-8 +set_property PACKAGE_PIN C9 [get_ports {sclk[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sclk[11]}] -## JP3-9 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP3-9 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP3-10 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP3-10 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP3-11 -set_property PACKAGE_PIN B9 [get_ports {latch[4]}] -set_property IOSTANDARD LVCMOS33 [get_ports {latch[4]}] +### JP3-11 +set_property PACKAGE_PIN B9 [get_ports {latch[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {latch[5]}] -## JP3-12 -set_property PACKAGE_PIN A10 [get_ports {din[5]}] -set_property IOSTANDARD LVCMOS33 [get_ports {din[5]}] +### JP3-12 +set_property PACKAGE_PIN A10 [get_ports {din[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[11]}] -## JP3-13 -set_property PACKAGE_PIN B10 [get_ports {clear[4]}] -set_property IOSTANDARD LVCMOS33 [get_ports {clear[4]}] +### JP3-13 +set_property PACKAGE_PIN B10 [get_ports {sdo_bit[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[4]}] -## JP3-14 -set_property PACKAGE_PIN C11 [get_ports {sdo_bit[5]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[5]}] +### JP3-14 +set_property PACKAGE_PIN C11 [get_ports {sdo_bit[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[11]}] -## JP3-15 -set_property PACKAGE_PIN B12 [get_ports {clear[1]}] -set_property IOSTANDARD LVCMOS33 [get_ports {clear[1]}] +### JP3-15 +set_property PACKAGE_PIN B12 [get_ports {sclk[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sclk[4]}] -## JP3-16 -set_property PACKAGE_PIN A12 [get_ports {clear[0]}] -set_property IOSTANDARD LVCMOS33 [get_ports {clear[0]}] +### JP3-16 +set_property PACKAGE_PIN A12 [get_ports {clear[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {clear[10]}] -## JP3-17 -set_property PACKAGE_PIN C12 [get_ports {latch[1]}] -set_property IOSTANDARD LVCMOS33 [get_ports {latch[1]}] +### JP3-17 +set_property PACKAGE_PIN C12 [get_ports {clear[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {clear[4]}] -## JP3-18 -set_property PACKAGE_PIN F13 [get_ports {latch[0]}] -set_property IOSTANDARD LVCMOS33 [get_ports {latch[0]}] +### JP3-18 +set_property PACKAGE_PIN F13 [get_ports {latch[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {latch[10]}] -## JP3-19 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP3-19 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP3-20 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP3-20 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP3-21 -set_property PACKAGE_PIN A13 [get_ports {sclk[1]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sclk[1]}] +### JP3-21 +set_property PACKAGE_PIN A13 [get_ports {sdo_bit[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[3]}] -## JP3-22 -set_property PACKAGE_PIN A14 [get_ports {sclk[0]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sclk[0]}] +### JP3-22 +set_property PACKAGE_PIN A14 [get_ports {sclk[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sclk[10]}] -## JP3-23 -set_property PACKAGE_PIN E13 [get_ports {din[1]}] -set_property IOSTANDARD LVCMOS33 [get_ports {din[1]}] +### JP3-23 +set_property PACKAGE_PIN E13 [get_ports {din[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[3]}] -## JP3-24 -set_property PACKAGE_PIN B14 [get_ports {din[0]}] -set_property IOSTANDARD LVCMOS33 [get_ports {din[0]}] +### JP3-24 +set_property PACKAGE_PIN B14 [get_ports {din[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[10]}] -## JP3-25 -set_property PACKAGE_PIN C14 [get_ports {sdo_bit[1]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[1]}] +### JP3-25 +set_property PACKAGE_PIN C14 [get_ports {sclk[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sclk[3]}] -## JP3-26 -set_property PACKAGE_PIN A15 [get_ports {sdo_bit[0]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[0]}] +### JP3-26 +set_property PACKAGE_PIN A15 [get_ports {sdo_bit[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[10]}] -## JP3-27 -set_property PACKAGE_PIN B15 [get_ports {clear[10]}] -set_property IOSTANDARD LVCMOS33 [get_ports {clear[10]}] +### JP3-27 +set_property PACKAGE_PIN B15 [get_ports {latch[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {latch[3]}] -## JP3-28 -set_property PACKAGE_PIN B16 [get_ports {clear[3]}] -set_property IOSTANDARD LVCMOS33 [get_ports {clear[3]}] +### JP3-28 +set_property PACKAGE_PIN B16 [get_ports {clear[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {clear[9]}] -## JP3-29 -set_property PACKAGE_PIN C16 [get_ports {latch[10]}] -set_property IOSTANDARD LVCMOS33 [get_ports {latch[10]}] +### JP3-29 +set_property PACKAGE_PIN C16 [get_ports {clear[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {clear[3]}] -## JP3-30 -set_property PACKAGE_PIN D15 [get_ports {latch[3]}] -set_property IOSTANDARD LVCMOS33 [get_ports {latch[3]}] +### JP3-30 +set_property PACKAGE_PIN D15 [get_ports {latch[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {latch[9]}] -## JP3-31 -#set_property PACKAGE_PIN [get_ports {latch[11]}] -#set_property IOSTANDARD [get_ports {latch[11]}] +### JP3-31 +##set_property PACKAGE_PIN [get_ports {latch[11]}] +##set_property IOSTANDARD [get_ports {latch[11]}] -## JP3-32 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP3-32 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP3-33 -set_property PACKAGE_PIN D16 [get_ports {clear[11]}] -set_property IOSTANDARD LVCMOS33 [get_ports {clear[11]}] +### JP3-33 +set_property PACKAGE_PIN D16 [get_ports {sdo_bit[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[7]}] -## JP3-34 -set_property PACKAGE_PIN D14 [get_ports {sclk[3]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sclk[3]}] +### JP3-34 +set_property PACKAGE_PIN D14 [get_ports {sclk[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sclk[9]}] -## JP3-35 -set_property PACKAGE_PIN E16 [get_ports {latch[11]}] -set_property IOSTANDARD LVCMOS33 [get_ports {latch[11]}] +### JP3-35 +set_property PACKAGE_PIN E16 [get_ports {din[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[7]}] -## JP3-36 -set_property PACKAGE_PIN E15 [get_ports {din[3]}] -set_property IOSTANDARD LVCMOS33 [get_ports {din[3]}] +### JP3-36 +set_property PACKAGE_PIN E15 [get_ports {din[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[9]}] -## JP3-37 -set_property PACKAGE_PIN G15 [get_ports {sclk[11]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sclk[11]}] +### JP3-37 +set_property PACKAGE_PIN G15 [get_ports {sclk[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sclk[7]}] -## JP3-38 -set_property PACKAGE_PIN F14 [get_ports {sdo_bit[3]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[3]}] +### JP3-38 +set_property PACKAGE_PIN F14 [get_ports {sdo_bit[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[9]}] -## JP3-39 -set_property PACKAGE_PIN H14 [get_ports {din[11]}] -set_property IOSTANDARD LVCMOS33 [get_ports {din[11]}] +### JP3-39 +set_property PACKAGE_PIN H14 [get_ports {latch[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {latch[7]}] -## JP3-40 -set_property PACKAGE_PIN G16 [get_ports {clear[2]}] -set_property IOSTANDARD LVCMOS33 [get_ports {clear[2]}] +### JP3-40 +set_property PACKAGE_PIN G16 [get_ports {clear[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {clear[8]}] -## JP3-41 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP3-41 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP3-42 -##set_property PACKAGE_PIN [get_ports {}] -##set_property IOSTANDARD [get_ports {}] +### JP3-42 +###set_property PACKAGE_PIN [get_ports {}] +###set_property IOSTANDARD [get_ports {}] -## JP3-43 -set_property PACKAGE_PIN H13 [get_ports {sdo_bit[11]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[11]}] +### JP3-43 +set_property PACKAGE_PIN H13 [get_ports {clear[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {clear[7]}] -## JP3-44 -set_property PACKAGE_PIN H16 [get_ports {latch[2]}] -set_property IOSTANDARD LVCMOS33 [get_ports {latch[2]}] +### JP3-44 +set_property PACKAGE_PIN H16 [get_ports {latch[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {latch[8]}] -## JP3-45 -set_property PACKAGE_PIN F15 [get_ports {sdo_bit[2]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[2]}] +### JP3-45 +set_property PACKAGE_PIN F15 [get_ports {din[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[8]}] -## JP3-46 -set_property PACKAGE_PIN G14 [get_ports {sclk[2]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sclk[2]}] +### JP3-46 +set_property PACKAGE_PIN G14 [get_ports {sclk[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sclk[8]}] -# JP3-47 -set_property PACKAGE_PIN E12 [get_ports {din[2]}] -set_property IOSTANDARD LVCMOS33 [get_ports {din[2]}] +## JP3-47 +set_property PACKAGE_PIN E12 [get_ports {sdo_bit[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sdo_bit[8]}] # JP3-48 #set_property PACKAGE_PIN [get_ports {}] diff --git a/project_LITE/project_LITE/17.srcs/sources_1/imports/imports/OSC1_LITE_one_channel_control.v b/project_LITE/project_LITE/17.srcs/sources_1/imports/imports/OSC1_LITE_one_channel_control.v index 32db5a0..37d1111 100755 --- a/project_LITE/project_LITE/17.srcs/sources_1/imports/imports/OSC1_LITE_one_channel_control.v +++ b/project_LITE/project_LITE/17.srcs/sources_1/imports/imports/OSC1_LITE_one_channel_control.v @@ -26,16 +26,16 @@ module OSC1_LITE_Control( */ output wire [11:0] clear, - output wire [11:0] latch, - output wire [11:0] sclk, - output wire [11:0] din, - input wire [11:0] sdo_bit, + output wire [11:0] latch, + output wire [11:0] sclk, + output wire [11:0] din, + input wire [11:0] sdo_bit - output wire khan ); +wire khan; // Target interface bus: wire ti_clk; wire [30:0] ok1; diff --git a/script.m b/script.m index 3cdddc8..84fbf3b 100755 --- a/script.m +++ b/script.m @@ -1,6 +1,7 @@ -obj = OSC136H +obj = OSC136H; if obj.ConnectToFirst == 0 obj.SetAllHigh +% obj.SetAllZero else prinf("doomed") end \ No newline at end of file