SPIN1_API: dispatcher runs with interrupts disabled too agressively

[lplana]

1. The only critical section is the access to priority queue head/tail registers, which are also accessed by the scheduler. The rest of the code can run outside the critical section.

2. The critical section only needs to disable 'irq' interrupts, which can start the scheduler. 'fiq' interrupts do not start the scheduler and, therefore, do not affect the priority queue registers.