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#23 readme++ Scala CI #369: Commit 4195c2a pushed by Dolu1990
September 4, 2024 10:50 4m 6s dev
dev
September 4, 2024 10:50 4m 6s
sync Scala CI #368: Commit c99ad0d pushed by Dolu1990
September 4, 2024 06:11 3m 39s dev
dev
September 4, 2024 06:11 3m 39s
Fix FpuPackerPlugin linkedHashMap.keys.map not being linked anymore XD Scala CI #367: Commit ba69a8a pushed by Dolu1990
September 4, 2024 05:35 3m 25s dev
dev
September 4, 2024 05:35 3m 25s
Litex soc withLowLatencyPeriph added Scala CI #366: Commit 63933cd pushed by Dolu1990
September 3, 2024 14:33 3m 21s dev
dev
September 3, 2024 14:33 3m 21s
Verious litex soc optimisations : Scala CI #365: Commit fd102e3 pushed by Dolu1990
September 3, 2024 06:07 3m 57s dev
dev
September 3, 2024 06:07 3m 57s
litex soc bring back meme blackboxing Scala CI #364: Commit f225f3f pushed by Dolu1990
August 30, 2024 16:21 3m 48s dev
dev
August 30, 2024 16:21 3m 48s
litex soc now support cpu-clk Scala CI #363: Commit 3474401 pushed by Dolu1990
August 30, 2024 16:18 3m 26s dev
dev
August 30, 2024 16:18 3m 26s
litex soc add rgb to ycbcr converter Scala CI #362: Commit c10a86a pushed by Dolu1990
August 29, 2024 09:42 6m 0s dev
dev
August 29, 2024 09:42 6m 0s
sync Scala CI #361: Commit 068e579 pushed by Dolu1990
August 29, 2024 06:01 3m 19s dev
dev
August 29, 2024 06:01 3m 19s
Got litex soc to have memory coherent VGA Scala CI #360: Commit 7bff1c9 pushed by Dolu1990
August 28, 2024 17:37 19m 30s dev
dev
August 28, 2024 17:37 19m 30s
Add a few Vexii parameters (div/mmu) Scala CI #359: Commit 30e326d pushed by Dolu1990
August 19, 2024 08:11 4m 2s wip
wip
August 19, 2024 08:11 4m 2s
Fix performance counter eventxh Scala CI #358: Commit c4b1ad9 pushed by Dolu1990
August 19, 2024 04:41 3m 21s wip
wip
August 19, 2024 04:41 3m 21s
Fix LsuPlugin waiter Scala CI #357: Commit 5f251e7 pushed by Dolu1990
August 13, 2024 08:39 6m 11s wip
wip
August 13, 2024 08:39 6m 11s
Fix FpuUnpacker unpacking done Scala CI #356: Commit 0d5ad63 pushed by Dolu1990
August 13, 2024 01:57 3m 41s dev
dev
August 13, 2024 01:57 3m 41s
mmu interface : replace REDO by REFILL+HAZARD Scala CI #355: Commit 93386cc pushed by Dolu1990
August 7, 2024 14:21 3m 48s dev
dev
August 7, 2024 14:21 3m 48s
Update synt Scala CI #354: Commit 35bd490 pushed by Dolu1990
August 7, 2024 07:25 3m 31s dev
dev
August 7, 2024 07:25 3m 31s
prefetcher imprevment Scala CI #353: Commit e3c1736 pushed by Dolu1990
August 6, 2024 12:00 4m 11s dev
dev
August 6, 2024 12:00 4m 11s
Improve d$ prefetcher by only prefetching if a miss happend (once in … Scala CI #352: Commit 19c80b6 pushed by Dolu1990
August 5, 2024 12:28 3m 23s dev
dev
August 5, 2024 12:28 3m 23s
Merge https://github.com/SpinalHDL/NaxRiscv/pull/120 Scala CI #351: Commit 78351ea pushed by Dolu1990
August 5, 2024 09:34 3m 21s dev
dev
August 5, 2024 09:34 3m 21s
stoptime is now 1 on reset Scala CI #350: Commit 26954d0 pushed by Dolu1990
August 5, 2024 09:13 19m 26s dev
dev
August 5, 2024 09:13 19m 26s
tcl fix Scala CI #349: Commit 0c543f5 pushed by Dolu1990
July 20, 2024 20:18 4m 15s dev
dev
July 20, 2024 20:18 4m 15s
sync Scala CI #348: Commit 36dad63 pushed by Dolu1990
July 18, 2024 09:31 4m 17s dev
dev
July 18, 2024 09:31 4m 17s
sync Scala CI #347: Commit 7b16ef3 pushed by Dolu1990
July 18, 2024 09:25 4m 13s dev
dev
July 18, 2024 09:25 4m 13s
Merge pull request #22 from SpinalHDL/prefetch_i Scala CI #346: Commit 3b8ae0d pushed by Dolu1990
July 18, 2024 09:23 3m 55s dev
dev
July 18, 2024 09:23 3m 55s
Add instruction prefetcher Scala CI #345: Pull request #22 opened by Dolu1990
July 18, 2024 09:23 3m 36s prefetch_i
prefetch_i
July 18, 2024 09:23 3m 36s