From 949014ccde5d256aedfc83f1774e1fa9bacd9a57 Mon Sep 17 00:00:00 2001 From: Cho Moon Date: Fri, 15 Mar 2024 03:28:59 +0000 Subject: [PATCH 01/32] phase 1 for enhanced clock gater handling 1) treat clock gaters like macro cell instances 2) need to change arrival computation Signed-off-by: Cho Moon --- src/cts/include/cts/TritonCTS.h | 11 +- src/cts/src/TreeBuilder.h | 6 + src/cts/src/TritonCTS.cpp | 44 ++++--- src/cts/test/balance_levels.defok | 212 +++++++++--------------------- src/cts/test/balance_levels.ok | 57 +++++--- src/cts/test/balance_levels.py | 3 +- src/cts/test/cts_aux.py | 4 +- 7 files changed, 148 insertions(+), 189 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index 21de9958136..47ee2bc2ac1 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -130,7 +130,7 @@ class TritonCTS // db functions bool masterExists(const std::string& master) const; void populateTritonCTS(); - void writeClockNetsToDb(Clock& clockNet, std::set& clkLeafNets); + void writeClockNetsToDb(TreeBuilder* builder, std::set& clkLeafNets); void writeClockNDRsToDb(const std::set& clkLeafNets); void incrementNumClocks() { ++numberOfClocks_; } void clearNumClocks() { numberOfClocks_ = 0; } @@ -166,7 +166,8 @@ class TritonCTS Clock& clockNet, const std::vector>& registerSinks, odb::dbNet*& firstNet, - odb::dbNet*& secondNet); + odb::dbNet*& secondNet, + std::string& topBufferName); void computeITermPosition(odb::dbITerm* term, int& x, int& y) const; void countSinksPostDbWrite(TreeBuilder* builder, odb::dbNet* net, @@ -212,7 +213,6 @@ class TritonCTS void adjustLatencies(TreeBuilder* macroBuilder, TreeBuilder* registerBuilder); void computeTopBufferDelay(TreeBuilder* builder); odb::dbInst* insertDelayBuffer(odb::dbInst* driver, - int index, const std::string& clockName, int locX, int locY); @@ -240,6 +240,11 @@ class TritonCTS // root buffer and sink bufer candidates std::vector rootBuffers_; std::vector sinkBuffers_; + + // register tree root buffer indices + unsigned regTreeRootBufIndex_ = 0; + // index for delay buffer added for latency adjustment + unsigned delayBufIndex_ = 0; }; } // namespace cts diff --git a/src/cts/src/TreeBuilder.h b/src/cts/src/TreeBuilder.h index 8ac102bc759..ec15843ff06 100644 --- a/src/cts/src/TreeBuilder.h +++ b/src/cts/src/TreeBuilder.h @@ -247,6 +247,10 @@ class TreeBuilder void setTopBufferDelay(float delay) { topBufferDelay_ = delay; } odb::dbInst* getTopBuffer() const { return topBuffer_; } void setTopBuffer(odb::dbInst* inst) { topBuffer_ = inst; } + std::string getTopBufferName() const { return topBufferName_; } + void setTopBufferName(std::string name) { topBufferName_ = name; } + odb::dbNet* getTopInputNet() const { return topInputNet_; } + void setTopInputNet(odb::dbNet* net) { topInputNet_ = net; } protected: CtsOptions* options_ = nullptr; @@ -276,6 +280,8 @@ class TreeBuilder float aveArrival_ = 0.0; float topBufferDelay_ = 0.0; odb::dbInst* topBuffer_ = nullptr; + std::string topBufferName_; + odb::dbNet* topInputNet_ = nullptr; }; } // namespace cts diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index ac1fd07c64c..6dc4d5e5f70 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -359,7 +359,7 @@ void TritonCTS::writeDataToDb() { std::set clkLeafNets; for (TreeBuilder* builder : *builders_) { - writeClockNetsToDb(builder->getClock(), clkLeafNets); + writeClockNetsToDb(builder, clkLeafNets); if (options_->applyNDR()) { writeClockNDRsToDb(clkLeafNets); } @@ -1010,8 +1010,9 @@ HTreeBuilder* TritonCTS::initClockTreeForMacrosAndRegs( // create a new net 'secondNet' to drive register sinks odb::dbNet* secondNet; - Clock clockNet2 - = forkRegisterClockNetwork(clockNet, registerSinks, firstNet, secondNet); + std::string topBufferName; + Clock clockNet2 = forkRegisterClockNetwork( + clockNet, registerSinks, firstNet, secondNet, topBufferName); // add register sinks to secondNet HTreeBuilder* secondBuilder = addClockSinks( @@ -1022,6 +1023,8 @@ HTreeBuilder* TritonCTS::initClockTreeForMacrosAndRegs( "registers"); if (secondBuilder) { secondBuilder->setTreeType(TreeType::RegisterTree); + secondBuilder->setTopBufferName(topBufferName); + secondBuilder->setTopInputNet(firstNet); } return secondBuilder; @@ -1050,7 +1053,8 @@ bool TritonCTS::separateMacroRegSinks( if (iterm->isInputSignal() && inst->isPlaced()) { odb::dbMTerm* mterm = iterm->getMTerm(); - if (hasInsertionDelay(inst, mterm)) { + // Treat clock gaters like macro sink + if (hasInsertionDelay(inst, mterm) || !isSink(iterm)) { macroSinks.emplace_back(inst, mterm); } else { registerSinks.emplace_back(inst, mterm); @@ -1098,7 +1102,8 @@ Clock TritonCTS::forkRegisterClockNetwork( Clock& clockNet, const std::vector>& registerSinks, odb::dbNet*& firstNet, - odb::dbNet*& secondNet) + odb::dbNet*& secondNet, + std::string& topBufferName) { // create a new clock net to drive register sinks std::string newClockName = clockNet.getName() + "_" + "regs"; @@ -1116,8 +1121,10 @@ Clock TritonCTS::forkRegisterClockNetwork( // create a new clock buffer odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str()); - std::string cellName = "clkbuf_regs_0_" + clockNet.getSdcName(); - odb::dbInst* clockBuf = odb::dbInst::create(block_, master, cellName.c_str()); + topBufferName = "clkbuf_regs_" + std::to_string(regTreeRootBufIndex_++) + "_" + + clockNet.getSdcName(); + odb::dbInst* clockBuf + = odb::dbInst::create(block_, master, topBufferName.c_str()); odb::dbITerm* inputTerm = getFirstInput(clockBuf); odb::dbITerm* outputTerm = clockBuf->getFirstOutput(); inputTerm->connect(firstNet); @@ -1162,19 +1169,22 @@ void TritonCTS::computeITermPosition(odb::dbITerm* term, int& x, int& y) const } }; -void TritonCTS::writeClockNetsToDb(Clock& clockNet, +void TritonCTS::writeClockNetsToDb(TreeBuilder* builder, std::set& clkLeafNets) { + Clock& clockNet = builder->getClock(); odb::dbNet* topClockNet = clockNet.getNetObj(); disconnectAllSinksFromNet(topClockNet); // re-connect top buffer that separates macros from registers - std::string topRegBufferName = "clkbuf_regs_0_" + clockNet.getName(); - odb::dbInst* topRegBuffer = block_->findInst(topRegBufferName.c_str()); - if (topRegBuffer) { - odb::dbITerm* topRegBufferInputPin = getFirstInput(topRegBuffer); - topRegBufferInputPin->connect(topClockNet); + if (builder->getTreeType() == TreeType::RegisterTree) { + odb::dbInst* topRegBuffer + = block_->findInst(builder->getTopBufferName().c_str()); + if (topRegBuffer) { + odb::dbITerm* topRegBufferInputPin = getFirstInput(topRegBuffer); + topRegBufferInputPin->connect(builder->getTopInputNet()); + } } createClockBuffers(clockNet); @@ -2032,7 +2042,6 @@ void TritonCTS::adjustLatencies(TreeBuilder* macroBuilder, = builder->legalizeOneBuffer(bufferLoc, options_->getRootBuffer()); odb::dbInst* buffer = insertDelayBuffer(driver, - i, builder->getClock().getSdcName(), legalBufferLoc.getX() * scalingFactor, legalBufferLoc.getY() * scalingFactor); @@ -2050,7 +2059,7 @@ void TritonCTS::computeTopBufferDelay(TreeBuilder* builder) Clock clock = builder->getClock(); std::string topBufferName; if (builder->getTreeType() == TreeType::RegisterTree) { - topBufferName = "clkbuf_regs_0_" + clock.getSdcName(); + topBufferName = builder->getTopBufferName(); } else { topBufferName = "clkbuf_0_" + clock.getName(); } @@ -2084,20 +2093,19 @@ void TritonCTS::computeTopBufferDelay(TreeBuilder* builder) // Create a new delay buffer and connect output pin of driver to input pin of // new buffer. Output pin of new buffer will be connected later. odb::dbInst* TritonCTS::insertDelayBuffer(odb::dbInst* driver, - int index, const std::string& clockName, int locX, int locY) { // creat a new input net std::string newNetName - = "delaynet_" + std::to_string(index) + "_" + clockName; + = "delaynet_" + std::to_string(delayBufIndex_) + "_" + clockName; odb::dbNet* newNet = odb::dbNet::create(block_, newNetName.c_str()); newNet->setSigType(odb::dbSigType::CLOCK); // create a new delay buffer std::string newBufName - = "delaybuf_" + std::to_string(index) + "_" + clockName; + = "delaybuf_" + std::to_string(delayBufIndex_++) + "_" + clockName; odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str()); odb::dbInst* newBuf = odb::dbInst::create(block_, master, newBufName.c_str()); newBuf->setSourceType(odb::dbSourceType::TIMING); diff --git a/src/cts/test/balance_levels.defok b/src/cts/test/balance_levels.defok index c1483a4166b..a231b0515c1 100644 --- a/src/cts/test/balance_levels.defok +++ b/src/cts/test/balance_levels.defok @@ -4,90 +4,45 @@ BUSBITCHARS "[]" ; DESIGN multi_sink ; UNITS DISTANCE MICRONS 2000 ; DIEAREA ( 0 0 ) ( 200000 200000 ) ; -COMPONENTS 383 ; +COMPONENTS 338 ; - CELL/CKGATE BUF_X1 + PLACED ( 100000 100000 ) N ; - clkbuf_0_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 103228 140117 ) N ; - - clkbuf_0_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 103228 51229 ) N ; + - clkbuf_0_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 100250 101225 ) N ; + - clkbuf_0_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 103228 51229 ) N ; + - clkbuf_1_0__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 100250 87225 ) N ; - clkbuf_4_0__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 35318 119627 ) N ; - - clkbuf_4_0__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 37046 24385 ) N ; + - clkbuf_4_0__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 37181 26644 ) N ; - clkbuf_4_10__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 169474 113337 ) N ; - - clkbuf_4_10__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 169474 24449 ) N ; + - clkbuf_4_10__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 169474 24449 ) N ; - clkbuf_4_11__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 176988 120851 ) N ; - - clkbuf_4_11__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 176988 31963 ) N ; + - clkbuf_4_11__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 176988 31963 ) N ; - clkbuf_4_12__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 136180 148710 ) N ; - - clkbuf_4_12__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 135454 59367 ) N ; + - clkbuf_4_12__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 135454 59367 ) N ; - clkbuf_4_13__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 138264 161152 ) N ; - - clkbuf_4_13__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 137599 71599 ) N ; + - clkbuf_4_13__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 137599 71599 ) N ; - clkbuf_4_14__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 175261 148092 ) N ; - - clkbuf_4_14__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 175738 59340 ) N ; + - clkbuf_4_14__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 175738 59340 ) N ; - clkbuf_4_15__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 173171 159411 ) N ; - - clkbuf_4_15__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 173942 71102 ) N ; + - clkbuf_4_15__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 173942 71102 ) N ; - clkbuf_4_1__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 31476 129670 ) N ; - - clkbuf_4_1__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 30387 31043 ) N ; + - clkbuf_4_1__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 28978 35266 ) N ; - clkbuf_4_2__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 68717 119605 ) N ; - - clkbuf_4_2__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 64508 26508 ) N ; + - clkbuf_4_2__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 66913 28914 ) N ; - clkbuf_4_3__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 71061 131581 ) N ; - - clkbuf_4_3__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 71219 35368 ) N ; + - clkbuf_4_3__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 69122 41782 ) N ; - clkbuf_4_4__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 31714 150934 ) N ; - - clkbuf_4_4__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 31830 61223 ) N ; + - clkbuf_4_4__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 30369 61835 ) N ; - clkbuf_4_5__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 33478 164353 ) N ; - - clkbuf_4_5__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 33728 74610 ) N ; + - clkbuf_4_5__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 31247 76899 ) N ; - clkbuf_4_6__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 70729 156126 ) N ; - - clkbuf_4_6__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 68707 60992 ) N ; + - clkbuf_4_6__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 68700 66662 ) N ; - clkbuf_4_7__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 64318 165027 ) N ; - - clkbuf_4_7__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 66599 73858 ) N ; + - clkbuf_4_7__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 64650 75806 ) N ; - clkbuf_4_8__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 115396 ) N ; - - clkbuf_4_8__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 26508 ) N ; + - clkbuf_4_8__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 26508 ) N ; - clkbuf_4_9__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 124256 ) N ; - - clkbuf_4_9__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 35368 ) N ; - - clkbuf_level_0_1_1027_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 133484 35513 ) N ; - - clkbuf_level_0_1_10_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 36329 22762 ) N ; - - clkbuf_level_0_1_1130_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 170571 22017 ) N ; - - clkbuf_level_0_1_1233_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 179381 31532 ) N ; - - clkbuf_level_0_1_1336_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 134033 58567 ) N ; - - clkbuf_level_0_1_1439_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 136203 73072 ) N ; - - clkbuf_level_0_1_1542_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 177253 58502 ) N ; - - clkbuf_level_0_1_1645_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 175553 72615 ) N ; - - clkbuf_level_0_1_23_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 27455 30225 ) N ; - - clkbuf_level_0_1_36_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 66780 23660 ) N ; - - clkbuf_level_0_1_49_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 72971 35513 ) N ; - - clkbuf_level_0_1_512_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 30235 60113 ) N ; - - clkbuf_level_0_1_615_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 31658 77098 ) N ; - - clkbuf_level_0_1_718_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 70393 59940 ) N ; - - clkbuf_level_0_1_821_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 68117 75839 ) N ; - - clkbuf_level_0_1_924_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 139675 23660 ) N ; - - clkbuf_level_1_1_1028_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 131732 35659 ) N ; - - clkbuf_level_1_1_1131_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 171668 19585 ) N ; - - clkbuf_level_1_1_11_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 35613 21140 ) N ; - - clkbuf_level_1_1_1234_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 181774 31102 ) N ; - - clkbuf_level_1_1_1337_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 132612 57767 ) N ; - - clkbuf_level_1_1_1440_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 134807 74545 ) N ; - - clkbuf_level_1_1_1543_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 178768 57665 ) N ; - - clkbuf_level_1_1_1646_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 177165 74128 ) N ; - - clkbuf_level_1_1_24_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 24524 29407 ) N ; - - clkbuf_level_1_1_37_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 69053 20813 ) N ; - - clkbuf_level_1_1_410_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 74723 35659 ) N ; - - clkbuf_level_1_1_513_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 28640 59003 ) N ; - - clkbuf_level_1_1_616_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 29589 79586 ) N ; - - clkbuf_level_1_1_719_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 72079 58888 ) N ; - - clkbuf_level_1_1_822_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 69636 77821 ) N ; - - clkbuf_level_1_1_925_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 137402 20813 ) N ; - - clkbuf_level_2_1_1029_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 129980 35805 ) N ; - - clkbuf_level_2_1_1132_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 172765 17153 ) N ; - - clkbuf_level_2_1_1235_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 184167 30671 ) N ; - - clkbuf_level_2_1_12_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 34897 19518 ) N ; - - clkbuf_level_2_1_1338_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 131192 56967 ) N ; - - clkbuf_level_2_1_1441_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 133411 76018 ) N ; - - clkbuf_level_2_1_1544_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 180283 56828 ) N ; - - clkbuf_level_2_1_1647_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 178776 75641 ) N ; - - clkbuf_level_2_1_25_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 21592 28590 ) N ; - - clkbuf_level_2_1_38_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 71326 17965 ) N ; - - clkbuf_level_2_1_411_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 76476 35805 ) N ; - - clkbuf_level_2_1_514_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 27046 57894 ) N ; - - clkbuf_level_2_1_617_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 27520 82074 ) N ; - - clkbuf_level_2_1_720_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 73765 57836 ) N ; - - clkbuf_level_2_1_823_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 71154 79802 ) N ; - - clkbuf_level_2_1_926_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 135130 17965 ) N ; + - clkbuf_4_9__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 35368 ) N ; + - clkbuf_regs_0_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 99481 48451 ) N ; - ff0 DFF_X1 + PLACED ( 5555 5555 ) N ; - ff1 DFF_X1 + PLACED ( 16666 5555 ) N ; - ff10 DFF_X1 + PLACED ( 116665 5555 ) N ; @@ -395,125 +350,80 @@ PINS 1 ; + LAYER metal6 ( -140 -140 ) ( 140 140 ) + FIXED ( 100000 199860 ) N ; END PINS -NETS 84 ; +NETS 39 ; - CELL/clk2 ( clkbuf_0_CELL\/clk2 A ) ( CELL/CKGATE Z ) + USE CLOCK ; - - clk ( PIN clk ) ( clkbuf_0_clk A ) + USE CLOCK ; + - clk ( PIN clk ) ( clkbuf_regs_0_clk A ) ( clkbuf_0_clk A ) + USE CLOCK ; + - clk_regs ( clkbuf_0_clk_regs A ) ( clkbuf_regs_0_clk Z ) + USE CLOCK ; - clknet_0_CELL\/clk2 ( clkbuf_4_15__f_CELL\/clk2 A ) ( clkbuf_4_14__f_CELL\/clk2 A ) ( clkbuf_4_13__f_CELL\/clk2 A ) ( clkbuf_4_12__f_CELL\/clk2 A ) ( clkbuf_4_11__f_CELL\/clk2 A ) ( clkbuf_4_10__f_CELL\/clk2 A ) ( clkbuf_4_9__f_CELL\/clk2 A ) ( clkbuf_4_8__f_CELL\/clk2 A ) ( clkbuf_4_7__f_CELL\/clk2 A ) ( clkbuf_4_6__f_CELL\/clk2 A ) ( clkbuf_4_5__f_CELL\/clk2 A ) ( clkbuf_4_4__f_CELL\/clk2 A ) ( clkbuf_4_3__f_CELL\/clk2 A ) ( clkbuf_4_2__f_CELL\/clk2 A ) ( clkbuf_4_1__f_CELL\/clk2 A ) ( clkbuf_4_0__f_CELL\/clk2 A ) ( clkbuf_0_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_0_clk ( clkbuf_4_15__f_clk A ) ( clkbuf_4_14__f_clk A ) ( clkbuf_4_13__f_clk A ) ( clkbuf_4_12__f_clk A ) ( clkbuf_4_11__f_clk A ) ( clkbuf_4_10__f_clk A ) ( clkbuf_4_9__f_clk A ) - ( clkbuf_4_8__f_clk A ) ( clkbuf_4_7__f_clk A ) ( clkbuf_4_6__f_clk A ) ( clkbuf_4_5__f_clk A ) ( clkbuf_4_4__f_clk A ) ( clkbuf_4_3__f_clk A ) ( clkbuf_4_2__f_clk A ) ( clkbuf_4_1__f_clk A ) - ( clkbuf_4_0__f_clk A ) ( clkbuf_0_clk Z ) + USE CLOCK ; + - clknet_0_clk ( clkbuf_0_clk Z ) ( clkbuf_1_0__f_clk A ) + USE CLOCK ; + - clknet_0_clk_regs ( clkbuf_4_15__f_clk_regs A ) ( clkbuf_4_14__f_clk_regs A ) ( clkbuf_4_13__f_clk_regs A ) ( clkbuf_4_12__f_clk_regs A ) ( clkbuf_4_11__f_clk_regs A ) ( clkbuf_4_10__f_clk_regs A ) ( clkbuf_4_9__f_clk_regs A ) + ( clkbuf_4_8__f_clk_regs A ) ( clkbuf_4_7__f_clk_regs A ) ( clkbuf_4_6__f_clk_regs A ) ( clkbuf_4_5__f_clk_regs A ) ( clkbuf_4_4__f_clk_regs A ) ( clkbuf_4_3__f_clk_regs A ) ( clkbuf_4_2__f_clk_regs A ) ( clkbuf_4_1__f_clk_regs A ) + ( clkbuf_4_0__f_clk_regs A ) ( clkbuf_0_clk_regs Z ) + USE CLOCK ; + - clknet_1_0__leaf_clk ( CELL/CKGATE A ) ( clkbuf_1_0__f_clk Z ) + USE CLOCK ; - clknet_4_0__leaf_CELL\/clk2 ( ff162 CK ) ( ff163 CK ) ( ff164 CK ) ( ff165 CK ) ( ff180 CK ) ( ff181 CK ) ( ff182 CK ) ( ff183 CK ) ( ff184 CK ) ( clkbuf_4_0__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_0__leaf_clk ( clkbuf_level_0_1_10_clk A ) ( clkbuf_4_0__f_clk Z ) + USE CLOCK ; + - clknet_4_0__leaf_clk_regs ( ff0 CK ) ( ff1 CK ) ( ff2 CK ) ( ff3 CK ) ( ff18 CK ) ( ff19 CK ) ( ff20 CK ) + ( ff21 CK ) ( ff39 CK ) ( ff40 CK ) ( clkbuf_4_0__f_clk_regs Z ) + USE CLOCK ; - clknet_4_10__leaf_CELL\/clk2 ( ff158 CK ) ( ff159 CK ) ( ff160 CK ) ( ff176 CK ) ( ff177 CK ) ( ff178 CK ) ( ff194 CK ) ( clkbuf_4_10__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_10__leaf_clk ( clkbuf_level_0_1_1130_clk A ) ( clkbuf_4_10__f_clk Z ) + USE CLOCK ; + - clknet_4_10__leaf_clk_regs ( ff14 CK ) ( ff15 CK ) ( ff16 CK ) ( ff32 CK ) ( ff33 CK ) ( ff34 CK ) ( ff50 CK ) + ( clkbuf_4_10__f_clk_regs Z ) + USE CLOCK ; - clknet_4_11__leaf_CELL\/clk2 ( ff161 CK ) ( ff179 CK ) ( ff195 CK ) ( ff196 CK ) ( ff197 CK ) ( ff212 CK ) ( ff213 CK ) ( ff214 CK ) ( ff215 CK ) ( clkbuf_4_11__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_11__leaf_clk ( clkbuf_level_0_1_1233_clk A ) ( clkbuf_4_11__f_clk Z ) + USE CLOCK ; + - clknet_4_11__leaf_clk_regs ( ff17 CK ) ( ff35 CK ) ( ff51 CK ) ( ff52 CK ) ( ff53 CK ) ( ff68 CK ) ( ff69 CK ) + ( ff70 CK ) ( ff71 CK ) ( clkbuf_4_11__f_clk_regs Z ) + USE CLOCK ; - clknet_4_12__leaf_CELL\/clk2 ( ff225 CK ) ( ff226 CK ) ( ff227 CK ) ( ff228 CK ) ( ff229 CK ) ( ff243 CK ) ( ff244 CK ) ( ff245 CK ) ( ff246 CK ) ( ff247 CK ) ( clkbuf_4_12__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_12__leaf_clk ( clkbuf_level_0_1_1336_clk A ) ( clkbuf_4_12__f_clk Z ) + USE CLOCK ; + - clknet_4_12__leaf_clk_regs ( ff81 CK ) ( ff82 CK ) ( ff83 CK ) ( ff84 CK ) ( ff85 CK ) ( ff99 CK ) ( ff100 CK ) + ( ff101 CK ) ( ff103 CK ) ( clkbuf_4_12__f_clk_regs Z ) + USE CLOCK ; - clknet_4_13__leaf_CELL\/clk2 ( ff261 CK ) ( ff262 CK ) ( ff263 CK ) ( ff264 CK ) ( ff265 CK ) ( ff279 CK ) ( ff280 CK ) ( ff281 CK ) ( ff282 CK ) ( ff283 CK ) ( ff297 CK ) ( ff298 CK ) ( ff299 CK ) ( clkbuf_4_13__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_13__leaf_clk ( clkbuf_level_0_1_1439_clk A ) ( clkbuf_4_13__f_clk Z ) + USE CLOCK ; + - clknet_4_13__leaf_clk_regs ( ff102 CK ) ( ff117 CK ) ( ff118 CK ) ( ff119 CK ) ( ff120 CK ) ( ff121 CK ) ( ff135 CK ) + ( ff136 CK ) ( ff137 CK ) ( ff138 CK ) ( ff139 CK ) ( clkbuf_4_13__f_clk_regs Z ) + USE CLOCK ; - clknet_4_14__leaf_CELL\/clk2 ( ff230 CK ) ( ff231 CK ) ( ff232 CK ) ( ff233 CK ) ( ff248 CK ) ( ff250 CK ) ( ff251 CK ) ( clkbuf_4_14__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_14__leaf_clk ( clkbuf_level_0_1_1542_clk A ) ( clkbuf_4_14__f_clk Z ) + USE CLOCK ; + - clknet_4_14__leaf_clk_regs ( ff86 CK ) ( ff87 CK ) ( ff88 CK ) ( ff89 CK ) ( ff104 CK ) ( ff106 CK ) ( ff107 CK ) + ( clkbuf_4_14__f_clk_regs Z ) + USE CLOCK ; - clknet_4_15__leaf_CELL\/clk2 ( ff249 CK ) ( ff266 CK ) ( ff267 CK ) ( ff268 CK ) ( ff269 CK ) ( ff284 CK ) ( ff285 CK ) ( ff286 CK ) ( ff287 CK ) ( clkbuf_4_15__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_15__leaf_clk ( clkbuf_level_0_1_1645_clk A ) ( clkbuf_4_15__f_clk Z ) + USE CLOCK ; + - clknet_4_15__leaf_clk_regs ( ff105 CK ) ( ff122 CK ) ( ff123 CK ) ( ff124 CK ) ( ff125 CK ) ( ff140 CK ) ( ff141 CK ) + ( ff142 CK ) ( ff143 CK ) ( clkbuf_4_15__f_clk_regs Z ) + USE CLOCK ; - clknet_4_1__leaf_CELL\/clk2 ( ff198 CK ) ( ff199 CK ) ( ff200 CK ) ( ff201 CK ) ( ff202 CK ) ( ff216 CK ) ( clkbuf_4_1__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_1__leaf_clk ( clkbuf_level_0_1_23_clk A ) ( clkbuf_4_1__f_clk Z ) + USE CLOCK ; + - clknet_4_1__leaf_clk_regs ( ff36 CK ) ( ff37 CK ) ( ff38 CK ) ( ff54 CK ) ( ff55 CK ) ( ff56 CK ) ( ff57 CK ) + ( clkbuf_4_1__f_clk_regs Z ) + USE CLOCK ; - clknet_4_2__leaf_CELL\/clk2 ( ff150 CK ) ( ff151 CK ) ( ff152 CK ) ( ff166 CK ) ( ff167 CK ) ( ff168 CK ) ( ff169 CK ) ( ff170 CK ) ( ff185 CK ) ( ff186 CK ) ( ff187 CK ) ( ff188 CK ) ( clkbuf_4_2__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_2__leaf_clk ( clkbuf_level_0_1_36_clk A ) ( clkbuf_4_2__f_clk Z ) + USE CLOCK ; + - clknet_4_2__leaf_clk_regs ( ff4 CK ) ( ff5 CK ) ( ff6 CK ) ( ff7 CK ) ( ff8 CK ) ( ff22 CK ) ( ff23 CK ) + ( ff24 CK ) ( ff25 CK ) ( ff26 CK ) ( ff41 CK ) ( ff42 CK ) ( ff43 CK ) ( ff44 CK ) ( clkbuf_4_2__f_clk_regs Z ) + USE CLOCK ; - clknet_4_3__leaf_CELL\/clk2 ( ff203 CK ) ( ff204 CK ) ( ff205 CK ) ( ff206 CK ) ( ff220 CK ) ( ff221 CK ) ( ff222 CK ) ( ff223 CK ) ( ff224 CK ) ( clkbuf_4_3__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_3__leaf_clk ( clkbuf_level_0_1_49_clk A ) ( clkbuf_4_3__f_clk Z ) + USE CLOCK ; + - clknet_4_3__leaf_clk_regs ( ff58 CK ) ( ff59 CK ) ( ff60 CK ) ( ff61 CK ) ( ff62 CK ) ( ff76 CK ) ( ff77 CK ) + ( ff78 CK ) ( ff79 CK ) ( ff80 CK ) ( clkbuf_4_3__f_clk_regs Z ) + USE CLOCK ; - clknet_4_4__leaf_CELL\/clk2 ( ff217 CK ) ( ff218 CK ) ( ff219 CK ) ( ff234 CK ) ( ff235 CK ) ( ff236 CK ) ( ff237 CK ) ( ff254 CK ) ( clkbuf_4_4__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_4__leaf_clk ( clkbuf_level_0_1_512_clk A ) ( clkbuf_4_4__f_clk Z ) + USE CLOCK ; + - clknet_4_4__leaf_clk_regs ( ff72 CK ) ( ff73 CK ) ( ff74 CK ) ( ff75 CK ) ( ff90 CK ) ( ff91 CK ) ( ff92 CK ) + ( ff93 CK ) ( clkbuf_4_4__f_clk_regs Z ) + USE CLOCK ; - clknet_4_5__leaf_CELL\/clk2 ( ff252 CK ) ( ff253 CK ) ( ff255 CK ) ( ff270 CK ) ( ff271 CK ) ( ff272 CK ) ( ff273 CK ) ( ff288 CK ) ( ff289 CK ) ( ff290 CK ) ( ff291 CK ) ( clkbuf_4_5__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_5__leaf_clk ( clkbuf_level_0_1_615_clk A ) ( clkbuf_4_5__f_clk Z ) + USE CLOCK ; + - clknet_4_5__leaf_clk_regs ( ff108 CK ) ( ff109 CK ) ( ff110 CK ) ( ff111 CK ) ( ff126 CK ) ( ff127 CK ) ( ff128 CK ) + ( ff129 CK ) ( ff144 CK ) ( ff145 CK ) ( ff146 CK ) ( ff147 CK ) ( clkbuf_4_5__f_clk_regs Z ) + USE CLOCK ; - clknet_4_6__leaf_CELL\/clk2 ( ff238 CK ) ( ff239 CK ) ( ff240 CK ) ( ff241 CK ) ( ff242 CK ) ( ff257 CK ) ( ff259 CK ) ( ff260 CK ) ( clkbuf_4_6__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_6__leaf_clk ( clkbuf_level_0_1_718_clk A ) ( clkbuf_4_6__f_clk Z ) + USE CLOCK ; + - clknet_4_6__leaf_clk_regs ( ff94 CK ) ( ff95 CK ) ( ff96 CK ) ( ff97 CK ) ( ff98 CK ) ( ff113 CK ) ( ff114 CK ) + ( clkbuf_4_6__f_clk_regs Z ) + USE CLOCK ; - clknet_4_7__leaf_CELL\/clk2 ( ff256 CK ) ( ff258 CK ) ( ff274 CK ) ( ff275 CK ) ( ff276 CK ) ( ff277 CK ) ( ff278 CK ) ( ff292 CK ) ( ff293 CK ) ( ff294 CK ) ( ff295 CK ) ( ff296 CK ) ( clkbuf_4_7__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_7__leaf_clk ( CELL/CKGATE A ) ( clkbuf_level_0_1_821_clk A ) ( clkbuf_4_7__f_clk Z ) + USE CLOCK ; + - clknet_4_7__leaf_clk_regs ( ff112 CK ) ( ff115 CK ) ( ff116 CK ) ( ff130 CK ) ( ff131 CK ) ( ff132 CK ) ( ff133 CK ) + ( ff134 CK ) ( ff148 CK ) ( ff149 CK ) ( clkbuf_4_7__f_clk_regs Z ) + USE CLOCK ; - clknet_4_8__leaf_CELL\/clk2 ( ff153 CK ) ( ff154 CK ) ( ff155 CK ) ( ff156 CK ) ( ff157 CK ) ( ff171 CK ) ( ff172 CK ) ( ff173 CK ) ( ff174 CK ) ( ff175 CK ) ( ff191 CK ) ( ff193 CK ) ( clkbuf_4_8__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_8__leaf_clk ( clkbuf_level_0_1_924_clk A ) ( clkbuf_4_8__f_clk Z ) + USE CLOCK ; + - clknet_4_8__leaf_clk_regs ( ff9 CK ) ( ff10 CK ) ( ff11 CK ) ( ff12 CK ) ( ff13 CK ) ( ff27 CK ) ( ff28 CK ) + ( ff29 CK ) ( ff30 CK ) ( ff31 CK ) ( ff47 CK ) ( ff49 CK ) ( clkbuf_4_8__f_clk_regs Z ) + USE CLOCK ; - clknet_4_9__leaf_CELL\/clk2 ( ff189 CK ) ( ff190 CK ) ( ff192 CK ) ( ff207 CK ) ( ff208 CK ) ( ff209 CK ) ( ff210 CK ) ( ff211 CK ) ( clkbuf_4_9__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_9__leaf_clk ( clkbuf_level_0_1_1027_clk A ) ( clkbuf_4_9__f_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1027_clk ( clkbuf_level_1_1_1028_clk A ) ( clkbuf_level_0_1_1027_clk Z ) + USE CLOCK ; - - clknet_level_0_1_10_clk ( clkbuf_level_1_1_11_clk A ) ( clkbuf_level_0_1_10_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1130_clk ( clkbuf_level_1_1_1131_clk A ) ( clkbuf_level_0_1_1130_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1233_clk ( clkbuf_level_1_1_1234_clk A ) ( clkbuf_level_0_1_1233_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1336_clk ( clkbuf_level_1_1_1337_clk A ) ( clkbuf_level_0_1_1336_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1439_clk ( clkbuf_level_1_1_1440_clk A ) ( clkbuf_level_0_1_1439_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1542_clk ( clkbuf_level_1_1_1543_clk A ) ( clkbuf_level_0_1_1542_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1645_clk ( clkbuf_level_1_1_1646_clk A ) ( clkbuf_level_0_1_1645_clk Z ) + USE CLOCK ; - - clknet_level_0_1_23_clk ( clkbuf_level_1_1_24_clk A ) ( clkbuf_level_0_1_23_clk Z ) + USE CLOCK ; - - clknet_level_0_1_36_clk ( clkbuf_level_1_1_37_clk A ) ( clkbuf_level_0_1_36_clk Z ) + USE CLOCK ; - - clknet_level_0_1_49_clk ( clkbuf_level_1_1_410_clk A ) ( clkbuf_level_0_1_49_clk Z ) + USE CLOCK ; - - clknet_level_0_1_512_clk ( clkbuf_level_1_1_513_clk A ) ( clkbuf_level_0_1_512_clk Z ) + USE CLOCK ; - - clknet_level_0_1_615_clk ( clkbuf_level_1_1_616_clk A ) ( clkbuf_level_0_1_615_clk Z ) + USE CLOCK ; - - clknet_level_0_1_718_clk ( clkbuf_level_1_1_719_clk A ) ( clkbuf_level_0_1_718_clk Z ) + USE CLOCK ; - - clknet_level_0_1_821_clk ( clkbuf_level_1_1_822_clk A ) ( clkbuf_level_0_1_821_clk Z ) + USE CLOCK ; - - clknet_level_0_1_924_clk ( clkbuf_level_1_1_925_clk A ) ( clkbuf_level_0_1_924_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1028_clk ( clkbuf_level_2_1_1029_clk A ) ( clkbuf_level_1_1_1028_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1131_clk ( clkbuf_level_2_1_1132_clk A ) ( clkbuf_level_1_1_1131_clk Z ) + USE CLOCK ; - - clknet_level_1_1_11_clk ( clkbuf_level_2_1_12_clk A ) ( clkbuf_level_1_1_11_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1234_clk ( clkbuf_level_2_1_1235_clk A ) ( clkbuf_level_1_1_1234_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1337_clk ( clkbuf_level_2_1_1338_clk A ) ( clkbuf_level_1_1_1337_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1440_clk ( clkbuf_level_2_1_1441_clk A ) ( clkbuf_level_1_1_1440_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1543_clk ( clkbuf_level_2_1_1544_clk A ) ( clkbuf_level_1_1_1543_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1646_clk ( clkbuf_level_2_1_1647_clk A ) ( clkbuf_level_1_1_1646_clk Z ) + USE CLOCK ; - - clknet_level_1_1_24_clk ( clkbuf_level_2_1_25_clk A ) ( clkbuf_level_1_1_24_clk Z ) + USE CLOCK ; - - clknet_level_1_1_37_clk ( clkbuf_level_2_1_38_clk A ) ( clkbuf_level_1_1_37_clk Z ) + USE CLOCK ; - - clknet_level_1_1_410_clk ( clkbuf_level_2_1_411_clk A ) ( clkbuf_level_1_1_410_clk Z ) + USE CLOCK ; - - clknet_level_1_1_513_clk ( clkbuf_level_2_1_514_clk A ) ( clkbuf_level_1_1_513_clk Z ) + USE CLOCK ; - - clknet_level_1_1_616_clk ( clkbuf_level_2_1_617_clk A ) ( clkbuf_level_1_1_616_clk Z ) + USE CLOCK ; - - clknet_level_1_1_719_clk ( clkbuf_level_2_1_720_clk A ) ( clkbuf_level_1_1_719_clk Z ) + USE CLOCK ; - - clknet_level_1_1_822_clk ( clkbuf_level_2_1_823_clk A ) ( clkbuf_level_1_1_822_clk Z ) + USE CLOCK ; - - clknet_level_1_1_925_clk ( clkbuf_level_2_1_926_clk A ) ( clkbuf_level_1_1_925_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1029_clk ( ff45 CK ) ( ff46 CK ) ( ff48 CK ) ( ff63 CK ) ( ff64 CK ) ( ff65 CK ) ( ff66 CK ) - ( ff67 CK ) ( clkbuf_level_2_1_1029_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1132_clk ( ff14 CK ) ( ff15 CK ) ( ff16 CK ) ( ff32 CK ) ( ff33 CK ) ( ff34 CK ) ( ff50 CK ) - ( clkbuf_level_2_1_1132_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1235_clk ( ff17 CK ) ( ff35 CK ) ( ff51 CK ) ( ff52 CK ) ( ff53 CK ) ( ff68 CK ) ( ff69 CK ) - ( ff70 CK ) ( ff71 CK ) ( clkbuf_level_2_1_1235_clk Z ) + USE CLOCK ; - - clknet_level_2_1_12_clk ( ff0 CK ) ( ff2 CK ) ( ff3 CK ) ( ff20 CK ) ( ff21 CK ) ( ff39 CK ) ( ff57 CK ) - ( clkbuf_level_2_1_12_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1338_clk ( ff81 CK ) ( ff82 CK ) ( ff83 CK ) ( ff84 CK ) ( ff85 CK ) ( ff99 CK ) ( ff100 CK ) - ( ff101 CK ) ( ff103 CK ) ( clkbuf_level_2_1_1338_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1441_clk ( ff102 CK ) ( ff117 CK ) ( ff118 CK ) ( ff119 CK ) ( ff120 CK ) ( ff121 CK ) ( ff135 CK ) - ( ff136 CK ) ( ff137 CK ) ( ff138 CK ) ( ff139 CK ) ( clkbuf_level_2_1_1441_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1544_clk ( ff86 CK ) ( ff87 CK ) ( ff88 CK ) ( ff89 CK ) ( ff104 CK ) ( ff106 CK ) ( ff107 CK ) - ( clkbuf_level_2_1_1544_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1647_clk ( ff105 CK ) ( ff122 CK ) ( ff123 CK ) ( ff124 CK ) ( ff125 CK ) ( ff140 CK ) ( ff141 CK ) - ( ff142 CK ) ( ff143 CK ) ( clkbuf_level_2_1_1647_clk Z ) + USE CLOCK ; - - clknet_level_2_1_25_clk ( ff1 CK ) ( ff18 CK ) ( ff19 CK ) ( ff36 CK ) ( ff37 CK ) ( ff38 CK ) ( ff54 CK ) - ( ff55 CK ) ( ff56 CK ) ( clkbuf_level_2_1_25_clk Z ) + USE CLOCK ; - - clknet_level_2_1_38_clk ( ff4 CK ) ( ff5 CK ) ( ff6 CK ) ( ff7 CK ) ( ff8 CK ) ( ff22 CK ) ( ff23 CK ) - ( ff24 CK ) ( ff25 CK ) ( ff26 CK ) ( ff40 CK ) ( ff42 CK ) ( clkbuf_level_2_1_38_clk Z ) + USE CLOCK ; - - clknet_level_2_1_411_clk ( ff41 CK ) ( ff43 CK ) ( ff44 CK ) ( ff58 CK ) ( ff59 CK ) ( ff60 CK ) ( ff61 CK ) - ( ff62 CK ) ( clkbuf_level_2_1_411_clk Z ) + USE CLOCK ; - - clknet_level_2_1_514_clk ( ff72 CK ) ( ff73 CK ) ( ff74 CK ) ( ff75 CK ) ( ff90 CK ) ( ff91 CK ) ( ff92 CK ) - ( ff93 CK ) ( clkbuf_level_2_1_514_clk Z ) + USE CLOCK ; - - clknet_level_2_1_617_clk ( ff108 CK ) ( ff109 CK ) ( ff110 CK ) ( ff111 CK ) ( ff126 CK ) ( ff127 CK ) ( ff128 CK ) - ( ff129 CK ) ( ff144 CK ) ( ff145 CK ) ( ff146 CK ) ( ff147 CK ) ( clkbuf_level_2_1_617_clk Z ) + USE CLOCK ; - - clknet_level_2_1_720_clk ( ff76 CK ) ( ff77 CK ) ( ff78 CK ) ( ff79 CK ) ( ff80 CK ) ( ff94 CK ) ( ff95 CK ) - ( ff96 CK ) ( ff97 CK ) ( ff98 CK ) ( clkbuf_level_2_1_720_clk Z ) + USE CLOCK ; - - clknet_level_2_1_823_clk ( ff112 CK ) ( ff113 CK ) ( ff114 CK ) ( ff115 CK ) ( ff116 CK ) ( ff130 CK ) ( ff131 CK ) - ( ff132 CK ) ( ff133 CK ) ( ff134 CK ) ( ff148 CK ) ( ff149 CK ) ( clkbuf_level_2_1_823_clk Z ) + USE CLOCK ; - - clknet_level_2_1_926_clk ( ff9 CK ) ( ff10 CK ) ( ff11 CK ) ( ff12 CK ) ( ff13 CK ) ( ff27 CK ) ( ff28 CK ) - ( ff29 CK ) ( ff30 CK ) ( ff31 CK ) ( ff47 CK ) ( ff49 CK ) ( clkbuf_level_2_1_926_clk Z ) + USE CLOCK ; + - clknet_4_9__leaf_clk_regs ( ff45 CK ) ( ff46 CK ) ( ff48 CK ) ( ff63 CK ) ( ff64 CK ) ( ff65 CK ) ( ff66 CK ) + ( ff67 CK ) ( clkbuf_4_9__f_clk_regs Z ) + USE CLOCK ; END NETS END DESIGN diff --git a/src/cts/test/balance_levels.ok b/src/cts/test/balance_levels.ok index 7fc24514d43..5e134a7f6f7 100644 --- a/src/cts/test/balance_levels.ok +++ b/src/cts/test/balance_levels.ok @@ -9,14 +9,34 @@ CLKBUF_X3 [INFO CTS-0049] Characterization buffer is CLKBUF_X3. [INFO CTS-0007] Net "clk" found for clock "clk". -[INFO CTS-0010] Clock net "clk" has 151 sinks. +[INFO CTS-0011] Clock net "clk" for macros has 1 sinks. +[INFO CTS-0011] Clock net "clk_regs" for registers has 150 sinks. [INFO CTS-0010] Clock net "CELL/clk2" has 150 sinks. -[INFO CTS-0008] TritonCTS found 2 clock nets. +[INFO CTS-0008] TritonCTS found 3 clock nets. [INFO CTS-0097] Characterization used 1 buffer(s) types. [INFO CTS-0200] 0 placement blockages have been identified. [INFO CTS-0201] 0 placed hard macros will be treated like blockages. [INFO CTS-0027] Generating H-Tree topology for net clk. -[INFO CTS-0028] Total number of sinks: 151. +[INFO CTS-0028] Total number of sinks: 1. +[INFO CTS-0029] Sinks will be clustered in groups of up to 5 and with maximum cluster diameter of 60.0 um. +[INFO CTS-0030] Number of static layers: 1. +[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). +[INFO CTS-0021] Distance between buffers: 7 units (100 um). +[INFO CTS-0023] Original sink region: [(100250, 101225), (100250, 101225)]. +[INFO CTS-0024] Normalized sink region: [(7.16071, 7.23036), (7.16071, 7.23036)]. +[INFO CTS-0025] Width: 0.0000. +[INFO CTS-0026] Height: 0.0000. + Level 1 + Direction: Vertical + Sinks per sub-region: 1 + Sub-region size: 0.0000 X 0.0000 +[INFO CTS-0034] Segment length (rounded): 1. +[INFO CTS-0032] Stop criterion found. Max number of sinks is 15. +[INFO CTS-0035] Number of sinks covered: 1. +[INFO CTS-0200] 0 placement blockages have been identified. +[INFO CTS-0201] 0 placed hard macros will be treated like blockages. +[INFO CTS-0027] Generating H-Tree topology for net clk_regs. +[INFO CTS-0028] Total number of sinks: 150. [INFO CTS-0029] Sinks will be clustered in groups of up to 5 and with maximum cluster diameter of 60.0 um. [INFO CTS-0030] Number of static layers: 1. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). @@ -27,7 +47,7 @@ [INFO CTS-0026] Height: 6.3491. Level 1 Direction: Horizontal - Sinks per sub-region: 76 + Sinks per sub-region: 75 Sub-region size: 6.7460 X 6.3491 [INFO CTS-0034] Segment length (rounded): 4. Level 2 @@ -46,7 +66,7 @@ Sub-region size: 3.3730 X 1.5873 [INFO CTS-0034] Segment length (rounded): 1. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. -[INFO CTS-0035] Number of sinks covered: 151. +[INFO CTS-0035] Number of sinks covered: 150. [INFO CTS-0200] 0 placement blockages have been identified. [INFO CTS-0201] 0 placed hard macros will be treated like blockages. [INFO CTS-0027] Generating H-Tree topology for net CELL\/clk2. @@ -81,13 +101,18 @@ [INFO CTS-0034] Segment length (rounded): 1. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. [INFO CTS-0035] Number of sinks covered: 150. -[INFO CTS-0093] Fixing tree levels for max depth 5 -Fixing from level 2 (parent=0 + current=2) to max 5 for driver clk -[INFO CTS-0018] Created 65 clock buffers. +[INFO CTS-0018] Created 3 clock buffers. +[INFO CTS-0012] Minimum number of buffers in the clock path: 2. +[INFO CTS-0013] Maximum number of buffers in the clock path: 2. +[INFO CTS-0014] 1 clock nets were removed/fixed. +[INFO CTS-0015] Created 2 clock nets. +[INFO CTS-0016] Fanout distribution for the current clock = 0:1, 1:1.. +[INFO CTS-0017] Max level of the clock tree: 1. +[INFO CTS-0018] Created 17 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. -[INFO CTS-0013] Maximum number of buffers in the clock path: 5. -[INFO CTS-0015] Created 65 clock nets. -[INFO CTS-0016] Fanout distribution for the current clock = 2:1, 7:3, 8:3, 9:4, 10:1, 11:1, 12:4.. +[INFO CTS-0013] Maximum number of buffers in the clock path: 2. +[INFO CTS-0015] Created 17 clock nets. +[INFO CTS-0016] Fanout distribution for the current clock = 7:4, 8:2, 9:3, 10:3, 11:1, 12:2, 14:1.. [INFO CTS-0017] Max level of the clock tree: 4. [INFO CTS-0018] Created 17 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. @@ -95,11 +120,13 @@ Fixing from level 2 (parent=0 + current=2) to max 5 for driver clk [INFO CTS-0015] Created 17 clock nets. [INFO CTS-0016] Fanout distribution for the current clock = 6:1, 7:2, 8:3, 9:4, 10:1, 11:1, 12:3, 13:1.. [INFO CTS-0017] Max level of the clock tree: 4. -[INFO CTS-0098] Clock net "clk" -[INFO CTS-0099] Sinks 151 +[INFO CTS-0124] Clock net "clk" +[INFO CTS-0125] Sinks 1 +[INFO CTS-0098] Clock net "clk_regs" +[INFO CTS-0099] Sinks 150 [INFO CTS-0100] Leaf buffers 0 -[INFO CTS-0101] Average sink wire length 125.08 um -[INFO CTS-0102] Path depth 2 - 5 +[INFO CTS-0101] Average sink wire length 48.98 um +[INFO CTS-0102] Path depth 2 - 2 [INFO CTS-0098] Clock net "CELL\/clk2" [INFO CTS-0099] Sinks 150 [INFO CTS-0100] Leaf buffers 0 diff --git a/src/cts/test/balance_levels.py b/src/cts/test/balance_levels.py index c285c0505f2..0e1cbca069c 100644 --- a/src/cts/test/balance_levels.py +++ b/src/cts/test/balance_levels.py @@ -24,7 +24,8 @@ sink_clustering_max_diameter=60.0, balance_levels=True, num_static_layers=1, - obstruction_aware=True + obstruction_aware=True, + insertion_delay=True ) def_file = helpers.make_result_file("balance_levels.def") diff --git a/src/cts/test/cts_aux.py b/src/cts/test/cts_aux.py index 2b2fd7b6a58..cd9e178d624 100644 --- a/src/cts/test/cts_aux.py +++ b/src/cts/test/cts_aux.py @@ -52,7 +52,8 @@ def clock_tree_synthesis(design, *, num_static_layers=None, sink_clustering_buffer=None, obstruction_aware=False, - apply_ndr=False + apply_ndr=False, + insertion_delay=True ): cts = design.getTritonCts() @@ -62,6 +63,7 @@ def clock_tree_synthesis(design, *, parms.setSinkClustering(sink_clustering_enable) parms.setBalanceLevels(balance_levels) parms.setObstructionAware(obstruction_aware) + parms.enableInsertionDelay(insertion_delay) parms.setApplyNDR(apply_ndr) if is_pos_int(sink_clustering_size): From 747e4a932a3c677a3ed1b342efb1435c97ac74b0 Mon Sep 17 00:00:00 2001 From: Cho Moon Date: Sat, 16 Mar 2024 02:45:18 +0000 Subject: [PATCH 02/32] phase 2 for enhanced clock gater handling 1) arrival computation is now recursive 2) latency adjustments are made from bottom up Signed-off-by: Cho Moon --- src/cts/include/cts/TritonCTS.h | 6 +- src/cts/src/TritonCTS.cpp | 96 ++++++++++++++++++++++--------- src/cts/test/balance_levels.defok | 4 +- 3 files changed, 75 insertions(+), 31 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index 47ee2bc2ac1..f78d7c386c6 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -130,7 +130,8 @@ class TritonCTS // db functions bool masterExists(const std::string& master) const; void populateTritonCTS(); - void writeClockNetsToDb(TreeBuilder* builder, std::set& clkLeafNets); + void writeClockNetsToDb(TreeBuilder* builder, + std::set& clkLeafNets); void writeClockNDRsToDb(const std::set& clkLeafNets); void incrementNumClocks() { ++numberOfClocks_; } void clearNumClocks() { numberOfClocks_ = 0; } @@ -210,6 +211,9 @@ class TritonCTS void printClockNetwork(const Clock& clockNet) const; void balanceMacroRegisterLatencies(); void computeAveSinkArrivals(TreeBuilder* builder); + void computeSinkArrivalRecur(odb::dbITerm* iterm, + float& sumArrivals, + unsigned& numSinks); void adjustLatencies(TreeBuilder* macroBuilder, TreeBuilder* registerBuilder); void computeTopBufferDelay(TreeBuilder* builder); odb::dbInst* insertDelayBuffer(odb::dbInst* driver, diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 6dc4d5e5f70..91b7ded9148 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -1921,7 +1921,10 @@ void TritonCTS::balanceMacroRegisterLatencies() return; } - for (TreeBuilder* registerBuilder : *builders_) { + // Visit builders from bottom up such that latencies are adjusted near bottom + // trees first + for (auto iter = builders_->rbegin(); iter != builders_->rend(); ++iter) { + TreeBuilder* registerBuilder = *iter; if (registerBuilder->getTreeType() == TreeType::RegisterTree) { TreeBuilder* macroBuilder = registerBuilder->getParent(); if (macroBuilder) { @@ -1937,36 +1940,14 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) { Clock clock = builder->getClock(); // compute average input arrival at all sinks - float arrival = 0.0; - float ins_delay = 0.0; + float sumArrivals = 0.0; + unsigned numSinks = 0; clock.forEachSink([&](const ClockInst& sink) { odb::dbITerm* iterm = sink.getDbInputPin(); - odb::dbInst* inst = iterm->getInst(); - sta::Pin* pin = network_->dbToSta(iterm); - // ignore arrival fall (no inverters in current clock tree) - arrival - += openSta_->pinArrival(pin, sta::RiseFall::rise(), sta::MinMax::max()); - // add insertion delay - ins_delay = 0.0; - sta::LibertyCell* libCell = network_->libertyCell(network_->dbToSta(inst)); - odb::dbMTerm* mterm = iterm->getMTerm(); - if (libCell && mterm) { - sta::LibertyPort* libPort - = libCell->findLibertyPort(mterm->getConstName()); - if (libPort) { - sta::RiseFallMinMax insDelays = libPort->clockTreePathDelays(); - if (insDelays.hasValue()) { - ins_delay - = (insDelays.value(sta::RiseFall::rise(), sta::MinMax::max()) - + insDelays.value(sta::RiseFall::fall(), sta::MinMax::max())) - / 2.0; - } - } - } - arrival += ins_delay; + computeSinkArrivalRecur(iterm, sumArrivals, numSinks); }); - arrival = arrival / (float) clock.getNumSinks(); - builder->setAveSinkArrival(arrival); + float aveArrival = sumArrivals / (float) numSinks; + builder->setAveSinkArrival(aveArrival); debugPrint(logger_, CTS, "insertion delay", @@ -1978,6 +1959,65 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) builder->getAveSinkArrival()); } +void TritonCTS::computeSinkArrivalRecur(odb::dbITerm* iterm, + float& sumArrivals, + unsigned& numSinks) +{ + if (iterm) { + odb::dbInst* inst = iterm->getInst(); + if (inst) { + if (isSink(iterm)) { + // either register or macro input pin + sta::Pin* pin = network_->dbToSta(iterm); + if (pin) { + // ignore arrival fall (no inverters in current clock tree) + float arrival = openSta_->pinArrival( + pin, sta::RiseFall::rise(), sta::MinMax::max()); + // add insertion delay + float insDelay = 0.0; + sta::LibertyCell* libCell + = network_->libertyCell(network_->dbToSta(inst)); + odb::dbMTerm* mterm = iterm->getMTerm(); + if (libCell && mterm) { + sta::LibertyPort* libPort + = libCell->findLibertyPort(mterm->getConstName()); + if (libPort) { + sta::RiseFallMinMax insDelays = libPort->clockTreePathDelays(); + if (insDelays.hasValue()) { + insDelay = (insDelays.value(sta::RiseFall::rise(), + sta::MinMax::max()) + + insDelays.value(sta::RiseFall::fall(), + sta::MinMax::max())) + / 2.0; + } + } + } + sumArrivals += (arrival + insDelay); + numSinks++; + } + return; + } else { + // not a sink, but a clock gater + odb::dbITerm* outTerm = inst->getFirstOutput(); + if (outTerm) { + odb::dbNet* outNet = outTerm->getNet(); + if (outNet) { + odb::dbSet iterms = outNet->getITerms(); + odb::dbSet::iterator iter; + for (iter = iterms.begin(); iter != iterms.end(); ++iter) { + odb::dbITerm* inTerm = *iter; + if (inTerm->getIoType() == odb::dbIoType::INPUT) { + computeSinkArrivalRecur(inTerm, sumArrivals, numSinks); + } + } + } + } + } + } + } + return; +} + // Balance latencies between macro tree and register tree // by adding delay buffers to one tree void TritonCTS::adjustLatencies(TreeBuilder* macroBuilder, diff --git a/src/cts/test/balance_levels.defok b/src/cts/test/balance_levels.defok index a231b0515c1..80b129a6a83 100644 --- a/src/cts/test/balance_levels.defok +++ b/src/cts/test/balance_levels.defok @@ -353,11 +353,11 @@ END PINS NETS 39 ; - CELL/clk2 ( clkbuf_0_CELL\/clk2 A ) ( CELL/CKGATE Z ) + USE CLOCK ; - clk ( PIN clk ) ( clkbuf_regs_0_clk A ) ( clkbuf_0_clk A ) + USE CLOCK ; - - clk_regs ( clkbuf_0_clk_regs A ) ( clkbuf_regs_0_clk Z ) + USE CLOCK ; + - clk_regs ( clkbuf_regs_0_clk Z ) ( clkbuf_0_clk_regs A ) + USE CLOCK ; - clknet_0_CELL\/clk2 ( clkbuf_4_15__f_CELL\/clk2 A ) ( clkbuf_4_14__f_CELL\/clk2 A ) ( clkbuf_4_13__f_CELL\/clk2 A ) ( clkbuf_4_12__f_CELL\/clk2 A ) ( clkbuf_4_11__f_CELL\/clk2 A ) ( clkbuf_4_10__f_CELL\/clk2 A ) ( clkbuf_4_9__f_CELL\/clk2 A ) ( clkbuf_4_8__f_CELL\/clk2 A ) ( clkbuf_4_7__f_CELL\/clk2 A ) ( clkbuf_4_6__f_CELL\/clk2 A ) ( clkbuf_4_5__f_CELL\/clk2 A ) ( clkbuf_4_4__f_CELL\/clk2 A ) ( clkbuf_4_3__f_CELL\/clk2 A ) ( clkbuf_4_2__f_CELL\/clk2 A ) ( clkbuf_4_1__f_CELL\/clk2 A ) ( clkbuf_4_0__f_CELL\/clk2 A ) ( clkbuf_0_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_0_clk ( clkbuf_0_clk Z ) ( clkbuf_1_0__f_clk A ) + USE CLOCK ; + - clknet_0_clk ( clkbuf_1_0__f_clk A ) ( clkbuf_0_clk Z ) + USE CLOCK ; - clknet_0_clk_regs ( clkbuf_4_15__f_clk_regs A ) ( clkbuf_4_14__f_clk_regs A ) ( clkbuf_4_13__f_clk_regs A ) ( clkbuf_4_12__f_clk_regs A ) ( clkbuf_4_11__f_clk_regs A ) ( clkbuf_4_10__f_clk_regs A ) ( clkbuf_4_9__f_clk_regs A ) ( clkbuf_4_8__f_clk_regs A ) ( clkbuf_4_7__f_clk_regs A ) ( clkbuf_4_6__f_clk_regs A ) ( clkbuf_4_5__f_clk_regs A ) ( clkbuf_4_4__f_clk_regs A ) ( clkbuf_4_3__f_clk_regs A ) ( clkbuf_4_2__f_clk_regs A ) ( clkbuf_4_1__f_clk_regs A ) ( clkbuf_4_0__f_clk_regs A ) ( clkbuf_0_clk_regs Z ) + USE CLOCK ; From 5ead700b85cf9e3439ca6619a55e37677bd671e6 Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 8 Jul 2024 17:31:32 -0300 Subject: [PATCH 03/32] use paths arrival time for insertion delay Signed-off-by: arthur --- src/cts/include/cts/TritonCTS.h | 3 +- src/cts/src/TritonCTS.cpp | 110 +++++++++++++------------------- 2 files changed, 46 insertions(+), 67 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index 332b74accac..e7882bccdd5 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -216,7 +216,8 @@ class TritonCTS void balanceMacroRegisterLatencies(); float getVertexClkArrival(sta::Vertex* sink_vertex, odb::dbNet* topNet); void computeAveSinkArrivals(TreeBuilder* builder); - void computeSinkArrivalRecur(odb::dbITerm* iterm, + void computeSinkArrivalRecur(odb::dbNet* topClokcNet, + odb::dbITerm* iterm, float& sumArrivals, unsigned& numSinks); void adjustLatencies(TreeBuilder* macroBuilder, TreeBuilder* registerBuilder); diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 8b631765a4e..a931f668ade 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -55,15 +55,15 @@ #include "ord/OpenRoad.hh" #include "rsz/Resizer.hh" #include "sta/Fuzzy.hh" -#include "sta/Liberty.hh" -#include "sta/PatternMatch.hh" -#include "sta/Sdc.hh" -#include "utl/Logger.h" #include "sta/Graph.hh" #include "sta/GraphDelayCalc.hh" +#include "sta/Liberty.hh" #include "sta/PathAnalysisPt.hh" #include "sta/PathEnd.hh" #include "sta/PathExpanded.hh" +#include "sta/PatternMatch.hh" +#include "sta/Sdc.hh" +#include "utl/Logger.h" namespace cts { @@ -1192,11 +1192,6 @@ void TritonCTS::writeClockNetsToDb(TreeBuilder* builder, { Clock& clockNet = builder->getClock(); odb::dbNet* topClockNet = clockNet.getNetObj(); - logger_->report("Top clock Net: {}", topClockNet->getName()); - if(builder->getTopInputNet()) { - logger_->report("Builder Top input Net: {}", builder->getTopInputNet()->getName()); - } - disconnectAllSinksFromNet(topClockNet); @@ -1969,9 +1964,10 @@ void TritonCTS::balanceMacroRegisterLatencies() } } -float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet) { +float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet) +{ sta::VertexPathIterator path_iter(sinVertex, openSta_); - /*float clkPathArrival = 0.0;*/ + float clkPathArrival = 0.0; int paths_accepted = 0; while (path_iter.hasNext()) { sta::PathVertex* path = path_iter.next(); @@ -1983,15 +1979,17 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet) sta::PathExpanded expand(path, openSta_); const sta::Clock* clock = path->clock(openSta_); - if(clock) { - sta::PathRef* start = expand.startPath(); - sta::PathRef* end = expand.endPath(); + if (clock) { + const sta::PathRef* start = expand.startPath(); + + odb::dbNet* path_start_net; if (start->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { // only populate with rising edges continue; } - if (start->dcalcAnalysisPt(openSta_)->delayMinMax() != sta::MinMax::max()) { + if (start->dcalcAnalysisPt(openSta_)->delayMinMax() + != sta::MinMax::max()) { // only populate with max delay continue; } @@ -2000,47 +1998,26 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet) odb::dbBTerm* port; odb::dbModITerm* moditerm; odb::dbModBTerm* modbterm; - sta::Net* sta_net; network_->staToDb(start->pin(openSta_), term, port, moditerm, modbterm); - if(term) { - logger_->report("start_path iterm: {}", term->getName()); + if (term) { + path_start_net = term->getNet(); } - if(port) { - logger_->report("start_path bterm: {}", port->getName()); + if (port) { + path_start_net = port->getNet(); } - - if(moditerm) { - logger_->report("start_path moditerm: {}", moditerm->getName()); + if (path_start_net == topNet) { + clkPathArrival = path->arrival(openSta_); + paths_accepted += 1; } - - if(modbterm) { - logger_->report("start_path modbterm: {}", modbterm->getName()); - } - - sta::Term* term_sta = network_->term(start->pin(openSta_)); - if (term != nullptr) { - sta_net = network_->net(term_sta); - } else { - sta_net = network_->net(start->pin(openSta_)); - } - if(sta_net){ - logger_->report("start_path net: {}", network_->staToDb(sta_net)->getName()); - } - paths_accepted += 1; - // dont add paths that do not share a net at the root - /*if(network_) - logger_->report("start path net: {}", network_->staToDb(startNet)->getName()); - clkPathArrival = path->arrival(openSta_); - if(path->arrival(openSta_) != end->arrival(openSta_)) { - logger_->report("Difference"); - }*/ } } - logger_->report("Paths accepted: {}", paths_accepted); - /*if(paths_accepted > 1 || paths_accepted == 0) { - logger_->report("Paths accepted: {}", paths_accepted); - }*/ - return 0.0; + if (paths_accepted > 1 || paths_accepted == 0) { + logger_->error(CTS, + 1, + "Number of clock paths is not 1. Number of clock paths: {}", + paths_accepted); + } + return clkPathArrival; } void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) @@ -2050,12 +2027,16 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) openSta_->ensureClkNetwork(); openSta_->ensureClkArrivals(); Clock clock = builder->getClock(); + odb::dbNet* topClockNet = clock.getNetObj(); + if (builder->getTreeType() == TreeType::RegisterTree) { + topClockNet = builder->getTopInputNet(); + } // compute average input arrival at all sinks float sumArrivals = 0.0; unsigned numSinks = 0; clock.forEachSink([&](const ClockInst& sink) { odb::dbITerm* iterm = sink.getDbInputPin(); - computeSinkArrivalRecur(iterm, sumArrivals, numSinks); + computeSinkArrivalRecur(topClockNet, iterm, sumArrivals, numSinks); }); float aveArrival = sumArrivals / (float) numSinks; builder->setAveSinkArrival(aveArrival); @@ -2070,7 +2051,8 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) builder->getAveSinkArrival()); } -void TritonCTS::computeSinkArrivalRecur(odb::dbITerm* iterm, +void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, + odb::dbITerm* iterm, float& sumArrivals, unsigned& numSinks) { @@ -2083,20 +2065,14 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbITerm* iterm, if (pin) { sta::Graph* graph = openSta_->graph(); sta::Vertex* drvr_vertex = graph->pinDrvrVertex(pin); - sta::Vertex* load_vertex = graph->pinLoadVertex(pin); - logger_->report("sink iterm name: {}", iterm->getName()); - if(drvr_vertex != load_vertex) { - logger_->report("diferentes vertices"); - getVertexClkArrival(drvr_vertex, nullptr); - getVertexClkArrival(load_vertex, nullptr); - } else { - logger_->report("iguais vertices"); - getVertexClkArrival(drvr_vertex, nullptr); - } - + float arrival = getVertexClkArrival(drvr_vertex, topClokcNet); // ignore arrival fall (no inverters in current clock tree) - float arrival = openSta_->pinArrival( + float arrival_pin = openSta_->pinArrival( pin, sta::RiseFall::rise(), sta::MinMax::max()); + if (arrival != arrival_pin) { + logger_->report("returned arrival: {}", arrival); + logger_->report("pin arrival: {}", arrival_pin); + } // add insertion delay float insDelay = 0.0; sta::LibertyCell* libCell @@ -2106,7 +2082,8 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbITerm* iterm, sta::LibertyPort* libPort = libCell->findLibertyPort(mterm->getConstName()); if (libPort) { - sta::RiseFallMinMax insDelays = libPort->clockTreePathDelays(); + const sta::RiseFallMinMax insDelays + = libPort->clockTreePathDelays(); if (insDelays.hasValue()) { insDelay = (insDelays.value(sta::RiseFall::rise(), sta::MinMax::max()) @@ -2131,7 +2108,8 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbITerm* iterm, for (iter = iterms.begin(); iter != iterms.end(); ++iter) { odb::dbITerm* inTerm = *iter; if (inTerm->getIoType() == odb::dbIoType::INPUT) { - computeSinkArrivalRecur(inTerm, sumArrivals, numSinks); + computeSinkArrivalRecur( + topClokcNet, inTerm, sumArrivals, numSinks); } } } From ff2804f8d990bf49a0a9d0be6f6e12276af90e7f Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 8 Jul 2024 17:32:21 -0300 Subject: [PATCH 04/32] update ok files Signed-off-by: arthur --- src/cts/test/balance_levels.defok | 207 ++++++++++++++---------------- src/cts/test/balance_levels.ok | 10 +- 2 files changed, 98 insertions(+), 119 deletions(-) diff --git a/src/cts/test/balance_levels.defok b/src/cts/test/balance_levels.defok index 6e859e33096..27fc13e0e6d 100644 --- a/src/cts/test/balance_levels.defok +++ b/src/cts/test/balance_levels.defok @@ -4,7 +4,7 @@ BUSBITCHARS "[]" ; DESIGN multi_sink ; UNITS DISTANCE MICRONS 2000 ; DIEAREA ( 0 0 ) ( 200000 200000 ) ; -COMPONENTS 338 ; +COMPONENTS 368 ; - CELL/CKGATE BUF_X1 + PLACED ( 100000 100000 ) N ; - clkbuf_0_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 103228 140117 ) N ; - clkbuf_0_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 100250 101225 ) N ; @@ -43,6 +43,36 @@ COMPONENTS 338 ; - clkbuf_4_9__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 124256 ) N ; - clkbuf_4_9__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 35368 ) N ; - clkbuf_regs_0_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 99481 48451 ) N ; + - clkload0 INV_X2 + SOURCE TIMING + PLACED ( 37181 26644 ) N ; + - clkload1 INV_X4 + SOURCE TIMING + PLACED ( 28978 35266 ) N ; + - clkload10 INV_X2 + SOURCE TIMING + PLACED ( 176988 31963 ) N ; + - clkload11 INV_X2 + SOURCE TIMING + PLACED ( 135454 59367 ) N ; + - clkload12 INV_X2 + SOURCE TIMING + PLACED ( 137599 71599 ) N ; + - clkload13 INV_X4 + SOURCE TIMING + PLACED ( 175738 59340 ) N ; + - clkload14 INV_X2 + SOURCE TIMING + PLACED ( 173942 71102 ) N ; + - clkload15 INV_X2 + SOURCE TIMING + PLACED ( 35318 119627 ) N ; + - clkload16 INV_X4 + SOURCE TIMING + PLACED ( 31476 129670 ) N ; + - clkload17 CLKBUF_X3 + SOURCE TIMING + PLACED ( 68717 119605 ) N ; + - clkload18 INV_X2 + SOURCE TIMING + PLACED ( 71061 131581 ) N ; + - clkload19 INV_X2 + SOURCE TIMING + PLACED ( 31714 150934 ) N ; + - clkload2 INV_X2 + SOURCE TIMING + PLACED ( 69122 41782 ) N ; + - clkload20 INV_X1 + SOURCE TIMING + PLACED ( 33478 164353 ) N ; + - clkload21 INV_X2 + SOURCE TIMING + PLACED ( 70729 156126 ) N ; + - clkload22 CLKBUF_X3 + SOURCE TIMING + PLACED ( 64318 165027 ) N ; + - clkload23 CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 115396 ) N ; + - clkload24 INV_X2 + SOURCE TIMING + PLACED ( 135237 124256 ) N ; + - clkload25 INV_X4 + SOURCE TIMING + PLACED ( 169474 113337 ) N ; + - clkload26 INV_X2 + SOURCE TIMING + PLACED ( 176988 120851 ) N ; + - clkload27 INV_X2 + SOURCE TIMING + PLACED ( 136180 148710 ) N ; + - clkload28 INV_X4 + SOURCE TIMING + PLACED ( 175261 148092 ) N ; + - clkload29 INV_X2 + SOURCE TIMING + PLACED ( 173171 159411 ) N ; + - clkload3 INV_X4 + SOURCE TIMING + PLACED ( 30369 61835 ) N ; + - clkload4 INV_X1 + SOURCE TIMING + PLACED ( 31247 76899 ) N ; + - clkload5 INV_X4 + SOURCE TIMING + PLACED ( 68700 66662 ) N ; + - clkload6 INV_X2 + SOURCE TIMING + PLACED ( 64650 75806 ) N ; + - clkload7 INV_X1 + SOURCE TIMING + PLACED ( 141948 26508 ) N ; + - clkload8 INV_X4 + SOURCE TIMING + PLACED ( 135237 35368 ) N ; + - clkload9 INV_X4 + SOURCE TIMING + PLACED ( 169474 24449 ) N ; - ff0 DFF_X1 + PLACED ( 5555 5555 ) N ; - ff1 DFF_X1 + PLACED ( 16666 5555 ) N ; - ff10 DFF_X1 + PLACED ( 116665 5555 ) N ; @@ -362,120 +392,69 @@ NETS 39 ; ( clkbuf_4_8__f_clk_regs A ) ( clkbuf_4_7__f_clk_regs A ) ( clkbuf_4_6__f_clk_regs A ) ( clkbuf_4_5__f_clk_regs A ) ( clkbuf_4_4__f_clk_regs A ) ( clkbuf_4_3__f_clk_regs A ) ( clkbuf_4_2__f_clk_regs A ) ( clkbuf_4_1__f_clk_regs A ) ( clkbuf_4_0__f_clk_regs A ) ( clkbuf_0_clk_regs Z ) + USE CLOCK ; - clknet_1_0__leaf_clk ( CELL/CKGATE A ) ( clkbuf_1_0__f_clk Z ) + USE CLOCK ; - - clknet_4_0__leaf_CELL\/clk2 ( ff162 CK ) ( ff163 CK ) ( ff164 CK ) ( ff165 CK ) ( ff180 CK ) ( ff181 CK ) ( ff182 CK ) - ( ff183 CK ) ( ff184 CK ) ( clkbuf_4_0__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_0__leaf_clk_regs ( ff0 CK ) ( ff1 CK ) ( ff2 CK ) ( ff3 CK ) ( ff18 CK ) ( ff19 CK ) ( ff20 CK ) - ( ff21 CK ) ( ff39 CK ) ( ff40 CK ) ( clkbuf_4_0__f_clk_regs Z ) + USE CLOCK ; - - clknet_4_10__leaf_CELL\/clk2 ( ff158 CK ) ( ff159 CK ) ( ff160 CK ) ( ff176 CK ) ( ff177 CK ) ( ff178 CK ) ( ff194 CK ) - ( clkbuf_4_10__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_10__leaf_clk_regs ( ff14 CK ) ( ff15 CK ) ( ff16 CK ) ( ff32 CK ) ( ff33 CK ) ( ff34 CK ) ( ff50 CK ) - ( clkbuf_4_10__f_clk_regs Z ) + USE CLOCK ; - - clknet_4_11__leaf_CELL\/clk2 ( ff161 CK ) ( ff179 CK ) ( ff195 CK ) ( ff196 CK ) ( ff197 CK ) ( ff212 CK ) ( ff213 CK ) - ( ff214 CK ) ( ff215 CK ) ( clkbuf_4_11__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_11__leaf_clk_regs ( ff17 CK ) ( ff35 CK ) ( ff51 CK ) ( ff52 CK ) ( ff53 CK ) ( ff68 CK ) ( ff69 CK ) - ( ff70 CK ) ( ff71 CK ) ( clkbuf_4_11__f_clk_regs Z ) + USE CLOCK ; - - clknet_4_12__leaf_CELL\/clk2 ( ff225 CK ) ( ff226 CK ) ( ff227 CK ) ( ff228 CK ) ( ff229 CK ) ( ff243 CK ) ( ff244 CK ) - ( ff245 CK ) ( ff246 CK ) ( ff247 CK ) ( clkbuf_4_12__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_12__leaf_clk_regs ( ff81 CK ) ( ff82 CK ) ( ff83 CK ) ( ff84 CK ) ( ff85 CK ) ( ff99 CK ) ( ff100 CK ) - ( ff101 CK ) ( ff103 CK ) ( clkbuf_4_12__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_0__leaf_CELL\/clk2 ( clkload15 A ) ( ff162 CK ) ( ff163 CK ) ( ff164 CK ) ( ff165 CK ) ( ff180 CK ) ( ff181 CK ) + ( ff182 CK ) ( ff183 CK ) ( ff184 CK ) ( clkbuf_4_0__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_0__leaf_clk_regs ( clkload0 A ) ( ff0 CK ) ( ff1 CK ) ( ff2 CK ) ( ff3 CK ) ( ff18 CK ) ( ff19 CK ) + ( ff20 CK ) ( ff21 CK ) ( ff39 CK ) ( ff40 CK ) ( clkbuf_4_0__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_10__leaf_CELL\/clk2 ( clkload25 A ) ( ff158 CK ) ( ff159 CK ) ( ff160 CK ) ( ff176 CK ) ( ff177 CK ) ( ff178 CK ) + ( ff194 CK ) ( clkbuf_4_10__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_10__leaf_clk_regs ( clkload9 A ) ( ff14 CK ) ( ff15 CK ) ( ff16 CK ) ( ff32 CK ) ( ff33 CK ) ( ff34 CK ) + ( ff50 CK ) ( clkbuf_4_10__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_11__leaf_CELL\/clk2 ( clkload26 A ) ( ff161 CK ) ( ff179 CK ) ( ff195 CK ) ( ff196 CK ) ( ff197 CK ) ( ff212 CK ) + ( ff213 CK ) ( ff214 CK ) ( ff215 CK ) ( clkbuf_4_11__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_11__leaf_clk_regs ( clkload10 A ) ( ff17 CK ) ( ff35 CK ) ( ff51 CK ) ( ff52 CK ) ( ff53 CK ) ( ff68 CK ) + ( ff69 CK ) ( ff70 CK ) ( ff71 CK ) ( clkbuf_4_11__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_12__leaf_CELL\/clk2 ( clkload27 A ) ( ff225 CK ) ( ff226 CK ) ( ff227 CK ) ( ff228 CK ) ( ff229 CK ) ( ff243 CK ) + ( ff244 CK ) ( ff245 CK ) ( ff246 CK ) ( ff247 CK ) ( clkbuf_4_12__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_12__leaf_clk_regs ( clkload11 A ) ( ff81 CK ) ( ff82 CK ) ( ff83 CK ) ( ff84 CK ) ( ff85 CK ) ( ff99 CK ) + ( ff100 CK ) ( ff101 CK ) ( ff103 CK ) ( clkbuf_4_12__f_clk_regs Z ) + USE CLOCK ; - clknet_4_13__leaf_CELL\/clk2 ( ff261 CK ) ( ff262 CK ) ( ff263 CK ) ( ff264 CK ) ( ff265 CK ) ( ff279 CK ) ( ff280 CK ) ( ff281 CK ) ( ff282 CK ) ( ff283 CK ) ( ff297 CK ) ( ff298 CK ) ( ff299 CK ) ( clkbuf_4_13__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_13__leaf_clk ( clkbuf_level_0_1_1439_clk A ) ( clkbuf_4_13__f_clk Z ) + USE CLOCK ; - - clknet_4_14__leaf_CELL\/clk2 ( ff230 CK ) ( ff231 CK ) ( ff232 CK ) ( ff233 CK ) ( ff248 CK ) ( ff250 CK ) ( ff251 CK ) - ( clkbuf_4_14__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_14__leaf_clk ( clkbuf_level_0_1_1542_clk A ) ( clkbuf_4_14__f_clk Z ) + USE CLOCK ; - - clknet_4_15__leaf_CELL\/clk2 ( ff249 CK ) ( ff266 CK ) ( ff267 CK ) ( ff268 CK ) ( ff269 CK ) ( ff284 CK ) ( ff285 CK ) - ( ff286 CK ) ( ff287 CK ) ( clkbuf_4_15__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_15__leaf_clk ( clkbuf_level_0_1_1645_clk A ) ( clkbuf_4_15__f_clk Z ) + USE CLOCK ; - - clknet_4_1__leaf_CELL\/clk2 ( ff198 CK ) ( ff199 CK ) ( ff200 CK ) ( ff201 CK ) ( ff202 CK ) ( ff216 CK ) ( clkbuf_4_1__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_1__leaf_clk ( clkbuf_level_0_1_23_clk A ) ( clkbuf_4_1__f_clk Z ) + USE CLOCK ; - - clknet_4_2__leaf_CELL\/clk2 ( ff150 CK ) ( ff151 CK ) ( ff152 CK ) ( ff166 CK ) ( ff167 CK ) ( ff168 CK ) ( ff169 CK ) - ( ff170 CK ) ( ff185 CK ) ( ff186 CK ) ( ff187 CK ) ( ff188 CK ) ( clkbuf_4_2__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_2__leaf_clk ( clkbuf_level_0_1_36_clk A ) ( clkbuf_4_2__f_clk Z ) + USE CLOCK ; - - clknet_4_3__leaf_CELL\/clk2 ( ff203 CK ) ( ff204 CK ) ( ff205 CK ) ( ff206 CK ) ( ff220 CK ) ( ff221 CK ) ( ff222 CK ) - ( ff223 CK ) ( ff224 CK ) ( clkbuf_4_3__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_3__leaf_clk ( clkbuf_level_0_1_49_clk A ) ( clkbuf_4_3__f_clk Z ) + USE CLOCK ; - - clknet_4_4__leaf_CELL\/clk2 ( ff217 CK ) ( ff218 CK ) ( ff219 CK ) ( ff234 CK ) ( ff235 CK ) ( ff236 CK ) ( ff237 CK ) - ( ff254 CK ) ( clkbuf_4_4__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_4__leaf_clk ( clkbuf_level_0_1_512_clk A ) ( clkbuf_4_4__f_clk Z ) + USE CLOCK ; - - clknet_4_5__leaf_CELL\/clk2 ( ff252 CK ) ( ff253 CK ) ( ff255 CK ) ( ff270 CK ) ( ff271 CK ) ( ff272 CK ) ( ff273 CK ) - ( ff288 CK ) ( ff289 CK ) ( ff290 CK ) ( ff291 CK ) ( clkbuf_4_5__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_5__leaf_clk ( clkbuf_level_0_1_615_clk A ) ( clkbuf_4_5__f_clk Z ) + USE CLOCK ; - - clknet_4_6__leaf_CELL\/clk2 ( ff238 CK ) ( ff239 CK ) ( ff240 CK ) ( ff241 CK ) ( ff242 CK ) ( ff257 CK ) ( ff259 CK ) - ( ff260 CK ) ( clkbuf_4_6__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_6__leaf_clk ( clkbuf_level_0_1_718_clk A ) ( clkbuf_4_6__f_clk Z ) + USE CLOCK ; - - clknet_4_7__leaf_CELL\/clk2 ( ff256 CK ) ( ff258 CK ) ( ff274 CK ) ( ff275 CK ) ( ff276 CK ) ( ff277 CK ) ( ff278 CK ) - ( ff292 CK ) ( ff293 CK ) ( ff294 CK ) ( ff295 CK ) ( ff296 CK ) ( clkbuf_4_7__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_7__leaf_clk ( CELL/CKGATE A ) ( clkbuf_level_0_1_821_clk A ) ( clkbuf_4_7__f_clk Z ) + USE CLOCK ; - - clknet_4_8__leaf_CELL\/clk2 ( ff153 CK ) ( ff154 CK ) ( ff155 CK ) ( ff156 CK ) ( ff157 CK ) ( ff171 CK ) ( ff172 CK ) - ( ff173 CK ) ( ff174 CK ) ( ff175 CK ) ( ff191 CK ) ( ff193 CK ) ( clkbuf_4_8__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_8__leaf_clk ( clkbuf_level_0_1_924_clk A ) ( clkbuf_4_8__f_clk Z ) + USE CLOCK ; - - clknet_4_9__leaf_CELL\/clk2 ( ff189 CK ) ( ff190 CK ) ( ff192 CK ) ( ff207 CK ) ( ff208 CK ) ( ff209 CK ) ( ff210 CK ) - ( ff211 CK ) ( clkbuf_4_9__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_9__leaf_clk ( clkbuf_level_0_1_1027_clk A ) ( clkbuf_4_9__f_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1027_clk ( clkbuf_level_1_1_1028_clk A ) ( clkbuf_level_0_1_1027_clk Z ) + USE CLOCK ; - - clknet_level_0_1_10_clk ( clkbuf_level_1_1_11_clk A ) ( clkbuf_level_0_1_10_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1130_clk ( clkbuf_level_1_1_1131_clk A ) ( clkbuf_level_0_1_1130_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1233_clk ( clkbuf_level_1_1_1234_clk A ) ( clkbuf_level_0_1_1233_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1336_clk ( clkbuf_level_1_1_1337_clk A ) ( clkbuf_level_0_1_1336_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1439_clk ( clkbuf_level_1_1_1440_clk A ) ( clkbuf_level_0_1_1439_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1542_clk ( clkbuf_level_1_1_1543_clk A ) ( clkbuf_level_0_1_1542_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1645_clk ( clkbuf_level_1_1_1646_clk A ) ( clkbuf_level_0_1_1645_clk Z ) + USE CLOCK ; - - clknet_level_0_1_23_clk ( clkbuf_level_1_1_24_clk A ) ( clkbuf_level_0_1_23_clk Z ) + USE CLOCK ; - - clknet_level_0_1_36_clk ( clkbuf_level_1_1_37_clk A ) ( clkbuf_level_0_1_36_clk Z ) + USE CLOCK ; - - clknet_level_0_1_49_clk ( clkbuf_level_1_1_410_clk A ) ( clkbuf_level_0_1_49_clk Z ) + USE CLOCK ; - - clknet_level_0_1_512_clk ( clkbuf_level_1_1_513_clk A ) ( clkbuf_level_0_1_512_clk Z ) + USE CLOCK ; - - clknet_level_0_1_615_clk ( clkbuf_level_1_1_616_clk A ) ( clkbuf_level_0_1_615_clk Z ) + USE CLOCK ; - - clknet_level_0_1_718_clk ( clkbuf_level_1_1_719_clk A ) ( clkbuf_level_0_1_718_clk Z ) + USE CLOCK ; - - clknet_level_0_1_821_clk ( clkbuf_level_1_1_822_clk A ) ( clkbuf_level_0_1_821_clk Z ) + USE CLOCK ; - - clknet_level_0_1_924_clk ( clkbuf_level_1_1_925_clk A ) ( clkbuf_level_0_1_924_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1028_clk ( clkbuf_level_2_1_1029_clk A ) ( clkbuf_level_1_1_1028_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1131_clk ( clkbuf_level_2_1_1132_clk A ) ( clkbuf_level_1_1_1131_clk Z ) + USE CLOCK ; - - clknet_level_1_1_11_clk ( clkbuf_level_2_1_12_clk A ) ( clkbuf_level_1_1_11_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1234_clk ( clkbuf_level_2_1_1235_clk A ) ( clkbuf_level_1_1_1234_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1337_clk ( clkbuf_level_2_1_1338_clk A ) ( clkbuf_level_1_1_1337_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1440_clk ( clkbuf_level_2_1_1441_clk A ) ( clkbuf_level_1_1_1440_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1543_clk ( clkbuf_level_2_1_1544_clk A ) ( clkbuf_level_1_1_1543_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1646_clk ( clkbuf_level_2_1_1647_clk A ) ( clkbuf_level_1_1_1646_clk Z ) + USE CLOCK ; - - clknet_level_1_1_24_clk ( clkbuf_level_2_1_25_clk A ) ( clkbuf_level_1_1_24_clk Z ) + USE CLOCK ; - - clknet_level_1_1_37_clk ( clkbuf_level_2_1_38_clk A ) ( clkbuf_level_1_1_37_clk Z ) + USE CLOCK ; - - clknet_level_1_1_410_clk ( clkbuf_level_2_1_411_clk A ) ( clkbuf_level_1_1_410_clk Z ) + USE CLOCK ; - - clknet_level_1_1_513_clk ( clkbuf_level_2_1_514_clk A ) ( clkbuf_level_1_1_513_clk Z ) + USE CLOCK ; - - clknet_level_1_1_616_clk ( clkbuf_level_2_1_617_clk A ) ( clkbuf_level_1_1_616_clk Z ) + USE CLOCK ; - - clknet_level_1_1_719_clk ( clkbuf_level_2_1_720_clk A ) ( clkbuf_level_1_1_719_clk Z ) + USE CLOCK ; - - clknet_level_1_1_822_clk ( clkbuf_level_2_1_823_clk A ) ( clkbuf_level_1_1_822_clk Z ) + USE CLOCK ; - - clknet_level_1_1_925_clk ( clkbuf_level_2_1_926_clk A ) ( clkbuf_level_1_1_925_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1029_clk ( ff45 CK ) ( ff46 CK ) ( ff48 CK ) ( ff63 CK ) ( ff64 CK ) ( ff65 CK ) ( ff66 CK ) - ( ff67 CK ) ( clkbuf_level_2_1_1029_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1132_clk ( ff14 CK ) ( ff15 CK ) ( ff16 CK ) ( ff32 CK ) ( ff33 CK ) ( ff34 CK ) ( ff50 CK ) - ( clkbuf_level_2_1_1132_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1235_clk ( ff17 CK ) ( ff35 CK ) ( ff51 CK ) ( ff52 CK ) ( ff53 CK ) ( ff68 CK ) ( ff69 CK ) - ( ff70 CK ) ( ff71 CK ) ( clkbuf_level_2_1_1235_clk Z ) + USE CLOCK ; - - clknet_level_2_1_12_clk ( ff0 CK ) ( ff2 CK ) ( ff3 CK ) ( ff20 CK ) ( ff21 CK ) ( ff39 CK ) ( ff57 CK ) - ( clkbuf_level_2_1_12_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1338_clk ( ff81 CK ) ( ff82 CK ) ( ff83 CK ) ( ff84 CK ) ( ff85 CK ) ( ff99 CK ) ( ff100 CK ) - ( ff101 CK ) ( ff103 CK ) ( clkbuf_level_2_1_1338_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1441_clk ( ff102 CK ) ( ff117 CK ) ( ff118 CK ) ( ff119 CK ) ( ff120 CK ) ( ff121 CK ) ( ff135 CK ) - ( ff136 CK ) ( ff137 CK ) ( ff138 CK ) ( ff139 CK ) ( clkbuf_level_2_1_1441_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1544_clk ( ff86 CK ) ( ff87 CK ) ( ff88 CK ) ( ff89 CK ) ( ff104 CK ) ( ff106 CK ) ( ff107 CK ) - ( clkbuf_level_2_1_1544_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1647_clk ( ff105 CK ) ( ff122 CK ) ( ff123 CK ) ( ff124 CK ) ( ff125 CK ) ( ff140 CK ) ( ff141 CK ) - ( ff142 CK ) ( ff143 CK ) ( clkbuf_level_2_1_1647_clk Z ) + USE CLOCK ; - - clknet_level_2_1_25_clk ( ff1 CK ) ( ff18 CK ) ( ff19 CK ) ( ff36 CK ) ( ff37 CK ) ( ff38 CK ) ( ff54 CK ) - ( ff55 CK ) ( ff56 CK ) ( clkbuf_level_2_1_25_clk Z ) + USE CLOCK ; - - clknet_level_2_1_38_clk ( ff4 CK ) ( ff5 CK ) ( ff6 CK ) ( ff7 CK ) ( ff8 CK ) ( ff22 CK ) ( ff23 CK ) - ( ff24 CK ) ( ff25 CK ) ( ff26 CK ) ( ff40 CK ) ( ff42 CK ) ( clkbuf_level_2_1_38_clk Z ) + USE CLOCK ; - - clknet_level_2_1_411_clk ( ff41 CK ) ( ff43 CK ) ( ff44 CK ) ( ff58 CK ) ( ff59 CK ) ( ff60 CK ) ( ff61 CK ) - ( ff62 CK ) ( clkbuf_level_2_1_411_clk Z ) + USE CLOCK ; - - clknet_level_2_1_514_clk ( ff72 CK ) ( ff73 CK ) ( ff74 CK ) ( ff75 CK ) ( ff90 CK ) ( ff91 CK ) ( ff92 CK ) - ( ff93 CK ) ( clkbuf_level_2_1_514_clk Z ) + USE CLOCK ; - - clknet_level_2_1_617_clk ( ff108 CK ) ( ff109 CK ) ( ff110 CK ) ( ff111 CK ) ( ff126 CK ) ( ff127 CK ) ( ff128 CK ) - ( ff129 CK ) ( ff144 CK ) ( ff145 CK ) ( ff146 CK ) ( ff147 CK ) ( clkbuf_level_2_1_617_clk Z ) + USE CLOCK ; - - clknet_level_2_1_720_clk ( ff76 CK ) ( ff77 CK ) ( ff78 CK ) ( ff79 CK ) ( ff80 CK ) ( ff94 CK ) ( ff95 CK ) - ( ff96 CK ) ( ff97 CK ) ( ff98 CK ) ( clkbuf_level_2_1_720_clk Z ) + USE CLOCK ; - - clknet_level_2_1_823_clk ( ff112 CK ) ( ff113 CK ) ( ff114 CK ) ( ff115 CK ) ( ff116 CK ) ( ff130 CK ) ( ff131 CK ) - ( ff132 CK ) ( ff133 CK ) ( ff134 CK ) ( ff148 CK ) ( ff149 CK ) ( clkbuf_level_2_1_823_clk Z ) + USE CLOCK ; - - clknet_level_2_1_926_clk ( ff9 CK ) ( ff10 CK ) ( ff11 CK ) ( ff12 CK ) ( ff13 CK ) ( ff27 CK ) ( ff28 CK ) - ( ff29 CK ) ( ff30 CK ) ( ff31 CK ) ( ff47 CK ) ( ff49 CK ) ( clkbuf_level_2_1_926_clk Z ) + USE CLOCK ; + - clknet_4_13__leaf_clk_regs ( clkload12 A ) ( ff102 CK ) ( ff117 CK ) ( ff118 CK ) ( ff119 CK ) ( ff120 CK ) ( ff121 CK ) + ( ff135 CK ) ( ff136 CK ) ( ff137 CK ) ( ff138 CK ) ( ff139 CK ) ( clkbuf_4_13__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_14__leaf_CELL\/clk2 ( clkload28 A ) ( ff230 CK ) ( ff231 CK ) ( ff232 CK ) ( ff233 CK ) ( ff248 CK ) ( ff250 CK ) + ( ff251 CK ) ( clkbuf_4_14__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_14__leaf_clk_regs ( clkload13 A ) ( ff86 CK ) ( ff87 CK ) ( ff88 CK ) ( ff89 CK ) ( ff104 CK ) ( ff106 CK ) + ( ff107 CK ) ( clkbuf_4_14__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_15__leaf_CELL\/clk2 ( clkload29 A ) ( ff249 CK ) ( ff266 CK ) ( ff267 CK ) ( ff268 CK ) ( ff269 CK ) ( ff284 CK ) + ( ff285 CK ) ( ff286 CK ) ( ff287 CK ) ( clkbuf_4_15__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_15__leaf_clk_regs ( clkload14 A ) ( ff105 CK ) ( ff122 CK ) ( ff123 CK ) ( ff124 CK ) ( ff125 CK ) ( ff140 CK ) + ( ff141 CK ) ( ff142 CK ) ( ff143 CK ) ( clkbuf_4_15__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_1__leaf_CELL\/clk2 ( clkload16 A ) ( ff198 CK ) ( ff199 CK ) ( ff200 CK ) ( ff201 CK ) ( ff202 CK ) ( ff216 CK ) + ( clkbuf_4_1__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_1__leaf_clk_regs ( clkload1 A ) ( ff36 CK ) ( ff37 CK ) ( ff38 CK ) ( ff54 CK ) ( ff55 CK ) ( ff56 CK ) + ( ff57 CK ) ( clkbuf_4_1__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_2__leaf_CELL\/clk2 ( clkload17 A ) ( ff150 CK ) ( ff151 CK ) ( ff152 CK ) ( ff166 CK ) ( ff167 CK ) ( ff168 CK ) + ( ff169 CK ) ( ff170 CK ) ( ff185 CK ) ( ff186 CK ) ( ff187 CK ) ( ff188 CK ) ( clkbuf_4_2__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_2__leaf_clk_regs ( ff4 CK ) ( ff5 CK ) ( ff6 CK ) ( ff7 CK ) ( ff8 CK ) ( ff22 CK ) ( ff23 CK ) + ( ff24 CK ) ( ff25 CK ) ( ff26 CK ) ( ff41 CK ) ( ff42 CK ) ( ff43 CK ) ( ff44 CK ) ( clkbuf_4_2__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_3__leaf_CELL\/clk2 ( clkload18 A ) ( ff203 CK ) ( ff204 CK ) ( ff205 CK ) ( ff206 CK ) ( ff220 CK ) ( ff221 CK ) + ( ff222 CK ) ( ff223 CK ) ( ff224 CK ) ( clkbuf_4_3__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_3__leaf_clk_regs ( clkload2 A ) ( ff58 CK ) ( ff59 CK ) ( ff60 CK ) ( ff61 CK ) ( ff62 CK ) ( ff76 CK ) + ( ff77 CK ) ( ff78 CK ) ( ff79 CK ) ( ff80 CK ) ( clkbuf_4_3__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_4__leaf_CELL\/clk2 ( clkload19 A ) ( ff217 CK ) ( ff218 CK ) ( ff219 CK ) ( ff234 CK ) ( ff235 CK ) ( ff236 CK ) + ( ff237 CK ) ( ff254 CK ) ( clkbuf_4_4__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_4__leaf_clk_regs ( clkload3 A ) ( ff72 CK ) ( ff73 CK ) ( ff74 CK ) ( ff75 CK ) ( ff90 CK ) ( ff91 CK ) + ( ff92 CK ) ( ff93 CK ) ( clkbuf_4_4__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_5__leaf_CELL\/clk2 ( clkload20 A ) ( ff252 CK ) ( ff253 CK ) ( ff255 CK ) ( ff270 CK ) ( ff271 CK ) ( ff272 CK ) + ( ff273 CK ) ( ff288 CK ) ( ff289 CK ) ( ff290 CK ) ( ff291 CK ) ( clkbuf_4_5__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_5__leaf_clk_regs ( clkload4 A ) ( ff108 CK ) ( ff109 CK ) ( ff110 CK ) ( ff111 CK ) ( ff126 CK ) ( ff127 CK ) + ( ff128 CK ) ( ff129 CK ) ( ff144 CK ) ( ff145 CK ) ( ff146 CK ) ( ff147 CK ) ( clkbuf_4_5__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_6__leaf_CELL\/clk2 ( clkload21 A ) ( ff238 CK ) ( ff239 CK ) ( ff240 CK ) ( ff241 CK ) ( ff242 CK ) ( ff257 CK ) + ( ff259 CK ) ( ff260 CK ) ( clkbuf_4_6__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_6__leaf_clk_regs ( clkload5 A ) ( ff94 CK ) ( ff95 CK ) ( ff96 CK ) ( ff97 CK ) ( ff98 CK ) ( ff113 CK ) + ( ff114 CK ) ( clkbuf_4_6__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_7__leaf_CELL\/clk2 ( clkload22 A ) ( ff256 CK ) ( ff258 CK ) ( ff274 CK ) ( ff275 CK ) ( ff276 CK ) ( ff277 CK ) + ( ff278 CK ) ( ff292 CK ) ( ff293 CK ) ( ff294 CK ) ( ff295 CK ) ( ff296 CK ) ( clkbuf_4_7__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_7__leaf_clk_regs ( clkload6 A ) ( ff112 CK ) ( ff115 CK ) ( ff116 CK ) ( ff130 CK ) ( ff131 CK ) ( ff132 CK ) + ( ff133 CK ) ( ff134 CK ) ( ff148 CK ) ( ff149 CK ) ( clkbuf_4_7__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_8__leaf_CELL\/clk2 ( clkload23 A ) ( ff153 CK ) ( ff154 CK ) ( ff155 CK ) ( ff156 CK ) ( ff157 CK ) ( ff171 CK ) + ( ff172 CK ) ( ff173 CK ) ( ff174 CK ) ( ff175 CK ) ( ff191 CK ) ( ff193 CK ) ( clkbuf_4_8__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_8__leaf_clk_regs ( clkload7 A ) ( ff9 CK ) ( ff10 CK ) ( ff11 CK ) ( ff12 CK ) ( ff13 CK ) ( ff27 CK ) + ( ff28 CK ) ( ff29 CK ) ( ff30 CK ) ( ff31 CK ) ( ff47 CK ) ( ff49 CK ) ( clkbuf_4_8__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_9__leaf_CELL\/clk2 ( clkload24 A ) ( ff189 CK ) ( ff190 CK ) ( ff192 CK ) ( ff207 CK ) ( ff208 CK ) ( ff209 CK ) + ( ff210 CK ) ( ff211 CK ) ( clkbuf_4_9__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_9__leaf_clk_regs ( clkload8 A ) ( ff45 CK ) ( ff46 CK ) ( ff48 CK ) ( ff63 CK ) ( ff64 CK ) ( ff65 CK ) + ( ff66 CK ) ( ff67 CK ) ( clkbuf_4_9__f_clk_regs Z ) + USE CLOCK ; END NETS END DESIGN diff --git a/src/cts/test/balance_levels.ok b/src/cts/test/balance_levels.ok index 00f1f0a771c..9ee00fc2d59 100644 --- a/src/cts/test/balance_levels.ok +++ b/src/cts/test/balance_levels.ok @@ -97,12 +97,11 @@ [INFO CTS-0034] Segment length (rounded): 1. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. [INFO CTS-0035] Number of sinks covered: 150. -[INFO CTS-0018] Created 3 clock buffers. +[INFO CTS-0018] Created 2 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. [INFO CTS-0013] Maximum number of buffers in the clock path: 2. -[INFO CTS-0014] 1 clock nets were removed/fixed. [INFO CTS-0015] Created 2 clock nets. -[INFO CTS-0016] Fanout distribution for the current clock = 0:1, 1:1.. +[INFO CTS-0016] Fanout distribution for the current clock = 1:1.. [INFO CTS-0017] Max level of the clock tree: 1. [INFO CTS-0018] Created 17 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. @@ -119,10 +118,11 @@ [INFO CTS-0124] Clock net "clk" [INFO CTS-0125] Sinks 1 [INFO CTS-0098] Clock net "clk_regs" -[INFO CTS-0099] Sinks 150 +[INFO CTS-0099] Sinks 165 [INFO CTS-0100] Leaf buffers 0 -[INFO CTS-0101] Average sink wire length 48.98 um +[INFO CTS-0101] Average sink wire length 48.10 um [INFO CTS-0102] Path depth 2 - 2 +[INFO CTS-0207] Leaf load cells 30 [INFO CTS-0098] Clock net "CELL\/clk2" [INFO CTS-0099] Sinks 165 [INFO CTS-0100] Leaf buffers 0 From c6b48589bd67f7039cd48ef4b81e30687714fb5b Mon Sep 17 00:00:00 2001 From: arthur Date: Thu, 11 Jul 2024 10:13:52 -0300 Subject: [PATCH 05/32] remove debug prints Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index a931f668ade..1b32abcf7bc 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2069,10 +2069,7 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, // ignore arrival fall (no inverters in current clock tree) float arrival_pin = openSta_->pinArrival( pin, sta::RiseFall::rise(), sta::MinMax::max()); - if (arrival != arrival_pin) { - logger_->report("returned arrival: {}", arrival); - logger_->report("pin arrival: {}", arrival_pin); - } + // add insertion delay float insDelay = 0.0; sta::LibertyCell* libCell From 34311deb91190adc151e36088fb01728a62b9229 Mon Sep 17 00:00:00 2001 From: arthur Date: Tue, 16 Jul 2024 12:33:47 -0300 Subject: [PATCH 06/32] fix error message Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 1b32abcf7bc..44d2eda4afa 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2013,7 +2013,7 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet) } if (paths_accepted > 1 || paths_accepted == 0) { logger_->error(CTS, - 1, + 2, "Number of clock paths is not 1. Number of clock paths: {}", paths_accepted); } From 9db8841b9027b4e27f824e7d39ac3fc3a03b431e Mon Sep 17 00:00:00 2001 From: arthur Date: Tue, 16 Jul 2024 15:18:43 -0300 Subject: [PATCH 07/32] debug prints Signed-off-by: arthur --- src/cts/include/cts/TritonCTS.h | 2 +- src/cts/src/TritonCTS.cpp | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index e7882bccdd5..1fed3d094ac 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -214,7 +214,7 @@ class TritonCTS ClockInst& dummyClock); void printClockNetwork(const Clock& clockNet) const; void balanceMacroRegisterLatencies(); - float getVertexClkArrival(sta::Vertex* sink_vertex, odb::dbNet* topNet); + float getVertexClkArrival(sta::Vertex* sink_vertex, odb::dbNet* topNet, odb::dbITerm* iterm); void computeAveSinkArrivals(TreeBuilder* builder); void computeSinkArrivalRecur(odb::dbNet* topClokcNet, odb::dbITerm* iterm, diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 44d2eda4afa..46a06914f5b 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -1964,7 +1964,7 @@ void TritonCTS::balanceMacroRegisterLatencies() } } -float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet) +float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, odb::dbITerm* iterm) { sta::VertexPathIterator path_iter(sinVertex, openSta_); float clkPathArrival = 0.0; @@ -2008,13 +2008,17 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet) if (path_start_net == topNet) { clkPathArrival = path->arrival(openSta_); paths_accepted += 1; + } else{ + logger_->report("Path start net regected: {}",path_start_net->getName()); } } } if (paths_accepted > 1 || paths_accepted == 0) { + logger_->error(CTS, 2, - "Number of clock paths is not 1. Number of clock paths: {}", + "Number of clock paths is not 1 for pin {}. Number of clock paths: {}", + iterm->getName(), paths_accepted); } return clkPathArrival; @@ -2028,7 +2032,7 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) openSta_->ensureClkArrivals(); Clock clock = builder->getClock(); odb::dbNet* topClockNet = clock.getNetObj(); - if (builder->getTreeType() == TreeType::RegisterTree) { + if (builder->getTopInputNet() != nullptr) { topClockNet = builder->getTopInputNet(); } // compute average input arrival at all sinks @@ -2065,7 +2069,7 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, if (pin) { sta::Graph* graph = openSta_->graph(); sta::Vertex* drvr_vertex = graph->pinDrvrVertex(pin); - float arrival = getVertexClkArrival(drvr_vertex, topClokcNet); + float arrival = getVertexClkArrival(drvr_vertex, topClokcNet, iterm); // ignore arrival fall (no inverters in current clock tree) float arrival_pin = openSta_->pinArrival( pin, sta::RiseFall::rise(), sta::MinMax::max()); From 11fc3b7d8dc852faf14a443f0386e9e0fbbfff97 Mon Sep 17 00:00:00 2001 From: arthur Date: Wed, 17 Jul 2024 17:14:22 -0300 Subject: [PATCH 08/32] store the input clock net information on the tree builder Signed-off-by: arthur --- src/cts/include/cts/TritonCTS.h | 7 +++-- src/cts/src/TreeBuilder.h | 3 ++ src/cts/src/TritonCTS.cpp | 54 ++++++++++++++++++++++++--------- 3 files changed, 48 insertions(+), 16 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index 1fed3d094ac..bb5b384071e 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -138,9 +138,11 @@ class TritonCTS void clearNumClocks() { numberOfClocks_ = 0; } unsigned getNumClocks() const { return numberOfClocks_; } void initOneClockTree(odb::dbNet* driverNet, + odb::dbNet* clkInputNet, const std::string& sdcClockName, TreeBuilder* parent); - TreeBuilder* initClock(odb::dbNet* net, + TreeBuilder* initClock(odb::dbNet* firstNet, + odb::dbNet* clkInputNet, const std::string& sdcClock, TreeBuilder* parentBuilder); void disconnectAllSinksFromNet(odb::dbNet* net); @@ -148,7 +150,8 @@ class TritonCTS void checkUpstreamConnections(odb::dbNet* net); void createClockBuffers(Clock& clockNet); HTreeBuilder* initClockTreeForMacrosAndRegs( - odb::dbNet*& net, + odb::dbNet*& firstNet, + odb::dbNet* clkInputNet, const std::unordered_set& buffer_masters, Clock& ClockNet, TreeBuilder* parentBuilder); diff --git a/src/cts/src/TreeBuilder.h b/src/cts/src/TreeBuilder.h index ec15843ff06..4109587f7dd 100644 --- a/src/cts/src/TreeBuilder.h +++ b/src/cts/src/TreeBuilder.h @@ -251,6 +251,8 @@ class TreeBuilder void setTopBufferName(std::string name) { topBufferName_ = name; } odb::dbNet* getTopInputNet() const { return topInputNet_; } void setTopInputNet(odb::dbNet* net) { topInputNet_ = net; } + odb::dbNet* getDrivingNet() const { return drivingNet_; } + void setDrivingNet(odb::dbNet* net) { drivingNet_ = net; } protected: CtsOptions* options_ = nullptr; @@ -281,6 +283,7 @@ class TreeBuilder float topBufferDelay_ = 0.0; odb::dbInst* topBuffer_ = nullptr; std::string topBufferName_; + odb::dbNet* drivingNet_ = nullptr; odb::dbNet* topInputNet_ = nullptr; }; diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 46a06914f5b..51ca0634b02 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -189,6 +189,7 @@ void TritonCTS::buildClockTrees() } void TritonCTS::initOneClockTree(odb::dbNet* driverNet, + odb::dbNet* clkInputNet, const std::string& sdcClockName, TreeBuilder* parent) { @@ -197,7 +198,7 @@ void TritonCTS::initOneClockTree(odb::dbNet* driverNet, logger_->info( CTS, 116, "Special net \"{}\" skipped.", driverNet->getName()); } else { - clockBuilder = initClock(driverNet, sdcClockName, parent); + clockBuilder = initClock(driverNet, clkInputNet, sdcClockName, parent); } // Treat gated clocks as separate clock trees // TODO: include sinks from gated clocks together with other sinks and build @@ -214,7 +215,7 @@ void TritonCTS::initOneClockTree(odb::dbNet* driverNet, if (visitedClockNets_.find(outputNet) == visitedClockNets_.end() && !openSta_->sdc()->isLeafPinClock( network_->dbToSta(outputPin))) { - initOneClockTree(outputNet, sdcClockName, clockBuilder); + initOneClockTree(outputNet, clkInputNet, sdcClockName, clockBuilder); } } } @@ -865,7 +866,7 @@ void TritonCTS::populateTritonCTS() // Initializes the net in TritonCTS. If the number of sinks is less than // 2, the net is discarded. if (visitedClockNets_.find(net) == visitedClockNets_.end()) { - initOneClockTree(net, clkName, nullptr); + initOneClockTree(net, net, clkName, nullptr); } } else { logger_->warn( @@ -886,6 +887,7 @@ void TritonCTS::populateTritonCTS() } TreeBuilder* TritonCTS::initClock(odb::dbNet* firstNet, + odb::dbNet* clkInputNet, const std::string& sdcClock, TreeBuilder* parentBuilder) { @@ -941,7 +943,7 @@ TreeBuilder* TritonCTS::initClock(odb::dbNet* firstNet, // Build a clock tree to drive macro cells with insertion delays // separated from registers or leaves without insertion delays HTreeBuilder* builder = initClockTreeForMacrosAndRegs( - firstNet, buffer_masters, clockNet, parentBuilder); + firstNet, clkInputNet, buffer_masters, clockNet, parentBuilder); return builder; } @@ -964,6 +966,7 @@ TreeBuilder* TritonCTS::initClock(odb::dbNet* firstNet, // HTreeBuilder* TritonCTS::initClockTreeForMacrosAndRegs( odb::dbNet*& firstNet, + odb::dbNet* clkInputNet, const std::unordered_set& buffer_masters, Clock& clockNet, TreeBuilder* parentBuilder) @@ -1024,6 +1027,7 @@ HTreeBuilder* TritonCTS::initClockTreeForMacrosAndRegs( "macros"); if (firstBuilder) { firstBuilder->setTreeType(TreeType::MacroTree); + firstBuilder->setTopInputNet(clkInputNet); } // create a new net 'secondNet' to drive register sinks @@ -1042,7 +1046,8 @@ HTreeBuilder* TritonCTS::initClockTreeForMacrosAndRegs( if (secondBuilder) { secondBuilder->setTreeType(TreeType::RegisterTree); secondBuilder->setTopBufferName(topBufferName); - secondBuilder->setTopInputNet(firstNet); + secondBuilder->setDrivingNet(firstNet); + secondBuilder->setTopInputNet(clkInputNet); } return secondBuilder; @@ -1201,7 +1206,7 @@ void TritonCTS::writeClockNetsToDb(TreeBuilder* builder, = block_->findInst(builder->getTopBufferName().c_str()); if (topRegBuffer) { odb::dbITerm* topRegBufferInputPin = getFirstInput(topRegBuffer); - topRegBufferInputPin->connect(builder->getTopInputNet()); + topRegBufferInputPin->connect(builder->getDrivingNet()); } } @@ -1970,11 +1975,24 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, float clkPathArrival = 0.0; int paths_accepted = 0; while (path_iter.hasNext()) { - sta::PathVertex* path = path_iter.next(); + sta::Path* path = path_iter.next(); + bool path_transition = true; + bool path_min_max = true; if (path->dcalcAnalysisPt(openSta_)->corner() != openSta_->cmdCorner()) { continue; } + if (path->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { + // only populate with rising edges + path_transition = false; + continue; + } + if (path->dcalcAnalysisPt(openSta_)->delayMinMax() + != sta::MinMax::max()) { + // only populate with max delay + path_min_max = false; + continue; + } sta::PathExpanded expand(path, openSta_); @@ -1985,13 +2003,23 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, odb::dbNet* path_start_net; if (start->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { // only populate with rising edges - continue; + if(path_transition) { + logger_->report("Não são o mesmo transitions"); + } } if (start->dcalcAnalysisPt(openSta_)->delayMinMax() != sta::MinMax::max()) { + if(path_min_max) { + logger_->report("Não são o mesmo MinMax"); + } // only populate with max delay - continue; + } + if(!path_transition) { + logger_->report("Não são o mesmo transitions"); + } + if(!path_min_max) { + logger_->report("Não são o mesmo MinMax"); } odb::dbITerm* term; @@ -2008,8 +2036,6 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, if (path_start_net == topNet) { clkPathArrival = path->arrival(openSta_); paths_accepted += 1; - } else{ - logger_->report("Path start net regected: {}",path_start_net->getName()); } } } @@ -2031,16 +2057,16 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) openSta_->ensureClkNetwork(); openSta_->ensureClkArrivals(); Clock clock = builder->getClock(); - odb::dbNet* topClockNet = clock.getNetObj(); + odb::dbNet* topInputClockNet = clock.getNetObj(); if (builder->getTopInputNet() != nullptr) { - topClockNet = builder->getTopInputNet(); + topInputClockNet = builder->getTopInputNet(); } // compute average input arrival at all sinks float sumArrivals = 0.0; unsigned numSinks = 0; clock.forEachSink([&](const ClockInst& sink) { odb::dbITerm* iterm = sink.getDbInputPin(); - computeSinkArrivalRecur(topClockNet, iterm, sumArrivals, numSinks); + computeSinkArrivalRecur(topInputClockNet, iterm, sumArrivals, numSinks); }); float aveArrival = sumArrivals / (float) numSinks; builder->setAveSinkArrival(aveArrival); From d97cac15bce714454d4f5c963b8c8b354834b1e7 Mon Sep 17 00:00:00 2001 From: arthurjolo Date: Thu, 18 Jul 2024 20:36:28 +0000 Subject: [PATCH 09/32] debug prints Signed-off-by: arthurjolo --- src/cts/src/TritonCTS.cpp | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 51ca0634b02..feb4ae0f9b9 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -1971,6 +1971,7 @@ void TritonCTS::balanceMacroRegisterLatencies() float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, odb::dbITerm* iterm) { + logger_->report("Analisando iterm: {}", iterm->getName()); sta::VertexPathIterator path_iter(sinVertex, openSta_); float clkPathArrival = 0.0; int paths_accepted = 0; @@ -1978,20 +1979,14 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, sta::Path* path = path_iter.next(); bool path_transition = true; bool path_min_max = true; - - if (path->dcalcAnalysisPt(openSta_)->corner() != openSta_->cmdCorner()) { - continue; - } if (path->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { // only populate with rising edges - path_transition = false; - continue; + path_transition = false; } if (path->dcalcAnalysisPt(openSta_)->delayMinMax() != sta::MinMax::max()) { // only populate with max delay path_min_max = false; - continue; } sta::PathExpanded expand(path, openSta_); @@ -2003,7 +1998,8 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, odb::dbNet* path_start_net; if (start->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { // only populate with rising edges - if(path_transition) { + continue; + if(path_transition) { logger_->report("Não são o mesmo transitions"); } } @@ -2013,6 +2009,7 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, if(path_min_max) { logger_->report("Não são o mesmo MinMax"); } + continue; // only populate with max delay } if(!path_transition) { @@ -2029,14 +2026,23 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, network_->staToDb(start->pin(openSta_), term, port, moditerm, modbterm); if (term) { path_start_net = term->getNet(); + if (iterm->getName() == "u_ca53_noram/u_ca53tlb/u_tlb_pagewalk/g_protection_pw6_walk_cache_ecc_err_early_reg/CK") { + logger_->report("iterm do start: {}", term->getName()); + } } if (port) { path_start_net = port->getNet(); + if (iterm->getName() == "u_ca53_noram/u_ca53tlb/u_tlb_pagewalk/g_protection_pw6_walk_cache_ecc_err_early_reg/CK") { + logger_->report("iterm do start: {}", port->getName()); + } } if (path_start_net == topNet) { clkPathArrival = path->arrival(openSta_); paths_accepted += 1; - } + return clkPathArrival; + } else if (iterm->getName() == "u_ca53_noram/u_ca53tlb/u_tlb_pagewalk/g_protection_pw6_walk_cache_ecc_err_early_reg/CK") { + logger_->report("Rejeitou: {}, Queria: {}",path_start_net->getName(), topNet->getName()); + } } } if (paths_accepted > 1 || paths_accepted == 0) { @@ -2097,7 +2103,7 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, sta::Vertex* drvr_vertex = graph->pinDrvrVertex(pin); float arrival = getVertexClkArrival(drvr_vertex, topClokcNet, iterm); // ignore arrival fall (no inverters in current clock tree) - float arrival_pin = openSta_->pinArrival( + float pin_arrival = openSta_->pinArrival( pin, sta::RiseFall::rise(), sta::MinMax::max()); // add insertion delay From e2c3b7fae5ad1895fd79ccbb854ac33522396044 Mon Sep 17 00:00:00 2001 From: arthurjolo Date: Tue, 23 Jul 2024 02:54:51 +0000 Subject: [PATCH 10/32] remove debug print Signed-off-by: arthurjolo --- src/cts/src/TritonCTS.cpp | 29 +++++------------------------ 1 file changed, 5 insertions(+), 24 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index feb4ae0f9b9..d7281aa5a74 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -1206,6 +1206,7 @@ void TritonCTS::writeClockNetsToDb(TreeBuilder* builder, = block_->findInst(builder->getTopBufferName().c_str()); if (topRegBuffer) { odb::dbITerm* topRegBufferInputPin = getFirstInput(topRegBuffer); + odb::dbITerm* topRegBufferOutPin = topRegBuffer->getFirstOutput(); topRegBufferInputPin->connect(builder->getDrivingNet()); } } @@ -1971,7 +1972,6 @@ void TritonCTS::balanceMacroRegisterLatencies() float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, odb::dbITerm* iterm) { - logger_->report("Analisando iterm: {}", iterm->getName()); sta::VertexPathIterator path_iter(sinVertex, openSta_); float clkPathArrival = 0.0; int paths_accepted = 0; @@ -1999,25 +1999,13 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, if (start->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { // only populate with rising edges continue; - if(path_transition) { - logger_->report("Não são o mesmo transitions"); - } } if (start->dcalcAnalysisPt(openSta_)->delayMinMax() != sta::MinMax::max()) { - if(path_min_max) { - logger_->report("Não são o mesmo MinMax"); - } continue; // only populate with max delay } - if(!path_transition) { - logger_->report("Não são o mesmo transitions"); - } - if(!path_min_max) { - logger_->report("Não são o mesmo MinMax"); - } odb::dbITerm* term; odb::dbBTerm* port; @@ -2026,30 +2014,23 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, network_->staToDb(start->pin(openSta_), term, port, moditerm, modbterm); if (term) { path_start_net = term->getNet(); - if (iterm->getName() == "u_ca53_noram/u_ca53tlb/u_tlb_pagewalk/g_protection_pw6_walk_cache_ecc_err_early_reg/CK") { - logger_->report("iterm do start: {}", term->getName()); - } + + } if (port) { path_start_net = port->getNet(); - if (iterm->getName() == "u_ca53_noram/u_ca53tlb/u_tlb_pagewalk/g_protection_pw6_walk_cache_ecc_err_early_reg/CK") { - logger_->report("iterm do start: {}", port->getName()); - } + } if (path_start_net == topNet) { clkPathArrival = path->arrival(openSta_); paths_accepted += 1; return clkPathArrival; - } else if (iterm->getName() == "u_ca53_noram/u_ca53tlb/u_tlb_pagewalk/g_protection_pw6_walk_cache_ecc_err_early_reg/CK") { - logger_->report("Rejeitou: {}, Queria: {}",path_start_net->getName(), topNet->getName()); } } } if (paths_accepted > 1 || paths_accepted == 0) { - logger_->error(CTS, - 2, - "Number of clock paths is not 1 for pin {}. Number of clock paths: {}", + logger_->report("Number of clock paths is not 1 for pin {}. Number of clock paths: {}", iterm->getName(), paths_accepted); } From 079addee18c4e74e95219cf2d6fd8bd94c531e4a Mon Sep 17 00:00:00 2001 From: arthur Date: Fri, 23 Aug 2024 10:56:07 -0300 Subject: [PATCH 11/32] format code Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index d7281aa5a74..9d83300d37c 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2003,7 +2003,7 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, if (start->dcalcAnalysisPt(openSta_)->delayMinMax() != sta::MinMax::max()) { - continue; + continue; // only populate with max delay } @@ -2014,8 +2014,6 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, network_->staToDb(start->pin(openSta_), term, port, moditerm, modbterm); if (term) { path_start_net = term->getNet(); - - } if (port) { path_start_net = port->getNet(); @@ -2024,7 +2022,7 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, if (path_start_net == topNet) { clkPathArrival = path->arrival(openSta_); paths_accepted += 1; - return clkPathArrival; + return clkPathArrival; } } } From 17c46015f66bda2b44ec1a283cfaad966ccbdbee Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 26 Aug 2024 16:10:12 -0300 Subject: [PATCH 12/32] update graph information correctly Signed-off-by: arthur --- src/cts/include/cts/TritonCTS.h | 6 +++-- src/cts/src/TritonCTS.cpp | 41 +++++++++++++-------------------- 2 files changed, 20 insertions(+), 27 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index b58dfe02bb5..d69abaa6275 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -59,6 +59,7 @@ class dbNetwork; class Unit; class LibertyCell; class Vertex; +class Graph; } // namespace sta namespace stt { @@ -210,11 +211,12 @@ class TritonCTS void printClockNetwork(const Clock& clockNet) const; void balanceMacroRegisterLatencies(); float getVertexClkArrival(sta::Vertex* sink_vertex, odb::dbNet* topNet, odb::dbITerm* iterm); - void computeAveSinkArrivals(TreeBuilder* builder); + void computeAveSinkArrivals(TreeBuilder* builder, sta::Graph* graph); void computeSinkArrivalRecur(odb::dbNet* topClokcNet, odb::dbITerm* iterm, float& sumArrivals, - unsigned& numSinks); + unsigned& numSinks, + sta::Graph* graph); void adjustLatencies(TreeBuilder* macroBuilder, TreeBuilder* registerBuilder); void computeTopBufferDelay(TreeBuilder* builder); odb::dbInst* insertDelayBuffer(odb::dbInst* driver, diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 127f0de1abe..bb6f9587b91 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2023,14 +2023,23 @@ void TritonCTS::balanceMacroRegisterLatencies() // Visit builders from bottom up such that latencies are adjusted near bottom // trees first + openSta_->ensureGraph(); + openSta_->searchPreamble(); + openSta_->ensureClkNetwork(); + openSta_->ensureClkArrivals(); + sta::Graph* graph = openSta_->graph(); for (auto iter = builders_->rbegin(); iter != builders_->rend(); ++iter) { TreeBuilder* registerBuilder = *iter; if (registerBuilder->getTreeType() == TreeType::RegisterTree) { TreeBuilder* macroBuilder = registerBuilder->getParent(); if (macroBuilder) { - computeAveSinkArrivals(registerBuilder); - computeAveSinkArrivals(macroBuilder); + computeAveSinkArrivals(registerBuilder, graph); + computeAveSinkArrivals(macroBuilder, graph); adjustLatencies(macroBuilder, registerBuilder); + // Update graph information after possible buffers inserted + openSta_->updateTiming(false); + openSta_->ensureClkNetwork(); + openSta_->ensureClkArrivals(); } } } @@ -2043,17 +2052,6 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, int paths_accepted = 0; while (path_iter.hasNext()) { sta::Path* path = path_iter.next(); - bool path_transition = true; - bool path_min_max = true; - if (path->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { - // only populate with rising edges - path_transition = false; - } - if (path->dcalcAnalysisPt(openSta_)->delayMinMax() - != sta::MinMax::max()) { - // only populate with max delay - path_min_max = false; - } sta::PathExpanded expand(path, openSta_); @@ -2101,12 +2099,8 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, return clkPathArrival; } -void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) +void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder, sta::Graph* graph) { - openSta_->ensureGraph(); - openSta_->searchPreamble(); - openSta_->ensureClkNetwork(); - openSta_->ensureClkArrivals(); Clock clock = builder->getClock(); odb::dbNet* topInputClockNet = clock.getNetObj(); if (builder->getTopInputNet() != nullptr) { @@ -2117,7 +2111,7 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) unsigned numSinks = 0; clock.forEachSink([&](const ClockInst& sink) { odb::dbITerm* iterm = sink.getDbInputPin(); - computeSinkArrivalRecur(topInputClockNet, iterm, sumArrivals, numSinks); + computeSinkArrivalRecur(topInputClockNet, iterm, sumArrivals, numSinks, graph); }); float aveArrival = sumArrivals / (float) numSinks; builder->setAveSinkArrival(aveArrival); @@ -2135,7 +2129,8 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, odb::dbITerm* iterm, float& sumArrivals, - unsigned& numSinks) + unsigned& numSinks, + sta::Graph* graph) { if (iterm) { odb::dbInst* inst = iterm->getInst(); @@ -2144,12 +2139,8 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, // either register or macro input pin sta::Pin* pin = network_->dbToSta(iterm); if (pin) { - sta::Graph* graph = openSta_->graph(); sta::Vertex* drvr_vertex = graph->pinDrvrVertex(pin); float arrival = getVertexClkArrival(drvr_vertex, topClokcNet, iterm); - // ignore arrival fall (no inverters in current clock tree) - float pin_arrival = openSta_->pinArrival( - pin, sta::RiseFall::rise(), sta::MinMax::max()); // add insertion delay float insDelay = 0.0; @@ -2186,7 +2177,7 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, odb::dbITerm* inTerm = *iter; if (inTerm->getIoType() == odb::dbIoType::INPUT) { computeSinkArrivalRecur( - topClokcNet, inTerm, sumArrivals, numSinks); + topClokcNet, inTerm, sumArrivals, numSinks, graph); } } } From 833b9173bba69cb50eef50da0189a2426db9ec96 Mon Sep 17 00:00:00 2001 From: arthur Date: Thu, 7 Nov 2024 17:19:41 -0300 Subject: [PATCH 13/32] fix crash Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index d3b4e2cbec8..e910b5609f7 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2184,6 +2184,10 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, float arrival = getVertexClkArrival(sinkVertex, topClokcNet, iterm); float pin_arrival = openSta_->pinArrival( pin, sta::RiseFall::rise(), sta::MinMax::max()); + if(arrival != pin_arrival) { + logger_->report("Arrival we looked up: {}", arrival); + logger_->report("Arrival from sta API: {}", pin_arrival); + } // add insertion delay float insDelay = 0.0; sta::LibertyCell* libCell @@ -2291,7 +2295,7 @@ void TritonCTS::adjustLatencies(TreeBuilder* macroBuilder, double locY = (double) (sourceY + offsetY * (i + 1)) / scalingFactor; Point bufferLoc(locX, locY); Point legalBufferLoc - = builder->legalizeOneBuffer(bufferLoc, options_->getRootBuffer(), std::vector>()); + = builder->legalizeOneBuffer(bufferLoc, options_->getRootBuffer()); odb::dbInst* buffer = insertDelayBuffer(driver, builder->getClock().getSdcName(), From 1f22e4b9503bc72857606b190f6d25fa92c150d0 Mon Sep 17 00:00:00 2001 From: arthur Date: Fri, 8 Nov 2024 14:10:23 -0300 Subject: [PATCH 14/32] remove unused variables Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index e910b5609f7..a2965003043 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -1285,9 +1285,6 @@ void TritonCTS::writeClockNetsToDb(TreeBuilder* builder, odb::dbModule* top_module = network_->getNetDriverParentModule(network_->dbToSta(topClockNet)); - const std::string topRegBufferName = "clkbuf_regs_0_" + clockNet.getSdcName(); - odb::dbInst* topRegBuffer = block_->findInst(topRegBufferName.c_str()); - disconnectAllSinksFromNet(topClockNet); // re-connect top buffer that separates macros from registers @@ -2182,12 +2179,6 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, if (pin) { sta::Vertex* sinkVertex = graph->pinDrvrVertex(pin); float arrival = getVertexClkArrival(sinkVertex, topClokcNet, iterm); - float pin_arrival = openSta_->pinArrival( - pin, sta::RiseFall::rise(), sta::MinMax::max()); - if(arrival != pin_arrival) { - logger_->report("Arrival we looked up: {}", arrival); - logger_->report("Arrival from sta API: {}", pin_arrival); - } // add insertion delay float insDelay = 0.0; sta::LibertyCell* libCell From 6774e439088004984f09bfc6af991195d28e2229 Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 11 Nov 2024 10:05:10 -0300 Subject: [PATCH 15/32] add possible speedup Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index a2965003043..47116966aee 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2090,24 +2090,23 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet int pathsAccepted = 0; while (pathIter.hasNext()) { sta::Path* path = pathIter.next(); + if (path->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { + // only populate with rising edges + continue; + } - sta::PathExpanded expand(path, openSta_); + if (path->dcalcAnalysisPt(openSta_)->delayMinMax() + != sta::MinMax::max()) { + continue; + // only populate with max delay + } const sta::Clock* clock = path->clock(openSta_); - if (clock || !clock) { + if (clock) { const sta::PathRef* start = expand.startPath(); + sta::PathExpanded expand(path, openSta_); odb::dbNet* pathStartNet = nullptr; - if (start->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { - // only populate with rising edges - continue; - } - - if (start->dcalcAnalysisPt(openSta_)->delayMinMax() - != sta::MinMax::max()) { - continue; - // only populate with max delay - } odb::dbITerm* term; odb::dbBTerm* port; From c618ba53625336c10b7487b0de75ed6b5e3850e1 Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 11 Nov 2024 10:37:55 -0300 Subject: [PATCH 16/32] fix crash Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 47116966aee..301f173cb0f 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2103,8 +2103,9 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet const sta::Clock* clock = path->clock(openSta_); if (clock) { - const sta::PathRef* start = expand.startPath(); sta::PathExpanded expand(path, openSta_); + const sta::PathRef* start = expand.startPath(); + odb::dbNet* pathStartNet = nullptr; From 63ee16f6ed8951558ff3f529a368f9aac287ef7d Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 11 Nov 2024 10:53:36 -0300 Subject: [PATCH 17/32] calng format Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 301f173cb0f..902c62700b9 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -299,7 +299,8 @@ void TritonCTS::initOneClockTree(odb::dbNet* driverNet, if (visitedClockNets_.find(outputNet) == visitedClockNets_.end() && !openSta_->sdc()->isLeafPinClock( network_->dbToSta(outputPin))) { - initOneClockTree(outputNet, clkInputNet, sdcClockName, clockBuilder); + initOneClockTree( + outputNet, clkInputNet, sdcClockName, clockBuilder); } } } @@ -1230,8 +1231,8 @@ Clock TritonCTS::forkRegisterClockNetwork( odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str()); topBufferName = "clkbuf_regs_" + std::to_string(regTreeRootBufIndex_++) + "_" + clockNet.getSdcName(); - odb::dbInst* clockBuf - = odb::dbInst::create(block_, master, topBufferName.c_str(), false, target_module); + odb::dbInst* clockBuf = odb::dbInst::create( + block_, master, topBufferName.c_str(), false, target_module); odb::dbITerm* inputTerm = getFirstInput(clockBuf); odb::dbITerm* outputTerm = clockBuf->getFirstOutput(); inputTerm->connect(firstNet); @@ -2082,9 +2083,10 @@ void TritonCTS::balanceMacroRegisterLatencies() } } -float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet, odb::dbITerm* iterm) +float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, + odb::dbNet* topNet, + odb::dbITerm* iterm) { - sta::VertexPathIterator pathIter(sinkVertex, openSta_); float clkPathArrival = 0.0; int pathsAccepted = 0; @@ -2095,8 +2097,7 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet continue; } - if (path->dcalcAnalysisPt(openSta_)->delayMinMax() - != sta::MinMax::max()) { + if (path->dcalcAnalysisPt(openSta_)->delayMinMax() != sta::MinMax::max()) { continue; // only populate with max delay } @@ -2105,7 +2106,6 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet if (clock) { sta::PathExpanded expand(path, openSta_); const sta::PathRef* start = expand.startPath(); - odb::dbNet* pathStartNet = nullptr; @@ -2119,7 +2119,6 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet } if (port) { pathStartNet = port->getNet(); - } if (pathStartNet == topNet) { clkPathArrival = path->arrival(openSta_); @@ -2129,10 +2128,10 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet } } if (pathsAccepted > 1 || pathsAccepted == 0) { - - logger_->report("Number of clock paths is not 1 for pin {}. Number of clock paths: {}", - iterm->getName(), - pathsAccepted); + logger_->report( + "Number of clock paths is not 1 for pin {}. Number of clock paths: {}", + iterm->getName(), + pathsAccepted); } return clkPathArrival; } @@ -2149,7 +2148,8 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder, sta::Graph* graph) unsigned numSinks = 0; clock.forEachSink([&](const ClockInst& sink) { odb::dbITerm* iterm = sink.getDbInputPin(); - computeSinkArrivalRecur(topInputClockNet, iterm, sumArrivals, numSinks, graph); + computeSinkArrivalRecur( + topInputClockNet, iterm, sumArrivals, numSinks, graph); }); float aveArrival = sumArrivals / (float) numSinks; builder->setAveSinkArrival(aveArrival); From 1df059944f773a8313be76ec9be3f92b1249dbdc Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 11 Nov 2024 11:33:06 -0300 Subject: [PATCH 18/32] update ok file Signed-off-by: arthur --- src/cts/test/lvt_lib.ok | 44 ++++++++++++++++++++++++++++++++--------- 1 file changed, 35 insertions(+), 9 deletions(-) diff --git a/src/cts/test/lvt_lib.ok b/src/cts/test/lvt_lib.ok index 9560c02ec12..d754950c415 100644 --- a/src/cts/test/lvt_lib.ok +++ b/src/cts/test/lvt_lib.ok @@ -7,14 +7,32 @@ CLKBUF_X1_L [INFO CTS-0049] Characterization buffer is CLKBUF_X1_L. [INFO CTS-0007] Net "clk" found for clock "clk". -[INFO CTS-0010] Clock net "clk" has 151 sinks. +[INFO CTS-0011] Clock net "clk" for macros has 1 sinks. +[INFO CTS-0011] Clock net "clk_regs" for registers has 150 sinks. [INFO CTS-0010] Clock net "CELL/clk2" has 150 sinks. -[INFO CTS-0008] TritonCTS found 2 clock nets. +[INFO CTS-0008] TritonCTS found 3 clock nets. [INFO CTS-0097] Characterization used 1 buffer(s) types. [INFO CTS-0200] 0 placement blockages have been identified. [INFO CTS-0201] 0 placed hard macros will be treated like blockages. [INFO CTS-0027] Generating H-Tree topology for net clk. -[INFO CTS-0028] Total number of sinks: 151. +[INFO CTS-0028] Total number of sinks: 1. +[INFO CTS-0030] Number of static layers: 0. +[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). +[INFO CTS-0023] Original sink region: [(100250, 101225), (100250, 101225)]. +[INFO CTS-0024] Normalized sink region: [(7.16071, 7.23036), (7.16071, 7.23036)]. +[INFO CTS-0025] Width: 0.0000. +[INFO CTS-0026] Height: 0.0000. + Level 1 + Direction: Vertical + Sinks per sub-region: 1 + Sub-region size: 0.0000 X 0.0000 +[INFO CTS-0034] Segment length (rounded): 1. +[INFO CTS-0032] Stop criterion found. Max number of sinks is 15. +[INFO CTS-0035] Number of sinks covered: 1. +[INFO CTS-0200] 0 placement blockages have been identified. +[INFO CTS-0201] 0 placed hard macros will be treated like blockages. +[INFO CTS-0027] Generating H-Tree topology for net clk_regs. +[INFO CTS-0028] Total number of sinks: 150. [INFO CTS-0030] Number of static layers: 0. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). [INFO CTS-0023] Original sink region: [(8785, 6785), (197672, 95673)]. @@ -23,7 +41,7 @@ [INFO CTS-0026] Height: 6.3491. Level 1 Direction: Horizontal - Sinks per sub-region: 76 + Sinks per sub-region: 75 Sub-region size: 6.7460 X 6.3491 [INFO CTS-0034] Segment length (rounded): 4. Level 2 @@ -42,7 +60,7 @@ Sub-region size: 3.3730 X 1.5873 [INFO CTS-0034] Segment length (rounded): 1. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. -[INFO CTS-0035] Number of sinks covered: 151. +[INFO CTS-0035] Number of sinks covered: 150. [INFO CTS-0200] 0 placement blockages have been identified. [INFO CTS-0201] 0 placed hard macros will be treated like blockages. [INFO CTS-0027] Generating H-Tree topology for net CELL\/clk2. @@ -75,11 +93,17 @@ [INFO CTS-0034] Segment length (rounded): 1. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. [INFO CTS-0035] Number of sinks covered: 150. +[INFO CTS-0018] Created 2 clock buffers. +[INFO CTS-0012] Minimum number of buffers in the clock path: 2. +[INFO CTS-0013] Maximum number of buffers in the clock path: 2. +[INFO CTS-0015] Created 2 clock nets. +[INFO CTS-0016] Fanout distribution for the current clock = 1:1.. +[INFO CTS-0017] Max level of the clock tree: 1. [INFO CTS-0018] Created 17 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. [INFO CTS-0013] Maximum number of buffers in the clock path: 2. [INFO CTS-0015] Created 17 clock nets. -[INFO CTS-0016] Fanout distribution for the current clock = 7:1, 8:4, 9:5, 10:3, 12:2, 13:1.. +[INFO CTS-0016] Fanout distribution for the current clock = 7:1, 8:4, 9:6, 10:2, 12:2, 13:1.. [INFO CTS-0017] Max level of the clock tree: 4. [INFO CTS-0018] Created 17 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. @@ -87,10 +111,12 @@ [INFO CTS-0015] Created 17 clock nets. [INFO CTS-0016] Fanout distribution for the current clock = 7:3, 8:2, 9:4, 10:4, 12:2, 13:1.. [INFO CTS-0017] Max level of the clock tree: 4. -[INFO CTS-0098] Clock net "clk" -[INFO CTS-0099] Sinks 166 +[INFO CTS-0124] Clock net "clk" +[INFO CTS-0125] Sinks 1 +[INFO CTS-0098] Clock net "clk_regs" +[INFO CTS-0099] Sinks 165 [INFO CTS-0100] Leaf buffers 0 -[INFO CTS-0101] Average sink wire length 121.61 um +[INFO CTS-0101] Average sink wire length 48.97 um [INFO CTS-0102] Path depth 2 - 2 [INFO CTS-0207] Leaf load cells 30 [INFO CTS-0098] Clock net "CELL\/clk2" From 3ca3d4ee142b2bb476dd7b6d4f684edbfa292f83 Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 11 Nov 2024 11:34:23 -0300 Subject: [PATCH 19/32] remove non exiting flag Signed-off-by: arthur --- src/cts/test/cts_aux.py | 1 - 1 file changed, 1 deletion(-) diff --git a/src/cts/test/cts_aux.py b/src/cts/test/cts_aux.py index a1d2a33bab7..058eda0712b 100644 --- a/src/cts/test/cts_aux.py +++ b/src/cts/test/cts_aux.py @@ -64,7 +64,6 @@ def clock_tree_synthesis( parms.setSinkClustering(sink_clustering_enable) parms.setBalanceLevels(balance_levels) parms.setObstructionAware(obstruction_aware) - parms.enableInsertionDelay(insertion_delay) parms.setApplyNDR(apply_ndr) if is_pos_int(sink_clustering_size): From 6613c2d73bd6086670f3bd4f1a367dd3c5137143 Mon Sep 17 00:00:00 2001 From: arthur Date: Tue, 12 Nov 2024 14:44:49 -0300 Subject: [PATCH 20/32] address clang tidy Signed-off-by: arthur --- src/cts/include/cts/TritonCTS.h | 2 +- src/cts/src/TreeBuilder.h | 2 +- src/cts/src/TritonCTS.cpp | 17 ++++------------- 3 files changed, 6 insertions(+), 15 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index 9d13b180d69..3542344a5ff 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -207,7 +207,7 @@ class TritonCTS ClockInst& dummyClock); void printClockNetwork(const Clock& clockNet) const; void balanceMacroRegisterLatencies(); - float getVertexClkArrival(sta::Vertex* sink_vertex, odb::dbNet* topNet, odb::dbITerm* iterm); + float getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet, odb::dbITerm* iterm); void computeAveSinkArrivals(TreeBuilder* builder, sta::Graph* graph); void computeSinkArrivalRecur(odb::dbNet* topClokcNet, odb::dbITerm* iterm, diff --git a/src/cts/src/TreeBuilder.h b/src/cts/src/TreeBuilder.h index 4109587f7dd..9323d6e80c5 100644 --- a/src/cts/src/TreeBuilder.h +++ b/src/cts/src/TreeBuilder.h @@ -248,7 +248,7 @@ class TreeBuilder odb::dbInst* getTopBuffer() const { return topBuffer_; } void setTopBuffer(odb::dbInst* inst) { topBuffer_ = inst; } std::string getTopBufferName() const { return topBufferName_; } - void setTopBufferName(std::string name) { topBufferName_ = name; } + void setTopBufferName(std::string name) { topBufferName_ = std::move(name); } odb::dbNet* getTopInputNet() const { return topInputNet_; } void setTopInputNet(odb::dbNet* net) { topInputNet_ = net; } odb::dbNet* getDrivingNet() const { return drivingNet_; } diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 902c62700b9..52c1aff048b 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2089,7 +2089,6 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, { sta::VertexPathIterator pathIter(sinkVertex, openSta_); float clkPathArrival = 0.0; - int pathsAccepted = 0; while (pathIter.hasNext()) { sta::Path* path = pathIter.next(); if (path->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { @@ -2111,9 +2110,9 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbITerm* term; odb::dbBTerm* port; - odb::dbModITerm* moditerm; - odb::dbModBTerm* modbterm; - network_->staToDb(start->pin(openSta_), term, port, moditerm, modbterm); + odb::dbModITerm* modIterm; + odb::dbModBTerm* modBterm; + network_->staToDb(start->pin(openSta_), term, port, modIterm, modBterm); if (term) { pathStartNet = term->getNet(); } @@ -2122,17 +2121,11 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, } if (pathStartNet == topNet) { clkPathArrival = path->arrival(openSta_); - pathsAccepted += 1; return clkPathArrival; } } } - if (pathsAccepted > 1 || pathsAccepted == 0) { - logger_->report( - "Number of clock paths is not 1 for pin {}. Number of clock paths: {}", - iterm->getName(), - pathsAccepted); - } + logger_->warn(CTS, 2, "No paths found for pin {}.", iterm->getName()); return clkPathArrival; } @@ -2201,7 +2194,6 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, sumArrivals += (arrival + insDelay); numSinks++; } - return; } else { // not a sink, but a clock gater odb::dbITerm* outTerm = inst->getFirstOutput(); @@ -2222,7 +2214,6 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, } } } - return; } // Balance latencies between macro tree and register tree From c5dc866f035dc6fa71ce4e112754f8e1d5aed810 Mon Sep 17 00:00:00 2001 From: arthur Date: Tue, 12 Nov 2024 14:45:08 -0300 Subject: [PATCH 21/32] clang Signed-off-by: arthur --- src/cts/include/cts/TritonCTS.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index 3542344a5ff..d8c207b4888 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -207,7 +207,9 @@ class TritonCTS ClockInst& dummyClock); void printClockNetwork(const Clock& clockNet) const; void balanceMacroRegisterLatencies(); - float getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet, odb::dbITerm* iterm); + float getVertexClkArrival(sta::Vertex* sinkVertex, + odb::dbNet* topNet, + odb::dbITerm* iterm); void computeAveSinkArrivals(TreeBuilder* builder, sta::Graph* graph); void computeSinkArrivalRecur(odb::dbNet* topClokcNet, odb::dbITerm* iterm, From 3ed2a0445bc5cbb051039f7f2f46c832522ad5f1 Mon Sep 17 00:00:00 2001 From: arthur Date: Tue, 12 Nov 2024 14:45:33 -0300 Subject: [PATCH 22/32] fix regression failures Signed-off-by: arthur --- test/ibex_sky130hd.metrics_limits | 22 +++++++++++----------- test/ibex_sky130hs.metrics_limits | 24 ++++++++++++------------ 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/test/ibex_sky130hd.metrics_limits b/test/ibex_sky130hd.metrics_limits index 185e5444f13..11585434c29 100644 --- a/test/ibex_sky130hd.metrics_limits +++ b/test/ibex_sky130hd.metrics_limits @@ -1,22 +1,22 @@ { "IFP::instance_count" : "18835.2" - ,"DPL::design_area" : "201139.19999999998" - ,"DPL::utilization" : "33.12" + ,"DPL::design_area" : "197145.6" + ,"DPL::utilization" : "32.52" ,"RSZ::repair_design_buffer_count" : "403" ,"RSZ::max_slew_slack" : "0" ,"RSZ::max_capacitance_slack" : "0" ,"RSZ::max_fanout_slack" : "0" - ,"RSZ::worst_slack_min" : "-1.514693533972104" - ,"RSZ::worst_slack_max" : "-3.4550099408817325" - ,"RSZ::tns_max" : "-2410.336839746874" - ,"RSZ::hold_buffer_count" : "387" + ,"RSZ::worst_slack_min" : "-1.0439922649094353" + ,"RSZ::worst_slack_max" : "-2.3114357842543503" + ,"RSZ::tns_max" : "-2381.8289966316056" + ,"RSZ::hold_buffer_count" : "0" ,"GRT::ANT::errors" : "0" ,"DRT::drv" : "0" - ,"DRT::worst_slack_min" : "-2.022091227750159" - ,"DRT::worst_slack_max" : "-4.526241963178564" - ,"DRT::tns_max" : "-2565.5963862496214" - ,"DRT::clock_skew" : "3.196192734278436" - ,"DRT::max_slew_slack" : "-4.185469746589661" + ,"DRT::worst_slack_min" : "-1.2937988918086523" + ,"DRT::worst_slack_max" : "-3.319472133845383" + ,"DRT::tns_max" : "-2397.881877888032" + ,"DRT::clock_skew" : "3.1835918802282483" + ,"DRT::max_slew_slack" : "-5.152180790901185" ,"DRT::max_capacitance_slack" : "0" ,"DRT::max_fanout_slack" : "0" ,"DRT::clock_period" : "15.155" diff --git a/test/ibex_sky130hs.metrics_limits b/test/ibex_sky130hs.metrics_limits index 3ccd598ac6d..ad127349cd9 100644 --- a/test/ibex_sky130hs.metrics_limits +++ b/test/ibex_sky130hs.metrics_limits @@ -1,23 +1,23 @@ { "IFP::instance_count" : "16722.0" - ,"DPL::design_area" : "303136.8" - ,"DPL::utilization" : "50.16" + ,"DPL::design_area" : "297738.0" + ,"DPL::utilization" : "49.199999999999996" ,"RSZ::repair_design_buffer_count" : "562" ,"RSZ::max_slew_slack" : "0" ,"RSZ::max_capacitance_slack" : "0" ,"RSZ::max_fanout_slack" : "0" - ,"RSZ::worst_slack_min" : "-1.1252660978179787" - ,"RSZ::worst_slack_max" : "-1.1080318832747007" + ,"RSZ::worst_slack_min" : "-0.8296003753220063" + ,"RSZ::worst_slack_max" : "-0.3892583777709363" ,"RSZ::tns_max" : "-1573.2615" - ,"RSZ::hold_buffer_count" : "409" - ,"GRT::ANT::errors" : "1" + ,"RSZ::hold_buffer_count" : "0" + ,"GRT::ANT::errors" : "0" ,"DRT::drv" : "0" - ,"DRT::worst_slack_min" : "-1.4389010025203173" - ,"DRT::worst_slack_max" : "-1.7248460560269625" - ,"DRT::tns_max" : "-1596.287934744031" - ,"DRT::clock_skew" : "2.3666093754562323" - ,"DRT::max_slew_slack" : "-35.96203565597534" - ,"DRT::max_capacitance_slack" : "-40.381100718502445" + ,"DRT::worst_slack_min" : "-0.8301188494891697" + ,"DRT::worst_slack_max" : "-1.0005294288490796" + ,"DRT::tns_max" : "-1573.2615" + ,"DRT::clock_skew" : "2.3486445453242455" + ,"DRT::max_slew_slack" : "-43.21588397026062" + ,"DRT::max_capacitance_slack" : "-48.642419470111655" ,"DRT::max_fanout_slack" : "0" ,"DRT::clock_period" : "11.29" ,"DRT::ANT::errors" : "0" From ead9e13c62de5286fd6ad693d99f4a1bef0d850d Mon Sep 17 00:00:00 2001 From: Vitor Bandeira Date: Fri, 1 Nov 2024 20:31:41 +0000 Subject: [PATCH 23/32] deb: fix changelog syntax Signed-off-by: Vitor Bandeira --- debian/create-changelog.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/debian/create-changelog.sh b/debian/create-changelog.sh index 320f475f707..901e4541cd5 100755 --- a/debian/create-changelog.sh +++ b/debian/create-changelog.sh @@ -8,5 +8,7 @@ fi cat > debian/changelog < on %ad") + * Automated release + +$(git log --date=rfc -1 --pretty=format:" -- %an <%ae> %ad") EOF From 977b0fbe03f2708dd746b71610bf3707ab5dc877 Mon Sep 17 00:00:00 2001 From: Vitor Bandeira Date: Fri, 1 Nov 2024 20:31:58 +0000 Subject: [PATCH 24/32] deb: disable testing Signed-off-by: Vitor Bandeira --- debian/rules | 1 + 1 file changed, 1 insertion(+) diff --git a/debian/rules b/debian/rules index 4512dc18b7b..b62ff4b8fc9 100755 --- a/debian/rules +++ b/debian/rules @@ -18,4 +18,5 @@ override_dh_shlibdeps: override_dh_install: dh_install --sourcedir=/opt +override_dh_auto_test: override_dh_dwz: From 154991dd86e17ba6d2e6de6ab1512e16a8f3b251 Mon Sep 17 00:00:00 2001 From: Vitor Bandeira Date: Thu, 14 Nov 2024 16:42:16 +0000 Subject: [PATCH 25/32] gha: drop deb action Signed-off-by: Vitor Bandeira --- .../github-actions-build-deb-package.yml | 87 ------------------- 1 file changed, 87 deletions(-) delete mode 100644 .github/workflows/github-actions-build-deb-package.yml diff --git a/.github/workflows/github-actions-build-deb-package.yml b/.github/workflows/github-actions-build-deb-package.yml deleted file mode 100644 index 741c832fe8b..00000000000 --- a/.github/workflows/github-actions-build-deb-package.yml +++ /dev/null @@ -1,87 +0,0 @@ -name: Build deb packages - -on: - push: - branches: - - master - -jobs: - builder: - name: 'Build .deb package' - strategy: - fail-fast: false - matrix: - os: ['debian11', 'ubuntu20.04', 'ubuntu22.04'] - runs-on: ubuntu-latest - container: - image: openroad/${{ matrix.os }}-dev - - steps: - - uses: actions/checkout@v4 - with: - submodules: true - - - name: Set release version - id: set_version - run: | - git config --global --add safe.directory '*' - echo "RELEASE_VERSION=$(git describe | sed 's/v//')" >> $GITHUB_ENV - echo "RELEASE_DATE=$(date +'%Y-%m-%d')" >> $GITHUB_ENV - - - name: Build package - run: | - ./debian/create-changelog.sh ${{ env.RELEASE_VERSION }} - debuild --preserve-env --preserve-envvar=PATH -B - mkdir -p artifacts - mv ../openroad_* artifacts - - - name: Rename artifact - id: artifact - run: | - cd artifacts - file=$(realpath openroad_*.deb) - artifact=$(echo $file | sed 's/\.\([^.]*\)$/-${{ matrix.os }}.\1/') - mv $file $artifact - echo "file=$(realpath $artifact)" >> $GITHUB_OUTPUT - name=$(basename $artifact) - name=${name%.deb} - echo "name=$name" >> $GITHUB_OUTPUT - - - name: Upload workflow artifact - uses: actions/upload-artifact@v3 - with: - name: ${{ steps.artifact.outputs.name }} - path: ${{ steps.artifact.outputs.file }} - - - name: Get release info - uses: cardinalby/git-get-release-action@v1 - env: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - with: - tag_name: ${{ env.RELEASE_VERSION }} - release_name: ${{ env.RELEASE_VERSION }} - doNotFailIfNotFound: true - id: release_info - - - name: Create release if not exists - if: steps.release_info.outputs.name == '' - uses: actions/create-release@v1 - env: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - with: - tag_name: ${{ env.RELEASE_VERSION }} - release_name: ${{ env.RELEASE_VERSION }} - body: "Release ${{ env.RELEASE_VERSION }} on ${{ env.RELEASE_DATE }}" - id: create_release - - - name: Upload Release Asset - id: upload-release-asset - uses: actions/upload-release-asset@v1 - env: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - with: - upload_url: ${{ steps.release_info.outputs.upload_url || steps.create_release.outputs.upload_url }} - asset_path: ${{ steps.artifact.outputs.file }} - asset_name: ${{ steps.artifact.outputs.name }}-${{ env.RELEASE_VERSION }}.deb - asset_content_type: application/octet-stream - From 064cfbca572075edc21ead0ce64c3f7eb82597b8 Mon Sep 17 00:00:00 2001 From: Vitor Bandeira Date: Thu, 7 Nov 2024 17:18:11 +0000 Subject: [PATCH 26/32] etc: add docker fromImage checker There can be a case where we want to build a "builder" or "binary" docker image, but the "dev" image needed is not available yet. With this change the script should generate the dependency images automatically. Signed-off-by: Vitor Bandeira --- etc/DockerHelper.sh | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/etc/DockerHelper.sh b/etc/DockerHelper.sh index de32db17aff..a726c547668 100755 --- a/etc/DockerHelper.sh +++ b/etc/DockerHelper.sh @@ -8,6 +8,7 @@ baseDir="$(pwd)" # docker hub organization/user from where to pull/push images org=openroad depsPrefixesFile="/etc/openroad_deps_prefixes.txt" +args=("${@}") _help() { cat < /dev/null 2>&1; then + echo "Image '${fromImage}' exists locally." + else + echo "Image '${fromImage}' does not exist locally. Attempting to pull..." + # Try to pull the image + if docker pull "${fromImage}"; then + echo "Successfully pulled '${fromImage}'." + else + echo "Unable to pull '${fromImage}'. Attempting to build..." + # Build the image using the createImage command + newArgs="" + newTarget="" + for arg in "${args[@]}"; do + # Check if the argument matches -target=builder + if [[ "${arg}" == "-target=builder" ]]; then + newTarget="dev" + elif [[ "${arg}" == "-target=binary" ]]; then + newTarget="builder" + else + newArgs+=" ${arg}" + fi + done + if [[ "${newTarget}" == "" ]]; then + echo "Error" + exit 1 + fi + newArgs+=" -target=${newTarget}" + createImage="$0 ${newArgs}" + echo "Running: ${createImage}" + if ${createImage}; then + echo "Successfully built '${newTarget}' image." + else + echo "Failed to build '${newTarget}' needed for '${target}' target." + return 1 + fi + fi + fi + set -e + exit 42 +} + _create() { + if [[ "${target}" != "dev" ]]; then + _checkFromImage + fi echo "Create docker image ${imagePath} using ${file}" eval docker buildx build \ --file "${file}" \ From 22230f6c9810761f68e19264fac0762f7ff89748 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Fri, 22 Nov 2024 00:13:53 +0000 Subject: [PATCH 27/32] drt: make global beginDebugIter & debugMazeIter const Developer can modify/un-const as needed locally. Signed-off-by: Matt Liberty --- src/drt/src/dr/FlexDR_maze.cpp | 2 +- src/drt/src/dr/FlexGridGraph_maze.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drt/src/dr/FlexDR_maze.cpp b/src/drt/src/dr/FlexDR_maze.cpp index 1e1eb6ff909..13b1b878cb7 100644 --- a/src/drt/src/dr/FlexDR_maze.cpp +++ b/src/drt/src/dr/FlexDR_maze.cpp @@ -43,7 +43,7 @@ namespace drt { namespace gtl = boost::polygon; -int beginDebugIter = std::numeric_limits::max(); +const int beginDebugIter = std::numeric_limits::max(); static frSquaredDistance pt2boxDistSquare(const Point& pt, const Rect& box) { diff --git a/src/drt/src/dr/FlexGridGraph_maze.cpp b/src/drt/src/dr/FlexGridGraph_maze.cpp index 76c2818ca85..5c37d10f5d3 100644 --- a/src/drt/src/dr/FlexGridGraph_maze.cpp +++ b/src/drt/src/dr/FlexGridGraph_maze.cpp @@ -32,7 +32,7 @@ namespace drt { -int debugMazeIter = std::numeric_limits::max(); +const int debugMazeIter = std::numeric_limits::max(); void FlexGridGraph::expand(FlexWavefrontGrid& currGrid, const frDirEnum& dir, const FlexMazeIdx& dstMazeIdx1, From 251cd3bb17cce10fea495903d19680a97e6b4999 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Fri, 22 Nov 2024 00:55:02 +0000 Subject: [PATCH 28/32] odb: properly swig collections of dbTech Fixes #6207 Signed-off-by: Matt Liberty --- src/odb/src/swig/common/containers.i | 1 + 1 file changed, 1 insertion(+) diff --git a/src/odb/src/swig/common/containers.i b/src/odb/src/swig/common/containers.i index cf71d25b01e..30494ad8dba 100644 --- a/src/odb/src/swig/common/containers.i +++ b/src/odb/src/swig/common/containers.i @@ -31,6 +31,7 @@ WRAP_DB_CONTAINER(odb::dbSBox) WRAP_DB_CONTAINER(odb::dbSWire) WRAP_DB_CONTAINER(odb::dbSite) WRAP_DB_CONTAINER(odb::dbTarget) +WRAP_DB_CONTAINER(odb::dbTech) WRAP_DB_CONTAINER(odb::dbTechLayer) WRAP_DB_CONTAINER(odb::dbTechLayerArraySpacingRule) WRAP_DB_CONTAINER(odb::dbTechLayerCornerSpacingRule) From afc9df20e369e38de0a5989037e5110fda9d07c7 Mon Sep 17 00:00:00 2001 From: Vitor Bandeira Date: Thu, 21 Nov 2024 12:29:16 +0000 Subject: [PATCH 29/32] etc: add support for rocklinux9 and ubuntu24 Signed-off-by: Vitor Bandeira --- etc/DependencyInstaller.sh | 183 +++++++++++-------------------------- etc/DockerHelper.sh | 27 ++++-- 2 files changed, 71 insertions(+), 139 deletions(-) diff --git a/etc/DependencyInstaller.sh b/etc/DependencyInstaller.sh index 7d0d3ac1f01..a9878c8bfe4 100755 --- a/etc/DependencyInstaller.sh +++ b/etc/DependencyInstaller.sh @@ -16,9 +16,6 @@ _equivalenceDeps() { # yosys yosysPrefix=${PREFIX:-"/usr/local"} if [[ ! $(command -v yosys) || ! $(command -v yosys-config) ]]; then ( - if [[ -f /opt/rh/llvm-toolset-7.0/enable ]]; then - source /opt/rh/llvm-toolset-7.0/enable - fi cd "${baseDir}" git clone --depth=1 -b "${yosysVersion}" --recursive https://github.com/YosysHQ/yosys cd yosys @@ -31,9 +28,6 @@ _equivalenceDeps() { # eqy eqyPrefix=${PREFIX:-"/usr/local"} if ! command -v eqy &> /dev/null; then ( - if [[ -f /opt/rh/llvm-toolset-7.0/enable ]]; then - source /opt/rh/llvm-toolset-7.0/enable - fi cd "${baseDir}" git clone --depth=1 -b "${yosysVersion}" https://github.com/YosysHQ/eqy cd eqy @@ -46,9 +40,6 @@ _equivalenceDeps() { # sby sbyPrefix=${PREFIX:-"/usr/local"} if ! command -v sby &> /dev/null; then ( - if [[ -f /opt/rh/llvm-toolset-7.0/enable ]]; then - source /opt/rh/llvm-toolset-7.0/enable - fi cd "${baseDir}" git clone --depth=1 -b "${yosysVersion}" --recursive https://github.com/YosysHQ/sby cd sby @@ -262,10 +253,10 @@ EOF _installOrTools() { os=$1 - version=$2 + osVersion=$2 arch=$3 - orToolsVersionBig=9.10 - orToolsVersionSmall=${orToolsVersionBig}.4067 + orToolsVersionBig=9.11 + orToolsVersionSmall=${orToolsVersionBig}.4210 rm -rf "${baseDir}" mkdir -p "${baseDir}" @@ -274,7 +265,7 @@ _installOrTools() { # Disable exit on error for 'find' command, as it might return non zero set +euo pipefail - LIST=($(find / -type f -name "libortools.so*" 2>/dev/null)) + LIST=($(find /local* /opt* /lib* /usr* /bin* -type f -name "libortools.so*" 2>/dev/null)) # Bring back exit on error set -euo pipefail # Return if right version of or-tools is installed @@ -295,10 +286,10 @@ _installOrTools() { ${cmakePrefix}/bin/cmake -S. -Bbuild -DBUILD_DEPS:BOOL=ON -DBUILD_EXAMPLES:BOOL=OFF -DBUILD_SAMPLES:BOOL=OFF -DBUILD_TESTING:BOOL=OFF -DCMAKE_INSTALL_PREFIX=${orToolsPath} -DCMAKE_CXX_FLAGS="-w" -DCMAKE_C_FLAGS="-w" ${cmakePrefix}/bin/cmake --build build --config Release --target install -v -j $(nproc) else - if [[ $version == rodete ]]; then - version=11 + if [[ $osVersion == rodete ]]; then + osVersion=11 fi - orToolsFile=or-tools_${arch}_${os}-${version}_cpp_v${orToolsVersionSmall}.tar.gz + orToolsFile=or-tools_${arch}_${os}-${osVersion}_cpp_v${orToolsVersionSmall}.tar.gz eval wget https://github.com/google/or-tools/releases/download/v${orToolsVersionBig}/${orToolsFile} if command -v brew &> /dev/null; then orToolsPath="$(brew --prefix or-tools)" @@ -388,17 +379,12 @@ _installRHELCleanUp() { _installRHELPackages() { arch=amd64 - version=3.1.11.1 + pandocVersion=3.1.11.1 yum -y update - if [[ $(yum repolist | egrep -c "rhel-8-for-x86_64-appstream-rpms") -eq 0 ]]; then - yum -y install http://mirror.centos.org/centos/8-stream/BaseOS/x86_64/os/Packages/centos-gpg-keys-8-6.el8.noarch.rpm - yum -y install http://mirror.centos.org/centos/8-stream/BaseOS/x86_64/os/Packages/centos-stream-repos-8-6.el8.noarch.rpm - rpm --import /etc/pki/rpm-gpg/RPM-GPG-KEY-centosofficial - fi yum -y install tzdata yum -y install redhat-rpm-config rpm-build - yum -y install https://dl.fedoraproject.org/pub/epel/epel-release-latest-8.noarch.rpm + yum -y install https://dl.fedoraproject.org/pub/epel/epel-release-latest-9.noarch.rpm yum -y install \ autoconf \ automake \ @@ -409,11 +395,11 @@ _installRHELPackages() { gdb \ git \ glibc-devel \ - libtool \ libffi-devel \ - llvm7.0 \ - llvm7.0-devel \ - llvm7.0-libs \ + libtool \ + llvm \ + llvm-devel \ + llvm-libs \ make \ pcre-devel \ pcre2-devel \ @@ -424,10 +410,9 @@ _installRHELPackages() { python3-devel \ python3-pip \ qt5-qtbase-devel \ + qt5-qtcharts-devel \ qt5-qtimageformats \ readline \ - readline-devel \ - tcl-devel \ tcl-tclreadline \ tcl-tclreadline-devel \ tcl-thread-devel \ @@ -436,65 +421,14 @@ _installRHELPackages() { zlib-devel yum install -y \ - http://repo.okay.com.mx/centos/8/x86_64/release/bison-3.0.4-10.el8.x86_64.rpm \ - https://forensics.cert.org/centos/cert/7/x86_64/flex-2.6.1-9.el7.x86_64.rpm - - eval wget https://github.com/jgm/pandoc/releases/download/${version}/pandoc-${version}-linux-${arch}.tar.gz - tar xvzf pandoc-${version}-linux-${arch}.tar.gz --strip-components 1 -C /usr/local/ - rm -rf pandoc-${version}-linux-${arch}.tar.gz -} - -_installCentosCleanUp() { - yum clean -y all - rm -rf /var/lib/apt/lists/* -} - -_installCentosPackages() { - yum update -y - yum install -y tzdata - yum groupinstall -y "Development Tools" - if ! command -v lcov &> /dev/null; then - yum install -y http://downloads.sourceforge.net/ltp/lcov-1.14-1.noarch.rpm - fi - if ! command -v yum list installed ius-release &> /dev/null; then - yum install -y https://repo.ius.io/ius-release-el7.rpm - fi - if ! command -v yum list installed epel-release &> /dev/null; then - yum install -y https://dl.fedoraproject.org/pub/epel/epel-release-latest-7.noarch.rpm - fi - yum install -y centos-release-scl - yum install -y \ - devtoolset-8 \ - devtoolset-8-libatomic-devel \ - groff \ - libffi-devel \ - libgomp \ - libstdc++ \ - llvm-toolset-7.0 \ - llvm-toolset-7.0-libomp-devel \ - pandoc \ - pcre-devel \ - pcre2-devel \ - python-devel \ - python36 \ - python36-devel \ - python36-libs \ - python36-pip \ - qt5-qtbase-devel \ - qt5-qtimageformats \ - readline-devel \ - rh-python38-python \ - rh-python38-python-libs \ - rh-python38-python-pip \ - rh-python38-scldevel \ - tcl \ - tcl-devel \ - tcl-tclreadline \ - tcl-tclreadline-devel \ - tcllib \ - wget \ - ccache \ - zlib-devel + https://mirror.stream.centos.org/9-stream/AppStream/x86_64/os/Packages/bison-3.7.4-5.el9.x86_64.rpm \ + https://mirror.stream.centos.org/9-stream/AppStream/x86_64/os/Packages/flex-2.6.4-9.el9.x86_64.rpm \ + https://mirror.stream.centos.org/9-stream/AppStream/x86_64/os/Packages/readline-devel-8.1-4.el9.x86_64.rpm \ + https://rpmfind.net/linux/centos-stream/9-stream/AppStream/x86_64/os/Packages/tcl-devel-8.6.10-7.el9.x86_64.rpm + + eval wget https://github.com/jgm/pandoc/releases/download/${pandocVersion}/pandoc-${pandocVersion}-linux-${arch}.tar.gz + tar xvzf pandoc-${pandocVersion}-linux-${arch}.tar.gz --strip-components 1 -C /usr/local/ + rm -rf pandoc-${pandocVersion}-linux-${arch}.tar.gz } _installOpenSuseCleanUp() { @@ -699,10 +633,12 @@ _installCI() { containerd.io \ docker-buildx-plugin - # Install clang for C++20 support - wget https://apt.llvm.org/llvm.sh - chmod +x llvm.sh - ./llvm.sh 16 all + if _versionCompare ${1} -lt 24.04; then + # Install clang for C++20 support + wget https://apt.llvm.org/llvm.sh + chmod +x llvm.sh + ./llvm.sh 16 all + fi } @@ -873,50 +809,39 @@ case "${platform}" in esac case "${os}" in - "CentOS Linux" ) - if [[ ${CI} == "yes" ]]; then - echo "WARNING: Installing CI dependencies is only supported on Ubuntu 22.04" >&2 - fi - if [[ "${option}" == "base" || "${option}" == "all" ]]; then - _checkIsLocal - _installCentosPackages - _installCentosCleanUp - fi - if [[ "${option}" == "common" || "${option}" == "all" ]]; then - _installCommonDev - _installOrTools "centos" "7" "amd64" - fi - cat <&2 fi @@ -927,7 +852,7 @@ EOF fi if [[ "${option}" == "common" || "${option}" == "all" ]]; then _installCommonDev - _installOrTools "centos" "8" "amd64" + _installOrTools "rockylinux" "9" "amd64" fi ;; "Darwin" ) @@ -962,21 +887,21 @@ To enable GCC-11 you need to run: EOF ;; "Debian GNU/Linux" | "Debian GNU/Linux rodete" ) - version=$(awk -F= '/^VERSION_ID/{print $2}' /etc/os-release | sed 's/"//g') - if [[ -z ${version} ]]; then - version=$(awk -F= '/^VERSION_CODENAME/{print $2}' /etc/os-release | sed 's/"//g') + debianVersion=$(awk -F= '/^VERSION_ID/{print $2}' /etc/os-release | sed 's/"//g') + if [[ -z ${debianVersion} ]]; then + debianVersion=$(awk -F= '/^VERSION_CODENAME/{print $2}' /etc/os-release | sed 's/"//g') fi if [[ ${CI} == "yes" ]]; then echo "WARNING: Installing CI dependencies is only supported on Ubuntu 22.04" >&2 fi if [[ "${option}" == "base" || "${option}" == "all" ]]; then _checkIsLocal - _installDebianPackages "${version}" + _installDebianPackages "${debianVersion}" _installDebianCleanUp fi if [[ "${option}" == "common" || "${option}" == "all" ]]; then _installCommonDev - _installOrTools "debian" "${version}" "amd64" + _installOrTools "debian" "${debianVersion}" "amd64" fi ;; *) diff --git a/etc/DockerHelper.sh b/etc/DockerHelper.sh index a726c547668..e66938fe772 100755 --- a/etc/DockerHelper.sh +++ b/etc/DockerHelper.sh @@ -20,7 +20,9 @@ usage: $0 [CMD] [OPTIONS] push Push the docker image to Docker Hub OPTIONS: - -os=OS_NAME Choose between ubuntu22.04 (default), ubuntu20.04, rhel, opensuse and debian11. + -os=OS_NAME Choose between: + ubuntu20.04, ubuntu22.04 (default), + ubuntu24.04, rockylinux9, opensuse or debian11. -target=TARGET Choose target for the Docker image: 'dev': os + packages to compile app 'builder': os + packages to compile app + @@ -58,14 +60,17 @@ _setup() { "ubuntu22.04") osBaseImage="ubuntu:22.04" ;; + "ubuntu24.04") + osBaseImage="ubuntu:24.04" + ;; "opensuse") osBaseImage="opensuse/leap" ;; "debian11") osBaseImage="debian:bullseye" ;; - "rhel") - osBaseImage="redhat/ubi8" + "rockylinux9") + osBaseImage="rockylinux:9" ;; *) echo "Target OS ${os} not supported" >&2 @@ -91,7 +96,7 @@ _setup() { imageName="${IMAGE_NAME_OVERRIDE:-"${imageName}-${compiler}"}" ;; "dev" ) - fromImage="${FROM_IMAGE_OVERRIDE:-$osBaseImage}" + fromImage="${FROM_IMAGE_OVERRIDE:-${osBaseImage}}" context="etc" buildArgs="-save-deps-prefixes=${depsPrefixesFile}" if [[ "${isLocal}" == "yes" ]]; then @@ -100,7 +105,7 @@ _setup() { if [[ "${equivalenceDeps}" == "yes" ]]; then buildArgs="${buildArgs} -eqy" fi - if [[ "$CI" == "yes" ]]; then + if [[ "${CI}" == "yes" ]]; then buildArgs="${buildArgs} -ci" fi if [[ "${buildArgs}" != "" ]]; then @@ -181,12 +186,14 @@ _checkFromImage() { fi fi set -e - exit 42 } _create() { - if [[ "${target}" != "dev" ]]; then - _checkFromImage + if [[ "${target}" == "binary" ]]; then + _checkFromImage "builder" + fi + if [[ "${target}" == "builder" ]]; then + _checkFromImage "dev" fi echo "Create docker image ${imagePath} using ${file}" eval docker buildx build \ @@ -308,9 +315,9 @@ while [ "$#" -gt 0 ]; do done if [[ "${numThreads}" == "-1" ]]; then - if [[ "$OSTYPE" == "linux-gnu"* ]]; then + if [[ "${OSTYPE}" == "linux-gnu"* ]]; then numThreads=$(nproc --all) - elif [[ "$OSTYPE" == "darwin"* ]]; then + elif [[ "${OSTYPE}" == "darwin"* ]]; then numThreads=$(sysctl -n hw.ncpu) else numThreads=2 From ac5ec6f595763434b2325c3fdc3142ef72c87036 Mon Sep 17 00:00:00 2001 From: Vitor Bandeira Date: Fri, 1 Nov 2024 20:32:39 +0000 Subject: [PATCH 30/32] ci: move deb to Jenkins Signed-off-by: Vitor Bandeira --- Jenkinsfile | 70 +++++++++++++++++++++++++++++++++++----- debian/move-artifacts.sh | 14 ++++++++ 2 files changed, 76 insertions(+), 8 deletions(-) create mode 100755 debian/move-artifacts.sh diff --git a/Jenkinsfile b/Jenkinsfile index 701d4d243ed..2b0dd428e53 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -4,7 +4,7 @@ def baseTests(String image) { Map base_tests = [failFast: false]; base_tests['Unit Tests CTest'] = { - docker.image(image).inside('--user=root --privileged -v /var/run/docker.sock:/var/run/docker.sock') { + withDockerContainer(args: '-u root', image: image) { stage('Setup CTest') { echo 'Nothing to be done.'; } @@ -27,7 +27,7 @@ def baseTests(String image) { base_tests['Unit Tests Tcl'] = { node { - docker.image(image).inside('--user=root --privileged -v /var/run/docker.sock:/var/run/docker.sock') { + withDockerContainer(args: '-u root', image: image) { stage('Setup Tcl Tests') { sh label: 'Configure git', script: "git config --system --add safe.directory '*'"; checkout scm; @@ -68,7 +68,7 @@ def baseTests(String image) { flow_tests.each { current_test -> base_tests["Flow Test - ${current_test}"] = { node { - docker.image(image).inside('--user=root --privileged -v /var/run/docker.sock:/var/run/docker.sock') { + withDockerContainer(args: '-u root', image: image) { stage("Setup ${current_test}") { sh label: 'Configure git', script: "git config --system --add safe.directory '*'"; checkout scm; @@ -104,7 +104,7 @@ def getParallelTests(String image) { 'Build without GUI': { node { - docker.image(image).inside('--user=root --privileged -v /var/run/docker.sock:/var/run/docker.sock') { + withDockerContainer(args: '-u root', image: image) { stage('Setup no-GUI Build') { echo "Build without GUI"; sh label: 'Configure git', script: "git config --system --add safe.directory '*'"; @@ -121,7 +121,7 @@ def getParallelTests(String image) { 'Build without Test': { node { - docker.image(image).inside('--user=root --privileged -v /var/run/docker.sock:/var/run/docker.sock') { + withDockerContainer(args: '-u root', image: image) { stage('Setup no-test Build') { echo "Build without Tests"; sh label: 'Configure git', script: "git config --system --add safe.directory '*'"; @@ -148,7 +148,7 @@ def getParallelTests(String image) { 'Unit Tests Ninja': { node { - docker.image(image).inside('--user=root --privileged -v /var/run/docker.sock:/var/run/docker.sock') { + withDockerContainer(args: '-u root', image: image) { stage('Setup Ninja Tests') { sh label: 'Configure git', script: "git config --system --add safe.directory '*'"; checkout scm; @@ -174,7 +174,7 @@ def getParallelTests(String image) { 'Compile with C++20': { node { - docker.image(image).inside('--user=root --privileged -v /var/run/docker.sock:/var/run/docker.sock') { + withDockerContainer(args: '-u root', image: image) { stage('Setup C++20 Compile') { sh label: 'Configure git', script: "git config --system --add safe.directory '*'"; checkout scm; @@ -188,6 +188,41 @@ def getParallelTests(String image) { ]; + deb_os = [ + [name: 'Ubuntu 20.04' , image: 'openroad/ubuntu20.04-dev'], + [name: 'Ubuntu 22.04' , image: 'openroad/ubuntu22.04-dev'], + [name: 'Debian 11' , image: 'openroad/debian11-dev'] + ]; + + deb_os.each { os -> + ret["Build .deb - ${os.name}"] = { + node { + stage('Setup and Build') { + sh label: 'Pull latest image', script: "docker pull ${os.image}:latest"; + withDockerContainer(args: '-u root', image: "${os.image}") { + sh label: 'Configure git', script: "git config --system --add safe.directory '*'"; + checkout([ + $class: 'GitSCM', + branches: [[name: scm.branches[0].name]], + doGenerateSubmoduleConfigurations: false, + extensions: [ + [$class: 'CloneOption', noTags: false], + [$class: 'SubmoduleOption', recursiveSubmodules: true] + ], + submoduleCfg: [], + userRemoteConfigs: scm.userRemoteConfigs + ]); + def version = sh(script: 'git describe | sed s,^v,,', returnStdout: true).trim(); + sh label: 'Create Changelog', script: "./debian/create-changelog.sh ${version}"; + sh label: 'Run debuild', script: 'debuild --preserve-env --preserve-envvar=PATH -B -j$(nproc)'; + sh label: 'Move generated files', script: "./debian/move-artifacts.sh ${version}"; + archiveArtifacts artifacts: '*' + "${version}" + '*'; + } + } + } + } + } + return ret; } @@ -196,7 +231,26 @@ node { checkout scm; } def DOCKER_IMAGE; - stage('Build and Push Docker Image') { + stage('Build, Test and Push Docker Image') { + Map build_docker_images = [failFast: false]; + test_os = [ + [name: 'Ubuntu 20.04', base: 'ubuntu:20.04', image: 'ubuntu20.04'], + [name: 'Ubuntu 22.04', base: 'ubuntu:22.04', image: 'ubuntu22.04'], + [name: 'Ubuntu 24.04', base: 'ubuntu:24.04', image: 'ubuntu24.04'], + [name: 'RockyLinux 9', base: 'rockylinux:9', image: 'rockylinux9'], + [name: 'Debian 11', base: 'debian:11', image: 'debian11'] + ]; + test_os.each { os -> + build_docker_images["Test Installer - ${os.name}"] = { + node { + checkout scm; + sh label: 'Build Docker image', script: "./etc/DockerHelper.sh create -target=builder -os=${os.image}"; + sh label: 'Test Docker image', script: "./etc/DockerHelper.sh test -target=builder -os=${os.image}"; + dockerPush("${os.image}", 'openroad'); + } + } + } + parallel(build_docker_images); DOCKER_IMAGE = dockerPush('ubuntu22.04', 'openroad'); echo "Docker image is ${DOCKER_IMAGE}"; } diff --git a/debian/move-artifacts.sh b/debian/move-artifacts.sh new file mode 100755 index 00000000000..16b0d332a3b --- /dev/null +++ b/debian/move-artifacts.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash + +if [[ $# -ne 1 ]]; then + echo "Error: This script requires exactly one argument." + echo "usage: $0 " + exit 1 +fi + +for file in ../*${1}*; do + base_name=$(basename "$file") + name="${base_name%.*}" + ext="${base_name##*.}" + mv "$file" "${name}-${os_name}.${ext}" +done From 6bc8226fb0c067b17fbbaa3a953493d85877714f Mon Sep 17 00:00:00 2001 From: Vitor Bandeira Date: Thu, 21 Nov 2024 16:49:38 +0000 Subject: [PATCH 31/32] ci: save deb artifacts with os name Signed-off-by: Vitor Bandeira --- Jenkinsfile | 9 ++++----- debian/move-artifacts.sh | 6 +++--- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 2b0dd428e53..f535ef204c8 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -189,11 +189,10 @@ def getParallelTests(String image) { ]; deb_os = [ - [name: 'Ubuntu 20.04' , image: 'openroad/ubuntu20.04-dev'], - [name: 'Ubuntu 22.04' , image: 'openroad/ubuntu22.04-dev'], - [name: 'Debian 11' , image: 'openroad/debian11-dev'] + [name: 'Ubuntu 20.04' , artifact_name: 'ubuntu-20.04', image: 'openroad/ubuntu20.04-dev'], + [name: 'Ubuntu 22.04' , artifact_name: 'ubuntu-22.04', image: 'openroad/ubuntu22.04-dev'], + [name: 'Debian 11' , artifact_name: 'debian11', image: 'openroad/debian11-dev'] ]; - deb_os.each { os -> ret["Build .deb - ${os.name}"] = { node { @@ -215,7 +214,7 @@ def getParallelTests(String image) { def version = sh(script: 'git describe | sed s,^v,,', returnStdout: true).trim(); sh label: 'Create Changelog', script: "./debian/create-changelog.sh ${version}"; sh label: 'Run debuild', script: 'debuild --preserve-env --preserve-envvar=PATH -B -j$(nproc)'; - sh label: 'Move generated files', script: "./debian/move-artifacts.sh ${version}"; + sh label: 'Move generated files', script: "./debian/move-artifacts.sh ${version} ${os.artifact_name}"; archiveArtifacts artifacts: '*' + "${version}" + '*'; } } diff --git a/debian/move-artifacts.sh b/debian/move-artifacts.sh index 16b0d332a3b..d2329ab9b9a 100755 --- a/debian/move-artifacts.sh +++ b/debian/move-artifacts.sh @@ -1,8 +1,8 @@ #!/usr/bin/env bash -if [[ $# -ne 1 ]]; then +if [[ $# -ne 2 ]]; then echo "Error: This script requires exactly one argument." - echo "usage: $0 " + echo "usage: $0 " exit 1 fi @@ -10,5 +10,5 @@ for file in ../*${1}*; do base_name=$(basename "$file") name="${base_name%.*}" ext="${base_name##*.}" - mv "$file" "${name}-${os_name}.${ext}" + mv "$file" "${name}-${2}.${ext}" done From edfac6e95c5eefdcf6b8932e124c3a12b818f91b Mon Sep 17 00:00:00 2001 From: Vitor Bandeira Date: Thu, 21 Nov 2024 18:01:31 +0000 Subject: [PATCH 32/32] ci: only run deb installer on master Signed-off-by: Vitor Bandeira --- Jenkinsfile | 58 +++++++++++++++++++++++++++-------------------------- 1 file changed, 30 insertions(+), 28 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index f535ef204c8..8f47f404aab 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -188,34 +188,36 @@ def getParallelTests(String image) { ]; - deb_os = [ - [name: 'Ubuntu 20.04' , artifact_name: 'ubuntu-20.04', image: 'openroad/ubuntu20.04-dev'], - [name: 'Ubuntu 22.04' , artifact_name: 'ubuntu-22.04', image: 'openroad/ubuntu22.04-dev'], - [name: 'Debian 11' , artifact_name: 'debian11', image: 'openroad/debian11-dev'] - ]; - deb_os.each { os -> - ret["Build .deb - ${os.name}"] = { - node { - stage('Setup and Build') { - sh label: 'Pull latest image', script: "docker pull ${os.image}:latest"; - withDockerContainer(args: '-u root', image: "${os.image}") { - sh label: 'Configure git', script: "git config --system --add safe.directory '*'"; - checkout([ - $class: 'GitSCM', - branches: [[name: scm.branches[0].name]], - doGenerateSubmoduleConfigurations: false, - extensions: [ - [$class: 'CloneOption', noTags: false], - [$class: 'SubmoduleOption', recursiveSubmodules: true] - ], - submoduleCfg: [], - userRemoteConfigs: scm.userRemoteConfigs - ]); - def version = sh(script: 'git describe | sed s,^v,,', returnStdout: true).trim(); - sh label: 'Create Changelog', script: "./debian/create-changelog.sh ${version}"; - sh label: 'Run debuild', script: 'debuild --preserve-env --preserve-envvar=PATH -B -j$(nproc)'; - sh label: 'Move generated files', script: "./debian/move-artifacts.sh ${version} ${os.artifact_name}"; - archiveArtifacts artifacts: '*' + "${version}" + '*'; + if (env.BRANCH_NAME == 'master') { + deb_os = [ + [name: 'Ubuntu 20.04' , artifact_name: 'ubuntu-20.04', image: 'openroad/ubuntu20.04-dev'], + [name: 'Ubuntu 22.04' , artifact_name: 'ubuntu-22.04', image: 'openroad/ubuntu22.04-dev'], + [name: 'Debian 11' , artifact_name: 'debian11', image: 'openroad/debian11-dev'] + ]; + deb_os.each { os -> + ret["Build .deb - ${os.name}"] = { + node { + stage('Setup and Build') { + sh label: 'Pull latest image', script: "docker pull ${os.image}:latest"; + withDockerContainer(args: '-u root', image: "${os.image}") { + sh label: 'Configure git', script: "git config --system --add safe.directory '*'"; + checkout([ + $class: 'GitSCM', + branches: [[name: scm.branches[0].name]], + doGenerateSubmoduleConfigurations: false, + extensions: [ + [$class: 'CloneOption', noTags: false], + [$class: 'SubmoduleOption', recursiveSubmodules: true] + ], + submoduleCfg: [], + userRemoteConfigs: scm.userRemoteConfigs + ]); + def version = sh(script: 'git describe | sed s,^v,,', returnStdout: true).trim(); + sh label: 'Create Changelog', script: "./debian/create-changelog.sh ${version}"; + sh label: 'Run debuild', script: 'debuild --preserve-env --preserve-envvar=PATH -B -j$(nproc)'; + sh label: 'Move generated files', script: "./debian/move-artifacts.sh ${version} ${os.artifact_name}"; + archiveArtifacts artifacts: '*' + "${version}" + '*'; + } } } }