fmax_notes.org

CPU

Configuration	FMax	LUTs	critical path stage
Default(master)	35.47	26732	s1
execute disabled	52.88	11443	ready path from write->form_pop
execute disabled, extra s2m pipes	57.63	14488	hazard detector
no hazard detector	75.81	11510	decode mux
execute, s2m pipes, no retime	15.26		WTF
no hazard detector, no retime	79.48	11267	decoder
better hazard detector	65.2		form_pop somehow?
enable adder	64.5	18579	hazard?
enable logical	60.3	19268
enable comparator	50.5	20601	s1
enable shifter	32.26	31388	s1
just shifter	34.8	28257	s1
no shifter, popcnt and zcnt	49.5
branch	51.9
full cpu without shifter, retimed	55.6
full cpu with shifter, retimed	45.7
pipelined shifter	47.34
pipelined shifter with partial shift (2 bits)	51.98
pipelined shifter with partial shift (3 bits)	40.1
pipelined shifter with partial shift (1 bits)	47.9
pipelined shifter with partial shift (2 bits) no retiming	52.22
pipelined shifter with partial shift (3 bits) no retiming	48
pipelined shifter with partial shift (1 bits) no retiming	51.89
full cpu, pipelined partial 1 bits	47.8
full cpu, pipelined partial 0 bits	48.9
full cpu, pipelined partial 2 bits	46.74		popcnt
just popcnt	58.04
just popcnt	61.59
full cpu, pipelined partial 0 bits	47.2		s2 adder
full cpu, pipelined partial 1 bits	47.0		hazard
post rebase	47.59		comparator
no comparator	52.54		hazard? not sure
pipelined comparator	49.08		branch
pipelined add,cmp,logic, nothing else	66.91
pipelined comparator, no branch	55.79		shifter
pipelined comparator, no branch, no shifter	57.54		hazard?
pipelined branch	49.25		???
pipelined branch, nothing else	53 MHz		??? form pop?
register flush signal in s2m pipe	61.24
pipelined branch, new s2m pipe, everything but shifter	52.56
just branch, no s2m pipes	47.68		??? form pop?
^, s2m pipe before s2	47.06
^, s2m pipe before hazard, write, and ldst	58.31
^, enable logical, add, cmp, popcnt	55.04
^,with shifter	47.79		strangely not shifter, decode
disable shifter, enable shifter part of decoder	53.47		???
just adder	53
Just logical	54
Just logical, no stage 3	65.33
just adder, fixed stage3	64.49
adder, logic, fixed s3	63.69
adder, logic, branch, fixed s3	54.24
new hazard detector	55.97
old branch unit	55.97
move all additions to stage 1	60.85
evenly split additions between both stages	61.98
decouple ctr 0 calculation	52.11		ldst
decouple ctr 0 calculation better	53.38		hazard

Hazard Detector

Configuration	FMAx
Stock, 8 stages	44.99
Bitvector and reduc	58.00
before	55.74
slot set based	62.43

Before

ltp: 20 size: 5986

After

ltp: 19 size: 4854

Stage 3 ltp

Start	41
reduce number of comparisons	37
use top bit of the result and orR	7

Decoder size

Before	9074
after sorting	11656
greater than sorting	8105
greater than sorting reversed	11712
less than sorting reversed	10559

Sorting opcodes doesn’t provide very much benefit it seems