From fa5fa3879612310b40d2ebb4d336a7bcc82bd0a2 Mon Sep 17 00:00:00 2001 From: Rachit Garg Date: Sun, 22 Jan 2023 18:30:32 +0100 Subject: [PATCH 1/2] Add Ultra96-V2 --- src/finn/util/basic.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 4aba87216c..60f2446f59 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -34,6 +34,7 @@ # mapping from PYNQ board names to FPGA part names pynq_part_map = dict() pynq_part_map["Ultra96"] = "xczu3eg-sbva484-1-e" +pynq_part_map["Ultra96-V2"] = "xczu3eg-sbva484-1-i" pynq_part_map["Pynq-Z1"] = "xc7z020clg400-1" pynq_part_map["Pynq-Z2"] = "xc7z020clg400-1" pynq_part_map["ZCU102"] = "xczu9eg-ffvb1156-2-e" @@ -46,6 +47,7 @@ pynq_native_port_width["Pynq-Z1"] = 64 pynq_native_port_width["Pynq-Z2"] = 64 pynq_native_port_width["Ultra96"] = 128 +pynq_native_port_width["Ultra96-V2"] = 128 pynq_native_port_width["ZCU102"] = 128 pynq_native_port_width["ZCU104"] = 128 pynq_native_port_width["ZCU111"] = 128 From 6c0f869e36857546af5b3f24c833a89800ffd53a Mon Sep 17 00:00:00 2001 From: Rachit Garg Date: Sun, 22 Jan 2023 18:34:08 +0100 Subject: [PATCH 2/2] Added Ultra96-V2 --- src/finn/transformation/fpgadataflow/templates.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py index 78bcdea0d7..757b1382c3 100644 --- a/src/finn/transformation/fpgadataflow/templates.py +++ b/src/finn/transformation/fpgadataflow/templates.py @@ -120,6 +120,9 @@ } elseif {$BOARD == "Ultra96"} { set_property board_part avnet.com:ultra96v1:part0:1.2 [current_project] set ZYNQ_TYPE "zynq_us+" +} elseif {$BOARD == "Ultra96-V2"} { + set_property board_part avnet.com:ultra96v2:part0:1.2 [current_project] + set ZYNQ_TYPE "zynq_us+" } elseif {$BOARD == "Pynq-Z2"} { set ZYNQ_TYPE "zynq_7000" set_property board_part tul.com.tw:pynq-z2:part0:1.0 [current_project]