From 690b72c3681dd8d5c754016db97146097f0bacab Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 20 Dec 2024 12:52:41 -0800 Subject: [PATCH] directly generate enums --- examples/nxp/lpc/src/blinky.zig | 8 +- port/espressif/esp/src/hals/esp32-c3/uart.zig | 2 +- .../rp2xxx/src/hal/clocks/common.zig | 10 +-- port/raspberrypi/rp2xxx/src/hal/dma.zig | 12 ++- port/raspberrypi/rp2xxx/src/hal/gpio.zig | 10 +-- port/raspberrypi/rp2xxx/src/hal/i2c.zig | 78 +++++++++---------- port/raspberrypi/rp2xxx/src/hal/random.zig | 4 +- port/raspberrypi/rp2xxx/src/hal/usb.zig | 8 +- tools/regz/src/gen.zig | 76 ++++++------------ 9 files changed, 89 insertions(+), 119 deletions(-) diff --git a/examples/nxp/lpc/src/blinky.zig b/examples/nxp/lpc/src/blinky.zig index 328d6370..7371dd5c 100644 --- a/examples/nxp/lpc/src/blinky.zig +++ b/examples/nxp/lpc/src/blinky.zig @@ -21,10 +21,10 @@ const all_mask = led_mask[0] | led_mask[1] | led_mask[2] | led_mask[3]; pub fn main() !void { conn.PINSEL3.modify(.{ - .P1_18 = .{ .value = .GPIO_P1 }, - .P1_20 = .{ .value = .GPIO_P1 }, - .P1_21 = .{ .value = .GPIO_P1 }, - .P1_23 = .{ .value = .GPIO_P1 }, + .P1_18 = .GPIO_P1, + .P1_20 = .GPIO_P1, + .P1_21 = .GPIO_P1, + .P1_23 = .GPIO_P1, }); const p1 = &gpio[1]; diff --git a/port/espressif/esp/src/hals/esp32-c3/uart.zig b/port/espressif/esp/src/hals/esp32-c3/uart.zig index b5cfcab0..480cf7e9 100644 --- a/port/espressif/esp/src/hals/esp32-c3/uart.zig +++ b/port/espressif/esp/src/hals/esp32-c3/uart.zig @@ -12,6 +12,6 @@ pub fn write(comptime index: comptime_int, slice: []const u8) void { const r = reg(index); for (slice) |c| { while (r.STATUS.read().TXFIFO_CNT > 8) {} - r.FIFO.raw = c; + r.FIFO = @enumFromInt(c); } } diff --git a/port/raspberrypi/rp2xxx/src/hal/clocks/common.zig b/port/raspberrypi/rp2xxx/src/hal/clocks/common.zig index e9776a56..347003d1 100644 --- a/port/raspberrypi/rp2xxx/src/hal/clocks/common.zig +++ b/port/raspberrypi/rp2xxx/src/hal/clocks/common.zig @@ -24,19 +24,19 @@ pub const xosc = struct { } pub fn init() void { if (xosc_freq <= 15_000_000 and xosc_freq >= 1_000_000) { - XOSC.CTRL.modify(.{ .FREQ_RANGE = .{ .value = .@"1_15MHZ" } }); + XOSC.CTRL.modify(.{ .FREQ_RANGE = .@"1_15MHZ" }); } else if (xosc_freq <= 30_000_000 and xosc_freq >= 10_000_000) { - XOSC.CTRL.modify(.{ .FREQ_RANGE = .{ .value = .@"10_30MHZ" } }); + XOSC.CTRL.modify(.{ .FREQ_RANGE = .@"10_30MHZ" }); } else if (xosc_freq <= 60_000_000 and xosc_freq >= 25_000_000) { - XOSC.CTRL.modify(.{ .FREQ_RANGE = .{ .value = .@"25_60MHZ" } }); + XOSC.CTRL.modify(.{ .FREQ_RANGE = .@"25_60MHZ" }); } else if (xosc_freq <= 100_000_000 and xosc_freq >= 40_000_000) { - XOSC.CTRL.modify(.{ .FREQ_RANGE = .{ .value = .@"40_100MHZ" } }); + XOSC.CTRL.modify(.{ .FREQ_RANGE = .@"40_100MHZ" }); } else { unreachable; } XOSC.STARTUP.modify(.{ .DELAY = startup_delay_value }); - XOSC.CTRL.modify(.{ .ENABLE = .{ .value = .ENABLE } }); + XOSC.CTRL.modify(.{ .ENABLE = .ENABLE }); // wait for xosc startup to complete: while (XOSC.STATUS.read().STABLE == 0) {} diff --git a/port/raspberrypi/rp2xxx/src/hal/dma.zig b/port/raspberrypi/rp2xxx/src/hal/dma.zig index b7f96294..11d77d51 100644 --- a/port/raspberrypi/rp2xxx/src/hal/dma.zig +++ b/port/raspberrypi/rp2xxx/src/hal/dma.zig @@ -106,13 +106,11 @@ pub const Channel = enum(u4) { regs.trans_count = count; regs.ctrl_trig.modify(.{ .EN = @intFromBool(config.enable), - .DATA_SIZE = .{ - .value = switch (config.transfer_size_bytes) { - 1 => @TypeOf(regs.ctrl_trig.read().DATA_SIZE.value).SIZE_BYTE, - 2 => .SIZE_HALFWORD, - 4 => .SIZE_WORD, - else => unreachable, - }, + .DATA_SIZE = switch (config.transfer_size_bytes) { + 1 => @TypeOf(regs.ctrl_trig.read().DATA_SIZE.value).SIZE_BYTE, + 2 => .SIZE_HALFWORD, + 4 => .SIZE_WORD, + else => unreachable, }, .INCR_READ = @intFromBool(config.read_increment), .INCR_WRITE = @intFromBool(config.write_increment), diff --git a/port/raspberrypi/rp2xxx/src/hal/gpio.zig b/port/raspberrypi/rp2xxx/src/hal/gpio.zig index b4971131..caf1c83b 100644 --- a/port/raspberrypi/rp2xxx/src/hal/gpio.zig +++ b/port/raspberrypi/rp2xxx/src/hal/gpio.zig @@ -471,11 +471,11 @@ pub const Pin = enum(u6) { const regs = gpio.get_regs(); regs.ctrl.modify(.{ - .FUNCSEL = .{ .value = function }, - .OUTOVER = .{ .value = .normal }, - .INOVER = .{ .value = .normal }, - .IRQOVER = .{ .value = .normal }, - .OEOVER = .{ .value = .normal }, + .FUNCSEL = function, + .OUTOVER = .normal, + .INOVER = .normal, + .IRQOVER = .normal, + .OEOVER = .normal, }); switch (cpu) { diff --git a/port/raspberrypi/rp2xxx/src/hal/i2c.zig b/port/raspberrypi/rp2xxx/src/hal/i2c.zig index ddc09b05..e67d2240 100644 --- a/port/raspberrypi/rp2xxx/src/hal/i2c.zig +++ b/port/raspberrypi/rp2xxx/src/hal/i2c.zig @@ -217,18 +217,18 @@ pub const I2C = enum(u1) { inline fn disable(i2c: I2C) void { i2c.get_regs().IC_ENABLE.write(.{ - .ENABLE = .{ .value = .DISABLED }, - .ABORT = .{ .value = .DISABLE }, - .TX_CMD_BLOCK = .{ .value = .NOT_BLOCKED }, + .ENABLE = .DISABLED, + .ABORT = .DISABLE, + .TX_CMD_BLOCK = .NOT_BLOCKED, .padding = 0, }); } inline fn enable(i2c: I2C) void { i2c.get_regs().IC_ENABLE.write(.{ - .ENABLE = .{ .value = .ENABLED }, - .ABORT = .{ .value = .DISABLE }, - .TX_CMD_BLOCK = .{ .value = .NOT_BLOCKED }, + .ENABLE = .ENABLED, + .ABORT = .DISABLE, + .TX_CMD_BLOCK = .NOT_BLOCKED, .padding = 0, }); } @@ -244,15 +244,15 @@ pub const I2C = enum(u1) { i2c.disable(); const regs = i2c.get_regs(); regs.IC_CON.write(.{ - .MASTER_MODE = .{ .value = .ENABLED }, - .SPEED = .{ .value = .FAST }, - .IC_RESTART_EN = .{ .value = if (config.repeated_start) .ENABLED else .DISABLED }, - .IC_SLAVE_DISABLE = .{ .value = .SLAVE_DISABLED }, - .TX_EMPTY_CTRL = .{ .value = .ENABLED }, - .IC_10BITADDR_SLAVE = .{ .raw = 0 }, - .IC_10BITADDR_MASTER = .{ .raw = 0 }, - .STOP_DET_IFADDRESSED = .{ .raw = 0 }, - .RX_FIFO_FULL_HLD_CTRL = .{ .raw = 0 }, + .MASTER_MODE = .ENABLED, + .SPEED = .FAST, + .IC_RESTART_EN = if (config.repeated_start) .ENABLED else .DISABLED, + .IC_SLAVE_DISABLE = .SLAVE_DISABLED, + .TX_EMPTY_CTRL = .ENABLED, + .IC_10BITADDR_SLAVE = @enumFromInt(0), + .IC_10BITADDR_MASTER = @enumFromInt(0), + .STOP_DET_IFADDRESSED = @enumFromInt(0), + .RX_FIFO_FULL_HLD_CTRL = @enumFromInt(0), .STOP_DET_IF_MASTER_ACTIVE = 0, .padding = 0, }); @@ -263,8 +263,8 @@ pub const I2C = enum(u1) { // DREQ signal control regs.IC_DMA_CR.write(.{ - .RDMAE = .{ .value = .ENABLED }, - .TDMAE = .{ .value = .ENABLED }, + .RDMAE = .ENABLED, + .TDMAE = .ENABLED, .padding = 0, }); @@ -308,8 +308,8 @@ pub const I2C = enum(u1) { i2c.disable(); i2c.get_regs().IC_TAR.write(.{ .IC_TAR = @intFromEnum(addr), - .GC_OR_START = .{ .value = .GENERAL_CALL }, - .SPECIAL = .{ .value = .DISABLED }, + .GC_OR_START = .GENERAL_CALL, + .SPECIAL = .DISABLED, .padding = 0, }); i2c.enable(); @@ -324,10 +324,10 @@ pub const I2C = enum(u1) { // IC_CLR_TX_ABRT register always reads as 0. _ = regs.IC_CLR_TX_ABRT.read(); - if (abort_reason.ABRT_7B_ADDR_NOACK.value == .ACTIVE) { + if (abort_reason.ABRT_7B_ADDR_NOACK == .ACTIVE) { // Address byte wasn't acknowledged by any targets on the bus return TransactionError.DeviceNotPresent; - } else if (abort_reason.ABRT_TXDATA_NOACK.value == .ABRT_TXDATA_NOACK_GENERATED) { + } else if (abort_reason.ABRT_TXDATA_NOACK == .ABRT_TXDATA_NOACK_GENERATED) { // Address byte was acknowledged, but a data byte wasn't return TransactionError.NoAcknowledge; } else if (abort_reason.TX_FLUSH_CNT > 0) { @@ -353,7 +353,7 @@ pub const I2C = enum(u1) { // condition here? If so, additional code would be needed here // to take care of the abort. // As far as I can tell from the datasheet, no, this is not possible. - while (regs.IC_RAW_INTR_STAT.read().STOP_DET.value == .INACTIVE) { + while (regs.IC_RAW_INTR_STAT.read().STOP_DET == .INACTIVE) { hw.tight_loop_contents(); if (deadline.is_reached()) break; @@ -400,12 +400,12 @@ pub const I2C = enum(u1) { var iter = write_vec.iterator(); while (iter.next_element()) |element| { regs.IC_DATA_CMD.write(.{ - .RESTART = .{ .raw = 0 }, - .STOP = .{ .raw = @intFromBool(element.last) }, - .CMD = .{ .value = .WRITE }, + .RESTART = @enumFromInt(0), + .STOP = @enumFromInt(@intFromBool(element.last)), + .CMD = .WRITE, .DAT = element.value, - .FIRST_DATA_BYTE = .{ .value = .INACTIVE }, + .FIRST_DATA_BYTE = .INACTIVE, .padding = 0, }); // If an abort occurrs, the TX/RX FIFO is flushed, and subsequent writes to IC_DATA_CMD @@ -427,7 +427,7 @@ pub const I2C = enum(u1) { // Waits until everything in the TX FIFO is either successfully transmitted, or flushed // due to an abort. This functions because of TX_EMPTY_CTRL being enabled in apply(). - while (regs.IC_RAW_INTR_STAT.read().TX_EMPTY.value == .INACTIVE) { + while (regs.IC_RAW_INTR_STAT.read().TX_EMPTY == .INACTIVE) { if (deadline.is_reached()) { timed_out = true; break; @@ -479,12 +479,12 @@ pub const I2C = enum(u1) { var iter = read_vec.iterator(); while (iter.next_element_ptr()) |element| { regs.IC_DATA_CMD.write(.{ - .RESTART = .{ .raw = 0 }, - .STOP = .{ .raw = @intFromBool(element.last) }, - .CMD = .{ .value = .READ }, + .RESTART = @enumFromInt(0), + .STOP = @enumFromInt(@intFromBool(element.last)), + .CMD = .READ, .DAT = 0, - .FIRST_DATA_BYTE = .{ .value = .INACTIVE }, + .FIRST_DATA_BYTE = .INACTIVE, .padding = 0, }); @@ -551,12 +551,12 @@ pub const I2C = enum(u1) { var write_iter = write_vec.iterator(); send_loop: while (write_iter.next_element()) |element| { regs.IC_DATA_CMD.write(.{ - .RESTART = .{ .raw = 0 }, - .STOP = .{ .raw = 0 }, - .CMD = .{ .value = .WRITE }, + .RESTART = @enumFromInt(0), + .STOP = @enumFromInt(0), + .CMD = .WRITE, .DAT = element.value, - .FIRST_DATA_BYTE = .{ .value = .INACTIVE }, + .FIRST_DATA_BYTE = .INACTIVE, .padding = 0, }); // If an abort occurrs, the TX/RX FIFO is flushed, and subsequent writes to IC_DATA_CMD @@ -583,12 +583,12 @@ pub const I2C = enum(u1) { var read_iter = read_vec.iterator(); recv_loop: while (read_iter.next_element_ptr()) |element| { regs.IC_DATA_CMD.write(.{ - .RESTART = .{ .raw = @intFromBool(element.first) }, - .STOP = .{ .raw = @intFromBool(element.last) }, - .CMD = .{ .value = .READ }, + .RESTART = @enumFromInt(@intFromBool(element.first)), + .STOP = @enumFromInt(@intFromBool(element.last)), + .CMD = .READ, .DAT = 0, - .FIRST_DATA_BYTE = .{ .value = .INACTIVE }, + .FIRST_DATA_BYTE = .INACTIVE, .padding = 0, }); diff --git a/port/raspberrypi/rp2xxx/src/hal/random.zig b/port/raspberrypi/rp2xxx/src/hal/random.zig index e3117127..f0e5a610 100644 --- a/port/raspberrypi/rp2xxx/src/hal/random.zig +++ b/port/raspberrypi/rp2xxx/src/hal/random.zig @@ -70,8 +70,8 @@ pub const Ascon = struct { fn rosc(buffer: []u8) void { const rosc_state = peripherals.ROSC.CTRL.read().ENABLE.value; // Enable the ROSC so it generates random bits for us - peripherals.ROSC.CTRL.modify(.{ .ENABLE = .{ .value = .ENABLE } }); - defer peripherals.ROSC.CTRL.modify(.{ .ENABLE = .{ .value = rosc_state } }); + peripherals.ROSC.CTRL.modify(.{ .ENABLE = .ENABLE }); + defer peripherals.ROSC.CTRL.modify(.{ .ENABLE = rosc_state }); var i: usize = 0; while (i < buffer.len) : (i += 1) { diff --git a/port/raspberrypi/rp2xxx/src/hal/usb.zig b/port/raspberrypi/rp2xxx/src/hal/usb.zig index 7c4d5693..a30cf272 100644 --- a/port/raspberrypi/rp2xxx/src/hal/usb.zig +++ b/port/raspberrypi/rp2xxx/src/hal/usb.zig @@ -159,7 +159,7 @@ pub fn F(comptime config: UsbConfig) type { peripherals.PLL_USB.PRIM.modify(.{ .POSTDIV1 = 5, .POSTDIV2 = 5 }); peripherals.PLL_USB.PWR.modify(.{ .POSTDIVPD = 0 }); // Switch usbclk to be derived from PLLUSB - peripherals.CLOCKS.CLK_USB_CTRL.modify(.{ .AUXSRC = .{ .value = .clksrc_pll_usb } }); + peripherals.CLOCKS.CLK_USB_CTRL.modify(.{ .AUXSRC = .clksrc_pll_usb }); // We now have the stable 48MHz reference clock required for USB: } @@ -179,7 +179,7 @@ pub fn F(comptime config: UsbConfig) type { rp2xxx_endpoints.get_buf_ctrl(@intCast(i), .In).?.write_raw(0); rp2xxx_endpoints.get_buf_ctrl(@intCast(i), .Out).?.write_raw(0); } - + // Mux the controller to the onboard USB PHY. I was surprised that there are // alternatives to this, but, there are. peripherals.USB.USB_MUXING.modify(.{ @@ -432,7 +432,7 @@ pub fn F(comptime config: UsbConfig) type { ep.endpoint_control.?.modify(.{ .ENABLE = 1, .INTERRUPT_PER_BUFF = 1, - .ENDPOINT_TYPE = .{ .raw = ep.transfer_type.as_number() }, + .ENDPOINT_TYPE = @enumFromInt(ep.transfer_type.as_number()), .BUFFER_ADDRESS = rp2xxx_buffers.data_offset(ep.data_buffer), }); } @@ -505,4 +505,4 @@ pub fn F(comptime config: UsbConfig) type { }; } }; -} \ No newline at end of file +} diff --git a/tools/regz/src/gen.zig b/tools/regz/src/gen.zig index 3bd86f3e..16a2961a 100644 --- a/tools/regz/src/gen.zig +++ b/tools/regz/src/gen.zig @@ -772,45 +772,35 @@ fn write_fields( if (e.name) |enum_name| { if (e.struct_id == null or try db.enum_has_name_collision(enum_id)) { try writer.print( - \\{}: packed union {{ - \\ raw: u{}, - \\ value: enum(u{}) {{ + \\{}: enum(u{}) {{ \\ , .{ std.zig.fmtId(field.name), e.size_bits, - e.size_bits, }); try write_enum_fields(db, arena, &e, writer); - try writer.writeAll("},\n},\n"); + try writer.writeAll("},\n"); } else { try writer.print( - \\{}: packed union {{ - \\ raw: u{}, - \\ value: {}, - \\}}, + \\{}: {}, \\ , .{ std.zig.fmtId(field.name), - field.size_bits, std.zig.fmtId(enum_name), }); } } else { try writer.print( - \\{}: packed union {{ - \\ raw: u{}, - \\ value: enum(u{}) {{ + \\{}: enum(u{}) {{ \\ , .{ std.zig.fmtId(field.name), e.size_bits, - e.size_bits, }); try write_enum_fields(db, arena, &e, writer); - try writer.writeAll("},\n},\n"); + try writer.writeAll("},\n"); } } else { try writer.print("{}: u{},\n", .{ std.zig.fmtId(field.name), field.get_size_bits() }); @@ -1038,10 +1028,7 @@ test "gen.field with named enum" { \\ }; \\ \\ TEST_REGISTER: mmio.Mmio(packed struct(u8) { - \\ TEST_FIELD: packed union { - \\ raw: u4, - \\ value: TEST_ENUM, - \\ }, + \\ TEST_FIELD: TEST_ENUM, \\ padding: u4, \\ }), \\ }; @@ -1067,13 +1054,10 @@ test "gen.field with anonymous enum" { \\ pub const peripherals = struct { \\ pub const TEST_PERIPHERAL = extern struct { \\ TEST_REGISTER: mmio.Mmio(packed struct(u8) { - \\ TEST_FIELD: packed union { - \\ raw: u4, - \\ value: enum(u4) { - \\ TEST_ENUM_FIELD1 = 0x0, - \\ TEST_ENUM_FIELD2 = 0x1, - \\ _, - \\ }, + \\ TEST_FIELD: enum(u4) { + \\ TEST_ENUM_FIELD1 = 0x0, + \\ TEST_ENUM_FIELD2 = 0x1, + \\ _, \\ }, \\ padding: u4, \\ }), @@ -1423,21 +1407,15 @@ test "gen.name collisions in enum name cause them to be anonymous" { \\ pub const peripherals = struct { \\ pub const TEST_PERIPHERAL = extern struct { \\ TEST_REGISTER: mmio.Mmio(packed struct(u8) { - \\ TEST_FIELD1: packed union { - \\ raw: u4, - \\ value: enum(u4) { - \\ TEST_ENUM_FIELD1 = 0x0, - \\ TEST_ENUM_FIELD2 = 0x1, - \\ _, - \\ }, + \\ TEST_FIELD1: enum(u4) { + \\ TEST_ENUM_FIELD1 = 0x0, + \\ TEST_ENUM_FIELD2 = 0x1, + \\ _, \\ }, - \\ TEST_FIELD2: packed union { - \\ raw: u4, - \\ value: enum(u4) { - \\ TEST_ENUM_FIELD1 = 0x0, - \\ TEST_ENUM_FIELD2 = 0x1, - \\ _, - \\ }, + \\ TEST_FIELD2: enum(u4) { + \\ TEST_ENUM_FIELD1 = 0x0, + \\ TEST_ENUM_FIELD2 = 0x1, + \\ _, \\ }, \\ }), \\ }; @@ -1465,12 +1443,9 @@ test "gen.pick one enum field in value collisions" { \\ pub const peripherals = struct { \\ pub const TEST_PERIPHERAL = extern struct { \\ TEST_REGISTER: mmio.Mmio(packed struct(u8) { - \\ TEST_FIELD: packed union { - \\ raw: u4, - \\ value: enum(u4) { - \\ TEST_ENUM_FIELD1 = 0x0, - \\ _, - \\ }, + \\ TEST_FIELD: enum(u4) { + \\ TEST_ENUM_FIELD1 = 0x0, + \\ _, \\ }, \\ padding: u4, \\ }), @@ -1497,12 +1472,9 @@ test "gen.pick one enum field in name collisions" { \\ pub const peripherals = struct { \\ pub const TEST_PERIPHERAL = extern struct { \\ TEST_REGISTER: mmio.Mmio(packed struct(u8) { - \\ TEST_FIELD: packed union { - \\ raw: u4, - \\ value: enum(u4) { - \\ TEST_ENUM_FIELD1 = 0x0, - \\ _, - \\ }, + \\ TEST_FIELD: enum(u4) { + \\ TEST_ENUM_FIELD1 = 0x0, + \\ _, \\ }, \\ padding: u4, \\ }),