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MpcForMG5001.mdwn

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GP4020 MPC Settings for the SigTec MG5001 Receiver

  • Assumes the GP4020 is being clocked at the default rate of 20MHz (50ns/instr.)

GP4020 Memory Area 1 (0x0000 0000 - 1FFF FFFF)

  • Purpose: External ROM
  • Device: Atmel [[AM29LV200BB]]-70EC: 2Mb (256KB) CMOS Flash, Boot code sector architecture: bottom, 70ns, 48pin TSOP, 0 - 70 degC
    • Valid address range: 0x0000 0000 - 0x003F FFFF (0x6000 0000 - 0x0603F FFFF if swapped with Memory Area 4; see below)
  • Configuration Register Address: 0xE000 8000
  • Default (reset) value: 0xFF00 0035
  • Here's what I think the settings should be:
Bit Field name Bit Position On Reset Value Setting Description
Access Waits 31:28 1111 0020 70ns Flash access time
Stop Waits 27:24 1111 0000 30ns off-bus time
Reserved 23:08 0..0 0..0
Configuration Mode 07:06 00 00 Stay in the old "Butterfly" config mode
Wait Control 05 1 1 Wait states controlled by MPC, not SWAIT signal.
Read-Only Status 04 1 1 Disable writes; looks like ROM
Sub-memory Write Status 03 0 0 Disable sub-memory width writes
Access Type 02 1 1 Memory access type
Data Size 01:00 01 01 Half word memory device

(Note: 03:00 = 0101 implies a 16bit memory without 8 bit writes)

  • And the hex value for this is: 0x0000 0035

GP4020 Memory Area 2 (0x2000 0000 - 0x3FFF FFFF)

  • Purpose: External RAM
  • Device: ISSI [[IS61LV12816]]-12T: 2Mb (256KB) CMOS static RAM, 12ns, 44pin TSOP-2, 0 - 70 deg C
    • Valid address range: 0x2000 0000 - 0x203F FFFF
  • Configuration Register Address: 0xE000 8004
  • Default (reset) value: 0xFF00 0034
  • Here's what I think the settings should be:
Bit Field name Bit Position On Reset Value Setting Description
Access Waits 31:28 1111 0000 12ns SRAM access time
Stop Waits 27:24 1111 0000 12ns off-bus time
Reserved 23:08 0..0 0..0
Configuration Mode 07:06 00 01 Go to new "firefly" config mode
Wait Control 05 1 1 Wait states controlled by MPC, not SWAIT signal.
Read-Only Status 04 1 0 Not read-only
Sub-memory Write Status 03 0 1 Access Sub Memory Type 0
Access Type 02 1 0 Access Sub Memory Type 1
Data Size 01:00 00 01 Data Size = 16 bits

(Note: 03:00 = 1001 implies a 16bit memory with 8 bit writes)

  • And the hex value for this is: 0x0000 0069

GP4020 Memory Area 3 (0x4000 0000 - 0x5FFF FFFF)

  • Purpose: Internal Peripherals (and possibly external devices as well)
  • Device: CORR, 1PPS, SCG, RTC, and PCL peripherals
  • Configuration Register Address: 0xE000 8008
  • Default (reset) value: 0xFF00 0034
  • Page 111 of GP4020 data sheet basically says to set this register to 0x3303 306E

GP4020 Memory Area 4 (0x6000 0000 - 0x7FFF FFFF)

  • Purpose: Internal RAM
  • Device: High speed internal 8KB (32 x 2KB) SRAM
    • Valid address range: 0x6000 0000 - 0x6000 1FFF (0x0000 0000 - 0x0000 1FFF if swapped with Memory Area 1; see below)
  • Configuration Register Address: 0xE000 800C
  • Default (reset) value: 0xFF00 0034
  • Here's what I think the settings should be:
Bit Field name Bit Position On Reset Value Setting Description
Access Waits 31:28 1111 0000 No wait states
Stop Waits 27:24 1111 0000 No wait states
Reserved 23:08 0..0 0..0
Configuration Mode 07:06 00 01 Go to new config mode
Wait Control 05 1 1 Wait states controlled by MPC, not SWAIT signal.
Read-Only Status 04 1 0 Enabled writes
Sub-memory Write Status 03 0 1 Enable sub-memory width writes
Access Type 02 1 1 Memory access type
Data Size 01:00 00 10 32 bit or any sub-width

(Note: 03:00 = 1110 implies a 32bit memory with 8 and 16 bit writes)

  • And the hex value for this is: 0x0000 006E

Swapping Memory Area 1 and 4

You can swap Memory Area 1 (the slow Flash) with Memory Area 4 (the fast internal SRAM) in order to speed up interrupts (since the interrupt vector table is located clear to 0x0000 0000). To do this, set bit 0 in the System Configuartion Register which on the GP4020 is address 0xE000 2004. To undo the swap, just clear the bit. Be sure not to affect the bits in the SCR, which control interrupt and DMA priority levels. For more information see page 24 in the [[FireFly]] MF1 Core Design Document.

WARNING: On page 16 of that same document it mentions that the MPC bits might need to be changed if the Memory Area 1 / Memory Area 4 swap is done - is this true? If so, if this isn't done it'll screw everything up on the transition.

Old notes, misc:

20bit address (SADD[0-19]), 16bits data (SDATA[0-15]) and control lines:

  • NSCS[0,1,2A] chip selects
  • NSWE[0-1] write enable (2 so you can use 8bit devices)
  • NSOE Output Enable (usual "CS" line)
  • SWAIT INPUT: waot isgnal
  • NSUB "Select Upper Byte": selects which byte to write to for byte operations

Area 1 - External ROM (or Internal boot loader if MULTI_FNIO is high) 2 - External RAM 3 - Internal peripherals (CORR, 1PPS, SCG, RTC, PCL) and possibly external RAM 4 - Internal SRAM (8KB)

Firefly Internal control lines: NCS[0-3] (Not Chip Select) External Chip selects: NSCS[0,1,2A] (Not System? Chip Select)