From e99c680c7a82b480ce91f4728af21f6f4fd77bd6 Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Tue, 29 Aug 2023 15:07:04 -0700
Subject: [PATCH] Create a base class for process technologies.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
---
 vlsiffra/tech/asap7.py    |  5 ++-
 vlsiffra/tech/base.py     | 89 +++++++++++++++++++++++++++++++++++++++
 vlsiffra/tech/gf180mcu.py |  5 ++-
 vlsiffra/tech/none.py     |  5 ++-
 vlsiffra/tech/sky130.py   |  6 ++-
 5 files changed, 102 insertions(+), 8 deletions(-)
 create mode 100644 vlsiffra/tech/base.py

diff --git a/vlsiffra/tech/asap7.py b/vlsiffra/tech/asap7.py
index 7f519ea..e21e781 100644
--- a/vlsiffra/tech/asap7.py
+++ b/vlsiffra/tech/asap7.py
@@ -1,7 +1,8 @@
-from amaranth import Elaboratable, Instance, Signal
+from amaranth import Instance, Signal
+from .base import Process
 
 
-class ASAP7Process(Elaboratable):
+class ASAP7Process(Process):
     def _PoweredInstance(self, *args, **kwargs):
         if self._powered:
             kwargs.update({
diff --git a/vlsiffra/tech/base.py b/vlsiffra/tech/base.py
new file mode 100644
index 0000000..29049db
--- /dev/null
+++ b/vlsiffra/tech/base.py
@@ -0,0 +1,89 @@
+from amaranth import Elaboratable
+
+# The following shell command can be used to discover the usage;
+# grep -R '_generate_'  | sed -e's/: */:/' -e's/(.*/(/' | sort | uniq | less
+
+
+class Process(Elaboratable):
+    """ Base class for process technologies. """
+
+    def _PoweredInstance(self, *args, **kwargs):
+        pass
+
+    # Standard cells used in *both* `adders.py` and `multipliers.py`
+
+    def _generate_and(self, a, b, o):
+        """2 input AND gate.
+
+        Used by both `adders.py` and `multipliers.py`.
+        """
+        raise NotImplementedError()
+
+    def _generate_xor(self, a, b, o):
+        """2 input XOR gate.
+
+        Used by both `adders.py` and `multipliers.py`.
+        """
+        raise NotImplementedError()
+
+    def _generate_full_adder(self, a, b, carry_in, sum_out, carry_out, name=None):
+        """Full adder.
+
+        Used by both `adders.py` and `multipliers.py`.
+        """
+        raise NotImplementedError()
+
+    def _generate_half_adder(self, a, b, sum_out, carry_out, name=None):
+        """Half adder.
+
+        Used by both `adders.py` and `multipliers.py`.
+        """
+        raise NotImplementedError()
+
+    # Standard cells used only in adders
+    def _generate_ao21(self, a1, a2, b1, o):
+        """2-input AND into first input of 2-input OR.
+
+        Used by `adders.py`.
+        """
+        raise NotImplementedError()
+
+    # Standard cells used only in `multipliers.py`
+    def _generate_inv(self, a, o):
+        """1-bit inverter.
+
+        Used by `multipliers.py`.
+        """
+        raise NotImplementedError()
+
+    def _generate_ao22(self, a1, a2, b1, b2, o):
+        """2-input AND into both inputs of 2-input OR.
+
+        Used by `multipliers.py`.
+        """
+        raise NotImplementedError()
+
+    def _generate_ao32(self, a1, a2):
+        """3-input AND into first input, and 2-input AND into 2nd input of 2-input OR.
+
+        Used by `multipliers.py`.
+        """
+        raise NotImplementedError()
+
+    def _generate_ao33(self, a1, a2, a3, b1, b2, b3, o):
+        """3-input AND into both inputs of 2-input OR.
+
+        Optional, a `oai33` cell can be provided instead.
+
+        Used by `multipliers.py`.
+        """
+        raise AttributeError()
+
+    def _generate_oai33(self, a1, a2, a3, b1, b2, b3, o):
+        """3-input AND into both inputs of 2-input OR.
+
+        Optional, can be provided instead of the `ao33` cell.
+
+        Used by `multipliers.py`.
+        """
+        raise AttributeError()
diff --git a/vlsiffra/tech/gf180mcu.py b/vlsiffra/tech/gf180mcu.py
index d9d9521..322eb7d 100644
--- a/vlsiffra/tech/gf180mcu.py
+++ b/vlsiffra/tech/gf180mcu.py
@@ -1,7 +1,8 @@
-from amaranth import Elaboratable, Instance, Signal
+from amaranth import Instance, Signal
+from .base import Process
 
 
-class GF180MCUProcess(Elaboratable):
+class GF180MCUProcess(Process):
     def _PoweredInstance(self, *args, **kwargs):
         if self._powered:
             kwargs.update({
diff --git a/vlsiffra/tech/none.py b/vlsiffra/tech/none.py
index 201fde8..f794808 100644
--- a/vlsiffra/tech/none.py
+++ b/vlsiffra/tech/none.py
@@ -1,7 +1,8 @@
-from amaranth import Elaboratable, Cat
+from amaranth import Cat
+from .base import Process
 
 
-class NoneProcess(Elaboratable):
+class NoneProcess(Process):
     def _generate_and(self, a, b, o):
         self.m.d.comb += o.eq(a & b)
 
diff --git a/vlsiffra/tech/sky130.py b/vlsiffra/tech/sky130.py
index c127865..f6b9e33 100644
--- a/vlsiffra/tech/sky130.py
+++ b/vlsiffra/tech/sky130.py
@@ -1,4 +1,6 @@
-from amaranth import Elaboratable, Instance
+from amaranth import Instance
+from .base import Process
+
 
 """
 Skywater's 130nm process technology with Google open source PDK found at
@@ -13,7 +15,7 @@
 """
 
 
-class SKY130Process(Elaboratable):
+class SKY130Process(Process):
     LIBRARY = None
 
     def _PoweredInstance(self, *args, **kwargs):