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/* Generated by Yosys 0.25+83 (git sha1 755b753e1, aarch64-apple-darwin20.2-clang 10.0.0-4ubuntu1 -fPIC -Os) */
/* top = 1 */
/* src = "d42_qilins_sevenseg/src/wrapper.v:2.9-12.18" */
module d42_qilins_sevenseg(io_in, io_out);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire _34_;
wire _35_;
wire _36_;
wire _37_;
wire _38_;
wire _39_;
wire _40_;
wire _41_;
wire _42_;
wire _43_;
wire _44_;
/* src = "d42_qilins_sevenseg/src/wrapper.v:3.26-3.31" */
input [13:0] io_in;
wire [13:0] io_in;
/* src = "d42_qilins_sevenseg/src/wrapper.v:4.27-4.33" */
output [13:0] io_out;
wire [13:0] io_out;
/* hdlname = "mchip gate10 in" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:53.16-53.18|d42_qilins_sevenseg/src/wokwi.v:117.12-120.4" */
wire \mchip.gate10.in ;
/* hdlname = "mchip gate11 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:121.12-125.4" */
wire \mchip.gate11.b ;
/* hdlname = "mchip gate15 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:136.12-140.4" */
wire \mchip.gate15.a ;
/* hdlname = "mchip gate16 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:141.12-145.4" */
wire \mchip.gate16.a ;
/* hdlname = "mchip gate17 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:146.12-150.4" */
wire \mchip.gate17.a ;
/* hdlname = "mchip gate17 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:146.12-150.4" */
wire \mchip.gate17.b ;
/* hdlname = "mchip gate20 out" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:28.17-28.20|d42_qilins_sevenseg/src/wokwi.v:161.11-165.4" */
wire \mchip.gate20.out ;
/* hdlname = "mchip gate22 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:171.12-175.4" */
wire \mchip.gate22.a ;
/* hdlname = "mchip gate24 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:181.12-185.4" */
wire \mchip.gate24.b ;
/* hdlname = "mchip gate25 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:186.12-190.4" */
wire \mchip.gate25.b ;
/* hdlname = "mchip gate26 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:191.12-195.4" */
wire \mchip.gate26.a ;
/* hdlname = "mchip gate27 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:196.12-200.4" */
wire \mchip.gate27.b ;
/* hdlname = "mchip gate28 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:201.12-205.4" */
wire \mchip.gate28.a ;
/* hdlname = "mchip gate28 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:201.12-205.4" */
wire \mchip.gate28.b ;
/* hdlname = "mchip gate34 out" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:28.17-28.20|d42_qilins_sevenseg/src/wokwi.v:231.11-235.4" */
wire \mchip.gate34.out ;
/* hdlname = "mchip gate36 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:246.12-250.4" */
wire \mchip.gate36.b ;
/* hdlname = "mchip gate37 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:251.12-255.4" */
wire \mchip.gate37.a ;
/* hdlname = "mchip gate38 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:256.12-260.4" */
wire \mchip.gate38.a ;
/* hdlname = "mchip gate39 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:261.12-265.4" */
wire \mchip.gate39.a ;
/* hdlname = "mchip gate45 out" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:28.17-28.20|d42_qilins_sevenseg/src/wokwi.v:291.11-295.4" */
wire \mchip.gate45.out ;
/* hdlname = "mchip gate47 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:301.12-305.4" */
wire \mchip.gate47.b ;
/* hdlname = "mchip gate48 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:306.12-310.4" */
wire \mchip.gate48.b ;
/* hdlname = "mchip gate49 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:311.12-315.4" */
wire \mchip.gate49.b ;
/* hdlname = "mchip gate50 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:316.12-320.4" */
wire \mchip.gate50.a ;
/* hdlname = "mchip gate53 out" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:28.17-28.20|d42_qilins_sevenseg/src/wokwi.v:331.11-335.4" */
wire \mchip.gate53.out ;
/* hdlname = "mchip gate57 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:351.12-355.4" */
wire \mchip.gate57.b ;
/* hdlname = "mchip gate58 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:356.12-360.4" */
wire \mchip.gate58.b ;
/* hdlname = "mchip gate59 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:361.12-365.4" */
wire \mchip.gate59.a ;
/* hdlname = "mchip gate60 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:366.12-370.4" */
wire \mchip.gate60.b ;
/* hdlname = "mchip gate61 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:371.12-375.4" */
wire \mchip.gate61.a ;
/* hdlname = "mchip gate61 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:371.12-375.4" */
wire \mchip.gate61.b ;
/* hdlname = "mchip gate63 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:381.12-385.4" */
wire \mchip.gate63.a ;
/* hdlname = "mchip gate68 out" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:28.17-28.20|d42_qilins_sevenseg/src/wokwi.v:401.11-405.4" */
wire \mchip.gate68.out ;
/* hdlname = "mchip gate69 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:411.12-415.4" */
wire \mchip.gate69.a ;
/* hdlname = "mchip gate7 in" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:53.16-53.18|d42_qilins_sevenseg/src/wokwi.v:105.12-108.4" */
wire \mchip.gate7.in ;
/* hdlname = "mchip gate70 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:416.12-420.4" */
wire \mchip.gate70.a ;
/* hdlname = "mchip gate70 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:416.12-420.4" */
wire \mchip.gate70.b ;
/* hdlname = "mchip gate71 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:421.12-425.4" */
wire \mchip.gate71.a ;
/* hdlname = "mchip gate71 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:421.12-425.4" */
wire \mchip.gate71.b ;
/* hdlname = "mchip gate74 out" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:28.17-28.20|d42_qilins_sevenseg/src/wokwi.v:436.11-440.4" */
wire \mchip.gate74.out ;
/* hdlname = "mchip gate75 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:441.12-445.4" */
wire \mchip.gate75.b ;
/* hdlname = "mchip gate77 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:451.12-455.4" */
wire \mchip.gate77.b ;
/* hdlname = "mchip gate78 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:456.12-460.4" */
wire \mchip.gate78.a ;
/* hdlname = "mchip gate79 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:461.12-465.4" */
wire \mchip.gate79.a ;
/* hdlname = "mchip gate8 in" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:53.16-53.18|d42_qilins_sevenseg/src/wokwi.v:109.12-112.4" */
wire \mchip.gate8.in ;
/* hdlname = "mchip gate80 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:466.12-470.4" */
wire \mchip.gate80.a ;
/* hdlname = "mchip gate80 b" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:18.16-18.17|d42_qilins_sevenseg/src/wokwi.v:466.12-470.4" */
wire \mchip.gate80.b ;
/* hdlname = "mchip gate83 out" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:28.17-28.20|d42_qilins_sevenseg/src/wokwi.v:481.11-485.4" */
wire \mchip.gate83.out ;
/* hdlname = "mchip gate85 a" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:17.16-17.17|d42_qilins_sevenseg/src/wokwi.v:491.12-495.4" */
wire \mchip.gate85.a ;
/* hdlname = "mchip gate85 out" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:19.17-19.20|d42_qilins_sevenseg/src/wokwi.v:491.12-495.4" */
wire \mchip.gate85.out ;
/* hdlname = "mchip gate9 in" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/cells.v:53.16-53.18|d42_qilins_sevenseg/src/wokwi.v:113.12-116.4" */
wire \mchip.gate9.in ;
/* hdlname = "mchip io_in" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:6.15-6.20" */
/* unused_bits = "4 5 6 7" */
wire [7:0] \mchip.io_in ;
/* hdlname = "mchip io_out" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:7.16-7.22" */
wire [7:0] \mchip.io_out ;
/* hdlname = "mchip net1" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:9.8-9.12" */
wire \mchip.net1 ;
/* hdlname = "mchip net10" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:18.8-18.13" */
wire \mchip.net10 ;
/* hdlname = "mchip net11" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:19.8-19.13" */
wire \mchip.net11 ;
/* hdlname = "mchip net12" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:20.8-20.13" */
wire \mchip.net12 ;
/* hdlname = "mchip net13" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:21.8-21.13" */
wire \mchip.net13 ;
/* hdlname = "mchip net14" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:22.8-22.13" */
wire \mchip.net14 ;
/* hdlname = "mchip net2" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:10.8-10.12" */
wire \mchip.net2 ;
/* hdlname = "mchip net3" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:11.8-11.12" */
wire \mchip.net3 ;
/* hdlname = "mchip net4" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:12.8-12.12" */
wire \mchip.net4 ;
/* hdlname = "mchip net5" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:13.8-13.12" */
wire \mchip.net5 ;
/* hdlname = "mchip net6" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:14.8-14.12" */
wire \mchip.net6 ;
/* hdlname = "mchip net7" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:15.8-15.12" */
wire \mchip.net7 ;
/* hdlname = "mchip net8" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:16.8-16.12" */
wire \mchip.net8 ;
/* hdlname = "mchip net9" */
/* src = "d42_qilins_sevenseg/src/wrapper.v:7.44-10.14|d42_qilins_sevenseg/src/wokwi.v:17.8-17.12" */
wire \mchip.net9 ;
assign _00_ = io_in[2] | ~(io_in[0]);
assign _01_ = ~io_in[3];
assign _02_ = io_in[2] & io_in[1];
assign _03_ = io_in[1] & ~(io_in[2]);
assign _04_ = io_in[3] ? _03_ : _02_;
assign _05_ = ~(io_in[1] | io_in[0]);
assign _06_ = io_in[2] & ~(io_in[1]);
assign _07_ = io_in[3] ? _06_ : _05_;
assign _08_ = ~(_07_ | _04_);
assign \mchip.gate68.out = ~(_08_ & _00_);
assign _09_ = io_in[0] & ~(io_in[1]);
assign _10_ = io_in[1] & ~(io_in[0]);
assign _11_ = io_in[3] & ~(io_in[2]);
assign _12_ = _11_ | _10_;
assign _13_ = io_in[3] & ~(io_in[0]);
assign _14_ = ~(io_in[2] | io_in[0]);
assign _15_ = _14_ | _13_;
assign _16_ = _15_ | _12_;
assign \mchip.gate53.out = _16_ | _09_;
assign _17_ = ~(io_in[1] | io_in[3]);
assign _18_ = ~(io_in[2] | io_in[1]);
assign _19_ = io_in[3] & ~(_00_);
assign _20_ = _19_ | _18_;
assign _21_ = io_in[2] & ~(io_in[0]);
assign _22_ = io_in[3] ? _21_ : _14_;
assign _23_ = _22_ | _20_;
assign \mchip.gate45.out = _23_ | _17_;
assign _24_ = _17_ | _02_;
assign _25_ = io_in[0] ? _01_ : io_in[2];
assign _26_ = io_in[0] | ~(io_in[1]);
assign _27_ = io_in[3] & ~(_26_);
assign _28_ = _09_ & ~(io_in[2]);
assign _29_ = _28_ | _27_;
assign _30_ = _29_ | _25_;
assign \mchip.gate34.out = _30_ | _24_;
assign _31_ = io_in[2] & io_in[0];
assign _32_ = io_in[1] ? _01_ : io_in[0];
assign _33_ = _32_ | _31_;
assign _34_ = ~(io_in[2] | io_in[3]);
assign _35_ = _10_ & ~(io_in[2]);
assign _36_ = _35_ | _34_;
assign \mchip.gate20.out = _36_ | _33_;
assign \mchip.gate85.out = io_in[0] & ~(_18_);
assign _37_ = io_in[0] & io_in[3];
assign _38_ = io_in[2] & ~(io_in[3]);
assign _39_ = ~(_38_ | _09_);
assign _40_ = io_in[2] ? io_in[1] : _26_;
assign _41_ = ~(_40_ & _39_);
assign \mchip.gate83.out = _41_ | _37_;
assign _42_ = io_in[1] & io_in[0];
assign _43_ = _42_ | _31_;
assign _44_ = _38_ | _17_;
assign \mchip.gate74.out = _44_ | _43_;
assign io_out = { 6'h00, \mchip.gate85.out , \mchip.gate83.out , \mchip.gate20.out , \mchip.gate74.out , \mchip.gate68.out , \mchip.gate53.out , \mchip.gate45.out , \mchip.gate34.out };
assign \mchip.gate10.in = io_in[3];
assign \mchip.gate11.b = io_in[1];
assign \mchip.gate15.a = io_in[1];
assign \mchip.gate16.a = io_in[0];
assign \mchip.gate17.a = io_in[0];
assign \mchip.gate17.b = io_in[2];
assign \mchip.gate22.a = io_in[0];
assign \mchip.gate24.b = io_in[1];
assign \mchip.gate25.b = io_in[3];
assign \mchip.gate26.a = io_in[0];
assign \mchip.gate27.b = io_in[2];
assign \mchip.gate28.a = io_in[1];
assign \mchip.gate28.b = io_in[2];
assign \mchip.gate36.b = io_in[2];
assign \mchip.gate37.a = io_in[3];
assign \mchip.gate38.a = io_in[0];
assign \mchip.gate39.a = io_in[3];
assign \mchip.gate47.b = io_in[3];
assign \mchip.gate48.b = io_in[3];
assign \mchip.gate49.b = io_in[1];
assign \mchip.gate50.a = io_in[0];
assign \mchip.gate57.b = io_in[2];
assign \mchip.gate58.b = io_in[3];
assign \mchip.gate59.a = io_in[1];
assign \mchip.gate60.b = io_in[3];
assign \mchip.gate61.a = io_in[1];
assign \mchip.gate61.b = io_in[2];
assign \mchip.gate63.a = io_in[0];
assign \mchip.gate69.a = io_in[2];
assign \mchip.gate7.in = io_in[0];
assign \mchip.gate70.a = io_in[0];
assign \mchip.gate70.b = io_in[2];
assign \mchip.gate71.a = io_in[0];
assign \mchip.gate71.b = io_in[1];
assign \mchip.gate75.b = io_in[1];
assign \mchip.gate77.b = io_in[2];
assign \mchip.gate78.a = io_in[2];
assign \mchip.gate79.a = io_in[0];
assign \mchip.gate8.in = io_in[1];
assign \mchip.gate80.a = io_in[0];
assign \mchip.gate80.b = io_in[3];
assign \mchip.gate85.a = io_in[0];
assign \mchip.gate9.in = io_in[2];
assign \mchip.io_in = io_in[7:0];
assign \mchip.io_out = { \mchip.gate85.out , \mchip.gate83.out , \mchip.gate20.out , \mchip.gate74.out , \mchip.gate68.out , \mchip.gate53.out , \mchip.gate45.out , \mchip.gate34.out };
assign \mchip.net1 = io_in[0];
assign \mchip.net10 = \mchip.gate20.out ;
assign \mchip.net11 = \mchip.gate83.out ;
assign \mchip.net12 = \mchip.gate85.out ;
assign \mchip.net13 = 1'h0;
assign \mchip.net14 = 1'h1;
assign \mchip.net2 = io_in[1];
assign \mchip.net3 = io_in[2];
assign \mchip.net4 = io_in[3];
assign \mchip.net5 = \mchip.gate34.out ;
assign \mchip.net6 = \mchip.gate45.out ;
assign \mchip.net7 = \mchip.gate53.out ;
assign \mchip.net8 = \mchip.gate68.out ;
assign \mchip.net9 = \mchip.gate74.out ;
endmodule