winch(x64): Threads

[saulecabrera]

The Wasm Threads proposal is considered Tier 1 according to Wasmtime's Tiers of support.

Winch currently doesn't support this proposal.

• i32.atomic.load8_u @MarinPostma
• i32.atomic.load16_u @MarinPostma
• i32.atomic.load @MarinPostma
• i64.atomic.load8_u @MarinPostma
• i64.atomic.load16_u @MarinPostma
• i64.atomic.load32_u @MarinPostma
• i64.atomic.load @MarinPostma
• i32.atomic.store8 @MarinPostma
• i32.atomic.store16 @MarinPostma
• i32.atomic.store @MarinPostma
• i64.atomic.store8 @MarinPostma
• i64.atomic.store16 @MarinPostma
• i64.atomic.store32 @MarinPostma
• i64.atomic.store @MarinPostma
• i32.atomic.rmw8.add_u
• i32.atomic.rmw16.add_u
• i32.atomic.rmw.add
• i64.atomic.rmw8.add_u
• i64.atomic.rmw16.add_u
• i64.atomic.rmw32.add_u
• i64.atomic.rmw.add
• i32.atomic.rmw8.sub_u
• i32.atomic.rmw16.sub_u
• i32.atomic.rmw.sub
• i64.atomic.rmw8.sub_u
• i64.atomic.rmw16.sub_u
• i64.atomic.rmw32.sub_u
• i64.atomic.rmw.sub
• i32.atomic.rmw8.and_u
• i32.atomic.rmw16.and_u
• i32.atomic.rmw.and
• i64.atomic.rmw8.and_u
• i64.atomic.rmw16.and_u
• i64.atomic.rmw32.and_u
• i64.atomic.rmw.and
• i32.atomic.rmw8.or_u
• i32.atomic.rmw16.or_u
• i32.atomic.rmw.or
• i64.atomic.rmw8.or_u
• i64.atomic.rmw16.or_u
• i64.atomic.rmw32.or_u
• i64.atomic.rmw.or
• i32.atomic.rmw8.xor_u
• i32.atomic.rmw16.xor_u
• i32.atomic.rmw.xor
• i64.atomic.rmw8.xor_u
• i64.atomic.rmw16.xor_u
• i64.atomic.rmw32.xor_u
• i64.atomic.rmw.xor
• i32.atomic.rmw8.xchg_u
• i32.atomic.rmw16.xchg_u
• i32.atomic.rmw.xchg
• i64.atomic.rmw8.xchg_u
• i64.atomic.rmw16.xchg_u
• i64.atomic.rmw32.xchg_u
• i64.atomic.rmw.xchg
• i32.atomic.rmw8.cmpxchg_u
• i32.atomic.rmw16.cmpxchg_u
• i32.atomic.rmw.cmpxchg
• i64.atomic.rmw8.cmpxchg_u
• i64.atomic.rmw16.cmpxchg_u
• i64.atomic.rmw32.cmpxchg_u
• i64.atomic.rmw.cmpxchg

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[MarinPostma]

If my understanding is correct, we need to:

• we need to add to this macros the list of new instruction from thread proposal
• implement the new instructions for the aarch64 and x86_64 backend (in both masm.rs and asm.rs)
• probably add a compile time flag, like winch-thread that removes this flag while the feature is being developped

Is there anything else I'm missing?

[saulecabrera]

Sorry it took me a bit to get back to you on this.

I've update the issue to ensure that it accurately reflects:

• What needs to be done in terms of Wasm instructions.
• Represent that this issue is exclusively for x64

That said:

we need to add to this macros the list of new instruction from thread proposal

Correct, we need to implement each of the instructions to support the threads proposal. I'd suggest reaching out here or via Zulip so that we can coordinate which instructions you'd like to work on to avoid duplicate effort.

implement the new instructions for the aarch64 and x86_64 backend (in both masm.rs and asm.rs)

I'd suggest working on one backend at a time. To ensure that we can review work for each backend carefully and independently. I've opened similar issues for aarch64 as well (e.g., #9927), so that we can track each work separately.

probably add a compile time flag, like winch-thread that removes this flag while the feature is being developped

Instead of a compile time flag, I'd recommend: (i) removing the WasmFeatures::THREADS for the x64 backend here (ii) adding WasmFeatures::THREADS for aarch64 (assuming that we start first with x64) (iii) finally updating the list of spec tests that should fail for the threads proposal, initially this list will probably include all the spec tests or most of them and will get smaller over time until the proposal is fully supported (this is similar to what we have for SIMD today, given that Winch has partial support for it).

[MarinPostma]

@saulecabrera I'll take the loads and stores to start with