From a4415ab7a5a4191e850902a31af4973b1c8b0c23 Mon Sep 17 00:00:00 2001 From: Fabien Marteau Date: Thu, 7 Mar 2024 08:57:51 +0100 Subject: [PATCH 1/4] Adding companion main class to generate GCD.v verilog source --- src/main/scala/gcd/GCD.scala | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/main/scala/gcd/GCD.scala b/src/main/scala/gcd/GCD.scala index 07e434ca..2f6375ba 100644 --- a/src/main/scala/gcd/GCD.scala +++ b/src/main/scala/gcd/GCD.scala @@ -3,6 +3,7 @@ package gcd import chisel3._ +import circt.stage.ChiselStage /** * Compute GCD using subtraction method. @@ -32,3 +33,14 @@ class GCD extends Module { io.outputGCD := x io.outputValid := y === 0.U } + +/** + * Generate Verilog sources and save it in file GCD.v + */ +object GCD extends App { + val verilog_src = ChiselStage.emitSystemVerilog( + new GCD(), + firtoolOpts = Array("-disable-all-randomization", + "-strip-debug-info")) + os.write(os.pwd / "GCD.v", verilog_src) +} From 0661927935fab3d5fa2ddf5912af61a340269d98 Mon Sep 17 00:00:00 2001 From: Fabien Marteau Date: Thu, 7 Mar 2024 11:50:13 +0100 Subject: [PATCH 2/4] Remove verilog file if exists before generate it --- src/main/scala/gcd/GCD.scala | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/main/scala/gcd/GCD.scala b/src/main/scala/gcd/GCD.scala index 2f6375ba..f224fc30 100644 --- a/src/main/scala/gcd/GCD.scala +++ b/src/main/scala/gcd/GCD.scala @@ -42,5 +42,8 @@ object GCD extends App { new GCD(), firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")) - os.write(os.pwd / "GCD.v", verilog_src) + val fverilog = os.pwd / "GCD.v" + if(os.exists(fverilog)) + os.remove(fverilog) + os.write(fverilog, verilog_src) } From 51c49d1908d042e3fd2d51a494ccfe04f4cd9085 Mon Sep 17 00:00:00 2001 From: Fabien Marteau Date: Thu, 7 Mar 2024 16:15:26 +0100 Subject: [PATCH 3/4] Use emitSystemVerilogFile to simplify --- src/main/scala/gcd/GCD.scala | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/main/scala/gcd/GCD.scala b/src/main/scala/gcd/GCD.scala index f224fc30..231579c2 100644 --- a/src/main/scala/gcd/GCD.scala +++ b/src/main/scala/gcd/GCD.scala @@ -38,12 +38,8 @@ class GCD extends Module { * Generate Verilog sources and save it in file GCD.v */ object GCD extends App { - val verilog_src = ChiselStage.emitSystemVerilog( + val verilog_src = ChiselStage.emitSystemVerilogFile( new GCD(), firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")) - val fverilog = os.pwd / "GCD.v" - if(os.exists(fverilog)) - os.remove(fverilog) - os.write(fverilog, verilog_src) } From 149c75c8d71fb68c10b2ba8a0ca12586483d2874 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Thu, 7 Mar 2024 14:26:46 -0800 Subject: [PATCH 4/4] Apply suggestions from code review --- src/main/scala/gcd/GCD.scala | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/main/scala/gcd/GCD.scala b/src/main/scala/gcd/GCD.scala index 231579c2..42c5e804 100644 --- a/src/main/scala/gcd/GCD.scala +++ b/src/main/scala/gcd/GCD.scala @@ -3,7 +3,8 @@ package gcd import chisel3._ -import circt.stage.ChiselStage +// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._ +import _root_.circt.stage.ChiselStage /** * Compute GCD using subtraction method. @@ -38,8 +39,8 @@ class GCD extends Module { * Generate Verilog sources and save it in file GCD.v */ object GCD extends App { - val verilog_src = ChiselStage.emitSystemVerilogFile( - new GCD(), - firtoolOpts = Array("-disable-all-randomization", - "-strip-debug-info")) + ChiselStage.emitSystemVerilogFile( + new GCD, + firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") + ) }