No Sim Results when implicit reg not initialized

[ThePerfectComputer]

Below I create a slow counter(I know I can simply use regEn) where the initial register value of slowCount is never specified. The compiler doesn't complain about this, but I also don't see any simulation results.

Should the compiler complain about no knowing the initial value of a Signal?

module BlinkyCount(topEntity, main) where
import qualified Data.List as List
import Clash.Prelude

incrWhenTrue :: Num a => Bool -> a -> a
incrWhenTrue cond val
  | cond      = val + 1
  | otherwise = val

slowCount :: HiddenClockResetEnable dom => Signal dom (Signed 8)
slowCount =  incrWhenTrue <$> (riseEvery d1024) <*> slowCount

sim_results = sampleN @System 64 slowCount

main :: IO ()
main = do
  putStrLn "Simulating Blinky"
  print $ List.zip [0..] sim_results

[martijnbastiaan]

slowCount forms a combinatorial loop. That is, its value depends on itself, without a memory element inserted in between. Simulation will therefore be stuck in an ifinite loop, trying to calculate 1 + val where val ~ 1 + val. E.g.,

1 + val
1 + (1 + val)
1 + (1 + (1 + val))
1 + (1 + (1 + (1 + val)))
..

[lmbollen]

You currently have no state that stores the counter value.
I'm gonna take a guess and say you probably want add a dflipflop to slowCount if you don´t want initial state:

slowCount = dflipfop (incrWhenTrue <$> (riseEvery d1024) <*> slowCount)

Do note that, since the output of an uninitialized circuit is undefined. All values in your simulation will be undefined + n, where n starts at 0 and increments every 1024 cycles.

If you do want initial state, you should probably be using register

slowCount = register 0 (incrWhenTrue <$> (riseEvery d1024) <*> slowCount)

You can also refactor the code into a single line:
slowCount = register 0 $ mux (riseEvery d1024) (fmap (+1) slowCount) slowCount

[DigitalBrains1]

I was going to say that since we have Num Signal, you can shorten that further to:

slowCount = register 0 $ mux (riseEvery d1024) (slowCount + 1) slowCount

but I tried it out and your one-liner seems to grow exponentially in execution time with every next sample. I think you may have unearthed an issue with mux or riseEvery... I will create an issue later today when I have a chance.