Add checking to detect multiple identical assignments/multiple assignments to the same signal.

[dmlockhart]

If there are multiple assignments to the same signal, the following code is generated:

  assign val_regs$002$en          = resp_rdy;
  assign val_regs$002$en          = resp_rdy;

This appears to be valid Verilog (it translates and simulates fine in Verilator), but throws an error when we try to push the design through the ASIC flow.

Note that there could also be a problem having code like this

  assign val_regs$002$en          = source1;
  assign val_regs$002$en          = source2;

This is trickier to catch because of slices and such.