From 058088436df3eb58206ac4b83fbe86331616f503 Mon Sep 17 00:00:00 2001 From: Tim Lunn Date: Thu, 28 Dec 2023 12:24:41 +1100 Subject: [PATCH 1/9] Bump toolchain to 12.2.rel1 --- Dockerfile | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/Dockerfile b/Dockerfile index 9e7cce8a..c95309ad 100644 --- a/Dockerfile +++ b/Dockerfile @@ -15,7 +15,8 @@ RUN \ default-jre-headless \ patch \ python3 \ - unzip + unzip \ + xz-utils # Install Simplicity Commander (unfortunately no stable URL available, this # is known to be working with Commander_linux_x86_64_1v15p0b1306.tar.bz). @@ -36,15 +37,15 @@ RUN \ ENV PATH="$PATH:/opt/slc_cli" -ARG GCC_ARM_VERSION="10.3-2021.10" +ARG GCC_ARM_VERSION="12.2.rel1" # Install ARM GCC embedded toolchain RUN \ - curl -O https://armkeil.blob.core.windows.net/developer/Files/downloads/gnu-rm/${GCC_ARM_VERSION}/gcc-arm-none-eabi-${GCC_ARM_VERSION}-x86_64-linux.tar.bz2 \ - && tar -C /opt -xjf gcc-arm-none-eabi-10.3-2021.10-x86_64-linux.tar.bz2 \ - && rm gcc-arm-none-eabi-${GCC_ARM_VERSION}-x86_64-linux.tar.bz2 + curl -O https://armkeil.blob.core.windows.net/developer/Files/downloads/gnu/${GCC_ARM_VERSION}/binrel/arm-gnu-toolchain-${GCC_ARM_VERSION}-x86_64-arm-none-eabi.tar.xz \ + && tar -C /opt -xJf arm-gnu-toolchain-${GCC_ARM_VERSION}-x86_64-arm-none-eabi.tar.xz \ + && rm arm-gnu-toolchain-${GCC_ARM_VERSION}-x86_64-arm-none-eabi.tar.xz -ENV PATH="$PATH:/opt/gcc-arm-none-eabi-${GCC_ARM_VERSION}/bin" +ENV PATH="$PATH:/opt/arm-gnu-toolchain-${GCC_ARM_VERSION}-x86_64-arm-none-eabi/bin" ARG GECKO_SDK_VERSION="v4.3.2" @@ -69,5 +70,5 @@ RUN \ --sdk="/gecko_sdk/" \ && slc signature trust --sdk "/gecko_sdk/" \ && slc configuration \ - --gcc-toolchain="/opt/gcc-arm-none-eabi-${GCC_ARM_VERSION}/" + --gcc-toolchain="/opt/arm-gnu-toolchain-${GCC_ARM_VERSION}-x86_64-arm-none-eabi/" From 69fe1167c2bbb20462538bf461e6154a94392d35 Mon Sep 17 00:00:00 2001 From: Tim Lunn Date: Thu, 28 Dec 2023 12:44:22 +1100 Subject: [PATCH 2/9] Bump GeckoSDK 4.4.0 --- .devcontainer/devcontainer.json | 4 ++-- .github/workflows/build.yaml | 8 ++++---- Dockerfile | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/.devcontainer/devcontainer.json b/.devcontainer/devcontainer.json index cc1aabe6..a38a4f7b 100644 --- a/.devcontainer/devcontainer.json +++ b/.devcontainer/devcontainer.json @@ -2,10 +2,10 @@ // README at: https://github.com/devcontainers/templates/tree/main/src/docker-existing-dockerfile { "name": "Silabs Firmware Builder", - "image": "ghcr.io/darkxst/silabs-firmware-builder:4.3.2", + "image": "ghcr.io/darkxst/silabs-firmware-builder:4.4.0", "containerEnv": { - "GECKO_SDK_VERSION": "v4.3.2" + "GECKO_SDK_VERSION": "v4.4.0" } // Features to add to the dev container. More info: https://containers.dev/features. // "features": {}, diff --git a/.github/workflows/build.yaml b/.github/workflows/build.yaml index 7c5503e1..5b675033 100644 --- a/.github/workflows/build.yaml +++ b/.github/workflows/build.yaml @@ -16,7 +16,7 @@ on: workflow_dispatch: env: - sdk_version: 4.3.2 + sdk_version: 4.4.0 jobs: build-container: @@ -26,8 +26,8 @@ jobs: packages: write outputs: sdk_version: ${{ env.sdk_version }} - ot_version: 2.3.2.0 - ezsp_version: 7.3.2.0 + ot_version: 2.4.0.0 + ezsp_version: 7.4.0.0 steps: - uses: actions/checkout@v3.3.0 - name: Log in to the GitHub container registry @@ -154,7 +154,7 @@ jobs: sdk_version: ${{ needs.build-container.outputs.sdk_version}} metadata_fw_type: "ot-rcp" baudrate: ${{ matrix.baudrate }} - metadata_extra: "{ \"ot_rcp_version\": \"SL-OPENTHREAD/2.3.2.0_GitHub-e6df00dd6\" }" + metadata_extra: "{ \"ot_rcp_version\": \"SL-OPENTHREAD/2.4.0.0_GitHub-7074a43e4\" }" collect_artifacts: name: download and publish all artifacts diff --git a/Dockerfile b/Dockerfile index c95309ad..b053f6c2 100644 --- a/Dockerfile +++ b/Dockerfile @@ -47,7 +47,7 @@ RUN \ ENV PATH="$PATH:/opt/arm-gnu-toolchain-${GCC_ARM_VERSION}-x86_64-arm-none-eabi/bin" -ARG GECKO_SDK_VERSION="v4.3.2" +ARG GECKO_SDK_VERSION="v4.4.0" RUN \ git clone --depth 1 -b ${GECKO_SDK_VERSION} \ From 10cd886470f6ea3ea631185c6e350538084a2d94 Mon Sep 17 00:00:00 2001 From: Tim Lunn Date: Thu, 28 Dec 2023 15:24:38 +1100 Subject: [PATCH 3/9] Update patch for sl_cpc_config patches --- ...configure-cpc-usart-vcom-for-elelabs.patch | 44 +++++++++++ ...0001-config-configure-cpc-usart-vcom.patch | 39 ---------- ...config-configure-cpc-usart-vcom-B1B0.patch | 74 +++++++++---------- ...g-configure-cpc-usart-vcom-A6A5-B1B0.patch | 70 ++++++++++-------- ...g-configure-cpc-usart-vcom-A6A5-B1B0.patch | 53 +++++++++++++ ...figure-cpc-usart-vcom-for-SkyConnect.patch | 51 ------------- ...-configure-cpc-usart-vcom-for-Yellow.patch | 73 +++++++++--------- ...g-configure-cpc-usart-vcom-B1B0-D3D4.patch | 74 ++++++++++--------- ...config-configure-cpc-usart-vcom-B1B0.patch | 74 +++++++++---------- 9 files changed, 285 insertions(+), 267 deletions(-) create mode 100644 RCPMultiPAN/Elelabs-ELx0x3/0001-config-configure-cpc-usart-vcom-for-elelabs.patch delete mode 100644 RCPMultiPAN/Elelabs-ELx0x3/0001-config-configure-cpc-usart-vcom.patch create mode 100644 RCPMultiPAN/SkyConnect/0001-config-configure-cpc-usart-vcom-A6A5-B1B0.patch delete mode 100644 RCPMultiPAN/SkyConnect/0001-config-configure-cpc-usart-vcom-for-SkyConnect.patch diff --git a/RCPMultiPAN/Elelabs-ELx0x3/0001-config-configure-cpc-usart-vcom-for-elelabs.patch b/RCPMultiPAN/Elelabs-ELx0x3/0001-config-configure-cpc-usart-vcom-for-elelabs.patch new file mode 100644 index 00000000..af05061a --- /dev/null +++ b/RCPMultiPAN/Elelabs-ELx0x3/0001-config-configure-cpc-usart-vcom-for-elelabs.patch @@ -0,0 +1,44 @@ +From c4b4ea8e3b778442f9861eaf0be2a5340cf400c7 Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Thu, 28 Dec 2023 18:53:47 +1100 +Subject: [PATCH] config: configure cpc usart vcom for elelabs + +--- + config/sl_cpc_drv_uart_usart_vcom_config.h | 21 ++++++++++----------- + 1 file changed, 10 insertions(+), 11 deletions(-) + +diff --git a/config/sl_cpc_drv_uart_usart_vcom_config.h b/config/sl_cpc_drv_uart_usart_vcom_config.h +index 06d41dd..1b0a352 100644 +--- a/config/sl_cpc_drv_uart_usart_vcom_config.h ++++ b/config/sl_cpc_drv_uart_usart_vcom_config.h +@@ -59,17 +59,16 @@ + // <<< sl:start pin_tool >>> + // SL_CPC_DRV_UART_VCOM + // $[USART_SL_CPC_DRV_UART_VCOM] +-#warning "CPC USART peripheral not configured" +-// #define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +-// #define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 +-// +-// #define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_TX_PIN 13 +-// #define SL_CPC_DRV_UART_VCOM_TX_LOC 22 +-// +-// #define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_RX_PIN 14 +-// #define SL_CPC_DRV_UART_VCOM_RX_LOC 20 ++#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 ++#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 ++ ++#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA ++#define SL_CPC_DRV_UART_VCOM_TX_PIN 0 ++#define SL_CPC_DRV_UART_VCOM_TX_LOC 0 ++ ++#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA ++#define SL_CPC_DRV_UART_VCOM_RX_PIN 1 ++#define SL_CPC_DRV_UART_VCOM_RX_LOC 0 + // + // #define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD + // #define SL_CPC_DRV_UART_VCOM_CTS_PIN 15 +-- +2.40.1 + diff --git a/RCPMultiPAN/Elelabs-ELx0x3/0001-config-configure-cpc-usart-vcom.patch b/RCPMultiPAN/Elelabs-ELx0x3/0001-config-configure-cpc-usart-vcom.patch deleted file mode 100644 index 1934626c..00000000 --- a/RCPMultiPAN/Elelabs-ELx0x3/0001-config-configure-cpc-usart-vcom.patch +++ /dev/null @@ -1,39 +0,0 @@ ---- a/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h 2023-04-12 09:03:35.591439514 +0200 -+++ b/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h 2023-04-12 09:05:42.178039314 +0200 -@@ -63,24 +63,24 @@ - #define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - - // USART TX --#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_TX_PIN 13 --#define SL_CPC_DRV_UART_VCOM_TX_LOC 22 -+#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -+#define SL_CPC_DRV_UART_VCOM_TX_PIN 0 -+#define SL_CPC_DRV_UART_VCOM_TX_LOC 0 - - // USART RX --#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_RX_PIN 14 --#define SL_CPC_DRV_UART_VCOM_RX_LOC 20 -+#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -+#define SL_CPC_DRV_UART_VCOM_RX_PIN 1 -+#define SL_CPC_DRV_UART_VCOM_RX_LOC 0 - - // USART CTS --#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_CTS_PIN 15 --#define SL_CPC_DRV_UART_VCOM_CTS_LOC 20 -+// #define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD -+// #define SL_CPC_DRV_UART_VCOM_CTS_PIN 15 -+// #define SL_CPC_DRV_UART_VCOM_CTS_LOC 20 - - // USART RTS --#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_RTS_PIN 16 --#define SL_CPC_DRV_UART_VCOM_RTS_LOC 20 -+// #define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD -+// #define SL_CPC_DRV_UART_VCOM_RTS_PIN 16 -+// #define SL_CPC_DRV_UART_VCOM_RTS_LOC 20 - - // [USART_SL_CPC_DRV_UART_VCOM]$ - // <<< sl:end pin_tool >>> diff --git a/RCPMultiPAN/SLZB-06M/0001-config-configure-cpc-usart-vcom-B1B0.patch b/RCPMultiPAN/SLZB-06M/0001-config-configure-cpc-usart-vcom-B1B0.patch index 676ced08..3ab5feee 100644 --- a/RCPMultiPAN/SLZB-06M/0001-config-configure-cpc-usart-vcom-B1B0.patch +++ b/RCPMultiPAN/SLZB-06M/0001-config-configure-cpc-usart-vcom-B1B0.patch @@ -1,45 +1,41 @@ +From 937b868877e963b1f66451b6109bf788f8c17dbd Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Thu, 28 Dec 2023 18:33:50 +1100 +Subject: [PATCH] config: configure cpc usart vcom B1B0 + --- - ...cpc_drv_secondary_uart_usart_vcom_config.h | 24 +++++++++---------- - 1 file changed, 12 insertions(+), 12 deletions(-) + config/sl_cpc_drv_uart_usart_vcom_config.h | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) -diff --git a/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h b/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -index 66288db..56c21a9 100644 ---- a/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -+++ b/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -@@ -62,21 +62,21 @@ - #define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 - #define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - --// USART TX --#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_TX_PIN 13 -+// USART0 TX on PB01 +diff --git a/config/sl_cpc_drv_uart_usart_vcom_config.h b/config/sl_cpc_drv_uart_usart_vcom_config.h +index dbce4ed..f100f68 100644 +--- a/config/sl_cpc_drv_uart_usart_vcom_config.h ++++ b/config/sl_cpc_drv_uart_usart_vcom_config.h +@@ -59,15 +59,15 @@ + // <<< sl:start pin_tool >>> + // SL_CPC_DRV_UART_VCOM + // $[USART_SL_CPC_DRV_UART_VCOM] +-#warning "CPC USART peripheral not configured" +-// #define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +-// #define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 +-// +-// #define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_TX_PIN 13 +-// +-// #define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_RX_PIN 14 ++ ++#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 ++#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 ++ +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortB -+#define SL_CPC_DRV_UART_VCOM_TX_PIN 1 - --// USART RX --#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_RX_PIN 14 -+// USART0 RX on PB00 ++#define SL_CPC_DRV_UART_VCOM_TX_PIN 01 ++ +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortB -+#define SL_CPC_DRV_UART_VCOM_RX_PIN 0 - --// USART CTS --#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_CTS_PIN 13 -+// USART0 CTS on PB01 -+//#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD -+//#define SL_CPC_DRV_UART_VCOM_CTS_PIN 3 - --// USART RTS --#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_RTS_PIN 14 -+// USART0 RTS on PB00 -+//#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD -+//#define SL_CPC_DRV_UART_VCOM_RTS_PIN 4 - - // [USART_SL_CPC_DRV_UART_VCOM]$ - // <<< sl:end pin_tool >>> ++#define SL_CPC_DRV_UART_VCOM_RX_PIN 00 + // + // #define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD + // #define SL_CPC_DRV_UART_VCOM_CTS_PIN 13 -- -2.39.1 +2.40.1 diff --git a/RCPMultiPAN/SLZB-07/0001-config-configure-cpc-usart-vcom-A6A5-B1B0.patch b/RCPMultiPAN/SLZB-07/0001-config-configure-cpc-usart-vcom-A6A5-B1B0.patch index 6d8709eb..aacbecbb 100644 --- a/RCPMultiPAN/SLZB-07/0001-config-configure-cpc-usart-vcom-A6A5-B1B0.patch +++ b/RCPMultiPAN/SLZB-07/0001-config-configure-cpc-usart-vcom-A6A5-B1B0.patch @@ -1,45 +1,53 @@ +From 675bfdf1bb78893a4c51e7ba0eb71fc52305e474 Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Thu, 28 Dec 2023 18:33:50 +1100 +Subject: [PATCH] config: configure cpc usart vcom A6A5-B1B0 + --- - ...cpc_drv_secondary_uart_usart_vcom_config.h | 24 +++++++++---------- - 1 file changed, 12 insertions(+), 12 deletions(-) + config/sl_cpc_drv_uart_usart_vcom_config.h | 30 +++++++++++----------- + 1 file changed, 15 insertions(+), 15 deletions(-) -diff --git a/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h b/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -index 66288db..56c21a9 100644 ---- a/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -+++ b/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -@@ -62,21 +62,21 @@ - #define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 - #define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - --// USART TX --#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_TX_PIN 13 -+// USART0 TX on PA06 +diff --git a/config/sl_cpc_drv_uart_usart_vcom_config.h b/config/sl_cpc_drv_uart_usart_vcom_config.h +index dbce4ed..816402f 100644 +--- a/config/sl_cpc_drv_uart_usart_vcom_config.h ++++ b/config/sl_cpc_drv_uart_usart_vcom_config.h +@@ -59,21 +59,21 @@ + // <<< sl:start pin_tool >>> + // SL_CPC_DRV_UART_VCOM + // $[USART_SL_CPC_DRV_UART_VCOM] +-#warning "CPC USART peripheral not configured" +-// #define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +-// #define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 +-// +-// #define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_TX_PIN 13 +-// +-// #define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_RX_PIN 14 +-// +-// #define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_CTS_PIN 13 +-// +-// #define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_RTS_PIN 14 ++ ++#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 ++#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 ++ +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_TX_PIN 6 - --// USART RX --#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_RX_PIN 14 -+// USART0 RX on PA05 ++ +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RX_PIN 5 - --// USART CTS --#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_CTS_PIN 13 -+// USART0 CTS on PB01 ++ +#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortB +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 1 - --// USART RTS --#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_RTS_PIN 14 -+// USART0 RTS on PB00 ++ +#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortB +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 - // [USART_SL_CPC_DRV_UART_VCOM]$ // <<< sl:end pin_tool >>> + -- -2.39.1 +2.40.1 diff --git a/RCPMultiPAN/SkyConnect/0001-config-configure-cpc-usart-vcom-A6A5-B1B0.patch b/RCPMultiPAN/SkyConnect/0001-config-configure-cpc-usart-vcom-A6A5-B1B0.patch new file mode 100644 index 00000000..aacbecbb --- /dev/null +++ b/RCPMultiPAN/SkyConnect/0001-config-configure-cpc-usart-vcom-A6A5-B1B0.patch @@ -0,0 +1,53 @@ +From 675bfdf1bb78893a4c51e7ba0eb71fc52305e474 Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Thu, 28 Dec 2023 18:33:50 +1100 +Subject: [PATCH] config: configure cpc usart vcom A6A5-B1B0 + +--- + config/sl_cpc_drv_uart_usart_vcom_config.h | 30 +++++++++++----------- + 1 file changed, 15 insertions(+), 15 deletions(-) + +diff --git a/config/sl_cpc_drv_uart_usart_vcom_config.h b/config/sl_cpc_drv_uart_usart_vcom_config.h +index dbce4ed..816402f 100644 +--- a/config/sl_cpc_drv_uart_usart_vcom_config.h ++++ b/config/sl_cpc_drv_uart_usart_vcom_config.h +@@ -59,21 +59,21 @@ + // <<< sl:start pin_tool >>> + // SL_CPC_DRV_UART_VCOM + // $[USART_SL_CPC_DRV_UART_VCOM] +-#warning "CPC USART peripheral not configured" +-// #define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +-// #define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 +-// +-// #define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_TX_PIN 13 +-// +-// #define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_RX_PIN 14 +-// +-// #define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_CTS_PIN 13 +-// +-// #define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_RTS_PIN 14 ++ ++#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 ++#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 ++ ++#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA ++#define SL_CPC_DRV_UART_VCOM_TX_PIN 6 ++ ++#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA ++#define SL_CPC_DRV_UART_VCOM_RX_PIN 5 ++ ++#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortB ++#define SL_CPC_DRV_UART_VCOM_CTS_PIN 1 ++ ++#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortB ++#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + // [USART_SL_CPC_DRV_UART_VCOM]$ + // <<< sl:end pin_tool >>> + +-- +2.40.1 + diff --git a/RCPMultiPAN/SkyConnect/0001-config-configure-cpc-usart-vcom-for-SkyConnect.patch b/RCPMultiPAN/SkyConnect/0001-config-configure-cpc-usart-vcom-for-SkyConnect.patch deleted file mode 100644 index 0a4bbc50..00000000 --- a/RCPMultiPAN/SkyConnect/0001-config-configure-cpc-usart-vcom-for-SkyConnect.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 952a0a662f48fe5c44d7350f6d89b90dfbea60ad Mon Sep 17 00:00:00 2001 -Message-Id: <952a0a662f48fe5c44d7350f6d89b90dfbea60ad.1675725669.git.stefan@agner.ch> -From: Stefan Agner -Date: Tue, 7 Feb 2023 00:14:01 +0100 -Subject: [PATCH] config: configure cpc usart vcom for SkyConnect - ---- - ...cpc_drv_secondary_uart_usart_vcom_config.h | 24 +++++++++---------- - 1 file changed, 12 insertions(+), 12 deletions(-) - -diff --git a/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h b/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -index 66288db..56c21a9 100644 ---- a/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -+++ b/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -@@ -62,21 +62,21 @@ - #define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 - #define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - --// USART TX --#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_TX_PIN 13 -+// USART0 TX on PA06 -+#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -+#define SL_CPC_DRV_UART_VCOM_TX_PIN 6 - --// USART RX --#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_RX_PIN 14 -+// USART0 RX on PA05 -+#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -+#define SL_CPC_DRV_UART_VCOM_RX_PIN 5 - --// USART CTS --#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_CTS_PIN 13 -+// USART0 CTS on PB01 -+#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortB -+#define SL_CPC_DRV_UART_VCOM_CTS_PIN 1 - --// USART RTS --#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_RTS_PIN 14 -+// USART0 RTS on PB00 -+#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortB -+#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 - - // [USART_SL_CPC_DRV_UART_VCOM]$ - // <<< sl:end pin_tool >>> --- -2.39.1 - diff --git a/RCPMultiPAN/Yellow/0001-config-configure-cpc-usart-vcom-for-Yellow.patch b/RCPMultiPAN/Yellow/0001-config-configure-cpc-usart-vcom-for-Yellow.patch index ea81872d..ea60c531 100644 --- a/RCPMultiPAN/Yellow/0001-config-configure-cpc-usart-vcom-for-Yellow.patch +++ b/RCPMultiPAN/Yellow/0001-config-configure-cpc-usart-vcom-for-Yellow.patch @@ -1,50 +1,53 @@ -From 20184d2a2b267ce0ff81464d140481ce1657da74 Mon Sep 17 00:00:00 2001 -Message-Id: <20184d2a2b267ce0ff81464d140481ce1657da74.1679556106.git.stefan@agner.ch> -From: Stefan Agner -Date: Tue, 7 Feb 2023 00:18:24 +0100 +From d137c364d5447be700ba49f55a868da9d80cd5f1 Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Thu, 28 Dec 2023 18:33:50 +1100 Subject: [PATCH] config: configure cpc usart vcom for Yellow --- - ...cpc_drv_secondary_uart_usart_vcom_config.h | 22 +++++++++---------- - 1 file changed, 11 insertions(+), 11 deletions(-) + config/sl_cpc_drv_uart_usart_vcom_config.h | 30 +++++++++++----------- + 1 file changed, 15 insertions(+), 15 deletions(-) -diff --git a/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h b/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -index 66288db..e006ebc 100644 ---- a/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -+++ b/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -@@ -62,21 +62,21 @@ - #define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 - #define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - --// USART TX --#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_TX_PIN 13 -+// USART0 TX on PA05 +diff --git a/config/sl_cpc_drv_uart_usart_vcom_config.h b/config/sl_cpc_drv_uart_usart_vcom_config.h +index dbce4ed..5333bca 100644 +--- a/config/sl_cpc_drv_uart_usart_vcom_config.h ++++ b/config/sl_cpc_drv_uart_usart_vcom_config.h +@@ -59,21 +59,21 @@ + // <<< sl:start pin_tool >>> + // SL_CPC_DRV_UART_VCOM + // $[USART_SL_CPC_DRV_UART_VCOM] +-#warning "CPC USART peripheral not configured" +-// #define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +-// #define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 +-// +-// #define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_TX_PIN 13 +-// +-// #define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_RX_PIN 14 +-// +-// #define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_CTS_PIN 13 +-// +-// #define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_RTS_PIN 14 ++ ++#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 ++#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 ++ +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 - --// USART RX --#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_RX_PIN 14 -+// USART0 RX on PA06 ++ +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 - --// USART CTS -+// USART0 CTS on PD02 - #define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_CTS_PIN 13 ++ ++#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 2 - --// USART RTS --#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_RTS_PIN 14 -+// USART0 RTS on PC01 ++ +#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortC +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 1 - // [USART_SL_CPC_DRV_UART_VCOM]$ // <<< sl:end pin_tool >>> + -- -2.40.0 +2.40.1 diff --git a/RCPMultiPAN/ZB-GW04-1v2/0001-config-configure-cpc-usart-vcom-B1B0-D3D4.patch b/RCPMultiPAN/ZB-GW04-1v2/0001-config-configure-cpc-usart-vcom-B1B0-D3D4.patch index ec890bb1..488f4ecf 100644 --- a/RCPMultiPAN/ZB-GW04-1v2/0001-config-configure-cpc-usart-vcom-B1B0-D3D4.patch +++ b/RCPMultiPAN/ZB-GW04-1v2/0001-config-configure-cpc-usart-vcom-B1B0-D3D4.patch @@ -1,45 +1,53 @@ +From 6c8377ef5ce335bf3bc3341e6d45f6c2aca4a61e Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Thu, 28 Dec 2023 18:33:50 +1100 +Subject: [PATCH] config: configure cpc usart vcom B1B0-D3D4 + --- - ...cpc_drv_secondary_uart_usart_vcom_config.h | 24 +++++++++---------- - 1 file changed, 12 insertions(+), 12 deletions(-) + config/sl_cpc_drv_uart_usart_vcom_config.h | 30 +++++++++++----------- + 1 file changed, 15 insertions(+), 15 deletions(-) -diff --git a/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h b/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -index 66288db..56c21a9 100644 ---- a/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -+++ b/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -@@ -62,21 +62,21 @@ - #define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 - #define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - --// USART TX --#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_TX_PIN 13 -+// USART0 TX on PA06 +diff --git a/config/sl_cpc_drv_uart_usart_vcom_config.h b/config/sl_cpc_drv_uart_usart_vcom_config.h +index dbce4ed..c8c835f 100644 +--- a/config/sl_cpc_drv_uart_usart_vcom_config.h ++++ b/config/sl_cpc_drv_uart_usart_vcom_config.h +@@ -59,21 +59,21 @@ + // <<< sl:start pin_tool >>> + // SL_CPC_DRV_UART_VCOM + // $[USART_SL_CPC_DRV_UART_VCOM] +-#warning "CPC USART peripheral not configured" +-// #define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +-// #define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 +-// +-// #define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_TX_PIN 13 +-// +-// #define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_RX_PIN 14 +-// +-// #define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_CTS_PIN 13 +-// +-// #define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_RTS_PIN 14 ++ ++#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 ++#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 ++ +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortB -+#define SL_CPC_DRV_UART_VCOM_TX_PIN 1 - --// USART RX --#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_RX_PIN 14 -+// USART0 RX on PA05 ++#define SL_CPC_DRV_UART_VCOM_TX_PIN 01 ++ +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortB -+#define SL_CPC_DRV_UART_VCOM_RX_PIN 0 - --// USART CTS --#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_CTS_PIN 13 -+// USART0 CTS on PB01 ++#define SL_CPC_DRV_UART_VCOM_RX_PIN 00 ++ +#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 3 - --// USART RTS --#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_RTS_PIN 14 -+// USART0 RTS on PB00 ++ +#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 4 - // [USART_SL_CPC_DRV_UART_VCOM]$ // <<< sl:end pin_tool >>> + -- -2.39.1 +2.40.1 diff --git a/RCPMultiPAN/ZBDongleE/0001-config-configure-cpc-usart-vcom-B1B0.patch b/RCPMultiPAN/ZBDongleE/0001-config-configure-cpc-usart-vcom-B1B0.patch index 676ced08..3ab5feee 100644 --- a/RCPMultiPAN/ZBDongleE/0001-config-configure-cpc-usart-vcom-B1B0.patch +++ b/RCPMultiPAN/ZBDongleE/0001-config-configure-cpc-usart-vcom-B1B0.patch @@ -1,45 +1,41 @@ +From 937b868877e963b1f66451b6109bf788f8c17dbd Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Thu, 28 Dec 2023 18:33:50 +1100 +Subject: [PATCH] config: configure cpc usart vcom B1B0 + --- - ...cpc_drv_secondary_uart_usart_vcom_config.h | 24 +++++++++---------- - 1 file changed, 12 insertions(+), 12 deletions(-) + config/sl_cpc_drv_uart_usart_vcom_config.h | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) -diff --git a/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h b/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -index 66288db..56c21a9 100644 ---- a/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -+++ b/config/sl_cpc_drv_secondary_uart_usart_vcom_config.h -@@ -62,21 +62,21 @@ - #define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 - #define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - --// USART TX --#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_TX_PIN 13 -+// USART0 TX on PB01 +diff --git a/config/sl_cpc_drv_uart_usart_vcom_config.h b/config/sl_cpc_drv_uart_usart_vcom_config.h +index dbce4ed..f100f68 100644 +--- a/config/sl_cpc_drv_uart_usart_vcom_config.h ++++ b/config/sl_cpc_drv_uart_usart_vcom_config.h +@@ -59,15 +59,15 @@ + // <<< sl:start pin_tool >>> + // SL_CPC_DRV_UART_VCOM + // $[USART_SL_CPC_DRV_UART_VCOM] +-#warning "CPC USART peripheral not configured" +-// #define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +-// #define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 +-// +-// #define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_TX_PIN 13 +-// +-// #define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortD +-// #define SL_CPC_DRV_UART_VCOM_RX_PIN 14 ++ ++#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 ++#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 ++ +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortB -+#define SL_CPC_DRV_UART_VCOM_TX_PIN 1 - --// USART RX --#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_RX_PIN 14 -+// USART0 RX on PB00 ++#define SL_CPC_DRV_UART_VCOM_TX_PIN 01 ++ +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortB -+#define SL_CPC_DRV_UART_VCOM_RX_PIN 0 - --// USART CTS --#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_CTS_PIN 13 -+// USART0 CTS on PB01 -+//#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD -+//#define SL_CPC_DRV_UART_VCOM_CTS_PIN 3 - --// USART RTS --#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD --#define SL_CPC_DRV_UART_VCOM_RTS_PIN 14 -+// USART0 RTS on PB00 -+//#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortD -+//#define SL_CPC_DRV_UART_VCOM_RTS_PIN 4 - - // [USART_SL_CPC_DRV_UART_VCOM]$ - // <<< sl:end pin_tool >>> ++#define SL_CPC_DRV_UART_VCOM_RX_PIN 00 + // + // #define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortD + // #define SL_CPC_DRV_UART_VCOM_CTS_PIN 13 -- -2.39.1 +2.40.1 From ee7250f5cf4c2cc5b0304734a109a971aba9a100 Mon Sep 17 00:00:00 2001 From: Tim Lunn Date: Thu, 28 Dec 2023 19:06:07 +1100 Subject: [PATCH 4/9] Drop bootloader reset patches included in new release --- ...thread-Support-reset-into-bootloader.patch | 188 ------------------ ...-Implement-reset-into-bootloader-pla.patch | 58 ------ 2 files changed, 246 deletions(-) delete mode 100644 OpenThreadRCP/GeckoSDK/0001-third_party-openthread-Support-reset-into-bootloader.patch delete mode 100644 OpenThreadRCP/GeckoSDK/0002-openthread-efr32-Implement-reset-into-bootloader-pla.patch diff --git a/OpenThreadRCP/GeckoSDK/0001-third_party-openthread-Support-reset-into-bootloader.patch b/OpenThreadRCP/GeckoSDK/0001-third_party-openthread-Support-reset-into-bootloader.patch deleted file mode 100644 index 31e07596..00000000 --- a/OpenThreadRCP/GeckoSDK/0001-third_party-openthread-Support-reset-into-bootloader.patch +++ /dev/null @@ -1,188 +0,0 @@ -From 59e7a11a59cd10e2c292bf5dd1439a672b1bc898 Mon Sep 17 00:00:00 2001 -Message-ID: <59e7a11a59cd10e2c292bf5dd1439a672b1bc898.1686305449.git.stefan@agner.ch> -From: Stefan Agner -Date: Fri, 9 Jun 2023 12:10:44 +0200 -Subject: [PATCH] third_party: openthread: Support reset into bootloader - ---- - .../openthread/include/openthread/instance.h | 8 ++++++++ - .../include/openthread/platform/misc.h | 8 ++++++++ - .../openthread/src/core/api/instance_api.cpp | 1 + - .../openthread/src/core/common/instance.cpp | 11 ++++++++++- - .../openthread/src/core/common/instance.hpp | 6 ++++++ - .../openthread/src/lib/spinel/radio_spinel.hpp | 2 +- - .../openthread/src/lib/spinel/spinel.h | 5 +++-- - .../third_party/openthread/src/ncp/ncp_base.cpp | 17 ++++++++++++++--- - .../third_party/openthread/src/ncp/ncp_config.h | 7 +++++++ - 9 files changed, 58 insertions(+), 7 deletions(-) - -diff --git a/util/third_party/openthread/include/openthread/instance.h b/util/third_party/openthread/include/openthread/instance.h -index 580f334c5..7d9408cef 100644 ---- a/util/third_party/openthread/include/openthread/instance.h -+++ b/util/third_party/openthread/include/openthread/instance.h -@@ -250,6 +250,14 @@ void otRemoveStateChangeCallback(otInstance *aInstance, otStateChangedCallback a - */ - void otInstanceReset(otInstance *aInstance); - -+/** -+ * This method reboots the platform into its bootloader. -+ * -+ * @param[in] aInstance A pointer to an OpenThread instance. -+ * -+ */ -+void otInstanceRebootBootloader(otInstance *aInstance); -+ - /** - * Deletes all the settings stored on non-volatile memory, and then triggers a platform reset. - * -diff --git a/util/third_party/openthread/include/openthread/platform/misc.h b/util/third_party/openthread/include/openthread/platform/misc.h -index 99c3ed3f5..9b8419294 100644 ---- a/util/third_party/openthread/include/openthread/platform/misc.h -+++ b/util/third_party/openthread/include/openthread/platform/misc.h -@@ -61,6 +61,14 @@ extern "C" { - */ - void otPlatReset(otInstance *aInstance); - -+/** -+ * This function reboots the platform into its bootloader, if supported. -+ * -+ * @param[in] aInstance The OpenThread instance structure. -+ * -+ */ -+void otPlatRebootBootloader(otInstance *aInstance); -+ - /** - * Enumeration of possible reset reason codes. - * -diff --git a/util/third_party/openthread/src/core/api/instance_api.cpp b/util/third_party/openthread/src/core/api/instance_api.cpp -index 06db73ce3..04c473af6 100644 ---- a/util/third_party/openthread/src/core/api/instance_api.cpp -+++ b/util/third_party/openthread/src/core/api/instance_api.cpp -@@ -112,6 +112,7 @@ otError otInstanceErasePersistentInfo(otInstance *aInstance) { return AsCoreType - #endif // OPENTHREAD_MTD || OPENTHREAD_FTD - - #if OPENTHREAD_RADIO -+void otInstanceRebootBootloader(otInstance *aInstance) { AsCoreType(aInstance).RebootBootloader(); } - void otInstanceResetRadioStack(otInstance *aInstance) { AsCoreType(aInstance).ResetRadioStack(); } - #endif - -diff --git a/util/third_party/openthread/src/core/common/instance.cpp b/util/third_party/openthread/src/core/common/instance.cpp -index d0aebecd3..55fda63b3 100644 ---- a/util/third_party/openthread/src/core/common/instance.cpp -+++ b/util/third_party/openthread/src/core/common/instance.cpp -@@ -309,12 +309,21 @@ exit: - void Instance::Reset(void) { otPlatReset(this); } - - #if OPENTHREAD_RADIO -+void Instance::RebootBootloader(void) -+{ -+#if OPENTHREAD_CONFIG_NCP_REBOOT_BOOTLOADER_ENABLE -+ otPlatRebootBootloader(this); -+#else -+ Reset(); -+#endif -+} -+ - void Instance::ResetRadioStack(void) - { - mRadio.Init(); - mLinkRaw.Init(); - } --#endif -+#endif // OPENTHREAD_RADIO - - void Instance::AfterInit(void) - { -diff --git a/util/third_party/openthread/src/core/common/instance.hpp b/util/third_party/openthread/src/core/common/instance.hpp -index 8ce6eba09..6ccf5ea25 100644 ---- a/util/third_party/openthread/src/core/common/instance.hpp -+++ b/util/third_party/openthread/src/core/common/instance.hpp -@@ -225,6 +225,12 @@ public: - void Reset(void); - - #if OPENTHREAD_RADIO -+ /** -+ * This method reboots the radio into its bootloader. -+ * -+ */ -+ void RebootBootloader(void); -+ - /** - * This method resets the internal states of the radio. - * -diff --git a/util/third_party/openthread/src/lib/spinel/radio_spinel.hpp b/util/third_party/openthread/src/lib/spinel/radio_spinel.hpp -index 5aa474415..b4e0c349a 100644 ---- a/util/third_party/openthread/src/lib/spinel/radio_spinel.hpp -+++ b/util/third_party/openthread/src/lib/spinel/radio_spinel.hpp -@@ -875,7 +875,7 @@ public: - /** - * This method tries to reset the co-processor. - * -- * @prarm[in] aResetType The reset type, SPINEL_RESET_PLATFORM or SPINEL_RESET_STACK. -+ * @prarm[in] aResetType The reset type, SPINEL_RESET_PLATFORM, SPINEL_RESET_STACK, or SPINEL_RESET_BOOTLOADER. - * - * @retval OT_ERROR_NONE Successfully removed item from the property. - * @retval OT_ERROR_BUSY Failed due to another operation is on going. -diff --git a/util/third_party/openthread/src/lib/spinel/spinel.h b/util/third_party/openthread/src/lib/spinel/spinel.h -index d2a3644e9..31aedadfb 100644 ---- a/util/third_party/openthread/src/lib/spinel/spinel.h -+++ b/util/third_party/openthread/src/lib/spinel/spinel.h -@@ -901,8 +901,9 @@ enum - - enum - { -- SPINEL_RESET_PLATFORM = 1, -- SPINEL_RESET_STACK = 2, -+ SPINEL_RESET_PLATFORM = 1, -+ SPINEL_RESET_STACK = 2, -+ SPINEL_RESET_BOOTLOADER = 3, - }; - - enum -diff --git a/util/third_party/openthread/src/ncp/ncp_base.cpp b/util/third_party/openthread/src/ncp/ncp_base.cpp -index fa79b0aef..a1e87ba7b 100644 ---- a/util/third_party/openthread/src/ncp/ncp_base.cpp -+++ b/util/third_party/openthread/src/ncp/ncp_base.cpp -@@ -1370,9 +1370,20 @@ otError NcpBase::CommandHandler_RESET(uint8_t aHeader) - else - #endif - { -- // Signal a platform reset. If implemented, this function -- // shouldn't return. -- otInstanceReset(mInstance); -+#if OPENTHREAD_RADIO -+ if (reset_type == SPINEL_RESET_BOOTLOADER) -+ { -+ // Reboot into the bootloader. If implemented, this function -+ // shouldn't return. -+ otInstanceRebootBootloader(mInstance); -+ } -+ else -+#endif -+ { -+ // Signal a platform reset. If implemented, this function -+ // shouldn't return. -+ otInstanceReset(mInstance); -+ } - - #if OPENTHREAD_MTD || OPENTHREAD_FTD - // We only get to this point if the -diff --git a/util/third_party/openthread/src/ncp/ncp_config.h b/util/third_party/openthread/src/ncp/ncp_config.h -index bc54fb52a..bb11d5b33 100644 ---- a/util/third_party/openthread/src/ncp/ncp_config.h -+++ b/util/third_party/openthread/src/ncp/ncp_config.h -@@ -189,4 +189,11 @@ - #define OPENTHREAD_ENABLE_NCP_VENDOR_HOOK 0 - #endif - -+/** -+ * @def OPENTHREAD_CONFIG_NCP_REBOOT_BOOTLOADER_ENABLE -+ */ -+#ifndef OPENTHREAD_CONFIG_NCP_REBOOT_BOOTLOADER_ENABLE -+#define OPENTHREAD_CONFIG_NCP_REBOOT_BOOTLOADER_ENABLE 0 -+#endif -+ - #endif // CONFIG_NCP_H_ --- -2.41.0 - diff --git a/OpenThreadRCP/GeckoSDK/0002-openthread-efr32-Implement-reset-into-bootloader-pla.patch b/OpenThreadRCP/GeckoSDK/0002-openthread-efr32-Implement-reset-into-bootloader-pla.patch deleted file mode 100644 index 413d98f4..00000000 --- a/OpenThreadRCP/GeckoSDK/0002-openthread-efr32-Implement-reset-into-bootloader-pla.patch +++ /dev/null @@ -1,58 +0,0 @@ -From cf28b5b8c1e5e8c23ab374d93f7726e73cd35119 Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: <774ce9b07d1f4a9b077da187ba413269900cd5db.1678797513.git.stefan@agner.ch> -References: <774ce9b07d1f4a9b077da187ba413269900cd5db.1678797513.git.stefan@agner.ch> -From: Stefan Agner -Date: Tue, 14 Mar 2023 13:13:19 +0100 -Subject: [PATCH] openthread: efr32: Implement reset into bootloader platform - support - ---- - .../platform-abstraction/efr32/misc.c | 24 +++++++++++++++++++ - 1 file changed, 24 insertions(+) - -diff --git a/protocol/openthread/platform-abstraction/efr32/misc.c b/protocol/openthread/platform-abstraction/efr32/misc.c -index 2ed8355..66fc003 100644 ---- a/protocol/openthread/platform-abstraction/efr32/misc.c -+++ b/protocol/openthread/platform-abstraction/efr32/misc.c -@@ -36,6 +36,10 @@ - #include "em_rmu.h" - #include "platform-efr32.h" - -+#ifdef SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT -+#include "btl_interface.h" -+#endif // SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT -+ - static uint32_t sResetCause; - - void efr32MiscInit(void) -@@ -53,6 +57,26 @@ void otPlatReset(otInstance *aInstance) - NVIC_SystemReset(); - } - -+void otPlatRebootBootloader(otInstance *aInstance) -+{ -+ OT_UNUSED_VARIABLE(aInstance); -+ -+#if defined(SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT) -+ BootloaderResetCause_t* resetCause = (BootloaderResetCause_t*) (RAM_MEM_BASE); -+ resetCause->reason = BOOTLOADER_RESET_REASON_BOOTLOAD; -+ resetCause->signature = BOOTLOADER_RESET_SIGNATURE_VALID; -+#endif -+ -+#if defined(RMU_PRESENT) -+ // Clear resetcause -+ RMU->CMD = RMU_CMD_RCCLR; -+ // Trigger a software system reset -+ RMU->CTRL = (RMU->CTRL & ~_RMU_CTRL_SYSRMODE_MASK) | RMU_CTRL_SYSRMODE_EXTENDED; -+#endif -+ -+ NVIC_SystemReset(); -+} -+ - otPlatResetReason otPlatGetResetReason(otInstance *aInstance) - { - OT_UNUSED_VARIABLE(aInstance); --- -2.39.2 - From 0ab2f5064c16c3fe52bc5588a641f1aa628883cc Mon Sep 17 00:00:00 2001 From: Tim Lunn Date: Thu, 28 Dec 2023 19:09:15 +1100 Subject: [PATCH 5/9] manifest: update openthread enable bootloader define --- manifests/defaults.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/manifests/defaults.json b/manifests/defaults.json index 31b94ca1..c7c8c5d0 100644 --- a/manifests/defaults.json +++ b/manifests/defaults.json @@ -16,7 +16,7 @@ }, "ot-rcp": { "components": "bootloader_interface", - "extra_c_defs": "'-DOPENTHREAD_CONFIG_NCP_REBOOT_BOOTLOADER_ENABLE=1'" + "extra_c_defs": "'-DOPENTHREAD_CONFIG_PLATFORM_BOOTLOADER_MODE_ENABLE=1'" } } \ No newline at end of file From 8d1354b3949e74a28d8e8e30853585e7282089f7 Mon Sep 17 00:00:00 2001 From: Tim Lunn Date: Thu, 4 Jan 2024 12:30:46 +1100 Subject: [PATCH 6/9] Build with zigbee_mfglib https://github.com/NabuCasa/silabs-firmware-builder/issues/39 --- manifests/defaults.json | 4 ++-- manifests/yellow.json | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/manifests/defaults.json b/manifests/defaults.json index c7c8c5d0..d9056880 100644 --- a/manifests/defaults.json +++ b/manifests/defaults.json @@ -2,7 +2,7 @@ "name": "Default settings", "target": "default", "ncp-uart-hw": { - "components": "zigbee_token_interface", + "components": "zigbee_token_interface,zigbee_mfglib", "configuration": { "SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE":64, "EMBER_APS_UNICAST_MESSAGE_COUNT":20, @@ -12,7 +12,7 @@ "extra_c_defs": "'-DEMBER_ADDRESS_TABLE_SIZE=16' '-DEMBER_MULTICAST_TABLE_SIZE=16'" }, "rcp-uart-802154": { - "components": "cpc_security_secondary_none" + "components": "cpc_security_secondary_none,zigbee_mfglib" }, "ot-rcp": { "components": "bootloader_interface", diff --git a/manifests/yellow.json b/manifests/yellow.json index 355d4478..bfc4e23c 100644 --- a/manifests/yellow.json +++ b/manifests/yellow.json @@ -3,10 +3,10 @@ "target": "yellow", "device": "MGM210PA32JIA", "ncp-uart-hw": { - "components": "simple_led:board_activity,zigbee_token_interface" + "components": "simple_led:board_activity,zigbee_token_interface,zigbee_mfglib" }, "rcp-uart-802154": { - "components": "simple_led:board_activity,cpc_security_secondary_none" + "components": "simple_led:board_activity,cpc_security_secondary_none,zigbee_mfglib" }, "ot-rcp": { From f6de87665d2f43f0394ed4dd1c110d06d59983ba Mon Sep 17 00:00:00 2001 From: puddly <32534428+puddly@users.noreply.github.com> Date: Thu, 4 Jan 2024 12:34:19 -0500 Subject: [PATCH 7/9] Disable ZGP on multi-PAN https://github.com/NabuCasa/silabs-firmware-builder/pull/45 --- .github/workflows/build.yaml | 1 + .github/workflows/silabs-firmware-build.yaml | 4 ++++ manifests/defaults.json | 3 ++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/.github/workflows/build.yaml b/.github/workflows/build.yaml index 5b675033..9de8ed76 100644 --- a/.github/workflows/build.yaml +++ b/.github/workflows/build.yaml @@ -115,6 +115,7 @@ jobs: project_name: "rcp-uart-802154" device: ${{ matrix.device }} components: ${{ matrix.components }} + without_components: ${{ matrix.without_components }} configuration: ${{ matrix.configuration }} patchpath: "RCPMultiPAN/${{ matrix.name }}" sdkpatchpath: "RCPMultiPAN/GeckoSDK" diff --git a/.github/workflows/silabs-firmware-build.yaml b/.github/workflows/silabs-firmware-build.yaml index 1446c7e1..93bc086e 100644 --- a/.github/workflows/silabs-firmware-build.yaml +++ b/.github/workflows/silabs-firmware-build.yaml @@ -21,6 +21,9 @@ on: components: required: false type: string + without_components: + required: false + type: string configuration: required: false type: string @@ -63,6 +66,7 @@ jobs: run: | slc generate \ --with="${{ inputs.device }},${{ inputs.components }}" \ + --without="${{ inputs.without_components }}" \ --project-file="${{ inputs.project_file }}" \ --export-destination=${{ inputs.firmware_name }} \ --copy-proj-sources --copy-sdk-sources --new-project --force \ diff --git a/manifests/defaults.json b/manifests/defaults.json index d9056880..41dacfa1 100644 --- a/manifests/defaults.json +++ b/manifests/defaults.json @@ -12,7 +12,8 @@ "extra_c_defs": "'-DEMBER_ADDRESS_TABLE_SIZE=16' '-DEMBER_MULTICAST_TABLE_SIZE=16'" }, "rcp-uart-802154": { - "components": "cpc_security_secondary_none,zigbee_mfglib" + "components": "cpc_security_secondary_none,zigbee_mfglib", + "without_components": "ot_rcp_gp_interface" }, "ot-rcp": { "components": "bootloader_interface", From 425245f914ba71e2ea2730265b66d2aa75685104 Mon Sep 17 00:00:00 2001 From: Tim Lunn Date: Fri, 5 Jan 2024 12:12:28 +1100 Subject: [PATCH 8/9] Add the EFR32 watchdog to RPC firmware (#33) https://github.com/NabuCasa/silabs-firmware-builder/pull/33 --- .github/workflows/build.yaml | 2 + .github/workflows/silabs-firmware-build.yaml | 22 +++++ Dockerfile | 1 + .../inc/nc_efr32_wdog.h | 26 ++++++ .../nc_efr32_watchdog.slcc | 38 ++++++++ .../nc_efr32_watchdog.slce | 8 ++ .../src/nc_efr32_wdog.c | 92 +++++++++++++++++++ manifests/defaults.json | 3 +- 8 files changed, 191 insertions(+), 1 deletion(-) create mode 100644 gecko_sdk_extensions/nc_efr32_watchdog_extension/inc/nc_efr32_wdog.h create mode 100644 gecko_sdk_extensions/nc_efr32_watchdog_extension/nc_efr32_watchdog.slcc create mode 100644 gecko_sdk_extensions/nc_efr32_watchdog_extension/nc_efr32_watchdog.slce create mode 100644 gecko_sdk_extensions/nc_efr32_watchdog_extension/src/nc_efr32_wdog.c diff --git a/.github/workflows/build.yaml b/.github/workflows/build.yaml index 9de8ed76..6adc5dac 100644 --- a/.github/workflows/build.yaml +++ b/.github/workflows/build.yaml @@ -85,6 +85,7 @@ jobs: components: ${{ matrix.components }} configuration: ${{ matrix.configuration }} patchpath: "EmberZNet/${{ matrix.name }}" + slcp_yaml_changes: ${{ matrix.slcp_yaml_changes }} extra_c_defs: ${{ matrix.extra_c_defs }} sdk_version: ${{ needs.build-container.outputs.sdk_version}} metadata_fw_type: "ncp-uart-hw" @@ -119,6 +120,7 @@ jobs: configuration: ${{ matrix.configuration }} patchpath: "RCPMultiPAN/${{ matrix.name }}" sdkpatchpath: "RCPMultiPAN/GeckoSDK" + slcp_yaml_changes: ${{ matrix.slcp_yaml_changes }} extra_c_defs: ${{ matrix.extra_c_defs }} sdk_version: ${{ needs.build-container.outputs.sdk_version}} baudrate: ${{ matrix.baudrate }} diff --git a/.github/workflows/silabs-firmware-build.yaml b/.github/workflows/silabs-firmware-build.yaml index 93bc086e..b93ab2d9 100644 --- a/.github/workflows/silabs-firmware-build.yaml +++ b/.github/workflows/silabs-firmware-build.yaml @@ -46,6 +46,9 @@ on: required: false default: "null" type: string + slcp_yaml_changes: + required: false + type: string jobs: firmware-build: @@ -62,6 +65,19 @@ jobs: - name: Adjust permission shell: bash run: chown builder . + + - name: Link SDK extensions + shell: bash + run: | + # XXX: slc-cli does not actually work when the extensions aren't in the SDK! + ln -s $PWD/gecko_sdk_extensions /gecko_sdk/extension + + - name: Trust SDK extensions + run: | + for ext in /gecko_sdk/extension/*/; do + slc signature trust --extension-path="$ext" + done + - name: Generate Firmware Project run: | slc generate \ @@ -98,6 +114,12 @@ jobs: patch -p1 < $patch done + - name: Patch SLCP project file + if: "${{ inputs.slcp_yaml_changes != '' }}" + run: | + cd ${{ inputs.firmware_name }} + yq --in-place --yaml-output '${{ inputs.slcp_yaml_changes }}' "${{ inputs.project_name }}.slcp" + - name: Build Firmware run: | cd ${{ inputs.firmware_name }} diff --git a/Dockerfile b/Dockerfile index b053f6c2..8929e12d 100644 --- a/Dockerfile +++ b/Dockerfile @@ -10,6 +10,7 @@ RUN \ git \ git-lfs \ jq \ + yq \ libgl1 \ make \ default-jre-headless \ diff --git a/gecko_sdk_extensions/nc_efr32_watchdog_extension/inc/nc_efr32_wdog.h b/gecko_sdk_extensions/nc_efr32_watchdog_extension/inc/nc_efr32_wdog.h new file mode 100644 index 00000000..d1af5b8b --- /dev/null +++ b/gecko_sdk_extensions/nc_efr32_watchdog_extension/inc/nc_efr32_wdog.h @@ -0,0 +1,26 @@ +/***************************************************************************//** + * @file nc_efr32_wdog.h + * @brief Legacy HAL Watchdog + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories, Inc, www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include +#include "em_cmu.h" +#include "em_wdog.h" +#include "em_rmu.h" +#include "sli_cpc_timer.h" +#include "sl_component_catalog.h" + +void nc_enable_watchdog(void); +void nc_periodic_timer(sli_cpc_timer_handle_t *handle, void *data); \ No newline at end of file diff --git a/gecko_sdk_extensions/nc_efr32_watchdog_extension/nc_efr32_watchdog.slcc b/gecko_sdk_extensions/nc_efr32_watchdog_extension/nc_efr32_watchdog.slcc new file mode 100644 index 00000000..688ae1ba --- /dev/null +++ b/gecko_sdk_extensions/nc_efr32_watchdog_extension/nc_efr32_watchdog.slcc @@ -0,0 +1,38 @@ +root_path: ./ +id: nc_efr32_watchdog +label: EFR32 Watchdog +package: ext-comp +category: External Components +quality: production +description: > + EFR32 Watchdog. +requires: + - name: component_catalog + - name: emlib_wdog + - name: emlib_wdog +provides: + - name: nc_efr32_watchdog + +source: + - path: src/nc_efr32_wdog.c + +include: + - path: inc + file_list: + - path: nc_efr32_wdog.h + +template_contribution: + - name: component_catalog + value: nc_efr32_watchdog + - name: event_handler + value: + event: service_init + include: "nc_efr32_wdog.h" + handler: nc_enable_watchdog + priority: 9999 # load very very late + - name: event_handler + value: + event: service_process_action + include: "nc_efr32_wdog.h" + handler: nc_poke_watchdog + priority: 9999 # run last diff --git a/gecko_sdk_extensions/nc_efr32_watchdog_extension/nc_efr32_watchdog.slce b/gecko_sdk_extensions/nc_efr32_watchdog_extension/nc_efr32_watchdog.slce new file mode 100644 index 00000000..ba087a3f --- /dev/null +++ b/gecko_sdk_extensions/nc_efr32_watchdog_extension/nc_efr32_watchdog.slce @@ -0,0 +1,8 @@ +id: "nc_efr32_watchdog" +label: "EFR32 Watchdog" +version: "1.0.0" +sdk: + id: "gecko_sdk" + version: 4.3.2 +component_path: + - path: "./" \ No newline at end of file diff --git a/gecko_sdk_extensions/nc_efr32_watchdog_extension/src/nc_efr32_wdog.c b/gecko_sdk_extensions/nc_efr32_watchdog_extension/src/nc_efr32_wdog.c new file mode 100644 index 00000000..21979c00 --- /dev/null +++ b/gecko_sdk_extensions/nc_efr32_watchdog_extension/src/nc_efr32_wdog.c @@ -0,0 +1,92 @@ +/***************************************************************************//** + * @file nc_efr32_wdog.c + * @brief Legacy HAL Watchdog + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories, Inc, www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "em_wdog.h" +#include "nc_efr32_wdog.h" + +static bool feed_watchdog_on_warn_interrupt; + + +#if (_SILICON_LABS_32B_SERIES >= 1) +void WDOG0_IRQHandler(void) +{ + uint32_t interrupts; + + interrupts = WDOGn_IntGet(WDOG0); + WDOGn_IntClear(WDOG0, interrupts); + + if (feed_watchdog_on_warn_interrupt) { + WDOGn_Feed(WDOG0); + feed_watchdog_on_warn_interrupt = false; + } +} +#endif + + +void nc_enable_watchdog(void) +{ + // Enable LE interface +#if !defined(_SILICON_LABS_32B_SERIES_2) + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2) && !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + CMU_ClockEnable(cmuClock_WDOG0, true); +#endif + + // Make sure FULL reset is used on WDOG timeout +#if defined(_RMU_CTRL_WDOGRMODE_MASK) + RMU_ResetControl(rmuResetWdog, rmuResetModeFull); +#endif + + WDOG_Init_TypeDef init = WDOG_INIT_DEFAULT; + init.enable = false; + init.debugRun = false; + init.perSel = wdogPeriod_64k; // 2 seconds + init.warnSel = wdogWarnTime75pct; + +#if defined(_WDOG_CTRL_CLKSEL_MASK) + init.clkSel = wdogClkSelLFRCO; +#else + // Series 2 devices select watchdog oscillator with the CMU. + CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO); +#endif + + WDOGn_Unlock(WDOG0); + WDOGn_Init(WDOG0, &init); + + // Enable warning interrupt + NVIC_ClearPendingIRQ(WDOG0_IRQn); + WDOGn_IntClear(WDOG0, WDOG_IF_WARN); + NVIC_EnableIRQ(WDOG0_IRQn); + WDOGn_IntEnable(WDOG0, WDOG_IEN_WARN); + + WDOGn_Enable(WDOG0, true); + WDOGn_Feed(WDOG0); + + feed_watchdog_on_warn_interrupt = false; +} + + +void nc_poke_watchdog() +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + feed_watchdog_on_warn_interrupt = true; + CORE_EXIT_ATOMIC(); +} diff --git a/manifests/defaults.json b/manifests/defaults.json index 41dacfa1..f8a8f9a3 100644 --- a/manifests/defaults.json +++ b/manifests/defaults.json @@ -13,7 +13,8 @@ }, "rcp-uart-802154": { "components": "cpc_security_secondary_none,zigbee_mfglib", - "without_components": "ot_rcp_gp_interface" + "without_components": "ot_rcp_gp_interface", + "slcp_yaml_changes": ". += {\"sdk_extension\": [{\"id\": \"nc_efr32_watchdog\", \"version\": \"1.0.0\"}]} | .component += [{\"from\": \"nc_efr32_watchdog\", \"id\": \"nc_efr32_watchdog\"}]" }, "ot-rcp": { "components": "bootloader_interface", From cbf300e84e449d9623517d68b84b0049cae964a2 Mon Sep 17 00:00:00 2001 From: Tim Lunn Date: Fri, 5 Jan 2024 14:31:06 +1100 Subject: [PATCH 9/9] Update .gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 .gitignore diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..496ee2ca --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +.DS_Store \ No newline at end of file