diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 668d2a9cab..9f2a4317ac 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1732,7 +1732,13 @@ def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth", data_width=8,
         udp_port                = 1234,
         buffer_depth            = 16,
         with_ip_broadcast       = True,
-        with_timing_constraints = True):
+        with_timing_constraints = True,
+        interface               = "crossbar",
+        endianness              = "big",
+        tx_cdc_depth            = 32,
+        tx_cdc_buffered         = True,
+        rx_cdc_buffered         = True,
+        tx_cdc_depth            = 32):
         # Imports
         from liteeth.core import LiteEthUDPIPCore
         from liteeth.frontend.etherbone import LiteEthEtherbone
@@ -1751,6 +1757,12 @@ def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth", data_width=8,
             dw          = data_width,
             with_ip_broadcast = with_ip_broadcast,
             with_sys_datapath = with_sys_datapath,
+            tx_cdc_depth    = tx_cdc_depth,
+            tx_cdc_buffered = tx_cdc_buffered,
+            rx_cdc_depth    = rx_cdc_depth,
+            rx_cdc_buffered = rx_cdc_buffered,
+            interface   = interface,
+            endianness  = endianness,
         )
         if not with_sys_datapath:
             # Use PHY's eth_tx/eth_rx clock domains.