From b36923914f62f47fea28a8679432ae5b94608425 Mon Sep 17 00:00:00 2001 From: Charles-Henri Mousset Date: Mon, 30 Dec 2024 17:47:15 +0100 Subject: [PATCH] [enh] Added differential input for ICE40 --- litex/build/lattice/common.py | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/litex/build/lattice/common.py b/litex/build/lattice/common.py index 28bf247ad4..f5f221d2ee 100644 --- a/litex/build/lattice/common.py +++ b/litex/build/lattice/common.py @@ -425,6 +425,29 @@ class LatticeiCE40DifferentialOutput: def lower(dr): return LatticeiCE40DifferentialOutputImpl(dr.i, dr.o_p, dr.o_n) +# iCE40 Differential Input ------------------------------------------------------------------------- + +class LatticeiCE40DifferentialInputImpl(Module): + def __init__(self, i_p, o): + self.specials += [ + Instance("SB_IO", + p_PIN_TYPE = C(0b000001, 6), # PIN_INPUT + p_IO_STANDARD = "SB_LVDS_INPUT", + p_PULLUP = C(0b0, 1), + p_NEG_TRIGGER = C(0b0, 1), + io_PACKAGE_PIN = i_p, + o_D_IN_0 = o, + i_OUTPUT_ENABLE= C(0b1, 1) + ), + # according to https://www.latticesemi.com/support/answerdatabase/6/1/6/6161 the n pin + # will get assigned to the LVDS input automatically + ] + +class LatticeiCE40DifferentialInput: + @staticmethod + def lower(dr): + return LatticeiCE40DifferentialInputImpl(dr.i_p, dr.o) + # iCE40 DDR Output --------------------------------------------------------------------------------- class LatticeiCE40DDROutputImpl(Module): @@ -520,6 +543,7 @@ def lower(dr): AsyncResetSynchronizer: LatticeiCE40AsyncResetSynchronizer, Tristate: LatticeiCE40Tristate, DifferentialOutput: LatticeiCE40DifferentialOutput, + DifferentialInput: LatticeiCE40DifferentialInput, DDROutput: LatticeiCE40DDROutput, DDRInput: LatticeiCE40DDRInput, SDROutput: LatticeiCE40SDROutput,