Support for Python 3.13

[david-sawatzke]

After updating to Python 1.13, litex doesn't build anymore (for e.g. the colorlight target) with the following error:

Traceback (most recent call last):
  File "[..]/colorlight_5a_75x.py", line 259, in <module>
    main()
    ~~~~^^
  File "[..]/colorlight_5a_75x.py", line 237, in main
    soc = BaseSoC(board=args.board, revision=args.revision,
        sys_clk_freq     = args.sys_clk_freq,
    ...<8 lines>...
        **parser.soc_argdict
    )
  File "[..]/colorlight_5a_75x.py", line 162, in __init__
    SoCCore.__init__(self, platform, int(sys_clk_freq), ident="LiteX SoC on Colorlight " + board.upper(), **kwargs)
    ~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "[..]litex_inst/litex/litex/soc/integration/soc_core.py", line 214, in __init__
    self.add_controller("ctrl")
    ~~~~~~~~~~~~~~~~~~~^^^^^^^^
  File "[..]litex_inst/litex/litex/soc/integration/soc.py", line 1055, in add_controller
    self.add_module(name=name, module=SoCController(**kwargs))
                                      ~~~~~~~~~~~~~^^^^^^^^^^
  File "[..]litex_inst/litex/litex/soc/integration/soc.py", line 890, in __init__
    self._reset = CSRStorage(fields=[
                  ~~~~~~~~~~^^^^^^^^^
        CSRField("soc_rst", size=1, offset=0, pulse=True, description="""Write `1` to this register to reset the full SoC (Pulse Reset)"""),
        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
        CSRField("cpu_rst", size=1, offset=1,             description="""Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset)"""),
        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
    ])
    ^^
  File "[..]litex_inst/litex/litex/soc/interconnect/csr.py", line 388, in __init__
    _CompoundCSR.__init__(self, size, name, n)
    ~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^
  File "[..]litex_inst/litex/litex/soc/interconnect/csr.py", line 136, in __init__
    _CSRBase.__init__(self, size, name, n)
    ~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^
  File "[..]litex_inst/litex/litex/soc/interconnect/csr.py", line 53, in __init__
    raise ValueError("Cannot extract CSR name from code, need to specify.")

litex_sim also fails inside migen with:

Traceback (most recent call last):
  File "[..]/.venv/bin/litex_sim", line 8, in <module>
    sys.exit(main())
             ~~~~^^
  File "[..]/litex_inst/litex/litex/tools/litex_sim.py", line 485, in main
    conf_soc = SimSoC(**soc_kwargs)
  File "[..]/litex_inst/litex/litex/tools/litex_sim.py", line 191, in __init__
    self.crg = CRG(platform.request("sys_clk"))
               ~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "[..]/litex_inst/litex/litex/build/io.py", line 222, in __init__
    self.clock_domains.cd_por = ClockDomain(reset_less=True)
                                ~~~~~~~~~~~^^^^^^^^^^^^^^^^^
  File "[..]/litex_inst/migen/migen/fhdl/structure.py", line 710, in __init__

which is related to m-labs/migen#297 and probably the same root cause for both

[Chandler-Kluser]

Python 3.13, same thing happens here, too