We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Render FPGA LUTs as a digital circuit diagram.
FPGA devices use look-up table (LUT) to implement arbitrary combinatorial logic.
for N bit LUT configuration can be represented as an 2^N long number.
N
2^N
Most typical LUTs are LUT4 with N = 4 with 2^N = 16 bit config word shown on the figure below.
N = 4
2^N = 16
Mux representation of LUT is not the most human-readable one.
Any configuration of the LUT can be rendered as a digital circuit diagram.
https://github.com/drom/icedrom -- is an JavaScript libratry that can render LUT config as digital circuit diagram.
Read more HERE https://observablehq.com/@drom/lut4-decoder
The text was updated successfully, but these errors were encountered:
This would be excellent to be part of a sphinx extension - potentially http://sphinxcontrib-verilog-diagrams.rtfd.io/ too
Sphinx Verilog Diagrams — Sphinx Verilog 0.0-19-gdca0472 documentation
Sorry, something went wrong.
No branches or pull requests
Brief explanation
Render FPGA LUTs as a digital circuit diagram.
Detailed Explanation
FPGA devices use look-up table (LUT) to implement arbitrary combinatorial logic.
for
N
bit LUT configuration can be represented as an2^N
long number.Most typical LUTs are LUT4 with
N = 4
with2^N = 16
bit config word shown on the figure below.Mux representation of LUT is not the most human-readable one.
Any configuration of the LUT can be rendered as a digital circuit diagram.
https://github.com/drom/icedrom -- is an JavaScript libratry that can render LUT config as digital circuit diagram.
Read more HERE https://observablehq.com/@drom/lut4-decoder
The text was updated successfully, but these errors were encountered: