diff --git a/src/nes.gao b/src/nes.gao index 79fe16a..d46a3ec 100644 --- a/src/nes.gao +++ b/src/nes.gao @@ -2,7 +2,7 @@ 3.0 Standard - + clk loading @@ -136,7 +136,6 @@ sdram/cycle[1] sdram/cycle[0] - sdram/oeB nes/prg_allow nes/prg_read @@ -159,6 +158,177 @@ loader/ines[5][1] loader/ines[5][0] + + rv_addr_Z[9] + rv_addr_Z[8] + rv_addr_Z[7] + rv_addr_Z[6] + rv_addr_Z[5] + rv_addr_Z[4] + rv_addr_Z[3] + rv_addr_Z[2] + + rv_valid_Z + + flash_wstrb[3] + flash_wstrb[2] + flash_wstrb[1] + flash_wstrb[0] + + + rv_dout_Z[15] + rv_dout_Z[14] + rv_dout_Z[13] + rv_dout_Z[12] + rv_dout_Z[11] + rv_dout_Z[10] + rv_dout_Z[9] + rv_dout_Z[8] + rv_dout_Z[7] + rv_dout_Z[6] + rv_dout_Z[5] + rv_dout_Z[4] + rv_dout_Z[3] + rv_dout_Z[2] + rv_dout_Z[1] + rv_dout_Z[0] + + + rv_wdata_Z[15] + rv_wdata_Z[14] + rv_wdata_Z[13] + rv_wdata_Z[12] + rv_wdata_Z[11] + rv_wdata_Z[10] + rv_wdata_Z[9] + rv_wdata_Z[8] + rv_wdata_Z[7] + rv_wdata_Z[6] + rv_wdata_Z[5] + rv_wdata_Z[4] + rv_wdata_Z[3] + rv_wdata_Z[2] + rv_wdata_Z[1] + rv_wdata_Z[0] + + rv_req + rv_req_ack_Z + + rv_ds[1] + rv_ds[0] + + rv_word + + O_sdram_cs_n + O_sdram_ras_n + O_sdram_cas_n + O_sdram_wen_n + + + O_sdram_addr[10] + O_sdram_addr[9] + O_sdram_addr[8] + O_sdram_addr[7] + O_sdram_addr[6] + O_sdram_addr[5] + O_sdram_addr[4] + O_sdram_addr[3] + O_sdram_addr[2] + O_sdram_addr[1] + O_sdram_addr[0] + + + IO_sdram_dq[31] + IO_sdram_dq[30] + IO_sdram_dq[29] + IO_sdram_dq[28] + IO_sdram_dq[27] + IO_sdram_dq[26] + IO_sdram_dq[25] + IO_sdram_dq[24] + IO_sdram_dq[23] + IO_sdram_dq[22] + IO_sdram_dq[21] + IO_sdram_dq[20] + IO_sdram_dq[19] + IO_sdram_dq[18] + IO_sdram_dq[17] + IO_sdram_dq[16] + IO_sdram_dq[15] + IO_sdram_dq[14] + IO_sdram_dq[13] + IO_sdram_dq[12] + IO_sdram_dq[11] + IO_sdram_dq[10] + IO_sdram_dq[9] + IO_sdram_dq[8] + IO_sdram_dq[7] + IO_sdram_dq[6] + IO_sdram_dq[5] + IO_sdram_dq[4] + IO_sdram_dq[3] + IO_sdram_dq[2] + IO_sdram_dq[1] + IO_sdram_dq[0] + + + O_sdram_ba[1] + O_sdram_ba[0] + + + O_sdram_dqm[3] + O_sdram_dqm[2] + O_sdram_dqm[1] + O_sdram_dqm[0] + + sdram/oeB + + O_sdram_addr_d[10] + O_sdram_addr_d[9] + O_sdram_addr_d[8] + O_sdram_addr_d[7] + O_sdram_addr_d[6] + O_sdram_addr_d[5] + O_sdram_addr_d[4] + O_sdram_addr_d[3] + O_sdram_addr_d[2] + O_sdram_addr_d[1] + O_sdram_addr_d[0] + + + IO_sdram_dq_in[31] + IO_sdram_dq_in[30] + IO_sdram_dq_in[29] + IO_sdram_dq_in[28] + IO_sdram_dq_in[27] + IO_sdram_dq_in[26] + IO_sdram_dq_in[25] + IO_sdram_dq_in[24] + IO_sdram_dq_in[23] + IO_sdram_dq_in[22] + IO_sdram_dq_in[21] + IO_sdram_dq_in[20] + IO_sdram_dq_in[19] + IO_sdram_dq_in[18] + IO_sdram_dq_in[17] + IO_sdram_dq_in[16] + IO_sdram_dq_in[15] + IO_sdram_dq_in[14] + IO_sdram_dq_in[13] + IO_sdram_dq_in[12] + IO_sdram_dq_in[11] + IO_sdram_dq_in[10] + IO_sdram_dq_in[9] + IO_sdram_dq_in[8] + IO_sdram_dq_in[7] + IO_sdram_dq_in[6] + IO_sdram_dq_in[5] + IO_sdram_dq_in[4] + IO_sdram_dq_in[3] + IO_sdram_dq_in[2] + IO_sdram_dq_in[1] + IO_sdram_dq_in[0] + @@ -172,8 +342,16 @@ loading_r - - + + + rv_valid_Z + + + + + iosys/flash_loaded + + @@ -190,8 +368,8 @@ - - + + @@ -206,8 +384,8 @@ - M1 + M2 - 1111101111011101 + 0011100010011110 diff --git a/src/nestang_top.sv b/src/nestang_top.sv index 8882e83..7ce5df4 100644 --- a/src/nestang_top.sv +++ b/src/nestang_top.sv @@ -194,6 +194,7 @@ reg [7:0] reset_cnt = 255; // reset for 255 cycles before start everything always @(posedge clk) begin reset_cnt <= reset_cnt == 0 ? 0 : reset_cnt - 1; if (reset_cnt == 0) +// if (reset_cnt == 0 && s1) // for nano sys_resetn <= ~(nes_btn[5] && nes_btn[2]); // 8BitDo Home button = Select + Down end diff --git a/src/sdram_nes.v b/src/sdram_nes.v index 8a968ea..2df1e81 100644 --- a/src/sdram_nes.v +++ b/src/sdram_nes.v @@ -20,15 +20,12 @@ module sdram_nes #( // Clock frequency, max 66.7Mhz with current set of T_xx/CAS parameters. parameter FREQ = 64_800_000, - // Time delays for 66.7Mhz max clock (min clock cycle 15ns) - // The SDRAM supports max 166.7Mhz (RP/RCD/RC need changes) - // Alliance AS4C32M16SB-7TIN 512Mb - parameter [3:0] CAS = 4'd2, // 2/3 cycles, set in mode register - parameter [3:0] T_WR = 4'd2, // 2 cycles, write recovery - parameter [3:0] T_MRD= 4'd2, // 2 cycles, mode register set - parameter [3:0] T_RP = 4'd1, // 15ns, precharge to active - parameter [3:0] T_RCD= 4'd1, // 15ns, active to r/w - parameter [3:0] T_RC = 4'd4 // 63ns, ref/active to ref/active + parameter [4:0] CAS = 4'd2, // 2/3 cycles, set in mode register + parameter [4:0] T_WR = 4'd2, // 2 cycles, write recovery + parameter [4:0] T_MRD= 4'd2, // 2 cycles, mode register set + parameter [4:0] T_RP = 4'd2, // 15ns, precharge to active + parameter [4:0] T_RCD= 4'd2, // 15ns, active to r/w + parameter [4:0] T_RC = 4'd6 // 63ns, ref/active to ref/active ) ( inout reg [SDRAM_DATA_WIDTH-1:0] SDRAM_DQ, // 16 bit bidirectional data bus output [SDRAM_ROW_WIDTH-1:0] SDRAM_A, // 13 bit multiplexed address bus @@ -76,9 +73,9 @@ reg [SDRAM_DATA_WIDTH-1:0] dq_out; assign SDRAM_DQ = dq_oen ? {SDRAM_DATA_WIDTH{1'bz}} : dq_out; wire [SDRAM_DATA_WIDTH-1:0] dq_in = SDRAM_DQ; // DQ input reg [3:0] cmd; -reg [12:0] a; +reg [SDRAM_ROW_WIDTH-1:0] a; assign {SDRAM_nCS, SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} = cmd; -assign SDRAM_A = SDRAM_ROW_WIDTH'(a); +assign SDRAM_A = a; assign SDRAM_CKE = 1'b1; @@ -98,7 +95,7 @@ localparam [10:0] MODE_REG = {4'b0, CAS[2:0], BURST_MODE, BURST_LEN}; localparam RFRSH_CYCLES = 9'd501; // state -reg [11:0] cycle; // one hot encoded +reg [16:0] cycle; // one hot encoded reg normal, setup; reg cfg_now; // pulse for configuration @@ -208,27 +205,29 @@ always @(posedge clk) begin // setup process if (setup) begin - cycle <= {cycle[10:0], 1'b0}; // cycle 0-11 for setup + cycle <= {cycle[15:0], 1'b0}; // cycle 0-16 for setup // configuration sequence if (cycle[0]) begin // precharge all cmd <= CMD_PreCharge; a[10] <= 1'b1; + SDRAM_BA <= 0; end - if (cycle[T_RP]) begin + if (cycle[T_RP]) begin // 2 // 1st AutoRefresh cmd <= CMD_AutoRefresh; end - if (cycle[T_RP+T_RC]) begin + if (cycle[T_RP+T_RC]) begin // 8 // 2nd AutoRefresh cmd <= CMD_AutoRefresh; end - if (cycle[T_RP+T_RC+T_RC]) begin + if (cycle[T_RP+T_RC+T_RC]) begin // 14 // set register cmd <= CMD_SetModeReg; a[10:0] <= MODE_REG; + SDRAM_BA <= 0; end - if (cycle[T_RP+T_RC+T_RC+T_MRD]) begin + if (cycle[T_RP+T_RC+T_RC+T_MRD]) begin // 16 setup <= 0; normal <= 1; cycle <= 1; @@ -237,7 +236,7 @@ always @(posedge clk) begin end if (normal) begin if (clkref & ~clkref_r) // go to cycle 5 after clkref posedge - cycle <= 12'b0000_0010_0000; + cycle[5:0] <= 6'b10_0000; else cycle[5:0] <= {cycle[4:0], cycle[5]}; refresh_cnt <= refresh_cnt + 1'd1;