From dbd0187d0f92abdf8e895309c20fc26874e91dd7 Mon Sep 17 00:00:00 2001 From: nand2mario Date: Sun, 31 Mar 2024 22:41:01 +0800 Subject: [PATCH] iosys: report CORE_ID to firmware. menu screen shows correctly --- src/iosys/gowin_dpb_menu.v | 8 +- src/iosys/iosys.v | 13 ++- src/iosys/textdisp.v | 2 +- src/nestang_top.sv | 5 +- src/tang_primer_25k/gowin_pll_nes.ipc | 145 ++++++++++++++++++++++++++ src/tang_primer_25k/gowin_pll_nes.mod | 59 +++++++++++ src/tang_primer_25k/gowin_pll_nes.v | 137 ++++++++++++++++++++++++ 7 files changed, 359 insertions(+), 10 deletions(-) create mode 100644 src/tang_primer_25k/gowin_pll_nes.ipc create mode 100644 src/tang_primer_25k/gowin_pll_nes.mod create mode 100644 src/tang_primer_25k/gowin_pll_nes.v diff --git a/src/iosys/gowin_dpb_menu.v b/src/iosys/gowin_dpb_menu.v index 5b4d5bd..6345851 100644 --- a/src/iosys/gowin_dpb_menu.v +++ b/src/iosys/gowin_dpb_menu.v @@ -90,10 +90,10 @@ defparam dpb_inst_0.INIT_RAM_18 = 256'h00000000000000000000000000000000000000000 defparam dpb_inst_0.INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam dpb_inst_0.INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam dpb_inst_0.INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam dpb_inst_0.INIT_RAM_1C = 256'h383070000700000001FF0000000F00000001FF0000001F00000001FF0000001C; -defparam dpb_inst_0.INIT_RAM_1D = 256'hBC73DFE7BC383DCEF79C7F9FF7FC383DFEFF9E7F9FF7F83878FC7F8F00000000; -defparam dpb_inst_0.INIT_RAM_1E = 256'hFC387DFCE39F7F9CE7FC38700EE39F73DCE71C38707EE3BC71DCE71C3839FEE3; -defparam dpb_inst_0.INIT_RAM_1F = 256'h00003F80000000000000007F8000000000000000701CE7783838F8E3877F1CE7; +defparam dpb_inst_0.INIT_RAM_1C = 256'h380E0731F000000000384E0731F000000001FF7EFF30F000000001FF3CFF30F0; // LOGO: generated from src/assets/logo.py +defparam dpb_inst_0.INIT_RAM_1D = 256'h301C7719FC3870033F301C6719C038387F37301CE739CC381C7F33B00FC3F8F8; // \ +defparam dpb_inst_0.INIT_RAM_1E = 256'h0000000000001FC719FC183E7F3C301E6719CE187F7F3C301C7719FE3873033E; // | +defparam dpb_inst_0.INIT_RAM_1F = 256'h000000000000000000000007E0000000000000000E60000000000000001C0000; // / defparam dpb_inst_0.INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam dpb_inst_0.INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam dpb_inst_0.INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; diff --git a/src/iosys/iosys.v b/src/iosys/iosys.v index 0d2a487..0355106 100644 --- a/src/iosys/iosys.v +++ b/src/iosys/iosys.v @@ -30,7 +30,11 @@ // design are read in the correct order. `define PICOSOC_V -module iosys #(parameter FREQ=21_477_000) +module iosys #( + parameter FREQ=21_477_000, + parameter [14:0] COLOR_LOGO=15'b00000_10101_00000, + parameter [15:0] CORE_ID=1 // 1: nestang, 2: snestang +) ( input clk, // SNES mclk input hclk, // hdmi clock @@ -180,8 +184,10 @@ wire joystick_reg_sel = mem_valid && (mem_addr == 32'h 0200_0040); wire time_reg_sel = mem_valid && (mem_addr == 32'h0200_0050); // milli-seconds since start-up (overflows in 49 days) +wire id_reg_sel = mem_valid && (mem_addr == 32'h0200_0060); + assign mem_ready = ram_ready || textdisp_reg_char_sel || simpleuart_reg_div_sel || - romload_reg_ctrl_sel || romload_reg_data_sel || joystick_reg_sel || time_reg_sel || + romload_reg_ctrl_sel || romload_reg_data_sel || joystick_reg_sel || time_reg_sel || id_reg_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait) || ((simplespimaster_reg_byte_sel || simplespimaster_reg_word_sel) && !simplespimaster_reg_wait); @@ -190,6 +196,7 @@ assign mem_rdata = ram_ready ? ram_rdata : simpleuart_reg_div_sel ? simpleuart_reg_div_do : simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : time_reg_sel ? time_reg : + id_reg_sel ? {16'b0, CORE_ID} : (simplespimaster_reg_byte_sel | simplespimaster_reg_word_sel) ? simplespimaster_reg_do : 32'h 0000_0000; @@ -209,7 +216,7 @@ picorv32 #( ); // text display @ 0x0200_0000 -textdisp disp ( +textdisp #(.COLOR_LOGO(COLOR_LOGO)) disp ( .clk(clk), .hclk(hclk), .resetn(resetn), .overlay_x(overlay_x), .overlay_y(overlay_y), .overlay_color(overlay_color), .reg_char_we(textdisp_reg_char_sel ? mem_wstrb : 4'b0), diff --git a/src/iosys/textdisp.v b/src/iosys/textdisp.v index f04d454..d805975 100644 --- a/src/iosys/textdisp.v +++ b/src/iosys/textdisp.v @@ -20,7 +20,7 @@ module textdisp( localparam [14:0] COLOR_BACK = 15'b00000_00000_00000; localparam [14:0] COLOR_TEXT = 15'b10000_11111_11111; // yellow localparam [14:0] COLOR_CURSOR = 15'b10000_11000_11111; // orange -localparam [14:0] COLOR_LOGO = 15'b00000_10101_00000; // green +parameter [14:0] COLOR_LOGO = 15'b00000_10101_00000; // green // // Pixel output logic for characters and logo: diff --git a/src/nestang_top.sv b/src/nestang_top.sv index eb56878..3cfdd3d 100644 --- a/src/nestang_top.sv +++ b/src/nestang_top.sv @@ -370,7 +370,7 @@ wire [9:0] overlay_y; wire [14:0] overlay_color; // BGR5 // HDMI output -nes2hdmi u_hdmi ( +nes2hdmi u_hdmi ( // purple: RGB=440064 (010001000_00000000_01100100), BGR5=01100_00000_01000 .clk(clk), .resetn(sys_resetn), .color(color), .cycle(cycle), .scanline(scanline), .sample(sample >> 1), @@ -464,7 +464,8 @@ always @(posedge clk) begin // RV end end -iosys iosys ( +iosys #(.COLOR_LOGO(15'b01100_00000_01000), .CORE_ID(1) ) // purple nestang logo + iosys ( .clk(clk), .hclk(hclk), .resetn(sys_resetn), .overlay(overlay), .overlay_x(overlay_x), .overlay_y(overlay_y), diff --git a/src/tang_primer_25k/gowin_pll_nes.ipc b/src/tang_primer_25k/gowin_pll_nes.ipc new file mode 100644 index 0000000..c7e9ea4 --- /dev/null +++ b/src/tang_primer_25k/gowin_pll_nes.ipc @@ -0,0 +1,145 @@ +[General] +ipc_version=4 +file=gowin_pll_nes +module=gowin_pll_nes +target_device=gw5a25a-002 +type=clock_plladv +version=1.0 + +[Config] +AdvancedMode=false +ClkfbDivideFactorStatic=true +ClkfbDivideFactorStaticValue=1 +ClkfbInternal=true +ClkfboutExpectedFrequency=400 +ClkfboutTolerance=0.0 +ClkfboutVCODivideFactorStatic=true +ClkfboutVCODivideFactorStaticValue=49 +ClkfboutVCOFractionalDivideFactorStaticValue=0 +ClkinClockFrequency=50 +ClkinDividerFactorStatic=true +ClkinDividerFactorStaticValue=2 +ClkinDividerReset=false +Clkou1BPhaseStatic=true +Clkou2BPhaseStatic=true +Clkou3BPhaseStatic=true +Clkout0Bypass=false +Clkout0DutyCycleDynamic=false +Clkout0DutyCycleDynamicValue=0 +Clkout0DutyCycleStatic=true +Clkout0DutyTrimStatic=true +Clkout0DutyTrimStaticFalling=false +Clkout0DutyTrimStaticRising=true +Clkout0DutyTrimStaticStep=0 +Clkout0ExpectedFrequency=21.477 +Clkout0PhaseDynamic=false +Clkout0PhaseStatic=true +Clkout0PhaseStaticValue=0 +Clkout0Tolerance=0.2 +Clkout0VCODivideFactorStatic=true +Clkout0VCODivideFactorStaticValue=57 +Clkout0VCOFractionalDivideFactorStaticValue=0 +Clkout1Bypass=false +Clkout1DutyCycleDynamic=false +Clkout1DutyCycleDynamicValue=0 +Clkout1DutyCycleStatic=true +Clkout1DutyTrimStatic=true +Clkout1DutyTrimStaticFalling=false +Clkout1DutyTrimStaticRising=true +Clkout1DutyTrimStaticStep=0 +Clkout1ExpectedFrequency=64.431 +Clkout1PhaseDynamic=false +Clkout1PhaseStaticValue=0 +Clkout1Tolerance=0.2 +Clkout1VCODivideFactorStatic=true +Clkout1VCODivideFactorStaticValue=19 +Clkout2Bypass=false +Clkout2DutyCycleDynamic=false +Clkout2DutyCycleDynamicValue=0 +Clkout2DutyCycleStatic=true +Clkout2DutyTrimStatic=true +Clkout2DutyTrimStaticFalling=false +Clkout2DutyTrimStaticRising=true +Clkout2DutyTrimStaticStep=0 +Clkout2ExpectedFrequency=64.431 +Clkout2PhaseDynamic=false +Clkout2PhaseStaticValue=225 +Clkout2Tolerance=0.2 +Clkout2VCODivideFactorStatic=true +Clkout2VCODivideFactorStaticValue=19 +Clkout3Bypass=false +Clkout3DutyCycleDynamic=false +Clkout3DutyCycleDynamicValue=0 +Clkout3DutyCycleStatic=true +Clkout3DutyTrimStatic=true +Clkout3DutyTrimStaticFalling=false +Clkout3DutyTrimStaticRising=true +Clkout3DutyTrimStaticStep=0 +Clkout3ExpectedFrequency=400 +Clkout3PhaseDynamic=false +Clkout3PhaseStaticValue=0 +Clkout3Tolerance=0.0 +Clkout3VCODivideFactorStatic=true +Clkout3VCODivideFactorStaticValue=8 +Clkout4Bypass=false +Clkout4DutyCycleDynamic=false +Clkout4DutyCycleDynamicValue=0 +Clkout4DutyCycleStatic=true +Clkout4ExpectedFrequency=400 +Clkout4PhaseDynamic=false +Clkout4PhaseStatic=true +Clkout4PhaseStaticValue=0 +Clkout4Tolerance=0.0 +Clkout4VCODivideFactorStatic=true +Clkout4VCODivideFactorStaticValue=8 +Clkout5Bypass=false +Clkout5DutyCycleDynamic=false +Clkout5DutyCycleDynamicValue=0 +Clkout5DutyCycleStatic=true +Clkout5ExpectedFrequency=400 +Clkout5PhaseDynamic=false +Clkout5PhaseStatic=true +Clkout5PhaseStaticValue=0 +Clkout5Tolerance=0.0 +Clkout5VCODivideFactorStatic=true +Clkout5VCODivideFactorStaticValue=8 +Clkout6Bypass=false +Clkout6DutyCycleDynamic=false +Clkout6DutyCycleDynamicValue=0 +Clkout6DutyCycleStatic=true +Clkout6ExpectedFrequency=400 +Clkout6PhaseDynamic=false +Clkout6PhaseStatic=true +Clkout6PhaseStaticValue=0 +Clkout6Tolerance=0.0 +Clkout6VCODivideFactorStatic=true +Clkout6VCODivideFactorStaticValue=8 +ClkoutDividerReset=false +EnableCascade=false +EnableClkfbout=false +EnableClkout0Divider=false +EnableClkout1=true +EnableClkout1Divider=false +EnableClkout2=true +EnableClkout2Divider=false +EnableClkout3=false +EnableClkout3Divider=false +EnableClkout4=false +EnableClkout4Divider=false +EnableClkout5=false +EnableClkout5Divider=false +EnableClkout6=false +EnableClkout6Divider=false +EnableLock=false +EnableSsc=false +GeneralMode=true +ICPSELStatic=true +ICPSELStaticValue=X +LANG=0 +LPFCAPStaticValue=C0 +LPFRESStaticValue=X +LPFSELStatic=true +PLLPowerDown=false +PLLReset=false +clkfbExternal=false +clkfbExternalValue= diff --git a/src/tang_primer_25k/gowin_pll_nes.mod b/src/tang_primer_25k/gowin_pll_nes.mod new file mode 100644 index 0000000..c8f250e --- /dev/null +++ b/src/tang_primer_25k/gowin_pll_nes.mod @@ -0,0 +1,59 @@ +-series GW5A +-device GW5A-25 +-device_version A +-package MBGA121N +-part_number GW5A-LV25MG121NC1/I0 + + +-mod_name gowin_pll_nes +-file_name gowin_pll_nes +-path D:/Gowin/dev/nes-experiments/01.sdram_nes/src/primer25k/ +-type PLL_ADV +-file_type vlg +-ssc false +-rst false +-rst_pwd false +-rst_i false +-rst_o false +-fclkin 50 +-idiv_sel 2 +-clkfb_sel 0 +-fbdiv_sel 1 +-en_lock false +-dyn_dpa_en false +-clkout0_bypass false +-odiv0_sel 57 +-odiv0_frac_sel 0 +-clkout0_dt_dir 1 +-clkout0_dt_step 0 +-dyn_pe0_sel false +-clkout0_pe_coarse 0 +-clkout0_pe_fine 0 +-de0_en false +-clkout0_dt_dir 1 +-clkout0_dt_step 0 +-en_clkout1 true +-clkout1_bypass false +-odiv1_sel 19 +-clkout1_dt_dir 1 +-clkout1_dt_step 0 +-dyn_pe1_sel false +-clkout1_pe_coarse 0 +-clkout1_pe_fine 0 +-de1_en false +-en_clkout2 true +-clkout2_bypass false +-odiv2_sel 19 +-clkout2_dt_dir 1 +-clkout2_dt_step 0 +-dyn_pe2_sel false +-clkout2_pe_coarse 11 +-clkout2_pe_fine 7 +-de2_en false +-en_clkout3 false +-en_clkout4 false +-en_clkout5 false +-en_clkout6 false +-en_clkfbout false +-mdiv_sel 49 +-mdiv_frac_sel 0 \ No newline at end of file diff --git a/src/tang_primer_25k/gowin_pll_nes.v b/src/tang_primer_25k/gowin_pll_nes.v new file mode 100644 index 0000000..e45f297 --- /dev/null +++ b/src/tang_primer_25k/gowin_pll_nes.v @@ -0,0 +1,137 @@ +//Copyright (C)2014-2023 Gowin Semiconductor Corporation. +//All rights reserved. +//File Title: IP file +//Tool Version: V1.9.9 (64-bit) +//Part Number: GW5A-LV25MG121NC1/I0 +//Device: GW5A-25 +//Device Version: A +//Created Time: Sun Mar 31 00:24:37 2024 + +module gowin_pll_nes (clkout0, clkout1, clkout2, clkin); + +output clkout0; +output clkout1; +output clkout2; +input clkin; + +wire lock; +wire clkout3; +wire clkout4; +wire clkout5; +wire clkout6; +wire clkfbout; +wire [7:0] mdrdo; +wire gw_gnd; + +assign gw_gnd = 1'b0; + +PLLA PLLA_inst ( + .LOCK(lock), + .CLKOUT0(clkout0), + .CLKOUT1(clkout1), + .CLKOUT2(clkout2), + .CLKOUT3(clkout3), + .CLKOUT4(clkout4), + .CLKOUT5(clkout5), + .CLKOUT6(clkout6), + .CLKFBOUT(clkfbout), + .MDRDO(mdrdo), + .CLKIN(clkin), + .CLKFB(gw_gnd), + .RESET(gw_gnd), + .PLLPWD(gw_gnd), + .RESET_I(gw_gnd), + .RESET_O(gw_gnd), + .PSSEL({gw_gnd,gw_gnd,gw_gnd}), + .PSDIR(gw_gnd), + .PSPULSE(gw_gnd), + .SSCPOL(gw_gnd), + .SSCON(gw_gnd), + .SSCMDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .SSCMDSEL_FRAC({gw_gnd,gw_gnd,gw_gnd}), + .MDCLK(gw_gnd), + .MDOPC({gw_gnd,gw_gnd}), + .MDAINC(gw_gnd), + .MDWDI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}) +); + +defparam PLLA_inst.FCLKIN = "50"; +defparam PLLA_inst.IDIV_SEL = 2; +defparam PLLA_inst.FBDIV_SEL = 1; +defparam PLLA_inst.ODIV0_SEL = 57; +defparam PLLA_inst.ODIV1_SEL = 19; +defparam PLLA_inst.ODIV2_SEL = 19; +defparam PLLA_inst.ODIV3_SEL = 8; +defparam PLLA_inst.ODIV4_SEL = 8; +defparam PLLA_inst.ODIV5_SEL = 8; +defparam PLLA_inst.ODIV6_SEL = 8; +defparam PLLA_inst.MDIV_SEL = 49; +defparam PLLA_inst.MDIV_FRAC_SEL = 0; +defparam PLLA_inst.ODIV0_FRAC_SEL = 0; +defparam PLLA_inst.CLKOUT0_EN = "TRUE"; +defparam PLLA_inst.CLKOUT1_EN = "TRUE"; +defparam PLLA_inst.CLKOUT2_EN = "TRUE"; +defparam PLLA_inst.CLKOUT3_EN = "FALSE"; +defparam PLLA_inst.CLKOUT4_EN = "FALSE"; +defparam PLLA_inst.CLKOUT5_EN = "FALSE"; +defparam PLLA_inst.CLKOUT6_EN = "FALSE"; +defparam PLLA_inst.CLKFB_SEL = "INTERNAL"; +defparam PLLA_inst.CLKOUT0_DT_DIR = 1'b1; +defparam PLLA_inst.CLKOUT1_DT_DIR = 1'b1; +defparam PLLA_inst.CLKOUT2_DT_DIR = 1'b1; +defparam PLLA_inst.CLKOUT3_DT_DIR = 1'b1; +defparam PLLA_inst.CLKOUT0_DT_STEP = 0; +defparam PLLA_inst.CLKOUT1_DT_STEP = 0; +defparam PLLA_inst.CLKOUT2_DT_STEP = 0; +defparam PLLA_inst.CLKOUT3_DT_STEP = 0; +defparam PLLA_inst.CLK0_IN_SEL = 1'b0; +defparam PLLA_inst.CLK0_OUT_SEL = 1'b0; +defparam PLLA_inst.CLK1_IN_SEL = 1'b0; +defparam PLLA_inst.CLK1_OUT_SEL = 1'b0; +defparam PLLA_inst.CLK2_IN_SEL = 1'b0; +defparam PLLA_inst.CLK2_OUT_SEL = 1'b0; +defparam PLLA_inst.CLK3_IN_SEL = 1'b0; +defparam PLLA_inst.CLK3_OUT_SEL = 1'b0; +defparam PLLA_inst.CLK4_IN_SEL = 2'b00; +defparam PLLA_inst.CLK4_OUT_SEL = 1'b0; +defparam PLLA_inst.CLK5_IN_SEL = 1'b0; +defparam PLLA_inst.CLK5_OUT_SEL = 1'b0; +defparam PLLA_inst.CLK6_IN_SEL = 1'b0; +defparam PLLA_inst.CLK6_OUT_SEL = 1'b0; +defparam PLLA_inst.DYN_DPA_EN = "FALSE"; +defparam PLLA_inst.CLKOUT0_PE_COARSE = 0; +defparam PLLA_inst.CLKOUT0_PE_FINE = 0; +defparam PLLA_inst.CLKOUT1_PE_COARSE = 0; +defparam PLLA_inst.CLKOUT1_PE_FINE = 0; +defparam PLLA_inst.CLKOUT2_PE_COARSE = 11; +defparam PLLA_inst.CLKOUT2_PE_FINE = 7; +defparam PLLA_inst.CLKOUT3_PE_COARSE = 0; +defparam PLLA_inst.CLKOUT3_PE_FINE = 0; +defparam PLLA_inst.CLKOUT4_PE_COARSE = 0; +defparam PLLA_inst.CLKOUT4_PE_FINE = 0; +defparam PLLA_inst.CLKOUT5_PE_COARSE = 0; +defparam PLLA_inst.CLKOUT5_PE_FINE = 0; +defparam PLLA_inst.CLKOUT6_PE_COARSE = 0; +defparam PLLA_inst.CLKOUT6_PE_FINE = 0; +defparam PLLA_inst.DYN_PE0_SEL = "FALSE"; +defparam PLLA_inst.DYN_PE1_SEL = "FALSE"; +defparam PLLA_inst.DYN_PE2_SEL = "FALSE"; +defparam PLLA_inst.DYN_PE3_SEL = "FALSE"; +defparam PLLA_inst.DYN_PE4_SEL = "FALSE"; +defparam PLLA_inst.DYN_PE5_SEL = "FALSE"; +defparam PLLA_inst.DYN_PE6_SEL = "FALSE"; +defparam PLLA_inst.DE0_EN = "FALSE"; +defparam PLLA_inst.DE1_EN = "FALSE"; +defparam PLLA_inst.DE2_EN = "FALSE"; +defparam PLLA_inst.DE3_EN = "FALSE"; +defparam PLLA_inst.DE4_EN = "FALSE"; +defparam PLLA_inst.DE5_EN = "FALSE"; +defparam PLLA_inst.DE6_EN = "FALSE"; +defparam PLLA_inst.RESET_I_EN = "FALSE"; +defparam PLLA_inst.RESET_O_EN = "FALSE"; +defparam PLLA_inst.ICP_SEL = 6'bXXXXXX; +defparam PLLA_inst.LPF_RES = 3'bXXX; +defparam PLLA_inst.LPF_CAP = 2'b00; +defparam PLLA_inst.SSC_EN = "FALSE"; + +endmodule //gowin_pll_nes