From fe7aad1494b7033c5be3e40c6f8a5b7bec117efa Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Thu, 9 May 2024 21:13:11 -0700
Subject: [PATCH] Build C binaries

---
 .github/workflows/build.yml | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 .github/workflows/build.yml

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
new file mode 100644
index 000000000..b0560fa84
--- /dev/null
+++ b/.github/workflows/build.yml
@@ -0,0 +1,37 @@
+name: Build
+
+on:
+  push:
+    branches:
+      - master
+
+jobs:
+  build:
+    runs-on: ubuntu-22.04
+    steps:
+    - name: Install packages
+      run: sudo apt install -y opam zlib1g-dev pkg-config libgmp-dev z3 device-tree-compiler
+    - name: Check out repository code
+      uses: actions/checkout@HEAD
+      with:
+        submodules: true
+    - name: Ensure pre-commit checks pass
+      run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always
+    - name: Init opam
+      run: opam init --disable-sandboxing -y
+    - name: Install sail
+      run: opam install -y sail
+    - name: Build and test simulators
+      run: eval $(opam env) && make c_emulator/riscv_sim_RV64 && ARCH=32 c_emulator/riscv_sim_RV32
+    - name: Upload ARCH=64 model
+      if: always()
+      uses: actions/upload-artifact@v4
+      with:
+        name: riscv_sim_RV64
+        path: c_emulator/riscv_sim_RV64
+    - name: Upload ARCH=32 model
+      if: always()
+      uses: actions/upload-artifact@v4
+      with:
+        name: riscv_sim_RV32
+        path: c_emulator/riscv_sim_RV32