From 90d6bf76c4df33669fcd92c22b8e8e93b040550d Mon Sep 17 00:00:00 2001 From: Alberto Gonzalez Date: Tue, 12 May 2020 17:10:30 +0000 Subject: [PATCH] Fix typos in documentation. --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 8e18c62..b79c035 100644 --- a/README.md +++ b/README.md @@ -6,7 +6,7 @@ The compilation flow consists of the following parts: -* **elastic-circuits**: A collection of LLVM passes which input a C/C++ program and transform its IR into a dataflow circuit. The output of this pass is a .DOT file which represents a netlist of dataflow components. The details of the .DOT dataflow description are given in *Documents/Dataflow.md*. +* **elastic-circuits**: A collection of LLVM passes which input a C/C++ program and transform its IR into a dataflow circuit. The output of this pass is a .DOT file which represents a netlist of dataflow components. The details of the .DOT dataflow description are given in *Documentation/Dataflow.md*. * **Buffers**: Buffer placement for throughput and critical path optimization. Inputs the .DOT netlist from *elastic-circuits* and outputs a .DOT netlist with buffers placed and sized to maximize throughput under a given clock period constaint. @@ -16,4 +16,4 @@ All folders contain README files with detailed instructions on installation and ### Simulation and Verification -Please refer to *Documents/ModelSim Simulation.md* on details about running the simulation and incorporating Xilinx computational units into the dataflow designs. The designs can be verified using the framework in the *hls_verifier* folder. \ No newline at end of file +Please refer to *Documentation/ModelSim Simulation.md* on details about running the simulation and incorporating Xilinx computational units into the dataflow designs. The designs can be verified using the framework in the *hls_verifier* folder.