Errors trying to load bitstream onto Arty A7-100

[JamesTimothyMeech]

I have followed the instructions in the readme so far but when it comes to loading the bitstream to the Arty A7-100 I get errors.

When I run ./make.py --board=arty --load i get this error:

Traceback (most recent call last): File "./make.py", line 945, in <module> main() File "./make.py", line 934, in main board.load(filename=builder.get_bitstream_filename(mode="sram")) File "./make.py", line 33, in load prog.load_bitstream(filename) File "/home/james/Desktop/Casino/litex/litex/build/openocd.py", line 28, in load_bitstream self.call(["openocd", "-f", config, "-c", script]) File "/home/james/Desktop/Casino/litex/litex/build/generic_programmer.py", line 101, in call raise OSError(msg) OSError: Error occured during OpenOCD's call, please check: OpenOCD installation. Access permissions. Hardware and cable. Bitstream presence.

When I run sudo ./make.py --board=arty --load I get this error:

Traceback (most recent call last): File "/home/james/Desktop/Casino/linux-on-litex-vexriscv/./make.py", line 13, in <module> from litex.soc.integration.builder import Builder ModuleNotFoundError: No module named 'litex'

[trabucayre]

The first error is unfortunately not really clear but could you check access right (ls -l /dev/ttyUSB* to see group owner and ìd to displays list of group for your user)?
Second error: by using sudosome environment variables are lost (not exported).

[JamesTimothyMeech]

Thank it was either a USB cable issue or some problem / confusion I had about my F4PGA installation.

When I run (xc7) james@james-System-Product-Name:~/Desktop/Casino/linux-on-litex-vexriscv$ ./make.py --board=arty --toolchain=symbiflow --build

It fails with this error:

Project status:
    [R] bitstream:  bitstream -> /home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/gateware/arty.bit
    [N] build_dir:  /home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/gateware
    [S] eblif:  synth -> /home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/gateware/arty.eblif
    [S] fasm:  fasm -> /home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/gateware/arty.fasm
    [S] fasm_extra:  synth -> /home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/gateware/arty_fasm_extra.fasm
    [S] io_place:  ioplace -> /home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/gateware/arty.ioplace
    [S] net:  pack -> /home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/gateware/arty.net
    [X] pcf:  MISSING
    [S] place:  place -> /home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/gateware/arty.place
    [S] place_constraints:  place_constraints -> /home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/gateware/arty.preplace
    [S] route:  route -> /home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/gateware/arty.route
    [S] sdc:  synth -> /home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/gateware/arty.sdc
    [N] sources:  ['/home/james/Desktop/Casino/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/Ram_1w_1rs_Generic.v', '/home/james/Desktop/Casino/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw128_Ood.v', '/home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/gateware/arty.v']
    [N] xdc:  /home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/gateware/arty.xdc

Executing module `yosys`:
    [1/3] : Synthesizing sources: ['/home/james/Desktop/Casino/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/Ram_1w_1rs_Generic.v', '/home/james/Desktop/Casino/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw128_Ood.v', '/home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/gateware/arty.v']...
[ERROR]: yosys non-zero return code.

stderr:
ERROR: Cell $iopadmap$arty.sdcard_cd of type \IBUF doesn't support the \SLEW attribute

[JamesTimothyMeech]

If I instead run ./make.py --board=arty --build it builds fine but then running ./make.py --board=arty --build causes it to get stuck doing fpga_program forever

make: Leaving directory '/home/james/Desktop/Casino/linux-on-litex-vexriscv/build/arty/software/bios'
INFO:SoC:Initializing ROM rom with contents (Size: 0xcfc0).
INFO:SoC:Auto-Resizing ROM rom from 0x10000 to 0xcfc0.
build/arty/arty.dts:253.34-264.19: Warning (unit_address_vs_reg): /soc/clk@f0005000/CLKOUT0: node has a reg or ranges property, but no unit name
build/arty/arty.dts:266.34-277.19: Warning (unit_address_vs_reg): /soc/clk@f0005000/CLKOUT1: node has a reg or ranges property, but no unit name
build/arty/arty.dts:44.42-48.19: Warning (interrupt_provider): /cpus/cpu@0/interrupt-controller: Missing #address-cells in interrupt provider
Open On-Chip Debugger 0.12.0+dev-01154-g91bd43134 (2023-04-26-09:59)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter driver' not 'interface'
DEPRECATED! use 'ftdi vid_pid' not 'ftdi_vid_pid'
DEPRECATED! use 'ftdi channel' not 'ftdi_channel'
DEPRECATED! use 'ftdi layout_init' not 'ftdi_layout_init'
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
DEPRECATED! use 'adapter speed' not 'adapter_khz'
fpga_program

[ratzupaltuff]

I have the same problem too sometimes. For now a reboot of my computer (while the device is connected) solved the problem every time. I checked the permissions and checkd the udev rules. Sometimes if I switched the USB port where the Arty A7 is connected after booting into my Ubuntu the problem occured. But I have not found a solution either, apart from rebooting my OS if it happens.