diff --git a/pythondata_cpu_serv/verilog/.gitmodules b/pythondata_cpu_serv/verilog/.gitmodules
new file mode 100644
index 0000000..ef0a528
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/.gitmodules
@@ -0,0 +1,4 @@
+[submodule "zephyr"]
+ path = zephyr
+ url = https://github.com/olofk/zephyr
+ branch = serv
diff --git a/pythondata_cpu_serv/verilog/LICENSE b/pythondata_cpu_serv/verilog/LICENSE
new file mode 100644
index 0000000..8572ea0
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/LICENSE
@@ -0,0 +1,7 @@
+ISC License
+
+Copyright 2019, Olof Kindgren
+
+Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
\ No newline at end of file
diff --git a/pythondata_cpu_serv/verilog/README.md b/pythondata_cpu_serv/verilog/README.md
new file mode 100644
index 0000000..b312369
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/README.md
@@ -0,0 +1,149 @@
+
+
+# SERV
+
+SERV is an award-winning bit-serial RISC-V core
+
+## Prerequisites
+
+Create a directory to keep all the different parts of the project together. We
+will refer to this directory as `$SERV` from now on.
+
+Download the main serv repo
+
+`cd $SERV && git clone https://github.com/olofk/serv`
+
+Install FuseSoC
+
+`pip install fusesoc`
+
+Initialize the FuseSoC standard libraries
+
+`fusesoc init`
+
+Create a workspace directory for FuseSoC
+
+`mkdir $SERV/workspace`
+
+Register the serv repo as a core library
+
+`cd $SERV/workspace && fusesoc library add serv $SERV`
+
+Check that the CPU passes the linter
+
+`cd $SERV/workspace && fusesoc run --target=lint serv`
+
+## Running test software
+
+Build and run the single threaded zephyr hello world example with verilator (should be stopped with Ctrl-C):
+
+ cd $SERV/workspace
+ fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/serv/sw/zephyr_hello.hex
+
+..or... the multithreaded version
+
+ fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/serv/sw/zephyr_hello_mt.hex --memsize=16384
+
+...or... the philosophers example
+
+ fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/serv/sw/zephyr_phil.hex --memsize=32768
+
+...or... the synchronization example
+
+ fusesoc run --target=verilator_tb servant --uart_baudrate=57600 --firmware=$SERV/serv/sw/zephyr_sync.hex --memsize=16384
+
+Other applications can be tested by compiling and converting to bin and then hex e.g. with makehex.py found in `$SERV/serv/riscv-target/serv`
+
+## Run the compliance tests
+
+Build the verilator model (if not already done)
+
+`cd $SERV/workspace && fusesoc run --target=verilator_tb --setup --build servant`
+
+Download the tests repo
+
+`cd $SERV && git clone https://github.com/riscv/riscv-compliance`
+
+Run the compliance tests
+
+`cd $SERV/riscv-compliance && make TARGETDIR=$SERV/serv/riscv-target RISCV_TARGET=serv RISCV_DECICE=rv32i RISCV_ISA=rv32i TARGET_SIM=$SERV/workspace/build/servant_1.0.1/verilator_tb-verilator/Vservant_sim`
+
+## Run on hardware
+
+The servant SoC has been ported to a number of different FPGA boards. To see all currently supported targets run
+
+ fusesoc core show servant
+
+By default, these targets have the program memory preloaded with a small Zephyr hello world example that writes its output on a UART pin. Don't forget to install the appropriate toolchain (e.g. icestorm, Vivado, Quartus...) and add to your PATH
+
+Some targets also depend on functionality in the FuseSoC base library (fusesoc-cores). Running `fusesoc library list` should tell you if fusesoc-cores is already available. If not, add it to your workspace with
+
+ fusesoc library add fusesoc-cores https://github.com/fusesoc/fusesoc-cores
+
+Now we're ready to build. Note, for all the cases below, it's possible to run with `--memfile=$SERV/sw/blinky.hex`
+(or any other suitable program) as the last argument to preload the LED blink example
+instead of hello world.
+
+### TinyFPGA BX
+
+Pin A6 is used for UART output with 115200 baud rate.
+
+ cd $SERV/workspace
+ fusesoc run --target=tinyfpga_bx servant
+ tinyprog --program build/servant_1.0.1/tinyfpga_bx-icestorm/servant_1.0.1.bin
+
+### Icebreaker
+
+Pin 9 is used for UART output with 57600 baud rate.
+
+ cd $SERV/workspace
+ fusesoc run --target=icebreaker servant
+
+### Arty A7 35T
+
+Pin D10 (uart_rxd_out) is used for UART output with 57600 baud rate (to use
+blinky.hex change D10 to H5 (led[4]) in data/arty_a7_35t.xdc).
+
+ cd $SERV/workspace
+ fusesoc run --target=arty_a7_35t servant
+
+### Alhambra II
+
+Pin 61 is used for UART output with 38400 baud rate (note that it works with non-standard 43200 value too). This pin is connected to a FT2232H chip in board, that manages the communications between the FPGA and the computer.
+
+ cd $SERV/workspace
+ fusesoc run --target=alhambra servant
+ iceprog -d i:0x0403:0x6010:0 build/servant_1.0.1/alhambra-icestorm/servant_1.0.1.bin
+
+## Other targets
+
+The above targets are run on the servant SoC, but there are some targets defined for the CPU itself. Verilator can be run in lint mode to check for design problems by running
+
+ fusesoc run --target=lint serv
+
+It's also possible to just synthesise for different targets to check resource usage and such. To do that for the iCE40 devices, run
+
+ fusesoc run --tool=icestorm serv --pnr=none
+
+...or to synthesize with vivado for Xilinx targets, run
+
+ fusesoc run --tool=vivado serv --pnr=none
+
+This will synthesize for the default Vivado part. To synthesise for a specific device, run e.g.
+
+ fusesoc run --tool=vivado serv --pnr=none --part=xc7a100tcsg324-1
+
+
+## Good to know
+
+Don't feed serv any illegal instructions after midnight. Many logic expressions are hand-optimized using the old-fashioned method with Karnaugh maps on paper, and shamelessly take advantage of the fact that some opcodes aren't supposed to appear. As serv was written with 4-input LUT FPGAs as target, and opcodes are 5 bits, this can save quite a bit of resources in the decoder.
+
+The bus interface is kind of Wishbone, but with most signals removed. There's an important difference though. Don't send acks on the instruction or data buses unless serv explicitly asks for something by raising its cyc signal. Otherwise serv becomes very confused.
+
+Don't go changing the clock frequency on a whim when running Zephyr. Or well, it's ok I guess, but since the UART is bitbanged, this will change the baud rate as well. As of writing, the UART is running at 115200 baud rate when the CPU is 32 MHz. There are two NOPs in the driver to slow it down a bit, so if those are removed I think it could achieve baud rate 115200 on a 24MHz clock.. in case someone wants to try
+
+## TODO
+
+- Applications have to be preloaded to RAM at compile-time
+- Store bootloader and register file together in a RAM
+- Make it faster and smaller
diff --git a/pythondata_cpu_serv/verilog/bench/servant_sim.v b/pythondata_cpu_serv/verilog/bench/servant_sim.v
new file mode 100644
index 0000000..64da239
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/bench/servant_sim.v
@@ -0,0 +1,25 @@
+`default_nettype none
+module servant_sim
+ (input wire wb_clk,
+ input wire wb_rst,
+ output wire q);
+
+ parameter memfile = "";
+ parameter memsize = 8192;
+ parameter with_csr = 1;
+
+ reg [1023:0] firmware_file;
+ initial
+ if ($value$plusargs("firmware=%s", firmware_file)) begin
+ $display("Loading RAM from %0s", firmware_file);
+ $readmemh(firmware_file, dut.ram.mem);
+ end
+
+ servant
+ #(.memfile (memfile),
+ .memsize (memsize),
+ .sim (1),
+ .with_csr (with_csr))
+ dut(wb_clk, wb_rst, q);
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/bench/servant_tb.cpp b/pythondata_cpu_serv/verilog/bench/servant_tb.cpp
new file mode 100644
index 0000000..b8f294a
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/bench/servant_tb.cpp
@@ -0,0 +1,153 @@
+#include
+#include
+
+#include "verilated_vcd_c.h"
+#include "Vservant_sim.h"
+
+using namespace std;
+
+static bool done;
+
+vluint64_t main_time = 0; // Current simulation time
+// This is a 64-bit integer to reduce wrap over issues and
+// allow modulus. You can also use a double, if you wish.
+
+double sc_time_stamp () { // Called by $time in Verilog
+ return main_time; // converts to double, to match
+ // what SystemC does
+}
+
+void INThandler(int signal)
+{
+ printf("\nCaught ctrl-c\n");
+ done = true;
+}
+
+typedef struct {
+ bool last_value;
+} gpio_context_t;
+
+void do_gpio(gpio_context_t *context, bool gpio) {
+ if (context->last_value != gpio) {
+ context->last_value = gpio;
+ printf("%lu output q is %s\n", main_time, gpio ? "ON" : "OFF");
+ }
+}
+
+typedef struct {
+ uint8_t state;
+ char ch;
+ uint32_t baud_t;
+ vluint64_t last_update;
+} uart_context_t;
+
+void uart_init(uart_context_t *context, uint32_t baud_rate) {
+ context->baud_t = 1000*1000*1000/baud_rate;
+ context->state = 0;
+}
+
+void do_uart(uart_context_t *context, bool rx) {
+ if (context->state == 0) {
+ if (rx)
+ context->state++;
+ }
+ else if (context->state == 1) {
+ if (!rx) {
+ context->last_update = main_time + context->baud_t/2;
+ context->state++;
+ }
+ }
+ else if(context->state == 2) {
+ if (main_time > context->last_update) {
+ context->last_update += context->baud_t;
+ context->ch = 0;
+ context->state++;
+ }
+ }
+ else if (context->state < 11) {
+ if (main_time > context->last_update) {
+ context->last_update += context->baud_t;
+ context->ch |= rx << (context->state-3);
+ context->state++;
+ }
+ }
+ else {
+ if (main_time > context->last_update) {
+ context->last_update += context->baud_t;
+ putchar(context->ch);
+ context->state=1;
+ }
+ }
+}
+
+int main(int argc, char **argv, char **env)
+{
+ vluint64_t sample_time = 0;
+ uint32_t insn = 0;
+ uint32_t ex_pc = 0;
+ int baud_rate = 0;
+
+ gpio_context_t gpio_context;
+ uart_context_t uart_context;
+ Verilated::commandArgs(argc, argv);
+
+ Vservant_sim* top = new Vservant_sim;
+
+ const char *arg = Verilated::commandArgsPlusMatch("uart_baudrate=");
+ if (arg[0]) {
+ baud_rate = atoi(arg+15);
+ if (baud_rate) {
+ uart_init(&uart_context, baud_rate);
+ }
+ }
+
+ VerilatedVcdC * tfp = 0;
+ const char *vcd = Verilated::commandArgsPlusMatch("vcd=");
+ if (vcd[0]) {
+ Verilated::traceEverOn(true);
+ tfp = new VerilatedVcdC;
+ top->trace (tfp, 99);
+ tfp->open ("trace.vcd");
+ }
+
+ signal(SIGINT, INThandler);
+
+ vluint64_t timeout = 0;
+ const char *arg_timeout = Verilated::commandArgsPlusMatch("timeout=");
+ if (arg_timeout[0])
+ timeout = atoi(arg_timeout+9);
+
+ vluint64_t vcd_start = 0;
+ const char *arg_vcd_start = Verilated::commandArgsPlusMatch("vcd_start=");
+ if (arg_vcd_start[0])
+ vcd_start = atoi(arg_vcd_start+11);
+
+ bool dump = false;
+ top->wb_clk = 1;
+ bool q = top->q;
+ while (!(done || Verilated::gotFinish())) {
+ if (tfp && !dump && (main_time > vcd_start)) {
+ dump = true;
+ }
+ top->wb_rst = main_time < 100;
+ top->eval();
+ if (dump)
+ tfp->dump(main_time);
+ if (baud_rate)
+ do_uart(&uart_context, top->q);
+ else
+ do_gpio(&gpio_context, top->q);
+
+ if (timeout && (main_time >= timeout)) {
+ printf("Timeout: Exiting at time %lu\n", main_time);
+ done = true;
+ }
+
+ top->wb_clk = !top->wb_clk;
+ main_time+=31.25;
+
+ }
+ if (tfp)
+ tfp->close();
+ exit(0);
+}
diff --git a/pythondata_cpu_serv/verilog/bench/servant_tb.v b/pythondata_cpu_serv/verilog/bench/servant_tb.v
new file mode 100644
index 0000000..41183cd
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/bench/servant_tb.v
@@ -0,0 +1,24 @@
+`default_nettype none
+module servant_tb;
+
+ parameter memfile = "";
+ parameter memsize = 8192;
+ parameter with_csr = 1;
+
+ reg wb_clk = 1'b0;
+ reg wb_rst = 1'b1;
+
+ always #31 wb_clk <= !wb_clk;
+ initial #62 wb_rst <= 1'b0;
+
+ vlog_tb_utils vtu();
+
+ uart_decoder #(57600) uart_decoder (q);
+
+ servant_sim
+ #(.memfile (memfile),
+ .memsize (memsize),
+ .with_csr (with_csr))
+ dut(wb_clk, wb_rst, q);
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/bench/uart_decoder.v b/pythondata_cpu_serv/verilog/bench/uart_decoder.v
new file mode 100644
index 0000000..f80b3c5
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/bench/uart_decoder.v
@@ -0,0 +1,18 @@
+module uart_decoder
+ #(parameter BAUD_RATE = 115200)
+ (input rx);
+
+ localparam T = 1000000000/BAUD_RATE;
+
+ integer i;
+ reg [7:0] ch;
+
+ initial forever begin
+ @(negedge rx);
+ #(T/2) ch = 0;
+ for (i=0;i<8;i=i+1)
+ #T ch[i] = rx;
+ $write("%c",ch);
+ $fflush;
+ end
+endmodule
diff --git a/pythondata_cpu_serv/verilog/data/alhambra.pcf b/pythondata_cpu_serv/verilog/data/alhambra.pcf
new file mode 100644
index 0000000..9c902dc
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/data/alhambra.pcf
@@ -0,0 +1,5 @@
+# 12 MHz clock
+set_io i_clk 49
+
+# RS232
+set_io q 61
diff --git a/pythondata_cpu_serv/verilog/data/arty_a7_35t.xdc b/pythondata_cpu_serv/verilog/data/arty_a7_35t.xdc
new file mode 100644
index 0000000..e6fcbfa
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/data/arty_a7_35t.xdc
@@ -0,0 +1,10 @@
+set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports i_clk];
+
+set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports q]
+
+#set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports q]
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports i_clk];
diff --git a/pythondata_cpu_serv/verilog/data/cyc1000.sdc b/pythondata_cpu_serv/verilog/data/cyc1000.sdc
new file mode 100644
index 0000000..c674e2f
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/data/cyc1000.sdc
@@ -0,0 +1,8 @@
+# Main system clock (12 Mhz)
+create_clock -name "clk" -period 83.333ns [get_ports {i_clk}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
diff --git a/pythondata_cpu_serv/verilog/data/cyc1000.tcl b/pythondata_cpu_serv/verilog/data/cyc1000.tcl
new file mode 100644
index 0000000..7d8c144
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/data/cyc1000.tcl
@@ -0,0 +1,14 @@
+#
+# Clock / Reset
+#
+set_location_assignment PIN_M2 -to i_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk
+set_location_assignment PIN_N6 -to i_rst
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk
+
+#UART/GPIO
+set_location_assignment PIN_M6 -to q
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q
+
+set_location_assignment PIN_T7 -to uart_txd
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart*
diff --git a/pythondata_cpu_serv/verilog/data/icebreaker.pcf b/pythondata_cpu_serv/verilog/data/icebreaker.pcf
new file mode 100644
index 0000000..124cb75
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/data/icebreaker.pcf
@@ -0,0 +1,5 @@
+# 12 MHz clock
+set_io i_clk 35
+
+# RS232
+set_io q 9
diff --git a/pythondata_cpu_serv/verilog/data/nexys_a7.xdc b/pythondata_cpu_serv/verilog/data/nexys_a7.xdc
new file mode 100644
index 0000000..3906727
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/data/nexys_a7.xdc
@@ -0,0 +1,4 @@
+set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports i_clk];
+set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports q]
+
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports i_clk];
diff --git a/pythondata_cpu_serv/verilog/data/tinyfpga_bx.pcf b/pythondata_cpu_serv/verilog/data/tinyfpga_bx.pcf
new file mode 100644
index 0000000..7a56754
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/data/tinyfpga_bx.pcf
@@ -0,0 +1,2 @@
+set_io q A6
+set_io i_clk B2
diff --git a/pythondata_cpu_serv/verilog/data/ulx3s.lpf b/pythondata_cpu_serv/verilog/data/ulx3s.lpf
new file mode 100644
index 0000000..0ea49d6
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/data/ulx3s.lpf
@@ -0,0 +1,14 @@
+LOCATE COMP "clk" SITE "G2";
+IOBUF PORT "clk" PULLMODE=NONE IO_TYPE=LVCMOS33;
+FREQUENCY PORT "clk" 25.000 MHZ;
+LOCATE COMP "q" SITE "B2";
+IOBUF PORT "q" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+LOCATE COMP "btn0" SITE "D6"; # BTN_PWRn (inverted logic)
+IOBUF PORT "btn0" PULLMODE=UP IO_TYPE=LVCMOS33;
+
+LOCATE COMP "wifi_gpio0" SITE "L2";
+IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+LOCATE COMP "uart_txd" SITE "L4"; # FPGA transmits to ftdi
+IOBUF PORT "uart_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
diff --git a/pythondata_cpu_serv/verilog/data/upduino2.pcf b/pythondata_cpu_serv/verilog/data/upduino2.pcf
new file mode 100644
index 0000000..9611af5
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/data/upduino2.pcf
@@ -0,0 +1,4 @@
+set_io g 39
+set_io b 40
+set_io r 41
+set_io q 14
diff --git a/pythondata_cpu_serv/verilog/data/zcu106.xdc b/pythondata_cpu_serv/verilog/data/zcu106.xdc
new file mode 100644
index 0000000..2d6d0d3
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/data/zcu106.xdc
@@ -0,0 +1,8 @@
+## Clock signal
+set_property -dict { PACKAGE_PIN H9 IOSTANDARD LVDS } [get_ports i_clk_p];
+set_property -dict { PACKAGE_PIN G9 IOSTANDARD LVDS } [get_ports i_clk_n];
+create_clock -add -name sys_clk_pin -period 8 [get_nets i_clk];
+
+## LED
+set_property -dict { PACKAGE_PIN AL11 IOSTANDARD LVCMOS12 } [get_ports q];
+set_property -dict { PACKAGE_PIN AL17 IOSTANDARD LVCMOS12 } [get_ports o_uart_tx]
diff --git a/pythondata_cpu_serv/verilog/riscv-target/serv/compliance_io.h b/pythondata_cpu_serv/verilog/riscv-target/serv/compliance_io.h
new file mode 100644
index 0000000..65e0148
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/riscv-target/serv/compliance_io.h
@@ -0,0 +1,36 @@
+// RISC-V Compliance IO Test Header File
+
+/*
+ * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied.
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef _COMPLIANCE_IO_H
+#define _COMPLIANCE_IO_H
+
+//-----------------------------------------------------------------------
+// RV IO Macros (Non functional)
+//-----------------------------------------------------------------------
+
+#define RVTEST_IO_INIT
+#define RVTEST_IO_WRITE_STR(_STR)
+#define RVTEST_IO_CHECK()
+#define RVTEST_IO_ASSERT_GPR_EQ(_R, _I)
+#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I)
+#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I)
+
+#endif // _COMPLIANCE_IO_H
diff --git a/pythondata_cpu_serv/verilog/riscv-target/serv/compliance_test.h b/pythondata_cpu_serv/verilog/riscv-target/serv/compliance_test.h
new file mode 100644
index 0000000..512793b
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/riscv-target/serv/compliance_test.h
@@ -0,0 +1,67 @@
+// RISC-V Compliance Test Header File
+// Copyright (c) 2017, Codasip Ltd. All Rights Reserved.
+// See LICENSE for license details.
+//
+// Description: Common header file for RV32I tests
+
+#ifndef _COMPLIANCE_TEST_H
+#define _COMPLIANCE_TEST_H
+
+//-----------------------------------------------------------------------
+// RV Compliance Macros
+//-----------------------------------------------------------------------
+
+#define RV_COMPLIANCE_HALT \
+la a0, data_begin; \
+ la a1, data_end; \
+ li a2, 0x80000000; \
+complience_halt_loop: \
+ beq a0, a1, complience_halt_break; \
+ addi a3, a0, 4; \
+complience_halt_loop2: \
+ addi a3, a3, -1; \
+ \
+ lb a4, 0 (a3); \
+ srai a5, a4, 4; \
+ andi a5, a5, 0xF; \
+ li a6, 10; \
+ blt a5, a6, notLetter; \
+ addi a5, a5, 39; \
+notLetter: \
+ addi a5, a5, 0x30; \
+ sw a5, 0 (a2); \
+ \
+ srai a5, a4, 0; \
+ andi a5, a5, 0xF; \
+ li a6, 10; \
+ blt a5, a6, notLetter2; \
+ addi a5, a5, 39; \
+notLetter2: \
+ addi a5, a5, 0x30; \
+ sw a5, 0 (a2); \
+ bne a0, a3,complience_halt_loop2; \
+ addi a0, a0, 4; \
+ \
+ li a4, '\n'; \
+ sw a4, 0 (a2); \
+ j complience_halt_loop; \
+ j complience_halt_break; \
+complience_halt_break:; \
+ lui a0,0x90000000>>12; \
+ sw a3,0(a0);
+
+#define RV_COMPLIANCE_RV32M
+
+#define RV_COMPLIANCE_CODE_BEGIN \
+ .section .text.init; \
+ .align 4; \
+ .globl _start; \
+_start: \
+
+#define RV_COMPLIANCE_CODE_END
+
+#define RV_COMPLIANCE_DATA_BEGIN .align 4; .global data_begin; data_begin:
+
+#define RV_COMPLIANCE_DATA_END .align 4; .global data_end; data_end:
+
+#endif
diff --git a/pythondata_cpu_serv/verilog/riscv-target/serv/device/rv32i/Makefile.include b/pythondata_cpu_serv/verilog/riscv-target/serv/device/rv32i/Makefile.include
new file mode 100644
index 0000000..9ef57a7
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/riscv-target/serv/device/rv32i/Makefile.include
@@ -0,0 +1,26 @@
+TARGET_SIM ?= server
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+ $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RUN_TARGET=\
+ $(TARGET_SIM) \
+ +timeout=100000000 \
+ +signature=$(work_dir_isa)/$(*).signature.output \
+ +firmware=$(work_dir_isa)/$<.hex 2> $(work_dir_isa)/$@
+
+RISCV_PREFIX ?= riscv32-unknown-elf-
+RISCV_GCC ?= $(RISCV_PREFIX)gcc
+RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy
+RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
+
+COMPILE_TARGET=\
+ $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \
+ -I$(ROOTDIR)/riscv-test-env/ \
+ -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+ -T$(TARGETDIR)/$(RISCV_TARGET)/link.ld $$< \
+ -o $(work_dir_isa)/$$@; \
+ $$(RISCV_OBJCOPY) -O binary $(work_dir_isa)/$$@ $(work_dir_isa)/$$@.bin; \
+ $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump; \
+ python3 $(TARGETDIR)/$(RISCV_TARGET)/makehex.py $(work_dir_isa)/$$@.bin 2048 > $(work_dir_isa)/$$@.hex;
diff --git a/pythondata_cpu_serv/verilog/riscv-target/serv/link.ld b/pythondata_cpu_serv/verilog/riscv-target/serv/link.ld
new file mode 100644
index 0000000..db7be33
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/riscv-target/serv/link.ld
@@ -0,0 +1,18 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+SECTIONS
+{
+ . = 0x00000000;
+ .text.init : { *(.text.init) }
+ . = ALIGN(0x1000);
+ .tohost : { *(.tohost) }
+ . = ALIGN(0x1000);
+ .text : { *(.text) }
+ . = ALIGN(0x1000);
+ .data : { *(.data) }
+ .data.string : { *(.data.string)}
+ .bss : { *(.bss) }
+ _end = .;
+}
+
diff --git a/pythondata_cpu_serv/verilog/riscv-target/serv/makehex.py b/pythondata_cpu_serv/verilog/riscv-target/serv/makehex.py
new file mode 100644
index 0000000..419b378
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/riscv-target/serv/makehex.py
@@ -0,0 +1,27 @@
+#!/usr/bin/env python3
+#
+# This is free and unencumbered software released into the public domain.
+#
+# Anyone is free to copy, modify, publish, use, compile, sell, or
+# distribute this software, either in source code form or as a compiled
+# binary, for any purpose, commercial or non-commercial, and by any
+# means.
+
+from sys import argv
+
+binfile = argv[1]
+nwords = int(argv[2])
+
+with open(binfile, "rb") as f:
+ bindata = f.read()
+
+assert len(bindata) < 4*nwords
+assert len(bindata) % 4 == 0
+
+for i in range(nwords):
+ if i < len(bindata) // 4:
+ w = bindata[4*i : 4*i+4]
+ print("%02x%02x%02x%02x" % (w[3], w[2], w[1], w[0]))
+ else:
+ print("0")
+
diff --git a/pythondata_cpu_serv/verilog/rtl/ser_shift.v b/pythondata_cpu_serv/verilog/rtl/ser_shift.v
new file mode 100644
index 0000000..8ec995b
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/rtl/ser_shift.v
@@ -0,0 +1,30 @@
+`default_nettype none
+module ser_shift
+ (
+ input wire i_clk,
+ input wire i_load,
+ input wire [4:0] i_shamt,
+ input wire i_shamt_msb,
+ input wire i_signbit,
+ input wire i_right,
+ output wire o_done,
+ input wire i_d,
+ output wire o_q);
+
+ reg signbit;
+ reg [5:0] cnt;
+ reg wrapped;
+
+ always @(posedge i_clk) begin
+ cnt <= cnt + 6'd1;
+ if (i_load) begin
+ cnt <= 6'd0;
+ signbit <= i_signbit & i_right;
+ end
+ wrapped <= cnt[5] | (i_shamt_msb & !i_right);
+ end
+
+ assign o_done = (cnt[4:0] == i_shamt);
+ assign o_q = (i_right^wrapped) ? i_d : signbit;
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/rtl/serv_alu.v b/pythondata_cpu_serv/verilog/rtl/serv_alu.v
new file mode 100644
index 0000000..e6d7a46
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/rtl/serv_alu.v
@@ -0,0 +1,112 @@
+`default_nettype none
+module serv_alu
+ (
+ input wire clk,
+ input wire i_rst,
+ input wire i_en,
+ input wire i_cnt0,
+ input wire i_rs1,
+ input wire i_rs2,
+ input wire i_imm,
+ input wire i_op_b_rs2,
+ input wire i_buf,
+ input wire i_init,
+ input wire i_cnt_done,
+ input wire i_sub,
+ input wire [1:0] i_bool_op,
+ input wire i_cmp_eq,
+ input wire i_cmp_uns,
+ output wire o_cmp,
+ input wire i_shamt_en,
+ input wire i_sh_right,
+ input wire i_sh_signed,
+ output wire o_sh_done,
+ input wire [3:0] i_rd_sel,
+ output wire o_rd);
+
+ wire result_add;
+ wire result_eq;
+ wire result_lt;
+ wire result_sh;
+
+ reg result_lt_r;
+
+ wire [4:0] shamt;
+ reg shamt_msb;
+
+ wire shamt_ser;
+ wire plus_1;
+
+ wire add_cy;
+ reg add_cy_r;
+
+ wire b_inv_plus_1;
+ wire b_inv_plus_1_cy;
+ reg b_inv_plus_1_cy_r;
+
+ wire op_b = i_op_b_rs2 ? i_rs2 : i_imm;
+ assign shamt_ser = i_sh_right ? op_b : b_inv_plus_1;
+
+ shift_reg #(.LEN (5)) shamt_reg
+ (.clk (clk),
+ .i_rst (i_rst),
+ .i_en (i_shamt_en),
+ .i_d (shamt_ser),
+ .o_q (shamt[0]),
+ .o_par (shamt[4:1]));
+
+ ser_shift shift
+ (
+ .i_clk (clk),
+ .i_load (i_init),
+ .i_shamt (shamt),
+ .i_shamt_msb (shamt_msb),
+ .i_signbit (i_sh_signed & i_rs1),
+ .i_right (i_sh_right),
+ .o_done (o_sh_done),
+ .i_d (i_buf),
+ .o_q (result_sh));
+
+ wire add_b = i_sub ? b_inv_plus_1 : op_b;
+ assign {add_cy,result_add} = i_rs1+add_b+add_cy_r;
+ assign {b_inv_plus_1_cy,b_inv_plus_1} = {1'b0,~op_b}+plus_1+b_inv_plus_1_cy_r;
+
+ reg lt_r;
+
+ reg eq_r;
+
+ wire lt_sign = i_cnt_done & !i_cmp_uns;
+
+ wire eq = (i_rs1 == op_b);
+
+ assign result_eq = eq & eq_r;
+ assign result_lt = eq ? lt_r : op_b^lt_sign;
+
+ assign plus_1 = i_cnt0;
+ assign o_cmp = i_cmp_eq ? result_eq : result_lt;
+
+ localparam [15:0] BOOL_LUT = 16'h8E96;//And, Or, =, xor
+ wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, op_b}];
+
+ assign o_rd = (i_rd_sel[0] & result_add) |
+ (i_rd_sel[1] & result_sh) |
+ (i_rd_sel[2] & result_lt_r & plus_1) |
+ (i_rd_sel[3] & result_bool);
+
+
+ always @(posedge clk) begin
+ add_cy_r <= i_en & add_cy;
+ b_inv_plus_1_cy_r <= i_en & b_inv_plus_1_cy;
+
+ lt_r <= result_lt & i_en;
+
+ if (i_en) begin
+ result_lt_r <= result_lt;
+ end
+ eq_r <= result_eq | ~i_en;
+
+ if (i_shamt_en)
+ shamt_msb <= b_inv_plus_1_cy;
+ end
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/rtl/serv_bufreg.v b/pythondata_cpu_serv/verilog/rtl/serv_bufreg.v
new file mode 100644
index 0000000..1f8c70c
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/rtl/serv_bufreg.v
@@ -0,0 +1,42 @@
+module serv_bufreg
+ (
+ input wire i_clk,
+ input wire i_cnt0,
+ input wire i_cnt1,
+ input wire i_en,
+ input wire i_init,
+ input wire i_loop,
+ input wire i_rs1,
+ input wire i_rs1_en,
+ input wire i_imm,
+ input wire i_imm_en,
+ input wire i_clr_lsb,
+ output reg [1:0] o_lsb,
+ output wire [31:0] o_dbus_adr,
+ output wire o_q);
+
+ wire c, q;
+ reg c_r;
+ reg [31:0] data;
+
+ wire clr_lsb = i_cnt0 & i_clr_lsb;
+
+ assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en & !clr_lsb)} + c_r;
+
+ always @(posedge i_clk) begin
+ //Clear carry when not in INIT state
+ c_r <= c & i_init;
+
+ if (i_en)
+ data <= {(i_loop & !i_init) ? o_q : q, data[31:1]};
+
+ if (i_cnt0 & i_init)
+ o_lsb[0] <= q;
+ if (i_cnt1 & i_init)
+ o_lsb[1] <= q;
+ end
+
+ assign o_q = data[0];
+ assign o_dbus_adr = {data[31:2], 2'b00};
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/rtl/serv_csr.v b/pythondata_cpu_serv/verilog/rtl/serv_csr.v
new file mode 100644
index 0000000..897e272
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/rtl/serv_csr.v
@@ -0,0 +1,108 @@
+`default_nettype none
+module serv_csr
+ (
+ input wire i_clk,
+ input wire i_en,
+ input wire i_cnt0to3,
+ input wire i_cnt2,
+ input wire i_cnt3,
+ input wire i_cnt7,
+ input wire i_cnt_done,
+ input wire i_e_op,
+ input wire i_ebreak,
+ input wire i_mem_cmd,
+ input wire i_mem_misalign,
+ //From mpram
+ input wire i_rf_csr_out,
+ //to mpram
+ output wire o_csr_in,
+ //Stuff
+ input wire i_mtip,
+ output wire o_new_irq,
+ input wire i_pending_irq,
+ input wire i_trap_taken,
+ input wire i_mstatus_en,
+ input wire i_mie_en,
+ input wire i_mcause_en,
+ input wire [1:0] i_csr_source,
+ input wire i_mret,
+ input wire i_d,
+ output wire o_q);
+
+`include "serv_params.vh"
+
+ reg mstatus;
+ reg mstatus_mie;
+ reg mstatus_mpie;
+ reg mie_mtie;
+
+ reg mcause31;
+ reg [3:0] mcause3_0;
+ wire mcause;
+
+ wire csr_in;
+ wire csr_out;
+
+ reg timer_irq_r;
+
+ assign csr_in = (i_csr_source == CSR_SOURCE_EXT) ? i_d :
+ (i_csr_source == CSR_SOURCE_SET) ? csr_out | i_d :
+ (i_csr_source == CSR_SOURCE_CLR) ? csr_out & ~i_d :
+ (i_csr_source == CSR_SOURCE_CSR) ? csr_out :
+ 1'bx;
+
+ assign csr_out = (i_mstatus_en & i_en & mstatus) |
+ i_rf_csr_out |
+ (i_mcause_en & i_en & mcause);
+
+ assign o_q = csr_out;
+
+ wire timer_irq = i_mtip & mstatus_mie & mie_mtie;
+
+ assign mcause = i_cnt0to3 ? mcause3_0[0] : //[3:0]
+ i_cnt_done ? mcause31 //[31]
+ : 1'b0;
+
+ assign o_csr_in = csr_in;
+
+ assign o_new_irq = !timer_irq_r & timer_irq;
+
+
+ always @(posedge i_clk) begin
+ /*
+ Note: To save resources mstatus_mpie (mstatus bit 7) is not
+ readable or writable from sw
+ */
+ if (i_mstatus_en & i_cnt3)
+ mstatus_mie <= csr_in;
+
+ if (i_mie_en & i_cnt7)
+ mie_mtie <= csr_in;
+
+ mstatus <= i_cnt2 & mstatus_mie;
+
+ timer_irq_r <= timer_irq;
+
+ if (i_mret) begin
+ mstatus_mie <= mstatus_mpie;
+ end
+
+ if (i_trap_taken) begin
+ mstatus_mpie <= mstatus_mie;
+ mstatus_mie <= 1'b0;
+ mcause31 <= i_pending_irq;
+ mcause3_0 <= i_pending_irq ? 4'd7 :
+ i_e_op ? {!i_ebreak, 3'b011} :
+ i_mem_misalign ? {2'b01, i_mem_cmd, 1'b0} :
+ 4'd0;
+ end
+
+ if (i_mcause_en & i_en) begin
+ if (i_cnt0to3)
+ mcause3_0 <= {csr_in, mcause3_0[3:1]};
+ if (i_cnt_done)
+ mcause31 <= csr_in;
+ end
+ end
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/rtl/serv_ctrl.v b/pythondata_cpu_serv/verilog/rtl/serv_ctrl.v
new file mode 100644
index 0000000..203c8a4
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/rtl/serv_ctrl.v
@@ -0,0 +1,100 @@
+`default_nettype none
+module serv_ctrl
+ (
+ input wire clk,
+ input wire i_rst,
+ //State
+ input wire i_pc_en,
+ input wire i_cnt12to31,
+ input wire i_cnt2,
+ input wire i_cnt_done,
+ //Control
+ input wire i_jump,
+ input wire i_jal_or_jalr,
+ input wire i_utype,
+ input wire i_pc_rel,
+ input wire i_trap,
+ //Data
+ input wire i_imm,
+ input wire i_buf,
+ input wire i_csr_pc,
+ output wire o_rd,
+ output wire o_bad_pc,
+ //External
+ output wire [31:0] o_ibus_adr,
+ output wire o_ibus_cyc,
+ input wire i_ibus_ack);
+
+ parameter RESET_PC = 32'd0;
+ parameter WITH_CSR = 1;
+
+ reg en_pc_r;
+
+ wire pc_plus_4;
+ wire pc_plus_4_cy;
+ reg pc_plus_4_cy_r;
+ wire pc_plus_offset;
+ wire pc_plus_offset_cy;
+ reg pc_plus_offset_cy_r;
+ wire pc_plus_offset_aligned;
+ wire plus_4;
+
+ wire pc;
+
+ wire new_pc;
+
+ wire offset_a;
+ wire offset_b;
+
+ assign plus_4 = i_cnt2;
+
+ assign o_ibus_adr[0] = pc;
+ assign o_bad_pc = pc_plus_offset_aligned;
+
+ assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+pc_plus_4_cy_r;
+
+ shift_reg
+ #(
+ .LEN (32),
+ .INIT (RESET_PC))
+ pc_reg
+ (
+ .clk (clk),
+ .i_rst (i_rst),
+ .i_en (i_pc_en),
+ .i_d (new_pc),
+ .o_q (pc),
+ .o_par (o_ibus_adr[31:1])
+ );
+
+ generate
+ if (WITH_CSR)
+ assign new_pc = i_trap ? (i_csr_pc & en_pc_r) : i_jump ? pc_plus_offset_aligned : pc_plus_4;
+ else
+ assign new_pc = i_jump ? pc_plus_offset_aligned : pc_plus_4;
+ endgenerate
+ assign o_rd = (i_utype & pc_plus_offset_aligned) | (pc_plus_4 & i_jal_or_jalr);
+
+ assign offset_a = i_pc_rel & pc;
+ assign offset_b = i_utype ? (i_imm & i_cnt12to31): i_buf;
+ assign {pc_plus_offset_cy,pc_plus_offset} = offset_a+offset_b+pc_plus_offset_cy_r;
+
+ assign pc_plus_offset_aligned = pc_plus_offset & en_pc_r;
+
+ assign o_ibus_cyc = en_pc_r & !i_pc_en;
+
+ always @(posedge clk) begin
+ pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy;
+ pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy;
+
+ if (i_pc_en)
+ en_pc_r <= 1'b1;
+ else if (o_ibus_cyc & i_ibus_ack)
+ en_pc_r <= 1'b0;
+
+ if (i_rst) begin
+ en_pc_r <= 1'b1;
+ end
+ end
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/rtl/serv_decode.v b/pythondata_cpu_serv/verilog/rtl/serv_decode.v
new file mode 100644
index 0000000..d66a1e0
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/rtl/serv_decode.v
@@ -0,0 +1,239 @@
+`default_nettype none
+module serv_decode
+ (
+ input wire clk,
+ //Input
+ input wire i_cnt_en,
+ input wire i_cnt_done,
+ input wire [31:2] i_wb_rdt,
+ input wire i_wb_en,
+ input wire i_alu_cmp,
+ //To state
+ output wire o_take_branch,
+ output wire o_e_op,
+ output wire o_ebreak,
+ output wire o_branch_op,
+ output wire o_mem_op,
+ output wire o_shift_op,
+ output wire o_slt_op,
+ output wire o_rd_op,
+ //To bufreg
+ output wire o_bufreg_loop,
+ output wire o_bufreg_rs1_en,
+ output wire o_bufreg_imm_en,
+ output wire o_bufreg_clr_lsb,
+ //To ctrl
+ output wire o_ctrl_jal_or_jalr,
+ output wire o_ctrl_utype,
+ output wire o_ctrl_pc_rel,
+ output wire o_ctrl_mret,
+ //To alu
+ output wire o_alu_sub,
+ output wire [1:0] o_alu_bool_op,
+ output wire o_alu_cmp_eq,
+ output wire o_alu_cmp_uns,
+ output wire o_alu_sh_signed,
+ output wire o_alu_sh_right,
+ output wire [3:0] o_alu_rd_sel,
+ //To RF
+ output reg [4:0] o_rf_rd_addr,
+ output reg [4:0] o_rf_rs1_addr,
+ output reg [4:0] o_rf_rs2_addr,
+ //To mem IF
+ output wire o_mem_signed,
+ output wire o_mem_word,
+ output wire o_mem_half,
+ output wire o_mem_cmd,
+ //To CSR
+ output wire o_csr_en,
+ output wire [1:0] o_csr_addr,
+ output wire o_csr_mstatus_en,
+ output wire o_csr_mie_en,
+ output wire o_csr_mcause_en,
+ output wire [1:0] o_csr_source,
+ output wire o_csr_d_sel,
+ output wire o_csr_imm,
+ //To top
+ output wire o_imm,
+ output wire o_op_b_source,
+ output wire o_rd_csr_en,
+ output wire o_rd_alu_en);
+
+`include "serv_params.vh"
+
+ reg [4:0] opcode;
+ reg [2:0] funct3;
+ reg op20;
+ reg op21;
+ reg op22;
+ reg op26;
+
+ reg imm30;
+
+ wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]);
+
+ assign o_mem_op = !opcode[4] & !opcode[2] & !opcode[0];
+ assign o_shift_op = op_or_opimm & (funct3[1:0] == 2'b01);
+ assign o_slt_op = op_or_opimm & (funct3[2:1] == 2'b01);
+ assign o_branch_op = opcode[4] & !opcode[2];
+
+ //Matches system opcodes except CSR accesses (funct3 == 0)
+ //No idea anymore why the !op21 condition is needed here
+ assign o_e_op = opcode[4] & opcode[2] & !op21 & !(|funct3);
+
+ assign o_ebreak = op20;
+
+ //jal,branch = imm
+ //jalr = rs1+imm
+ //mem = rs1+imm
+ //shift = rs1
+ assign o_bufreg_rs1_en = !opcode[4] | (!opcode[1] & opcode[0]);
+ assign o_bufreg_imm_en = !opcode[2];
+
+ //Loop bufreg contents for shift operations
+ assign o_bufreg_loop = op_or_opimm;
+
+ //Clear LSB of immediate for BRANCH and JAL ops
+ //True for BRANCH and JAL
+ //False for JALR/LOAD/STORE/OP/OPIMM?
+ assign o_bufreg_clr_lsb = opcode[4] & ((opcode[1:0] == 2'b00) | (opcode[1:0] == 2'b11));
+
+ //Take branch for jump or branch instructions (opcode == 1x0xx) if
+ //a) It's an unconditional branch (opcode[0] == 1)
+ //b) It's a conditional branch (opcode[0] == 0) of type beq,blt,bltu (funct3[0] == 0) and ALU compare is true
+ //c) It's a conditional branch (opcode[0] == 0) of type bne,bge,bgeu (funct3[0] == 1) and ALU compare is false
+ //Only valid during the last cycle of INIT, when the branch condition has
+ //been calculated.
+ assign o_take_branch = opcode[4] & !opcode[2] & (opcode[0] | (i_alu_cmp^funct3[0]));
+
+ assign o_ctrl_utype = !opcode[4] & opcode[2] & opcode[0];
+ assign o_ctrl_jal_or_jalr = opcode[4] & opcode[0];
+
+ //True for jal, b* auipc
+ //False for jalr, lui
+ assign o_ctrl_pc_rel = (opcode[2:0] == 3'b000) |
+ (opcode[1:0] == 2'b11) |
+ (opcode[4:3] == 2'b00);
+
+ assign o_ctrl_mret = (opcode[4] & opcode[2] & op21 & !(|funct3));
+
+ //Write to RD
+ //True for OP-IMM, AUIPC, OP, LUI, SYSTEM, JALR, JAL, LOAD
+ //False for STORE, BRANCH, MISC-MEM
+ assign o_rd_op = (opcode[2] |
+ (!opcode[2] & opcode[4] & opcode[0]) |
+ (!opcode[2] & !opcode[3] & !opcode[0])) & (|o_rf_rd_addr);
+
+ assign o_alu_sub = opcode[3] & imm30/*alu_sub_r*/;
+
+ /*
+ 300 0_000 mstatus RWSC
+ 304 0_100 mie SCWi
+ 305 0_101 mtvec RW
+ 340 1_000 mscratch
+ 341 1_001 mepc RW
+ 342 1_010 mcause R
+ 343 1_011 mtval
+ 344 1_100 mip CWi
+ */
+
+ //true for mtvec,mscratch,mepc and mtval
+ //false for mstatus, mie, mcause, mip
+ wire csr_valid = op20 | (op26 & !op22 & !op21);
+
+ //Matches system ops except eceall/ebreak
+ wire csr_op = opcode[4] & opcode[2] & (|funct3);
+ assign o_rd_csr_en = csr_op;
+
+ assign o_csr_en = csr_op & csr_valid;
+ assign o_csr_mstatus_en = csr_op & !op26 & !op22;
+ assign o_csr_mie_en = csr_op & !op26 & op22 & !op20;
+ assign o_csr_mcause_en = csr_op & op21 & !op20;
+
+ assign o_csr_source = funct3[1:0];
+ assign o_csr_d_sel = funct3[2];
+ assign o_csr_imm = o_rf_rs1_addr[0];
+
+ assign o_csr_addr = (op26 & !op20) ? CSR_MSCRATCH :
+ (op26 & !op21) ? CSR_MEPC :
+ (op26) ? CSR_MTVAL :
+ CSR_MTVEC;
+
+ assign o_alu_cmp_eq = funct3[2:1] == 2'b00;
+
+ assign o_alu_cmp_uns = (funct3[0] & funct3[1]) | (funct3[1] & funct3[2]);
+ assign o_alu_sh_signed = imm30;
+ assign o_alu_sh_right = funct3[2];
+
+ assign o_mem_cmd = opcode[3];
+ assign o_mem_signed = ~funct3[2];
+ assign o_mem_word = funct3[1];
+ assign o_mem_half = funct3[0];
+
+ assign o_alu_bool_op = funct3[1:0];
+
+ reg signbit;
+
+ reg [8:0] imm19_12_20;
+ reg imm7;
+ reg [5:0] imm30_25;
+ reg [4:0] imm24_20;
+ reg [4:0] imm11_7;
+
+ wire [1:0] m2;
+ //True for OP-IMM, LOAD, STORE, JALR
+ //False for LUI, AUIPC, JAL
+ assign m2[0] = (opcode[1:0] == 2'b00) | (opcode[2:1] == 2'b00);
+ assign m2[1] = opcode[4] & !opcode[0];
+ wire m3 = opcode[4];
+
+ assign o_alu_rd_sel[0] = (funct3 == 3'b000); // Add/sub
+ assign o_alu_rd_sel[1] = (funct3[1:0] == 2'b01); //Shift
+ assign o_alu_rd_sel[2] = (funct3[2:1] == 2'b01); //SLT*
+ assign o_alu_rd_sel[3] = (funct3[2] & !(funct3[1:0] == 2'b01)); //Bool
+ always @(posedge clk) begin
+ if (i_wb_en) begin
+ o_rf_rd_addr <= i_wb_rdt[11:7];
+ o_rf_rs1_addr <= i_wb_rdt[19:15];
+ o_rf_rs2_addr <= i_wb_rdt[24:20];
+ funct3 <= i_wb_rdt[14:12];
+ imm30 <= i_wb_rdt[30];
+ opcode <= i_wb_rdt[6:2];
+ op20 <= i_wb_rdt[20];
+ op21 <= i_wb_rdt[21];
+ op22 <= i_wb_rdt[22];
+ op26 <= i_wb_rdt[26];
+
+ //Immediate decoder
+ signbit <= i_wb_rdt[31];
+ imm19_12_20 <= {i_wb_rdt[19:12],i_wb_rdt[20]};
+ imm7 <= i_wb_rdt[7];
+ imm30_25 <= i_wb_rdt[30:25];
+ imm24_20 <= i_wb_rdt[24:20];
+ imm11_7 <= i_wb_rdt[11:7];
+ end
+ if (i_cnt_en) begin
+ imm19_12_20 <= {m3 ? signbit : imm24_20[0], imm19_12_20[8:1]};
+ imm7 <= signbit;
+ imm30_25 <= {m2[1] ? imm7 : m2[0] ? signbit : imm19_12_20[0], imm30_25[5:1]};
+ imm24_20 <= {imm30_25[0], imm24_20[4:1]};
+ imm11_7 <= {imm30_25[0], imm11_7[4:1]};
+ if (csr_op & o_csr_d_sel)
+ o_rf_rs1_addr <= {1'b0,o_rf_rs1_addr[4:1]};
+ end
+ end
+
+ //True for S (STORE) or B (BRANCH) type instructions
+ //False for J type instructions
+ wire m1 = opcode[3:0] == 4'b1000;
+
+ assign o_imm = i_cnt_done ? signbit : m1 ? imm11_7[0] : imm24_20[0];
+
+ //0 (OP_B_SOURCE_IMM) when OPIMM
+ //1 (OP_B_SOURCE_RS2) when BRANCH or OP
+ assign o_op_b_source = opcode[3];
+
+ assign o_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4];
+
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/rtl/serv_mem_if.v b/pythondata_cpu_serv/verilog/rtl/serv_mem_if.v
new file mode 100644
index 0000000..b9ea5cb
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/rtl/serv_mem_if.v
@@ -0,0 +1,68 @@
+`default_nettype none
+module serv_mem_if
+ #(parameter WITH_CSR = 1)
+ (
+ input wire i_clk,
+ input wire i_en,
+ input wire i_mem_op,
+ input wire i_signed,
+ input wire i_word,
+ input wire i_half,
+ input wire [1:0] i_bytecnt,
+ input wire i_rs2,
+ output wire o_rd,
+ input wire [1:0] i_lsb,
+ output wire o_misalign,
+ //External interface
+ output wire [31:0] o_wb_dat,
+ output wire [3:0] o_wb_sel,
+ input wire [31:0] i_wb_rdt,
+ input wire i_wb_ack);
+
+ reg signbit;
+
+ wire [2:0] tmp = {1'b0,i_bytecnt}+{1'b0,i_lsb};
+
+ reg [31:0] dat;
+
+ wire dat_en = i_en & !tmp[2];
+
+ wire dat_cur =
+ ((i_lsb == 2'd3) & dat[24]) |
+ ((i_lsb == 2'd2) & dat[16]) |
+ ((i_lsb == 2'd1) & dat[8]) |
+ ((i_lsb == 2'd0) & dat[0]);
+
+ wire dat_valid = i_word | (i_bytecnt == 2'b00) | (i_half & !i_bytecnt[1]);
+
+ assign o_rd = i_mem_op & (dat_valid ? dat_cur : signbit & i_signed);
+
+ assign o_wb_sel[3] = (i_lsb == 2'b11) | i_word | (i_half & i_lsb[1]);
+ assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word;
+ assign o_wb_sel[1] = (i_lsb == 2'b01) | i_word | (i_half & !i_lsb[1]);
+ assign o_wb_sel[0] = (i_lsb == 2'b00);
+
+ assign o_wb_dat = dat;
+
+ always @(posedge i_clk) begin
+ if (dat_en)
+ dat <= {i_rs2, dat[31:1]};
+
+ if (i_wb_ack)
+ dat <= i_wb_rdt;
+
+ if (dat_valid)
+ signbit <= dat_cur;
+ end
+ generate
+ if (WITH_CSR) begin
+ reg misalign;
+ always @(posedge i_clk)
+ misalign <= (i_lsb[0] & (i_word | i_half)) | (i_lsb[1] & i_word);
+ assign o_misalign = misalign & i_mem_op;
+ end else begin
+ assign o_misalign = 1'b0;
+ end
+ endgenerate
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/rtl/serv_params.vh b/pythondata_cpu_serv/verilog/rtl/serv_params.vh
new file mode 100644
index 0000000..0cf79d9
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/rtl/serv_params.vh
@@ -0,0 +1,11 @@
+localparam [1:0]
+ CSR_SOURCE_CSR = 2'b00,
+ CSR_SOURCE_EXT = 2'b01,
+ CSR_SOURCE_SET = 2'b10,
+ CSR_SOURCE_CLR = 2'b11;
+
+localparam [1:0]
+ CSR_MSCRATCH = 2'b00,
+ CSR_MTVEC = 2'b01,
+ CSR_MEPC = 2'b10,
+ CSR_MTVAL = 2'b11;
diff --git a/pythondata_cpu_serv/verilog/rtl/serv_rf_if.v b/pythondata_cpu_serv/verilog/rtl/serv_rf_if.v
new file mode 100644
index 0000000..b26e75f
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/rtl/serv_rf_if.v
@@ -0,0 +1,122 @@
+`default_nettype none
+module serv_rf_if
+ #(parameter WITH_CSR = 1)
+ (//RF Interface
+ output wire [4+WITH_CSR:0] o_wreg0,
+ output wire [4+WITH_CSR:0] o_wreg1,
+ output wire o_wen0,
+ output wire o_wen1,
+ output wire o_wdata0,
+ output wire o_wdata1,
+ output wire [4+WITH_CSR:0] o_rreg0,
+ output wire [4+WITH_CSR:0] o_rreg1,
+ input wire i_rdata0,
+ input wire i_rdata1,
+
+ //Trap interface
+ input wire i_trap,
+ input wire i_mret,
+ input wire i_mepc,
+ input wire i_mem_misalign,
+ input wire i_bufreg_q,
+ input wire i_bad_pc,
+ output wire o_csr_pc,
+ //CSR interface
+ input wire i_csr_en,
+ input wire [1:0] i_csr_addr,
+ input wire i_csr,
+ output wire o_csr,
+ //RD write port
+ input wire i_rd_wen,
+ input wire [4:0] i_rd_waddr,
+ input wire i_ctrl_rd,
+ input wire i_alu_rd,
+ input wire i_rd_alu_en,
+ input wire i_csr_rd,
+ input wire i_rd_csr_en,
+ input wire i_mem_rd,
+
+ //RS1 read port
+ input wire [4:0] i_rs1_raddr,
+ output wire o_rs1,
+ //RS2 read port
+ input wire [4:0] i_rs2_raddr,
+ output wire o_rs2);
+
+
+`include "serv_params.vh"
+
+ /*
+ ********** Write side ***********
+ */
+
+ generate
+ if (WITH_CSR) begin
+ wire rd = (i_ctrl_rd ) |
+ (i_alu_rd & i_rd_alu_en) |
+ (i_csr_rd & i_rd_csr_en) |
+ (i_mem_rd);
+
+ wire mtval = i_mem_misalign ? i_bufreg_q : i_bad_pc;
+
+ assign o_wdata0 = i_trap ? mtval : rd;
+ assign o_wdata1 = i_trap ? i_mepc : i_csr;
+
+ //port 0 rd mtval
+ //port 1 csr mepc
+ //mepc 100010
+ //mtval 100011
+ //csr 1000xx
+ //rd 0xxxxx
+ assign o_wreg0 = i_trap ? {4'b1000,CSR_MTVAL} : {1'b0,i_rd_waddr};
+ assign o_wreg1 = i_trap ? {4'b1000,CSR_MEPC} : {4'b1000,i_csr_addr};
+
+ assign o_wen0 = i_trap | i_rd_wen;
+ assign o_wen1 = i_trap | i_csr_en;
+
+ /*
+ ********** Read side ***********
+ */
+
+ //0 : RS1
+ //1 : RS2 / CSR
+
+
+ assign o_rreg0 = {1'b0, i_rs1_raddr};
+ assign o_rreg1 =
+ i_trap ? {4'b1000, CSR_MTVEC} :
+ i_mret ? {4'b1000, CSR_MEPC} :
+ i_csr_en ? {4'b1000, i_csr_addr} :
+ {1'b0,i_rs2_raddr};
+
+ assign o_rs1 = i_rdata0;
+ assign o_rs2 = i_rdata1;
+ assign o_csr = i_rdata1 & i_csr_en;
+ assign o_csr_pc = i_rdata1;
+
+ end else begin
+ wire rd = (i_ctrl_rd ) |
+ (i_alu_rd & i_rd_alu_en) |
+ (i_mem_rd);
+
+ assign o_wdata0 = rd;
+ assign o_wdata1 = 1'b0;
+
+ assign o_wreg0 = i_rd_waddr;
+ assign o_wreg1 = 5'd0;
+
+ assign o_wen0 =i_rd_wen;
+ assign o_wen1 = 1'b0;
+
+ /*
+ ********** Read side ***********
+ */
+
+ assign o_rreg0 = i_rs1_raddr;
+ assign o_rreg1 = i_rs2_raddr;
+
+ assign o_rs1 = i_rdata0;
+ assign o_rs2 = i_rdata1;
+ end // else: !if(WITH_CSR)
+ endgenerate
+endmodule
diff --git a/pythondata_cpu_serv/verilog/rtl/serv_rf_ram.v b/pythondata_cpu_serv/verilog/rtl/serv_rf_ram.v
new file mode 100644
index 0000000..9bbc503
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/rtl/serv_rf_ram.v
@@ -0,0 +1,26 @@
+module serv_rf_ram
+ #(parameter width=0,
+ parameter csr_regs=4,
+ parameter depth=32*(32+csr_regs)/width)
+ (input wire i_clk,
+ input wire [$clog2(depth)-1:0] i_waddr,
+ input wire [width-1:0] i_wdata,
+ input wire i_wen,
+ input wire [$clog2(depth)-1:0] i_raddr,
+ output reg [width-1:0] o_rdata);
+
+ reg [width-1:0] memory [0:depth-1];
+
+ always @(posedge i_clk) begin
+ if (i_wen)
+ memory[i_waddr] <= i_wdata;
+ o_rdata <= memory[i_raddr];
+ end
+
+`ifdef SERV_CLEAR_RAM
+ integer i;
+ initial
+ for (i=0;i 2)
+ always @(posedge i_clk) wdata0_r <= {i_wdata0, wdata0_r[width-2:1]};
+ else
+ always @(posedge i_clk) wdata0_r <= i_wdata0;
+ endgenerate
+
+ always @(posedge i_clk) begin
+ wen0_r <= i_wen0;
+ wen1_r <= i_wen1;
+ wreq_r <= i_wreq | rgnt;
+
+ wdata1_r <= {i_wdata1,wdata1_r[width-1:1]};
+
+ if (wgo)
+ wcnt <= wcnt+5'd1;
+
+ if (wreq_r) begin
+ wgo <= 1'b1;
+ end
+
+ if (wcnt == 5'b11111)
+ wgo <= 1'b0;
+
+ if (i_rst) begin
+ wcnt <= 5'd0;
+ end
+ end
+
+ /*
+ ********** Read side ***********
+ */
+
+ reg [4:0] rcnt;
+
+ wire rtrig0;
+ reg rtrig1;
+
+ wire [$clog2(32+csr_regs)-1:0] rreg = rtrig0 ? i_rreg1 : i_rreg0;
+ generate if (width == 32)
+ assign o_raddr = rreg;
+ else
+ assign o_raddr = {rreg, rcnt[4:l2w]};
+ endgenerate
+
+ reg [width-1:0] rdata0;
+ reg [width-2:0] rdata1;
+
+ assign o_rdata0 = rdata0[0];
+ assign o_rdata1 = rtrig1 ? i_rdata[0] : rdata1[0];
+
+ assign rtrig0 = (rcnt[l2w-1:0] == 1);
+
+ reg rreq_r;
+
+ generate if (width>2)
+ always @(posedge i_clk) begin
+ rdata1 <= {1'b0,rdata1[width-2:1]}; //Optimize?
+ if (rtrig1)
+ rdata1[width-2:0] <= i_rdata[width-1:1];
+ end
+ else
+ always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1];
+ endgenerate
+
+ always @(posedge i_clk) begin
+ rtrig1 <= rtrig0;
+ rcnt <= rcnt+5'd1;
+ if (i_rreq)
+ rcnt <= 5'd0;
+
+ rreq_r <= i_rreq;
+ rgnt <= rreq_r;
+
+ rdata0 <= {1'b0,rdata0[width-1:1]};
+ if (rtrig0)
+ rdata0 <= i_rdata;
+
+ if (i_rst) begin
+ rgnt <= 1'b0;
+ rreq_r <= 1'b0;
+ end
+ end
+
+
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/rtl/serv_rf_top.v b/pythondata_cpu_serv/verilog/rtl/serv_rf_top.v
new file mode 100644
index 0000000..66aec5d
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/rtl/serv_rf_top.v
@@ -0,0 +1,163 @@
+`default_nettype none
+
+module serv_rf_top
+ #(parameter RESET_PC = 32'd0,
+ parameter WITH_CSR = 1,
+ parameter RF_WIDTH = 2)
+ (
+ input wire clk,
+ input wire i_rst,
+ input wire i_timer_irq,
+`ifdef RISCV_FORMAL
+ output wire rvfi_valid,
+ output wire [63:0] rvfi_order,
+ output wire [31:0] rvfi_insn,
+ output wire rvfi_trap,
+ output wire rvfi_halt,
+ output wire rvfi_intr,
+ output wire [1:0] rvfi_mode,
+ output wire [1:0] rvfi_ixl,
+ output wire [4:0] rvfi_rs1_addr,
+ output wire [4:0] rvfi_rs2_addr,
+ output wire [31:0] rvfi_rs1_rdata,
+ output wire [31:0] rvfi_rs2_rdata,
+ output wire [4:0] rvfi_rd_addr,
+ output wire [31:0] rvfi_rd_wdata,
+ output wire [31:0] rvfi_pc_rdata,
+ output wire [31:0] rvfi_pc_wdata,
+ output wire [31:0] rvfi_mem_addr,
+ output wire [3:0] rvfi_mem_rmask,
+ output wire [3:0] rvfi_mem_wmask,
+ output wire [31:0] rvfi_mem_rdata,
+ output wire [31:0] rvfi_mem_wdata,
+`endif
+ output wire [31:0] o_ibus_adr,
+ output wire o_ibus_cyc,
+ input wire [31:0] i_ibus_rdt,
+ input wire i_ibus_ack,
+ output wire [31:0] o_dbus_adr,
+ output wire [31:0] o_dbus_dat,
+ output wire [3:0] o_dbus_sel,
+ output wire o_dbus_we ,
+ output wire o_dbus_cyc,
+ input wire [31:0] i_dbus_rdt,
+ input wire i_dbus_ack);
+
+ localparam CSR_REGS = WITH_CSR*4;
+ localparam RF_L2D = $clog2((32+CSR_REGS)*32/RF_WIDTH);
+
+ wire rf_wreq;
+ wire rf_rreq;
+ wire [4+WITH_CSR:0] wreg0;
+ wire [4+WITH_CSR:0] wreg1;
+ wire wen0;
+ wire wen1;
+ wire wdata0;
+ wire wdata1;
+ wire [4+WITH_CSR:0] rreg0;
+ wire [4+WITH_CSR:0] rreg1;
+ wire rf_ready;
+ wire rdata0;
+ wire rdata1;
+
+ wire [RF_L2D-1:0] waddr;
+ wire [RF_WIDTH-1:0] wdata;
+ wire wen;
+ wire [RF_L2D-1:0] raddr;
+ wire [RF_WIDTH-1:0] rdata;
+
+ serv_rf_ram_if
+ #(.width (RF_WIDTH),
+ .csr_regs (CSR_REGS))
+ rf_ram_if
+ (.i_clk (clk),
+ .i_rst (i_rst),
+ .i_wreq (rf_wreq),
+ .i_rreq (rf_rreq),
+ .o_ready (rf_ready),
+ .i_wreg0 (wreg0),
+ .i_wreg1 (wreg1),
+ .i_wen0 (wen0),
+ .i_wen1 (wen1),
+ .i_wdata0 (wdata0),
+ .i_wdata1 (wdata1),
+ .i_rreg0 (rreg0),
+ .i_rreg1 (rreg1),
+ .o_rdata0 (rdata0),
+ .o_rdata1 (rdata1),
+ .o_waddr (waddr),
+ .o_wdata (wdata),
+ .o_wen (wen),
+ .o_raddr (raddr),
+ .i_rdata (rdata));
+
+ serv_rf_ram
+ #(.width (RF_WIDTH),
+ .csr_regs (CSR_REGS))
+ rf_ram
+ (.i_clk (clk),
+ .i_waddr (waddr),
+ .i_wdata (wdata),
+ .i_wen (wen),
+ .i_raddr (raddr),
+ .o_rdata (rdata));
+
+ serv_top
+ #(.RESET_PC (RESET_PC),
+ .WITH_CSR (WITH_CSR))
+ cpu
+ (
+ .clk (clk),
+ .i_rst (i_rst),
+ .i_timer_irq (i_timer_irq),
+`ifdef RISCV_FORMAL
+ .rvfi_valid (rvfi_valid ),
+ .rvfi_order (rvfi_order ),
+ .rvfi_insn (rvfi_insn ),
+ .rvfi_trap (rvfi_trap ),
+ .rvfi_halt (rvfi_halt ),
+ .rvfi_intr (rvfi_intr ),
+ .rvfi_mode (rvfi_mode ),
+ .rvfi_ixl (rvfi_ixl ),
+ .rvfi_rs1_addr (rvfi_rs1_addr ),
+ .rvfi_rs2_addr (rvfi_rs2_addr ),
+ .rvfi_rs1_rdata (rvfi_rs1_rdata),
+ .rvfi_rs2_rdata (rvfi_rs2_rdata),
+ .rvfi_rd_addr (rvfi_rd_addr ),
+ .rvfi_rd_wdata (rvfi_rd_wdata ),
+ .rvfi_pc_rdata (rvfi_pc_rdata ),
+ .rvfi_pc_wdata (rvfi_pc_wdata ),
+ .rvfi_mem_addr (rvfi_mem_addr ),
+ .rvfi_mem_rmask (rvfi_mem_rmask),
+ .rvfi_mem_wmask (rvfi_mem_wmask),
+ .rvfi_mem_rdata (rvfi_mem_rdata),
+ .rvfi_mem_wdata (rvfi_mem_wdata),
+`endif
+ .o_rf_rreq (rf_rreq),
+ .o_rf_wreq (rf_wreq),
+ .i_rf_ready (rf_ready),
+ .o_wreg0 (wreg0),
+ .o_wreg1 (wreg1),
+ .o_wen0 (wen0),
+ .o_wen1 (wen1),
+ .o_wdata0 (wdata0),
+ .o_wdata1 (wdata1),
+ .o_rreg0 (rreg0),
+ .o_rreg1 (rreg1),
+ .i_rdata0 (rdata0),
+ .i_rdata1 (rdata1),
+
+ .o_ibus_adr (o_ibus_adr),
+ .o_ibus_cyc (o_ibus_cyc),
+ .i_ibus_rdt (i_ibus_rdt),
+ .i_ibus_ack (i_ibus_ack),
+
+ .o_dbus_adr (o_dbus_adr),
+ .o_dbus_dat (o_dbus_dat),
+ .o_dbus_sel (o_dbus_sel),
+ .o_dbus_we (o_dbus_we),
+ .o_dbus_cyc (o_dbus_cyc),
+ .i_dbus_rdt (i_dbus_rdt),
+ .i_dbus_ack (i_dbus_ack));
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/rtl/serv_state.v b/pythondata_cpu_serv/verilog/rtl/serv_state.v
new file mode 100644
index 0000000..b919264
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/rtl/serv_state.v
@@ -0,0 +1,153 @@
+module serv_state
+ (
+ input wire i_clk,
+ input wire i_rst,
+ input wire i_new_irq,
+ output wire o_trap_taken,
+ output reg o_pending_irq,
+ input wire i_dbus_ack,
+ input wire i_ibus_ack,
+ output wire o_rf_rreq,
+ output wire o_rf_wreq,
+ input wire i_rf_ready,
+ output wire o_rf_rd_en,
+ input wire i_take_branch,
+ input wire i_branch_op,
+ input wire i_mem_op,
+ input wire i_shift_op,
+ input wire i_slt_op,
+ input wire i_e_op,
+ input wire i_rd_op,
+ output reg o_init,
+ output reg o_cnt_en,
+ output wire o_cnt0,
+ output wire o_cnt0to3,
+ output wire o_cnt12to31,
+ output wire o_cnt1,
+ output wire o_cnt2,
+ output wire o_cnt3,
+ output wire o_cnt7,
+ output wire o_ctrl_pc_en,
+ output reg o_ctrl_jump,
+ output wire o_ctrl_trap,
+ input wire i_ctrl_misalign,
+ output wire o_alu_shamt_en,
+ input wire i_alu_sh_done,
+ output wire o_dbus_cyc,
+ output wire [1:0] o_mem_bytecnt,
+ input wire i_mem_misalign,
+ output reg o_cnt_done,
+ output wire o_bufreg_hold);
+
+ parameter WITH_CSR = 1;
+
+ wire cnt4;
+
+ reg stage_two_req;
+
+ reg [4:2] o_cnt;
+ reg [3:0] o_cnt_r;
+
+ //Update PC in RUN or TRAP states
+ assign o_ctrl_pc_en = o_cnt_en & !o_init;
+
+
+ assign o_mem_bytecnt = o_cnt[4:3];
+
+ assign o_cnt0to3 = (o_cnt[4:2] == 3'd0);
+ assign o_cnt12to31 = (o_cnt[4] | (o_cnt[3:2] == 2'b11));
+ assign o_cnt0 = (o_cnt[4:2] == 3'd0) & o_cnt_r[0];
+ assign o_cnt1 = (o_cnt[4:2] == 3'd0) & o_cnt_r[1];
+ assign o_cnt2 = (o_cnt[4:2] == 3'd0) & o_cnt_r[2];
+ assign o_cnt3 = (o_cnt[4:2] == 3'd0) & o_cnt_r[3];
+ assign cnt4 = (o_cnt[4:2] == 3'd1) & o_cnt_r[0];
+ assign o_cnt7 = (o_cnt[4:2] == 3'd1) & o_cnt_r[3];
+
+ assign o_alu_shamt_en = (o_cnt0to3 | cnt4) & o_init;
+
+
+ //slt*, branch/jump, shift, load/store
+ wire two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op;
+
+ reg stage_two_pending;
+
+ assign o_dbus_cyc = !o_cnt_en & stage_two_pending & i_mem_op & !i_mem_misalign;
+
+ wire trap_pending = WITH_CSR & ((o_ctrl_jump & i_ctrl_misalign) | i_mem_misalign);
+
+ //Prepare RF for reads when a new instruction is fetched
+ // or when stage one caused an exception (rreq implies a write request too)
+ assign o_rf_rreq = i_ibus_ack | (stage_two_req & trap_pending);
+
+ //Prepare RF for writes when everything is ready to enter stage two
+ assign o_rf_wreq = ((i_shift_op & i_alu_sh_done & stage_two_pending) | (i_mem_op & i_dbus_ack) | (stage_two_req & (i_slt_op | i_branch_op))) & !trap_pending;
+
+ assign o_rf_rd_en = i_rd_op & o_cnt_en & !o_init;
+
+ //Shift operations require bufreg to hold for one cycle between INIT and RUN before shifting
+ assign o_bufreg_hold = !o_cnt_en & (stage_two_req | ~i_shift_op);
+
+ always @(posedge i_clk) begin
+ if (o_cnt_done)
+ o_ctrl_jump <= o_init & i_take_branch;
+
+ if (o_cnt_en)
+ stage_two_pending <= o_init;
+
+ o_cnt_done <= (o_cnt[4:2] == 3'b111) & o_cnt_r[2];
+
+ //Need a strobe for the first cycle in the IDLE state after INIT
+ stage_two_req <= o_cnt_done & o_init;
+
+ if (i_rf_ready & !stage_two_pending)
+ o_init <= two_stage_op & !o_pending_irq;
+
+ if (o_cnt_done)
+ o_init <= 1'b0;
+
+ if (i_rf_ready)
+ o_cnt_en <= 1'b1;
+
+ if (o_cnt_done)
+ o_cnt_en <= 1'b0;
+
+ o_cnt <= o_cnt + {2'd0,o_cnt_r[3]};
+ if (o_cnt_en)
+ o_cnt_r <= {o_cnt_r[2:0],o_cnt_r[3]};
+
+ if (i_rst) begin
+ o_cnt <= 3'd0;
+ stage_two_pending <= 1'b0;
+ o_ctrl_jump <= 1'b0;
+ o_cnt_r <= 4'b0001;
+ end
+ end
+
+ generate
+ if (WITH_CSR) begin
+ reg irq_sync;
+ reg misalign_trap_sync;
+
+ assign o_ctrl_trap = i_e_op | o_pending_irq | misalign_trap_sync;
+ assign o_trap_taken = i_ibus_ack & o_ctrl_trap;
+
+ always @(posedge i_clk) begin
+ if (i_ibus_ack)
+ irq_sync <= 1'b0;
+ if (i_new_irq)
+ irq_sync <= 1'b1;
+
+ if (i_ibus_ack)
+ o_pending_irq <= irq_sync;
+
+ if (stage_two_req)
+ misalign_trap_sync <= trap_pending;
+ if (i_ibus_ack)
+ misalign_trap_sync <= 1'b0;
+ end // always @ (posedge i_clk)
+ end else begin
+ always @(*)
+ o_pending_irq = 1'b0;
+ end
+ endgenerate
+endmodule
diff --git a/pythondata_cpu_serv/verilog/rtl/serv_top.v b/pythondata_cpu_serv/verilog/rtl/serv_top.v
new file mode 100644
index 0000000..9c9ea9d
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/rtl/serv_top.v
@@ -0,0 +1,494 @@
+`default_nettype none
+
+module serv_top
+ #(parameter WITH_CSR = 1,
+ parameter RESET_PC = 32'd0)
+ (
+ input wire clk,
+ input wire i_rst,
+ input wire i_timer_irq,
+`ifdef RISCV_FORMAL
+ output reg rvfi_valid = 1'b0,
+ output reg [63:0] rvfi_order = 64'd0,
+ output reg [31:0] rvfi_insn = 32'd0,
+ output reg rvfi_trap = 1'b0,
+ output reg rvfi_halt = 1'b0,
+ output reg rvfi_intr = 1'b0,
+ output reg [1:0] rvfi_mode = 2'b11,
+ output reg [1:0] rvfi_ixl = 2'b01,
+ output reg [4:0] rvfi_rs1_addr,
+ output reg [4:0] rvfi_rs2_addr,
+ output reg [31:0] rvfi_rs1_rdata,
+ output reg [31:0] rvfi_rs2_rdata,
+ output reg [4:0] rvfi_rd_addr,
+ output reg [31:0] rvfi_rd_wdata,
+ output reg [31:0] rvfi_pc_rdata,
+ output reg [31:0] rvfi_pc_wdata,
+ output reg [31:0] rvfi_mem_addr,
+ output reg [3:0] rvfi_mem_rmask,
+ output reg [3:0] rvfi_mem_wmask,
+ output reg [31:0] rvfi_mem_rdata,
+ output reg [31:0] rvfi_mem_wdata,
+`endif
+ //RF Interface
+ output wire o_rf_rreq,
+ output wire o_rf_wreq,
+ input wire i_rf_ready,
+ output wire [4+WITH_CSR:0] o_wreg0,
+ output wire [4+WITH_CSR:0] o_wreg1,
+ output wire o_wen0,
+ output wire o_wen1,
+ output wire o_wdata0,
+ output wire o_wdata1,
+ output wire [4+WITH_CSR:0] o_rreg0,
+ output wire [4+WITH_CSR:0] o_rreg1,
+ input wire i_rdata0,
+ input wire i_rdata1,
+
+ output wire [31:0] o_ibus_adr,
+ output wire o_ibus_cyc,
+ input wire [31:0] i_ibus_rdt,
+ input wire i_ibus_ack,
+ output wire [31:0] o_dbus_adr,
+ output wire [31:0] o_dbus_dat,
+ output wire [3:0] o_dbus_sel,
+ output wire o_dbus_we ,
+ output wire o_dbus_cyc,
+ input wire [31:0] i_dbus_rdt,
+ input wire i_dbus_ack);
+
+ wire [4:0] rd_addr;
+ wire [4:0] rs1_addr;
+ wire [4:0] rs2_addr;
+
+ wire take_branch;
+ wire e_op;
+ wire ebreak;
+ wire branch_op;
+ wire mem_op;
+ wire shift_op;
+ wire slt_op;
+ wire rd_op;
+
+ wire rd_alu_en;
+ wire rd_csr_en;
+ wire ctrl_rd;
+ wire alu_rd;
+ wire mem_rd;
+ wire csr_rd;
+
+ wire ctrl_pc_en;
+ wire jump;
+ wire jal_or_jalr;
+ wire utype;
+ wire mret;
+ wire imm;
+ wire trap;
+ wire pc_rel;
+
+ wire init;
+ wire cnt_en;
+ wire cnt0to3;
+ wire cnt12to31;
+ wire cnt0;
+ wire cnt1;
+ wire cnt2;
+ wire cnt3;
+ wire cnt7;
+
+ wire cnt_done;
+
+ wire bufreg_hold;
+ wire bufreg_rs1_en;
+ wire bufreg_imm_en;
+ wire bufreg_loop;
+ wire bufreg_q;
+
+ wire alu_sub;
+ wire [1:0] alu_bool_op;
+ wire alu_cmp_eq;
+ wire alu_cmp_uns;
+ wire alu_cmp;
+ wire alu_shamt_en;
+ wire alu_sh_signed;
+ wire alu_sh_right;
+ wire alu_sh_done;
+ wire [3:0] alu_rd_sel;
+
+ wire rs1;
+ wire rs2;
+ wire rd_en;
+
+ wire op_b_source;
+ wire op_b;
+
+ wire mem_signed;
+ wire mem_word;
+ wire mem_half;
+ wire [1:0] mem_bytecnt;
+
+ wire mem_misalign;
+
+ wire bad_pc;
+
+ wire csr_mstatus_en;
+ wire csr_mie_en;
+ wire csr_mcause_en;
+ wire [1:0] csr_source;
+ wire csr_imm;
+ wire csr_d_sel;
+ wire csr_en;
+ wire [1:0] csr_addr;
+ wire csr_pc;
+
+
+ wire new_irq;
+ wire trap_taken;
+ wire pending_irq;
+
+ wire [1:0] lsb;
+
+ serv_state
+ #(.WITH_CSR (WITH_CSR))
+ state
+ (
+ .i_clk (clk),
+ .i_rst (i_rst),
+ .i_new_irq (new_irq),
+ .o_trap_taken (trap_taken),
+ .o_pending_irq (pending_irq),
+ .i_dbus_ack (i_dbus_ack),
+ .i_ibus_ack (i_ibus_ack),
+ .o_rf_rreq (o_rf_rreq),
+ .o_rf_wreq (o_rf_wreq),
+ .i_rf_ready (i_rf_ready),
+ .o_rf_rd_en (rd_en),
+ .i_take_branch (take_branch),
+ .i_branch_op (branch_op),
+ .i_mem_op (mem_op),
+ .i_shift_op (shift_op),
+ .i_slt_op (slt_op),
+ .i_e_op (e_op),
+ .i_rd_op (rd_op),
+ .o_init (init),
+ .o_cnt_en (cnt_en),
+ .o_cnt0to3 (cnt0to3),
+ .o_cnt12to31 (cnt12to31),
+ .o_cnt0 (cnt0),
+ .o_cnt1 (cnt1),
+ .o_cnt2 (cnt2),
+ .o_cnt3 (cnt3),
+ .o_cnt7 (cnt7),
+ .o_cnt_done (cnt_done),
+ .o_bufreg_hold (bufreg_hold),
+ .o_ctrl_pc_en (ctrl_pc_en),
+ .o_ctrl_jump (jump),
+ .o_ctrl_trap (trap),
+ .i_ctrl_misalign(lsb[1]),
+ .o_alu_shamt_en (alu_shamt_en),
+ .i_alu_sh_done (alu_sh_done),
+ .o_dbus_cyc (o_dbus_cyc),
+ .o_mem_bytecnt (mem_bytecnt),
+ .i_mem_misalign (mem_misalign));
+
+ wire bufreg_clr_lsb;
+
+ serv_decode decode
+ (
+ .clk (clk),
+ //Input
+ .i_cnt_en (cnt_en),
+ .i_cnt_done (cnt_done),
+ .i_wb_rdt (i_ibus_rdt[31:2]),
+ .i_wb_en (o_ibus_cyc & i_ibus_ack),
+ .i_alu_cmp (alu_cmp),
+ //To state
+ .o_take_branch (take_branch),
+ .o_e_op (e_op),
+ .o_ebreak (ebreak),
+ .o_branch_op (branch_op),
+ .o_mem_op (mem_op),
+ .o_shift_op (shift_op),
+ .o_slt_op (slt_op),
+ .o_rd_op (rd_op),
+ //To bufreg
+ .o_bufreg_loop (bufreg_loop),
+ .o_bufreg_rs1_en (bufreg_rs1_en),
+ .o_bufreg_imm_en (bufreg_imm_en),
+ .o_bufreg_clr_lsb (bufreg_clr_lsb),
+ //To ctrl
+ .o_ctrl_jal_or_jalr (jal_or_jalr),
+ .o_ctrl_utype (utype),
+ .o_ctrl_pc_rel (pc_rel),
+ .o_ctrl_mret (mret),
+ //To alu
+ .o_op_b_source (op_b_source),
+ .o_alu_sub (alu_sub),
+ .o_alu_bool_op (alu_bool_op),
+ .o_alu_cmp_eq (alu_cmp_eq),
+ .o_alu_cmp_uns (alu_cmp_uns),
+ .o_alu_sh_signed (alu_sh_signed),
+ .o_alu_sh_right (alu_sh_right),
+ .o_alu_rd_sel (alu_rd_sel),
+ //To RF
+ .o_rf_rd_addr (rd_addr),
+ .o_rf_rs1_addr (rs1_addr),
+ .o_rf_rs2_addr (rs2_addr),
+ //To mem IF
+ .o_mem_cmd (o_dbus_we),
+ .o_mem_signed (mem_signed),
+ .o_mem_word (mem_word),
+ .o_mem_half (mem_half),
+ //To CSR
+ .o_csr_en (csr_en),
+ .o_csr_addr (csr_addr),
+ .o_csr_mstatus_en (csr_mstatus_en),
+ .o_csr_mie_en (csr_mie_en),
+ .o_csr_mcause_en (csr_mcause_en),
+ .o_csr_source (csr_source),
+ .o_csr_d_sel (csr_d_sel),
+ .o_csr_imm (csr_imm),
+ //To top
+ .o_imm (imm),
+ .o_rd_csr_en (rd_csr_en),
+ .o_rd_alu_en (rd_alu_en));
+
+ serv_bufreg bufreg
+ (
+ .i_clk (clk),
+ .i_cnt0 (cnt0),
+ .i_cnt1 (cnt1),
+ .i_en (!bufreg_hold),
+ .i_init (init),
+ .i_loop (bufreg_loop),
+ .i_rs1 (rs1),
+ .i_rs1_en (bufreg_rs1_en),
+ .i_imm (imm),
+ .i_imm_en (bufreg_imm_en),
+ .i_clr_lsb (bufreg_clr_lsb),
+ .o_lsb (lsb),
+ .o_dbus_adr (o_dbus_adr),
+ .o_q (bufreg_q));
+
+ serv_ctrl
+ #(.RESET_PC (RESET_PC),
+ .WITH_CSR (WITH_CSR))
+ ctrl
+ (
+ .clk (clk),
+ .i_rst (i_rst),
+ //State
+ .i_pc_en (ctrl_pc_en),
+ .i_cnt12to31 (cnt12to31),
+ .i_cnt2 (cnt2),
+ .i_cnt_done (cnt_done),
+ //Control
+ .i_jump (jump),
+ .i_jal_or_jalr (jal_or_jalr),
+ .i_utype (utype),
+ .i_pc_rel (pc_rel),
+ .i_trap (trap | mret),
+ //Data
+ .i_imm (imm),
+ .i_buf (bufreg_q),
+ .i_csr_pc (csr_pc),
+ .o_rd (ctrl_rd),
+ .o_bad_pc (bad_pc),
+ //External
+ .o_ibus_adr (o_ibus_adr),
+ .o_ibus_cyc (o_ibus_cyc),
+ .i_ibus_ack (i_ibus_ack));
+
+
+ serv_alu alu
+ (
+ .clk (clk),
+ .i_rst (i_rst),
+ .i_en (cnt_en),
+ .i_cnt0 (cnt0),
+ .i_rs1 (rs1),
+ .i_rs2 (rs2),
+ .i_imm (imm),
+ .i_op_b_rs2 (op_b_source),
+ .i_buf (bufreg_q),
+ .i_init (init),
+ .i_cnt_done (cnt_done),
+ .i_sub (alu_sub),
+ .i_bool_op (alu_bool_op),
+ .i_cmp_eq (alu_cmp_eq),
+ .i_cmp_uns (alu_cmp_uns),
+ .o_cmp (alu_cmp),
+ .i_shamt_en (alu_shamt_en),
+ .i_sh_right (alu_sh_right),
+ .i_sh_signed (alu_sh_signed),
+ .o_sh_done (alu_sh_done),
+ .i_rd_sel (alu_rd_sel),
+ .o_rd (alu_rd));
+
+ wire csr_in;
+ wire rf_csr_out;
+
+ serv_rf_if
+ #(.WITH_CSR (WITH_CSR))
+ rf_if
+ (//RF interface
+ .o_wreg0 (o_wreg0),
+ .o_wreg1 (o_wreg1),
+ .o_wen0 (o_wen0),
+ .o_wen1 (o_wen1),
+ .o_wdata0 (o_wdata0),
+ .o_wdata1 (o_wdata1),
+ .o_rreg0 (o_rreg0),
+ .o_rreg1 (o_rreg1),
+ .i_rdata0 (i_rdata0),
+ .i_rdata1 (i_rdata1),
+
+ //Trap interface
+ .i_trap (trap),
+ .i_mret (mret),
+ .i_mepc (o_ibus_adr[0]),
+ .i_mem_misalign (mem_misalign),
+ .i_bufreg_q (bufreg_q),
+ .i_bad_pc (bad_pc),
+ .o_csr_pc (csr_pc),
+ //CSR write port
+ .i_csr_en (csr_en),
+ .i_csr_addr (csr_addr),
+ .i_csr (csr_in),
+ //RD write port
+ .i_rd_wen (rd_en),
+ .i_rd_waddr (rd_addr),
+ .i_ctrl_rd (ctrl_rd),
+ .i_alu_rd (alu_rd),
+ .i_rd_alu_en (rd_alu_en),
+ .i_csr_rd (csr_rd),
+ .i_rd_csr_en (rd_csr_en),
+ .i_mem_rd (mem_rd),
+
+ //RS1 read port
+ .i_rs1_raddr (rs1_addr),
+ .o_rs1 (rs1),
+ //RS2 read port
+ .i_rs2_raddr (rs2_addr),
+ .o_rs2 (rs2),
+
+ //CSR read port
+ .o_csr (rf_csr_out));
+
+ serv_mem_if
+ #(.WITH_CSR (WITH_CSR))
+ mem_if
+ (
+ .i_clk (clk),
+ .i_en (cnt_en),
+ .i_mem_op (mem_op),
+ .i_signed (mem_signed),
+ .i_word (mem_word),
+ .i_half (mem_half),
+ .i_bytecnt (mem_bytecnt),
+ .i_rs2 (rs2),
+ .o_rd (mem_rd),
+ .i_lsb (lsb),
+ .o_misalign (mem_misalign),
+ //External interface
+ .o_wb_dat (o_dbus_dat),
+ .o_wb_sel (o_dbus_sel),
+ .i_wb_rdt (i_dbus_rdt),
+ .i_wb_ack (i_dbus_ack));
+
+ generate
+ if (WITH_CSR) begin
+ serv_csr csr
+ (
+ .i_clk (clk),
+ .i_en (cnt_en),
+ .i_cnt0to3 (cnt0to3),
+ .i_cnt2 (cnt2),
+ .i_cnt3 (cnt3),
+ .i_cnt7 (cnt7),
+ .i_cnt_done (cnt_done),
+ .i_e_op (e_op),
+ .i_ebreak (ebreak),
+ .i_mem_cmd (o_dbus_we),
+ .i_mem_misalign (mem_misalign),
+ .i_rf_csr_out (rf_csr_out),
+ .o_csr_in (csr_in),
+ .i_mtip (i_timer_irq),
+ .o_new_irq (new_irq),
+ .i_trap_taken (trap_taken),
+ .i_pending_irq (pending_irq),
+ .i_mstatus_en (csr_mstatus_en),
+ .i_mie_en (csr_mie_en ),
+ .i_mcause_en (csr_mcause_en ),
+ .i_csr_source (csr_source),
+ .i_mret (mret),
+ .i_d (csr_d_sel ? csr_imm : rs1),
+ .o_q (csr_rd));
+ end else begin
+ assign csr_in = 1'b0;
+ assign csr_rd = 1'b0;
+ assign new_irq = 1'b0;
+ end
+ endgenerate
+
+
+`ifdef RISCV_FORMAL
+ reg [31:0] pc = RESET_PC;
+
+ wire rs_en = (branch_op|mem_op|shift_op|slt_op) ? init : ctrl_pc_en;
+
+ always @(posedge clk) begin
+ rvfi_valid <= cnt_done & ctrl_pc_en & !i_rst;
+ rvfi_order <= rvfi_order + {63'd0,rvfi_valid};
+ if (o_ibus_cyc & i_ibus_ack)
+ rvfi_insn <= i_ibus_rdt;
+ if (o_wen0)
+ rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:1]};
+ if (cnt_done & ctrl_pc_en) begin
+ rvfi_pc_rdata <= pc;
+ if (!rd_en)
+ rvfi_rd_addr <= 5'd0;
+ if (!rd_en | !(|rd_addr))
+ rvfi_rd_wdata <= 32'd0;
+ end
+ rvfi_trap <= trap;
+ if (rvfi_valid) begin
+ rvfi_trap <= 1'b0;
+ pc <= rvfi_pc_wdata;
+ end
+
+ rvfi_halt <= 1'b0;
+ rvfi_intr <= 1'b0;
+ rvfi_mode <= 2'd3;
+ rvfi_ixl = 2'd1;
+ if (i_rf_ready) begin
+ rvfi_rs1_addr <= rs1_addr;
+ rvfi_rs2_addr <= rs2_addr;
+ rvfi_rd_addr <= rd_addr;
+ end
+ if (rs_en) begin
+ rvfi_rs1_rdata <= {rs1,rvfi_rs1_rdata[31:1]};
+ rvfi_rs2_rdata <= {rs2,rvfi_rs2_rdata[31:1]};
+ end
+
+ if (i_dbus_ack) begin
+ rvfi_mem_addr <= o_dbus_adr;
+ rvfi_mem_rmask <= o_dbus_we ? 4'b0000 : o_dbus_sel;
+ rvfi_mem_wmask <= o_dbus_we ? o_dbus_sel : 4'b0000;
+ rvfi_mem_rdata <= i_dbus_rdt;
+ rvfi_mem_wdata <= o_dbus_dat;
+ end
+ if (i_ibus_ack) begin
+ rvfi_mem_rmask <= 4'b0000;
+ rvfi_mem_wmask <= 4'b0000;
+ end
+ end
+ /* verilator lint_off COMBDLY */
+ always @(o_ibus_adr)
+ rvfi_pc_wdata <= o_ibus_adr;
+ /* verilator lint_on COMBDLY */
+
+
+`endif
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/rtl/shift_reg.v b/pythondata_cpu_serv/verilog/rtl/shift_reg.v
new file mode 100644
index 0000000..64b5ed7
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/rtl/shift_reg.v
@@ -0,0 +1,20 @@
+module shift_reg
+ #(parameter LEN = 0,
+ parameter INIT = 0)
+ (
+ input wire clk,
+ input wire i_rst,
+ input wire i_en,
+ input wire i_d,
+ output wire o_q,
+ output wire [LEN-2:0] o_par);
+
+ reg [LEN-1:0] data;
+ assign o_q = data[0];
+ assign o_par = data[LEN-1:1];
+ always @(posedge clk)
+ if (i_rst)
+ data <= INIT;
+ else if (i_en)
+ data <= {i_d, data[LEN-1:1]};
+endmodule
diff --git a/pythondata_cpu_serv/verilog/serv.core b/pythondata_cpu_serv/verilog/serv.core
new file mode 100644
index 0000000..fe9c899
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/serv.core
@@ -0,0 +1,47 @@
+CAPI=2:
+
+name : ::serv:1.0.1
+
+filesets:
+ core:
+ files:
+ - rtl/serv_params.vh : {is_include_file : true}
+ - rtl/shift_reg.v
+ - rtl/ser_shift.v
+ - rtl/serv_bufreg.v
+ - rtl/serv_alu.v
+ - rtl/serv_csr.v
+ - rtl/serv_ctrl.v
+ - rtl/serv_decode.v
+ - rtl/serv_mem_if.v
+ - rtl/serv_rf_if.v
+ - rtl/serv_rf_ram_if.v
+ - rtl/serv_rf_ram.v
+ - rtl/serv_state.v
+ - rtl/serv_top.v
+ - rtl/serv_rf_top.v
+ file_type : verilogSource
+
+targets:
+ default:
+ filesets : [core]
+ parameters : [RISCV_FORMAL, SERV_CLEAR_RAM]
+ toplevel : ["is_toplevel? (serv_rf_top)"]
+
+ lint:
+ default_tool : verilator
+ filesets : [core]
+ tools:
+ verilator:
+ mode : lint-only
+ toplevel : serv_rf_top
+
+parameters:
+ RISCV_FORMAL:
+ datatype : bool
+ paramtype : vlogdefine
+
+ SERV_CLEAR_RAM:
+ datatype : bool
+ paramtype : vlogdefine
+
diff --git a/pythondata_cpu_serv/verilog/servant.core b/pythondata_cpu_serv/verilog/servant.core
new file mode 100644
index 0000000..81fba29
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant.core
@@ -0,0 +1,282 @@
+CAPI=2:
+
+name : ::servant:1.0.1
+
+filesets:
+ service:
+ files: [servant/ice40_pll.v, servant/service.v]
+ file_type : verilogSource
+ depend : ["fusesoc:utils:generators"]
+
+ mem_files:
+ files:
+ - sw/blinky.hex : {copyto : blinky.hex}
+ - sw/zephyr_hello.hex : {copyto : zephyr_hello.hex}
+ file_type : user
+
+ servant_tb:
+ files:
+ - bench/servant_sim.v
+ - "!tool_verilator? (bench/uart_decoder.v)"
+ - "!tool_verilator? (bench/servant_tb.v)"
+ - "tool_verilator? (bench/servant_tb.cpp)" : {file_type : cppSource}
+ file_type : verilogSource
+ depend : [vlog_tb_utils]
+
+ soc:
+ files:
+ - servant/servant_clock_gen.v
+ - servant/servant_timer.v
+ - servant/servant_gpio.v
+ - servant/servant_arbiter.v
+ - servant/servant_mux.v
+ - "tool_quartus? (servant/servant_ram_quartus.sv)" : {file_type : systemVerilogSource}
+ - "!tool_quartus? (servant/servant_ram.v)"
+ - servant/servant.v
+ file_type : verilogSource
+ depend : [serv]
+
+ cyc1000:
+ files:
+ - data/cyc1000.sdc : {file_type : SDC}
+ - data/cyc1000.tcl : {file_type : tclSource}
+ - servant/servclone10_clock_gen.v : {file_type : verilogSource}
+ - servant/servclone10.v : {file_type : verilogSource}
+
+ tinyfpga_bx: {files: [data/tinyfpga_bx.pcf : {file_type : PCF}]}
+ icebreaker : {files: [data/icebreaker.pcf : {file_type : PCF}]}
+ alhambra : {files: [data/alhambra.pcf : {file_type : PCF}]}
+
+ nexys_a7:
+ files:
+ - servant/servix_clock_gen.v : {file_type : verilogSource}
+ - servant/servix.v : {file_type : verilogSource}
+ - data/nexys_a7.xdc : {file_type : xdc}
+ arty_a7_35t:
+ files:
+ - servant/servix_clock_gen.v : {file_type : verilogSource}
+ - servant/servix.v : {file_type : verilogSource}
+ - data/arty_a7_35t.xdc : {file_type : xdc}
+
+ ulx3s:
+ files:
+ - data/ulx3s.lpf : {file_type : LPF}
+ - servant/ecppll.v : {file_type : verilogSource}
+ - servant/servant_ecp5_clock_gen.v : {file_type : verilogSource}
+ - servant/servant_ecp5.v : {file_type : verilogSource}
+
+ upduino2:
+ files:
+ - servant/servant_upduino2.v : {file_type : verilogSource}
+ - data/upduino2.pcf : {file_type : PCF}
+
+ zcu106:
+ files:
+ - servant/servus_clock_gen.v : {file_type : verilogSource}
+ - servant/servus.v : {file_type : verilogSource}
+ - data/zcu106.xdc : {file_type : xdc}
+
+targets:
+ default:
+ filesets : [soc]
+
+ cyc1000:
+ default_tool: quartus
+ description: cyc1000 FPGA board
+ filesets : [mem_files, soc, cyc1000]
+ parameters : [memfile, memsize=32768]
+ tools:
+ quartus:
+ family : Cyclone 10 LP
+ device : 10CL025YU256C8G
+ toplevel : servclone10
+
+ icebreaker:
+ default_tool : icestorm
+ filesets : [mem_files, soc, service, icebreaker]
+ generate: [icebreaker_pll]
+ parameters : [memfile, memsize, PLL=ICE40_PAD]
+ tools:
+ icestorm:
+ nextpnr_options: [--up5k, --freq, 16]
+ pnr: next
+ toplevel : service
+
+ tinyfpga_bx:
+ default_tool : icestorm
+ filesets : [mem_files, soc, service, tinyfpga_bx]
+ generate: [tinyfpga_bx_pll]
+ parameters : [memfile, memsize, PLL=ICE40_CORE]
+ tools:
+ icestorm:
+ nextpnr_options : [--lp8k, --package, cm81, --freq, 32]
+ pnr: next
+ toplevel : service
+
+ alhambra:
+ default_tool : icestorm
+ description: Open-hardware iCE40HX4K FPGA board
+ filesets : [mem_files, soc, service, alhambra]
+ generate: [alhambra_pll]
+ parameters : [memfile, memsize, PLL=ICE40_CORE]
+ tools:
+ icestorm:
+ nextpnr_options : [--hx8k, --package, tq144:4k, --freq, 16]
+ pnr: next
+ toplevel : service
+
+ lint:
+ default_tool : verilator
+ filesets : [soc]
+ tools:
+ verilator:
+ mode : lint-only
+ toplevel : servant
+
+ nexys_a7:
+ default_tool: vivado
+ filesets : [mem_files, soc, nexys_a7]
+ parameters : [memfile, memsize, frequency=32]
+ tools:
+ vivado: {part : xc7a100tcsg324-1}
+ toplevel : servix
+
+ arty_a7_35t:
+ default_tool: vivado
+ filesets : [mem_files, soc, arty_a7_35t]
+ parameters : [memfile, memsize, frequency=16]
+ tools:
+ vivado: {part : xc7a35ticsg324-1L}
+ toplevel : servix
+
+ sim:
+ default_tool: icarus
+ filesets : [soc, servant_tb]
+ parameters :
+ - RISCV_FORMAL
+ - SERV_CLEAR_RAM=true
+ - firmware
+ - memsize
+ toplevel : servant_tb
+
+ ulx3s_85:
+ default_tool: diamond
+ description : ULX3S 85k version
+ filesets : [mem_files, soc, ulx3s]
+ parameters : [memfile, memsize]
+ tools:
+ diamond:
+ part : LFE5U-85F-6BG381C
+ trellis:
+ nextpnr_options : [--package, CABGA381, --85k]
+ toplevel: servant_ecp5
+
+ upduino2:
+ default_tool : icestorm
+ filesets : [mem_files, soc, upduino2]
+ parameters : [memfile, memsize]
+ tools:
+ icestorm:
+ nextpnr_options: [--package, sg48, --up5k, --freq, 24]
+ pnr: next
+ toplevel : servant_upduino2
+
+ verilator_tb:
+ default_tool: verilator
+ filesets : [soc, servant_tb]
+ parameters :
+ - RISCV_FORMAL
+ - firmware
+ - memsize
+ - signature
+ - timeout
+ - uart_baudrate
+ - vcd
+ - vcd_start
+ tools:
+ verilator:
+ verilator_options : [--trace]
+ toplevel : servant_sim
+
+ zcu106:
+ default_tool: vivado
+ description : Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit
+ filesets : [mem_files, soc, zcu106]
+ parameters : [memfile, memsize]
+ tools:
+ vivado: {part : xczu7ev-ffvc1156-2-e}
+ toplevel : servus
+
+parameters:
+ PLL:
+ datatype : str
+ description : PLL type to use for main clock generation
+ paramtype : vlogparam
+
+ RISCV_FORMAL:
+ datatype : bool
+ paramtype : vlogdefine
+
+ SERV_CLEAR_RAM:
+ datatype : bool
+ paramtype : vlogdefine
+
+ firmware:
+ datatype : file
+ description : Preload RAM with a hex file at runtime (overrides memfile)
+ paramtype : plusarg
+
+ frequency:
+ datatype : int
+ description : PLL output frequency
+ paramtype : vlogparam
+
+ memfile:
+ datatype : file
+ description : Preload RAM with a hex file at compile-time
+ paramtype : vlogparam
+
+ memsize:
+ datatype : int
+ default : 8192
+ description : Memory size in bytes for RAM (default 8kiB)
+ paramtype : vlogparam
+
+ signature:
+ datatype : file
+ paramtype : plusarg
+ uart_baudrate:
+ datatype : int
+ description : Treat q output as an UART with the specified baudrate (0 or omitted parameter disables UART decoding)
+ paramtype : plusarg
+
+ timeout:
+ datatype : int
+ paramtype : plusarg
+
+ vcd:
+ datatype : bool
+ paramtype : plusarg
+
+ vcd_start:
+ datatype : int
+ description : Delay start of VCD dumping until the specified time
+ paramtype : plusarg
+
+generate:
+ icebreaker_pll:
+ generator: icepll
+ parameters:
+ freq_out : 16
+
+ tinyfpga_bx_pll:
+ generator: icepll
+ parameters:
+ freq_in : 16
+ freq_out : 32
+
+ alhambra_pll:
+ generator: icepll
+ parameters:
+ freq_in : 12
+ freq_out : 16
diff --git a/pythondata_cpu_serv/verilog/servant/ecppll.v b/pythondata_cpu_serv/verilog/servant/ecppll.v
new file mode 100644
index 0000000..bae4953
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/ecppll.v
@@ -0,0 +1,38 @@
+module pll(input clki,
+ output locked,
+ output clko
+);
+wire clkfb;
+wire clkos;
+wire clkop;
+(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
+EHXPLLL #(
+ .PLLRST_ENA("DISABLED"),
+ .INTFB_WAKE("DISABLED"),
+ .STDBY_ENABLE("DISABLED"),
+ .DPHASE_SOURCE("DISABLED"),
+ .CLKOP_FPHASE(0),
+ .CLKOP_CPHASE(18),
+ .OUTDIVIDER_MUXA("DIVA"),
+ .CLKOP_ENABLE("ENABLED"),
+ .CLKOP_DIV(38),
+ .CLKFB_DIV(5),
+ .CLKI_DIV(8),
+ .FEEDBK_PATH("INT_OP")
+ ) pll_i (
+ .CLKI(clki),
+ .CLKFB(clkfb),
+ .CLKINTFB(clkfb),
+ .CLKOP(clkop),
+ .RST(1'b0),
+ .STDBY(1'b0),
+ .PHASESEL0(1'b0),
+ .PHASESEL1(1'b0),
+ .PHASEDIR(1'b0),
+ .PHASESTEP(1'b0),
+ .PLLWAKESYNC(1'b0),
+ .ENCLKOP(1'b0),
+ .LOCK(locked)
+ );
+assign clko = clkop;
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/ice40_pll.v b/pythondata_cpu_serv/verilog/servant/ice40_pll.v
new file mode 100644
index 0000000..8daad94
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/ice40_pll.v
@@ -0,0 +1,40 @@
+`default_nettype none
+module ice40_pll
+ (
+ input i_clk,
+ output o_clk,
+ output o_rst);
+
+ parameter PLL = "NONE";
+
+ wire locked;
+
+ reg [1:0] rst_reg;
+ always @(posedge o_clk)
+ rst_reg <= {!locked, rst_reg[1]};
+ assign o_rst = rst_reg[0];
+
+ generate
+ if (PLL == "ICE40_CORE") begin
+ SB_PLL40_CORE
+ #(`include "pll.vh")
+ pll
+ (
+ .LOCK(locked),
+ .RESETB(1'b1),
+ .BYPASS(1'b0),
+ .REFERENCECLK(i_clk),
+ .PLLOUTCORE(o_clk));
+ end else if (PLL == "ICE40_PAD") begin
+ SB_PLL40_PAD
+ #(`include "pll.vh")
+ pll
+ (
+ .LOCK(locked),
+ .RESETB(1'b1),
+ .BYPASS(1'b0),
+ .PACKAGEPIN (i_clk),
+ .PLLOUTCORE(o_clk));
+ end
+ endgenerate
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servant.v b/pythondata_cpu_serv/verilog/servant/servant.v
new file mode 100644
index 0000000..a5e6424
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servant.v
@@ -0,0 +1,189 @@
+`default_nettype none
+module servant
+(
+ input wire wb_clk,
+ input wire wb_rst,
+ output wire q);
+
+ parameter memfile = "zephyr_hello.hex";
+ parameter memsize = 8192;
+ parameter sim = 0;
+ parameter with_csr = 1;
+
+ wire timer_irq;
+
+ wire [31:0] wb_ibus_adr;
+ wire wb_ibus_cyc;
+ wire [31:0] wb_ibus_rdt;
+ wire wb_ibus_ack;
+
+ wire [31:0] wb_dbus_adr;
+ wire [31:0] wb_dbus_dat;
+ wire [3:0] wb_dbus_sel;
+ wire wb_dbus_we;
+ wire wb_dbus_cyc;
+ wire [31:0] wb_dbus_rdt;
+ wire wb_dbus_ack;
+
+ wire [31:0] wb_dmem_adr;
+ wire [31:0] wb_dmem_dat;
+ wire [3:0] wb_dmem_sel;
+ wire wb_dmem_we;
+ wire wb_dmem_cyc;
+ wire [31:0] wb_dmem_rdt;
+ wire wb_dmem_ack;
+
+ wire [31:0] wb_mem_adr;
+ wire [31:0] wb_mem_dat;
+ wire [3:0] wb_mem_sel;
+ wire wb_mem_we;
+ wire wb_mem_cyc;
+ wire [31:0] wb_mem_rdt;
+ wire wb_mem_ack;
+
+ wire wb_gpio_dat;
+ wire wb_gpio_we;
+ wire wb_gpio_cyc;
+ wire wb_gpio_rdt;
+
+ wire [31:0] wb_timer_dat;
+ wire wb_timer_we;
+ wire wb_timer_cyc;
+ wire [31:0] wb_timer_rdt;
+
+ servant_arbiter arbiter
+ (.i_wb_cpu_dbus_adr (wb_dmem_adr),
+ .i_wb_cpu_dbus_dat (wb_dmem_dat),
+ .i_wb_cpu_dbus_sel (wb_dmem_sel),
+ .i_wb_cpu_dbus_we (wb_dmem_we ),
+ .i_wb_cpu_dbus_cyc (wb_dmem_cyc),
+ .o_wb_cpu_dbus_rdt (wb_dmem_rdt),
+ .o_wb_cpu_dbus_ack (wb_dmem_ack),
+
+ .i_wb_cpu_ibus_adr (wb_ibus_adr),
+ .i_wb_cpu_ibus_cyc (wb_ibus_cyc),
+ .o_wb_cpu_ibus_rdt (wb_ibus_rdt),
+ .o_wb_cpu_ibus_ack (wb_ibus_ack),
+
+ .o_wb_cpu_adr (wb_mem_adr),
+ .o_wb_cpu_dat (wb_mem_dat),
+ .o_wb_cpu_sel (wb_mem_sel),
+ .o_wb_cpu_we (wb_mem_we ),
+ .o_wb_cpu_cyc (wb_mem_cyc),
+ .i_wb_cpu_rdt (wb_mem_rdt),
+ .i_wb_cpu_ack (wb_mem_ack));
+
+ servant_mux #(sim) servant_mux
+ (
+ .i_clk (wb_clk),
+ .i_rst (wb_rst),
+ .i_wb_cpu_adr (wb_dbus_adr),
+ .i_wb_cpu_dat (wb_dbus_dat),
+ .i_wb_cpu_sel (wb_dbus_sel),
+ .i_wb_cpu_we (wb_dbus_we),
+ .i_wb_cpu_cyc (wb_dbus_cyc),
+ .o_wb_cpu_rdt (wb_dbus_rdt),
+ .o_wb_cpu_ack (wb_dbus_ack),
+
+ .o_wb_mem_adr (wb_dmem_adr),
+ .o_wb_mem_dat (wb_dmem_dat),
+ .o_wb_mem_sel (wb_dmem_sel),
+ .o_wb_mem_we (wb_dmem_we),
+ .o_wb_mem_cyc (wb_dmem_cyc),
+ .i_wb_mem_rdt (wb_dmem_rdt),
+
+ .o_wb_gpio_dat (wb_gpio_dat),
+ .o_wb_gpio_we (wb_gpio_we),
+ .o_wb_gpio_cyc (wb_gpio_cyc),
+ .i_wb_gpio_rdt (wb_gpio_rdt),
+
+ .o_wb_timer_dat (wb_timer_dat),
+ .o_wb_timer_we (wb_timer_we),
+ .o_wb_timer_cyc (wb_timer_cyc),
+ .i_wb_timer_rdt (wb_timer_rdt));
+
+ servant_ram
+ #(.memfile (memfile),
+ .depth (memsize))
+ ram
+ (// Wishbone interface
+ .i_wb_clk (wb_clk),
+ .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]),
+ .i_wb_cyc (wb_mem_cyc),
+ .i_wb_we (wb_mem_we) ,
+ .i_wb_sel (wb_mem_sel),
+ .i_wb_dat (wb_mem_dat),
+ .o_wb_rdt (wb_mem_rdt),
+ .o_wb_ack (wb_mem_ack));
+
+ generate
+ if (with_csr) begin
+ servant_timer
+ #(.WIDTH (32))
+ timer
+ (.i_clk (wb_clk),
+ .o_irq (timer_irq),
+ .i_wb_cyc (wb_timer_cyc),
+ .i_wb_we (wb_timer_we) ,
+ .i_wb_dat (wb_timer_dat),
+ .o_wb_dat (wb_timer_rdt));
+ end else begin
+ assign wb_timer_rdt = 32'd0;
+ assign timer_irq = 1'b0;
+ end
+ endgenerate
+
+ servant_gpio gpio
+ (.i_wb_clk (wb_clk),
+ .i_wb_dat (wb_gpio_dat),
+ .i_wb_we (wb_gpio_we),
+ .i_wb_cyc (wb_gpio_cyc),
+ .o_wb_rdt (wb_gpio_rdt),
+ .o_gpio (q));
+
+ serv_rf_top
+ #(.RESET_PC (32'h0000_0000),
+ .WITH_CSR (with_csr))
+ cpu
+ (
+ .clk (wb_clk),
+ .i_rst (wb_rst),
+ .i_timer_irq (timer_irq),
+`ifdef RISCV_FORMAL
+ .rvfi_valid (),
+ .rvfi_order (),
+ .rvfi_insn (),
+ .rvfi_trap (),
+ .rvfi_halt (),
+ .rvfi_intr (),
+ .rvfi_mode (),
+ .rvfi_ixl (),
+ .rvfi_rs1_addr (),
+ .rvfi_rs2_addr (),
+ .rvfi_rs1_rdata (),
+ .rvfi_rs2_rdata (),
+ .rvfi_rd_addr (),
+ .rvfi_rd_wdata (),
+ .rvfi_pc_rdata (),
+ .rvfi_pc_wdata (),
+ .rvfi_mem_addr (),
+ .rvfi_mem_rmask (),
+ .rvfi_mem_wmask (),
+ .rvfi_mem_rdata (),
+ .rvfi_mem_wdata (),
+`endif
+
+ .o_ibus_adr (wb_ibus_adr),
+ .o_ibus_cyc (wb_ibus_cyc),
+ .i_ibus_rdt (wb_ibus_rdt),
+ .i_ibus_ack (wb_ibus_ack),
+
+ .o_dbus_adr (wb_dbus_adr),
+ .o_dbus_dat (wb_dbus_dat),
+ .o_dbus_sel (wb_dbus_sel),
+ .o_dbus_we (wb_dbus_we),
+ .o_dbus_cyc (wb_dbus_cyc),
+ .i_dbus_rdt (wb_dbus_rdt),
+ .i_dbus_ack (wb_dbus_ack));
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servant_arbiter.v b/pythondata_cpu_serv/verilog/servant/servant_arbiter.v
new file mode 100644
index 0000000..00b39c8
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servant_arbiter.v
@@ -0,0 +1,39 @@
+/* Arbitrates between dbus and ibus accesses.
+ * Relies on the fact that not both masters are active at the same time
+ */
+module servant_arbiter
+ (
+ input wire [31:0] i_wb_cpu_dbus_adr,
+ input wire [31:0] i_wb_cpu_dbus_dat,
+ input wire [3:0] i_wb_cpu_dbus_sel,
+ input wire i_wb_cpu_dbus_we,
+ input wire i_wb_cpu_dbus_cyc,
+ output wire [31:0] o_wb_cpu_dbus_rdt,
+ output wire o_wb_cpu_dbus_ack,
+
+ input wire [31:0] i_wb_cpu_ibus_adr,
+ input wire i_wb_cpu_ibus_cyc,
+ output wire [31:0] o_wb_cpu_ibus_rdt,
+ output wire o_wb_cpu_ibus_ack,
+
+ output wire [31:0] o_wb_cpu_adr,
+ output wire [31:0] o_wb_cpu_dat,
+ output wire [3:0] o_wb_cpu_sel,
+ output wire o_wb_cpu_we,
+ output wire o_wb_cpu_cyc,
+ input wire [31:0] i_wb_cpu_rdt,
+ input wire i_wb_cpu_ack);
+
+ assign o_wb_cpu_dbus_rdt = i_wb_cpu_rdt;
+ assign o_wb_cpu_dbus_ack = i_wb_cpu_ack & !i_wb_cpu_ibus_cyc;
+
+ assign o_wb_cpu_ibus_rdt = i_wb_cpu_rdt;
+ assign o_wb_cpu_ibus_ack = i_wb_cpu_ack & i_wb_cpu_ibus_cyc;
+
+ assign o_wb_cpu_adr = i_wb_cpu_ibus_cyc ? i_wb_cpu_ibus_adr : i_wb_cpu_dbus_adr;
+ assign o_wb_cpu_dat = i_wb_cpu_dbus_dat;
+ assign o_wb_cpu_sel = i_wb_cpu_dbus_sel;
+ assign o_wb_cpu_we = i_wb_cpu_dbus_we & !i_wb_cpu_ibus_cyc;
+ assign o_wb_cpu_cyc = i_wb_cpu_ibus_cyc | i_wb_cpu_dbus_cyc;
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servant_clock_gen.v b/pythondata_cpu_serv/verilog/servant/servant_clock_gen.v
new file mode 100644
index 0000000..c430de8
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servant_clock_gen.v
@@ -0,0 +1,26 @@
+`default_nettype none
+module servant_clock_gen
+ (
+ input wire i_clk,
+ output wire o_clk,
+ output wire o_rst);
+
+ parameter [79:0] PLL = "NONE";
+
+ generate
+ if ((PLL == "ICE40_CORE") || (PLL == "ICE40_PAD")) begin
+ ice40_pll #(.PLL (PLL)) pll
+ (.i_clk (i_clk),
+ .o_clk (o_clk),
+ .o_rst (o_rst));
+ end else begin
+ assign o_clk = i_clk;
+
+ reg [4:0] rst_reg = 5'b11111;
+
+ always @(posedge o_clk)
+ rst_reg <= {1'b0, rst_reg[4:1]};
+ assign o_rst = rst_reg[0];
+ end
+ endgenerate
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servant_ecp5.v b/pythondata_cpu_serv/verilog/servant/servant_ecp5.v
new file mode 100644
index 0000000..a868d57
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servant_ecp5.v
@@ -0,0 +1,33 @@
+`default_nettype none
+module servant_ecp5
+(
+ input wire clk,
+ input wire btn0,
+ output wire wifi_gpio0,
+ output wire uart_txd,
+ output wire q);
+
+ parameter memfile = "zephyr_hello.hex";
+ parameter memsize = 8192;
+
+ wire wb_clk;
+ wire wb_rst;
+
+ assign wifi_gpio0 = btn0;
+ assign uart_txd = q;
+
+ servant_ecp5_clock_gen clock_gen
+ (.i_clk (clk),
+ .i_rst (!btn0),
+ .o_clk (wb_clk),
+ .o_rst (wb_rst));
+
+ servant
+ #(.memfile (memfile),
+ .memsize (memsize))
+ servant
+ (.wb_clk (wb_clk),
+ .wb_rst (wb_rst),
+ .q (q));
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servant_ecp5_clock_gen.v b/pythondata_cpu_serv/verilog/servant/servant_ecp5_clock_gen.v
new file mode 100644
index 0000000..0c5d24a
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servant_ecp5_clock_gen.v
@@ -0,0 +1,25 @@
+`default_nettype none
+module servant_ecp5_clock_gen
+ (
+ input i_clk,
+ input i_rst,
+ output o_clk,
+ output o_rst);
+
+ wire locked;
+
+ reg [1:0] rst_reg;
+ always @(posedge o_clk)
+ if (i_rst)
+ rst_reg <= 2'b11;
+ else
+ rst_reg <= {!locked, rst_reg[1]};
+
+ assign o_rst = rst_reg[0];
+
+ pll pll
+ (.clki (i_clk),
+ .clko (o_clk),
+ .locked (locked));
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servant_gpio.v b/pythondata_cpu_serv/verilog/servant/servant_gpio.v
new file mode 100644
index 0000000..da1debc
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servant_gpio.v
@@ -0,0 +1,14 @@
+module servant_gpio
+ (input wire i_wb_clk,
+ input wire i_wb_dat,
+ input wire i_wb_we,
+ input wire i_wb_cyc,
+ output reg o_wb_rdt,
+ output reg o_gpio);
+
+ always @(posedge i_wb_clk) begin
+ o_wb_rdt <= o_gpio;
+ if (i_wb_cyc & i_wb_we)
+ o_gpio <= i_wb_dat;
+ end
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servant_mux.v b/pythondata_cpu_serv/verilog/servant/servant_mux.v
new file mode 100644
index 0000000..8c11eff
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servant_mux.v
@@ -0,0 +1,89 @@
+/*
+ mem = 00
+ gpio = 01
+ timer = 10
+ testcon = 11
+ */
+module servant_mux
+ (
+ input wire i_clk,
+ input wire i_rst,
+ input wire [31:0] i_wb_cpu_adr,
+ input wire [31:0] i_wb_cpu_dat,
+ input wire [3:0] i_wb_cpu_sel,
+ input wire i_wb_cpu_we,
+ input wire i_wb_cpu_cyc,
+ output wire [31:0] o_wb_cpu_rdt,
+ output reg o_wb_cpu_ack,
+
+ output wire [31:0] o_wb_mem_adr,
+ output wire [31:0] o_wb_mem_dat,
+ output wire [3:0] o_wb_mem_sel,
+ output wire o_wb_mem_we,
+ output wire o_wb_mem_cyc,
+ input wire [31:0] i_wb_mem_rdt,
+
+ output wire o_wb_gpio_dat,
+ output wire o_wb_gpio_we,
+ output wire o_wb_gpio_cyc,
+ input wire i_wb_gpio_rdt,
+
+ output wire [31:0] o_wb_timer_dat,
+ output wire o_wb_timer_we,
+ output wire o_wb_timer_cyc,
+ input wire [31:0] i_wb_timer_rdt);
+
+ parameter sim = 0;
+
+ wire [1:0] s = i_wb_cpu_adr[31:30];
+
+ assign o_wb_cpu_rdt = s[1] ? i_wb_timer_rdt :
+ s[0] ? {31'd0,i_wb_gpio_rdt} : i_wb_mem_rdt;
+ always @(posedge i_clk) begin
+ o_wb_cpu_ack <= 1'b0;
+ if (i_wb_cpu_cyc & !o_wb_cpu_ack)
+ o_wb_cpu_ack <= 1'b1;
+ if (i_rst)
+ o_wb_cpu_ack <= 1'b0;
+ end
+
+ assign o_wb_mem_adr = i_wb_cpu_adr;
+ assign o_wb_mem_dat = i_wb_cpu_dat;
+ assign o_wb_mem_sel = i_wb_cpu_sel;
+ assign o_wb_mem_we = i_wb_cpu_we;
+ assign o_wb_mem_cyc = i_wb_cpu_cyc & (s == 2'b00);
+
+ assign o_wb_gpio_dat = i_wb_cpu_dat[0];
+ assign o_wb_gpio_we = i_wb_cpu_we;
+ assign o_wb_gpio_cyc = i_wb_cpu_cyc & (s == 2'b01);
+
+ assign o_wb_timer_dat = i_wb_cpu_dat;
+ assign o_wb_timer_we = i_wb_cpu_we;
+ assign o_wb_timer_cyc = i_wb_cpu_cyc & s[1];
+
+ generate
+ if (sim) begin
+ wire sig_en = (i_wb_cpu_adr[31:28] == 4'h8) & i_wb_cpu_cyc & o_wb_cpu_ack;
+ wire halt_en = (i_wb_cpu_adr[31:28] == 4'h9) & i_wb_cpu_cyc & o_wb_cpu_ack;
+
+ reg [1023:0] signature_file;
+ integer f = 0;
+
+ initial
+ /* verilator lint_off WIDTH */
+ if ($value$plusargs("signature=%s", signature_file)) begin
+ $display("Writing signature to %0s", signature_file);
+ f = $fopen(signature_file, "w");
+ end
+ /* verilator lint_on WIDTH */
+
+ always @(posedge i_clk)
+ if (sig_en & (f != 0))
+ $fwrite(f, "%c", i_wb_cpu_dat[7:0]);
+ else if(halt_en) begin
+ $display("Test complete");
+ $finish;
+ end
+ end
+ endgenerate
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servant_ram.v b/pythondata_cpu_serv/verilog/servant/servant_ram.v
new file mode 100644
index 0000000..11e058c
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servant_ram.v
@@ -0,0 +1,39 @@
+`default_nettype none
+module servant_ram
+ #(//Memory parameters
+ parameter depth = 256,
+ parameter aw = $clog2(depth),
+ parameter memfile = "")
+ (input wire i_wb_clk,
+ input wire [aw-1:2] i_wb_adr,
+ input wire [31:0] i_wb_dat,
+ input wire [3:0] i_wb_sel,
+ input wire i_wb_we,
+ input wire i_wb_cyc,
+ output reg [31:0] o_wb_rdt,
+ output reg o_wb_ack);
+
+ wire [3:0] we = {4{i_wb_we & i_wb_cyc}} & i_wb_sel;
+
+ reg [31:0] mem [0:depth/4-1] /* verilator public */;
+
+ wire [aw-3:0] addr = i_wb_adr[aw-1:2];
+
+ always @(posedge i_wb_clk)
+ o_wb_ack <= i_wb_cyc & !o_wb_ack;
+
+ always @(posedge i_wb_clk) begin
+ if (we[0]) mem[addr][7:0] <= i_wb_dat[7:0];
+ if (we[1]) mem[addr][15:8] <= i_wb_dat[15:8];
+ if (we[2]) mem[addr][23:16] <= i_wb_dat[23:16];
+ if (we[3]) mem[addr][31:24] <= i_wb_dat[31:24];
+ o_wb_rdt <= mem[addr];
+ end
+
+ initial
+ if(|memfile) begin
+ $display("Preloading %m from %s", memfile);
+ $readmemh(memfile, mem);
+ end
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servant_ram_quartus.sv b/pythondata_cpu_serv/verilog/servant/servant_ram_quartus.sv
new file mode 100644
index 0000000..8073359
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servant_ram_quartus.sv
@@ -0,0 +1,41 @@
+`default_nettype none
+module servant_ram
+ #(//Memory parameters
+ parameter depth = 256,
+ parameter aw = $clog2(depth),
+ parameter memfile = "")
+ (input wire i_wb_clk,
+ input wire [aw-1:2] i_wb_adr,
+ input wire [31:0] i_wb_dat,
+ input wire [3:0] i_wb_sel,
+ input wire i_wb_we,
+ input wire i_wb_cyc,
+ output reg [31:0] o_wb_rdt,
+ output reg o_wb_ack);
+
+ wire we = i_wb_we & i_wb_cyc;
+
+ logic [3:0][7:0] mem[0:depth/4-1];
+
+ wire [aw-3:0] addr = i_wb_adr[aw-1:2];
+
+ always @(posedge i_wb_clk)
+ o_wb_ack <= i_wb_cyc & !o_wb_ack;
+
+ always_ff @(posedge i_wb_clk) begin
+ if(we) begin
+ if(i_wb_sel[0]) mem[addr][0] <= i_wb_dat[7:0];
+ if(i_wb_sel[1]) mem[addr][1] <= i_wb_dat[15:8];
+ if(i_wb_sel[2]) mem[addr][2] <= i_wb_dat[23:16];
+ if(i_wb_sel[3]) mem[addr][3] <= i_wb_dat[31:24];
+ end
+ o_wb_rdt <= mem[addr];
+ end
+
+ initial
+ if(|memfile) begin
+ $display("Preloading %m from %s", memfile);
+ $readmemh(memfile, mem);
+ end
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servant_timer.v b/pythondata_cpu_serv/verilog/servant/servant_timer.v
new file mode 100644
index 0000000..28bdb82
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servant_timer.v
@@ -0,0 +1,30 @@
+`default_nettype none
+module servant_timer
+ #(parameter WIDTH = 16,
+ parameter DIVIDER = 0)
+ (input wire i_clk,
+ output reg o_irq,
+ input wire [31:0] i_wb_dat,
+ input wire i_wb_we,
+ input wire i_wb_cyc,
+ output reg [31:0] o_wb_dat);
+
+ localparam HIGH = WIDTH-1-DIVIDER;
+
+ reg [WIDTH-1:0] mtime;
+ reg [HIGH:0] mtimecmp;
+
+ wire [HIGH:0] mtimeslice = mtime[WIDTH-1:DIVIDER];
+
+ always @(mtimeslice) begin
+ o_wb_dat = 32'd0;
+ o_wb_dat[HIGH:0] = mtimeslice;
+ end
+
+ always @(posedge i_clk) begin
+ if (i_wb_cyc & i_wb_we)
+ mtimecmp <= i_wb_dat[HIGH:0];
+ mtime <= mtime + 'd1;
+ o_irq <= (mtimeslice >= mtimecmp);
+ end
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servant_upduino2.v b/pythondata_cpu_serv/verilog/servant/servant_upduino2.v
new file mode 100644
index 0000000..7c43004
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servant_upduino2.v
@@ -0,0 +1,77 @@
+`default_nettype none
+module servant_upduino2
+ (
+ output wire g,
+ output wire b,
+ output wire r,
+ output wire q);
+
+ parameter memfile = "zephyr_hello.hex";
+ parameter memsize = 8192;
+ parameter PLL = "NONE";
+
+ wire clk;
+ wire clk48;
+ wire locked;
+
+ SB_HFOSC inthosc
+ (
+ .CLKHFPU(1'b1),
+ .CLKHFEN(1'b1),
+ .CLKHF(clk48));
+
+ SB_PLL40_CORE
+ #(
+ .FEEDBACK_PATH("SIMPLE"),
+ .DIVR(4'b0010),
+ .DIVF(7'b0111111),
+ .DIVQ(3'b110),
+ .FILTER_RANGE(3'b001))
+ pll
+ (.LOCK(locked),
+ .RESETB(1'b1),
+ .BYPASS(1'b0),
+ .REFERENCECLK(clk48),
+ .PLLOUTCORE(clk));
+
+ SB_RGBA_DRV
+ #(
+ .CURRENT_MODE ("0b1"),
+ .RGB0_CURRENT ("0b000111"),
+ .RGB1_CURRENT ("0b000111"),
+ .RGB2_CURRENT ("0b000111"))
+ RGBA_DRIVER
+ (
+ .CURREN(1'b1),
+ .RGBLEDEN(1'b1),
+ .RGB0PWM(q),
+ .RGB1PWM(q),
+ .RGB2PWM(q),
+ .RGB0(g),
+ .RGB1(b),
+ .RGB2(r));
+
+ reg rst = 1'b1;
+
+/*
+ //Delayed reset
+ reg [25:0] cnt;
+ always @(posedge clk) begin
+ if (!cnt[25])
+ cnt <= cnt + 1;
+ rst <= !cnt[25];
+ end
+ */
+
+ always @(posedge clk)
+ rst <= !locked;
+
+ servant
+ #(.memfile (memfile),
+ .memsize (memsize))
+ servant
+ (.wb_clk (clk),
+ .wb_rst (rst),
+ .q (q));
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servclone10.v b/pythondata_cpu_serv/verilog/servant/servclone10.v
new file mode 100644
index 0000000..f2bf38d
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servclone10.v
@@ -0,0 +1,31 @@
+`default_nettype none
+module servclone10
+(
+ input wire i_clk,
+ input wire i_rst,
+ output wire q,
+ output wire uart_txd);
+
+ parameter memfile = "zephyr_hello.hex";
+ parameter memsize = 8192;
+
+ wire wb_clk;
+ wire wb_rst;
+
+ assign uart_txd = q;
+
+ servclone10_clock_gen clock_gen
+ (.i_clk (i_clk),
+ .i_rst (i_rst),
+ .o_clk (wb_clk),
+ .o_rst (wb_rst));
+
+ servant
+ #(.memfile (memfile),
+ .memsize (memsize))
+ servant
+ (.wb_clk (wb_clk),
+ .wb_rst (wb_rst),
+ .q (q));
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servclone10_clock_gen.v b/pythondata_cpu_serv/verilog/servant/servclone10_clock_gen.v
new file mode 100644
index 0000000..bf96ffd
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servclone10_clock_gen.v
@@ -0,0 +1,50 @@
+`default_nettype none
+module servclone10_clock_gen
+ (input wire i_clk,
+ input wire i_rst,
+ output wire o_clk,
+ output wire o_rst);
+
+ wire [4:0] clk;
+
+ wire clk_fb;
+
+ wire locked;
+ reg [9:0] r;
+
+ assign o_clk = clk[0];
+
+ assign o_rst = r[9];
+
+ always @(posedge o_clk)
+ if (locked)
+ r <= {r[8:0],1'b0};
+ else
+ r <= 10'b1111111111;
+
+ cyclone10lp_pll
+ #(.bandwidth_type ("auto"),
+ .clk0_divide_by (6),
+ .clk0_duty_cycle (50),
+ .clk0_multiply_by (16),
+ .clk0_phase_shift ("0"),
+ .compensate_clock ("clk0"),
+ .inclk0_input_frequency (83333),
+ .operation_mode ("normal"),
+ .pll_type ("auto"),
+ .lpm_type ("cyclone10lp_pll"))
+ pll
+ (.activeclock (),
+ .areset (i_rst),
+ .clk (clk),
+ .clkbad (),
+ .fbin (clk_fb),
+ .fbout (clk_fb),
+ .inclk (i_clk),
+ .locked (locked),
+ .phasedone (),
+ .scandataout (),
+ .scandone (),
+ .vcooverrange (),
+ .vcounderrange ());
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/service.v b/pythondata_cpu_serv/verilog/servant/service.v
new file mode 100644
index 0000000..0f60a99
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/service.v
@@ -0,0 +1,28 @@
+`default_nettype none
+module service
+(
+ input wire i_clk,
+ output wire q);
+
+ parameter memfile = "zephyr_hello.hex";
+ parameter memsize = 8192;
+ parameter PLL = "NONE";
+
+ wire wb_clk;
+ wire wb_rst;
+
+ servant_clock_gen #(.PLL (PLL))
+ clock_gen
+ (.i_clk (i_clk),
+ .o_clk (wb_clk),
+ .o_rst (wb_rst));
+
+ servant
+ #(.memfile (memfile),
+ .memsize (memsize))
+ servant
+ (.wb_clk (wb_clk),
+ .wb_rst (wb_rst),
+ .q (q));
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servix.v b/pythondata_cpu_serv/verilog/servant/servix.v
new file mode 100644
index 0000000..9b665ed
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servix.v
@@ -0,0 +1,30 @@
+`default_nettype none
+module servix
+(
+ input wire i_clk,
+ output wire q);
+
+ parameter frequency = 32;
+ parameter memfile = "zephyr_hello.hex";
+ parameter memsize = 8192;
+ parameter PLL = "NONE";
+
+ wire wb_clk;
+ wire wb_rst;
+
+ servix_clock_gen
+ #(.frequency (frequency))
+ clock_gen
+ (.i_clk (i_clk),
+ .o_clk (wb_clk),
+ .o_rst (wb_rst));
+
+ servant
+ #(.memfile (memfile),
+ .memsize (memsize))
+ servant
+ (.wb_clk (wb_clk),
+ .wb_rst (wb_rst),
+ .q (q));
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servix_clock_gen.v b/pythondata_cpu_serv/verilog/servant/servix_clock_gen.v
new file mode 100644
index 0000000..b44e75c
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servix_clock_gen.v
@@ -0,0 +1,39 @@
+`default_nettype none
+module servix_clock_gen
+ (input wire i_clk,
+ output wire o_clk,
+ output reg o_rst);
+
+ parameter frequency = 32;
+
+ wire clkfb;
+ wire locked;
+ reg locked_r;
+
+ PLLE2_BASE
+ #(.BANDWIDTH("OPTIMIZED"),
+ .CLKFBOUT_MULT(16),
+ .CLKIN1_PERIOD(10.0), //100MHz
+ .CLKOUT0_DIVIDE((frequency == 32) ? 50 : 100),
+ .DIVCLK_DIVIDE(1),
+ .STARTUP_WAIT("FALSE"))
+ PLLE2_BASE_inst
+ (.CLKOUT0(o_clk),
+ .CLKOUT1(),
+ .CLKOUT2(),
+ .CLKOUT3(),
+ .CLKOUT4(),
+ .CLKOUT5(),
+ .CLKFBOUT(clkfb),
+ .LOCKED(locked),
+ .CLKIN1(i_clk),
+ .PWRDWN(1'b0),
+ .RST(1'b0),
+ .CLKFBIN(clkfb));
+
+ always @(posedge o_clk) begin
+ locked_r <= locked;
+ o_rst <= !locked_r;
+ end
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servus.v b/pythondata_cpu_serv/verilog/servant/servus.v
new file mode 100644
index 0000000..05fa774
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servus.v
@@ -0,0 +1,36 @@
+`default_nettype none
+module servus
+ (input wire i_clk_p,
+ input wire i_clk_n,
+ output wire o_uart_tx,
+ output wire q);
+
+ parameter memfile = "zephyr_hello.hex";
+ parameter memsize = 8192;
+
+ wire i_clk;
+ wire clk;
+ wire rst;
+
+ assign o_uart_tx = q;
+
+ IBUFDS ibufds
+ (.I (i_clk_p),
+ .IB (i_clk_n),
+ .O (i_clk));
+
+ servus_clock_gen
+ clock_gen
+ (.i_clk (i_clk),
+ .o_clk (clk),
+ .o_rst (rst));
+
+ servant
+ #(.memfile (memfile),
+ .memsize (memsize))
+ servant
+ (.wb_clk (clk),
+ .wb_rst (rst),
+ .q (q));
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/servant/servus_clock_gen.v b/pythondata_cpu_serv/verilog/servant/servus_clock_gen.v
new file mode 100644
index 0000000..0e91c8c
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/servant/servus_clock_gen.v
@@ -0,0 +1,44 @@
+`default_nettype none
+module servus_clock_gen
+ (input wire i_clk,
+ output wire o_clk,
+ output reg o_rst);
+
+ wire clkfb;
+ wire locked;
+ reg locked_r;
+
+ MMCME4_ADV
+ #(.DIVCLK_DIVIDE (5),
+ .CLKFBOUT_MULT_F (48.000),
+ .CLKOUT0_DIVIDE_F (75.0),
+ .CLKIN1_PERIOD (8.0), //125MHz
+ .STARTUP_WAIT ("FALSE"))
+ mmcm
+ (.CLKFBOUT (clkfb),
+ .CLKFBOUTB (),
+ .CLKOUT0 (o_clk),
+ .CLKOUT0B (),
+ .CLKOUT1 (),
+ .CLKOUT1B (),
+ .CLKOUT2 (),
+ .CLKOUT2B (),
+ .CLKOUT3 (),
+ .CLKOUT3B (),
+ .CLKOUT4 (),
+ .CLKOUT5 (),
+ .CLKOUT6 (),
+ .CLKIN1 (i_clk),
+ .CLKIN2 (1'b0),
+ .CLKINSEL (1'b1),
+ .LOCKED (locked),
+ .PWRDWN (1'b0),
+ .RST (1'b0),
+ .CLKFBIN (clkfb));
+
+ always @(posedge o_clk) begin
+ locked_r <= locked;
+ o_rst <= !locked_r;
+ end
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/serving.core b/pythondata_cpu_serv/verilog/serving.core
new file mode 100644
index 0000000..63bca35
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/serving.core
@@ -0,0 +1,25 @@
+CAPI=2:
+
+name : ::serving:0
+
+filesets:
+ rtl:
+ files:
+ - serving/serving_arbiter.v
+ - serving/serving_mux.v
+ - serving/serving_ram.v
+ - serving/serving.v
+ file_type : verilogSource
+ depend : [serv]
+
+targets:
+ default:
+ filesets : [rtl]
+
+ lint:
+ default_tool : verilator
+ filesets : [rtl]
+ tools:
+ verilator:
+ mode : lint-only
+ toplevel : serving
diff --git a/pythondata_cpu_serv/verilog/serving/serving.v b/pythondata_cpu_serv/verilog/serving/serving.v
new file mode 100644
index 0000000..374bab4
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/serving/serving.v
@@ -0,0 +1,232 @@
+/* serving.v : Top-level for the serving SoC
+ *
+ * ISC License
+ *
+ * Copyright (C) 2020 Olof Kindgren
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+`default_nettype none
+module serving
+ (
+ input wire i_clk,
+ input wire i_rst,
+ input wire i_timer_irq,
+
+ output wire [31:0] o_wb_adr,
+ output wire [31:0] o_wb_dat,
+ output wire [3:0] o_wb_sel,
+ output wire o_wb_we ,
+ output wire o_wb_stb,
+ input wire [31:0] i_wb_rdt,
+ input wire i_wb_ack);
+
+ parameter memfile = "";
+ parameter memsize = 8192;
+ parameter WITH_CSR = 1;
+ localparam regs = 32+WITH_CSR*4;
+
+ localparam rf_width = 8;
+
+ localparam aw = $clog2(memsize);
+
+ wire [31:0] wb_ibus_adr;
+ wire wb_ibus_stb;
+ wire [31:0] wb_ibus_rdt;
+ wire wb_ibus_ack;
+
+ wire [31:0] wb_dbus_adr;
+ wire [31:0] wb_dbus_dat;
+ wire [3:0] wb_dbus_sel;
+ wire wb_dbus_we;
+ wire wb_dbus_stb;
+ wire [31:0] wb_dbus_rdt;
+ wire wb_dbus_ack;
+
+ wire [31:0] wb_dmem_adr;
+ wire [31:0] wb_dmem_dat;
+ wire [3:0] wb_dmem_sel;
+ wire wb_dmem_we;
+ wire wb_dmem_stb;
+ wire [31:0] wb_dmem_rdt;
+ wire wb_dmem_ack;
+
+ wire [31:0] wb_mem_adr;
+ wire [31:0] wb_mem_dat;
+ wire [3:0] wb_mem_sel;
+ wire wb_mem_we;
+ wire wb_mem_stb;
+ wire [31:0] wb_mem_rdt;
+ wire wb_mem_ack;
+
+ wire [6+WITH_CSR:0] waddr;
+ wire [rf_width-1:0] wdata;
+ wire wen;
+ wire [6+WITH_CSR:0] raddr;
+ wire [rf_width-1:0] rdata;
+
+
+ wire [aw-1:0] rf_waddr = ~{{aw-2-5-WITH_CSR{1'b0}},waddr};
+ wire [aw-1:0] rf_raddr = ~{{aw-2-5-WITH_CSR{1'b0}},raddr};
+
+ serving_arbiter arbiter
+ (.i_wb_cpu_dbus_adr (wb_dmem_adr),
+ .i_wb_cpu_dbus_dat (wb_dmem_dat),
+ .i_wb_cpu_dbus_sel (wb_dmem_sel),
+ .i_wb_cpu_dbus_we (wb_dmem_we ),
+ .i_wb_cpu_dbus_stb (wb_dmem_stb),
+ .o_wb_cpu_dbus_rdt (wb_dmem_rdt),
+ .o_wb_cpu_dbus_ack (wb_dmem_ack),
+
+ .i_wb_cpu_ibus_adr (wb_ibus_adr),
+ .i_wb_cpu_ibus_stb (wb_ibus_stb),
+ .o_wb_cpu_ibus_rdt (wb_ibus_rdt),
+ .o_wb_cpu_ibus_ack (wb_ibus_ack),
+
+ .o_wb_mem_adr (wb_mem_adr),
+ .o_wb_mem_dat (wb_mem_dat),
+ .o_wb_mem_sel (wb_mem_sel),
+ .o_wb_mem_we (wb_mem_we ),
+ .o_wb_mem_stb (wb_mem_stb),
+ .i_wb_mem_rdt (wb_mem_rdt),
+ .i_wb_mem_ack (wb_mem_ack));
+
+ serving_mux mux
+ (.i_clk (i_clk),
+ .i_rst (i_rst),
+
+ .i_wb_cpu_adr (wb_dbus_adr),
+ .i_wb_cpu_dat (wb_dbus_dat),
+ .i_wb_cpu_sel (wb_dbus_sel),
+ .i_wb_cpu_we (wb_dbus_we),
+ .i_wb_cpu_stb (wb_dbus_stb),
+ .o_wb_cpu_rdt (wb_dbus_rdt),
+ .o_wb_cpu_ack (wb_dbus_ack),
+
+ .o_wb_mem_adr (wb_dmem_adr),
+ .o_wb_mem_dat (wb_dmem_dat),
+ .o_wb_mem_sel (wb_dmem_sel),
+ .o_wb_mem_we (wb_dmem_we),
+ .o_wb_mem_stb (wb_dmem_stb),
+ .i_wb_mem_rdt (wb_dmem_rdt),
+ .i_wb_mem_ack (wb_dmem_ack),
+
+ .o_wb_ext_adr (o_wb_adr),
+ .o_wb_ext_dat (o_wb_dat),
+ .o_wb_ext_sel (o_wb_sel),
+ .o_wb_ext_we (o_wb_we),
+ .o_wb_ext_stb (o_wb_stb),
+ .i_wb_ext_rdt (i_wb_rdt),
+ .i_wb_ext_ack (i_wb_ack));
+
+ serving_ram
+ #(.memfile (memfile),
+ .depth (memsize))
+ ram
+ (// Wishbone interface
+ .i_clk (i_clk),
+ .i_waddr (rf_waddr),
+ .i_wdata (wdata),
+ .i_wen (wen),
+ .i_raddr (rf_raddr),
+ .o_rdata (rdata),
+ .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]),
+ .i_wb_stb (wb_mem_stb),
+ .i_wb_we (wb_mem_we) ,
+ .i_wb_sel (wb_mem_sel),
+ .i_wb_dat (wb_mem_dat),
+ .o_wb_rdt (wb_mem_rdt),
+ .o_wb_ack (wb_mem_ack));
+
+ localparam RF_L2W = $clog2(rf_width);
+
+ wire rf_wreq;
+ wire rf_rreq;
+ wire [$clog2(regs)-1:0] wreg0;
+ wire [$clog2(regs)-1:0] wreg1;
+ wire wen0;
+ wire wen1;
+ wire wdata0;
+ wire wdata1;
+ wire [$clog2(regs)-1:0] rreg0;
+ wire [$clog2(regs)-1:0] rreg1;
+ wire rf_ready;
+ wire rdata0;
+ wire rdata1;
+
+
+ serv_rf_ram_if
+ #(.width (rf_width),
+ .csr_regs (WITH_CSR*4))
+ rf_ram_if
+ (.i_clk (i_clk),
+ .i_rst (i_rst),
+ .i_wreq (rf_wreq),
+ .i_rreq (rf_rreq),
+ .o_ready (rf_ready),
+ .i_wreg0 (wreg0),
+ .i_wreg1 (wreg1),
+ .i_wen0 (wen0),
+ .i_wen1 (wen1),
+ .i_wdata0 (wdata0),
+ .i_wdata1 (wdata1),
+ .i_rreg0 (rreg0),
+ .i_rreg1 (rreg1),
+ .o_rdata0 (rdata0),
+ .o_rdata1 (rdata1),
+ .o_waddr (waddr),
+ .o_wdata (wdata),
+ .o_wen (wen),
+ .o_raddr (raddr),
+ .i_rdata (rdata));
+
+ serv_top
+ #(.RESET_PC (32'h0000_0000),
+ .WITH_CSR (WITH_CSR))
+ cpu
+ (
+ .clk (i_clk),
+ .i_rst (i_rst),
+ .i_timer_irq (i_timer_irq),
+ //RF IF
+ .o_rf_rreq (rf_rreq),
+ .o_rf_wreq (rf_wreq),
+ .i_rf_ready (rf_ready),
+ .o_wreg0 (wreg0),
+ .o_wreg1 (wreg1),
+ .o_wen0 (wen0),
+ .o_wen1 (wen1),
+ .o_wdata0 (wdata0),
+ .o_wdata1 (wdata1),
+ .o_rreg0 (rreg0),
+ .o_rreg1 (rreg1),
+ .i_rdata0 (rdata0),
+ .i_rdata1 (rdata1),
+
+ //Instruction bus
+ .o_ibus_adr (wb_ibus_adr),
+ .o_ibus_cyc (wb_ibus_stb),
+ .i_ibus_rdt (wb_ibus_rdt),
+ .i_ibus_ack (wb_ibus_ack),
+
+ //Data bus
+ .o_dbus_adr (wb_dbus_adr),
+ .o_dbus_dat (wb_dbus_dat),
+ .o_dbus_sel (wb_dbus_sel),
+ .o_dbus_we (wb_dbus_we),
+ .o_dbus_cyc (wb_dbus_stb),
+ .i_dbus_rdt (wb_dbus_rdt),
+ .i_dbus_ack (wb_dbus_ack));
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/serving/serving_arbiter.v b/pythondata_cpu_serv/verilog/serving/serving_arbiter.v
new file mode 100644
index 0000000..9d537d4
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/serving/serving_arbiter.v
@@ -0,0 +1,57 @@
+/* serving_arbiter.v : I/D arbiter for the serving SoC
+ * Relies on the fact that not both masters are active at the same time
+ *
+ * ISC License
+ *
+ * Copyright (C) 2020 Olof Kindgren
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+module serving_arbiter
+ (
+ input wire [31:0] i_wb_cpu_dbus_adr,
+ input wire [31:0] i_wb_cpu_dbus_dat,
+ input wire [3:0] i_wb_cpu_dbus_sel,
+ input wire i_wb_cpu_dbus_we,
+ input wire i_wb_cpu_dbus_stb,
+ output wire [31:0] o_wb_cpu_dbus_rdt,
+ output wire o_wb_cpu_dbus_ack,
+
+ input wire [31:0] i_wb_cpu_ibus_adr,
+ input wire i_wb_cpu_ibus_stb,
+ output wire [31:0] o_wb_cpu_ibus_rdt,
+ output wire o_wb_cpu_ibus_ack,
+
+ output wire [31:0] o_wb_mem_adr,
+ output wire [31:0] o_wb_mem_dat,
+ output wire [3:0] o_wb_mem_sel,
+ output wire o_wb_mem_we,
+ output wire o_wb_mem_stb,
+ input wire [31:0] i_wb_mem_rdt,
+ input wire i_wb_mem_ack);
+
+ assign o_wb_cpu_dbus_rdt = i_wb_mem_rdt;
+ assign o_wb_cpu_dbus_ack = i_wb_mem_ack & !i_wb_cpu_ibus_stb;
+
+ assign o_wb_cpu_ibus_rdt = i_wb_mem_rdt;
+ assign o_wb_cpu_ibus_ack = i_wb_mem_ack & i_wb_cpu_ibus_stb;
+
+ assign o_wb_mem_adr = i_wb_cpu_ibus_stb ? i_wb_cpu_ibus_adr : i_wb_cpu_dbus_adr;
+ assign o_wb_mem_dat = i_wb_cpu_dbus_dat;
+ assign o_wb_mem_sel = i_wb_cpu_dbus_sel;
+ assign o_wb_mem_we = i_wb_cpu_dbus_we & !i_wb_cpu_ibus_stb;
+ assign o_wb_mem_stb = i_wb_cpu_ibus_stb | i_wb_cpu_dbus_stb;
+
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/serving/serving_mux.v b/pythondata_cpu_serv/verilog/serving/serving_mux.v
new file mode 100644
index 0000000..daa1be8
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/serving/serving_mux.v
@@ -0,0 +1,66 @@
+/* serving_mux.v : Simple Wishbone mux for the serving SoC
+ *
+ * ISC License
+ *
+ * Copyright (C) 2020 Olof Kindgren
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+module serving_mux
+ (
+ input wire i_clk,
+ input wire i_rst,
+
+ input wire [31:0] i_wb_cpu_adr,
+ input wire [31:0] i_wb_cpu_dat,
+ input wire [3:0] i_wb_cpu_sel,
+ input wire i_wb_cpu_we,
+ input wire i_wb_cpu_stb,
+ output wire [31:0] o_wb_cpu_rdt,
+ output wire o_wb_cpu_ack,
+
+ output wire [31:0] o_wb_mem_adr,
+ output wire [31:0] o_wb_mem_dat,
+ output wire [3:0] o_wb_mem_sel,
+ output wire o_wb_mem_we,
+ output wire o_wb_mem_stb,
+ input wire [31:0] i_wb_mem_rdt,
+ input wire i_wb_mem_ack,
+
+ output wire [31:0] o_wb_ext_adr,
+ output wire [31:0] o_wb_ext_dat,
+ output wire [3:0] o_wb_ext_sel,
+ output wire o_wb_ext_we,
+ output wire o_wb_ext_stb,
+ input wire [31:0] i_wb_ext_rdt,
+ input wire i_wb_ext_ack);
+
+ wire ext = (i_wb_cpu_adr[31:30] != 2'b00);
+
+ assign o_wb_cpu_rdt = ext ? i_wb_ext_rdt : i_wb_mem_rdt;
+ assign o_wb_cpu_ack = ext ? i_wb_ext_ack : i_wb_mem_ack;
+
+ assign o_wb_mem_adr = i_wb_cpu_adr;
+ assign o_wb_mem_dat = i_wb_cpu_dat;
+ assign o_wb_mem_sel = i_wb_cpu_sel;
+ assign o_wb_mem_we = i_wb_cpu_we;
+ assign o_wb_mem_stb = i_wb_cpu_stb & !ext;
+
+ assign o_wb_ext_adr = i_wb_cpu_adr;
+ assign o_wb_ext_dat = i_wb_cpu_dat;
+ assign o_wb_ext_sel = i_wb_cpu_sel;
+ assign o_wb_ext_we = i_wb_cpu_we;
+ assign o_wb_ext_stb = i_wb_cpu_stb & ext;
+
+endmodule
diff --git a/pythondata_cpu_serv/verilog/serving/serving_ram.v b/pythondata_cpu_serv/verilog/serving/serving_ram.v
new file mode 100644
index 0000000..b58c224
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/serving/serving_ram.v
@@ -0,0 +1,83 @@
+/* serving_ram.v : Shared RF I/D SRAM for the serving SoC
+ *
+ * ISC License
+ *
+ * Copyright (C) 2020 Olof Kindgren
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+`default_nettype none
+module serving_ram
+ #(//Memory parameters
+ parameter depth = 256,
+ parameter aw = $clog2(depth),
+ parameter memfile = "")
+ (input wire i_clk,
+ input wire [aw-1:0] i_waddr,
+ input wire [7:0] i_wdata,
+ input wire i_wen,
+ input wire [aw-1:0] i_raddr,
+ output wire [7:0] o_rdata,
+
+ input wire [aw-1:2] i_wb_adr,
+ input wire [31:0] i_wb_dat,
+ input wire [3:0] i_wb_sel,
+ input wire i_wb_we,
+ input wire i_wb_stb,
+ output wire [31:0] o_wb_rdt,
+ output reg o_wb_ack);
+
+ wire wb_en = i_wb_stb & !i_wen & !o_wb_ack;
+
+ wire wb_we = i_wb_we & i_wb_sel[bsel];
+
+ wire we = wb_en ? wb_we : i_wen;
+
+ reg [7:0] mem [0:depth-1] /* verilator public */;
+
+ wire [aw-1:0] waddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_waddr;
+ wire [7:0] wdata = wb_en ? i_wb_dat[bsel*8+:8] : i_wdata;
+ wire [aw-1:0] raddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_raddr;
+
+ reg [2:0] wb_en_r;
+
+ reg [1:0] bsel;
+
+ reg [23:0] wb_rdt;
+ assign o_wb_rdt = {rdata, wb_rdt};
+
+ always @(posedge i_clk) begin
+ if (wb_en) bsel <= bsel + 2'd1;
+ wb_en_r <= {wb_en_r[1:0], wb_en};
+ o_wb_ack <= wb_en & &bsel;
+ if (bsel == 2'b01) wb_rdt[7:0] <= rdata;
+ if (bsel == 2'b10) wb_rdt[15:8] <= rdata;
+ if (bsel == 2'b11) wb_rdt[23:16] <= rdata;
+ end
+
+ reg [7:0] rdata;
+
+ always @(posedge i_clk) begin
+ if (we) mem[waddr] <= wdata;
+ rdata <= mem[raddr];
+ end
+
+ initial
+ if(|memfile) begin
+ $display("Preloading %m from %s", memfile);
+ $readmemh(memfile, mem);
+ end
+
+ assign o_rdata = rdata;
+endmodule
diff --git a/pythondata_cpu_serv/verilog/sw/Makefile b/pythondata_cpu_serv/verilog/sw/Makefile
new file mode 100644
index 0000000..1133f0c
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/sw/Makefile
@@ -0,0 +1,9 @@
+%.elf: %.S link.ld
+ riscv64-unknown-elf-gcc -nostartfiles -march=rv32i -mabi=ilp32 -Tlink.ld -o$@ $<
+%.bin: %.elf
+ riscv64-unknown-elf-objcopy -O binary $< $@
+%.hex: %.bin
+ python3 makehex.py $< 2048 > $@
+
+clean:
+ rm -f *.elf *.bin *.hex
diff --git a/pythondata_cpu_serv/verilog/sw/blinky.S b/pythondata_cpu_serv/verilog/sw/blinky.S
new file mode 100644
index 0000000..80bc620
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/sw/blinky.S
@@ -0,0 +1,46 @@
+/*
+* LED Blinker
+* Assuming that GPIO_BASE is mapped to a GPIO core, which in turn is
+* connected to LEDs, this will light the LEDs one at a time.
+* Useful as smoke test to see that serv is running correctly
+*/
+#ifndef GPIO_BASE
+#define GPIO_BASE 0x40000000
+#endif
+
+#ifndef DELAY
+#define DELAY 0x100000 /* Loop 100000 times before inverting the LED */
+#endif
+
+ /*
+ a0 = GPIO Base address
+ t0 = Value
+ t1 = Timer max value
+ t2 = Current timer value
+
+ */
+
+.globl _start
+_start:
+ /* Load GPIO base address to a0 */
+ lui a0, %hi(GPIO_BASE)
+ addi a0, a0, %lo(GPIO_BASE)
+
+ /* Set timer value to control blink speed */
+ li t1, DELAY
+
+bl1:
+ /* Write to LEDs */
+ sb t0, 0(a0)
+
+ /* invert LED */
+ xori t0, t0, 1
+
+ /* Reset timer */
+ and t2, zero, zero
+
+ /* Delay loop */
+time1:
+ addi t2, t2, 1
+ bne t1, t2, time1
+ j bl1
diff --git a/pythondata_cpu_serv/verilog/sw/blinky.hex b/pythondata_cpu_serv/verilog/sw/blinky.hex
new file mode 100644
index 0000000..b9847be
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/sw/blinky.hex
@@ -0,0 +1,2048 @@
+40000537
+00050513
+00100337
+00550023
+0012c293
+000073b3
+00138393
+fe731ee3
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diff --git a/pythondata_cpu_serv/verilog/sw/link.ld b/pythondata_cpu_serv/verilog/sw/link.ld
new file mode 100644
index 0000000..3398348
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/sw/link.ld
@@ -0,0 +1,10 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+SECTIONS
+{
+ . = 0x00000000;
+ .text : { *(.text) }
+ .data : { *(.data) }
+ .bss : { *(.bss) }
+}
diff --git a/pythondata_cpu_serv/verilog/sw/makehex.py b/pythondata_cpu_serv/verilog/sw/makehex.py
new file mode 100644
index 0000000..419b378
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/sw/makehex.py
@@ -0,0 +1,27 @@
+#!/usr/bin/env python3
+#
+# This is free and unencumbered software released into the public domain.
+#
+# Anyone is free to copy, modify, publish, use, compile, sell, or
+# distribute this software, either in source code form or as a compiled
+# binary, for any purpose, commercial or non-commercial, and by any
+# means.
+
+from sys import argv
+
+binfile = argv[1]
+nwords = int(argv[2])
+
+with open(binfile, "rb") as f:
+ bindata = f.read()
+
+assert len(bindata) < 4*nwords
+assert len(bindata) % 4 == 0
+
+for i in range(nwords):
+ if i < len(bindata) // 4:
+ w = bindata[4*i : 4*i+4]
+ print("%02x%02x%02x%02x" % (w[3], w[2], w[1], w[0]))
+ else:
+ print("0")
+
diff --git a/pythondata_cpu_serv/verilog/sw/zephyr_hello.hex b/pythondata_cpu_serv/verilog/sw/zephyr_hello.hex
new file mode 100644
index 0000000..10f929b
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/sw/zephyr_hello.hex
@@ -0,0 +1,2048 @@
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diff --git a/pythondata_cpu_serv/verilog/sw/zephyr_hello_mt.hex b/pythondata_cpu_serv/verilog/sw/zephyr_hello_mt.hex
new file mode 100644
index 0000000..f40034e
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/sw/zephyr_hello_mt.hex
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diff --git a/pythondata_cpu_serv/verilog/sw/zephyr_phil.hex b/pythondata_cpu_serv/verilog/sw/zephyr_phil.hex
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index 0000000..eab86ee
--- /dev/null
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diff --git a/pythondata_cpu_serv/verilog/sw/zephyr_sync.hex b/pythondata_cpu_serv/verilog/sw/zephyr_sync.hex
new file mode 100644
index 0000000..604178b
--- /dev/null
+++ b/pythondata_cpu_serv/verilog/sw/zephyr_sync.hex
@@ -0,0 +1,4096 @@
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diff --git a/pythondata_cpu_serv/verilog/zephyr b/pythondata_cpu_serv/verilog/zephyr
new file mode 160000
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+Subproject commit a690d52fa69f812924aa38f20c45f707c64fa16f