From 446a426436c0b7e457992981d3a1f2b4fda19992 Mon Sep 17 00:00:00 2001 From: Antonio Frighetto Date: Tue, 7 Jan 2025 09:38:44 +0100 Subject: [PATCH] [ARM] Record store with pre/post-indexed addressing as `mayStore` A miscompilation issue observed during machine sinking has been addressed with improved handling. Fixes: https://github.com/llvm/llvm-project/issues/121299. --- llvm/lib/Target/ARM/ARMInstrInfo.td | 3 ++- llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir | 7 +++---- .../tools/llvm-mca/ARM/cortex-a57-memory-instructions.s | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index c67177cd5a6fea..009b60c8400f02 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -3320,7 +3320,7 @@ def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), } - +let mayStore = 1, hasSideEffects = 0 in { def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, StMiscFrm, IIC_iStore_bh_ru, @@ -3352,6 +3352,7 @@ def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), let Inst{3-0} = offset{3-0}; // imm3_0/Rm let DecoderMethod = "DecodeAddrMode3Instruction"; } +} // mayStore = 1, hasSideEffects = 0 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), diff --git a/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir b/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir index e6e7a56d555d6c..92c983e2bfd1da 100644 --- a/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir +++ b/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir @@ -7,17 +7,16 @@ stack: - { id: 0, type: default, size: 8, alignment: 8 } body: | bb.0: - ; FIXME: This is a miscompilation. ; CHECK-LABEL: name: sink-store-load-dep ; CHECK: bb.0: ; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 %stack.0, 0, 14 /* CC::al */, $noreg :: (load (s32)) ; CHECK-NEXT: [[MOVi:%[0-9]+]]:gpr = MOVi 55296, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: [[ADDri1:%[0-9]+]]:gpr = ADDri [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: [[LDRH:%[0-9]+]]:gpr = LDRH killed [[ADDri1:%[0-9]+]], $noreg, 0, 14 /* CC::al */, $noreg :: (load (s16)) ; CHECK-NEXT: [[MOVi1:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: early-clobber %5:gpr = STRH_PRE [[MOVi:%[0-9]+]], [[LDRi12_:%[0-9]+]], [[MOVi1:%[0-9]+]], 0, 14 /* CC::al */, $noreg - ; CHECK-NEXT: [[SUBri:%.*]]:gpr = SUBri [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: [[SUBri:%.*]]:gpr = SUBri killed [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: bb.2: - ; CHECK-NEXT: [[ADDri1:%[0-9]+]]:gpr = ADDri [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg - ; CHECK-NEXT: [[LDRH:%[0-9]+]]:gpr = LDRH [[ADDri1:%[0-9]+]], $noreg, 0, 14 /* CC::al */, $noreg :: (load (s16)) ; CHECK-NEXT: [[MOVi2:%[0-9]+]]:gpr = MOVi [[LDRH:%[0-9]+]], 14 /* CC::al */, $noreg, $noreg %0:gpr = LDRi12 %stack.0, 0, 14, $noreg :: (load (s32)) %1:gpr = MOVi 55296, 14, $noreg, $noreg diff --git a/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s b/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s index 04c95f62fbe15c..36a2f04f4ace04 100644 --- a/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s +++ b/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s @@ -325,11 +325,11 @@ # CHECK-NEXT: 2 1 1.00 * strd r4, r5, [r12], -r10 # CHECK-NEXT: 1 1 1.00 * strh r3, [r4] # CHECK-NEXT: 1 1 1.00 * strh r2, [r7, #4] -# CHECK-NEXT: 2 1 1.00 U strh r1, [r8, #64]! +# CHECK-NEXT: 2 1 1.00 * strh r1, [r8, #64]! # CHECK-NEXT: 2 1 1.00 * strh r12, [sp], #4 # CHECK-NEXT: 1 1 1.00 * strh r6, [r5, r4] -# CHECK-NEXT: 2 1 1.00 U strh r3, [r8, r11]! -# CHECK-NEXT: 2 1 1.00 U strh r1, [r2, -r1]! +# CHECK-NEXT: 2 1 1.00 * strh r3, [r8, r11]! +# CHECK-NEXT: 2 1 1.00 * strh r1, [r2, -r1]! # CHECK-NEXT: 2 1 1.00 * strh r9, [r7], r2 # CHECK-NEXT: 2 1 1.00 * strh r4, [r3], -r2 # CHECK-NEXT: 2 1 1.00 U strht r2, [r5], #76