[bug] Incorrect bit vector range selection

[likeamahoney]

Hi all!

It was founded that the recently added automatic functions here and here (which are an autogenerated files produced by that script) had an incorrect bit range selections. Packages for all another targets (for example darjeeling and englishbreakfast) have the same issue.

The point is that logic type variable rsvd has a type width equal to 5 or 9 bits (Thus, bits 11 through 8 can never be extracted from it, and bits 8 through 0 can be extracted half the time) which follows from this and depends on top_pkg::TL_AUW parameter value (which target depends and can have a 23 or 27 value from here and here).

[rswarbrick]

@Razer6: Could you take a look at this?

[Razer6]

Yep, aware of it. I'll fix that soon. In general, the plan is to add the bit definitions for the role and CTN UID as part of the RACL config and then generate slicing functions out of that config.