From c9b815437bd9aff21e9dadc9f0ff9138ef3cb51f Mon Sep 17 00:00:00 2001 From: Maciej Gabryelski Date: Fri, 21 Oct 2022 09:24:13 +0200 Subject: [PATCH] State diagram for LPC Host and Peripheral added Signed-off-by: Maciej Gabryelski --- docs/FSM_state_diagrams_LPC.md | 81 ++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 docs/FSM_state_diagrams_LPC.md diff --git a/docs/FSM_state_diagrams_LPC.md b/docs/FSM_state_diagrams_LPC.md new file mode 100644 index 0000000..d62cc9d --- /dev/null +++ b/docs/FSM_state_diagrams_LPC.md @@ -0,0 +1,81 @@ +# Finite state machines for LPC peripheral and host + +### LPC Peripheral FSM state diagram: + +```mermaid +stateDiagram-v2 + [*] --> LPC_ST_IDLE + LPC_ST_IDLE --> LPC_ST_IDLE + LPC_ST_IDLE --> LPC_ST_START + LPC_ST_START --> LPC_ST_START + LPC_ST_START --> LPC_ST_CYCTYPE_RD + LPC_ST_START --> LPC_ST_CYCTYPE_WR + LPC_ST_CYCTYPE_RD --> LPC_ST_ADDR_RD_CLK1 + LPC_ST_CYCTYPE_WR --> LPC_ST_ADDR_WR_CLK1 + LPC_ST_ADDR_WR_CLK1 --> LPC_ST_ADDR_WR_CLK2 + LPC_ST_ADDR_WR_CLK2 --> LPC_ST_ADDR_WR_CLK3 + LPC_ST_ADDR_WR_CLK3 --> LPC_ST_ADDR_WR_CLK4 + LPC_ST_ADDR_WR_CLK4 --> LPC_ST_DATA_WR_CLK1 + LPC_ST_DATA_WR_CLK1 --> LPC_ST_DATA_WR_CLK2 + LPC_ST_DATA_WR_CLK2 --> LPC_ST_TAR_WR_CLK1 + LPC_ST_TAR_WR_CLK1 --> LPC_ST_TAR_WR_CLK2 + LPC_ST_TAR_WR_CLK2 --> LPC_ST_CYCTYPE_WR + LPC_ST_TAR_WR_CLK2 --> LPC_ST_SYNC_WR + LPC_ST_SYNC_WR --> LPC_ST_FINAL_TAR_CLK1 + + LPC_ST_ADDR_RD_CLK1 --> LPC_ST_ADDR_RD_CLK2 + LPC_ST_ADDR_RD_CLK2 --> LPC_ST_ADDR_RD_CLK3 + LPC_ST_ADDR_RD_CLK3 --> LPC_ST_ADDR_RD_CLK4 + LPC_ST_ADDR_RD_CLK4 --> LPC_ST_TAR_RD_CLK1 + LPC_ST_TAR_RD_CLK1 --> LPC_ST_TAR_RD_CLK2 + LPC_ST_TAR_RD_CLK2 --> LPC_ST_IDLE + LPC_ST_TAR_RD_CLK2 --> LPC_ST_SYNC_RD + LPC_ST_SYNC_RD --> LPC_ST_DATA_RD_CLK1 + LPC_ST_DATA_RD_CLK1 --> LPC_ST_DATA_RD_CLK2 + LPC_ST_DATA_RD_CLK2 --> LPC_ST_CYCTYPE_WR + LPC_ST_DATA_RD_CLK2 --> LPC_ST_FINAL_TAR_CLK1 + LPC_ST_FINAL_TAR_CLK1 --> LPC_ST_FINAL_TAR_CLK2 + LPC_ST_FINAL_TAR_CLK2 --> LPC_ST_IDLE +``` +### LPC Host FSM state diagram: + +```mermaid +stateDiagram-v2 + [*] --> LPC_ST_FORCE_RESET + LPC_ST_FORCE_RESET --> LPC_ST_IDLE + LPC_ST_IDLE --> LPC_ST_START + LPC_ST_START --> LPC_ST_CYCTYPE_TPM_RD + LPC_ST_START --> LPC_ST_CYCTYPE_TPM_WR + LPC_ST_START --> LPC_ST_CYCTYPE_MEMORY_TPM_RD + LPC_ST_START --> LPC_ST_CYCTYPE_MEMORY_TPM_WR + + LPC_ST_CYCTYPE_TPM_RD --> LPC_ST_ADDR_TPM_RD_CLK1 + LPC_ST_ADDR_TPM_RD_CLK1 --> LPC_ST_ADDR_TPM_RD_CLK2 + LPC_ST_ADDR_TPM_RD_CLK2 --> LPC_ST_ADDR_TPM_RD_CLK3 + LPC_ST_ADDR_TPM_RD_CLK3 --> LPC_ST_ADDR_TPM_RD_CLK4 + LPC_ST_ADDR_TPM_RD_CLK4 --> LPC_ST_TAR_TPM_RD_CLK1 + LPC_ST_TAR_TPM_RD_CLK1 --> LPC_ST_TAR_TPM_RD_CLK2 + LPC_ST_TAR_TPM_RD_CLK2 --> LPC_ST_SYNC_TPM_RD + LPC_ST_SYNC_TPM_RD --> LPC_ST_DATA_TPM_RD_CLK1 + LPC_ST_SYNC_TPM_RD --> LPC_ST_FORCE_RESET + LPC_ST_DATA_TPM_RD_CLK1 --> LPC_ST_DATA_TPM_RD_CLK2 + LPC_ST_DATA_TPM_RD_CLK2 --> `LPC_ST_FINAL_TAR_CLK1 + + LPC_ST_CYCTYPE_TPM_WR --> LPC_ST_ADDR_TPM_WR_CLK1 + LPC_ST_CYCTYPE_MEMORY_TPM_WR --> LPC_ST_ADDR_TPM_WR_CLK1 + LPC_ST_ADDR_TPM_WR_CLK1 --> LPC_ST_ADDR_TPM_WR_CLK2 + LPC_ST_ADDR_TPM_WR_CLK2 --> LPC_ST_ADDR_TPM_WR_CLK3 + LPC_ST_ADDR_TPM_WR_CLK3 --> LPC_ST_ADDR_TPM_WR_CLK4 + LPC_ST_ADDR_TPM_WR_CLK4 --> LPC_ST_DATA_TPM_WR_CLK1 + LPC_ST_DATA_TPM_WR_CLK1 --> LPC_ST_DATA_TPM_WR_CLK2 + LPC_ST_DATA_TPM_WR_CLK2 --> LPC_ST_TAR_TPM_WR_CLK1 + LPC_ST_TAR_TPM_WR_CLK1 --> LPC_ST_TAR_TPM_WR_CLK2 + LPC_ST_TAR_TPM_WR_CLK2 --> LPC_ST_SYNC_TPM_WR + LPC_ST_SYNC_TPM_WR --> LPC_ST_FINAL_TAR_CLK1 + LPC_ST_SYNC_TPM_WR --> LPC_ST_FORCE_RESET + + LPC_ST_FINAL_TAR_CLK1 --> LPC_ST_FORCE_RESET + LPC_ST_FINAL_TAR_CLK1 --> LPC_ST_FINAL_TAR_CLK2 + LPC_ST_FINAL_TAR_CLK2 --> LPC_ST_FORCE_RESET +``` +