From 7b4ec65fe2991ea1720bd14df086ec766ec0ed2e Mon Sep 17 00:00:00 2001 From: Maciej Gabryelski Date: Mon, 31 Oct 2022 12:32:20 +0100 Subject: [PATCH 1/3] docs/SoC_Gowin_GW1NSR.md: document describing Gowin SoC tests added Signed-off-by: Maciej Gabryelski --- docs/SoC_Gowin_GW1NSR.md | 80 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 docs/SoC_Gowin_GW1NSR.md diff --git a/docs/SoC_Gowin_GW1NSR.md b/docs/SoC_Gowin_GW1NSR.md new file mode 100644 index 0000000..1cce27d --- /dev/null +++ b/docs/SoC_Gowin_GW1NSR.md @@ -0,0 +1,80 @@ +# Testing the suitability of the SoC GW1NSR-4C for the construction of a hardware TPM module + +Some time ago "Gowin Semiconductor" released a series of SoC chips (combination +of hardware ARM Cortex-M3 MCU with FPGA chip) GW1NSR-4C. + +In a small QN48P housing there is a 32-bit ARM Cortex-M3 MCU clocked up to 80 MHz +and an FPGA chip containing, among others, about 5K LUTs and 3.5K Flip-flops. +These two systems are connected by a fast AHB bus. Here is link to datasheet for +this series of SoC: [GW1NSR series of FPGAs](https://www.gowinsemi.com/upload/database_doc/47/document/5c36e77302539.pdf?_file=database_doc%2F47%2Fdocument%2F5c36e77302539.pdf) + +## The purpose of the study + +The purpose of the test is to determine whether the chip from this series can be +used to implement a hardware TPM module. + +## Requirements that must be met by a system that is intended to be a platform for the hardware TPM + +As previously stated (and described), a TPM candidate must meet the following +requirements: + ++ sufficiently efficient CPU (hardware or softcore) ++ sufficiently large RAM memory (minimum 256KB) ++ must have programmable circuit (FPGA) allowing the implementation of the LPC + protocol driver ++ must have a high-speed bus connecting programmable logic to the CPU ++ it must have an efficient interrupt handler ++ it should have a DMA module that allows for transmissions between RAM from CPU + with BRAM memory from FPGA ++ they have the necessary peripheral systems, such as the hardware SPI and I2C controller + +## Conformity of the SoC GW1NSR-4C with the described requirements + +The SoCs of the GW1NSR-4C series meet most of the above-described requirements +for the hardware TPM module - hey have efficient CPU and needed peripherals. The +programmable circuitry (FPGA) has sufficient resources and is connected to the CPU +by a high-speed bus. The only problem that can be noticed is the very low amount +of RAM for the CPU - 16KB. The RAM memory for the CPU is made up of internal BRAM +blocks in the programmable circuit. + +Fortunately, the SoC systems from the described series have built-in PSRAM or +HyperRAM memory modules with a capacity of 64 Mbit (8 MB). Both types of memory +are pseudo-static memories - internally they are DRAM memories, but refreshing +is done internally. Unfortunately, it seems that these memories do not have a +hardware driver in the CPU, to use them you need to implement a driver (in Verilog) +in the FPGA part, there is also an IP core provided by `Gowin Semiconductors` [Gowin HyperRAM Memory Interface](https://www.gowinsemi.com/en/support/ip_detail/57/) + +## Test on the FPGA set of the correct operation of the `HyperRAM` memory + +We chose the 'Tang Nano 4K' FPGA board for hardware testing: [Tang Nano 4K](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-4K/Nano-4K.html) This board is based on the `GW1N-LV4CQN48PC7/16` chip. +We created a project in `Gowin EDA` ([Gowin EDA](https://www.gowinsemi.com/en/support/home/)) +with an implementation (Verilog) of the `HyperRAM` memory driver for this chip +based on Gowin IP Core. We also wrote a test routine that writes data to the +`HyperRAM` memory and checks the data read from the memory and in case of errors +it lights the LED from the FPGA board. This test is included in the source file +`hpram_test.v` end port named `error` is connected to the LED. Here is source code +of this project: [Github HyperRAM test](https://github.com/3mdeb/fpga-tests/tree/hyperram_test_gowin) +This test on the `Tang Nano 4K` FPGA kit was completed without errors. + +## Possibility to use the `HyperRAM` memory as the main RAM for the ARM Cortex-M3 hard CPU + +Since there is no hardware HyperRAM memory driver and a software driver (Verilog code) +in FPGA part is required, it is not possible to use this memory as RAM for the +hard CPU. This fact disqualifies Gowin's SoC from the GW1NSR-4C series as a +hardware `TPM` module. + +## Open source tools for the synthesis of FPGAs by `Gowin Semiconductors` + +There is project [YosysHQ/apicula](https://github.com/YosysHQ/apicula) with open +source tools for synthesis of `Gowin` FPGAs. Installation and use of these tools +is described on the project page. + +The project documentation shows that, among others: ++ BRAM blocks in FPGA fabric are not properly handled ++ PLL clocks are not supported + +## The final decision on the possibility of using the `Gowin` SoC as a hardware TPM module + +Due to the inability to connect a sufficiently large RAM memory to the CPU and +the open source tools not supporting the necessary FPGA blocks - Gowin's SoC +systems are not suitable for a hardware module for the implementation of `TPM` From c52f6a8bca9e7944deb208eab1e922856623ae71 Mon Sep 17 00:00:00 2001 From: Artur Kowalski Date: Fri, 18 Nov 2022 12:50:40 +0100 Subject: [PATCH 2/3] SoC_Gowin_GW1NSR.md: fixes --- docs/SoC_Gowin_GW1NSR.md | 78 ++++++++++++++++++++++------------------ 1 file changed, 44 insertions(+), 34 deletions(-) diff --git a/docs/SoC_Gowin_GW1NSR.md b/docs/SoC_Gowin_GW1NSR.md index 1cce27d..3379c23 100644 --- a/docs/SoC_Gowin_GW1NSR.md +++ b/docs/SoC_Gowin_GW1NSR.md @@ -1,19 +1,21 @@ -# Testing the suitability of the SoC GW1NSR-4C for the construction of a hardware TPM module +# Using Gowin GW1NSR-4C for the construction of a hardware TPM module Some time ago "Gowin Semiconductor" released a series of SoC chips (combination of hardware ARM Cortex-M3 MCU with FPGA chip) GW1NSR-4C. In a small QN48P housing there is a 32-bit ARM Cortex-M3 MCU clocked up to 80 MHz and an FPGA chip containing, among others, about 5K LUTs and 3.5K Flip-flops. -These two systems are connected by a fast AHB bus. Here is link to datasheet for -this series of SoC: [GW1NSR series of FPGAs](https://www.gowinsemi.com/upload/database_doc/47/document/5c36e77302539.pdf?_file=database_doc%2F47%2Fdocument%2F5c36e77302539.pdf) +These two systems are connected by a fast AHB bus. + +Datasheet for these SoCs is available +[here](https://www.gowinsemi.com/upload/database_doc/47/document/5c36e77302539.pdf?_file=database_doc%2F47%2Fdocument%2F5c36e77302539.pdf) ## The purpose of the study The purpose of the test is to determine whether the chip from this series can be used to implement a hardware TPM module. -## Requirements that must be met by a system that is intended to be a platform for the hardware TPM +## SoC requirements for TPM As previously stated (and described), a TPM candidate must meet the following requirements: @@ -26,55 +28,63 @@ requirements: + it must have an efficient interrupt handler + it should have a DMA module that allows for transmissions between RAM from CPU with BRAM memory from FPGA -+ they have the necessary peripheral systems, such as the hardware SPI and I2C controller ++ they have the necessary peripheral systems, such as the hardware SPI and I2C + controller -## Conformity of the SoC GW1NSR-4C with the described requirements +## Requirements conformity -The SoCs of the GW1NSR-4C series meet most of the above-described requirements -for the hardware TPM module - hey have efficient CPU and needed peripherals. The -programmable circuitry (FPGA) has sufficient resources and is connected to the CPU -by a high-speed bus. The only problem that can be noticed is the very low amount -of RAM for the CPU - 16KB. The RAM memory for the CPU is made up of internal BRAM -blocks in the programmable circuit. +The GW1NSR-4C series meet most of the above-described requirements for the +hardware TPM module - they have an efficient CPU and needed peripherals. The +programmable circuitry (FPGA) has sufficient resources and is connected to the +CPU by a high-speed bus. The only problem that can be noticed is the very low +amount of RAM for the CPU - 16KB. The RAM memory for the CPU is made up of +internal BRAM blocks in the programmable circuit. Fortunately, the SoC systems from the described series have built-in PSRAM or HyperRAM memory modules with a capacity of 64 Mbit (8 MB). Both types of memory are pseudo-static memories - internally they are DRAM memories, but refreshing is done internally. Unfortunately, it seems that these memories do not have a hardware driver in the CPU, to use them you need to implement a driver (in Verilog) -in the FPGA part, there is also an IP core provided by `Gowin Semiconductors` [Gowin HyperRAM Memory Interface](https://www.gowinsemi.com/en/support/ip_detail/57/) +in the FPGA part. There is also an IP core provided by Gowin itself +([Gowin HyperRAM Memory Interface](https://www.gowinsemi.com/en/support/ip_detail/57/)) + +## HyperRAM test + +We choose the [Tang Nano 4K](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-4K/Nano-4K.html) +board for hardware testing. This board is based on the +`GW1N-LV4CQN48PC7/16` chip. We created a project in +[Gowin EDA](https://www.gowinsemi.com/en/support/home/) with an implementation +(Verilog) of the HyperRAM memory driver based on Gowin IP Core. -## Test on the FPGA set of the correct operation of the `HyperRAM` memory +We also wrote a test routine that writes data to the HyperRAM memory and checks +the data read from the memory and in case of errors it lights a LED on the +board. This test is included in the source file `hpram_test.v` end port named +`error` is connected to the LED. Source code is availble +[here](https://github.com/3mdeb/fpga-tests/tree/master/HyperRAM_Test_Gowin). -We chose the 'Tang Nano 4K' FPGA board for hardware testing: [Tang Nano 4K](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-4K/Nano-4K.html) This board is based on the `GW1N-LV4CQN48PC7/16` chip. -We created a project in `Gowin EDA` ([Gowin EDA](https://www.gowinsemi.com/en/support/home/)) -with an implementation (Verilog) of the `HyperRAM` memory driver for this chip -based on Gowin IP Core. We also wrote a test routine that writes data to the -`HyperRAM` memory and checks the data read from the memory and in case of errors -it lights the LED from the FPGA board. This test is included in the source file -`hpram_test.v` end port named `error` is connected to the LED. Here is source code -of this project: [Github HyperRAM test](https://github.com/3mdeb/fpga-tests/tree/hyperram_test_gowin) -This test on the `Tang Nano 4K` FPGA kit was completed without errors. +This test on Tang Nano 4K was completed without errors. -## Possibility to use the `HyperRAM` memory as the main RAM for the ARM Cortex-M3 hard CPU +## Using HyperRAM as the main memory -Since there is no hardware HyperRAM memory driver and a software driver (Verilog code) -in FPGA part is required, it is not possible to use this memory as RAM for the -hard CPU. This fact disqualifies Gowin's SoC from the GW1NSR-4C series as a -hardware `TPM` module. +Since there is no hardware HyperRAM memory driver and a software driver in FPGA +part is required, it is not possible to use this memory as RAM for the hard CPU. -## Open source tools for the synthesis of FPGAs by `Gowin Semiconductors` +This fact disqualifies Gowin's SoC from the GW1NSR-4C series as a hardware TPM +module. + +## Open source tools for FPGA synthesis There is project [YosysHQ/apicula](https://github.com/YosysHQ/apicula) with open -source tools for synthesis of `Gowin` FPGAs. Installation and use of these tools +source tools for synthesis of Gowin FPGAs. Installation and use of these tools is described on the project page. The project documentation shows that, among others: + + BRAM blocks in FPGA fabric are not properly handled + PLL clocks are not supported -## The final decision on the possibility of using the `Gowin` SoC as a hardware TPM module +## The decision -Due to the inability to connect a sufficiently large RAM memory to the CPU and -the open source tools not supporting the necessary FPGA blocks - Gowin's SoC -systems are not suitable for a hardware module for the implementation of `TPM` +Due to the inability to connect a sufficiently large RAM memory to the CPU and +the open source tools not supporting the necessary FPGA blocks - Gowin's SoC +systems are not suitable for a hardware module for the implementation of TPM. From b0a63171083586a169067b330612fdcdbfde99fa Mon Sep 17 00:00:00 2001 From: Artur Kowalski Date: Fri, 18 Nov 2022 12:51:01 +0100 Subject: [PATCH 3/3] SoC_Gowin_GW1NSR.md: add to mkdocs.yml --- mkdocs.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/mkdocs.yml b/mkdocs.yml index ea5ae6e..791d238 100644 --- a/mkdocs.yml +++ b/mkdocs.yml @@ -37,3 +37,4 @@ nav: - 'SPI interface - implementation': tpm-spi-dev.md - 'SPI communication dump': tpm-spi-dump.md - 'LPC driver - implementation': TPM_with_LPC_protocol.md + - 'Gowin GW1NSR': SoC_Gowin_GW1NSR.md