diff --git a/conf/machine/coral-dev.conf b/conf/machine/coral-dev.conf index e7ad7cb..57e0d9c 100644 --- a/conf/machine/coral-dev.conf +++ b/conf/machine/coral-dev.conf @@ -4,7 +4,7 @@ #@DESCRIPTION: Machine configuration for Google Coral Dev Board #@MAINTAINER: Mirza Krak -MACHINEOVERRIDES =. "mx8mq:" +MACHINEOVERRIDES =. "mx8mq:use-nxp-bsp:" require conf/machine/include/imx-base.inc require conf/machine/include/arm/armv8a/tune-cortexa53.inc @@ -16,6 +16,7 @@ DEFAULTTUNE:use-mainline-bsp = "cortexa53-crypto" PREFERRED_PROVIDER_virtual/kernel:use-mainline-bsp = "linux-fslc" PREFERRED_PROVIDER_virtual/kernel:use-nxp-bsp = "linux-coral" +KBUILD_DEFCONFIG = "imx_v8_defconfig" MACHINE_FEATURES += "pci wifi bluetooth bcm43455 bcm4356" MACHINE_FEATURES:append:use-nxp-bsp = " optee bcm4359" @@ -23,11 +24,12 @@ MACHINE_FEATURES:append:use-nxp-bsp = " optee bcm4359" MACHINE_EXTRA_RDEPENDS += "\ kernel-modules \ libedgetpu \ + linux-firmware-ath10k \ " MACHINE_SOCARCH_FILTER:append:mx8mq = " virtual/libopenvg virtual/libgles1 virtual/libgles2 virtual/egl virtual/mesa virtual/libgl virtual/libg2d" -KERNEL_DEVICETREE:use-nxp-bsp = "freescale/fsl-imx8mq-phanbell.dtb" +KERNEL_DEVICETREE:use-nxp-bsp = "freescale/imx8mq-phanbell.dtb" KERNEL_DEVICETREE:use-mainline-bsp = "freescale/imx8mq-phanbell.dtb" IMX_DEFAULT_BOOTLOADER = "u-boot-coral" diff --git a/recipes-kernel/linux/files/defconfig b/recipes-kernel/linux/files/defconfig new file mode 100644 index 0000000..9c3d9ea --- /dev/null +++ b/recipes-kernel/linux/files/defconfig @@ -0,0 +1,828 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_ALPINE=y +CONFIG_ARCH_BCM2835=y +CONFIG_ARCH_BCM_IPROC=y +CONFIG_ARCH_BERLIN=y +CONFIG_ARCH_BRCMSTB=y +CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_LAYERSCAPE=y +CONFIG_ARCH_LG1K=y +CONFIG_ARCH_HISI=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MESON=y +CONFIG_ARCH_MVEBU=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ARCH_SEATTLE=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_R8A7795=y +CONFIG_ARCH_R8A7796=y +CONFIG_ARCH_STRATIX10=y +CONFIG_ARCH_TEGRA=y +CONFIG_ARCH_SPRD=y +CONFIG_ARCH_THUNDER=y +CONFIG_ARCH_THUNDER2=y +CONFIG_ARCH_UNIPHIER=y +CONFIG_ARCH_VEXPRESS=y +CONFIG_ARCH_XGENE=y +CONFIG_ARCH_ZX=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_ARCH_FSL_IMX8QM=y +CONFIG_ARCH_FSL_IMX8QP=y +CONFIG_ARCH_FSL_IMX8QXP=y +CONFIG_ARCH_FSL_IMX8MQ=y +CONFIG_ARCH_FSL_IMX8MM=y +CONFIG_PCI=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCI_IOV=y +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_ACPI=y +CONFIG_PCI_IMX6=y +CONFIG_PCI_HISI=y +CONFIG_PCIE_KIRIN=y +CONFIG_PCI_AARDVARK=y +CONFIG_PCIE_RCAR=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_XGENE=y +CONFIG_PCIE_ROCKCHIP=m +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_NUMA=y +CONFIG_PREEMPT=y +CONFIG_KSM=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_CMA=y +CONFIG_SECCOMP=y +CONFIG_KEXEC=y +CONFIG_CRASH_DUMP=y +CONFIG_XEN=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_COMPAT=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_ARM_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_BIG_LITTLE_CPUFREQ=y +CONFIG_ARM_IMX8_CPUFREQ=y +CONFIG_ARM_IMX8MQ_CPUFREQ=y +CONFIG_ARM_SCPI_CPUFREQ=y +CONFIG_ACPI_CPPC_CPUFREQ=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_IPV6_SIT=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_MANGLE=m +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC2=y +CONFIG_BPF_JIT=y +CONFIG_CAN=y +CONFIG_CAN_FLEXCAN=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +# CONFIG_BT_HS is not set +# CONFIG_BT_LE is not set +CONFIG_BT_LEDS=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIVHCI=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_INTERNAL_REGDB=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_MAC80211_LEDS=y +CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=320 +CONFIG_ARM_CCI400_PMU=y +CONFIG_ARM_CCI5xx_PMU=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAM=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SLRAM=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_FSL_FLEXSPI=y +CONFIG_MTD_UBI=y +CONFIG_OF_OVERLAY=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=m +CONFIG_XEN_BLKDEV_BACKEND=y +CONFIG_VIRTIO_BLK=y +CONFIG_BLK_DEV_NVME=m +CONFIG_SENSORS_FXOS8700=y +CONFIG_SENSORS_FXAS2100X=y +CONFIG_SRAM=y +CONFIG_EEPROM_AT25=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_HISI_SAS=y +CONFIG_SCSI_HISI_SAS_PCI=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_AHCI_CEVA=y +CONFIG_AHCI_MVEBU=y +CONFIG_AHCI_XGENE=y +CONFIG_AHCI_QORIQ=y +CONFIG_SATA_SIL24=y +CONFIG_SATA_RCAR=y +CONFIG_PATA_PLATFORM=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_TUN=y +CONFIG_VETH=m +CONFIG_VIRTIO_NET=y +CONFIG_AMD_XGBE=y +CONFIG_NET_XGENE=y +CONFIG_MACB=y +CONFIG_HNS_DSAF=y +CONFIG_HNS_ENET=y +CONFIG_E1000E=y +CONFIG_IGB=y +CONFIG_IGBVF=y +CONFIG_MVNETA=y +CONFIG_MVPP2=y +CONFIG_SKY2=y +CONFIG_QCOM_EMAC=m +CONFIG_RAVB=y +CONFIG_SMC91X=y +CONFIG_SMSC911X=y +CONFIG_STMMAC_ETH=m +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_AT803X_PHY=y +CONFIG_MARVELL_PHY=m +CONFIG_MESON_GXL_PHY=m +CONFIG_MICREL_PHY=y +CONFIG_NXP_TJA110X_PHY=y +CONFIG_REALTEK_PHY=m +CONFIG_ROCKCHIP_PHY=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +# CONFIG_WLAN_VENDOR_ATH is not set +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PCIE=y +CONFIG_HOSTAP=y +CONFIG_RTL_CARDS=m +# CONFIG_WLAN_VENDOR_TI is not set +CONFIG_XEN_NETDEV_BACKEND=m +CONFIG_IVSHMEM_NET=y +CONFIG_INPUT_POLLDEV=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_ADC=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX_SC_PWRKEY=y +CONFIG_KEYBOARD_CROS_EC=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_PM8941_PWRKEY=y +CONFIG_INPUT_HISI_POWERKEY=y +CONFIG_INPUT_MPL3115=y +CONFIG_INPUT_ISL29023=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_AMBAKMI=y +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_BCM2835AUX=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_UNIPHIER=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_MESON=y +CONFIG_SERIAL_MESON_CONSOLE=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_TEGRA=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=11 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_MVEBU_UART=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_BCM2835=m +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y +CONFIG_I2C_MESON=y +CONFIG_I2C_MV64XXX=y +CONFIG_I2C_PXA=y +CONFIG_I2C_QUP=y +CONFIG_I2C_RK3X=y +CONFIG_I2C_SH_MOBILE=y +CONFIG_I2C_TEGRA=y +CONFIG_I2C_UNIPHIER_F=y +CONFIG_I2C_RCAR=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_XEN_I2C_BACKEND=y +CONFIG_I2C_RPBUS=y +CONFIG_SPI=y +CONFIG_SPI_BCM2835=m +CONFIG_SPI_BCM2835AUX=m +CONFIG_SPI_FSL_LPSPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_MESON_SPICC=m +CONFIG_SPI_MESON_SPIFC=m +CONFIG_SPI_ORION=y +CONFIG_SPI_PL022=y +CONFIG_SPI_ROCKCHIP=y +CONFIG_SPI_QUP=y +CONFIG_SPI_S3C64XX=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y +CONFIG_SPMI=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_MAX77620=y +CONFIG_PINCTRL_IPQ8074=y +CONFIG_PINCTRL_MSM8916=y +CONFIG_PINCTRL_MSM8994=y +CONFIG_PINCTRL_MSM8996=y +CONFIG_PINCTRL_QDF2XXX=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_PL061=y +CONFIG_GPIO_RCAR=y +CONFIG_GPIO_XGENE=y +CONFIG_GPIO_XGENE_SB=y +CONFIG_GPIO_MAX732X=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_MAX77620=y +CONFIG_POWER_AVS=y +CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_BATTERY_BQ27XXX=y +CONFIG_SENSORS_ARM_SCPI=y +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_INA2XX=m +# CONFIG_MXC_MMA8451 is not set +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_IMX8M_THERMAL=y +CONFIG_IMX8MM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_ROCKCHIP_THERMAL=m +CONFIG_EXYNOS_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_S3C2410_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_IMX8_WDT=y +CONFIG_MESON_GXBB_WATCHDOG=m +CONFIG_MESON_WATCHDOG=m +CONFIG_RENESAS_WDT=y +CONFIG_UNIPHIER_WATCHDOG=y +CONFIG_BCM2835_WDT=y +CONFIG_MFD_AXP20X_RSB=y +CONFIG_MFD_CROS_EC=y +CONFIG_MFD_CROS_EC_I2C=y +CONFIG_MFD_CROS_EC_SPI=y +CONFIG_MFD_EXYNOS_LPASS=m +CONFIG_MFD_HI6421_PMIC=y +CONFIG_MFD_HI655X_PMIC=y +CONFIG_MFD_MAX77620=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_MFD_RK808=y +CONFIG_MFD_SEC_CORE=y +CONFIG_MFD_BD71837=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_HI6421V530=y +CONFIG_REGULATOR_HI655X=y +CONFIG_REGULATOR_MAX77620=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_QCOM_SMD_RPM=y +CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_RK808=y +CONFIG_REGULATOR_S2MPS11=y +CONFIG_REGULATOR_BD71837=y +CONFIG_RC_CORE=y +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_DVB_NET is not set +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_CAPTURE=y +CONFIG_VIDEO_MX8_CAPTURE=y +CONFIG_GMSL_MAX9286=y +CONFIG_VIDEO_MXC_CSI_CAMERA=y +CONFIG_MXC_MIPI_CSI=y +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m +CONFIG_VIDEO_SAMSUNG_S5P_MFC=m +CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m +CONFIG_VIDEO_RENESAS_FCP=m +CONFIG_VIDEO_RENESAS_VSP1=m +CONFIG_IMX_DPU_CORE=y +CONFIG_IMX_DCSS_CORE=y +CONFIG_IMX_LCDIF_CORE=y +CONFIG_DRM=y +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_EXYNOS=m +CONFIG_DRM_EXYNOS5433_DECON=y +CONFIG_DRM_EXYNOS7_DECON=y +CONFIG_DRM_EXYNOS_DSI=y +# CONFIG_DRM_EXYNOS_DP is not set +CONFIG_DRM_EXYNOS_HDMI=y +CONFIG_DRM_EXYNOS_MIC=y +CONFIG_DRM_ROCKCHIP=m +CONFIG_ROCKCHIP_ANALOGIX_DP=y +CONFIG_ROCKCHIP_CDN_DP=y +CONFIG_ROCKCHIP_DW_HDMI=y +CONFIG_ROCKCHIP_DW_MIPI_DSI=y +CONFIG_ROCKCHIP_INNO_HDMI=y +CONFIG_DRM_RCAR_DU=m +CONFIG_DRM_RCAR_LVDS=y +CONFIG_DRM_RCAR_VSP=y +CONFIG_DRM_MSM=m +CONFIG_DRM_TEGRA=m +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_PANEL_RAYDIUM_RM67191=y +CONFIG_DRM_NXP_SEIKO_43WVFIG=y +CONFIG_DRM_I2C_ADV7511=y +CONFIG_DRM_ITE_IT6263=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_NWL_DSI=y +CONFIG_DRM_IMX_SEC_DSIM=y +CONFIG_DRM_IMX_HDP=y +CONFIG_IMX_HDP_CEC=y +CONFIG_DRM_VC4=m +CONFIG_DRM_HISI_KIRIN=m +CONFIG_DRM_MXSFB=y +CONFIG_DRM_MESON=m +CONFIG_FB_IMX64=y +CONFIG_FB_IMX64_DEBUG=y +CONFIG_FB_ARMCLCD=y +CONFIG_FB_MXC_DISP_FRAMEWORK=y +CONFIG_BACKLIGHT_GENERIC=m +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_LP855X=m +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_BCM2835_SOC_I2S=m +CONFIG_SND_SOC_FSL_ACM=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_AK4458=y +CONFIG_SND_SOC_IMX_AK5558=y +CONFIG_SND_SOC_IMX_AK4497=y +CONFIG_SND_SOC_IMX_WM8960=y +CONFIG_SND_SOC_IMX_WM8524=y +CONFIG_SND_SOC_IMX_CS42888=y +CONFIG_SND_SOC_IMX_WM8962=y +CONFIG_SND_SOC_IMX_MICFIL=y +CONFIG_SND_SOC_IMX_RPMSG=y +CONFIG_SND_SOC_IMX_MQS=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_AMIX=y +CONFIG_SND_SOC_IMX_CDNHDMI=y +CONFIG_SND_SOC_IMX_DSP=y +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_SND_SOC_RCAR=y +CONFIG_SND_SOC_AK4613=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=y +CONFIG_USB=y +CONFIG_USB_OTG=y +CONFIG_USB_OTG_WHITELIST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_TEGRA=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MSM=y +CONFIG_USB_EHCI_EXYNOS=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_EXYNOS=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_HCD_TEST_MODE=y +CONFIG_USB_RENESAS_USBHS=m +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC2=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_ISP1760=y +CONFIG_USB_ISP1760_HOST_ROLE=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_HSIC_USB3503=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_GPIO_VBUS=y +CONFIG_USB_QCOM_8X16_PHY=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_RENESAS_USBHS_UDC=m +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_FSL_UTP=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_GADGET_UAC1=y +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_NCM=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ACPI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_MMC_SDHCI_OF_ESDHC=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MMC_SDHCI_TEGRA=y +CONFIG_MMC_MESON_GX=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_SPI=y +CONFIG_MMC_SDHI=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_EXYNOS=y +CONFIG_MMC_DW_K3=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SUNXI=y +CONFIG_MMC_BCM2835=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_MXC_MLB150=y +CONFIG_MXC_SIM=y +CONFIG_MXC_EMVSIM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_EDAC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MAX77686=y +CONFIG_RTC_DRV_RK808=m +CONFIG_RTC_DRV_S5M=y +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_S3C=y +CONFIG_RTC_DRV_PL031=y +CONFIG_RTC_DRV_TEGRA=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_IMX_SC=y +CONFIG_RTC_DRV_XGENE=y +CONFIG_DMADEVICES=y +CONFIG_DMA_BCM2835=m +CONFIG_FSL_EDMA_V3=y +CONFIG_IMX_SDMA=y +CONFIG_K3_DMA=y +CONFIG_MV_XOR_V2=y +CONFIG_MXS_DMA=y +CONFIG_PL330_DMA=y +CONFIG_TEGRA20_APB_DMA=y +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_HIDMA_MGMT=y +CONFIG_QCOM_HIDMA=y +CONFIG_RCAR_DMAC=y +CONFIG_UIO=y +CONFIG_UIO_PCI_GENERIC=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_MMIO=y +CONFIG_XEN_GNTDEV=y +CONFIG_XEN_GRANT_DEV_ALLOC=y +CONFIG_STAGING=y +CONFIG_ION=y +CONFIG_ION_SYSTEM_HEAP=y +CONFIG_ION_CMA_HEAP=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_SCPI=y +CONFIG_COMMON_CLK_CS2000_CP=y +CONFIG_COMMON_CLK_S2MPS11=y +CONFIG_CLK_QORIQ=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_COMMON_CLK_QCOM=y +CONFIG_QCOM_CLK_SMD_RPM=y +CONFIG_IPQ_GCC_8074=y +CONFIG_MSM_GCC_8916=y +CONFIG_MSM_GCC_8994=y +CONFIG_MSM_MMCC_8996=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_CLKSRC_IMX_SYS_CNT=y +CONFIG_ARM_MHU=y +CONFIG_PLATFORM_MHU=y +CONFIG_BCM2835_MBOX=y +CONFIG_HI6220_MBOX=y +CONFIG_ROCKCHIP_IOMMU=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y +CONFIG_RPMSG=y +CONFIG_RPMSG_QCOM_SMD=y +CONFIG_RASPBERRYPI_POWER=y +CONFIG_ARCH_MXC_ARM64=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SMD_RPM=y +CONFIG_QCOM_SMP2P=y +CONFIG_QCOM_SMSM=y +CONFIG_ROCKCHIP_PM_DOMAINS=y +CONFIG_ARCH_TEGRA_132_SOC=y +CONFIG_ARCH_TEGRA_210_SOC=y +CONFIG_ARCH_TEGRA_186_SOC=y +CONFIG_EXTCON_PTN5150=y +CONFIG_IIO=y +CONFIG_EXYNOS_ADC=y +CONFIG_IMX8QXP_ADC=y +CONFIG_ROCKCHIP_SARADC=m +CONFIG_PWM=y +CONFIG_PWM_BCM2835=m +CONFIG_PWM_CROS_EC=m +CONFIG_PWM_FSL_FTM=y +CONFIG_PWM_IMX=y +CONFIG_PWM_MESON=m +CONFIG_PWM_ROCKCHIP=y +CONFIG_PWM_SAMSUNG=y +CONFIG_PWM_TEGRA=m +CONFIG_PHY_XGENE=y +CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_HI6220_USB=y +CONFIG_PHY_RCAR_GEN3_USB2=y +CONFIG_PHY_ROCKCHIP_EMMC=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_PCIE=m +CONFIG_PHY_TEGRA_XUSB=y +CONFIG_QCOM_L2_PMU=y +CONFIG_QCOM_L3_PMU=y +CONFIG_IMX8_DDR_PERF=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_IMX_SCU_OCOTP=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_EFI_CAPSULE_LOADER=y +CONFIG_ACPI=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_VFAT_FS=y +CONFIG_HUGETLBFS=y +CONFIG_EFIVAR_FS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_9P_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +CONFIG_MEMTEST=y +CONFIG_SECURITY=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CHACHA20POLY1305=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA512_ARM64=m +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m +CONFIG_CRYPTO_CRC32_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_AES_ARM64_BS=m diff --git a/recipes-kernel/linux/linux-coral/defconfig b/recipes-kernel/linux/files/mendel.cfg similarity index 100% rename from recipes-kernel/linux/linux-coral/defconfig rename to recipes-kernel/linux/files/mendel.cfg diff --git a/recipes-kernel/linux/files/wifi.cfg b/recipes-kernel/linux/files/wifi.cfg new file mode 100644 index 0000000..3fa7961 --- /dev/null +++ b/recipes-kernel/linux/files/wifi.cfg @@ -0,0 +1,4 @@ +CONFIG_ATH10K=m +CONFIG_ATH10K_PCI=y +CONFIG_ATH_CARDS=y +CONFIG_WLAN=y diff --git a/recipes-kernel/linux/linux-coral-5.4/0001-regulator-bd718x7-Add-MODULE_ALIAS.patch b/recipes-kernel/linux/linux-coral-5.4/0001-regulator-bd718x7-Add-MODULE_ALIAS.patch new file mode 100644 index 0000000..4c98f43 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0001-regulator-bd718x7-Add-MODULE_ALIAS.patch @@ -0,0 +1,29 @@ +From 754c063fa38f0d4535e8d022f895e385728ca846 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Guido=20G=C3=BCnther?= +Date: Mon, 30 Sep 2019 22:26:00 +0200 +Subject: [PATCH 01/21] regulator: bd718x7: Add MODULE_ALIAS() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This fixes device probing when built as a module + +Signed-off-by: Guido Günther +Link: https://lore.kernel.org/r/46ce3400e227dd88d51486c02a6152c9ec52acbb.1569875042.git.agx@sigxcpu.org +Signed-off-by: Mark Brown +--- + drivers/regulator/bd718x7-regulator.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/regulator/bd718x7-regulator.c b/drivers/regulator/bd718x7-regulator.c +index bdab46a5c461..13a43eee2e46 100644 +--- a/drivers/regulator/bd718x7-regulator.c ++++ b/drivers/regulator/bd718x7-regulator.c +@@ -1293,3 +1293,4 @@ module_platform_driver(bd718xx_regulator); + MODULE_AUTHOR("Matti Vaittinen "); + MODULE_DESCRIPTION("BD71837/BD71847 voltage regulator driver"); + MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:bd718xx-pmic"); +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0002-regulator-bd718x7-Simplify-the-code-by-removing-stru.patch b/recipes-kernel/linux/linux-coral-5.4/0002-regulator-bd718x7-Simplify-the-code-by-removing-stru.patch new file mode 100644 index 0000000..bfa1356 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0002-regulator-bd718x7-Simplify-the-code-by-removing-stru.patch @@ -0,0 +1,92 @@ +From 28e6442b240279af714dbfd0144b2f5e8cbc2b6a Mon Sep 17 00:00:00 2001 +From: Axel Lin +Date: Wed, 8 Jan 2020 09:42:55 +0800 +Subject: [PATCH 02/21] regulator: bd718x7: Simplify the code by removing + struct bd718xx_pmic_inits + +Nowdays ROHM_CHIP_TYPE_AMOUNT includes not only BD71837/BD71847 but also +BD70528/BD71828 which are not supported by this driver. So it seems not +necessay to have pmic_regulators[ROHM_CHIP_TYPE_AMOUNT] as mapping table. +Simplify the code by removing struct bd718xx_pmic_inits and +pmic_regulators[ROHM_CHIP_TYPE_AMOUNT]. + +Signed-off-by: Axel Lin +Link: https://lore.kernel.org/r/20200108014256.11282-1-axel.lin@ingics.com +Signed-off-by: Mark Brown +--- + drivers/regulator/bd718x7-regulator.c | 34 +++++++++++---------------- + 1 file changed, 14 insertions(+), 20 deletions(-) + +diff --git a/drivers/regulator/bd718x7-regulator.c b/drivers/regulator/bd718x7-regulator.c +index 13a43eee2e46..8f9b2d8eaf10 100644 +--- a/drivers/regulator/bd718x7-regulator.c ++++ b/drivers/regulator/bd718x7-regulator.c +@@ -1142,28 +1142,14 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { + }, + }; + +-struct bd718xx_pmic_inits { +- const struct bd718xx_regulator_data *r_datas; +- unsigned int r_amount; +-}; +- + static int bd718xx_probe(struct platform_device *pdev) + { + struct bd718xx *mfd; + struct regulator_config config = { 0 }; +- struct bd718xx_pmic_inits pmic_regulators[ROHM_CHIP_TYPE_AMOUNT] = { +- [ROHM_CHIP_TYPE_BD71837] = { +- .r_datas = bd71837_regulators, +- .r_amount = ARRAY_SIZE(bd71837_regulators), +- }, +- [ROHM_CHIP_TYPE_BD71847] = { +- .r_datas = bd71847_regulators, +- .r_amount = ARRAY_SIZE(bd71847_regulators), +- }, +- }; +- + int i, j, err; + bool use_snvs; ++ const struct bd718xx_regulator_data *reg_data; ++ unsigned int num_reg_data; + + mfd = dev_get_drvdata(pdev->dev.parent); + if (!mfd) { +@@ -1172,8 +1158,16 @@ static int bd718xx_probe(struct platform_device *pdev) + goto err; + } + +- if (mfd->chip.chip_type >= ROHM_CHIP_TYPE_AMOUNT || +- !pmic_regulators[mfd->chip.chip_type].r_datas) { ++ switch (mfd->chip.chip_type) { ++ case ROHM_CHIP_TYPE_BD71837: ++ reg_data = bd71837_regulators; ++ num_reg_data = ARRAY_SIZE(bd71837_regulators); ++ break; ++ case ROHM_CHIP_TYPE_BD71847: ++ reg_data = bd71847_regulators; ++ num_reg_data = ARRAY_SIZE(bd71847_regulators); ++ break; ++ default: + dev_err(&pdev->dev, "Unsupported chip type\n"); + err = -EINVAL; + goto err; +@@ -1215,13 +1209,13 @@ static int bd718xx_probe(struct platform_device *pdev) + } + } + +- for (i = 0; i < pmic_regulators[mfd->chip.chip_type].r_amount; i++) { ++ for (i = 0; i < num_reg_data; i++) { + + const struct regulator_desc *desc; + struct regulator_dev *rdev; + const struct bd718xx_regulator_data *r; + +- r = &pmic_regulators[mfd->chip.chip_type].r_datas[i]; ++ r = ®_data[i]; + desc = &r->desc; + + config.dev = pdev->dev.parent; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0003-mfd-Rohm-PMICs-Use-platform_device_id-to-match-MFD-s.patch b/recipes-kernel/linux/linux-coral-5.4/0003-mfd-Rohm-PMICs-Use-platform_device_id-to-match-MFD-s.patch new file mode 100644 index 0000000..67d6027 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0003-mfd-Rohm-PMICs-Use-platform_device_id-to-match-MFD-s.patch @@ -0,0 +1,229 @@ +From 998dc427dbb50c81f2a588667bff4a1328460c24 Mon Sep 17 00:00:00 2001 +From: Matti Vaittinen +Date: Mon, 20 Jan 2020 15:42:38 +0200 +Subject: [PATCH 03/21] mfd: Rohm PMICs: Use platform_device_id to match MFD + sub-devices + +Thanks to Stephen Boyd I today learned we can use platform_device_id +to do device and module matching for MFD sub-devices! + +Do device matching using the platform_device_id instead of using +explicit module_aliases to load modules and custom parent-data field +to do module loading and sub-device matching. + +Cc: Stephen Boyd +Signed-off-by: Matti Vaittinen +Acked-by: Mark Brown +Signed-off-by: Lee Jones +--- + drivers/clk/clk-bd718x7.c | 12 ++++++++- + drivers/mfd/rohm-bd70528.c | 3 +-- + drivers/mfd/rohm-bd718x7.c | 39 ++++++++++++++++++++++----- + drivers/regulator/bd718x7-regulator.c | 11 +++++++- + include/linux/mfd/rohm-generic.h | 3 +-- + 5 files changed, 55 insertions(+), 13 deletions(-) + +diff --git a/drivers/clk/clk-bd718x7.c b/drivers/clk/clk-bd718x7.c +index ae6e5baee330..1c1764f74d0a 100644 +--- a/drivers/clk/clk-bd718x7.c ++++ b/drivers/clk/clk-bd718x7.c +@@ -74,6 +74,7 @@ static int bd71837_clk_probe(struct platform_device *pdev) + .name = "bd718xx-32k-out", + .ops = &bd71837_clk_ops, + }; ++ enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data; + + c = devm_kzalloc(&pdev->dev, sizeof(*c), GFP_KERNEL); + if (!c) +@@ -87,7 +88,7 @@ static int bd71837_clk_probe(struct platform_device *pdev) + dev_err(&pdev->dev, "No parent clk found\n"); + return -EINVAL; + } +- switch (mfd->chip_type) { ++ switch (chip) { + case ROHM_CHIP_TYPE_BD71837: + case ROHM_CHIP_TYPE_BD71847: + c->reg = BD718XX_REG_OUT32K; +@@ -121,11 +122,20 @@ static int bd71837_clk_probe(struct platform_device *pdev) + return rval; + } + ++static const struct platform_device_id bd718x7_clk_id[] = { ++ { "bd71837-clk", ROHM_CHIP_TYPE_BD71837 }, ++ { "bd71847-clk", ROHM_CHIP_TYPE_BD71847 }, ++ { "bd70528-clk", ROHM_CHIP_TYPE_BD70528 }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(platform, bd718x7_clk_id); ++ + static struct platform_driver bd71837_clk = { + .driver = { + .name = "bd718xx-clk", + }, + .probe = bd71837_clk_probe, ++ .id_table = bd718x7_clk_id, + }; + + module_platform_driver(bd71837_clk); +diff --git a/drivers/mfd/rohm-bd70528.c b/drivers/mfd/rohm-bd70528.c +index 55599d5c5c86..e66a4a1c3731 100644 +--- a/drivers/mfd/rohm-bd70528.c ++++ b/drivers/mfd/rohm-bd70528.c +@@ -48,7 +48,7 @@ static struct mfd_cell bd70528_mfd_cells[] = { + * We use BD71837 driver to drive the clock block. Only differences to + * BD70528 clock gate are the register address and mask. + */ +- { .name = "bd718xx-clk", }, ++ { .name = "bd70528-clk", }, + { .name = "bd70528-wdt", }, + { + .name = "bd70528-power", +@@ -237,7 +237,6 @@ static int bd70528_i2c_probe(struct i2c_client *i2c, + + dev_set_drvdata(&i2c->dev, &bd70528->chip); + +- bd70528->chip.chip_type = ROHM_CHIP_TYPE_BD70528; + bd70528->chip.regmap = devm_regmap_init_i2c(i2c, &bd70528_regmap); + if (IS_ERR(bd70528->chip.regmap)) { + dev_err(&i2c->dev, "Failed to initialize Regmap\n"); +diff --git a/drivers/mfd/rohm-bd718x7.c b/drivers/mfd/rohm-bd718x7.c +index 85e7f5133365..bb86ec829079 100644 +--- a/drivers/mfd/rohm-bd718x7.c ++++ b/drivers/mfd/rohm-bd718x7.c +@@ -30,14 +30,24 @@ static struct gpio_keys_platform_data bd718xx_powerkey_data = { + .name = "bd718xx-pwrkey", + }; + +-static struct mfd_cell bd718xx_mfd_cells[] = { ++static struct mfd_cell bd71837_mfd_cells[] = { + { + .name = "gpio-keys", + .platform_data = &bd718xx_powerkey_data, + .pdata_size = sizeof(bd718xx_powerkey_data), + }, +- { .name = "bd718xx-clk", }, +- { .name = "bd718xx-pmic", }, ++ { .name = "bd71837-clk", }, ++ { .name = "bd71837-pmic", }, ++}; ++ ++static struct mfd_cell bd71847_mfd_cells[] = { ++ { ++ .name = "gpio-keys", ++ .platform_data = &bd718xx_powerkey_data, ++ .pdata_size = sizeof(bd718xx_powerkey_data), ++ }, ++ { .name = "bd71847-clk", }, ++ { .name = "bd71847-pmic", }, + }; + + static const struct regmap_irq bd718xx_irqs[] = { +@@ -124,6 +134,9 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c, + { + struct bd718xx *bd718xx; + int ret; ++ unsigned int chip_type; ++ struct mfd_cell *mfd; ++ int cells; + + if (!i2c->irq) { + dev_err(&i2c->dev, "No IRQ configured\n"); +@@ -136,8 +149,21 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c, + return -ENOMEM; + + bd718xx->chip_irq = i2c->irq; +- bd718xx->chip.chip_type = (unsigned int)(uintptr_t) +- of_device_get_match_data(&i2c->dev); ++ chip_type = (unsigned int)(uintptr_t) ++ of_device_get_match_data(&i2c->dev); ++ switch (chip_type) { ++ case ROHM_CHIP_TYPE_BD71837: ++ mfd = bd71837_mfd_cells; ++ cells = ARRAY_SIZE(bd71837_mfd_cells); ++ break; ++ case ROHM_CHIP_TYPE_BD71847: ++ mfd = bd71847_mfd_cells; ++ cells = ARRAY_SIZE(bd71847_mfd_cells); ++ break; ++ default: ++ dev_err(&i2c->dev, "Unknown device type"); ++ return -EINVAL; ++ } + bd718xx->chip.dev = &i2c->dev; + dev_set_drvdata(&i2c->dev, bd718xx); + +@@ -170,8 +196,7 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c, + button.irq = ret; + + ret = devm_mfd_add_devices(bd718xx->chip.dev, PLATFORM_DEVID_AUTO, +- bd718xx_mfd_cells, +- ARRAY_SIZE(bd718xx_mfd_cells), NULL, 0, ++ mfd, cells, NULL, 0, + regmap_irq_get_domain(bd718xx->irq_data)); + if (ret) + dev_err(&i2c->dev, "Failed to create subdevices\n"); +diff --git a/drivers/regulator/bd718x7-regulator.c b/drivers/regulator/bd718x7-regulator.c +index 8f9b2d8eaf10..1ad69f7b6d9f 100644 +--- a/drivers/regulator/bd718x7-regulator.c ++++ b/drivers/regulator/bd718x7-regulator.c +@@ -1150,6 +1150,7 @@ static int bd718xx_probe(struct platform_device *pdev) + bool use_snvs; + const struct bd718xx_regulator_data *reg_data; + unsigned int num_reg_data; ++ enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data; + + mfd = dev_get_drvdata(pdev->dev.parent); + if (!mfd) { +@@ -1158,7 +1159,7 @@ static int bd718xx_probe(struct platform_device *pdev) + goto err; + } + +- switch (mfd->chip.chip_type) { ++ switch (chip) { + case ROHM_CHIP_TYPE_BD71837: + reg_data = bd71837_regulators; + num_reg_data = ARRAY_SIZE(bd71837_regulators); +@@ -1275,11 +1276,19 @@ static int bd718xx_probe(struct platform_device *pdev) + return err; + } + ++static const struct platform_device_id bd718x7_pmic_id[] = { ++ { "bd71837-pmic", ROHM_CHIP_TYPE_BD71837 }, ++ { "bd71847-pmic", ROHM_CHIP_TYPE_BD71847 }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(platform, bd718x7_pmic_id); ++ + static struct platform_driver bd718xx_regulator = { + .driver = { + .name = "bd718xx-pmic", + }, + .probe = bd718xx_probe, ++ .id_table = bd718x7_pmic_id, + }; + + module_platform_driver(bd718xx_regulator); +diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h +index bff15ac26f2c..922f88008232 100644 +--- a/include/linux/mfd/rohm-generic.h ++++ b/include/linux/mfd/rohm-generic.h +@@ -4,7 +4,7 @@ + #ifndef __LINUX_MFD_ROHM_H__ + #define __LINUX_MFD_ROHM_H__ + +-enum { ++enum rohm_chip_type { + ROHM_CHIP_TYPE_BD71837 = 0, + ROHM_CHIP_TYPE_BD71847, + ROHM_CHIP_TYPE_BD70528, +@@ -12,7 +12,6 @@ enum { + }; + + struct rohm_regmap_dev { +- unsigned int chip_type; + struct device *dev; + struct regmap *regmap; + }; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0004-regulator-bd718x7-Split-driver-to-common-and-bd718x7.patch b/recipes-kernel/linux/linux-coral-5.4/0004-regulator-bd718x7-Split-driver-to-common-and-bd718x7.patch new file mode 100644 index 0000000..a7c1c23 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0004-regulator-bd718x7-Split-driver-to-common-and-bd718x7.patch @@ -0,0 +1,494 @@ +From 46e726b6717847da205dccaf883d73fa1565f7d1 Mon Sep 17 00:00:00 2001 +From: Matti Vaittinen +Date: Mon, 20 Jan 2020 15:44:45 +0200 +Subject: [PATCH 04/21] regulator: bd718x7: Split driver to common and bd718x7 + specific parts + +Few ROHM PMICs allow setting the voltage states for different system states +like RUN, IDLE, SUSPEND and LPSR. States are then changed via SoC specific +mechanisms. bd718x7 driver implemented device-tree parsing functions for +these state specific voltages. The parsing functions can be re-used by +other ROHM chip drivers like bd71828. Split the generic functions from +bd718x7-regulator.c to rohm-regulator.c and export them for other modules +to use. + +Signed-off-by: Matti Vaittinen +Acked-by: Mark Brown +Signed-off-by: Lee Jones +--- + drivers/regulator/Kconfig | 4 + + drivers/regulator/Makefile | 1 + + drivers/regulator/bd718x7-regulator.c | 183 ++++++++------------------ + drivers/regulator/rohm-regulator.c | 95 +++++++++++++ + include/linux/mfd/rohm-generic.h | 66 ++++++++++ + 5 files changed, 221 insertions(+), 128 deletions(-) + create mode 100644 drivers/regulator/rohm-regulator.c + +diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig +index 96cdc0e1f7e8..af0ba71a5df6 100644 +--- a/drivers/regulator/Kconfig ++++ b/drivers/regulator/Kconfig +@@ -197,6 +197,7 @@ config REGULATOR_BD70528 + config REGULATOR_BD718XX + tristate "ROHM BD71837 Power Regulator" + depends on MFD_ROHM_BD718XX ++ select REGULATOR_ROHM + help + This driver supports voltage regulators on ROHM BD71837 PMIC. + This will enable support for the software controllable buck +@@ -808,6 +809,9 @@ config REGULATOR_RN5T618 + Say y here to support the regulators found on Ricoh RN5T567, + RN5T618 or RC5T619 PMIC. + ++config REGULATOR_ROHM ++ tristate ++ + config REGULATOR_RT5033 + tristate "Richtek RT5033 Regulators" + depends on MFD_RT5033 +diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile +index c58c41a3260c..4ab1fe2af3b3 100644 +--- a/drivers/regulator/Makefile ++++ b/drivers/regulator/Makefile +@@ -102,6 +102,7 @@ obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o + obj-$(CONFIG_REGULATOR_RC5T583) += rc5t583-regulator.o + obj-$(CONFIG_REGULATOR_RK808) += rk808-regulator.o + obj-$(CONFIG_REGULATOR_RN5T618) += rn5t618-regulator.o ++obj-$(CONFIG_REGULATOR_ROHM) += rohm-regulator.o + obj-$(CONFIG_REGULATOR_RT5033) += rt5033-regulator.o + obj-$(CONFIG_REGULATOR_S2MPA01) += s2mpa01.o + obj-$(CONFIG_REGULATOR_S2MPS11) += s2mps11.o +diff --git a/drivers/regulator/bd718x7-regulator.c b/drivers/regulator/bd718x7-regulator.c +index 1ad69f7b6d9f..cf3872837abc 100644 +--- a/drivers/regulator/bd718x7-regulator.c ++++ b/drivers/regulator/bd718x7-regulator.c +@@ -318,6 +318,7 @@ struct reg_init { + }; + struct bd718xx_regulator_data { + struct regulator_desc desc; ++ const struct rohm_dvs_config dvs; + const struct reg_init init; + const struct reg_init *additional_inits; + int additional_init_amnt; +@@ -349,133 +350,15 @@ static const struct reg_init bd71837_ldo6_inits[] = { + }, + }; + +-#define NUM_DVS_BUCKS 4 +- +-struct of_dvs_setting { +- const char *prop; +- unsigned int reg; +-}; +- +-static int set_dvs_levels(const struct of_dvs_setting *dvs, +- struct device_node *np, +- const struct regulator_desc *desc, +- struct regmap *regmap) +-{ +- int ret, i; +- unsigned int uv; +- +- ret = of_property_read_u32(np, dvs->prop, &uv); +- if (ret) { +- if (ret != -EINVAL) +- return ret; +- return 0; +- } +- +- for (i = 0; i < desc->n_voltages; i++) { +- ret = regulator_desc_list_voltage_linear_range(desc, i); +- if (ret < 0) +- continue; +- if (ret == uv) { +- i <<= ffs(desc->vsel_mask) - 1; +- ret = regmap_update_bits(regmap, dvs->reg, +- DVS_BUCK_RUN_MASK, i); +- break; +- } +- } +- return ret; +-} +- +-static int buck4_set_hw_dvs_levels(struct device_node *np, ++static int buck_set_hw_dvs_levels(struct device_node *np, + const struct regulator_desc *desc, + struct regulator_config *cfg) + { +- int ret, i; +- const struct of_dvs_setting dvs[] = { +- { +- .prop = "rohm,dvs-run-voltage", +- .reg = BD71837_REG_BUCK4_VOLT_RUN, +- }, +- }; ++ struct bd718xx_regulator_data *data; + +- for (i = 0; i < ARRAY_SIZE(dvs); i++) { +- ret = set_dvs_levels(&dvs[i], np, desc, cfg->regmap); +- if (ret) +- break; +- } +- return ret; +-} +-static int buck3_set_hw_dvs_levels(struct device_node *np, +- const struct regulator_desc *desc, +- struct regulator_config *cfg) +-{ +- int ret, i; +- const struct of_dvs_setting dvs[] = { +- { +- .prop = "rohm,dvs-run-voltage", +- .reg = BD71837_REG_BUCK3_VOLT_RUN, +- }, +- }; ++ data = container_of(desc, struct bd718xx_regulator_data, desc); + +- for (i = 0; i < ARRAY_SIZE(dvs); i++) { +- ret = set_dvs_levels(&dvs[i], np, desc, cfg->regmap); +- if (ret) +- break; +- } +- return ret; +-} +- +-static int buck2_set_hw_dvs_levels(struct device_node *np, +- const struct regulator_desc *desc, +- struct regulator_config *cfg) +-{ +- int ret, i; +- const struct of_dvs_setting dvs[] = { +- { +- .prop = "rohm,dvs-run-voltage", +- .reg = BD718XX_REG_BUCK2_VOLT_RUN, +- }, +- { +- .prop = "rohm,dvs-idle-voltage", +- .reg = BD718XX_REG_BUCK2_VOLT_IDLE, +- }, +- }; +- +- +- +- for (i = 0; i < ARRAY_SIZE(dvs); i++) { +- ret = set_dvs_levels(&dvs[i], np, desc, cfg->regmap); +- if (ret) +- break; +- } +- return ret; +-} +- +-static int buck1_set_hw_dvs_levels(struct device_node *np, +- const struct regulator_desc *desc, +- struct regulator_config *cfg) +-{ +- int ret, i; +- const struct of_dvs_setting dvs[] = { +- { +- .prop = "rohm,dvs-run-voltage", +- .reg = BD718XX_REG_BUCK1_VOLT_RUN, +- }, +- { +- .prop = "rohm,dvs-idle-voltage", +- .reg = BD718XX_REG_BUCK1_VOLT_IDLE, +- }, +- { +- .prop = "rohm,dvs-suspend-voltage", +- .reg = BD718XX_REG_BUCK1_VOLT_SUSP, +- }, +- }; +- +- for (i = 0; i < ARRAY_SIZE(dvs); i++) { +- ret = set_dvs_levels(&dvs[i], np, desc, cfg->regmap); +- if (ret) +- break; +- } +- return ret; ++ return rohm_regulator_set_dvs_levels(&data->dvs, np, desc, cfg->regmap); + } + + static const struct bd718xx_regulator_data bd71847_regulators[] = { +@@ -496,7 +379,17 @@ static const struct bd718xx_regulator_data bd71847_regulators[] = { + .enable_reg = BD718XX_REG_BUCK1_CTRL, + .enable_mask = BD718XX_BUCK_EN, + .owner = THIS_MODULE, +- .of_parse_cb = buck1_set_hw_dvs_levels, ++ .of_parse_cb = buck_set_hw_dvs_levels, ++ }, ++ .dvs = { ++ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | ++ ROHM_DVS_LEVEL_SUSPEND, ++ .run_reg = BD718XX_REG_BUCK1_VOLT_RUN, ++ .run_mask = DVS_BUCK_RUN_MASK, ++ .idle_reg = BD718XX_REG_BUCK1_VOLT_IDLE, ++ .idle_mask = DVS_BUCK_RUN_MASK, ++ .suspend_reg = BD718XX_REG_BUCK1_VOLT_SUSP, ++ .suspend_mask = DVS_BUCK_RUN_MASK, + }, + .init = { + .reg = BD718XX_REG_BUCK1_CTRL, +@@ -520,7 +413,14 @@ static const struct bd718xx_regulator_data bd71847_regulators[] = { + .enable_reg = BD718XX_REG_BUCK2_CTRL, + .enable_mask = BD718XX_BUCK_EN, + .owner = THIS_MODULE, +- .of_parse_cb = buck2_set_hw_dvs_levels, ++ .of_parse_cb = buck_set_hw_dvs_levels, ++ }, ++ .dvs = { ++ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE, ++ .run_reg = BD718XX_REG_BUCK2_VOLT_RUN, ++ .run_mask = DVS_BUCK_RUN_MASK, ++ .idle_reg = BD718XX_REG_BUCK2_VOLT_IDLE, ++ .idle_mask = DVS_BUCK_RUN_MASK, + }, + .init = { + .reg = BD718XX_REG_BUCK2_CTRL, +@@ -792,7 +692,17 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { + .enable_reg = BD718XX_REG_BUCK1_CTRL, + .enable_mask = BD718XX_BUCK_EN, + .owner = THIS_MODULE, +- .of_parse_cb = buck1_set_hw_dvs_levels, ++ .of_parse_cb = buck_set_hw_dvs_levels, ++ }, ++ .dvs = { ++ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE | ++ ROHM_DVS_LEVEL_SUSPEND, ++ .run_reg = BD718XX_REG_BUCK1_VOLT_RUN, ++ .run_mask = DVS_BUCK_RUN_MASK, ++ .idle_reg = BD718XX_REG_BUCK1_VOLT_IDLE, ++ .idle_mask = DVS_BUCK_RUN_MASK, ++ .suspend_reg = BD718XX_REG_BUCK1_VOLT_SUSP, ++ .suspend_mask = DVS_BUCK_RUN_MASK, + }, + .init = { + .reg = BD718XX_REG_BUCK1_CTRL, +@@ -816,7 +726,14 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { + .enable_reg = BD718XX_REG_BUCK2_CTRL, + .enable_mask = BD718XX_BUCK_EN, + .owner = THIS_MODULE, +- .of_parse_cb = buck2_set_hw_dvs_levels, ++ .of_parse_cb = buck_set_hw_dvs_levels, ++ }, ++ .dvs = { ++ .level_map = ROHM_DVS_LEVEL_RUN | ROHM_DVS_LEVEL_IDLE, ++ .run_reg = BD718XX_REG_BUCK2_VOLT_RUN, ++ .run_mask = DVS_BUCK_RUN_MASK, ++ .idle_reg = BD718XX_REG_BUCK2_VOLT_IDLE, ++ .idle_mask = DVS_BUCK_RUN_MASK, + }, + .init = { + .reg = BD718XX_REG_BUCK2_CTRL, +@@ -840,7 +757,12 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { + .enable_reg = BD71837_REG_BUCK3_CTRL, + .enable_mask = BD718XX_BUCK_EN, + .owner = THIS_MODULE, +- .of_parse_cb = buck3_set_hw_dvs_levels, ++ .of_parse_cb = buck_set_hw_dvs_levels, ++ }, ++ .dvs = { ++ .level_map = ROHM_DVS_LEVEL_RUN, ++ .run_reg = BD71837_REG_BUCK3_VOLT_RUN, ++ .run_mask = DVS_BUCK_RUN_MASK, + }, + .init = { + .reg = BD71837_REG_BUCK3_CTRL, +@@ -864,7 +786,12 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { + .enable_reg = BD71837_REG_BUCK4_CTRL, + .enable_mask = BD718XX_BUCK_EN, + .owner = THIS_MODULE, +- .of_parse_cb = buck4_set_hw_dvs_levels, ++ .of_parse_cb = buck_set_hw_dvs_levels, ++ }, ++ .dvs = { ++ .level_map = ROHM_DVS_LEVEL_RUN, ++ .run_reg = BD71837_REG_BUCK4_VOLT_RUN, ++ .run_mask = DVS_BUCK_RUN_MASK, + }, + .init = { + .reg = BD71837_REG_BUCK4_CTRL, +diff --git a/drivers/regulator/rohm-regulator.c b/drivers/regulator/rohm-regulator.c +new file mode 100644 +index 000000000000..399002383b28 +--- /dev/null ++++ b/drivers/regulator/rohm-regulator.c +@@ -0,0 +1,95 @@ ++// SPDX-License-Identifier: GPL-2.0 ++// Copyright (C) 2020 ROHM Semiconductors ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int set_dvs_level(const struct regulator_desc *desc, ++ struct device_node *np, struct regmap *regmap, ++ char *prop, unsigned int reg, unsigned int mask, ++ unsigned int omask, unsigned int oreg) ++{ ++ int ret, i; ++ uint32_t uv; ++ ++ ret = of_property_read_u32(np, prop, &uv); ++ if (ret) { ++ if (ret != -EINVAL) ++ return ret; ++ return 0; ++ } ++ ++ if (uv == 0) { ++ if (omask) ++ return regmap_update_bits(regmap, oreg, omask, 0); ++ } ++ for (i = 0; i < desc->n_voltages; i++) { ++ ret = regulator_desc_list_voltage_linear_range(desc, i); ++ if (ret < 0) ++ continue; ++ if (ret == uv) { ++ i <<= ffs(desc->vsel_mask) - 1; ++ ret = regmap_update_bits(regmap, reg, mask, i); ++ if (omask && !ret) ++ ret = regmap_update_bits(regmap, oreg, omask, ++ omask); ++ break; ++ } ++ } ++ return ret; ++} ++ ++int rohm_regulator_set_dvs_levels(const struct rohm_dvs_config *dvs, ++ struct device_node *np, ++ const struct regulator_desc *desc, ++ struct regmap *regmap) ++{ ++ int i, ret = 0; ++ char *prop; ++ unsigned int reg, mask, omask, oreg = desc->enable_reg; ++ ++ for (i = 0; i < ROHM_DVS_LEVEL_MAX && !ret; i++) { ++ if (dvs->level_map & (1 << i)) { ++ switch (i + 1) { ++ case ROHM_DVS_LEVEL_RUN: ++ prop = "rohm,dvs-run-voltage"; ++ reg = dvs->run_reg; ++ mask = dvs->run_mask; ++ omask = dvs->run_on_mask; ++ break; ++ case ROHM_DVS_LEVEL_IDLE: ++ prop = "rohm,dvs-idle-voltage"; ++ reg = dvs->idle_reg; ++ mask = dvs->idle_mask; ++ omask = dvs->idle_on_mask; ++ break; ++ case ROHM_DVS_LEVEL_SUSPEND: ++ prop = "rohm,dvs-suspend-voltage"; ++ reg = dvs->suspend_reg; ++ mask = dvs->suspend_mask; ++ omask = dvs->suspend_on_mask; ++ break; ++ case ROHM_DVS_LEVEL_LPSR: ++ prop = "rohm,dvs-lpsr-voltage"; ++ reg = dvs->lpsr_reg; ++ mask = dvs->lpsr_mask; ++ omask = dvs->lpsr_on_mask; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ret = set_dvs_level(desc, np, regmap, prop, reg, mask, ++ omask, oreg); ++ } ++ } ++ return ret; ++} ++EXPORT_SYMBOL(rohm_regulator_set_dvs_levels); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Matti Vaittinen "); ++MODULE_DESCRIPTION("Generic helpers for ROHM PMIC regulator drivers"); +diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h +index 922f88008232..800cc923fec8 100644 +--- a/include/linux/mfd/rohm-generic.h ++++ b/include/linux/mfd/rohm-generic.h +@@ -4,6 +4,9 @@ + #ifndef __LINUX_MFD_ROHM_H__ + #define __LINUX_MFD_ROHM_H__ + ++#include ++#include ++ + enum rohm_chip_type { + ROHM_CHIP_TYPE_BD71837 = 0, + ROHM_CHIP_TYPE_BD71847, +@@ -16,4 +19,67 @@ struct rohm_regmap_dev { + struct regmap *regmap; + }; + ++enum { ++ ROHM_DVS_LEVEL_UNKNOWN, ++ ROHM_DVS_LEVEL_RUN, ++ ROHM_DVS_LEVEL_IDLE, ++ ROHM_DVS_LEVEL_SUSPEND, ++ ROHM_DVS_LEVEL_LPSR, ++ ROHM_DVS_LEVEL_MAX = ROHM_DVS_LEVEL_LPSR, ++}; ++ ++/** ++ * struct rohm_dvs_config - dynamic voltage scaling register descriptions ++ * ++ * @level_map: bitmap representing supported run-levels for this ++ * regulator ++ * @run_reg: register address for regulator config at 'run' state ++ * @run_mask: value mask for regulator voltages at 'run' state ++ * @run_on_mask: enable mask for regulator at 'run' state ++ * @idle_reg: register address for regulator config at 'idle' state ++ * @idle_mask: value mask for regulator voltages at 'idle' state ++ * @idle_on_mask: enable mask for regulator at 'idle' state ++ * @suspend_reg: register address for regulator config at 'suspend' state ++ * @suspend_mask: value mask for regulator voltages at 'suspend' state ++ * @suspend_on_mask: enable mask for regulator at 'suspend' state ++ * @lpsr_reg: register address for regulator config at 'lpsr' state ++ * @lpsr_mask: value mask for regulator voltages at 'lpsr' state ++ * @lpsr_on_mask: enable mask for regulator at 'lpsr' state ++ * ++ * Description of ROHM PMICs voltage configuration registers for different ++ * system states. This is used to correctly configure the PMIC at startup ++ * based on values read from DT. ++ */ ++struct rohm_dvs_config { ++ uint64_t level_map; ++ unsigned int run_reg; ++ unsigned int run_mask; ++ unsigned int run_on_mask; ++ unsigned int idle_reg; ++ unsigned int idle_mask; ++ unsigned int idle_on_mask; ++ unsigned int suspend_reg; ++ unsigned int suspend_mask; ++ unsigned int suspend_on_mask; ++ unsigned int lpsr_reg; ++ unsigned int lpsr_mask; ++ unsigned int lpsr_on_mask; ++}; ++ ++#if IS_ENABLED(CONFIG_REGULATOR_ROHM) ++int rohm_regulator_set_dvs_levels(const struct rohm_dvs_config *dvs, ++ struct device_node *np, ++ const struct regulator_desc *desc, ++ struct regmap *regmap); ++ ++#else ++static inline int rohm_regulator_set_dvs_levels(const struct rohm_dvs_config *dvs, ++ struct device_node *np, ++ const struct regulator_desc *desc, ++ struct regmap *regmap) ++{ ++ return 0; ++} ++#endif ++ + #endif +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0005-regulator-bd718x7-remove-voltage-change-restriction-.patch b/recipes-kernel/linux/linux-coral-5.4/0005-regulator-bd718x7-remove-voltage-change-restriction-.patch new file mode 100644 index 0000000..996839d --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0005-regulator-bd718x7-remove-voltage-change-restriction-.patch @@ -0,0 +1,325 @@ +From f46b9d18f4fb8588c6048b8024523e012424d914 Mon Sep 17 00:00:00 2001 +From: Matti Vaittinen +Date: Wed, 13 May 2020 17:39:21 +0300 +Subject: [PATCH 05/21] regulator: bd718x7: remove voltage change restriction + from BD71847 LDOs + +The BD71837 had a HW "feature" where changing the regulator output +voltages of other regulators but bucks 1-4 might cause spikes if +regulators were enabled. Thus SW prohibit voltage changes for other +regulators except for bucks 1-4 when regulator is enabled. + +The HW colleagues did inadvertly fix this issue for BD71847 and +BD71850. + +The power-good detection for LDOs can still cause false alarms if +LDO voltage is changed upwards when LDO is enabled. + +Allow LDO voltage changes and disabe the power-good monioring for +the duration of the LDO voltage change and enable it after LDO +voltage has stabilized. ROHM HW colleagues measured the safety +limit of 1000uS for guaranteeing the voltage has stabilized. Let's +use that for starters and add confiurable stabilization wait-time +later if needed. + +Signed-off-by: Matti Vaittinen +Link: https://lore.kernel.org/r/20200513143921.GA22143@localhost.localdomain +Signed-off-by: Mark Brown +--- + drivers/regulator/bd718x7-regulator.c | 189 ++++++++++++++++++++++++-- + 1 file changed, 179 insertions(+), 10 deletions(-) + +diff --git a/drivers/regulator/bd718x7-regulator.c b/drivers/regulator/bd718x7-regulator.c +index cf3872837abc..003706cf6970 100644 +--- a/drivers/regulator/bd718x7-regulator.c ++++ b/drivers/regulator/bd718x7-regulator.c +@@ -59,8 +59,14 @@ static int bd718xx_buck1234_set_ramp_delay(struct regulator_dev *rdev, + * Bucks 5 to 8 and LDOs can use PFM and must be disabled when voltage + * is changed. Hence we return -EBUSY for these if voltage is changed + * when BUCK/LDO is enabled. ++ * ++ * On BD71847, BD71850, ... The LDO voltage can be changed when LDO is ++ * enabled. But if voltage is increased the LDO power-good monitoring ++ * must be disabled for the duration of changing + 1mS to ensure voltage ++ * has reached the higher level before HW does next under voltage detection ++ * cycle. + */ +-static int bd718xx_set_voltage_sel_restricted(struct regulator_dev *rdev, ++static int bd71837_set_voltage_sel_restricted(struct regulator_dev *rdev, + unsigned int sel) + { + if (regulator_is_enabled_regmap(rdev)) +@@ -69,8 +75,123 @@ static int bd718xx_set_voltage_sel_restricted(struct regulator_dev *rdev, + return regulator_set_voltage_sel_regmap(rdev, sel); + } + ++static void voltage_change_done(struct regulator_dev *rdev, unsigned int sel, ++ unsigned int *mask) ++{ ++ int ret; ++ ++ if (*mask) { ++ /* ++ * Let's allow scheduling as we use I2C anyways. We just need to ++ * guarantee minimum of 1ms sleep - it shouldn't matter if we ++ * exceed it due to the scheduling. ++ */ ++ msleep(1); ++ /* ++ * Note for next hacker. The PWRGOOD should not be masked on ++ * BD71847 so we will just unconditionally enable detection ++ * when voltage is set. ++ * If someone want's to disable PWRGOOD he must implement ++ * caching and restoring the old value here. I am not ++ * aware of such use-cases so for the sake of the simplicity ++ * we just always enable PWRGOOD here. ++ */ ++ ret = regmap_update_bits(rdev->regmap, BD718XX_REG_MVRFLTMASK2, ++ *mask, 0); ++ if (ret) ++ dev_err(&rdev->dev, ++ "Failed to re-enable voltage monitoring (%d)\n", ++ ret); ++ } ++} ++ ++static int voltage_change_prepare(struct regulator_dev *rdev, unsigned int sel, ++ unsigned int *mask) ++{ ++ int ret; ++ ++ *mask = 0; ++ if (regulator_is_enabled_regmap(rdev)) { ++ int now, new; ++ ++ now = rdev->desc->ops->get_voltage_sel(rdev); ++ if (now < 0) ++ return now; ++ ++ now = rdev->desc->ops->list_voltage(rdev, now); ++ if (now < 0) ++ return now; ++ ++ new = rdev->desc->ops->list_voltage(rdev, sel); ++ if (new < 0) ++ return new; ++ ++ /* ++ * If we increase LDO voltage when LDO is enabled we need to ++ * disable the power-good detection until voltage has reached ++ * the new level. According to HW colleagues the maximum time ++ * it takes is 1000us. I assume that on systems with light load ++ * this might be less - and we could probably use DT to give ++ * system specific delay value if performance matters. ++ * ++ * Well, knowing we use I2C here and can add scheduling delays ++ * I don't think it is worth the hassle and I just add fixed ++ * 1ms sleep here (and allow scheduling). If this turns out to ++ * be a problem we can change it to delay and make the delay ++ * time configurable. ++ */ ++ if (new > now) { ++ int ldo_offset = rdev->desc->id - BD718XX_LDO1; ++ ++ *mask = BD718XX_LDO1_VRMON80 << ldo_offset; ++ ret = regmap_update_bits(rdev->regmap, ++ BD718XX_REG_MVRFLTMASK2, ++ *mask, *mask); ++ if (ret) { ++ dev_err(&rdev->dev, ++ "Failed to stop voltage monitoring\n"); ++ return ret; ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++static int bd718xx_set_voltage_sel_restricted(struct regulator_dev *rdev, ++ unsigned int sel) ++{ ++ int ret; ++ int mask; ++ ++ ret = voltage_change_prepare(rdev, sel, &mask); ++ if (ret) ++ return ret; ++ ++ ret = regulator_set_voltage_sel_regmap(rdev, sel); ++ voltage_change_done(rdev, sel, &mask); ++ ++ return ret; ++} ++ + static int bd718xx_set_voltage_sel_pickable_restricted( + struct regulator_dev *rdev, unsigned int sel) ++{ ++ int ret; ++ int mask; ++ ++ ret = voltage_change_prepare(rdev, sel, &mask); ++ if (ret) ++ return ret; ++ ++ ret = regulator_set_voltage_sel_pickable_regmap(rdev, sel); ++ voltage_change_done(rdev, sel, &mask); ++ ++ return ret; ++} ++ ++static int bd71837_set_voltage_sel_pickable_restricted( ++ struct regulator_dev *rdev, unsigned int sel) + { + if (regulator_is_enabled_regmap(rdev)) + return -EBUSY; +@@ -85,6 +206,16 @@ static const struct regulator_ops bd718xx_pickable_range_ldo_ops = { + .list_voltage = regulator_list_voltage_pickable_linear_range, + .set_voltage_sel = bd718xx_set_voltage_sel_pickable_restricted, + .get_voltage_sel = regulator_get_voltage_sel_pickable_regmap, ++ ++}; ++ ++static const struct regulator_ops bd71837_pickable_range_ldo_ops = { ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .list_voltage = regulator_list_voltage_pickable_linear_range, ++ .set_voltage_sel = bd71837_set_voltage_sel_pickable_restricted, ++ .get_voltage_sel = regulator_get_voltage_sel_pickable_regmap, + }; + + static const struct regulator_ops bd718xx_pickable_range_buck_ops = { +@@ -92,11 +223,30 @@ static const struct regulator_ops bd718xx_pickable_range_buck_ops = { + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .list_voltage = regulator_list_voltage_pickable_linear_range, +- .set_voltage_sel = bd718xx_set_voltage_sel_pickable_restricted, ++ .set_voltage_sel = regulator_set_voltage_sel_pickable_regmap, ++ .get_voltage_sel = regulator_get_voltage_sel_pickable_regmap, ++ .set_voltage_time_sel = regulator_set_voltage_time_sel, ++}; ++ ++static const struct regulator_ops bd71837_pickable_range_buck_ops = { ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .list_voltage = regulator_list_voltage_pickable_linear_range, ++ .set_voltage_sel = bd71837_set_voltage_sel_pickable_restricted, + .get_voltage_sel = regulator_get_voltage_sel_pickable_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + }; + ++static const struct regulator_ops bd71837_ldo_regulator_ops = { ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .list_voltage = regulator_list_voltage_linear_range, ++ .set_voltage_sel = bd71837_set_voltage_sel_restricted, ++ .get_voltage_sel = regulator_get_voltage_sel_regmap, ++}; ++ + static const struct regulator_ops bd718xx_ldo_regulator_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, +@@ -106,6 +256,15 @@ static const struct regulator_ops bd718xx_ldo_regulator_ops = { + .get_voltage_sel = regulator_get_voltage_sel_regmap, + }; + ++static const struct regulator_ops bd71837_ldo_regulator_nolinear_ops = { ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .list_voltage = regulator_list_voltage_table, ++ .set_voltage_sel = bd71837_set_voltage_sel_restricted, ++ .get_voltage_sel = regulator_get_voltage_sel_regmap, ++}; ++ + static const struct regulator_ops bd718xx_ldo_regulator_nolinear_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, +@@ -120,7 +279,17 @@ static const struct regulator_ops bd718xx_buck_regulator_ops = { + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .list_voltage = regulator_list_voltage_linear_range, +- .set_voltage_sel = bd718xx_set_voltage_sel_restricted, ++ .set_voltage_sel = regulator_set_voltage_sel_regmap, ++ .get_voltage_sel = regulator_get_voltage_sel_regmap, ++ .set_voltage_time_sel = regulator_set_voltage_time_sel, ++}; ++ ++static const struct regulator_ops bd71837_buck_regulator_ops = { ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .list_voltage = regulator_list_voltage_linear_range, ++ .set_voltage_sel = bd71837_set_voltage_sel_restricted, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + }; +@@ -902,7 +1071,7 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { + .of_match = of_match_ptr("LDO1"), + .regulators_node = of_match_ptr("regulators"), + .id = BD718XX_LDO1, +- .ops = &bd718xx_pickable_range_ldo_ops, ++ .ops = &bd71837_pickable_range_ldo_ops, + .type = REGULATOR_VOLTAGE, + .n_voltages = BD718XX_LDO1_VOLTAGE_NUM, + .linear_ranges = bd718xx_ldo1_volts, +@@ -928,7 +1097,7 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { + .of_match = of_match_ptr("LDO2"), + .regulators_node = of_match_ptr("regulators"), + .id = BD718XX_LDO2, +- .ops = &bd718xx_ldo_regulator_nolinear_ops, ++ .ops = &bd71837_ldo_regulator_nolinear_ops, + .type = REGULATOR_VOLTAGE, + .volt_table = &ldo_2_volts[0], + .vsel_reg = BD718XX_REG_LDO2_VOLT, +@@ -950,7 +1119,7 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { + .of_match = of_match_ptr("LDO3"), + .regulators_node = of_match_ptr("regulators"), + .id = BD718XX_LDO3, +- .ops = &bd718xx_ldo_regulator_ops, ++ .ops = &bd71837_ldo_regulator_ops, + .type = REGULATOR_VOLTAGE, + .n_voltages = BD718XX_LDO3_VOLTAGE_NUM, + .linear_ranges = bd718xx_ldo3_volts, +@@ -973,7 +1142,7 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { + .of_match = of_match_ptr("LDO4"), + .regulators_node = of_match_ptr("regulators"), + .id = BD718XX_LDO4, +- .ops = &bd718xx_ldo_regulator_ops, ++ .ops = &bd71837_ldo_regulator_ops, + .type = REGULATOR_VOLTAGE, + .n_voltages = BD718XX_LDO4_VOLTAGE_NUM, + .linear_ranges = bd718xx_ldo4_volts, +@@ -996,7 +1165,7 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { + .of_match = of_match_ptr("LDO5"), + .regulators_node = of_match_ptr("regulators"), + .id = BD718XX_LDO5, +- .ops = &bd718xx_ldo_regulator_ops, ++ .ops = &bd71837_ldo_regulator_ops, + .type = REGULATOR_VOLTAGE, + .n_voltages = BD71837_LDO5_VOLTAGE_NUM, + .linear_ranges = bd71837_ldo5_volts, +@@ -1023,7 +1192,7 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { + .of_match = of_match_ptr("LDO6"), + .regulators_node = of_match_ptr("regulators"), + .id = BD718XX_LDO6, +- .ops = &bd718xx_ldo_regulator_ops, ++ .ops = &bd71837_ldo_regulator_ops, + .type = REGULATOR_VOLTAGE, + .n_voltages = BD718XX_LDO6_VOLTAGE_NUM, + .linear_ranges = bd718xx_ldo6_volts, +@@ -1050,7 +1219,7 @@ static const struct bd718xx_regulator_data bd71837_regulators[] = { + .of_match = of_match_ptr("LDO7"), + .regulators_node = of_match_ptr("regulators"), + .id = BD718XX_LDO7, +- .ops = &bd718xx_ldo_regulator_ops, ++ .ops = &bd71837_ldo_regulator_ops, + .type = REGULATOR_VOLTAGE, + .n_voltages = BD71837_LDO7_VOLTAGE_NUM, + .linear_ranges = bd71837_ldo7_volts, +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0006-arm64-dts-freescale-add-initial-support-for-Google-i.patch b/recipes-kernel/linux/linux-coral-5.4/0006-arm64-dts-freescale-add-initial-support-for-Google-i.patch new file mode 100644 index 0000000..3ed3fc8 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0006-arm64-dts-freescale-add-initial-support-for-Google-i.patch @@ -0,0 +1,428 @@ +From ca22043e293c06fb9ec120304e963047c49c7ece Mon Sep 17 00:00:00 2001 +From: Marco Antonio Franchi +Date: Tue, 17 Dec 2019 13:36:17 +0000 +Subject: [PATCH 06/21] arm64: dts: freescale: add initial support for Google + i.MX 8MQ Phanbell + +This patch adds the device tree to support Google Coral Edge TPU, +historicaly named as fsl-imx8mq-phanbell, a computer on module +which can be used for AI/ML propose. + +It introduces a minimal enablement support for this module and +was totally based on the NXP i.MX 8MQ EVK board and i.MX 8MQ Phanbell +Google Source Code for Coral Edge TPU Mendel release: +https://coral.googlesource.com/linux-imx/ + +Tested components: +- PMIC; +- USB-C OTG; +- USB-C PWR; +- micro-USB; +- USB. + +Signed-off-by: Marco Franchi +Reviewed-by: Fabio Estevam +Signed-off-by: Shawn Guo +--- + arch/arm64/boot/dts/freescale/Makefile | 1 + + .../boot/dts/freescale/imx8mq-phanbell.dts | 376 ++++++++++++++++++ + 2 files changed, 377 insertions(+) + create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts + +diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile +index d5eb439fe4a6..fafdad5368ff 100644 +--- a/arch/arm64/boot/dts/freescale/Makefile ++++ b/arch/arm64/boot/dts/freescale/Makefile +@@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dp.dtb ++dtb-$(CONFIG_ARCH_MXC) += imx8mq-phanbell.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mq-ddr3l-val.dtb imx8mq-ddr4-val.dtb imx8mq-ddr4-val-gpmi-nand.dtb +diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +new file mode 100644 +index 000000000000..3f2a489a4ad8 +--- /dev/null ++++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +@@ -0,0 +1,376 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright 2017-2019 NXP ++ */ ++ ++/dts-v1/; ++ ++#include "imx8mq.dtsi" ++ ++/ { ++ model = "Google i.MX8MQ Phanbell"; ++ compatible = "google,imx8mq-phanbell", "fsl,imx8mq"; ++ ++ chosen { ++ stdout-path = &uart1; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x00000000 0x40000000 0 0x40000000>; ++ }; ++ ++ pmic_osc: clock-pmic { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ clock-output-names = "pmic_osc"; ++ }; ++ ++ reg_usdhc2_vmmc: regulator-usdhc2-vmmc { ++ compatible = "regulator-fixed"; ++ regulator-name = "VSD_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++}; ++ ++&A53_0 { ++ cpu-supply = <&buck2>; ++}; ++ ++&A53_1 { ++ cpu-supply = <&buck2>; ++}; ++ ++&A53_2 { ++ cpu-supply = <&buck2>; ++}; ++ ++&A53_3 { ++ cpu-supply = <&buck2>; ++}; ++ ++&i2c1 { ++ clock-frequency = <400000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1>; ++ status = "okay"; ++ ++ pmic: pmic@4b { ++ compatible = "rohm,bd71837"; ++ reg = <0x4b>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pmic>; ++ #clock-cells = <0>; ++ clocks = <&pmic_osc>; ++ clock-output-names = "pmic_clk"; ++ interrupt-parent = <&gpio1>; ++ interrupts = <3 GPIO_ACTIVE_LOW>; ++ ++ regulators { ++ buck1: BUCK1 { ++ regulator-name = "buck1"; ++ regulator-min-microvolt = <700000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-ramp-delay = <1250>; ++ rohm,dvs-run-voltage = <900000>; ++ rohm,dvs-idle-voltage = <900000>; ++ rohm,dvs-suspend-voltage = <800000>; ++ }; ++ ++ buck2: BUCK2 { ++ regulator-name = "buck2"; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ rohm,dvs-run-voltage = <1000000>; ++ rohm,dvs-idle-voltage = <900000>; ++ }; ++ ++ buck3: BUCK3 { ++ regulator-name = "buck3"; ++ regulator-min-microvolt = <700000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-boot-on; ++ rohm,dvs-run-voltage = <900000>; ++ }; ++ ++ buck4: BUCK4 { ++ regulator-name = "buck4"; ++ regulator-min-microvolt = <700000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ rohm,dvs-run-voltage = <900000>; ++ }; ++ ++ buck5: BUCK5 { ++ regulator-name = "buck5"; ++ regulator-min-microvolt = <700000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ buck6: BUCK6 { ++ regulator-name = "buck6"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ buck7: BUCK7 { ++ regulator-name = "buck7"; ++ regulator-min-microvolt = <1605000>; ++ regulator-max-microvolt = <1995000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ buck8: BUCK8 { ++ regulator-name = "buck8"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo1: LDO1 { ++ regulator-name = "ldo1"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo2: LDO2 { ++ regulator-name = "ldo2"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo3: LDO3 { ++ regulator-name = "ldo3"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo4: LDO4 { ++ regulator-name = "ldo4"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo5: LDO5 { ++ regulator-name = "ldo5"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo6: LDO6 { ++ regulator-name = "ldo6"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo7: LDO7 { ++ regulator-name = "ldo7"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ }; ++ }; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1>; ++ status = "okay"; ++}; ++ ++&usdhc1 { ++ pinctrl-names = "default", "state_100mhz", "state_200mhz"; ++ pinctrl-0 = <&pinctrl_usdhc1>; ++ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; ++ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&usdhc2 { ++ pinctrl-names = "default", "state_100mhz", "state_200mhz"; ++ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; ++ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; ++ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; ++ bus-width = <4>; ++ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; ++ vmmc-supply = <®_usdhc2_vmmc>; ++ status = "okay"; ++}; ++ ++&usb3_phy0 { ++ status = "okay"; ++}; ++ ++&usb_dwc3_0 { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&usb3_phy1 { ++ status = "okay"; ++}; ++ ++&usb_dwc3_1 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&wdog1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_wdog>; ++ fsl,ext-reset-output; ++ status = "okay"; ++}; ++ ++&iomuxc { ++ pinctrl_i2c1: i2c1grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f ++ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f ++ >; ++ }; ++ ++ pinctrl_pmic: pmicirq { ++ fsl,pins = < ++ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 ++ >; ++ }; ++ ++ pinctrl_uart1: uart1grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 ++ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 ++ >; ++ }; ++ ++ pinctrl_usdhc1: usdhc1grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 ++ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 ++ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 ++ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 ++ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 ++ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 ++ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 ++ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 ++ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 ++ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 ++ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 ++ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 ++ >; ++ }; ++ ++ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { ++ fsl,pins = < ++ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 ++ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 ++ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 ++ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 ++ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 ++ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 ++ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 ++ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 ++ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 ++ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 ++ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 ++ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 ++ >; ++ }; ++ ++ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { ++ fsl,pins = < ++ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 ++ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 ++ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 ++ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 ++ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 ++ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 ++ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 ++ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 ++ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 ++ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 ++ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 ++ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 ++ >; ++ }; ++ ++ pinctrl_usdhc2_gpio: usdhc2grpgpio { ++ fsl,pins = < ++ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 ++ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 ++ >; ++ }; ++ ++ pinctrl_usdhc2: usdhc2grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 ++ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 ++ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 ++ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 ++ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 ++ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 ++ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 ++ >; ++ }; ++ ++ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { ++ fsl,pins = < ++ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 ++ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 ++ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 ++ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 ++ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 ++ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 ++ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 ++ >; ++ }; ++ ++ pinctrl_usdhc2_200mhz: usdhc2grp200mhz { ++ fsl,pins = < ++ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 ++ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 ++ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 ++ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 ++ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 ++ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 ++ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 ++ >; ++ }; ++ ++ pinctrl_wdog: wdoggrp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 ++ >; ++ }; ++}; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0007-arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch b/recipes-kernel/linux/linux-coral-5.4/0007-arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch new file mode 100644 index 0000000..0c53da5 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0007-arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch @@ -0,0 +1,76 @@ +From 9cf62eac95c7392a0075722c1bf5cdbfdd4393e4 Mon Sep 17 00:00:00 2001 +From: Alifer Moraes +Date: Tue, 11 Feb 2020 10:48:28 -0300 +Subject: [PATCH 07/21] arm64: dts: imx8mq-phanbell: Add support for ethernet + +Add support for ethernet on Google's i.MX 8MQ Phanbell + +Signed-off-by: Alifer Moraes +Tested-by: Vitor Massaru Iha +Signed-off-by: Shawn Guo +--- + .../boot/dts/freescale/imx8mq-phanbell.dts | 41 +++++++++++++++++++ + 1 file changed, 41 insertions(+) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +index 3f2a489a4ad8..16ed13c44a47 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +@@ -201,6 +201,27 @@ + }; + }; + ++&fec1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_fec1>; ++ phy-mode = "rgmii-id"; ++ phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; ++ phy-reset-duration = <10>; ++ phy-reset-post-delay = <30>; ++ phy-handle = <ðphy0>; ++ fsl,magic-packet; ++ status = "okay"; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ethphy0: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ }; ++ }; ++}; ++ + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +@@ -254,6 +275,26 @@ + }; + + &iomuxc { ++ pinctrl_fec1: fec1grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 ++ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 ++ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f ++ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f ++ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f ++ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f ++ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 ++ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 ++ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 ++ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 ++ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f ++ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 ++ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 ++ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f ++ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 ++ >; ++ }; ++ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0008-arm64-dts-imx8mq-phanbell-Add-gpio-fan-thermal-suppo.patch b/recipes-kernel/linux/linux-coral-5.4/0008-arm64-dts-imx8mq-phanbell-Add-gpio-fan-thermal-suppo.patch new file mode 100644 index 0000000..5bcab96 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0008-arm64-dts-imx8mq-phanbell-Add-gpio-fan-thermal-suppo.patch @@ -0,0 +1,124 @@ +From ee0824e83cf33f393a716fb5d93e877b9e430dd2 Mon Sep 17 00:00:00 2001 +From: Vitor Massaru Iha +Date: Mon, 2 Mar 2020 22:15:16 -0300 +Subject: [PATCH 08/21] arm64: dts: imx8mq-phanbell: Add gpio-fan/thermal + support + +It was based on Google Source Code for Coral Edge TPU Mendel release: +https://coral.googlesource.com/linux-imx/ + +It was tested on Coral Dev Board using this command: + sudo stress --cpu 4 --timeout 3600 + +Signed-off-by: Vitor Massaru Iha +Reviewed-by: Fabio Estevam +Signed-off-by: Shawn Guo +--- + .../boot/dts/freescale/imx8mq-phanbell.dts | 63 +++++++++++++++++++ + arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +- + 2 files changed, 64 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +index 16ed13c44a47..1a04d01acc18 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +@@ -35,6 +35,16 @@ + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; ++ ++ fan: gpio-fan { ++ compatible = "gpio-fan"; ++ gpio-fan,speed-map = <0 0 8600 1>; ++ gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; ++ #cooling-cells = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpio_fan>; ++ status = "okay"; ++ }; + }; + + &A53_0 { +@@ -53,6 +63,53 @@ + cpu-supply = <&buck2>; + }; + ++&cpu_thermal { ++ trips { ++ cpu_alert0: trip0 { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_alert1: trip1 { ++ temperature = <80000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_crit0: trip3 { ++ temperature = <90000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ fan_toggle0: trip4 { ++ temperature = <65000>; ++ hysteresis = <10000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_alert0>; ++ cooling-device = ++ <&A53_0 0 1>; /* Exclude highest OPP */ ++ }; ++ ++ map1 { ++ trip = <&cpu_alert1>; ++ cooling-device = ++ <&A53_0 0 2>; /* Exclude two highest OPPs */ ++ }; ++ ++ map4 { ++ trip = <&fan_toggle0>; ++ cooling-device = <&fan 0 1>; ++ }; ++ }; ++}; ++ + &i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; +@@ -295,6 +352,12 @@ + >; + }; + ++ pinctrl_gpio_fan: gpiofangrp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16 ++ >; ++ }; ++ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f +diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi +index b628a5369653..041ead56beea 100755 +--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi ++++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi +@@ -222,7 +222,7 @@ + }; + + thermal-zones { +- cpu-thermal { ++ cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0>; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0009-arm64-dts-imx8mq-phanbell-Fix-Ethernet-PHY-post-rese.patch b/recipes-kernel/linux/linux-coral-5.4/0009-arm64-dts-imx8mq-phanbell-Fix-Ethernet-PHY-post-rese.patch new file mode 100644 index 0000000..d9618e4 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0009-arm64-dts-imx8mq-phanbell-Fix-Ethernet-PHY-post-rese.patch @@ -0,0 +1,32 @@ +From f1eacbecb579c548724704c740848da19dffc5b6 Mon Sep 17 00:00:00 2001 +From: Alifer Moraes +Date: Fri, 6 Mar 2020 07:42:19 -0300 +Subject: [PATCH 09/21] arm64: dts: imx8mq-phanbell: Fix Ethernet PHY + post-reset duration + +i.MX8MQ Phanbell board uses Realtek RTL8211FD as Ethernet PHY. +Its datasheet states that the proper post reset duration should be at least 50 ms. + +Fixes: f34d4bfab354 ("arm64: dts: imx8mq-phanbell: Add support for ethernet") +Signed-off-by: Alifer Moraes +Signed-off-by: Shawn Guo +--- + arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +index 1a04d01acc18..77ab568fae67 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +@@ -264,7 +264,7 @@ + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; +- phy-reset-post-delay = <30>; ++ phy-reset-post-delay = <50>; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0010-arm64-dts-imx8mq-phanbell-Replace-deprecated-phy-res.patch b/recipes-kernel/linux/linux-coral-5.4/0010-arm64-dts-imx8mq-phanbell-Replace-deprecated-phy-res.patch new file mode 100644 index 0000000..3c9efd3 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0010-arm64-dts-imx8mq-phanbell-Replace-deprecated-phy-res.patch @@ -0,0 +1,43 @@ +From 5df89084e49729eafa4eb8b7833674668086cf15 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Sun, 23 Aug 2020 13:15:06 +0200 +Subject: [PATCH 10/21] arm64: dts: imx8mq-phanbell: Replace deprecated phy + reset properties + +Use preferred properties of phy node instead of deprecated +phy-reset-gpios (and others). This avoids copying deprecated code into +future DTSes. + +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Shawn Guo +--- + arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +index 77ab568fae67..3f541ddf0768 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +@@ -262,9 +262,6 @@ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; +- phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; +- phy-reset-duration = <10>; +- phy-reset-post-delay = <50>; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; +@@ -275,6 +272,9 @@ + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; ++ reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; + }; + }; + }; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0011-arm64-dts-imx8mq-phanbell-Align-pin-configuration-gr.patch b/recipes-kernel/linux/linux-coral-5.4/0011-arm64-dts-imx8mq-phanbell-Align-pin-configuration-gr.patch new file mode 100644 index 0000000..653d699 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0011-arm64-dts-imx8mq-phanbell-Align-pin-configuration-gr.patch @@ -0,0 +1,78 @@ +From d7cc3d71a65a2f611efb98ed0c39f85b3d5263f6 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Fri, 28 Aug 2020 18:47:46 +0200 +Subject: [PATCH 11/21] arm64: dts: imx8mq-phanbell: Align pin configuration + group names with schema + +Device tree schema expects pin configuration groups to end with 'grp' +suffix, otherwise dtbs_check complain with a warning like: + + ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' + +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Shawn Guo +--- + arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +index 3f541ddf0768..d6d3a3d5abc3 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +@@ -365,7 +365,7 @@ + >; + }; + +- pinctrl_pmic: pmicirq { ++ pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; +@@ -395,7 +395,7 @@ + >; + }; + +- pinctrl_usdhc1_100mhz: usdhc1grp100mhz { ++ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 +@@ -412,7 +412,7 @@ + >; + }; + +- pinctrl_usdhc1_200mhz: usdhc1grp200mhz { ++ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 +@@ -429,7 +429,7 @@ + >; + }; + +- pinctrl_usdhc2_gpio: usdhc2grpgpio { ++ pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 +@@ -448,7 +448,7 @@ + >; + }; + +- pinctrl_usdhc2_100mhz: usdhc2grp100mhz { ++ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 +@@ -460,7 +460,7 @@ + >; + }; + +- pinctrl_usdhc2_200mhz: usdhc2grp200mhz { ++ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0012-arm64-dts-imx8mq-phanbell-Disable-busfreq-to-avoid-s.patch b/recipes-kernel/linux/linux-coral-5.4/0012-arm64-dts-imx8mq-phanbell-Disable-busfreq-to-avoid-s.patch new file mode 100644 index 0000000..26e62f3 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0012-arm64-dts-imx8mq-phanbell-Disable-busfreq-to-avoid-s.patch @@ -0,0 +1,32 @@ +From 8d652338e1944cafff83e1470b64ebd6232b577c Mon Sep 17 00:00:00 2001 +From: Ryosuke Saito +Date: Thu, 22 Oct 2020 21:44:02 +0900 +Subject: [PATCH 12/21] arm64: dts: imx8mq-phanbell: Disable busfreq to avoid + system hang + +Avoid system hang on boot by disabling busfreq driver for i.MX8MQ +Phanbell board. + +Signed-off-by: Ryosuke Saito +--- + arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +index d6d3a3d5abc3..dc0270787f7b 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +@@ -20,6 +20,10 @@ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + ++ busfreq { ++ status = "disabled"; ++ }; ++ + pmic_osc: clock-pmic { + compatible = "fixed-clock"; + #clock-cells = <0>; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0013-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch b/recipes-kernel/linux/linux-coral-5.4/0013-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch new file mode 100644 index 0000000..f15cef2 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0013-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch @@ -0,0 +1,33 @@ +From e645d6b386a83843a36608ba3be7f864dfc06a91 Mon Sep 17 00:00:00 2001 +From: Richard Zhu +Date: Wed, 21 Jun 2017 10:23:00 +0800 +Subject: [PATCH 13/21] MLK-15307-2 clk: imx8mq: set the parent clocks of PCIE + +Configure the parent clocks of PCIE. + +Signed-off-by: Richard Zhu +Signed-off-by: Ryosuke Saito +--- + drivers/clk/imx/clk-imx8mq.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c +index f8aaed0712f2..7f7faa6cd9f9 100644 +--- a/drivers/clk/imx/clk-imx8mq.c ++++ b/drivers/clk/imx/clk-imx8mq.c +@@ -612,6 +612,12 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) + /* enable all the clocks just for bringup */ + imx_clk_init_on(np, clks); + ++ /* set pcie root's parent clk source */ ++ clk_set_parent(clks[IMX8MQ_CLK_PCIE1_CTRL], clks[IMX8MQ_SYS2_PLL_250M]); ++ clk_set_parent(clks[IMX8MQ_CLK_PCIE1_PHY], clks[IMX8MQ_SYS2_PLL_100M]); ++ clk_set_parent(clks[IMX8MQ_CLK_PCIE2_CTRL], clks[IMX8MQ_SYS2_PLL_250M]); ++ clk_set_parent(clks[IMX8MQ_CLK_PCIE2_PHY], clks[IMX8MQ_SYS2_PLL_100M]); ++ + clk_set_parent(clks[IMX8MQ_CLK_CSI1_CORE], clks[IMX8MQ_SYS1_PLL_266M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI1_PHY_REF], clks[IMX8MQ_SYS2_PLL_1000M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI1_ESC], clks[IMX8MQ_SYS1_PLL_800M]); +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0014-arm64-dts-imx8mq-Set-ext_osc-to-1-as-default.patch b/recipes-kernel/linux/linux-coral-5.4/0014-arm64-dts-imx8mq-Set-ext_osc-to-1-as-default.patch new file mode 100644 index 0000000..78d8bc5 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0014-arm64-dts-imx8mq-Set-ext_osc-to-1-as-default.patch @@ -0,0 +1,54 @@ +From 02b389837fff9bee4a0221513e7185277fa4ca92 Mon Sep 17 00:00:00 2001 +From: Ryosuke Saito +Date: Mon, 9 Nov 2020 21:18:54 +0900 +Subject: [PATCH] arm64: dts: imx8mq: Set ext_osc to 1 as default + +Currently, imx8mq PCIe driver codes assume that the external clock +generator is always used but e.g. imx8mq-phanbell board is an exception. +Such boards have to be configured with the internal PLL as PCIe REF +clock. + +Since there are many dts files which include imx8mq.dtsi without ext_osc +set properly and use the external clock implicitly, instead of modifying +all such dts files, set the default value of ext_osc to 1 to change the +driver's behavior and be able for such exceptional boards to override it +easily. + +This is not ideal though, makes fewer future conflicts for now. + +Signed-off-by: Ryosuke Saito +--- + arch/arm64/boot/dts/freescale/imx8mq.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi +index d53b658c736e..31d6dddbf50b 100755 +--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi ++++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi +@@ -1454,6 +1454,7 @@ + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; ++ ext_osc = <1>; + status = "disabled"; + }; + +@@ -1485,6 +1486,7 @@ + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "clkreq", "turnoff"; ++ ext_osc = <1>; + status = "disabled"; + }; + +@@ -1512,6 +1514,7 @@ + <10000000>; + num-ib-windows = <4>; + num-ob-windows = <4>; ++ ext_osc = <1>; + status = "disabled"; + }; + +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0015-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch b/recipes-kernel/linux/linux-coral-5.4/0015-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch new file mode 100644 index 0000000..3ad7722 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0015-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch @@ -0,0 +1,43 @@ +From f933537c63c6140707b96463f0573bd75f9a3b23 Mon Sep 17 00:00:00 2001 +From: Ryosuke Saito +Date: Sun, 15 Nov 2020 22:39:01 +0900 +Subject: [PATCH] PCI: imx: Use the external clock as REF_CLK when needed for + i.MX8MQ + +Do not use the external clock when the internal PLL is used as PCIe +REF_CLK. + +Signed-off-by: Ryosuke Saito +--- + drivers/pci/controller/dwc/pci-imx6.c | 15 +++++++-------- + 1 file changed, 7 insertions(+), 8 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c +index 1eed334db638..16844df2dfab 100644 +--- a/drivers/pci/controller/dwc/pci-imx6.c ++++ b/drivers/pci/controller/dwc/pci-imx6.c +@@ -1595,14 +1595,13 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) + break; + case IMX8MQ: + case IMX8MQ_EP: +- /* +- * TODO: Currently this code assumes external +- * oscillator is being used +- */ +- regmap_update_bits(imx6_pcie->iomuxc_gpr, +- imx6_pcie_grp_offset(imx6_pcie), +- IMX8MQ_GPR_PCIE_REF_USE_PAD, +- IMX8MQ_GPR_PCIE_REF_USE_PAD); ++ if (imx6_pcie->ext_osc) { ++ /* Use the external oscillator as REF clock */ ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, ++ imx6_pcie_grp_offset(imx6_pcie), ++ IMX8MQ_GPR_PCIE_REF_USE_PAD, ++ IMX8MQ_GPR_PCIE_REF_USE_PAD); ++ } + /* + * Regarding to the datasheet, the PCIE_VPH is suggested + * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0016-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch b/recipes-kernel/linux/linux-coral-5.4/0016-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch new file mode 100644 index 0000000..616b044 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0016-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch @@ -0,0 +1,70 @@ +From a38acdc9ca4548e7d6afad9bde51a6cd6d2de619 Mon Sep 17 00:00:00 2001 +From: Ryosuke Saito +Date: Sun, 15 Nov 2020 22:45:53 +0900 +Subject: [PATCH] PCI: imx: Provide a clock to the device for i.MX8MQ + +When the internal PLL is configured as PCIe REF_CLK, we also have to +output a clock via CLK2_P/N pin to the connector/device to provide it. +Configure 100 MHz clock as its output. + +Signed-off-by: Ryosuke Saito +--- + drivers/pci/controller/dwc/pci-imx6.c | 35 +++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c +index 16844df2dfab..650f54b97929 100644 +--- a/drivers/pci/controller/dwc/pci-imx6.c ++++ b/drivers/pci/controller/dwc/pci-imx6.c +@@ -290,6 +290,12 @@ struct imx6_pcie { + #define IMX8MM_GPR_PCIE_POWER_OFF BIT(17) + #define IMX8MM_GPR_PCIE_SSC_EN BIT(16) + ++#define IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG 0x74 ++#define IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK GENMASK(3, 0) ++#define IMX8MQ_ANA_PLLOUT_MONITOR_CKE BIT(4) ++#define IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG 0x7C ++#define IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK GENMASK(2, 0) ++ + static void imx6_pcie_ltssm_disable(struct device *dev); + + static bool imx6_pcie_readable_reg(struct device *dev, unsigned int reg) +@@ -1601,6 +1607,35 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) + imx6_pcie_grp_offset(imx6_pcie), + IMX8MQ_GPR_PCIE_REF_USE_PAD, + IMX8MQ_GPR_PCIE_REF_USE_PAD); ++ } else { ++ /* ++ * Use the internal PLL as REF clock and also ++ * provide a clock to the device. ++ */ ++ struct regmap *anatop = ++ syscon_regmap_lookup_by_compatible("fsl,imx8mq-anatop"); ++ ++ if (IS_ERR(anatop)) { ++ dev_err(imx6_pcie->pci->dev, ++ "Couldn't configure the internal PLL as REF clock\n"); ++ break; ++ } ++ ++ /* Select SYSTEM_PLL1_CLK as the clock source */ ++ regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG, ++ IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK, 0xb); ++ ++ /* ++ * SYSTEM_PLL1_CLK is 800 MHz, so divided by 8 ++ * for generating 100 MHz as output. ++ */ ++ regmap_update_bits(anatop, IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG, ++ IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK, 0x7); ++ ++ /* Enable CLK2_P/N clock to provide it to the device */ ++ regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG, ++ IMX8MQ_ANA_PLLOUT_MONITOR_CKE, ++ IMX8MQ_ANA_PLLOUT_MONITOR_CKE); + } + /* + * Regarding to the datasheet, the PCIE_VPH is suggested +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0017-arm64-dts-imx8mq-phanbell-Enable-PCIe.patch b/recipes-kernel/linux/linux-coral-5.4/0017-arm64-dts-imx8mq-phanbell-Enable-PCIe.patch new file mode 100644 index 0000000..8fa6299 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0017-arm64-dts-imx8mq-phanbell-Enable-PCIe.patch @@ -0,0 +1,127 @@ +From 300fb8ccf767c216e262cfc8e6efab2cce7e9b13 Mon Sep 17 00:00:00 2001 +From: Ryosuke Saito +Date: Thu, 5 Nov 2020 22:55:47 +0900 +Subject: [PATCH 17/21] arm64: dts: imx8mq-phanbell: Enable PCIe + +Add suport for PCIe. + +Signed-off-by: Ryosuke Saito +--- + .../boot/dts/freescale/imx8mq-phanbell.dts | 75 +++++++++++++++++++ + 1 file changed, 75 insertions(+) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +index dc0270787f7b..d2a261ebb8e2 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +@@ -49,6 +49,12 @@ + pinctrl-0 = <&pinctrl_gpio_fan>; + status = "okay"; + }; ++ ++ pcie1_refclk: pcie1-refclk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <100000000>; ++ }; + }; + + &A53_0 { +@@ -114,6 +120,17 @@ + }; + }; + ++&gpio3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_wifi_reset>; ++ ++ wl-reg-on { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ }; ++}; ++ + &i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; +@@ -262,6 +279,35 @@ + }; + }; + ++&pcie0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pcie0>; ++ reset-gpio = <&gpio3 10 GPIO_ACTIVE_LOW>; ++ clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, ++ <&clk IMX8MQ_CLK_PCIE1_AUX>, ++ <&clk IMX8MQ_CLK_PCIE1_PHY>, ++ <&clk IMX8MQ_CLK_DUMMY>; ++ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; ++ fsl,max-link-speed = <1>; ++ ext_osc = <0>; ++ hard-wired = <1>; ++ status = "okay"; ++}; ++ ++&pcie1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pcie1>; ++ reset-gpio = <&gpio3 18 GPIO_ACTIVE_LOW>; ++ clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, ++ <&clk IMX8MQ_CLK_PCIE2_AUX>, ++ <&clk IMX8MQ_CLK_PCIE2_PHY>, ++ <&pcie1_refclk>; ++ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; ++ ext_osc = <1>; ++ hard-wired = <1>; ++ status = "okay"; ++}; ++ + &fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; +@@ -336,6 +382,29 @@ + }; + + &iomuxc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hog>; ++ ++ pinctrl_hog: hoggrp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x05 ++ >; ++ }; ++ ++ pinctrl_pcie0: pcie0grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 ++ MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x16 ++ >; ++ }; ++ ++ pinctrl_pcie1: pcie1grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 ++ MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 ++ >; ++ }; ++ + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +@@ -481,4 +550,10 @@ + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; ++ ++ pinctrl_wifi_reset: wifiresetgrp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 ++ >; ++ }; + }; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0018-spi-spi-imx-Revive-cs-gpios-property-for-DT.patch b/recipes-kernel/linux/linux-coral-5.4/0018-spi-spi-imx-Revive-cs-gpios-property-for-DT.patch new file mode 100644 index 0000000..22c425c --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0018-spi-spi-imx-Revive-cs-gpios-property-for-DT.patch @@ -0,0 +1,46 @@ +From 62ac8479d1a70e2c0ef04a06936e47987f04b180 Mon Sep 17 00:00:00 2001 +From: Ryosuke Saito +Date: Sat, 2 Jan 2021 19:49:34 +0900 +Subject: [PATCH 18/21] spi: spi-imx: Revive cs-gpios property for DT + +The commit 881a0b993e9f ("spi: imx: GPIO based chip selects should not +be required") completely removed the 'cs-gpios' property from DT, but +still, one might require SS/CS lines to be configured as GPIO for some +good reason (e.g., restriction of board I/O pin assignment). +For that, let's revive the property again. + +Signed-off-by: Ryosuke Saito +--- + drivers/spi/spi-imx.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c +index 91e32291c44e..4b0492bd0e00 100644 +--- a/drivers/spi/spi-imx.c ++++ b/drivers/spi/spi-imx.c +@@ -1685,6 +1685,22 @@ static int spi_imx_probe(struct platform_device *pdev) + if (!of_property_read_u32(np, "num-cs", &num_cs)) + master->num_chipselect = num_cs; + /* If not preset, default value of 1 is used */ ++ ++ if (of_find_property(np, "cs-gpios", NULL)) { ++ master->cs_gpios = devm_kcalloc(&master->dev, ++ master->num_chipselect, ++ sizeof(int), GFP_KERNEL); ++ if (!master->cs_gpios) ++ return -ENOMEM; ++ ++ for (i = 0; i < master->num_chipselect; i++) { ++ ret = of_get_named_gpio(np, "cs-gpios", i); ++ if (ret < 0) ++ goto out_master_put; ++ ++ master->cs_gpios[i] = ret; ++ } ++ } + } + + spi_imx->bitbang.chipselect = spi_imx_chipselect; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0019-arm64-dts-imx8mq-phanbell-Enable-ECSPI1.patch b/recipes-kernel/linux/linux-coral-5.4/0019-arm64-dts-imx8mq-phanbell-Enable-ECSPI1.patch new file mode 100644 index 0000000..3cff598 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0019-arm64-dts-imx8mq-phanbell-Enable-ECSPI1.patch @@ -0,0 +1,69 @@ +From 40a8007cb59fefd4fc83c003742cf12cfae607ba Mon Sep 17 00:00:00 2001 +From: Ryosuke Saito +Date: Sat, 2 Jan 2021 19:55:05 +0900 +Subject: [PATCH 19/21] arm64: dts: imx8mq-phanbell: Enable ECSPI1 + +Add ecspi1 enabled with two spidev devices. + +Signed-off-by: Ryosuke Saito +--- + .../boot/dts/freescale/imx8mq-phanbell.dts | 36 +++++++++++++++++++ + 1 file changed, 36 insertions(+) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +index d2a261ebb8e2..386ef06d698d 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +@@ -308,6 +308,27 @@ + status = "okay"; + }; + ++&ecspi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; ++ cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>, ++ <&gpio3 2 GPIO_ACTIVE_HIGH>; ++ num-cs = <2>; ++ status = "okay"; ++ ++ spidev@0 { ++ compatible = "rohm,dh2228fv"; ++ spi-max-frequency = <20000000>; ++ reg = <0>; ++ }; ++ ++ spidev@1 { ++ compatible = "rohm,dh2228fv"; ++ spi-max-frequency = <20000000>; ++ reg = <1>; ++ }; ++}; ++ + &fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; +@@ -405,6 +426,21 @@ + >; + }; + ++ pinctrl_ecspi1: ecspi1grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 ++ MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 ++ MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 ++ >; ++ }; ++ ++ pinctrl_ecspi1_cs: ecspi1_cs_grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x82 ++ MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x82 ++ >; ++ }; ++ + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0020-arm64-dts-imx8mq-phanbell-Add-gpio-pinmux-for-40-pin.patch b/recipes-kernel/linux/linux-coral-5.4/0020-arm64-dts-imx8mq-phanbell-Add-gpio-pinmux-for-40-pin.patch new file mode 100644 index 0000000..07750ca --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0020-arm64-dts-imx8mq-phanbell-Add-gpio-pinmux-for-40-pin.patch @@ -0,0 +1,37 @@ +From 71e58a267131a7ca719c647c7ec2be002010d5c6 Mon Sep 17 00:00:00 2001 +From: Ryosuke Saito +Date: Sat, 2 Jan 2021 19:56:43 +0900 +Subject: [PATCH 20/21] arm64: dts: imx8mq-phanbell: Add gpio pinmux for 40-pin + header + +Add gpio pinmux for the 40-pin expansion header on the board. + +Signed-off-by: Ryosuke Saito +--- + arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +index 386ef06d698d..47c55e986da0 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +@@ -409,6 +409,16 @@ + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x05 ++ MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 ++ MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 ++ MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 ++ MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 ++ MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x19 ++ MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 ++ MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 ++ MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 ++ MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x19 ++ MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 + >; + }; + +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral-5.4/0021-arm64-dts-imx8mq-phanbell-Enable-I2C-2-I2C-3.patch b/recipes-kernel/linux/linux-coral-5.4/0021-arm64-dts-imx8mq-phanbell-Enable-I2C-2-I2C-3.patch new file mode 100644 index 0000000..695c283 --- /dev/null +++ b/recipes-kernel/linux/linux-coral-5.4/0021-arm64-dts-imx8mq-phanbell-Enable-I2C-2-I2C-3.patch @@ -0,0 +1,61 @@ +From 324a26744442949fab8aa9aeafe2bae25e9d5707 Mon Sep 17 00:00:00 2001 +From: Ryosuke Saito +Date: Fri, 23 Apr 2021 19:20:57 +0900 +Subject: [PATCH 21/21] arm64: dts: imx8mq-phanbell: Enable I2C-2/I2C-3 + +Enable I2C-2/I2C-3 which can be used through Dev Board 40-pin header. + +Signed-off-by: Ryosuke Saito +--- + .../boot/dts/freescale/imx8mq-phanbell.dts | 28 +++++++++++++++++++ + 1 file changed, 28 insertions(+) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +index 47c55e986da0..b50431ff5f33 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +@@ -279,6 +279,20 @@ + }; + }; + ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ status = "okay"; ++}; ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3>; ++ status = "okay"; ++}; ++ + &pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; +@@ -484,6 +498,20 @@ + >; + }; + ++ pinctrl_i2c2: i2c2grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f ++ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f ++ >; ++ }; ++ ++ pinctrl_i2c3: i2c3grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f ++ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f ++ >; ++ }; ++ + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-coral_4.14.bb b/recipes-kernel/linux/linux-coral_4.14.bb index 165f0dd..2fb31ab 100644 --- a/recipes-kernel/linux/linux-coral_4.14.bb +++ b/recipes-kernel/linux/linux-coral_4.14.bb @@ -14,17 +14,9 @@ SRC_URI = "\ file://0003-Compiler-Attributes-add-support-for-__copy-gcc-9.patch \ file://0004-Add-an-alias-for-imx8mq-phanbell.dts.patch \ file://defconfig \ + file://mendel.cfg \ file://extra.cfg \ " - -# As we use the 'defconfig' from Mendel OS (Debian) build scripts, we must also -# replicate the configure step to merge it. -do_configure:coral-dev() { - oe_runmake_call -C ${S} CC="${KERNEL_CC}" O=${B} defconfig - cat "${WORKDIR}/defconfig" | tee -a "${B}/.config" - oe_runmake_call -C ${S} CC="${KERNEL_CC}" O=${B} olddefconfig -} - KERNEL_EXTRA_ARGS += "LOADADDR=${UBOOT_ENTRYPOINT}" COMPATIBLE_MACHINE = "coral-dev" diff --git a/recipes-kernel/linux/linux-coral_5.4.bb b/recipes-kernel/linux/linux-coral_5.4.bb new file mode 100644 index 0000000..25058ea --- /dev/null +++ b/recipes-kernel/linux/linux-coral_5.4.bb @@ -0,0 +1,45 @@ +# Copyright (C) 2023 Khem Raj +require recipes-kernel/linux/linux-imx.inc + +LIC_FILES_CHKSUM = "file://COPYING;md5=bbea815ee2795b2f4230826c0c6b8814" + +SUMMARY = "Linux Kernel provided and supported by Google for Coral Dev Board" + +DEPENDS += "lzop-native bc-native" + +LINUX_VERSION = "5.4.210" + +FILESPATH =. "${FILE_DIRNAME}/${BPN}-5.4:" + +SRCREV = "f2663e3d184e8dc51cf925942ebbabecf8a29f17" +SRC_URI = "\ + git://github.com/Freescale/linux-fslc;protocol=https;branch=5.4-2.3.x-imx \ + file://extra.cfg \ + file://wifi.cfg \ + file://0001-regulator-bd718x7-Add-MODULE_ALIAS.patch \ + file://0002-regulator-bd718x7-Simplify-the-code-by-removing-stru.patch \ + file://0003-mfd-Rohm-PMICs-Use-platform_device_id-to-match-MFD-s.patch \ + file://0004-regulator-bd718x7-Split-driver-to-common-and-bd718x7.patch \ + file://0005-regulator-bd718x7-remove-voltage-change-restriction-.patch \ + file://0006-arm64-dts-freescale-add-initial-support-for-Google-i.patch \ + file://0007-arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch \ + file://0008-arm64-dts-imx8mq-phanbell-Add-gpio-fan-thermal-suppo.patch \ + file://0009-arm64-dts-imx8mq-phanbell-Fix-Ethernet-PHY-post-rese.patch \ + file://0010-arm64-dts-imx8mq-phanbell-Replace-deprecated-phy-res.patch \ + file://0011-arm64-dts-imx8mq-phanbell-Align-pin-configuration-gr.patch \ + file://0012-arm64-dts-imx8mq-phanbell-Disable-busfreq-to-avoid-s.patch \ + file://0013-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch \ + file://0014-arm64-dts-imx8mq-Set-ext_osc-to-1-as-default.patch \ + file://0015-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch \ + file://0016-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch \ + file://0017-arm64-dts-imx8mq-phanbell-Enable-PCIe.patch \ + file://0018-spi-spi-imx-Revive-cs-gpios-property-for-DT.patch \ + file://0019-arm64-dts-imx8mq-phanbell-Enable-ECSPI1.patch \ + file://0020-arm64-dts-imx8mq-phanbell-Add-gpio-pinmux-for-40-pin.patch \ + file://0021-arm64-dts-imx8mq-phanbell-Enable-I2C-2-I2C-3.patch \ +" +KERNEL_EXTRA_ARGS += "LOADADDR=${UBOOT_ENTRYPOINT}" + +OBJCOPY:toolchain-clang = "${HOST_PREFIX}objcopy" + +COMPATIBLE_MACHINE = "coral-dev" diff --git a/recipes-kernel/linux/linux-imx-5.15/0001-imx8mq-phanbell.dts-Enable-Coral-specifics-e.g.-PCIE.patch b/recipes-kernel/linux/linux-imx-5.15/0001-imx8mq-phanbell.dts-Enable-Coral-specifics-e.g.-PCIE.patch new file mode 100644 index 0000000..e582fb6 --- /dev/null +++ b/recipes-kernel/linux/linux-imx-5.15/0001-imx8mq-phanbell.dts-Enable-Coral-specifics-e.g.-PCIE.patch @@ -0,0 +1,226 @@ +From 2806bcdfbe52eeba6d09d3a952e270bdba4b8f19 Mon Sep 17 00:00:00 2001 +From: Khem Raj +Date: Tue, 7 Mar 2023 21:02:46 -0800 +Subject: [PATCH] imx8mq-phanbell.dts: Enable Coral specifics e.g. PCIE + +Signed-off-by: Khem Raj +--- + .../boot/dts/freescale/imx8mq-phanbell.dts | 155 +++++++++++++++++- + 1 file changed, 154 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +index a3b9d615a3b4..5ce4fc21443e 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +@@ -21,6 +21,10 @@ memory@40000000 { + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + ++ busfreq { ++ status = "disabled"; ++ }; ++ + pmic_osc: clock-pmic { + compatible = "fixed-clock"; + #clock-cells = <0>; +@@ -46,6 +50,12 @@ fan: gpio-fan { + pinctrl-0 = <&pinctrl_gpio_fan>; + status = "okay"; + }; ++ ++ pcie1_refclk: pcie1-refclk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <100000000>; ++ }; + }; + + &A53_0 { +@@ -111,6 +121,17 @@ map4 { + }; + }; + ++&gpio3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_wifi_reset>; ++ ++ wl-reg-on { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ }; ++}; ++ + &i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; +@@ -126,7 +147,7 @@ pmic: pmic@4b { + clocks = <&pmic_osc>; + clock-output-names = "pmic_clk"; + interrupt-parent = <&gpio1>; +- interrupts = <3 IRQ_TYPE_LEVEL_LOW>; ++ interrupts = <3 GPIO_ACTIVE_LOW>; + + regulators { + buck1: BUCK1 { +@@ -259,6 +280,70 @@ ldo7: LDO7 { + }; + }; + ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ status = "okay"; ++}; ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3>; ++ status = "okay"; ++}; ++ ++&pcie0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pcie0>; ++ reset-gpio = <&gpio3 10 GPIO_ACTIVE_LOW>; ++ clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, ++ <&clk IMX8MQ_CLK_PCIE1_AUX>, ++ <&clk IMX8MQ_CLK_PCIE1_PHY>, ++ <&clk IMX8MQ_CLK_DUMMY>; ++ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; ++ fsl,max-link-speed = <1>; ++ ext_osc = <0>; ++ hard-wired = <1>; ++ status = "okay"; ++}; ++ ++&pcie1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pcie1>; ++ reset-gpio = <&gpio3 18 GPIO_ACTIVE_LOW>; ++ clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, ++ <&clk IMX8MQ_CLK_PCIE2_AUX>, ++ <&clk IMX8MQ_CLK_PCIE2_PHY>, ++ <&pcie1_refclk>; ++ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; ++ ext_osc = <1>; ++ hard-wired = <1>; ++ status = "okay"; ++}; ++ ++&ecspi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; ++ cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>, ++ <&gpio3 2 GPIO_ACTIVE_HIGH>; ++ num-cs = <2>; ++ status = "okay"; ++ ++ spidev@0 { ++ compatible = "rohm,dh2228fv"; ++ spi-max-frequency = <20000000>; ++ reg = <0>; ++ }; ++ ++ spidev@1 { ++ compatible = "rohm,dh2228fv"; ++ spi-max-frequency = <20000000>; ++ reg = <1>; ++ }; ++}; ++ + &fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; +@@ -333,6 +418,54 @@ &wdog1 { + }; + + &iomuxc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hog>; ++ ++ pinctrl_hog: hoggrp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x05 ++ MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 ++ MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 ++ MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 ++ MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 ++ MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x19 ++ MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 ++ MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 ++ MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 ++ MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x19 ++ MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 ++ >; ++ }; ++ ++ pinctrl_pcie0: pcie0grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 ++ MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x16 ++ >; ++ }; ++ ++ pinctrl_pcie1: pcie1grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 ++ MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 ++ >; ++ }; ++ ++ pinctrl_ecspi1: ecspi1grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 ++ MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 ++ MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 ++ >; ++ }; ++ ++ pinctrl_ecspi1_cs: ecspi1_cs_grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x82 ++ MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x82 ++ >; ++ }; ++ + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 +@@ -366,6 +499,20 @@ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + ++ pinctrl_i2c2: i2c2grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f ++ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f ++ >; ++ }; ++ ++ pinctrl_i2c3: i2c3grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f ++ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f ++ >; ++ }; ++ + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 +@@ -478,4 +625,10 @@ pinctrl_wdog: wdoggrp { + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; ++ ++ pinctrl_wifi_reset: wifiresetgrp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 ++ >; ++ }; + }; +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-imx-5.15/0002-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch b/recipes-kernel/linux/linux-imx-5.15/0002-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch new file mode 100644 index 0000000..e3dbc7a --- /dev/null +++ b/recipes-kernel/linux/linux-imx-5.15/0002-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch @@ -0,0 +1,33 @@ +From aef5837a50af6adc53de4f907647cfd949912dba Mon Sep 17 00:00:00 2001 +From: Khem Raj +Date: Tue, 7 Mar 2023 21:13:29 -0800 +Subject: [PATCH 2/4] MLK-15307-2 clk: imx8mq: set the parent clocks of PCIE + +Configure the parent clocks of PCIE. + +Signed-off-by: Richard Zhu +Signed-off-by: Khem Raj +--- + drivers/clk/imx/clk-imx8mq.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c +index bf3100eb59ca..3a5ff7109ff1 100644 +--- a/drivers/clk/imx/clk-imx8mq.c ++++ b/drivers/clk/imx/clk-imx8mq.c +@@ -646,6 +646,12 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) + /* enable all the clocks just for bringup */ + imx_clk_init_on(np, hws); + ++ /* set pcie root's parent clk source */ ++ clk_set_parent(hws[IMX8MQ_CLK_PCIE1_CTRL]->clk, hws[IMX8MQ_SYS2_PLL_250M]->clk); ++ clk_set_parent(hws[IMX8MQ_CLK_PCIE1_PHY]->clk, hws[IMX8MQ_SYS2_PLL_100M]->clk); ++ clk_set_parent(hws[IMX8MQ_CLK_PCIE2_CTRL]->clk, hws[IMX8MQ_SYS2_PLL_250M]->clk); ++ clk_set_parent(hws[IMX8MQ_CLK_PCIE2_PHY]->clk, hws[IMX8MQ_SYS2_PLL_100M]->clk); ++ + clk_set_parent(hws[IMX8MQ_CLK_CSI1_CORE]->clk, hws[IMX8MQ_SYS1_PLL_266M]->clk); + clk_set_parent(hws[IMX8MQ_CLK_CSI1_PHY_REF]->clk, hws[IMX8MQ_SYS2_PLL_1000M]->clk); + clk_set_parent(hws[IMX8MQ_CLK_CSI1_ESC]->clk, hws[IMX8MQ_SYS1_PLL_800M]->clk); +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-imx-5.15/0003-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch b/recipes-kernel/linux/linux-imx-5.15/0003-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch new file mode 100644 index 0000000..3c7ca72 --- /dev/null +++ b/recipes-kernel/linux/linux-imx-5.15/0003-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch @@ -0,0 +1,44 @@ +From dd3d8c2c0b77eb742b288cf83e4849f87c8db5c6 Mon Sep 17 00:00:00 2001 +From: Khem Raj +Date: Tue, 7 Mar 2023 21:19:36 -0800 +Subject: [PATCH 3/4] PCI: imx: Use the external clock as REF_CLK when needed + for i.MX8MQ + +Do not use the external clock when the internal PLL is used as PCIe +REF_CLK. + +Signed-off-by: Ryosuke Saito +Signed-off-by: Khem Raj +--- + drivers/pci/controller/dwc/pci-imx6.c | 15 +++++++-------- + 1 file changed, 7 insertions(+), 8 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c +index 3a8350cad812..841af6f55c7d 100644 +--- a/drivers/pci/controller/dwc/pci-imx6.c ++++ b/drivers/pci/controller/dwc/pci-imx6.c +@@ -1569,14 +1569,13 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) + break; + case IMX8MQ: + case IMX8MQ_EP: +- /* +- * TODO: Currently this code assumes external +- * oscillator is being used +- */ +- regmap_update_bits(imx6_pcie->iomuxc_gpr, +- imx6_pcie_grp_offset(imx6_pcie), +- IMX8MQ_GPR_PCIE_REF_USE_PAD, +- IMX8MQ_GPR_PCIE_REF_USE_PAD); ++ if (imx6_pcie->ext_osc) { ++ /* Use the external oscillator as REF clock */ ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, ++ imx6_pcie_grp_offset(imx6_pcie), ++ IMX8MQ_GPR_PCIE_REF_USE_PAD, ++ IMX8MQ_GPR_PCIE_REF_USE_PAD); ++ } + /* + * Regarding the datasheet, the PCIE_VPH is suggested + * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-imx-5.15/0004-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch b/recipes-kernel/linux/linux-imx-5.15/0004-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch new file mode 100644 index 0000000..ab50273 --- /dev/null +++ b/recipes-kernel/linux/linux-imx-5.15/0004-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch @@ -0,0 +1,71 @@ +From 0845d9b5935ad8b3d450c2dfa62631c9c1df1bea Mon Sep 17 00:00:00 2001 +From: Khem Raj +Date: Tue, 7 Mar 2023 21:21:57 -0800 +Subject: [PATCH 4/4] PCI: imx: Provide a clock to the device for i.MX8MQ + +When the internal PLL is configured as PCIe REF_CLK, we also have to +output a clock via CLK2_P/N pin to the connector/device to provide it. +Configure 100 MHz clock as its output. + +Signed-off-by: Ryosuke Saito +Signed-off-by: Khem Raj +--- + drivers/pci/controller/dwc/pci-imx6.c | 35 +++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c +index 841af6f55c7d..ac36c7035460 100644 +--- a/drivers/pci/controller/dwc/pci-imx6.c ++++ b/drivers/pci/controller/dwc/pci-imx6.c +@@ -275,6 +275,12 @@ struct imx6_pcie { + #define IMX8MM_GPR_PCIE_POWER_OFF BIT(17) + #define IMX8MM_GPR_PCIE_SSC_EN BIT(16) + ++#define IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG 0x74 ++#define IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK GENMASK(3, 0) ++#define IMX8MQ_ANA_PLLOUT_MONITOR_CKE BIT(4) ++#define IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG 0x7C ++#define IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK GENMASK(2, 0) ++ + static int imx6_pcie_cz_enabled; + static void imx6_pcie_ltssm_disable(struct device *dev); + +@@ -1575,6 +1581,35 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) + imx6_pcie_grp_offset(imx6_pcie), + IMX8MQ_GPR_PCIE_REF_USE_PAD, + IMX8MQ_GPR_PCIE_REF_USE_PAD); ++ } else { ++ /* ++ * Use the internal PLL as REF clock and also ++ * provide a clock to the device. ++ */ ++ struct regmap *anatop = ++ syscon_regmap_lookup_by_compatible("fsl,imx8mq-anatop"); ++ ++ if (IS_ERR(anatop)) { ++ dev_err(imx6_pcie->pci->dev, ++ "Couldn't configure the internal PLL as REF clock\n"); ++ break; ++ } ++ ++ /* Select SYSTEM_PLL1_CLK as the clock source */ ++ regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG, ++ IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK, 0xb); ++ ++ /* ++ * SYSTEM_PLL1_CLK is 800 MHz, so divided by 8 ++ * for generating 100 MHz as output. ++ */ ++ regmap_update_bits(anatop, IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG, ++ IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK, 0x7); ++ ++ /* Enable CLK2_P/N clock to provide it to the device */ ++ regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG, ++ IMX8MQ_ANA_PLLOUT_MONITOR_CKE, ++ IMX8MQ_ANA_PLLOUT_MONITOR_CKE); + } + /* + * Regarding the datasheet, the PCIE_VPH is suggested +-- +2.39.2 + diff --git a/recipes-kernel/linux/linux-imx_%.bbappend b/recipes-kernel/linux/linux-imx_%.bbappend new file mode 100644 index 0000000..fe65167 --- /dev/null +++ b/recipes-kernel/linux/linux-imx_%.bbappend @@ -0,0 +1,12 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" + +FILESPATH =. "${FILE_DIRNAME}/${BPN}-5.15:" + +SRC_URI:append:coral-dev = "\ + file://0001-imx8mq-phanbell.dts-Enable-Coral-specifics-e.g.-PCIE.patch \ + file://0002-MLK-15307-2-clk-imx8mq-set-the-parent-clocks-of-PCIE.patch \ + file://0003-PCI-imx-Use-the-external-clock-as-REF_CLK-when-neede.patch \ + file://0004-PCI-imx-Provide-a-clock-to-the-device-for-i.MX8MQ.patch \ + file://extra.cfg \ + file://wifi.cfg \ +"