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Compile Issue in the fiddling with FIFO #2
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@morpheuskibbe My apologies for the long delay in responding. You should be able to leave a comment on the blog. I'll investigate that. You may have to register in order to leave a comment to avoid spam comments. Can you provide a little more information on how you are trying to use this? The code was built and tested using Xilinx Vivado. Are you using a different Verilog environment? A limit of 250 iterations is likely someone that you can configure in your tooling. At the clock speeds of an FPGA, 250 iterations is not a lot of time. OTOH, the delays built into the test code are not long. |
oh hey. ya it's been a bit. I'm using Quartus 18.1. I was mostly playing
with your code to learn Verilog and just hit compile without changing it so
the code was unedited.
…On Thu, Sep 28, 2023 at 2:33 PM Mark Seminatore ***@***.***> wrote:
@morpheuskibbe <https://github.com/morpheuskibbe> My apologies for the
long delay in responding. You should be able to leave a comment on the
blog. I'll investigate that. You may have to register in order to leave a
comment to avoid spam comments.
Can you provide a little more information on how you are trying to use
this? The code was built and tested using Xilinx Vivado. Are you using a
different Verilog environment?
A limit of 250 iterations is likely someone that you can configure in your
tooling. At the clock speeds of an FPGA, 250 iterations is not a lot of
time. OTOH, the delays built into the test code are not long.
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for this: https://fpgacoding.com/fiddling-with-a-fifo/
I would have left a comment on the post directly, but it seems that there's no way to do that.
I tried to run your code but on Analysis and elaboration I get.
Error (10119): Verilog HDL Loop Statement error at TopLevel.v(58): loop with non-constant loop condition must terminate within 250 iterations
and it refuses to finish.
This defers to the line "while(~full)" in your FIFO test bench. nay Idea why that would be happening?
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