diff --git a/fc1004.v b/fc1004.v
index 637dcec..e2dad17 100644
--- a/fc1004.v
+++ b/fc1004.v
@@ -27,6 +27,7 @@
 module fc1004
 	(
 	input MCLK,
+	input MCLK_e,
 	input [7:0] SD,
 	output SE1,
 	output SE0,
@@ -281,6 +282,7 @@ module fc1004
 	
 	ym7101 vdp(
 		.MCLK(MCLK),
+		.MCLK_e(MCLK_e),
 		.SD(SD),
 		.SE1(SE1),
 		.SE0(SE0),
@@ -395,6 +397,7 @@ module fc1004
 	ym6045 arb
 		(
 		.MCLK(MCLK),
+		.MCLK_e(MCLK_e),
 		.VCLK(CLK_i),
 		.ZCLK(ZCLK_i),
 		.VD8_i(VD_i[8]),
diff --git a/md_board.v b/md_board.v
index 029f023..ab38894 100644
--- a/md_board.v
+++ b/md_board.v
@@ -51,7 +51,7 @@ module md_board
 	output vdp_rs1, // h32/h40
 	output vdp_m2, // v28/v30
 	output vdp_lcb,
-	output vdp_psg_hclk1,
+	output vdp_psg_clk1,
 	output fm_clk1
 	
 	);
@@ -216,9 +216,17 @@ module md_board
 	wire [7:0] ym_ZD_o;
 	wire [7:0] ym_ZD_d;
 	
+	reg MCLK_e;
+	
+	always @(posedge MCLK2)
+	begin
+		MCLK_e <= ~MCLK_e;
+	end
+	
 	fc1004 ym
 		(
 		.MCLK(MCLK2),
+		.MCLK_e(MCLK_e),
 		.SD(SD),
 		.SE1(SE1),
 		.SE0(SE0),
diff --git a/ym6045.v b/ym6045.v
index 43fe8fb..71ccef6 100644
--- a/ym6045.v
+++ b/ym6045.v
@@ -24,6 +24,7 @@
 module ym6045
 	(
 	input MCLK,
+	input MCLK_e,
 	input VCLK,
 	input ZCLK,
 	input VD8_i,
@@ -414,8 +415,6 @@ module ym6045
 		edclk_buf <= w2;
 	end*/
 	
-	reg MCLK_e;
-	
 	ym_scnt_bit dff1(.MCLK(MCLK), .clk(MCLK_e), .load(w1), .val(1'h1), .cin(w3), .rst(sres), .nq(dff1_nq));
 	ym_scnt_bit dff2(.MCLK(MCLK), .clk(MCLK_e), .load(w1), .val(~dff9_q), .cin(1'h1), .rst(sres), .q(dff2_q), .nq(dff2_nq));
 	ym_scnt_bit dff3(.MCLK(MCLK), .clk(MCLK_e), .load(w1), .val(1'h0), .cin(dff2_q), .rst(sres), .q(dff3_q), .nq(dff3_nq));
@@ -423,7 +422,6 @@ module ym6045
 	always @(posedge MCLK)
 	begin
 		edclk_buf <= w2;
-		MCLK_e <= ~MCLK_e;
 	end
 	
 	//assign w1 = ~(~dff1 & ~dff2 & ~dff3);
diff --git a/ym7101.v b/ym7101.v
index ef7d93c..417f053 100644
--- a/ym7101.v
+++ b/ym7101.v
@@ -28,6 +28,7 @@
 
 module ym7101
 	(
+	input MCLK,
 	input [7:0] SD,
 	output SE1,
 	output SE0,
@@ -64,7 +65,7 @@ module ym7101
 	//output CLK1_d,
 	output SBCR,
 	output CLK0,
-	input MCLK,
+	input MCLK_e,
 	input EDCLK_i,
 	output EDCLK_o,
 	output EDCLK_d,
@@ -2274,12 +2275,9 @@ module ym7101
 	
 	assign mclk_cpu_clk1 = ~(mclk_clk3 | mclk_clk3_l);
 	
-	reg MCLK_e;
-	
 	always @(posedge MCLK)
 	begin
 		mclk_clk3_l <= mclk_clk3;
-		MCLK_e <= ~MCLK_e;
 	end
 	
 	ym7101_dff prescaler_dff1(.MCLK(MCLK), .clk(MCLK_e), .inp(reset_comb), .rst(1'h0), .outp(prescaler_dff1_l2));