OpenEmbedded for Tegra
-
|
I have a custom carrier board for the Xavier NX with a micro sd card cage connected to From 8836e5fc775bf9f45ad7c67b800e28d003bb62f0 Mon Sep 17 00:00:00 2001
From: Cameron McQuinn <[email protected]>
Date: Fri, 7 Oct 2022 20:46:07 +0000
Subject: [PATCH] Enable sdmmc3 with card detect on pcc0
---
nvidia/drivers/pinctrl/pinctrl-tegra194.c | 6 +--
.../common/tegra194-p3668-common.dtsi | 40 ++++++++++++-------
2 files changed, 29 insertions(+), 17 deletions(-)
diff --git a/nvidia/drivers/pinctrl/pinctrl-tegra194.c b/nvidia/drivers/pinctrl/pinctrl-tegra194.c
index ed3323ca25ee..3c00a13ad7d3 100644
--- a/nvidia/drivers/pinctrl/pinctrl-tegra194.c
+++ b/nvidia/drivers/pinctrl/pinctrl-tegra194.c
@@ -203,7 +203,7 @@
fname(CAN1_EN_PBB1, can1_en_pbb1, _GPIO, 217) \
fname(CAN1_WAKE_PBB2, can1_wake_pbb2, _GPIO, 218) \
fname(CAN1_ERR_PBB3, can1_err_pbb3, _GPIO, 219) \
- fname(SPI2_SCK_PCC0, spi2_sck_pcc0, _GPIO, 224) \
+ fname(SDMMC3_CD_PCC0, sdmmc3_cd_pcc0, _GPIO, 224) \
fname(SPI2_MISO_PCC1, spi2_miso_pcc1, _GPIO, 225) \
fname(SPI2_MOSI_PCC2, spi2_mosi_pcc2, _GPIO, 226) \
fname(SPI2_CS0_PCC3, spi2_cs0_pcc3, _GPIO, 227) \
@@ -461,7 +461,7 @@ static struct tegra_function tegra194_functions[] = {
#define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 1)
#define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
#define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
+#define drive_sdmmc3_cd_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
#define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 1)
#define drive_can1_dout_paa0 DRV_PINGROUP_ENTRY_Y(0x3004, 28, 2, 30, 2, -1, -1, -1, -1, 1)
#define drive_can1_din_paa1 DRV_PINGROUP_ENTRY_Y(0x300c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
@@ -705,7 +705,7 @@ static const struct tegra_pingroup tegra194_groups[] = {
PINGROUP(gen2_i2c_scl_pcc7, I2C2, RSVD1, RSVD2, RSVD3, 0x2030, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(spi2_cs0_pcc3, SPI2, UARTG, RSVD2, RSVD3, 0x2038, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(gen2_i2c_sda_pdd0, I2C2, RSVD1, RSVD2, RSVD3, 0x2040, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
- PINGROUP(spi2_sck_pcc0, SPI2, UARTG, RSVD2, RSVD3, 0x2048, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
+ PINGROUP(sdmmc3_cd_pcc0, SDMMC3, RSVD1, RSVD2, RSVD3, 0x2048, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(spi2_miso_pcc1, SPI2, UARTG, RSVD2, RSVD3, 0x2050, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(can1_dout_paa0, CAN1, RSVD1, RSVD2, RSVD3, 0x3000, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
PINGROUP(can1_din_paa1, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
diff --git a/nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-p3668-common.dtsi b/nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-p3668-common.dtsi
index a94051d19da1..5362c1a23d03 100644
--- a/nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-p3668-common.dtsi
+++ b/nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-p3668-common.dtsi
@@ -16,6 +16,7 @@
#include "dt-bindings/extcon-ids.h"
#include "dt-bindings/gpio/tegra194-gpio.h"
#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <tegra194-soc/tegra194-soc-cvm.dtsi>
#include "tegra194-fixed-regulator-p3668.dtsi"
#include <t19x-common-platforms/tegra194-comms.dtsi>
@@ -274,6 +275,13 @@
status = "okay";
};
+ sdmmc3: sdhci@3440000 {
+ mmc-ocr-mask = <0x0>;
+ cd-inverted;
+ cd-gpios = <&tegra_aon_gpio TEGRA194_AON_GPIO(CC, 0) 0>;
+ status = "okay";
+ };
+
mipical@3990000 {
status = "okay";
};
@@ -287,6 +295,23 @@
nvidia,cmd-timeout = <2000>;
};
+ pinmux@2430000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_default>;
+
+ pinmux_default: common {
+ sdmmc3_cd_pcc0 {
+ nvidia,pins = "sdmmc3_cd_pcc0";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+ nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+ };
+ };
+ };
+
gpio@c2f0000 {
pex-refclk-sel-low {
gpio-hog;
@@ -303,20 +328,7 @@
label = "pex_refclk_sel_high";
status = "disabled";
};
- w-disable1 {
- gpio-hog;
- output-high;
- gpios = <TEGRA194_AON_GPIO(CC, 2) GPIO_ACTIVE_LOW>;
- label = "w-disable1";
- status = "okay";
- };
- w-disable2 {
- gpio-hog;
- output-high;
- gpios = <TEGRA194_AON_GPIO(CC, 0) GPIO_ACTIVE_LOW>;
- label = "w-disable2";
- status = "okay";
- };
+
suspend_gpio: suspend-led-gpio {
gpio-hog;
output-high;
--
2.34.1 |
Beta Was this translation helpful? Give feedback.
Replies: 1 comment 1 reply
-
|
First, check under Also, I'm not sure that any pinmux changes you make in the kernel sources will really work. The MB1 pinmux configuration files, generated out of the pinmux configuration Excel spreadsheet they provide, are the way that NVIDIA documents you make such changes. |
Beta Was this translation helpful? Give feedback.
-
|
I managed to get this working. It turned out to be a carrier board issue. |
Beta Was this translation helpful? Give feedback.
First, check under
/proc/device-treeon the running device to see if thestatusentry forsdhci@3440000is reallyokayand notdisabled. I'm not sure what order thedtsifiles are included, so if your addition was processed before the entry integra194-soc-sdhci.dtsithat defines that node and sets itdisabled, that might explain it. It's usually better to do such overrides in the top-level.dtsfile after all the common stuff is included.Also, I'm not sure that any pinmux changes you make in the kernel sources will really work. The MB1 pinmux configuration files, generated out of the pinmux configuration Excel spreadsheet they provide, are the way that NVIDIA documents you make such cha…