diff --git a/src/Compiler/CompilerRS.cpp b/src/Compiler/CompilerRS.cpp index be688357b..8b4c42a98 100644 --- a/src/Compiler/CompilerRS.cpp +++ b/src/Compiler/CompilerRS.cpp @@ -811,6 +811,36 @@ void FOEDAG::TclArgs_setRsSynthesisOptions(const std::string &argsStr) { } } +std::string CompilerRS::BaseStaCommand() { + std::string command = m_staExecutablePath.string(); + return command; +} + +std::string CompilerRS::BaseStaScript(std::string libFileName, + std::string netlistFileName, + std::string sdfFileName, + std::string sdcFileName) { + std::string script = + std::string("read_liberty ") + libFileName + + std::string("\n") + // add lib for test only, need to research on this + std::string("read_verilog ") + netlistFileName + std::string("\n") + + std::string("link_design ") + + ProjManager()->getDesignTopModule().toStdString() + std::string("\n") + + std::string("read_sdf ") + sdfFileName + std::string("\n") + + std::string("read_sdc ") + sdcFileName + std::string("\n") + + std::string("report_checks\n") + + std::string("report_clock_min_period\n") + std::string("report_wns\n") + + std::string("exit\n"); + const std::string openStaFile = + (std::filesystem::path(ProjManager()->projectPath()) / + std::string(ProjManager()->projectName() + "_opensta.tcl")) + .string(); + std::ofstream ofssta(openStaFile); + ofssta << script << "\n"; + ofssta.close(); + return openStaFile; +} + bool CompilerRS::TimingAnalysis() { if (!ProjManager()->HasDesign()) { ErrorMessage("No design specified"); diff --git a/src/Compiler/CompilerRS.h b/src/Compiler/CompilerRS.h index 95c03ac18..a347d66a2 100644 --- a/src/Compiler/CompilerRS.h +++ b/src/Compiler/CompilerRS.h @@ -70,7 +70,11 @@ class CompilerRS : public CompilerOpenFPGA { protected: bool LicenseDevice(const std::string& deviceName); - + virtual std::string BaseStaCommand(); + virtual std::string BaseStaScript(std::string libFileName, + std::string netlistFileName, + std::string sdfFileName, + std::string sdcFileName); SynthesisEffort m_synthEffort = SynthesisEffort::None; SynthesisCarryInference m_synthCarry = SynthesisCarryInference::None; SynthesisFsmEncoding m_synthFsm = SynthesisFsmEncoding::None;