From c5525aef980a5de0571e89227738a76a311da5f3 Mon Sep 17 00:00:00 2001 From: moinijaz Date: Mon, 11 Mar 2024 12:23:44 +0500 Subject: [PATCH 1/2] removed RS_xx blackboxes --- blackbox_models/cell_sim_blackbox.v | 448 ---------------------- sim_models_internal/verilog/CARRY_CHAIN.v | 20 - tb/CARRY_CHAIN/CARRY_CHAIN_tb.v | 87 ----- 3 files changed, 555 deletions(-) delete mode 100644 sim_models_internal/verilog/CARRY_CHAIN.v delete mode 100644 tb/CARRY_CHAIN/CARRY_CHAIN_tb.v diff --git a/blackbox_models/cell_sim_blackbox.v b/blackbox_models/cell_sim_blackbox.v index 5a6a634..40b5219 100644 --- a/blackbox_models/cell_sim_blackbox.v +++ b/blackbox_models/cell_sim_blackbox.v @@ -31,23 +31,6 @@ module CARRY ( endmodule `endcelldefine // -// CARRY_CHAIN black box model -// FLE carry logic -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// -`celldefine -(* blackbox *) -module CARRY_CHAIN ( - input logic P, - input logic G, - input logic CIN, - output logic O, - output logic COUT -); -endmodule -`endcelldefine -// // CLK_BUF black box model // Global clock buffer // @@ -1084,437 +1067,6 @@ module LATCHNS(D, G, R, Q); endmodule `endcelldefine - -//DSP primitives// -`celldefine -(* blackbox *) -module RS_DSP ( - input [19:0] a, - input [17:0] b, - input [ 5:0] acc_fir, - output [37:0] z, - output [17:0] dly_b, - - (* clkbuf_sink *) - input clk, - input lreset, - - input [2:0] feedback, - input load_acc, - input unsigned_a, - input unsigned_b, - input saturate_enable, - input [5:0] shift_right, - input round, - input subtract - -); - - parameter [83:0] MODE_BITS = 84'd0; - - -endmodule -`endcelldefine - - -`celldefine -(* blackbox *) -module RS_DSP_MULT ( - input [19:0] a, - input [17:0] b, - output [37:0] z, - - input [2:0] feedback, - input unsigned_a, - input unsigned_b - -); - -parameter [79:0] MODE_BITS = 80'd0; - -endmodule -`endcelldefine - -`celldefine -(* blackbox *) -module RS_DSP_MULT_REGIN ( - input [19:0] a, - input [17:0] b, - output [37:0] z, - - (* clkbuf_sink *) - input clk, - input lreset, - - input [2:0] feedback, - input unsigned_a, - input unsigned_b - -); - -parameter [79:0] MODE_BITS = 80'd0; -endmodule -`endcelldefine - -`celldefine -(* blackbox *) -module RS_DSP_MULT_REGOUT ( - input [19:0] a, - input [17:0] b, - output [37:0] z, - - (* clkbuf_sink *) - input clk, - input lreset, - - input [2:0] feedback, - input unsigned_a, - input unsigned_b - -); - - -parameter [79:0] MODE_BITS = 80'd0; -endmodule -`endcelldefine - - -`celldefine -(* blackbox *) -module RS_DSP_MULT_REGIN_REGOUT ( - input [19:0] a, - input [17:0] b, - output [37:0] z, - - (* clkbuf_sink *) - input clk, - input lreset, - - input [2:0] feedback, - input unsigned_a, - input unsigned_b - -); - - -parameter [79:0] MODE_BITS = 80'd0; - -endmodule -`endcelldefine - - -`celldefine -(* blackbox *) -module RS_DSP_MULTADD ( - input [19:0] a, - input [17:0] b, - output [37:0] z, - output [17:0] dly_b, - - (* clkbuf_sink *) - input clk, - input lreset, - - input [ 2:0] feedback, - input [ 5:0] acc_fir, - input load_acc, - input unsigned_a, - input unsigned_b, - - - input saturate_enable, - input [ 5:0] shift_right, - input round, - input subtract - -); - -parameter [79:0] MODE_BITS = 80'd0; - - -endmodule -`endcelldefine - -`celldefine -(* blackbox *) -module RS_DSP_MULTADD_REGIN ( - input [19:0] a, - input [17:0] b, - output [37:0] z, - output [17:0] dly_b, - - (* clkbuf_sink *) - input clk, - input lreset, - - input [ 2:0] feedback, - input [ 5:0] acc_fir, - input load_acc, - input unsigned_a, - input unsigned_b, - - - input saturate_enable, - input [ 5:0] shift_right, - input round, - input subtract - -); - -parameter [79:0] MODE_BITS = 80'd0; - -endmodule -`endcelldefine - -`celldefine -(* blackbox *) -module RS_DSP_MULTADD_REGOUT ( - input [19:0] a, - input [17:0] b, - output [37:0] z, - output [17:0] dly_b, - - (* clkbuf_sink *) - input clk, - input lreset, - - input [ 2:0] feedback, - input [ 5:0] acc_fir, - input load_acc, - input unsigned_a, - input unsigned_b, - - - input saturate_enable, - input [ 5:0] shift_right, - input round, - input subtract - -); - -parameter [79:0] MODE_BITS = 80'd0; - -endmodule -`endcelldefine - -`celldefine -(* blackbox *) -module RS_DSP_MULTADD_REGIN_REGOUT ( - input [19:0] a, - input [17:0] b, - output [37:0] z, - output [17:0] dly_b, - - (* clkbuf_sink *) - input clk, - input lreset, - - input [ 2:0] feedback, - input [ 5:0] acc_fir, - input load_acc, - input unsigned_a, - input unsigned_b, - - - input saturate_enable, - input [ 5:0] shift_right, - input round, - input subtract -); - -parameter [79:0] MODE_BITS = 80'd0; - -endmodule -`endcelldefine - -`celldefine -(* blackbox *) -module RS_DSP_MULTACC ( - input [19:0] a, - input [17:0] b, - output [37:0] z, - - (* clkbuf_sink *) - input clk, - input lreset, - - input load_acc, - input [ 2:0] feedback, - input unsigned_a, - input unsigned_b, - - input saturate_enable, - input [ 5:0] shift_right, - input round, - input subtract -); -parameter [79:0] MODE_BITS = 80'd0; - -endmodule -`endcelldefine - -`celldefine -(* blackbox *) -module RS_DSP_MULTACC_REGIN ( - input [19:0] a, - input [17:0] b, - output [37:0] z, - - (* clkbuf_sink *) - input clk, - input lreset, - - input [ 2:0] feedback, - input load_acc, - input unsigned_a, - input unsigned_b, - - - input saturate_enable, - input [ 5:0] shift_right, - input round, - input subtract - -); - -parameter [79:0] MODE_BITS = 80'd0; - -endmodule -`endcelldefine - -`celldefine -(* blackbox *) -module RS_DSP_MULTACC_REGOUT ( - input [19:0] a, - input [17:0] b, - output [37:0] z, - - (* clkbuf_sink *) - input clk, - input lreset, - - input [ 2:0] feedback, - input load_acc, - input unsigned_a, - input unsigned_b, - - input saturate_enable, - input [ 5:0] shift_right, - input round, - input subtract -); - -parameter [79:0] MODE_BITS = 80'd0; - -endmodule -`endcelldefine - -`celldefine -(* blackbox *) -module RS_DSP_MULTACC_REGIN_REGOUT ( - input [19:0] a, - input [17:0] b, - output [37:0] z, - - (* clkbuf_sink *) - input clk, - input lreset, - - input [ 2:0] feedback, - input load_acc, - input unsigned_a, - input unsigned_b, - - input saturate_enable, - input [ 5:0] shift_right, - input round, - input subtract -); - -parameter [79:0] MODE_BITS = 80'd0; - -endmodule -`endcelldefine - -//TDP BRAM //FIFO - -`celldefine -(* blackbox *) -module RS_TDP36K ( - WEN_A1, - WEN_B1, - REN_A1, - REN_B1, - CLK_A1, - CLK_B1, - BE_A1, - BE_B1, - ADDR_A1, - ADDR_B1, - WDATA_A1, - WDATA_B1, - RDATA_A1, - RDATA_B1, - FLUSH1, - WEN_A2, - WEN_B2, - REN_A2, - REN_B2, - CLK_A2, - CLK_B2, - BE_A2, - BE_B2, - ADDR_A2, - ADDR_B2, - WDATA_A2, - WDATA_B2, - RDATA_A2, - RDATA_B2, - FLUSH2 -); - parameter [80:0] MODE_BITS = 81'd0; - parameter [36863:0] INIT_i = 36864'h0; - - - input wire WEN_A1; - input wire WEN_B1; - input wire REN_A1; - input wire REN_B1; - (* clkbuf_sink *) - input wire CLK_A1; - (* clkbuf_sink *) - input wire CLK_B1; - input wire [1:0] BE_A1; - input wire [1:0] BE_B1; - input wire [14:0] ADDR_A1; - input wire [14:0] ADDR_B1; - input wire [17:0] WDATA_A1; - input wire [17:0] WDATA_B1; - output reg [17:0] RDATA_A1; - output reg [17:0] RDATA_B1; - input wire FLUSH1; - input wire WEN_A2; - input wire WEN_B2; - input wire REN_A2; - input wire REN_B2; - (* clkbuf_sink *) - input wire CLK_A2; - (* clkbuf_sink *) - input wire CLK_B2; - input wire [1:0] BE_A2; - input wire [1:0] BE_B2; - input wire [13:0] ADDR_A2; - input wire [13:0] ADDR_B2; - input wire [17:0] WDATA_A2; - input wire [17:0] WDATA_B2; - output reg [17:0] RDATA_A2; - output reg [17:0] RDATA_B2; - input wire FLUSH2; - -endmodule -`endcelldefine - - `celldefine (* blackbox *) module BRAM2x18_TDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, CLK3, CLK4, D1ADDR, D1DATA, D1EN, E1ADDR, E1DATA, E1EN, F1ADDR, F1DATA, F1EN, G1ADDR, G1DATA, G1EN, H1ADDR, H1DATA, H1EN); diff --git a/sim_models_internal/verilog/CARRY_CHAIN.v b/sim_models_internal/verilog/CARRY_CHAIN.v deleted file mode 100644 index bafd173..0000000 --- a/sim_models_internal/verilog/CARRY_CHAIN.v +++ /dev/null @@ -1,20 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// CARRY_CHAIN simulation model -// FLE carry logic -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module CARRY_CHAIN ( - input P, // Partial data input - input G, // Partial data input - input CIN, // Carry in - output O, // Data Output - output COUT // Carry out -); - - assign {COUT, O} = {P ? CIN : G, P ^ CIN}; -endmodule -`endcelldefine diff --git a/tb/CARRY_CHAIN/CARRY_CHAIN_tb.v b/tb/CARRY_CHAIN/CARRY_CHAIN_tb.v deleted file mode 100644 index 21b751d..0000000 --- a/tb/CARRY_CHAIN/CARRY_CHAIN_tb.v +++ /dev/null @@ -1,87 +0,0 @@ - - -module CARRY_CHAIN_tb; - - //Ports - reg P; - reg G; - reg CIN; - wire O; - wire COUT1, COUT2; - reg clk = 1; - - integer i; - integer mismatch=0; - reg [6:0]cycle; - - always #(10) - clk = !clk; - - CARRY_CHAIN CARRY_CHAIN_inst ( - .P(P), - .G(G), - .CIN(CIN), - .O(O), - .COUT(COUT1) - ); - - adder adder_inst ( - .P(P), - .G(G), - .CIN(CIN), - .O(O), - .COUT(COUT2) - ); - - initial begin - {P , G, CIN} = 0; - - repeat (5) @(negedge clk); - - for (i=0; i<=100; i=i+1)begin - repeat (1) @ (negedge clk) - P <= $random; - G <= $random; - CIN <= $random; - cycle = cycle +1; - compare(cycle); - end - - if(mismatch == 0) - $display("\nSimulation result: Test Passed"); - else begin - $display("\nSimulation result: Test Failed"); - $display("%0d comparison(s) mismatched\nERROR: SIM: Simulation Failed", mismatch); - end - repeat (10) @(negedge clk); - - $finish; - end - - task compare(input integer cycle); - if(COUT1 !== COUT2) begin - $display("DATA mismatch !!! Carry Chain: %0d, Adder: %0d, Time: %0t", COUT1, COUT2, $time); - mismatch = mismatch+1; - end - endtask - - initial begin - $dumpfile("CARRY_CHAIN.vcd"); - $dumpvars; - end - -endmodule - - -module adder( - input wire P, - input wire G, - input wire CIN, - output wire O, - output wire COUT -); - -assign O = P ^ CIN; -assign COUT = P ? CIN : G; - -endmodule \ No newline at end of file From 79f7055947192f0620fe0ea33663ff50b13b1b3c Mon Sep 17 00:00:00 2001 From: moinijaz Date: Mon, 11 Mar 2024 12:36:16 +0500 Subject: [PATCH 2/2] removed CARRY_CHAIN spec --- specs_internal/CARRY_CHAIN.yaml | 65 --------------------------------- 1 file changed, 65 deletions(-) delete mode 100644 specs_internal/CARRY_CHAIN.yaml diff --git a/specs_internal/CARRY_CHAIN.yaml b/specs_internal/CARRY_CHAIN.yaml deleted file mode 100644 index 1d3d826..0000000 --- a/specs_internal/CARRY_CHAIN.yaml +++ /dev/null @@ -1,65 +0,0 @@ -# Periphery Primitives Parameters and Properties (P4) -# -# This file contains the list of Verilog parameters and SDC properties that are -# allowed for periphery primitives. -# -# See https://rapidsilicon.atlassian.net/wiki/spaces/RS/pages/214368265/Periphery+Primitive+Parameters+and+Properties+Definitions+P4DEF for more details -# -# The name needs to match the filename root -# name: -# desc: -# -# ports: -# : -# dir: -# desc: -# : -# dir: -# desc: -# -# # set as Verilog parameter -# parameters: -# : -# desc: -# values: -# - -# - -# : -# desc: -# values: -# - -# - -# -# # set in SDC or by synthesis attribute -# properties: -# : -# desc: -# values: -# - -# - -# : -# desc: -# - -# - -# -# primitive name should match the filename root. -name: CARRY_CHAIN -desc: FLE carry logic -category: core_fabric - -ports: - P: - dir: input - desc: Partial data input - G: - dir: input - desc: Partial data input - CIN: - dir: input - desc: Carry in - O: - dir: output - desc: Data Output - COUT: - dir: output - desc: Carry out