From 14719e0398daa63aa8c401ae38be7bb8ad981d7d Mon Sep 17 00:00:00 2001
From: Nadeem Yaseen <70559777+NadeemYaseen@users.noreply.github.com>
Date: Thu, 3 Oct 2024 00:19:15 +0500
Subject: [PATCH] Revert "Rename DLY_SEL_DCODER.v to DLY_SEL_DECODER.v"

---
 sim_models/verilog/{DLY_SEL_DECODER.v => DLY_SEL_DCODER.v} | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename sim_models/verilog/{DLY_SEL_DECODER.v => DLY_SEL_DCODER.v} (100%)

diff --git a/sim_models/verilog/DLY_SEL_DECODER.v b/sim_models/verilog/DLY_SEL_DCODER.v
similarity index 100%
rename from sim_models/verilog/DLY_SEL_DECODER.v
rename to sim_models/verilog/DLY_SEL_DCODER.v