diff --git a/sim_models_internal/verilog/TDP_RAM18KX2.v b/sim_models_internal/verilog/TDP_RAM18KX2.v index 8179b8e..0e7c962 100644 --- a/sim_models_internal/verilog/TDP_RAM18KX2.v +++ b/sim_models_internal/verilog/TDP_RAM18KX2.v @@ -8,13 +8,17 @@ // module TDP_RAM18KX2 #( + /* verilator lint_off WIDTHCONCAT */ parameter [16383:0] INIT1 = {16384{1'b0}}, // Initial Contents of data memory, RAM 1 + /* verilator lint_on WIDTHCONCAT */ parameter [2047:0] INIT1_PARITY = {2048{1'b0}}, // Initial Contents of parity memory, RAM 1 parameter WRITE_WIDTH_A1 = 18, // Write data width on port A, RAM 1 (1, 2, 4, 9, 18) parameter WRITE_WIDTH_B1 = 18, // Write data width on port B, RAM 1 (1, 2, 4, 9, 18) parameter READ_WIDTH_A1 = 18, // Read data width on port A, RAM 1 (1, 2, 4, 9, 18) parameter READ_WIDTH_B1 = 18, // Read data width on port B, RAM 1 (1, 2, 4, 9, 18) + /* verilator lint_off WIDTHCONCAT */ parameter [16383:0] INIT2 = {16384{1'b0}}, // Initial Contents of memory, RAM 2 + /* verilator lint_on WIDTHCONCAT */ parameter [2047:0] INIT2_PARITY = {2048{1'b0}}, // Initial Contents of memory, RAM 2 parameter WRITE_WIDTH_A2 = 18, // Write data width on port A, RAM 2 (1, 2, 4, 9, 18) parameter WRITE_WIDTH_B2 = 18, // Write data width on port B, RAM 2 (1, 2, 4, 9, 18) @@ -100,6 +104,11 @@ module TDP_RAM18KX2 #( reg [RAM1_DATA_WIDTH-1:0] RAM1_DATA [2**RAM1_ADDR_WIDTH-1:0]; + reg [RAM1_PARITY_WIDTH-1:0] temp_WPARITY_A1; + reg [RAM1_PARITY_WIDTH-1:0] temp_WPARITY_B1; + reg [RAM1_DATA_WIDTH-1:0] temp_WDATA_A1; + reg [RAM1_DATA_WIDTH-1:0] temp_WDATA_B1; + generate if (RAM1_PARITY_WIDTH > 0) begin: parity_RAM1 reg [RAM1_PARITY_WIDTH-1:0] RAM1_PARITY [2**RAM1_ADDR_WIDTH-1:0]; @@ -111,21 +120,42 @@ module TDP_RAM18KX2 #( f_p = 0; for (g_p = 0; g_p < 2**RAM1_ADDR_WIDTH; g_p = g_p + 1) for (h_p = 0; h_p < RAM1_PARITY_WIDTH; h_p = h_p + 1) begin + /* verilator lint_off INITIALDLY */ RAM1_PARITY[g_p][h_p] <= INIT1_PARITY[f_p]; + /* verilator lint_on INITIALDLY */ f_p = f_p + 1; end end + always @(temp_WPARITY_A1) + /* verilator lint_off WIDTH */ + RAM1_PARITY[a1_addr][i_p] = temp_WPARITY_A1; + /* verilator lint_on WIDTH */ + always @(posedge CLK_A1) if (WEN_A1) begin for (i_p = find_a1_write_index(ADDR_A1)*A1_PARITY_WRITE_WIDTH; i_p < find_a1_write_index(ADDR_A1)*A1_PARITY_WRITE_WIDTH+A1_PARITY_WRITE_WIDTH; i_p = i_p + 1) begin if (A1_PARITY_WRITE_WIDTH > 1) begin - if (BE_A1[i_p/1] == 1'b1) - RAM1_PARITY[a1_addr][i_p] <= WPARITY_A1[i_p-(find_a1_write_index(ADDR_A1)*A1_PARITY_WRITE_WIDTH)]; + if (BE_A1[i_p/1] == 1'b1) begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WPARITY_A1 <= WPARITY_A1[i_p-(find_a1_write_index(ADDR_A1)*A1_PARITY_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else + RAM1_PARITY[a1_addr][i_p] <= WPARITY_A1[i_p-(find_a1_write_index(ADDR_A1)*A1_PARITY_WRITE_WIDTH)]; + `endif + end end - else + else begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WPARITY_A1 <= WPARITY_A1[i_p-(find_a1_write_index(ADDR_A1)*A1_PARITY_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else RAM1_PARITY[a1_addr][i_p] <= WPARITY_A1[i_p-(find_a1_write_index(ADDR_A1)*A1_PARITY_WRITE_WIDTH)]; - //$display("i_p: %0h, [i_p/1] %0h", i_p, i_p/2,$time); + //$display("i_p: %0h, [i_p/1] %0h", i_p, i_p/2,$time); + `endif + end end end @@ -135,19 +165,38 @@ module TDP_RAM18KX2 #( RPARITY_A1[j_p-(find_a1_read_index(ADDR_A1)*A1_PARITY_READ_WIDTH)] <= RAM1_PARITY[a1_addr][j_p]; end else - RPARITY_A1 = 2'bx; + RPARITY_A1 <= 2'bx; + + always @(temp_WPARITY_B1) + /* verilator lint_off WIDTH */ + RAM1_PARITY[b1_addr][k_p] = temp_WPARITY_B1; + /* verilator lint_on WIDTH */ always @(posedge CLK_B1) if (WEN_B1) begin for (k_p = find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH; k_p < find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH+B1_PARITY_WRITE_WIDTH; k_p = k_p + 1) begin if (B1_PARITY_WRITE_WIDTH > 1) begin - if (BE_B1[k_p/1] == 1'b1) + if (BE_B1[k_p/1] == 1'b1) begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WPARITY_B1 <= WPARITY_B1[k_p-(find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else + RAM1_PARITY[b1_addr][k_p] <= WPARITY_B1[k_p-(find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH)]; + `endif + end + end + else begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WPARITY_B1 <= WPARITY_B1[k_p-(find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else RAM1_PARITY[b1_addr][k_p] <= WPARITY_B1[k_p-(find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH)]; + `endif end - else - RAM1_PARITY[b1_addr][k_p] <= WPARITY_B1[k_p-(find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH)]; end - end + end always @(posedge CLK_B1) if (REN_B1) begin @@ -155,7 +204,7 @@ module TDP_RAM18KX2 #( RPARITY_B1[m_p-(find_b1_read_index(ADDR_B1)*B1_PARITY_READ_WIDTH)] <= RAM1_PARITY[b1_addr][m_p]; end else - RPARITY_B1 = 2'bx; + RPARITY_B1 <= 2'bx; end endgenerate @@ -165,10 +214,17 @@ module TDP_RAM18KX2 #( f = 0; for (g = 0; g < 2**RAM1_ADDR_WIDTH; g = g + 1) for (h = 0; h < RAM1_DATA_WIDTH; h = h + 1) begin + /* verilator lint_off INITIALDLY */ RAM1_DATA[g][h] <= INIT1[f]; + /* verilator lint_on INITIALDLY */ f = f + 1; end end + + always @(temp_WDATA_A1) + /* verilator lint_off WIDTH */ + RAM1_DATA[a1_addr][i] = temp_WDATA_A1; + /* verilator lint_on WIDTH */ // Base RAM read/write functionality always @(posedge CLK_A1) @@ -176,11 +232,25 @@ module TDP_RAM18KX2 #( //$display("AADR_A: %b index: %d", ADDR_A1, find_a1_write_index(ADDR_A1)*8); for (i = find_a1_write_index(ADDR_A1)*A1_DATA_WRITE_WIDTH; i < find_a1_write_index(ADDR_A1)*A1_DATA_WRITE_WIDTH+A1_DATA_WRITE_WIDTH; i = i + 1) begin if (A1_DATA_WRITE_WIDTH > 9) begin - if (BE_A1[i/8] == 1'b1) + if (BE_A1[i/8] == 1'b1) begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WDATA_A1 <= WDATA_A1[i-(find_a1_write_index(ADDR_A1)*A1_DATA_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else + RAM1_DATA[a1_addr][i] <= WDATA_A1[i-(find_a1_write_index(ADDR_A1)*A1_DATA_WRITE_WIDTH)]; + `endif + end + end + else begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WDATA_A1 <= WDATA_A1[i-(find_a1_write_index(ADDR_A1)*A1_DATA_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else RAM1_DATA[a1_addr][i] <= WDATA_A1[i-(find_a1_write_index(ADDR_A1)*A1_DATA_WRITE_WIDTH)]; + `endif end - else - RAM1_DATA[a1_addr][i] <= WDATA_A1[i-(find_a1_write_index(ADDR_A1)*A1_DATA_WRITE_WIDTH)]; end collision_a_address = a1_addr; collision_a_write_flag = 1; @@ -198,24 +268,43 @@ module TDP_RAM18KX2 #( collision_a_read_flag = 0; end else - RDATA_A1 = 16'bx; + RDATA_A1 = 16'bx; + + always @(temp_WDATA_B1) + /* verilator lint_off WIDTH */ + RAM1_DATA[b1_addr][k] = temp_WDATA_B1; + /* verilator lint_on WIDTH */ always @(posedge CLK_B1) if (WEN_B1) begin for (k = find_b1_write_index(ADDR_B1)*B1_DATA_WRITE_WIDTH; k < find_b1_write_index(ADDR_B1)*B1_DATA_WRITE_WIDTH+B1_DATA_WRITE_WIDTH; k = k + 1) begin if (B1_DATA_WRITE_WIDTH > 9) begin - if (BE_B1[k/8] == 1'b1) + if (BE_B1[k/8] == 1'b1) begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WDATA_B1 <= WDATA_B1[k-(find_b1_write_index(ADDR_B1)*B1_DATA_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else + RAM1_DATA[b1_addr][k] <= WDATA_B1[k-(find_b1_write_index(ADDR_B1)*B1_DATA_WRITE_WIDTH)]; + `endif + end + end + else begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WDATA_B1 <= WDATA_B1[k-(find_b1_write_index(ADDR_B1)*B1_DATA_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else RAM1_DATA[b1_addr][k] <= WDATA_B1[k-(find_b1_write_index(ADDR_B1)*B1_DATA_WRITE_WIDTH)]; + `endif end - else - RAM1_DATA[b1_addr][k] <= WDATA_B1[k-(find_b1_write_index(ADDR_B1)*B1_DATA_WRITE_WIDTH)]; end collision_b_address = b1_addr; collision_b_write_flag = 1; #collision_window; collision_b_write_flag = 0; - end + end always @(posedge CLK_B1) if (REN_B1) begin @@ -305,6 +394,11 @@ module TDP_RAM18KX2 #( reg [RAM2_DATA_WIDTH-1:0] RAM2_DATA [2**RAM2_ADDR_WIDTH-1:0]; + reg [RAM2_PARITY_WIDTH-1:0] temp_WPARITY_A2; + reg [RAM2_PARITY_WIDTH-1:0] temp_WPARITY_B2; + reg [RAM2_DATA_WIDTH-1:0] temp_WDATA_A2; + reg [RAM2_DATA_WIDTH-1:0] temp_WDATA_B2; + generate if (RAM2_PARITY_WIDTH > 0) begin: parity_RAM2 reg [RAM2_PARITY_WIDTH-1:0] RAM2_PARITY [2**RAM2_ADDR_WIDTH-1:0]; @@ -316,21 +410,42 @@ module TDP_RAM18KX2 #( f_p2 = 0; for (g_p2 = 0; g_p2 < 2**RAM2_ADDR_WIDTH; g_p2 = g_p2 + 1) for (h_p2 = 0; h_p2 < RAM2_PARITY_WIDTH; h_p2 = h_p2 + 1) begin + /* verilator lint_off INITIALDLY */ RAM2_PARITY[g_p2][h_p2] <= INIT2_PARITY[f_p2]; + /* verilator lint_on INITIALDLY */ f_p2 = f_p2 + 1; end end + always @(temp_WPARITY_A2) + /* verilator lint_off WIDTH */ + RAM2_PARITY[a2_addr][i_p2] = temp_WPARITY_A2; + /* verilator lint_on WIDTH */ + always @(posedge CLK_A2) if (WEN_A2) begin for (i_p2 = find_a2_write_index(ADDR_A2)*A2_PARITY_WRITE_WIDTH; i_p2 < find_a2_write_index(ADDR_A2)*A2_PARITY_WRITE_WIDTH+A2_PARITY_WRITE_WIDTH; i_p2 = i_p2 + 1) begin if (A2_PARITY_WRITE_WIDTH > 1) begin - if (BE_A2[i_p2/1] == 1'b1) + if (BE_A2[i_p2/1] == 1'b1) begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WPARITY_A2 <= WPARITY_A2[i_p2-(find_a2_write_index(ADDR_A2)*A2_PARITY_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else + RAM2_PARITY[a2_addr][i_p2] <= WPARITY_A2[i_p2-(find_a2_write_index(ADDR_A2)*A2_PARITY_WRITE_WIDTH)]; + `endif + end + end + else begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WPARITY_A2 <= WPARITY_A2[i_p2-(find_a2_write_index(ADDR_A2)*A2_PARITY_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else RAM2_PARITY[a2_addr][i_p2] <= WPARITY_A2[i_p2-(find_a2_write_index(ADDR_A2)*A2_PARITY_WRITE_WIDTH)]; + //$display("i_p2: %0h, [i_p2/1] %0h", i_p2, i_p2/2,$time); + `endif end - else - RAM2_PARITY[a2_addr][i_p2] <= WPARITY_A2[i_p2-(find_a2_write_index(ADDR_A2)*A2_PARITY_WRITE_WIDTH)]; - //$display("i_p2: %0h, [i_p2/1] %0h", i_p2, i_p2/2,$time); end end @@ -340,17 +455,36 @@ module TDP_RAM18KX2 #( RPARITY_A2[j_p2-(find_a2_read_index(ADDR_A2)*A2_PARITY_READ_WIDTH)] <= RAM2_PARITY[a2_addr][j_p2]; end else - RPARITY_A2 = 2'bx; + RPARITY_A2 <= 2'bx; + + always @(temp_WPARITY_B2) + /* verilator lint_off WIDTH */ + RAM2_PARITY[b2_addr][k_p2] = temp_WPARITY_B2; + /* verilator lint_on WIDTH */ always @(posedge CLK_B2) if (WEN_B2) begin for (k_p2 = find_b2_write_index(ADDR_B2)*B2_PARITY_WRITE_WIDTH; k_p2 < find_b2_write_index(ADDR_B2)*B2_PARITY_WRITE_WIDTH+B2_PARITY_WRITE_WIDTH; k_p2 = k_p2 + 1) begin if (B2_PARITY_WRITE_WIDTH > 1) begin - if (BE_B2[k_p2/1] == 1'b1) + if (BE_B2[k_p2/1] == 1'b1) begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WPARITY_B2 <= WPARITY_B2[k_p2-(find_b2_write_index(ADDR_B2)*B2_PARITY_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else + RAM2_PARITY[b2_addr][k_p2] <= WPARITY_B2[k_p2-(find_b2_write_index(ADDR_B2)*B2_PARITY_WRITE_WIDTH)]; + `endif + end + end + else begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WPARITY_B2 <= WPARITY_B2[k_p2-(find_b2_write_index(ADDR_B2)*B2_PARITY_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else RAM2_PARITY[b2_addr][k_p2] <= WPARITY_B2[k_p2-(find_b2_write_index(ADDR_B2)*B2_PARITY_WRITE_WIDTH)]; + `endif end - else - RAM2_PARITY[b2_addr][k_p2] <= WPARITY_B2[k_p2-(find_b2_write_index(ADDR_B2)*B2_PARITY_WRITE_WIDTH)]; end end @@ -360,7 +494,7 @@ module TDP_RAM18KX2 #( RPARITY_B2[m_p2-(find_b2_read_index(ADDR_B2)*B2_PARITY_READ_WIDTH)] <= RAM2_PARITY[b2_addr][m_p2]; end else - RPARITY_B2 = 2'bx; + RPARITY_B2 <= 2'bx; end endgenerate @@ -370,22 +504,43 @@ module TDP_RAM18KX2 #( a = 0; for (b = 0; b < 2**RAM2_ADDR_WIDTH; b = b + 1) for (c = 0; c < RAM2_DATA_WIDTH; c = c + 1) begin + /* verilator lint_off INITIALDLY */ RAM2_DATA[b][c] <= INIT2[a]; + /* verilator lint_on INITIALDLY */ a = a + 1; end end + always @(temp_WDATA_A2) + /* verilator lint_off WIDTH */ + RAM2_DATA[a2_addr][l] = temp_WDATA_A2; + /* verilator lint_on WIDTH */ + // Base RAM read/write functionality always @(posedge CLK_A2) if (WEN_A2) begin //$display("AADR_A: %b index: %d", ADDR_A2, find_a2_write_index(ADDR_A2)*8); for (l = find_a2_write_index(ADDR_A2)*A2_DATA_WRITE_WIDTH; l < find_a2_write_index(ADDR_A2)*A2_DATA_WRITE_WIDTH+A2_DATA_WRITE_WIDTH; l = l + 1) begin if (A2_DATA_WRITE_WIDTH > 9) begin - if (BE_A2[l/8] == 1'b1) + if (BE_A2[l/8] == 1'b1) begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WDATA_A2 <= WDATA_A2[l-(find_a2_write_index(ADDR_A2)*A2_DATA_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else + RAM2_DATA[a2_addr][l] <= WDATA_A2[l-(find_a2_write_index(ADDR_A2)*A2_DATA_WRITE_WIDTH)]; + `endif + end + end + else begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WDATA_A2 <= WDATA_A2[l-(find_a2_write_index(ADDR_A2)*A2_DATA_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else RAM2_DATA[a2_addr][l] <= WDATA_A2[l-(find_a2_write_index(ADDR_A2)*A2_DATA_WRITE_WIDTH)]; + `endif end - else - RAM2_DATA[a2_addr][l] <= WDATA_A2[l-(find_a2_write_index(ADDR_A2)*A2_DATA_WRITE_WIDTH)]; end collision_a2_address = a2_addr; collision_a2_write_flag = 1; @@ -405,15 +560,34 @@ module TDP_RAM18KX2 #( else RDATA_A2 = 16'bx; + always @(temp_WDATA_B2) + /* verilator lint_off WIDTH */ + RAM2_DATA[b2_addr][p] = temp_WDATA_B2; + /* verilator lint_on WIDTH */ + always @(posedge CLK_B2) if (WEN_B2) begin for (p = find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH; p < find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH+B2_DATA_WRITE_WIDTH; p = p + 1) begin if (B2_DATA_WRITE_WIDTH > 9) begin - if (BE_B2[p/8] == 1'b1) - RAM2_DATA[b2_addr][p] <= WDATA_B2[p-(find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH)]; + if (BE_B2[p/8] == 1'b1) begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WDATA_B2 <= WDATA_B2[p-(find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else + RAM2_DATA[b2_addr][p] <= WDATA_B2[p-(find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH)]; + `endif + end end - else - RAM2_DATA[b2_addr][p] <= WDATA_B2[p-(find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH)]; + else begin + `ifdef SIM_VERILATOR + /* verilator lint_off WIDTH */ + temp_WDATA_B2 <= WDATA_B2[p-(find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH)]; + /* verilator lint_on WIDTH */ + `else + RAM2_DATA[b2_addr][p] <= WDATA_B2[p-(find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH)]; + `endif + end end collision_b2_address = b2_addr; @@ -476,8 +650,12 @@ module TDP_RAM18KX2 #( if (RAM1_ADDR_WIDTH == A1_WRITE_ADDR_WIDTH) find_a1_write_index = 0; - else - find_a1_write_index = ADDR_A1[13-RAM1_ADDR_WIDTH:14-A1_WRITE_ADDR_WIDTH]; + else + /* verilator lint_off SELRANGE */ + /* verilator lint_off WIDTH */ + find_a1_write_index = ADDR_A1[13-RAM1_ADDR_WIDTH:14-A1_WRITE_ADDR_WIDTH]; + /* verilator lint_on SELRANGE */ + /* verilator lint_on WIDTH */ endfunction @@ -486,8 +664,12 @@ module TDP_RAM18KX2 #( if (RAM1_ADDR_WIDTH == A1_READ_ADDR_WIDTH) find_a1_read_index = 0; - else + else + /* verilator lint_off SELRANGE */ + /* verilator lint_off WIDTH */ find_a1_read_index = ADDR_A1[13-RAM1_ADDR_WIDTH:14-A1_READ_ADDR_WIDTH]; + /* verilator lint_on SELRANGE */ + /* verilator lint_on WIDTH */ endfunction @@ -496,8 +678,12 @@ module TDP_RAM18KX2 #( if (RAM1_ADDR_WIDTH == B1_WRITE_ADDR_WIDTH) find_b1_write_index = 0; - else - find_b1_write_index = ADDR_B1[13-RAM1_ADDR_WIDTH:14-B1_WRITE_ADDR_WIDTH]; + else + /* verilator lint_off SELRANGE */ + /* verilator lint_off WIDTH */ + find_b1_write_index = ADDR_B1[13-RAM1_ADDR_WIDTH:14-B1_WRITE_ADDR_WIDTH]; + /* verilator lint_on SELRANGE */ + /* verilator lint_on WIDTH */ endfunction @@ -506,8 +692,12 @@ module TDP_RAM18KX2 #( if (RAM1_ADDR_WIDTH == B1_READ_ADDR_WIDTH) find_b1_read_index = 0; - else - find_b1_read_index = ADDR_B1[13-RAM1_ADDR_WIDTH:14-B1_READ_ADDR_WIDTH]; + else + /* verilator lint_off SELRANGE */ + /* verilator lint_off WIDTH */ + find_b1_read_index = ADDR_B1[13-RAM1_ADDR_WIDTH:14-B1_READ_ADDR_WIDTH]; + /* verilator lint_on SELRANGE */ + /* verilator lint_on WIDTH */ endfunction @@ -516,8 +706,12 @@ module TDP_RAM18KX2 #( if (RAM2_ADDR_WIDTH == A2_WRITE_ADDR_WIDTH) find_a2_write_index = 0; - else - find_a2_write_index = ADDR_A2[13-RAM2_ADDR_WIDTH:14-A2_WRITE_ADDR_WIDTH]; + else + /* verilator lint_off SELRANGE */ + /* verilator lint_off WIDTH */ + find_a2_write_index = ADDR_A2[13-RAM2_ADDR_WIDTH:14-A2_WRITE_ADDR_WIDTH]; + /* verilator lint_on SELRANGE */ + /* verilator lint_on WIDTH */ endfunction @@ -526,8 +720,12 @@ module TDP_RAM18KX2 #( if (RAM2_ADDR_WIDTH == A2_READ_ADDR_WIDTH) find_a2_read_index = 0; - else - find_a2_read_index = ADDR_A2[13-RAM2_ADDR_WIDTH:14-A2_READ_ADDR_WIDTH]; + else + /* verilator lint_off SELRANGE */ + /* verilator lint_off WIDTH */ + find_a2_read_index = ADDR_A2[13-RAM2_ADDR_WIDTH:14-A2_READ_ADDR_WIDTH]; + /* verilator lint_on SELRANGE */ + /* verilator lint_on WIDTH */ endfunction @@ -536,8 +734,12 @@ module TDP_RAM18KX2 #( if (RAM2_ADDR_WIDTH == B2_WRITE_ADDR_WIDTH) find_b2_write_index = 0; - else - find_b2_write_index = ADDR_B2[13-RAM2_ADDR_WIDTH:14-B2_WRITE_ADDR_WIDTH]; + else + /* verilator lint_off SELRANGE */ + /* verilator lint_off WIDTH */ + find_b2_write_index = ADDR_B2[13-RAM2_ADDR_WIDTH:14-B2_WRITE_ADDR_WIDTH]; + /* verilator lint_on SELRANGE */ + /* verilator lint_on WIDTH */ endfunction @@ -546,8 +748,12 @@ module TDP_RAM18KX2 #( if (RAM2_ADDR_WIDTH == B2_READ_ADDR_WIDTH) find_b2_read_index = 0; - else - find_b2_read_index = ADDR_B2[13-RAM2_ADDR_WIDTH:14-B2_READ_ADDR_WIDTH]; + else + /* verilator lint_off SELRANGE */ + /* verilator lint_off WIDTH */ + find_b2_read_index = ADDR_B2[13-RAM2_ADDR_WIDTH:14-B2_READ_ADDR_WIDTH]; + /* verilator lint_on SELRANGE */ + /* verilator lint_on WIDTH */ endfunction diff --git a/sim_models_internal/verilog/TDP_RAM36K.v b/sim_models_internal/verilog/TDP_RAM36K.v index 9129c29..409dd01 100644 --- a/sim_models_internal/verilog/TDP_RAM36K.v +++ b/sim_models_internal/verilog/TDP_RAM36K.v @@ -94,7 +94,7 @@ module TDP_RAM36K #( for (h_p = 0; h_p < RAM_PARITY_WIDTH; h_p = h_p + 1) begin /* verilator lint_off INITIALDLY */ RAM_PARITY[g_p][h_p] <= INIT_PARITY[f_p]; - /* verilator lint_off INITIALDLY */ + /* verilator lint_on INITIALDLY */ f_p = f_p + 1; end end