From 234dd2e19395c4246bfa5505be5b70dc3e39c96a Mon Sep 17 00:00:00 2001
From: moinijaz <moin.ijaz9@gmail.com>
Date: Tue, 3 Dec 2024 14:15:35 +0500
Subject: [PATCH 1/3] simulation updated for io_config

---
 .../ip/io_configurator/v1_0/sim/Makefile      |   2 -
 .../ip/io_configurator/v1_0/sim/PLL.v         | 447 ++++++++++--------
 .../v1_0/sim/io_configurator_v1_0.v           |   2 -
 3 files changed, 256 insertions(+), 195 deletions(-)

diff --git a/rapidsilicon/ip/io_configurator/v1_0/sim/Makefile b/rapidsilicon/ip/io_configurator/v1_0/sim/Makefile
index 77f0c189..90707b0d 100644
--- a/rapidsilicon/ip/io_configurator/v1_0/sim/Makefile
+++ b/rapidsilicon/ip/io_configurator/v1_0/sim/Makefile
@@ -2,8 +2,6 @@
 #
 # SPDX-License-Identifier: MIT
 
-MODULE_NAME ?= on_chip_memory
-
 OUT_DIR ?= $(PWD)
 
 all:
diff --git a/rapidsilicon/ip/io_configurator/v1_0/sim/PLL.v b/rapidsilicon/ip/io_configurator/v1_0/sim/PLL.v
index 65179887..509f82a6 100644
--- a/rapidsilicon/ip/io_configurator/v1_0/sim/PLL.v
+++ b/rapidsilicon/ip/io_configurator/v1_0/sim/PLL.v
@@ -1,4 +1,4 @@
-`timescale 1fs/1fs
+`timescale 1ps/10fs
 `celldefine
 //
 // PLL simulation model
@@ -8,226 +8,291 @@
 //
 
 module PLL #(
+  parameter DEV_FAMILY = "VIRGO", // Device Family
   parameter DIVIDE_CLK_IN_BY_2 = "FALSE", // Enable input divider (TRUE/FALSE)
-  parameter PLL_MULT = 16, // VCO clock multiplier value (16-1000)
+  parameter PLL_MULT = 16, // VCO clock multiplier value (16-640)
   parameter PLL_DIV = 1, // VCO clock divider value (1-63)
-  parameter PLL_POST_DIV = 2 // VCO clock post-divider value (2,4,6,8,10,12,14,16,18,20,24,28,30,32,36,40,42,48,50,56,60,70,72,84,98)
+  parameter PLL_MULT_FRAC = 0, // Fraction mode not supported
+  parameter PLL_POST_DIV = 17 // VCO clock post-divider value (17,18,19,20,21,22,23,34,35,36,37,38,39,51,52,53,54,55,68,69,70,71,85,86,87,102,103,119)
 ) (
   input PLL_EN, // PLL Enable
   input CLK_IN, // Clock input
-  output reg CLK_OUT = 1'b0, // Output clock, frequency is CLK_IN_FREQ*PLL_MULT/PLL_DIV/PLL_POST_DIV
-  output reg CLK_OUT_DIV2 = 1'b0, // CLK_OUT divided by 2 output
-  output reg CLK_OUT_DIV3 = 1'b0, // CLK_OUT divided by 3 output
-  output reg CLK_OUT_DIV4 = 1'b0, // CLK_OUT divided by 4 output
-  output reg SERDES_FAST_CLK = 1'b0, // Gearbox fast clock output
-  output reg LOCK = 1'b0 // PLL lock signal
+  output CLK_OUT, // Output clock, frequency is (CLK_IN/PLL_DIV)*(PLL_MULT/(PLL_POST_DIV0*PLL_POST_DIV1))
+  output CLK_OUT_DIV2, // CLK_OUT divided by 2 output
+  output CLK_OUT_DIV3, // CLK_OUT divided by 3 output
+  output CLK_OUT_DIV4, // CLK_OUT divided by 4 output
+  output FAST_CLK, // VCO clock output, frequency is (CLK_IN/PLL_DIV)*(PLL_MULT)
+  output LOCK // PLL lock signal
 );
 
-localparam div_input_clk = (DIVIDE_CLK_IN_BY_2=="TRUE") ? 2 : 1;
-
-localparam clk_in_max_period = (DIVIDE_CLK_IN_BY_2=="TRUE") ? 125000000/2 : 125000000;
-localparam clk_in_min_period = (DIVIDE_CLK_IN_BY_2=="TRUE") ? 2000000/2 : 2000000;
-
-localparam vco_max_period = 1250000;
-localparam vco_min_period = 312000;
-
-time clk_in_period = 0;
-time old_clk_in_period = 0;
-time clk_in_start;
-time vco_period = vco_max_period;
-
-reg pll_start = 1'b0;
-reg vco_clk_start = 1'b0;
-reg clk_out_start = 1'b0;
-integer vco_count = (PLL_MULT*PLL_DIV*2);
-integer div3_count = 1;
-reg [3:0] clk_in_count = 4'h0;
-reg [3:0] old_clk_in_count = 4'h0;
-
-always begin
-  LOCK = 1'b0;
-  pll_start = 1'b0;
-  clk_in_period = 0;
-  clk_in_count = 4'h0;
-  old_clk_in_count = 4'h0;
-  vco_period = 1250000;
-  vco_clk_start = 1'b0;
-  clk_out_start = 1'b0;
-  div3_count = 1;
-  vco_count = (PLL_MULT*PLL_DIV*2);
-  SERDES_FAST_CLK = 1'b0;
-  CLK_OUT = 1'b0;
-  CLK_OUT_DIV2 = 1'b0;
-  CLK_OUT_DIV3 = 1'b0;
-  CLK_OUT_DIV4 = 1'b0;
-  #100;
-  if (PLL_EN) begin
-    pll_start = 1'b1;
-    @(negedge PLL_EN, negedge LOCK);
-  end else
-    @(posedge PLL_EN);
-end
-
-always @(posedge pll_start) begin
-  repeat(9)
-    @(posedge CLK_IN);
-  vco_clk_start = 1'b1;
-  repeat (10)
-    @(posedge SERDES_FAST_CLK);
-  @(posedge CLK_IN);
-  clk_out_start = 1'b1;      
-  repeat (5)
-    @(posedge CLK_OUT);
-  LOCK = 1'b1;
-end
-
-always
-  if (vco_clk_start) begin
-    if (vco_count==(PLL_MULT*PLL_DIV*2)) begin
-      SERDES_FAST_CLK = 1'b0;
-      @(posedge CLK_IN);
-      vco_count = 1;
-    end else begin
-      SERDES_FAST_CLK = ~SERDES_FAST_CLK;
-      #(vco_period/2);
-      vco_count = vco_count + 1;
-    end 
-  end else begin
-    SERDES_FAST_CLK = 1'b0;
-    @(posedge CLK_IN);
-  end
+	localparam      FAST_LOCK      = 0; // Reduce lock time
 
-always @(posedge SERDES_FAST_CLK) begin
-  if (clk_out_start) begin
-    CLK_OUT = ~CLK_OUT;
-    repeat ((PLL_POST_DIV/2)-1)
-      @(posedge SERDES_FAST_CLK);
-  end else begin
-    CLK_OUT = 1'b0;
-  end
-end
-
-always @(posedge CLK_OUT)
-  CLK_OUT_DIV2 = ~CLK_OUT_DIV2;
-
-always @(CLK_OUT)
-  if (div3_count==2) begin
-    CLK_OUT_DIV3 = ~CLK_OUT_DIV3;
-    div3_count = 0;
-  end else
-    div3_count = div3_count + 1;
-
-always @(posedge CLK_OUT_DIV2)
-  CLK_OUT_DIV4 = ~CLK_OUT_DIV4;
-
-always @(posedge CLK_IN)
-  if (pll_start) begin
-    clk_in_start = $realtime;
-    if (LOCK)
-      clk_in_count = clk_in_count + 1'b1;
-
-    @(posedge CLK_IN);
-    if (clk_in_period == 0)
-      old_clk_in_period = $realtime - clk_in_start;
-    else
-      old_clk_in_period = clk_in_period;
-
-    clk_in_period = $realtime - clk_in_start;
-    vco_period = clk_in_period * div_input_clk  * PLL_DIV / PLL_MULT;
-    clk_in_start = $realtime;
-    if (LOCK)
-      clk_in_count = clk_in_count + 1'b1;
-    if (clk_in_period < clk_in_min_period) begin
-      $display("Warning at time %t: PLL instance %m input clock, CLK_IN, is too fast.", $realtime);
-      LOCK = 1'b0;
-    end
-    if (clk_in_period > clk_in_max_period) begin
-      $display("Warning at time %t: PLL instance %m input clock, CLK_IN, is too slow.", $realtime);
-      LOCK = 1'b0;
-    end
-    if ((LOCK==1'b1) && (clk_in_period > old_clk_in_period*1.05) || (clk_in_period < old_clk_in_period*0.95)) begin
-      $display("Warning at time %t: PLL instance %m input clock, CLK_IN, changed frequency and lost lock.", $realtime);
-      LOCK = 1'b0;
-    end
-  end
+	localparam real REF_MAX_PERIOD = PLL_MULT_FRAC ? 100000: 200000; //10 MHz or 5 MHz
+	localparam real REF_MIN_PERIOD = 833.33                        ; //1200 MHz
+
+	localparam real VCO_MAX_PERIOD = 62500; //16 MHz
+	localparam real VCO_MIN_PERIOD = 312.5; //3200 MHz
+
+
+	localparam LOCK_TIMER = FAST_LOCK ? 10 : 500;
+
+	logic [ 2:0] PLL_POST_DIV0;
+	logic [ 2:0] PLL_POST_DIV1;
+
+	assign PLL_POST_DIV0 = PLL_POST_DIV[2:0];
+	assign PLL_POST_DIV1 = PLL_POST_DIV[6:4];
+//---------------------------
+  real         t0                ;
+  real         t1                ;
+  real         ref_period        ;
+  real         vco_period        ;
+  real         postdiv_period    ;
+  real         old_ref_period    ;
+  logic          clk_pll           ;
+  logic          pllen_rse         ;
+  logic          pllstart       = 0;
+  logic          pllstart_ff1   = 0;
+  logic          pllstart_ff2   = 0;
+  logic          vcostart       = 0;
+  logic          vcostart_ff    = 0;
+  logic          lose_lock      = 0;
+  logic          clk_out_div2   = 0;
+  logic          clk_out_div3   = 0;
+  logic          clk_out_div4   = 0;
+  logic          clk_vco           ;
+  logic          clk_postdiv       ;
+  integer        div3_count     = 1;
+  logic   [ 5:0] PLL_DIV_ff     = 0;
+  logic   [11:0] PLL_MULT_ff    = 0;
+
+	logic [$clog2(LOCK_TIMER)-1:0] lock_counter = 0;
+
+
+	assign pllen_rse = pllstart==1 && pllstart_ff2==0;
+
+	always @ (posedge  CLK_IN) begin
+		if(PLL_EN) pllstart <= 1;
+		else      pllstart <= 0;
+
+		pllstart_ff1 <= pllstart;
+		pllstart_ff2 <= pllstart_ff1;
+
+	end
+
+	always @ (posedge  CLK_IN) begin
+		if(pllstart_ff2) vcostart <= 1;
+		else             vcostart <= 0;
+
+		vcostart_ff <= vcostart;
+	end
+
+
+	always @ (posedge  CLK_IN) begin
+		@(posedge CLK_IN) t0 = $realtime;
+		@(posedge CLK_IN) t1 = $realtime;
+		ref_period = t1 - t0;
+		vco_period = DIVIDE_CLK_IN_BY_2=="TRUE" ? (ref_period*PLL_DIV*2)/PLL_MULT : (ref_period*PLL_DIV)/PLL_MULT;
+    postdiv_period = DIVIDE_CLK_IN_BY_2=="TRUE" ? (ref_period*PLL_DIV*2*PLL_POST_DIV0*PLL_POST_DIV1)/PLL_MULT : (ref_period*PLL_DIV*PLL_POST_DIV0*PLL_POST_DIV1)/PLL_MULT;
+	end
+
+	always @ (posedge  CLK_IN) begin
+		old_ref_period = ref_period;
+	end
+
+	initial begin
+		clk_vco = 0;
+		forever begin
+			wait(vcostart_ff)
+				#(vco_period/2) clk_vco = PLL_EN ? ~clk_vco : '0;
+		end
+	end
 
-// Checking for proper CLK_IN and VCO frequencies
-always
-  if (LOCK) begin
-    #(5*clk_in_period);
-    if (clk_in_count == old_clk_in_count) begin
-      $display("Warning at time %t: PLL instance %m input clock, CLK_IN, has stopped.", $realtime);
-      LOCK = 1'b0;
-    end else
-      old_clk_in_count = clk_in_count;
-    if (vco_period<vco_min_period) begin
-      $display("\nError at time %t: PLL instance %m VCO clock period %0d fs violates minimum period.\nMust be greater than %0d fs.\nTry increasing PLL_DIV or decreasing PLL_MULT values.\n", $realtime, vco_period, vco_min_period);
-      $stop;
-    end else if (vco_period>vco_max_period) begin
-      $display("\nError at time %t: PLL instance %m VCO clock period %0d fs violates maximum period.\nMust be less than %0d fs.\nTry increasing PLL_MULT or decreasing PLL_DIV values.\n", $realtime, vco_period, vco_max_period);
-      $stop;
-    end
-  end else
-    @(posedge LOCK);
 
   initial begin
-   
-    if (int'(1fs) == 1) begin 
-      $display("");
-    end
-    else begin
-      $display("\n** Error: The timescale for PLL must be set to 1fs/1fs **\n");
-      #1 $stop;
+    clk_postdiv = 0;
+    forever begin
+      wait(vcostart_ff)
+        #(postdiv_period/2) clk_postdiv = PLL_EN ? ~clk_postdiv : '0;
     end
-  end
+  end  
+
+
+	always @(posedge CLK_IN) begin
+		PLL_DIV_ff  <= PLL_DIV;
+		PLL_MULT_ff <= PLL_MULT;
+	end
+
+	always @ (posedge  CLK_IN, negedge PLL_EN) begin
+		if(LOCK==0 & vcostart) lock_counter <= lock_counter + 1;
+		else if(lose_lock || PLL_EN==0 || PLL_MULT_ff!=PLL_MULT || PLL_DIV_ff!=PLL_DIV )     lock_counter <= 0;
+	end
+
+
+	always @(posedge CLK_OUT, negedge PLL_EN)
+		if(PLL_EN==0) clk_out_div2 = 1'b0;
+		else          clk_out_div2 = ~clk_out_div2;
+
+	always @(CLK_OUT, negedge PLL_EN)
+		if(PLL_EN==0) clk_out_div3 = 1'b0;
+		else begin
+			if (div3_count==2) begin
+				clk_out_div3 = ~clk_out_div3;
+				div3_count   = 0;
+			end else
+			div3_count = div3_count + 1;
+		end
+
+	always @(posedge clk_out_div2, negedge PLL_EN)
+		if(PLL_EN==0) clk_out_div4 = 1'b0;
+		else          clk_out_div4 = ~clk_out_div4;
+
+
+	assign CLK_OUT      = (PLL_POST_DIV0==1 && PLL_POST_DIV0==1) ? clk_vco : clk_postdiv;
+	assign CLK_OUT_DIV2 = clk_out_div2;
+	assign CLK_OUT_DIV3 = clk_out_div3;
+	assign CLK_OUT_DIV4 = clk_out_div4;
+	assign FAST_CLK     = clk_vco;
+	assign LOCK         = lock_counter >= LOCK_TIMER;
+
+
+
+	// Checking for proper CLK_IN and VCO frequencies
+	always @ (posedge CLK_IN) begin
+		if(pllstart_ff2)begin
+			if (ref_period<VCO_MIN_PERIOD) begin
+				$fatal(1,"\nError at time %t: PLL instance %m REF clock period %0d fs violates minimum period.\nMust be greater than %0d fs.\n", $realtime, ref_period, VCO_MIN_PERIOD);
+			end
+			else if (ref_period>VCO_MAX_PERIOD) begin
+				$fatal(1,"\nError at time %t: PLL instance %m REF clock period %0d fs violates maximum period.\nMust be less than %0d fs.\n", $realtime, ref_period, VCO_MAX_PERIOD);
+			end
+		end
+	end
+
+
+	always @ (posedge CLK_IN) begin
+		if ((LOCK==1'b1) && (ref_period > old_ref_period*1.05) || (ref_period < old_ref_period*0.95)) begin
+			$display("Warning at time %t: PLL instance %m input clock, CLK_IN, changed frequency and lost lock. Current value = %0d fs, old value = %d fs.\n", $realtime, ref_period, old_ref_period);
+			lose_lock = 1;
+		end
+		else lose_lock = 0;
+	end
+
+	always @ (posedge FAST_CLK) begin
+		if(vcostart_ff) begin
+			if (vco_period<VCO_MIN_PERIOD) begin
+				$fatal(1,"\nError at time %t: PLL instance %m VCO clock period %0d fs violates minimum period.\nMust be greater than %0d fs.\nTry increasing PLL_DIV or decreasing PLL_MULT values.\n", $realtime, vco_period, VCO_MIN_PERIOD);
+			end
+			else if (vco_period>VCO_MAX_PERIOD) begin
+				$fatal(1,"\nError at time %t: PLL instance %m VCO clock period %0d fs violates maximum period.\nMust be less than %0d fs.\nTry increasing PLL_MULT or decreasing PLL_DIV values.\n", $realtime, vco_period, VCO_MAX_PERIOD);
+			end
+		end
+	end
+
+
+
+	// Checking control inputs
+	always @ (posedge CLK_IN, posedge PLL_EN) begin
+		if(PLL_EN)begin
+			if(PLL_POST_DIV0==0)begin
+				$fatal(1,"Error at time %t: \n \t PLL instance %m, PLL_POST_DIV0 is equal to zero.\n \t Must be greater than 0", $realtime);
+			end
+
+			else if(PLL_POST_DIV1==0)begin
+				$fatal(1,"Error at time %t: \n \t PLL instance %m, PLL_POST_DIV1 is equal to zero.\n \t Must be greater than 0", $realtime);
+			end
+
+
+			else if(PLL_POST_DIV1>PLL_POST_DIV0) begin
+				$fatal(1,"Error at time %t: PLL_POST_DIV1 > PLL_POST_DIV0\n", $realtime);
+			end
+		end
+	end
+
+
+`ifndef SYNTHESIS  
+	`ifdef TIMED_SIM
+	  specparam T1 = 5;
+	  specparam T2 = 0.5;
+  
+		specify
+  
+				  (CLK_IN => CLK_OUT)      = (T1);
+				  (CLK_IN => CLK_OUT_DIV2) = (T1);
+				  (CLK_IN => CLK_OUT_DIV3) = (T1);
+				  (CLK_IN => CLK_OUT_DIV4) = (T1);
+				  (CLK_IN => FAST_CLK)     = (T1);
+  
+				  (negedge CLK_IN => (LOCK +: 0)) = (T1);
+				  (negedge PLL_EN => (LOCK +: 0)) = (T1);
+				  (posedge CLK_IN => (LOCK +: 0)) = (T1);
+				  (posedge PLL_EN => (LOCK +: 0)) = (T1);
+  
+				  $setuphold (posedge CLK_IN, negedge PLL_EN, T2, notifier);
+				  $setuphold (posedge CLK_IN, posedge PLL_EN, T2, notifier);
+				  $setuphold (negedge CLK_IN, negedge PLL_EN, T2, notifier);
+				  $setuphold (negedge CLK_IN, posedge PLL_EN, T2, notifier);
+		endspecify
+	`endif // `ifdef TIMED_SIM  
+`endif //  `ifndef SYNTHESIS
    initial begin
+    case(DEV_FAMILY)
+      "VIRGO": begin end
+      default: begin
+        $fatal(1,"\nError: PLL instance %m has parameter DEV_FAMILY set to %s.  Valid values are VIRGO\n", DEV_FAMILY);
+      end
+    endcase
     case(DIVIDE_CLK_IN_BY_2)
       "TRUE" ,
       "FALSE": begin end
       default: begin
-        $display("\nError: PLL instance %m has parameter DIVIDE_CLK_IN_BY_2 set to %s.  Valid values are TRUE, FALSE\n", DIVIDE_CLK_IN_BY_2);
-        #1 $stop ;
+        $fatal(1,"\nError: PLL instance %m has parameter DIVIDE_CLK_IN_BY_2 set to %s.  Valid values are TRUE, FALSE\n", DIVIDE_CLK_IN_BY_2);
       end
     endcase
 
-    if ((PLL_MULT < 16) || (PLL_MULT > 1000)) begin
-       $display("PLL instance %m PLL_MULT set to incorrect value, %d.  Values must be between 16 and 1000.", PLL_MULT);
-    #1 $stop;
+    if ((PLL_MULT < 16) || (PLL_MULT > 640)) begin
+       $fatal(1,"PLL instance %m PLL_MULT set to incorrect value, %d.  Values must be between 16 and 640.", PLL_MULT);
     end
 
     if ((PLL_DIV < 1) || (PLL_DIV > 63)) begin
-       $display("PLL instance %m PLL_DIV set to incorrect value, %d.  Values must be between 1 and 63.", PLL_DIV);
-    #1 $stop;
+       $fatal(1,"PLL instance %m PLL_DIV set to incorrect value, %d.  Values must be between 1 and 63.", PLL_DIV);
     end
+    case(PLL_MULT_FRAC)
+      0: begin end
+      default: begin
+        $fatal(1,"\nError: PLL instance %m has parameter PLL_MULT_FRAC set to %d.  Valid values are 0\n", PLL_MULT_FRAC);
+      end
+    endcase
     case(PLL_POST_DIV)
-      2 ,
-      4 ,
-      6 ,
-      8 ,
-      10 ,
-      12 ,
-      14 ,
-      16 ,
+      17 ,
       18 ,
+      19 ,
       20 ,
-      24 ,
-      28 ,
-      30 ,
-      32 ,
+      21 ,
+      22 ,
+      23 ,
+      34 ,
+      35 ,
       36 ,
-      40 ,
-      42 ,
-      48 ,
-      50 ,
-      56 ,
-      60 ,
+      37 ,
+      38 ,
+      39 ,
+      51 ,
+      52 ,
+      53 ,
+      54 ,
+      55 ,
+      68 ,
+      69 ,
       70 ,
-      72 ,
-      84 ,
-      98: begin end
+      71 ,
+      85 ,
+      86 ,
+      87 ,
+      102 ,
+      103 ,
+      119: begin end
       default: begin
-        $display("\nError: PLL instance %m has parameter PLL_POST_DIV set to %d.  Valid values are 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 24, 28, 30, 32, 36, 40, 42, 48, 50, 56, 60, 70, 72, 84, 98\n", PLL_POST_DIV);
-        #1 $stop ;
+        $fatal(1,"\nError: PLL instance %m has parameter PLL_POST_DIV set to %d.  Valid values are 17, 18, 19, 20, 21, 22, 23, 34, 35, 36, 37, 38, 39, 51, 52, 53, 54, 55, 68, 69, 70, 71, 85, 86, 87, 102, 103, 119\n", PLL_POST_DIV);
       end
     endcase
 
diff --git a/rapidsilicon/ip/io_configurator/v1_0/sim/io_configurator_v1_0.v b/rapidsilicon/ip/io_configurator/v1_0/sim/io_configurator_v1_0.v
index 12abcb0f..148be8a7 100644
--- a/rapidsilicon/ip/io_configurator/v1_0/sim/io_configurator_v1_0.v
+++ b/rapidsilicon/ip/io_configurator/v1_0/sim/io_configurator_v1_0.v
@@ -69,10 +69,8 @@ BOOT_CLOCK BOOT_CLOCK(
 );
 
 PLL #(
-	.DIVIDE_CLK_IN_BY_2("FALSE"),
 	.PLL_DIV(1'd1),
 	.PLL_MULT(7'd80),
-	.PLL_POST_DIV(2'd2)
 ) PLL (
 	.CLK_IN(lo_clk),
 	.PLL_EN(1'd1),

From a44040f98992ba9275a510a957f2cb1dd19d9b6c Mon Sep 17 00:00:00 2001
From: moinijaz <moin.ijaz9@gmail.com>
Date: Tue, 3 Dec 2024 14:44:08 +0500
Subject: [PATCH 2/3] summary updated in io_config for delays

---
 .../v1_0/io_configurator_gen.py               | 25 ++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/rapidsilicon/ip/io_configurator/v1_0/io_configurator_gen.py b/rapidsilicon/ip/io_configurator/v1_0/io_configurator_gen.py
index 1afa5ea2..5bdc4b48 100755
--- a/rapidsilicon/ip/io_configurator/v1_0/io_configurator_gen.py
+++ b/rapidsilicon/ip/io_configurator/v1_0/io_configurator_gen.py
@@ -3338,8 +3338,20 @@ def main():
         elif (args.io_mode == "PULLDOWN"):
             summary["IO_MODE"] = "Logic low in the absence of an external connection"
     
-    if (args.io_model in ["I_SERDES", "O_SERDES", "I_DDR", "O_DDR", "I_DELAY", "O_DELAY"]):
-    # CLOCK
+    if (args.io_model in ["I_SERDES", "O_SERDES", "I_DDR", "O_DDR", "IO_DELAY"]):
+        if (args.io_model == "IO_DELAY"):
+            if (args.io_type == "SINGLE_ENDED"):
+                summary["IO_TYPE"] = "Unidirectional data flow"
+            elif (args.io_type == "DIFFERENTIAL"):
+                summary["IO_TYPE"] = "Noise-resistant data transfer"
+            
+            if (args.io_mode == "NONE"):
+                summary["IO_MODE"] = "No internal pull-up or pull-down resistor enabled"
+            elif (args.io_mode == "PULLUP"):
+                summary["IO_MODE"] = "Logic high in the absence of an external connection"
+            elif (args.io_mode == "PULLDOWN"):
+                summary["IO_MODE"] = "Logic low in the absence of an external connection"
+        # CLOCK
         if (args.clocking == "RX_CLOCK"):
             summary["CLOCK"] = "IOPAD provides the clock signal"
         elif (args.clocking == "PLL"):
@@ -3384,8 +3396,15 @@ def main():
         if (args.io_model == "O_SERDES"):
             summary["CLOCK_FORWARDING"] = args.clock_forwarding
         
-    elif (args.io_model in ["I_DELAY", "I_DELAY_I_SERDES", "I_DELAY_I_DDR", "O_DELAY", "O_DELAY_O_SERDES", "O_DELAY_O_DDR"]):
+    elif (args.io_model in ["IO_DELAY"]):
         summary["TAP_DELAY_VALUE"] = args.delay
+        if (args.direction == "UNIDIRECTIONAL"):
+            if (args.combination in ["I_DELAY", "I_DELAY_I_SERDES", "I_DELAY_I_DDR"]):
+                summary["UTILIZATION"] = str(args.num_idly) + " " + args.combination
+            elif (args.combination in ["O_DELAY", "O_DELAY_O_SERDES", "O_DELAY_O_DDR"]):
+                summary["UTILIZATION"] = str(args.num_odly) + " " + args.combination
+        elif (args.direction == "BIDIRECTIONAL"):
+            summary["UTILIZATION"] = str(args.num_dly) + " " + args.combination
     
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:

From 14afa58b1fc87032adf8d63ec176c2912487d2c1 Mon Sep 17 00:00:00 2001
From: moinijaz <moin.ijaz9@gmail.com>
Date: Tue, 3 Dec 2024 14:46:56 +0500
Subject: [PATCH 3/3] updated defines for consistency

---
 rapidsilicon/ip/io_configurator/v1_0/io_configurator_gen.py | 4 ++--
 rapidsilicon/ip/io_configurator/v1_0/src/DLY_CONFIG.v       | 4 ++--
 rapidsilicon/ip/io_configurator/v1_0/src/header.vh          | 3 ++-
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/rapidsilicon/ip/io_configurator/v1_0/io_configurator_gen.py b/rapidsilicon/ip/io_configurator/v1_0/io_configurator_gen.py
index 5bdc4b48..e3a52646 100755
--- a/rapidsilicon/ip/io_configurator/v1_0/io_configurator_gen.py
+++ b/rapidsilicon/ip/io_configurator/v1_0/io_configurator_gen.py
@@ -3489,7 +3489,7 @@ def main():
         
         # io models defines
         if (args.direction == "UNIDIRECTIONAL"):
-            defines.append("`define unidirectional\n")
+            defines.append("`define UNIDIRECTIONAL\n")
             if (args.combination == "I_DELAY"):
                 defines.append("`define I_DELAY\n")
                 
@@ -3509,7 +3509,7 @@ def main():
                 defines.append("`define O_DDR_O_DELAY\n")
                 
         elif (args.direction == "BIDIRECTIONAL"):
-            defines.append("`define bidirectional\n")
+            defines.append("`define BIDIRECTIONAL\n")
             if (args.combination == "I_DELAY+O_DELAY"):
                 defines.append("`define I_DELAY_O_DELAY\n")
             
diff --git a/rapidsilicon/ip/io_configurator/v1_0/src/DLY_CONFIG.v b/rapidsilicon/ip/io_configurator/v1_0/src/DLY_CONFIG.v
index dbaccade..a2863c2e 100644
--- a/rapidsilicon/ip/io_configurator/v1_0/src/DLY_CONFIG.v
+++ b/rapidsilicon/ip/io_configurator/v1_0/src/DLY_CONFIG.v
@@ -399,7 +399,7 @@ always @(*) begin
         ACT_IDLY_CNT    = act_dly_cnt(NUM_GB_SITES*NUM_CNTRL);
 end
 
-`ifdef bidirectional
+`ifdef BIDIRECTIONAL
 wire  [(NUM_DLY/2)-1:0] i_buf_out;
 wire  [(NUM_DLY/2)-1:0] odly_out;
 
@@ -1227,7 +1227,7 @@ generate
     end
 endgenerate
 
-`elsif unidirectional
+`elsif UNIDIRECTIONAL
 wire  [NUM_DLY-1:0] i_buf_dout;
 generate
     for(genvar i = 0; i < NUM_DLY; i = i + 1) begin
diff --git a/rapidsilicon/ip/io_configurator/v1_0/src/header.vh b/rapidsilicon/ip/io_configurator/v1_0/src/header.vh
index 5c6b502e..c1db9036 100644
--- a/rapidsilicon/ip/io_configurator/v1_0/src/header.vh
+++ b/rapidsilicon/ip/io_configurator/v1_0/src/header.vh
@@ -1,3 +1,4 @@
 `define RX_CLOCK
 `define I_DELAY
-`define SINGLE_ENDED
\ No newline at end of file
+`define SINGLE_ENDED
+`define UNIDIRECTIONAL
\ No newline at end of file