diff --git a/EDA-3249/I_DELAY_primitive_inst/I_DELAY_primitive_inst.ospr b/EDA-3249/I_DELAY_primitive_inst/I_DELAY_primitive_inst.ospr new file mode 100644 index 00000000..7f4be4d5 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/I_DELAY_primitive_inst.ospr @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/I_DELAY_primitive_inst_analyzer.cmd b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/I_DELAY_primitive_inst_analyzer.cmd new file mode 100644 index 00000000..73347665 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/I_DELAY_primitive_inst_analyzer.cmd @@ -0,0 +1,5 @@ +read_verilog -sv /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog -I../../../.././rtl -I../../../../ -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v + +analyze -top I_DELAY_primitive_inst diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/analysis.rpt b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/analysis.rpt new file mode 100644 index 00000000..45890991 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/analysis.rpt @@ -0,0 +1,149 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.09 +Build : 1.2.3 +Hash : 89d4d1b +Date : Sep 19 2024 +Type : Engineering +Log Time : Thu Sep 19 08:35:00 2024 GMT +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.09 +Build : 1.2.3 +Hash : 89d4d1b +Date : Sep 19 2024 +Type : Engineering +Log Time : Thu Sep 19 08:35:00 2024 GMT + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) + + +-- Executing script file `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/I_DELAY_primitive_inst_analyzer.cmd' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v' to AST representation. +Generating RTLIL representation for module `\I_DELAY_primitive_inst'. +Successfully finished Verilog frontend. + +-- Running command `hierarchy -top I_DELAY_primitive_inst' -- + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst + +3.2. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst +Removed 0 unused modules. + +Dumping file hier_info.json ... + Process module "I_DELAY" +Dumping file port_info.json ... + +End of script. Logfile hash: 561b84ddef, CPU: user 0.03s system 0.01s, MEM: 15.88 MB peak +Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) +Time spent: 94% 4x read_verilog (0 sec), 3% 1x analyze (0 sec), ... diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/hier_info.json b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/hier_info.json new file mode 100644 index 00000000..e102806a --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/hier_info.json @@ -0,0 +1,192 @@ +{ + "fileIDs": { + "1": "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v", + "2": "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v" + }, + "hierTree": [ + { + "file": "2", + "internalSignals": [ + { + "name": "dff", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + } + ], + "language": "SystemVerilog", + "line": 1, + "moduleInsts": [ + { + "file": "2", + "instName": "inst", + "line": 18, + "module": "I_DELAY", + "parameters": [] + } + ], + "parameters": [ + { + "name": "DELAY", + "value": 0 + } + ], + "ports": [ + { + "direction": "Input", + "name": "reset", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "in", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "DLY_LOAD", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "DLY_ADJ", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "DLY_INCDEC", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Output", + "name": "DLY_TAP_VALUE", + "range": { + "lsb": 0, + "msb": 5 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "CLK_IN", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Output", + "name": "O", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + } + ], + "topModule": "I_DELAY_primitive_inst" + } + ], + "modules": { + "I_DELAY": { + "file": "1", + "language": "SystemVerilog", + "line": 337, + "module": "I_DELAY", + "parameters": [ + { + "name": "DELAY", + "value": 0 + } + ], + "ports": [ + { + "direction": "Input", + "name": "I", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "DLY_LOAD", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "DLY_ADJ", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "DLY_INCDEC", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Output", + "name": "DLY_TAP_VALUE", + "range": { + "lsb": 0, + "msb": 5 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "CLK_IN", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Output", + "name": "O", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + } + ] + } + } +} diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/port_info.json b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/port_info.json new file mode 100644 index 00000000..effeab3f --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/port_info.json @@ -0,0 +1,79 @@ +[ + { + "ports": [ + { + "direction": "Input", + "name": "reset", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "in", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "DLY_LOAD", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "DLY_ADJ", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "DLY_INCDEC", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Output", + "name": "DLY_TAP_VALUE", + "range": { + "lsb": 0, + "msb": 5 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "CLK_IN", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Output", + "name": "O", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + } + ], + "topModule": "I_DELAY_primitive_inst" + } +] diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/I_DELAY_primitive_inst_pack.cmd b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/I_DELAY_primitive_inst_pack.cmd new file mode 100644 index 00000000..7dc85e36 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/I_DELAY_primitive_inst_pack.cmd @@ -0,0 +1 @@ +/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/vpr /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --sdc_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc --route_chan_width 160 --suppress_warnings check_rr_node_warnings.log,check_rr_node --clock_modeling ideal --absorb_buffer_luts off --skip_sync_clustering_and_routing_results off --constant_net_method route --post_place_timing_report I_DELAY_primitive_inst_post_place_timing.rpt --device castor62x44_heterogeneous --allow_unrelated_clustering on --allow_dangling_combinational_nodes on --place_delta_delay_matrix_calculation_method dijkstra --gen_post_synthesis_netlist on --post_synth_netlist_unconn_inputs gnd --inner_loop_recompute_divider 1 --max_router_iterations 1500 --timing_report_detail detailed --timing_report_npaths 100 --top I_DELAY_primitive_inst --net_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net --place_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place --route_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route --pack diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/check_rr_node_warnings.log b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/check_rr_node_warnings.log new file mode 100644 index 00000000..e69de29b diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc new file mode 100644 index 00000000..e69de29b diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net new file mode 100644 index 00000000..2f1cd44e --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net @@ -0,0 +1,2666 @@ + + + $clk_buf_$ibuf_CLK_IN $ibuf_DLY_ADJ $ibuf_DLY_INCDEC $ibuf_DLY_LOAD $ibuf_in $ibuf_reset $ifab_$obuf_DLY_TAP_VALUE[0] $ifab_$obuf_DLY_TAP_VALUE[1] $ifab_$obuf_DLY_TAP_VALUE[2] $ifab_$obuf_DLY_TAP_VALUE[3] $ifab_$obuf_DLY_TAP_VALUE[4] $ifab_$obuf_DLY_TAP_VALUE[5] $obuf_O + out:$auto_440 out:$auto_441 out:$auto_442 out:$auto_443 out:$auto_444 out:$auto_445 out:$auto_446 out:$auto_447 out:$auto_448 out:$auto_449 out:$auto_450 out:$auto_451 out:$auto_452 out:$auto_453 out:$f2g_trx_dly_adj_$ibuf_DLY_ADJ out:$f2g_trx_dly_inc_$ibuf_DLY_INCDEC out:$f2g_trx_dly_ld_$ibuf_DLY_LOAD out:$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] out:$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] out:$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] out:$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] out:$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] out:$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] out:dff + $clk_buf_$ibuf_CLK_IN + + + open open open open open $true open open open open open open + open open open open open $ibuf_reset open open open open open open + open open open open open open open open open open open $ibuf_DLY_ADJ + $ibuf_in open open open open open open open open open open open + open open open open $true open + open + open + open + + + clb_lr[0].out[0]->clbouts1 clb_lr[0].out[1]->clbouts1 open clb_lr[0].out[3]->clbouts1 clb_lr[0].out[4]->clbouts1 open clb_lr[0].out[6]->clbouts1 clb_lr[0].out[7]->clbouts1 open clb_lr[0].out[9]->clbouts2 clb_lr[0].out[10]->clbouts2 open clb_lr[0].out[12]->clbouts2 clb_lr[0].out[13]->clbouts2 open clb_lr[0].out[15]->clbouts2 clb_lr[0].out[16]->clbouts3 open clb_lr[0].out[18]->clbouts3 clb_lr[0].out[19]->clbouts3 open clb_lr[0].out[21]->clbouts3 clb_lr[0].out[22]->clbouts3 open + open + open + open + + + open open $clk_buf_$ibuf_CLK_IN open open open open open open open open open open open open open + + + + clb.I00[5]->crossbar0 open open open open open open open open open open open open open open clb.I10[5]->crossbar1 open open clb.I00[5]->crossbar2 open clb.I00[5]->crossbar2 clb.I20[11]->crossbar2 clb.I00[5]->crossbar2 open open open open open open open open open open clb.I00[5]->crossbar4 open clb.I00[5]->crossbar4 open clb.I00[5]->crossbar4 open clb.I30[0]->crossbar4 open open open open open open open open + open clb.IS0[4]->crossbar7 + open open open clb.IS0[4]->crossbar6 + open + open + + + fle[0].out[0]->direct_out0_0 fle[0].out[1]->direct_out1_0 open fle[1].out[0]->direct_out0_1 fle[1].out[1]->direct_out1_1 open fle[2].out[0]->direct_out0_2 fle[2].out[1]->direct_out1_2 open fle[3].out[0]->direct_out0_3 fle[3].out[1]->direct_out1_3 open fle[4].out[0]->direct_out0_4 fle[4].out[1]->direct_out1_4 open fle[5].out[0]->direct_out0_5 fle[5].out[1]->direct_out1_5 open fle[6].out[0]->direct_out0_6 fle[6].out[1]->direct_out1_6 open fle[7].out[0]->direct_out0_7 fle[7].out[1]->direct_out1_7 open + open + open + + + clb.clk[2]->clks + + + + clb_lr.in[0]->direct_in_0 open open open open open + open + open + open open + open open + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + open + + + + fle.in[0]->direct1a open open open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + ble5.in[0]->direct1a open open open open + + + lut[0].out[0]->direct:lut5 + + + + + + + lut5.in[0]->direct:lut5 open open open open + 0 open open open open + + + $auto_446 + + + + + + + + + fle.in[0]->direct1b open open open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + ble5.in[0]->direct1a open open open open + + + lut[0].out[0]->direct:lut5 + + + + + + + lut5.in[0]->direct:lut5 open open open open + 0 open open open open + + + $auto_445 + + + + + + + + + + open open open open clb_lr.in[33]->direct_in_4 open + open + open + open open + open open + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + open + + + + open open open open fle.in[4]->direct1a + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open open open ble5.in[4]->direct1a + + + lut[0].out[0]->direct:lut5 + + + + + + + open open open open lut5.in[4]->direct:lut5 + open open open open 0 + + + $auto_451 + + + + + + + + + open open open open fle.in[4]->direct1b + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open open open ble5.in[4]->direct1a + + + lut[0].out[0]->direct:lut5 + + + + + + + open open open open lut5.in[4]->direct:lut5 + open open open open 0 + + + $auto_449 + + + + + + + + + + open open clb_lr.in[18]->direct_in_2 open open open + open + open + open open + open open + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + open + + + + open open fle.in[2]->direct1a open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open ble5.in[2]->direct1a open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open lut5.in[2]->direct:lut5 open open + open open 0 open open + + + $auto_448 + + + + + + + + + open open fle.in[2]->direct1b open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open ble5.in[2]->direct1a open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open lut5.in[2]->direct:lut5 open open + open open 0 open open + + + $auto_447 + + + + + + + + + + open open open open clb_lr.in[35]->direct_in_4 open + open + open + open open + open open + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + open + + + + open open open open fle.in[4]->direct1a + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open open open ble5.in[4]->direct1a + + + lut[0].out[0]->direct:lut5 + + + + + + + open open open open lut5.in[4]->direct:lut5 + open open open open 0 + + + $auto_440 + + + + + + + + + open open open open fle.in[4]->direct1b + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open open open ble5.in[4]->direct1a + + + lut[0].out[0]->direct:lut5 + + + + + + + open open open open lut5.in[4]->direct:lut5 + open open open open 0 + + + $auto_441 + + + + + + + + + + open open clb_lr.in[20]->direct_in_2 open open open + open + open + open open + open open + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + open + + + + open open fle.in[2]->direct1a open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open ble5.in[2]->direct1a open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open lut5.in[2]->direct:lut5 open open + open open 0 open open + + + $auto_442 + + + + + + + + + open open fle.in[2]->direct1b open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open ble5.in[2]->direct1a open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open lut5.in[2]->direct:lut5 open open + open open 0 open open + + + $auto_443 + + + + + + + + + + open open clb_lr.in[21]->direct_in_2 open clb_lr.in[37]->direct_in_4 open + open + open + open open + open open + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + open + + + + open open open open fle.in[4]->direct1a + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open open open ble5.in[4]->direct1a + + + lut[0].out[0]->direct:lut5 + + + + + + + open open open open lut5.in[4]->direct:lut5 + open open open open 0 + + + $auto_444 + + + + + + + + + open open fle.in[2]->direct1b open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open ble5.in[2]->direct1a open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open lut5.in[2]->direct:lut5 open open + open open 0 open open + + + $f2g_trx_dly_adj_$ibuf_DLY_ADJ + + + + + + + + + + open open clb_lr.in[22]->direct_in_2 open open open + open + open + open open + open open + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + open + + + + open open fle.in[2]->direct1a open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open ble5.in[2]->direct1a open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open lut5.in[2]->direct:lut5 open open + open open 0 open open + + + $auto_450 + + + + + + + + + open open fle.in[2]->direct1b open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open ble5.in[2]->direct1a open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open lut5.in[2]->direct:lut5 open open + open open 0 open open + + + $auto_452 + + + + + + + + + + open clb_lr.in[15]->direct_in_1 open open clb_lr.in[39]->direct_in_4 open + open + open + open clb_lr.reset[1]->direct_reset_7 + open clb_lr.enable[3]->direct_enable_7 + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + clb_lr.clk[0]->direct_clk7 + + + + open open open open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open open open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open open open open + + + $true + + + + + + + + + open fle.in[1]->direct1b open open fle.in[4]->direct1b + fle.reset[1]->direct5b + fle.enable[1]->direct6b + + + ff[0].Q[0]->mux4a + + + fle.clk[0]->direct3b + + + + open ble5.in[1]->direct1a open open ble5.in[4]->direct1a + + + lut[0].out[0]->direct:lut5 + + + + + + + open lut5.in[1]->direct:lut5 open open lut5.in[4]->direct:lut5 + open 1 open open 0 + + + $abc$192$li0_li0 + + + + + + + lut5[0].out[0]->direct2a + ble5.reset[0]->direct5a + ble5.enable[0]->direct6a + + + DFFRE[0].Q[0]->Q_to_Q + + + ble5.clk[0]->direct3a + + + + + + ff.D[0]->D_to_D + ff.R[0]->R_to_R + ff.E[0]->E_to_E + + + dff + + + ff.clk[0]->clk_to_C + + + + + + + + + + $ifab_$obuf_DLY_TAP_VALUE[0] $ifab_$obuf_DLY_TAP_VALUE[5] open open open $obuf_DLY_TAP_VALUE[3] open open open open open open + open open $ibuf_DLY_LOAD open $ifab_$obuf_DLY_TAP_VALUE[1] $ibuf_DLY_INCDEC open open open open open open + open open open open open $ifab_$obuf_DLY_TAP_VALUE[3] $obuf_O open open open open $ifab_$obuf_DLY_TAP_VALUE[2] + $ifab_$obuf_DLY_TAP_VALUE[4] open open open open open open open open open open open + open open open open open open + open + open + open + + + open clb_lr[0].out[1]->clbouts1 open clb_lr[0].out[3]->clbouts1 clb_lr[0].out[4]->clbouts1 open open clb_lr[0].out[7]->clbouts1 open open clb_lr[0].out[10]->clbouts2 open clb_lr[0].out[12]->clbouts2 open open clb_lr[0].out[15]->clbouts2 open open open clb_lr[0].out[19]->clbouts3 open clb_lr[0].out[21]->clbouts3 clb_lr[0].out[22]->clbouts3 open + open + open + open + + + open open open open open open open open open open open open open open open open + + + + clb_lr[0].out[0]->crossbar0 open open open open open open open open clb.I10[5]->crossbar1 clb_lr[0].out[6]->crossbar1 clb.I20[11]->crossbar1 open open open open open open open clb_lr[0].out[9]->crossbar2 clb.I00[1]->crossbar2 clb.I20[6]->crossbar2 open clb.I20[5]->crossbar2 clb.I10[4]->crossbar3 clb.I10[2]->crossbar3 open open clb_lr[0].out[13]->crossbar3 open clb.I30[0]->crossbar3 open open open clb.I00[0]->crossbar4 open open open clb_lr[0].out[18]->crossbar4 clb.I00[5]->crossbar4 open open open open open open open open + open open + open open open open + open + open + + + fle[0].out[0]->direct_out0_0 fle[0].out[1]->direct_out1_0 open fle[1].out[0]->direct_out0_1 fle[1].out[1]->direct_out1_1 open fle[2].out[0]->direct_out0_2 fle[2].out[1]->direct_out1_2 open fle[3].out[0]->direct_out0_3 fle[3].out[1]->direct_out1_3 open fle[4].out[0]->direct_out0_4 fle[4].out[1]->direct_out1_4 open fle[5].out[0]->direct_out0_5 open open fle[6].out[0]->direct_out0_6 fle[6].out[1]->direct_out1_6 open fle[7].out[0]->direct_out0_7 fle[7].out[1]->direct_out1_7 open + open + open + + + open + + + + clb_lr.in[0]->direct_in_0 open open clb_lr.in[24]->direct_in_3 open open + open + open + open open + open open + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + open + + + + open open open fle.in[3]->direct1a open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open open ble5.in[3]->direct1a open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open open lut5.in[3]->direct:lut5 open + open open open 0 open + + + $obuf_DLY_TAP_VALUE[1] + + + + + + + + + fle.in[0]->direct1b open open open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + ble5.in[0]->direct1a open open open open + + + lut[0].out[0]->direct:lut5 + + + + + + + lut5.in[0]->direct:lut5 open open open open + 0 open open open open + + + $f2g_tx_out_$obuf_DLY_TAP_VALUE[1] + + + + + + + + + + open clb_lr.in[9]->direct_in_1 open clb_lr.in[25]->direct_in_3 open open + open + open + open open + open open + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + open + + + + open open open fle.in[3]->direct1a open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open open ble5.in[3]->direct1a open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open open lut5.in[3]->direct:lut5 open + open open open 0 open + + + $f2g_trx_dly_ld_$ibuf_DLY_LOAD + + + + + + + + + open fle.in[1]->direct1b open open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open ble5.in[1]->direct1a open open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open lut5.in[1]->direct:lut5 open open open + open 0 open open open + + + $f2g_trx_dly_inc_$ibuf_DLY_INCDEC + + + + + + + + + + open clb_lr.in[10]->direct_in_1 open open clb_lr.in[34]->direct_in_4 open + open + open + open open + open open + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + open + + + + open open open open fle.in[4]->direct1a + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open open open ble5.in[4]->direct1a + + + lut[0].out[0]->direct:lut5 + + + + + + + open open open open lut5.in[4]->direct:lut5 + open open open open 0 + + + $obuf_DLY_TAP_VALUE[0] + + + + + + + + + open fle.in[1]->direct1b open open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open ble5.in[1]->direct1a open open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open lut5.in[1]->direct:lut5 open open open + open 0 open open open + + + $f2g_tx_out_$obuf_DLY_TAP_VALUE[0] + + + + + + + + + + open clb_lr.in[11]->direct_in_1 clb_lr.in[19]->direct_in_2 open open open + open + open + open open + open open + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + open + + + + open fle.in[1]->direct1a open open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open ble5.in[1]->direct1a open open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open lut5.in[1]->direct:lut5 open open open + open 0 open open open + + + $obuf_DLY_TAP_VALUE[2] + + + + + + + + + open open fle.in[2]->direct1b open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open ble5.in[2]->direct1a open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open lut5.in[2]->direct:lut5 open open + open open 0 open open + + + $f2g_tx_out_$obuf_DLY_TAP_VALUE[2] + + + + + + + + + + open open clb_lr.in[20]->direct_in_2 clb_lr.in[28]->direct_in_3 open open + open + open + open open + open open + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + open + + + + open open open fle.in[3]->direct1a open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open open ble5.in[3]->direct1a open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open open lut5.in[3]->direct:lut5 open + open open open 0 open + + + $f2g_tx_out_$obuf_DLY_TAP_VALUE[5] + + + + + + + + + open open fle.in[2]->direct1b open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open ble5.in[2]->direct1a open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open lut5.in[2]->direct:lut5 open open + open open 0 open open + + + $obuf_DLY_TAP_VALUE[5] + + + + + + + + + + open open clb_lr.in[21]->direct_in_2 open open open + open + open + open open + open open + + + ble5[0].out[0]->direct2 open + open + open + open + + + open + + + + open open fle.in[2]->direct1a open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open ble5.in[2]->direct1a open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open lut5.in[2]->direct:lut5 open open + open open 0 open open + + + $auto_453 + + + + + + + + + + + open open open clb_lr.in[30]->direct_in_3 clb_lr.in[38]->direct_in_4 open + open + open + open open + open open + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + open + + + + open open open fle.in[3]->direct1a open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open open ble5.in[3]->direct1a open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open open lut5.in[3]->direct:lut5 open + open open open 0 open + + + $obuf_DLY_TAP_VALUE[4] + + + + + + + + + open open open open fle.in[4]->direct1b + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open open open ble5.in[4]->direct1a + + + lut[0].out[0]->direct:lut5 + + + + + + + open open open open lut5.in[4]->direct:lut5 + open open open open 0 + + + $f2g_tx_out_$obuf_DLY_TAP_VALUE[4] + + + + + + + + + + open open clb_lr.in[23]->direct_in_2 open clb_lr.in[39]->direct_in_4 open + open + open + open open + open open + + + ble5[0].out[0]->direct2 ble5[1].out[0]->direct2 + open + open + open + + + open + + + + open open fle.in[2]->direct1a open open + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open ble5.in[2]->direct1a open open + + + lut[0].out[0]->direct:lut5 + + + + + + + open open lut5.in[2]->direct:lut5 open open + open open 0 open open + + + $obuf_DLY_TAP_VALUE[3] + + + + + + + + + open open open open fle.in[4]->direct1b + open + open + + + lut5[0].out[0]->mux4a + + + open + + + + open open open open ble5.in[4]->direct1a + + + lut[0].out[0]->direct:lut5 + + + + + + + open open open open lut5.in[4]->direct:lut5 + open open open open 0 + + + $f2g_tx_out_$obuf_DLY_TAP_VALUE[3] + + + + + + + + + + + + $f2g_tx_out_$obuf_DLY_TAP_VALUE[0] + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $f2g_tx_out_$obuf_DLY_TAP_VALUE[1] + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $f2g_tx_out_$obuf_DLY_TAP_VALUE[2] + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $f2g_tx_out_$obuf_DLY_TAP_VALUE[3] + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $f2g_tx_out_$obuf_DLY_TAP_VALUE[4] + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $f2g_tx_out_$obuf_DLY_TAP_VALUE[5] + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $auto_453 + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $f2g_trx_dly_adj_$ibuf_DLY_ADJ + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $f2g_trx_dly_inc_$ibuf_DLY_INCDEC + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $f2g_trx_dly_ld_$ibuf_DLY_LOAD + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + dff + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $auto_440 + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $auto_441 + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $auto_442 + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $auto_443 + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $auto_444 + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $auto_445 + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $auto_446 + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $auto_447 + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $auto_448 + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $auto_449 + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $auto_450 + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $auto_451 + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + $auto_452 + open + + + open + open + + + open open open open open open open open open open open open open open open open + + + + io.f2a_i[0]->io_output-f2a_i + + + + open + + + + + + + io_output.f2a_i[0]->mux1 + + + + + + + + + open + open + + + io_input[0].a2f_o[0]->io-a2f_o + open + + + open open open open open open open open open open open open open open open open + + + + + inpad[0].inpad[0]->mux2 + + + open + + + + + + + $clk_buf_$ibuf_CLK_IN + + + + + + + + + open + open + + + io_input[0].a2f_o[0]->io-a2f_o + open + + + open open open open open open open open open open open open open open open open + + + + + inpad[0].inpad[0]->mux2 + + + open + + + + + + + $ibuf_DLY_ADJ + + + + + + + + + open + open + + + io_input[0].a2f_o[0]->io-a2f_o + open + + + open open open open open open open open open open open open open open open open + + + + + inpad[0].inpad[0]->mux2 + + + open + + + + + + + $ibuf_DLY_INCDEC + + + + + + + + + open + open + + + io_input[0].a2f_o[0]->io-a2f_o + open + + + open open open open open open open open open open open open open open open open + + + + + inpad[0].inpad[0]->mux2 + + + open + + + + + + + $ibuf_DLY_LOAD + + + + + + + + + open + open + + + io_input[0].a2f_o[0]->io-a2f_o + open + + + open open open open open open open open open open open open open open open open + + + + + inpad[0].inpad[0]->mux2 + + + open + + + + + + + $ibuf_in + + + + + + + + + open + open + + + io_input[0].a2f_o[0]->io-a2f_o + open + + + open open open open open open open open open open open open open open open open + + + + + inpad[0].inpad[0]->mux2 + + + open + + + + + + + $ibuf_reset + + + + + + + + + open + open + + + io_input[0].a2f_o[0]->io-a2f_o + open + + + open open open open open open open open open open open open open open open open + + + + + inpad[0].inpad[0]->mux2 + + + open + + + + + + + $ifab_$obuf_DLY_TAP_VALUE[0] + + + + + + + + + open + open + + + io_input[0].a2f_o[0]->io-a2f_o + open + + + open open open open open open open open open open open open open open open open + + + + + inpad[0].inpad[0]->mux2 + + + open + + + + + + + $ifab_$obuf_DLY_TAP_VALUE[1] + + + + + + + + + open + open + + + io_input[0].a2f_o[0]->io-a2f_o + open + + + open open open open open open open open open open open open open open open open + + + + + inpad[0].inpad[0]->mux2 + + + open + + + + + + + $ifab_$obuf_DLY_TAP_VALUE[2] + + + + + + + + + open + open + + + io_input[0].a2f_o[0]->io-a2f_o + open + + + open open open open open open open open open open open open open open open open + + + + + inpad[0].inpad[0]->mux2 + + + open + + + + + + + $ifab_$obuf_DLY_TAP_VALUE[3] + + + + + + + + + open + open + + + io_input[0].a2f_o[0]->io-a2f_o + open + + + open open open open open open open open open open open open open open open open + + + + + inpad[0].inpad[0]->mux2 + + + open + + + + + + + $ifab_$obuf_DLY_TAP_VALUE[4] + + + + + + + + + open + open + + + io_input[0].a2f_o[0]->io-a2f_o + open + + + open open open open open open open open open open open open open open open open + + + + + inpad[0].inpad[0]->mux2 + + + open + + + + + + + $ifab_$obuf_DLY_TAP_VALUE[5] + + + + + + + + + open + open + + + io_input[0].a2f_o[0]->io-a2f_o + open + + + open open open open open open open open open open open open open open open open + + + + + inpad[0].inpad[0]->mux2 + + + open + + + + + + + $obuf_O + + + + + + + diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/packing.rpt b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/packing.rpt new file mode 100644 index 00000000..e367f945 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/packing.rpt @@ -0,0 +1,475 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.09 +Build : 1.2.3 +Hash : 89d4d1b +Date : Sep 19 2024 +Type : Engineering +Log Time : Thu Sep 19 08:35:27 2024 GMT +VPR FPGA Placement and Routing. +Version: +Revision: +Compiled: +Compiler: GNU 11.2.1 on Linux-3.10.0-1160.90.1.el7.x86_64 x86_64 +Build Info: Release VTR_ASSERT_LEVEL=2 + +University of Toronto +verilogtorouting.org +vtr-users@googlegroups.com +This is free open source code under MIT license. + +VPR was run with the following command-line: +/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/vpr /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --sdc_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc --route_chan_width 160 --suppress_warnings check_rr_node_warnings.log,check_rr_node --clock_modeling ideal --absorb_buffer_luts off --skip_sync_clustering_and_routing_results off --constant_net_method route --post_place_timing_report I_DELAY_primitive_inst_post_place_timing.rpt --device castor62x44_heterogeneous --allow_unrelated_clustering on --allow_dangling_combinational_nodes on --place_delta_delay_matrix_calculation_method dijkstra --gen_post_synthesis_netlist on --post_synth_netlist_unconn_inputs gnd --inner_loop_recompute_divider 1 --max_router_iterations 1500 --timing_report_detail detailed --timing_report_npaths 100 --top I_DELAY_primitive_inst --net_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net --place_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place --route_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route --pack + +Using up to 1 parallel worker(s) + +Architecture file: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml +Circuit name: fabric_I_DELAY_primitive_inst_post_synth + +# Loading Architecture Description +Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 3: Model 'dsp_phy' input port 'sc_in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 4: Model 'dsp_phy' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 5: Model 'dsp_phy' output port 'sc_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 6: Model 'RS_DSP_MULT' input port 'feedback' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 7: Model 'RS_DSP_MULT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 8: Model 'RS_DSP_MULT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 9: Model 'RS_DSP_MULT_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 10: Model 'RS_DSP_MULT_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 11: Model 'RS_DSP_MULT_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 12: Model 'RS_DSP_MULT_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 13: Model 'RS_DSP_MULT_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 14: Model 'RS_DSP_MULT_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 15: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 16: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 17: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 18: Model 'RS_DSP_MULTADD' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 19: Model 'RS_DSP_MULTADD' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 20: Model 'RS_DSP_MULTADD' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 21: Model 'RS_DSP_MULTADD' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 22: Model 'RS_DSP_MULTADD' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 23: Model 'RS_DSP_MULTADD' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 24: Model 'RS_DSP_MULTADD_REGIN' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 25: Model 'RS_DSP_MULTADD_REGIN' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 26: Model 'RS_DSP_MULTADD_REGIN' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 27: Model 'RS_DSP_MULTADD_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 28: Model 'RS_DSP_MULTADD_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 29: Model 'RS_DSP_MULTADD_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 30: Model 'RS_DSP_MULTADD_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 31: Model 'RS_DSP_MULTADD_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 32: Model 'RS_DSP_MULTADD_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 33: Model 'RS_DSP_MULTADD_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 34: Model 'RS_DSP_MULTADD_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 35: Model 'RS_DSP_MULTADD_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 36: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 37: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 38: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 39: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 40: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 41: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 42: Model 'RS_DSP_MULTACC' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 43: Model 'RS_DSP_MULTACC' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 44: Model 'RS_DSP_MULTACC' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 45: Model 'RS_DSP_MULTACC' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 46: Model 'RS_DSP_MULTACC' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 47: Model 'RS_DSP_MULTACC' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 48: Model 'RS_DSP_MULTACC_REGIN' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 49: Model 'RS_DSP_MULTACC_REGIN' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 50: Model 'RS_DSP_MULTACC_REGIN' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 51: Model 'RS_DSP_MULTACC_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 52: Model 'RS_DSP_MULTACC_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 53: Model 'RS_DSP_MULTACC_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 54: Model 'RS_DSP_MULTACC_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 55: Model 'RS_DSP_MULTACC_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 56: Model 'RS_DSP_MULTACC_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 57: Model 'RS_DSP_MULTACC_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 58: Model 'RS_DSP_MULTACC_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 59: Model 'RS_DSP_MULTACC_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 60: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 61: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 62: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 63: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 64: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 65: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 66: Model 'bram_phy' input port 'sc_in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 67: Model 'bram_phy' output port 'sc_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 68: Model 'bram_phy' output port 'PL_DATA_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 69: Model 'bram_phy' output port 'PL_ADDR_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 70: Model 'bram_phy' output port 'PL_WEN_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 71: Model 'bram_phy' output port 'PL_CLK_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 72: Model 'bram_phy' output port 'PL_REN_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 73: Model 'bram_phy' output port 'PL_ENA_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 74: Model 'bram_phy' output port 'PL_INIT_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +mode 'io[physical]' is defined by user to be disabled in packing +mode 'iopad[default]' is defined by user to be disabled in packing +mode 'fle[physical]' is defined by user to be disabled in packing +mode 'fabric[default]' is defined by user to be disabled in packing +mode 'ff_bypass[default]' is defined by user to be disabled in packing +mode 'dsp_lr[physical]' is defined by user to be disabled in packing +mode 'bram_lr[physical]' is defined by user to be disabled in packing +# Loading Architecture Description took 0.06 seconds (max_rss 17.2 MiB, delta_rss +0.0 MiB) + +Timing analysis: ON +Circuit netlist file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net +Circuit placement file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place +Circuit routing file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route +Circuit SDC file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc +Vpr floorplanning constraints file: not specified + +Packer: ENABLED +Placer: DISABLED +Router: DISABLED +Analysis: DISABLED + +VPR was run with the following options: + +NetlistOpts.abosrb_buffer_luts : false +NetlistOpts.sweep_dangling_primary_ios : true +NetlistOpts.sweep_dangling_nets : true +NetlistOpts.sweep_dangling_blocks : true +NetlistOpts.sweep_constant_primary_outputs: false +NetlistOpts.netlist_verbosity : 1 +NetlistOpts.const_gen_inference : COMB_SEQ + +PackerOpts.allow_unrelated_clustering: true +PackerOpts.alpha_clustering: 0.750000 +PackerOpts.beta_clustering: 0.900000 +PackerOpts.cluster_seed_type: BLEND2 +PackerOpts.connection_driven: true +PackerOpts.global_clocks: true +PackerOpts.hill_climbing_flag: false +PackerOpts.inter_cluster_net_delay: 1.000000 +PackerOpts.timing_driven: true +PackerOpts.target_external_pin_util: auto + +# Building complex block graph +Warning 75: clb[0].sr_in[0] unconnected pin in architecture. +Warning 76: clb[0].sr_out[0] unconnected pin in architecture. +Warning 77: dsp[0].sr_in[0] unconnected pin in architecture. +Warning 78: dsp[0].sr_in[1] unconnected pin in architecture. +Warning 79: dsp[0].sr_in[2] unconnected pin in architecture. +Warning 80: dsp[0].sr_out[0] unconnected pin in architecture. +Warning 81: dsp[0].sr_out[1] unconnected pin in architecture. +Warning 82: dsp[0].sr_out[2] unconnected pin in architecture. +Warning 83: bram[0].sr_in[0] unconnected pin in architecture. +Warning 84: bram[0].sr_in[1] unconnected pin in architecture. +Warning 85: bram[0].sr_in[2] unconnected pin in architecture. +Warning 86: bram[0].sr_in[3] unconnected pin in architecture. +Warning 87: bram[0].sr_in[4] unconnected pin in architecture. +Warning 88: bram[0].sr_in[5] unconnected pin in architecture. +Warning 89: bram[0].plr_i[0] unconnected pin in architecture. +Warning 90: bram[0].plr_i[1] unconnected pin in architecture. +Warning 91: bram[0].plr_i[2] unconnected pin in architecture. +Warning 92: bram[0].plr_i[3] unconnected pin in architecture. +Warning 93: bram[0].plr_i[4] unconnected pin in architecture. +Warning 94: bram[0].plr_i[5] unconnected pin in architecture. +Warning 95: bram[0].plr_i[6] unconnected pin in architecture. +Warning 96: bram[0].plr_i[7] unconnected pin in architecture. +Warning 97: bram[0].plr_i[8] unconnected pin in architecture. +Warning 98: bram[0].plr_i[9] unconnected pin in architecture. +Warning 99: bram[0].plr_i[10] unconnected pin in architecture. +Warning 100: bram[0].plr_i[11] unconnected pin in architecture. +Warning 101: bram[0].plr_i[12] unconnected pin in architecture. +Warning 102: bram[0].plr_i[13] unconnected pin in architecture. +Warning 103: bram[0].plr_i[14] unconnected pin in architecture. +Warning 104: bram[0].plr_i[15] unconnected pin in architecture. +Warning 105: bram[0].plr_i[16] unconnected pin in architecture. +Warning 106: bram[0].plr_i[17] unconnected pin in architecture. +Warning 107: bram[0].plr_i[18] unconnected pin in architecture. +Warning 108: bram[0].plr_i[19] unconnected pin in architecture. +Warning 109: bram[0].plr_i[20] unconnected pin in architecture. +Warning 110: bram[0].plr_i[21] unconnected pin in architecture. +Warning 111: bram[0].plr_i[22] unconnected pin in architecture. +Warning 112: bram[0].plr_i[23] unconnected pin in architecture. +Warning 113: bram[0].plr_i[24] unconnected pin in architecture. +Warning 114: bram[0].plr_i[25] unconnected pin in architecture. +Warning 115: bram[0].plr_i[26] unconnected pin in architecture. +Warning 116: bram[0].plr_i[27] unconnected pin in architecture. +Warning 117: bram[0].plr_i[28] unconnected pin in architecture. +Warning 118: bram[0].plr_i[29] unconnected pin in architecture. +Warning 119: bram[0].plr_i[30] unconnected pin in architecture. +Warning 120: bram[0].plr_i[31] unconnected pin in architecture. +Warning 121: bram[0].plr_i[32] unconnected pin in architecture. +Warning 122: bram[0].plr_i[33] unconnected pin in architecture. +Warning 123: bram[0].plr_i[34] unconnected pin in architecture. +Warning 124: bram[0].plr_i[35] unconnected pin in architecture. +Warning 125: bram[0].sr_out[0] unconnected pin in architecture. +Warning 126: bram[0].sr_out[1] unconnected pin in architecture. +Warning 127: bram[0].sr_out[2] unconnected pin in architecture. +Warning 128: bram[0].sr_out[3] unconnected pin in architecture. +Warning 129: bram[0].sr_out[4] unconnected pin in architecture. +Warning 130: bram[0].sr_out[5] unconnected pin in architecture. +Warning 131: bram[0].plr_o[0] unconnected pin in architecture. +Warning 132: bram[0].plr_o[1] unconnected pin in architecture. +Warning 133: bram[0].plr_o[2] unconnected pin in architecture. +Warning 134: bram[0].plr_o[3] unconnected pin in architecture. +Warning 135: bram[0].plr_o[4] unconnected pin in architecture. +Warning 136: bram[0].plr_o[5] unconnected pin in architecture. +Warning 137: bram[0].plr_o[6] unconnected pin in architecture. +Warning 138: bram[0].plr_o[7] unconnected pin in architecture. +Warning 139: bram[0].plr_o[8] unconnected pin in architecture. +Warning 140: bram[0].plr_o[9] unconnected pin in architecture. +Warning 141: bram[0].plr_o[10] unconnected pin in architecture. +Warning 142: bram[0].plr_o[11] unconnected pin in architecture. +Warning 143: bram[0].plr_o[12] unconnected pin in architecture. +Warning 144: bram[0].plr_o[13] unconnected pin in architecture. +Warning 145: bram[0].plr_o[14] unconnected pin in architecture. +Warning 146: bram[0].plr_o[15] unconnected pin in architecture. +Warning 147: bram[0].plr_o[16] unconnected pin in architecture. +Warning 148: bram[0].plr_o[17] unconnected pin in architecture. +Warning 149: bram[0].plr_o[18] unconnected pin in architecture. +Warning 150: bram[0].plr_o[19] unconnected pin in architecture. +Warning 151: bram[0].plr_o[20] unconnected pin in architecture. +Warning 152: bram[0].plr_o[21] unconnected pin in architecture. +Warning 153: bram[0].plr_o[22] unconnected pin in architecture. +Warning 154: bram[0].plr_o[23] unconnected pin in architecture. +Warning 155: bram[0].plr_o[24] unconnected pin in architecture. +Warning 156: bram[0].plr_o[25] unconnected pin in architecture. +Warning 157: bram[0].plr_o[26] unconnected pin in architecture. +Warning 158: bram[0].plr_o[27] unconnected pin in architecture. +Warning 159: bram[0].plr_o[28] unconnected pin in architecture. +Warning 160: bram[0].plr_o[29] unconnected pin in architecture. +Warning 161: bram[0].plr_o[30] unconnected pin in architecture. +Warning 162: bram[0].plr_o[31] unconnected pin in architecture. +Warning 163: bram[0].plr_o[32] unconnected pin in architecture. +Warning 164: bram[0].plr_o[33] unconnected pin in architecture. +Warning 165: bram[0].plr_o[34] unconnected pin in architecture. +Warning 166: bram[0].plr_o[35] unconnected pin in architecture. +# Building complex block graph took 0.04 seconds (max_rss 18.2 MiB, delta_rss +1.1 MiB) +Circuit file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif +# Load circuit +Found constant-zero generator '$false' +Found constant-one generator '$true' +Found constant-zero generator '$undef' +# Load circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.5 MiB) +# Clean circuit +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 13 additional primitive pins as constant generators due to constant inputs +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 0 additional primitive pins as constant generators due to constant inputs +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 0 additional primitive pins as constant generators due to constant inputs +Swept input(s) : 0 +Swept output(s) : 0 (0 dangling, 0 constant) +Swept net(s) : 2 +Swept block(s) : 2 +Constant Pins Marked: 13 +# Clean circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +# Compress circuit +# Compress circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +# Verify circuit +# Verify circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +Circuit Statistics: + Blocks: 69 + .input : 13 + .output: 24 + 0-LUT : 1 + 6-LUT : 30 + dffre : 1 + Nets : 45 + Avg Fanout: 1.3 + Max Fanout: 15.0 + Min Fanout: 1.0 + Netlist Clocks: 1 +# Build Timing Graph + Timing Graph Nodes: 104 + Timing Graph Edges: 94 + Timing Graph Levels: 6 +# Build Timing Graph took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +Netlist contains 1 clocks + Netlist Clock 'CLK_IN' Fanout: 1 pins (1.0%), 1 blocks (1.4%) +# Load Timing Constraints + +SDC file '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc' contained no SDC commands +Setting default timing constraints: + * constrain all primay inputs and primary outputs on netlist clock 'CLK_IN' + * optimize netlist clock to run as fast as possible +Timing constraints created 1 clocks + Constrained Clock 'CLK_IN' Source: 'CLK_IN.inpad[0]' + +# Load Timing Constraints took 0.00 seconds (max_rss 19.0 MiB, delta_rss +0.3 MiB) +# Packing +Begin packing '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif'. + +After removing unused inputs... + total blocks: 69, total nets: 45, total inputs: 13, total outputs: 24 +Begin prepacking. + +There is one chain in this architecture called "carrychain" with the following starting points: + clb[0]/clb_lr[0]/fle[0]/adder[0]/adder_carry[0].cin[0] + +0 attraction groups were created during prepacking. +Finish prepacking. +Using inter-cluster delay: 8.9048e-10 +Packing with pin utilization targets: io_top:1,1 io_right:1,1 io_bottom:1,1 io_left:1,1 clb:0.8,1 dsp:1,1 bram:1,1 +Packing with high fanout thresholds: io_top:128 io_right:128 io_bottom:128 io_left:128 clb:32 dsp:128 bram:128 +Starting Clustering - Clustering Progress: +------------------- -------------------------- --------- +Molecules processed Number of clusters created FPGA size +------------------- -------------------------- --------- + 2/68 2% 1 64 x 46 + 4/68 5% 1 64 x 46 + 6/68 8% 1 64 x 46 + 8/68 11% 1 64 x 46 + 10/68 14% 1 64 x 46 + 12/68 17% 1 64 x 46 + 14/68 20% 1 64 x 46 + 16/68 23% 1 64 x 46 + 18/68 26% 2 64 x 46 + 20/68 29% 2 64 x 46 + 22/68 32% 2 64 x 46 + 24/68 35% 2 64 x 46 + 26/68 38% 2 64 x 46 + 28/68 41% 2 64 x 46 + 30/68 44% 2 64 x 46 + 32/68 47% 2 64 x 46 + 34/68 50% 4 64 x 46 + 36/68 52% 6 64 x 46 + 38/68 55% 8 64 x 46 + 40/68 58% 10 64 x 46 + 42/68 61% 12 64 x 46 + 44/68 64% 14 64 x 46 + 46/68 67% 16 64 x 46 + 48/68 70% 18 64 x 46 + 50/68 73% 20 64 x 46 + 52/68 76% 22 64 x 46 + 54/68 79% 24 64 x 46 + 56/68 82% 26 64 x 46 + 58/68 85% 28 64 x 46 + 60/68 88% 30 64 x 46 + 62/68 91% 32 64 x 46 + 64/68 94% 34 64 x 46 + 66/68 97% 36 64 x 46 + 68/68 100% 38 64 x 46 + +Logic Element (fle) detailed count: + Total number of Logic Elements used : 16 + LEs used for logic and registers : 0 + LEs used for logic only : 16 + LEs used for registers only : 0 + +Incr Slack updates 1 in 3.518e-06 sec +Full Max Req/Worst Slack updates 1 in 6.294e-06 sec +Incr Max Req/Worst Slack updates 0 in 0 sec +Incr Criticality updates 0 in 0 sec +Full Criticality updates 1 in 8.597e-06 sec +FPGA sized to 64 x 46 (castor62x44_heterogeneous) +Device Utilization: 0.00 (target 1.00) + Block Utilization: 0.00 Type: io + Block Utilization: 0.00 Type: clb + +Start the iterative improvement process +the iterative improvement process is done +Clustering Statistics: +---------- -------- ------------------------------------ -------------------------- +Block Type # Blocks Avg. # of input clocks and pins used Avg. # of output pins used +---------- -------- ------------------------------------ -------------------------- + EMPTY 0 0 0 + io 37 0.648649 0.351351 + clb 2 8 13 + dsp 0 0 0 + bram 0 0 0 +Absorbed logical nets 6 out of 45 nets, 39 nets not absorbed. + +Netlist conversion complete. + +# Packing took 0.02 seconds (max_rss 20.9 MiB, delta_rss +1.6 MiB) +# Load packing +Begin loading packed FPGA netlist file. +Netlist generated from file '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net'. +Detected 1 constant generators (to see names run with higher pack verbosity) +Finished loading packed FPGA netlist file (took 0.05 seconds). +# Load packing took 0.05 seconds (max_rss 59.0 MiB, delta_rss +38.1 MiB) +Warning 167: Netlist contains 0 global net to non-global architecture pin connections + +Pb types usage... + io : 37 + io_output : 24 + outpad : 24 + io_input : 13 + inpad : 13 + clb : 2 + clb_lr : 2 + fle : 16 + ble5 : 31 + lut5 : 31 + lut : 31 + ff : 1 + DFFRE : 1 + +# Create Device +## Build Device Grid +FPGA sized to 64 x 46: 2944 grid tiles (castor62x44_heterogeneous) + +Resource usage... + Netlist + 37 blocks of type: io + Architecture + 4320 blocks of type: io_top + 3168 blocks of type: io_right + 4320 blocks of type: io_bottom + 3168 blocks of type: io_left + Netlist + 2 blocks of type: clb + Architecture + 2184 blocks of type: clb + Netlist + 0 blocks of type: dsp + Architecture + 56 blocks of type: dsp + Netlist + 0 blocks of type: bram + Architecture + 56 blocks of type: bram + +Device Utilization: 0.00 (target 1.00) + Physical Tile io_top: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_right: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_bottom: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_left: + Block Utilization: 0.01 Logical Block: io + Physical Tile clb: + Block Utilization: 0.00 Logical Block: clb + Physical Tile dsp: + Block Utilization: 0.00 Logical Block: dsp + Physical Tile bram: + Block Utilization: 0.00 Logical Block: bram + +## Build Device Grid took 0.00 seconds (max_rss 59.1 MiB, delta_rss +0.0 MiB) +Warning 168: Tileable routing resource graph does not support clock modeling yet! Related options are ignored... +## Build tileable routing resource graph +X-direction routing channel width is 160 +Y-direction routing channel width is 160 +Warning 169: Sized nonsensical R=0 transistor to minimum width +Warning 170: Sized nonsensical R=0 transistor to minimum width +Warning 171: Sized nonsensical R=0 transistor to minimum width +Warning 172: Sized nonsensical R=0 transistor to minimum width +## Build tileable routing resource graph took 13.42 seconds (max_rss 473.6 MiB, delta_rss +414.5 MiB) + RR Graph Nodes: 1365608 + RR Graph Edges: 6033268 +# Create Device took 14.03 seconds (max_rss 473.6 MiB, delta_rss +414.5 MiB) + + +Flow timing analysis took 0.00177694 seconds (0.00174604 STA, 3.0901e-05 slack) (1 full updates: 1 setup, 0 hold, 0 combined). +VPR succeeded +The entire flow of VPR took 14.56 seconds (max_rss 473.6 MiB) diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/packing_pin_util.rpt b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/packing_pin_util.rpt new file mode 100644 index 00000000..4ec9095e --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/packing_pin_util.rpt @@ -0,0 +1,89 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.09 +Build : 1.2.3 +Hash : 89d4d1b +Date : Sep 19 2024 +Type : Engineering +Log Time : Thu Sep 19 08:35:27 2024 GMT +#Packing pin usage report +Type: io + Input Pin Usage: + Max: 1.00 (0.06) + Avg: 0.65 (0.04) + Min: 0.00 (0.00) + Histogram: + [ 0: 1.8) 37 (100.0%) |************************************************ + [ 1.8: 3.6) 0 ( 0.0%) | + [ 3.6: 5.4) 0 ( 0.0%) | + [ 5.4: 7.2) 0 ( 0.0%) | + [ 7.2: 9) 0 ( 0.0%) | + [ 9: 11) 0 ( 0.0%) | + [ 11: 13) 0 ( 0.0%) | + [ 13: 14) 0 ( 0.0%) | + [ 14: 16) 0 ( 0.0%) | + [ 16: 18) 0 ( 0.0%) | + Output Pin Usage: + Max: 1.00 (0.50) + Avg: 0.35 (0.18) + Min: 0.00 (0.00) + Histogram: + [ 0: 0.2) 24 ( 64.9%) |************************************************ + [ 0.2: 0.4) 0 ( 0.0%) | + [ 0.4: 0.6) 0 ( 0.0%) | + [ 0.6: 0.8) 0 ( 0.0%) | + [ 0.8: 1) 13 ( 35.1%) |************************** + [ 1: 1.2) 0 ( 0.0%) | + [ 1.2: 1.4) 0 ( 0.0%) | + [ 1.4: 1.6) 0 ( 0.0%) | + [ 1.6: 1.8) 0 ( 0.0%) | + [ 1.8: 2) 0 ( 0.0%) | + +Type: clb + Input Pin Usage: + Max: 10.00 (0.14) + Avg: 8.00 (0.11) + Min: 6.00 (0.08) + Histogram: + [ 0: 7.3) 1 ( 50.0%) |************************************************** + [ 7.3: 15) 1 ( 50.0%) |************************************************** + [ 15: 22) 0 ( 0.0%) | + [ 22: 29) 0 ( 0.0%) | + [ 29: 36) 0 ( 0.0%) | + [ 36: 44) 0 ( 0.0%) | + [ 44: 51) 0 ( 0.0%) | + [ 51: 58) 0 ( 0.0%) | + [ 58: 66) 0 ( 0.0%) | + [ 66: 73) 0 ( 0.0%) | + Output Pin Usage: + Max: 16.00 (0.59) + Avg: 13.00 (0.48) + Min: 10.00 (0.37) + Histogram: + [ 0: 2.7) 0 ( 0.0%) | + [ 2.7: 5.4) 0 ( 0.0%) | + [ 5.4: 8.1) 0 ( 0.0%) | + [ 8.1: 11) 1 ( 50.0%) |************************************************** + [ 11: 14) 0 ( 0.0%) | + [ 14: 16) 1 ( 50.0%) |************************************************** + [ 16: 19) 0 ( 0.0%) | + [ 19: 22) 0 ( 0.0%) | + [ 22: 24) 0 ( 0.0%) | + [ 24: 27) 0 ( 0.0%) | + diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/pre_pack.report_timing.setup.rpt b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/pre_pack.report_timing.setup.rpt new file mode 100644 index 00000000..c5b0dbdb --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/pre_pack.report_timing.setup.rpt @@ -0,0 +1,381 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.09 +Build : 1.2.3 +Hash : 89d4d1b +Date : Sep 19 2024 +Type : Engineering +Log Time : Thu Sep 19 08:35:27 2024 GMT +#Timing report of worst 12 path(s) +# Unit scale: 1e-09 seconds +# Output precision: 3 + +# Logical Levels: 0 +# Timing Graph Levels: 6 + +#Path 1 +Startpoint: $ifab_$obuf_DLY_TAP_VALUE[0].inpad[0] (.input clocked by CLK_IN) +Endpoint : out:DLY_TAP_VALUE[0].outpad[0] (.output clocked by CLK_IN) +Path Type : setup + +Point Incr Path +------------------------------------------------------------------------------------------------ +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +input external delay 0.000 0.000 +$ifab_$obuf_DLY_TAP_VALUE[0].inpad[0] (.input) 0.000 0.000 +$obuf_DLY_TAP_VALUE[0].in[0] (.names) 0.890 0.890 +$obuf_DLY_TAP_VALUE[0].out[0] (.names) 0.218 1.109 +DLY_TAP_VALUE[0].in[0] (.names) 0.890 1.999 +DLY_TAP_VALUE[0].out[0] (.names) 0.218 2.217 +out:DLY_TAP_VALUE[0].outpad[0] (.output) 0.890 3.108 +data arrival time 3.108 + +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +clock uncertainty 0.000 0.000 +output external delay 0.000 0.000 +data required time 0.000 +------------------------------------------------------------------------------------------------ +data required time 0.000 +data arrival time -3.108 +------------------------------------------------------------------------------------------------ +slack (VIOLATED) -3.108 + + +#Path 2 +Startpoint: $ifab_$obuf_DLY_TAP_VALUE[1].inpad[0] (.input clocked by CLK_IN) +Endpoint : out:DLY_TAP_VALUE[1].outpad[0] (.output clocked by CLK_IN) +Path Type : setup + +Point Incr Path +------------------------------------------------------------------------------------------------ +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +input external delay 0.000 0.000 +$ifab_$obuf_DLY_TAP_VALUE[1].inpad[0] (.input) 0.000 0.000 +$obuf_DLY_TAP_VALUE[1].in[0] (.names) 0.890 0.890 +$obuf_DLY_TAP_VALUE[1].out[0] (.names) 0.218 1.109 +DLY_TAP_VALUE[1].in[0] (.names) 0.890 1.999 +DLY_TAP_VALUE[1].out[0] (.names) 0.218 2.217 +out:DLY_TAP_VALUE[1].outpad[0] (.output) 0.890 3.108 +data arrival time 3.108 + +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +clock uncertainty 0.000 0.000 +output external delay 0.000 0.000 +data required time 0.000 +------------------------------------------------------------------------------------------------ +data required time 0.000 +data arrival time -3.108 +------------------------------------------------------------------------------------------------ +slack (VIOLATED) -3.108 + + +#Path 3 +Startpoint: $ifab_$obuf_DLY_TAP_VALUE[2].inpad[0] (.input clocked by CLK_IN) +Endpoint : out:DLY_TAP_VALUE[2].outpad[0] (.output clocked by CLK_IN) +Path Type : setup + +Point Incr Path +------------------------------------------------------------------------------------------------ +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +input external delay 0.000 0.000 +$ifab_$obuf_DLY_TAP_VALUE[2].inpad[0] (.input) 0.000 0.000 +$obuf_DLY_TAP_VALUE[2].in[0] (.names) 0.890 0.890 +$obuf_DLY_TAP_VALUE[2].out[0] (.names) 0.218 1.109 +DLY_TAP_VALUE[2].in[0] (.names) 0.890 1.999 +DLY_TAP_VALUE[2].out[0] (.names) 0.218 2.217 +out:DLY_TAP_VALUE[2].outpad[0] (.output) 0.890 3.108 +data arrival time 3.108 + +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +clock uncertainty 0.000 0.000 +output external delay 0.000 0.000 +data required time 0.000 +------------------------------------------------------------------------------------------------ +data required time 0.000 +data arrival time -3.108 +------------------------------------------------------------------------------------------------ +slack (VIOLATED) -3.108 + + +#Path 4 +Startpoint: $ifab_$obuf_DLY_TAP_VALUE[3].inpad[0] (.input clocked by CLK_IN) +Endpoint : out:DLY_TAP_VALUE[3].outpad[0] (.output clocked by CLK_IN) +Path Type : setup + +Point Incr Path +------------------------------------------------------------------------------------------------ +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +input external delay 0.000 0.000 +$ifab_$obuf_DLY_TAP_VALUE[3].inpad[0] (.input) 0.000 0.000 +$obuf_DLY_TAP_VALUE[3].in[0] (.names) 0.890 0.890 +$obuf_DLY_TAP_VALUE[3].out[0] (.names) 0.218 1.109 +DLY_TAP_VALUE[3].in[0] (.names) 0.890 1.999 +DLY_TAP_VALUE[3].out[0] (.names) 0.218 2.217 +out:DLY_TAP_VALUE[3].outpad[0] (.output) 0.890 3.108 +data arrival time 3.108 + +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +clock uncertainty 0.000 0.000 +output external delay 0.000 0.000 +data required time 0.000 +------------------------------------------------------------------------------------------------ +data required time 0.000 +data arrival time -3.108 +------------------------------------------------------------------------------------------------ +slack (VIOLATED) -3.108 + + +#Path 5 +Startpoint: $ifab_$obuf_DLY_TAP_VALUE[4].inpad[0] (.input clocked by CLK_IN) +Endpoint : out:DLY_TAP_VALUE[4].outpad[0] (.output clocked by CLK_IN) +Path Type : setup + +Point Incr Path +------------------------------------------------------------------------------------------------ +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +input external delay 0.000 0.000 +$ifab_$obuf_DLY_TAP_VALUE[4].inpad[0] (.input) 0.000 0.000 +$obuf_DLY_TAP_VALUE[4].in[0] (.names) 0.890 0.890 +$obuf_DLY_TAP_VALUE[4].out[0] (.names) 0.218 1.109 +DLY_TAP_VALUE[4].in[0] (.names) 0.890 1.999 +DLY_TAP_VALUE[4].out[0] (.names) 0.218 2.217 +out:DLY_TAP_VALUE[4].outpad[0] (.output) 0.890 3.108 +data arrival time 3.108 + +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +clock uncertainty 0.000 0.000 +output external delay 0.000 0.000 +data required time 0.000 +------------------------------------------------------------------------------------------------ +data required time 0.000 +data arrival time -3.108 +------------------------------------------------------------------------------------------------ +slack (VIOLATED) -3.108 + + +#Path 6 +Startpoint: $ifab_$obuf_DLY_TAP_VALUE[5].inpad[0] (.input clocked by CLK_IN) +Endpoint : out:DLY_TAP_VALUE[5].outpad[0] (.output clocked by CLK_IN) +Path Type : setup + +Point Incr Path +------------------------------------------------------------------------------------------------ +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +input external delay 0.000 0.000 +$ifab_$obuf_DLY_TAP_VALUE[5].inpad[0] (.input) 0.000 0.000 +$obuf_DLY_TAP_VALUE[5].in[0] (.names) 0.890 0.890 +$obuf_DLY_TAP_VALUE[5].out[0] (.names) 0.218 1.109 +DLY_TAP_VALUE[5].in[0] (.names) 0.890 1.999 +DLY_TAP_VALUE[5].out[0] (.names) 0.218 2.217 +out:DLY_TAP_VALUE[5].outpad[0] (.output) 0.890 3.108 +data arrival time 3.108 + +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +clock uncertainty 0.000 0.000 +output external delay 0.000 0.000 +data required time 0.000 +------------------------------------------------------------------------------------------------ +data required time 0.000 +data arrival time -3.108 +------------------------------------------------------------------------------------------------ +slack (VIOLATED) -3.108 + + +#Path 7 +Startpoint: DLY_ADJ.inpad[0] (.input clocked by CLK_IN) +Endpoint : out:$f2g_trx_dly_adj_DLY_ADJ.outpad[0] (.output clocked by CLK_IN) +Path Type : setup + +Point Incr Path +-------------------------------------------------------------------------------------------- +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +input external delay 0.000 0.000 +DLY_ADJ.inpad[0] (.input) 0.000 0.000 +$f2g_trx_dly_adj_DLY_ADJ.in[0] (.names) 0.890 0.890 +$f2g_trx_dly_adj_DLY_ADJ.out[0] (.names) 0.218 1.109 +out:$f2g_trx_dly_adj_DLY_ADJ.outpad[0] (.output) 0.890 1.999 +data arrival time 1.999 + +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +clock uncertainty 0.000 0.000 +output external delay 0.000 0.000 +data required time 0.000 +-------------------------------------------------------------------------------------------- +data required time 0.000 +data arrival time -1.999 +-------------------------------------------------------------------------------------------- +slack (VIOLATED) -1.999 + + +#Path 8 +Startpoint: DLY_INCDEC.inpad[0] (.input clocked by CLK_IN) +Endpoint : out:$f2g_trx_dly_inc_DLY_INCDEC.outpad[0] (.output clocked by CLK_IN) +Path Type : setup + +Point Incr Path +----------------------------------------------------------------------------------------------- +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +input external delay 0.000 0.000 +DLY_INCDEC.inpad[0] (.input) 0.000 0.000 +$f2g_trx_dly_inc_DLY_INCDEC.in[0] (.names) 0.890 0.890 +$f2g_trx_dly_inc_DLY_INCDEC.out[0] (.names) 0.218 1.109 +out:$f2g_trx_dly_inc_DLY_INCDEC.outpad[0] (.output) 0.890 1.999 +data arrival time 1.999 + +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +clock uncertainty 0.000 0.000 +output external delay 0.000 0.000 +data required time 0.000 +----------------------------------------------------------------------------------------------- +data required time 0.000 +data arrival time -1.999 +----------------------------------------------------------------------------------------------- +slack (VIOLATED) -1.999 + + +#Path 9 +Startpoint: DLY_LOAD.inpad[0] (.input clocked by CLK_IN) +Endpoint : out:$f2g_trx_dly_ld_DLY_LOAD.outpad[0] (.output clocked by CLK_IN) +Path Type : setup + +Point Incr Path +-------------------------------------------------------------------------------------------- +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +input external delay 0.000 0.000 +DLY_LOAD.inpad[0] (.input) 0.000 0.000 +$f2g_trx_dly_ld_DLY_LOAD.in[0] (.names) 0.890 0.890 +$f2g_trx_dly_ld_DLY_LOAD.out[0] (.names) 0.218 1.109 +out:$f2g_trx_dly_ld_DLY_LOAD.outpad[0] (.output) 0.890 1.999 +data arrival time 1.999 + +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +clock uncertainty 0.000 0.000 +output external delay 0.000 0.000 +data required time 0.000 +-------------------------------------------------------------------------------------------- +data required time 0.000 +data arrival time -1.999 +-------------------------------------------------------------------------------------------- +slack (VIOLATED) -1.999 + + +#Path 10 +Startpoint: $obuf_O.inpad[0] (.input clocked by CLK_IN) +Endpoint : out:O.outpad[0] (.output clocked by CLK_IN) +Path Type : setup + +Point Incr Path +-------------------------------------------------------------------------------- +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +input external delay 0.000 0.000 +$obuf_O.inpad[0] (.input) 0.000 0.000 +O.in[0] (.names) 0.890 0.890 +O.out[0] (.names) 0.218 1.109 +out:O.outpad[0] (.output) 0.890 1.999 +data arrival time 1.999 + +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +clock uncertainty 0.000 0.000 +output external delay 0.000 0.000 +data required time 0.000 +-------------------------------------------------------------------------------- +data required time 0.000 +data arrival time -1.999 +-------------------------------------------------------------------------------- +slack (VIOLATED) -1.999 + + +#Path 11 +Startpoint: dff.Q[0] (dffre clocked by CLK_IN) +Endpoint : out:dff.outpad[0] (.output clocked by CLK_IN) +Path Type : setup + +Point Incr Path +-------------------------------------------------------------------------------- +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +CLK_IN.inpad[0] (.input) 0.000 0.000 +dff.C[0] (dffre) 0.890 0.890 +dff.Q[0] (dffre) [clock-to-output] 0.154 1.044 +out:dff.outpad[0] (.output) 0.890 1.935 +data arrival time 1.935 + +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +clock uncertainty 0.000 0.000 +output external delay 0.000 0.000 +data required time 0.000 +-------------------------------------------------------------------------------- +data required time 0.000 +data arrival time -1.935 +-------------------------------------------------------------------------------- +slack (VIOLATED) -1.935 + + +#Path 12 +Startpoint: in.inpad[0] (.input clocked by CLK_IN) +Endpoint : dff.D[0] (dffre clocked by CLK_IN) +Path Type : setup + +Point Incr Path +-------------------------------------------------------------------------------- +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +input external delay 0.000 0.000 +in.inpad[0] (.input) 0.000 0.000 +$abc$192$li0_li0.in[0] (.names) 0.890 0.890 +$abc$192$li0_li0.out[0] (.names) 0.218 1.109 +dff.D[0] (dffre) 0.890 1.999 +data arrival time 1.999 + +clock CLK_IN (rise edge) 0.000 0.000 +clock source latency 0.000 0.000 +CLK_IN.inpad[0] (.input) 0.000 0.000 +dff.C[0] (dffre) 0.890 0.890 +clock uncertainty 0.000 0.890 +cell setup time -0.032 0.859 +data required time 0.859 +-------------------------------------------------------------------------------- +data required time 0.859 +data arrival time -1.999 +-------------------------------------------------------------------------------- +slack (VIOLATED) -1.140 + + +#End of timing report diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/reports/packing_design_stat.json b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/reports/packing_design_stat.json new file mode 100644 index 00000000..a6cccc6b --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/reports/packing_design_stat.json @@ -0,0 +1,40 @@ +[ + { + "": { + "header": [ + "Design statistics", + "" + ], + "data": [ + [ + "CLB LUT packing percentage", + "1 %" + ], + [ + "CLB Register packing percentage", + "0 %" + ], + [ + "Wires", + "45" + ], + [ + "Max Fanout", + "15" + ], + [ + "Average Fanout", + "1.3" + ], + [ + "Maximum logic level", + "0" + ], + [ + "Average logic level", + "0" + ] + ] + } + } +] \ No newline at end of file diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/reports/packing_utilization.json b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/reports/packing_utilization.json new file mode 100644 index 00000000..fe24b53b --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/reports/packing_utilization.json @@ -0,0 +1,148 @@ +[ + { + "": { + "header": [ + "Logic", + "Used", + "Available", + "%" + ], + "data": [ + [ + "CLB", + "2", + "2184", + "0" + ], + [ + " LUTs", + "15", + "17472", + "0" + ], + [ + " LUT5", + "31", + "34944", + "0" + ], + [ + " LUT6", + "0", + "17472", + "0" + ], + [ + " Registers", + "1", + "34944", + "0" + ], + [ + " Flip Flop", + "1", + "34944", + "0" + ], + [ + " Adder Carry", + "0", + "17472", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "Block RAM", + "Used", + "Available", + "%" + ], + "data": [ + [ + "BRAM", + "0", + "56", + "0" + ], + [ + " 36k", + "0", + "56", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "DSP", + "Used", + "Available", + "%" + ], + "data": [ + [ + "DSP Block", + "0", + "56", + "0" + ], + [ + " 18x20", + "0", + "112", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "I/O", + "Used", + "Available", + "%" + ], + "data": [ + [ + "I/O", + "37", + "240", + "15" + ], + [ + " Inputs", + "13", + "240", + "5" + ], + [ + " Outputs", + "24", + "240", + "10" + ] + ] + } + }, + { + "": { + "header": [ + "Clock", + "Used" + ], + "data": [ + [ + "Clock", + "1" + ] + ] + } + } +] \ No newline at end of file diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/vpr_stdout.log b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/vpr_stdout.log new file mode 100644 index 00000000..fdf8f31a --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/vpr_stdout.log @@ -0,0 +1,451 @@ +VPR FPGA Placement and Routing. +Version: +Revision: +Compiled: +Compiler: GNU 11.2.1 on Linux-3.10.0-1160.90.1.el7.x86_64 x86_64 +Build Info: Release VTR_ASSERT_LEVEL=2 + +University of Toronto +verilogtorouting.org +vtr-users@googlegroups.com +This is free open source code under MIT license. + +VPR was run with the following command-line: +/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/vpr /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --sdc_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc --route_chan_width 160 --suppress_warnings check_rr_node_warnings.log,check_rr_node --clock_modeling ideal --absorb_buffer_luts off --skip_sync_clustering_and_routing_results off --constant_net_method route --post_place_timing_report I_DELAY_primitive_inst_post_place_timing.rpt --device castor62x44_heterogeneous --allow_unrelated_clustering on --allow_dangling_combinational_nodes on --place_delta_delay_matrix_calculation_method dijkstra --gen_post_synthesis_netlist on --post_synth_netlist_unconn_inputs gnd --inner_loop_recompute_divider 1 --max_router_iterations 1500 --timing_report_detail detailed --timing_report_npaths 100 --top I_DELAY_primitive_inst --net_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net --place_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place --route_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route --pack + +Using up to 1 parallel worker(s) + +Architecture file: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml +Circuit name: fabric_I_DELAY_primitive_inst_post_synth + +# Loading Architecture Description +Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 3: Model 'dsp_phy' input port 'sc_in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 4: Model 'dsp_phy' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 5: Model 'dsp_phy' output port 'sc_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 6: Model 'RS_DSP_MULT' input port 'feedback' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 7: Model 'RS_DSP_MULT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 8: Model 'RS_DSP_MULT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 9: Model 'RS_DSP_MULT_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 10: Model 'RS_DSP_MULT_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 11: Model 'RS_DSP_MULT_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 12: Model 'RS_DSP_MULT_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 13: Model 'RS_DSP_MULT_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 14: Model 'RS_DSP_MULT_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 15: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 16: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 17: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 18: Model 'RS_DSP_MULTADD' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 19: Model 'RS_DSP_MULTADD' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 20: Model 'RS_DSP_MULTADD' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 21: Model 'RS_DSP_MULTADD' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 22: Model 'RS_DSP_MULTADD' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 23: Model 'RS_DSP_MULTADD' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 24: Model 'RS_DSP_MULTADD_REGIN' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 25: Model 'RS_DSP_MULTADD_REGIN' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 26: Model 'RS_DSP_MULTADD_REGIN' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 27: Model 'RS_DSP_MULTADD_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 28: Model 'RS_DSP_MULTADD_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 29: Model 'RS_DSP_MULTADD_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 30: Model 'RS_DSP_MULTADD_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 31: Model 'RS_DSP_MULTADD_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 32: Model 'RS_DSP_MULTADD_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 33: Model 'RS_DSP_MULTADD_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 34: Model 'RS_DSP_MULTADD_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 35: Model 'RS_DSP_MULTADD_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 36: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 37: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 38: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 39: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 40: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 41: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 42: Model 'RS_DSP_MULTACC' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 43: Model 'RS_DSP_MULTACC' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 44: Model 'RS_DSP_MULTACC' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 45: Model 'RS_DSP_MULTACC' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 46: Model 'RS_DSP_MULTACC' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 47: Model 'RS_DSP_MULTACC' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 48: Model 'RS_DSP_MULTACC_REGIN' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 49: Model 'RS_DSP_MULTACC_REGIN' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 50: Model 'RS_DSP_MULTACC_REGIN' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 51: Model 'RS_DSP_MULTACC_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 52: Model 'RS_DSP_MULTACC_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 53: Model 'RS_DSP_MULTACC_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 54: Model 'RS_DSP_MULTACC_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 55: Model 'RS_DSP_MULTACC_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 56: Model 'RS_DSP_MULTACC_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 57: Model 'RS_DSP_MULTACC_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 58: Model 'RS_DSP_MULTACC_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 59: Model 'RS_DSP_MULTACC_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 60: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 61: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 62: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 63: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 64: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 65: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 66: Model 'bram_phy' input port 'sc_in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 67: Model 'bram_phy' output port 'sc_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 68: Model 'bram_phy' output port 'PL_DATA_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 69: Model 'bram_phy' output port 'PL_ADDR_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 70: Model 'bram_phy' output port 'PL_WEN_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 71: Model 'bram_phy' output port 'PL_CLK_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 72: Model 'bram_phy' output port 'PL_REN_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 73: Model 'bram_phy' output port 'PL_ENA_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 74: Model 'bram_phy' output port 'PL_INIT_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +mode 'io[physical]' is defined by user to be disabled in packing +mode 'iopad[default]' is defined by user to be disabled in packing +mode 'fle[physical]' is defined by user to be disabled in packing +mode 'fabric[default]' is defined by user to be disabled in packing +mode 'ff_bypass[default]' is defined by user to be disabled in packing +mode 'dsp_lr[physical]' is defined by user to be disabled in packing +mode 'bram_lr[physical]' is defined by user to be disabled in packing +# Loading Architecture Description took 0.06 seconds (max_rss 17.2 MiB, delta_rss +0.0 MiB) + +Timing analysis: ON +Circuit netlist file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net +Circuit placement file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place +Circuit routing file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route +Circuit SDC file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc +Vpr floorplanning constraints file: not specified + +Packer: ENABLED +Placer: DISABLED +Router: DISABLED +Analysis: DISABLED + +VPR was run with the following options: + +NetlistOpts.abosrb_buffer_luts : false +NetlistOpts.sweep_dangling_primary_ios : true +NetlistOpts.sweep_dangling_nets : true +NetlistOpts.sweep_dangling_blocks : true +NetlistOpts.sweep_constant_primary_outputs: false +NetlistOpts.netlist_verbosity : 1 +NetlistOpts.const_gen_inference : COMB_SEQ + +PackerOpts.allow_unrelated_clustering: true +PackerOpts.alpha_clustering: 0.750000 +PackerOpts.beta_clustering: 0.900000 +PackerOpts.cluster_seed_type: BLEND2 +PackerOpts.connection_driven: true +PackerOpts.global_clocks: true +PackerOpts.hill_climbing_flag: false +PackerOpts.inter_cluster_net_delay: 1.000000 +PackerOpts.timing_driven: true +PackerOpts.target_external_pin_util: auto + +# Building complex block graph +Warning 75: clb[0].sr_in[0] unconnected pin in architecture. +Warning 76: clb[0].sr_out[0] unconnected pin in architecture. +Warning 77: dsp[0].sr_in[0] unconnected pin in architecture. +Warning 78: dsp[0].sr_in[1] unconnected pin in architecture. +Warning 79: dsp[0].sr_in[2] unconnected pin in architecture. +Warning 80: dsp[0].sr_out[0] unconnected pin in architecture. +Warning 81: dsp[0].sr_out[1] unconnected pin in architecture. +Warning 82: dsp[0].sr_out[2] unconnected pin in architecture. +Warning 83: bram[0].sr_in[0] unconnected pin in architecture. +Warning 84: bram[0].sr_in[1] unconnected pin in architecture. +Warning 85: bram[0].sr_in[2] unconnected pin in architecture. +Warning 86: bram[0].sr_in[3] unconnected pin in architecture. +Warning 87: bram[0].sr_in[4] unconnected pin in architecture. +Warning 88: bram[0].sr_in[5] unconnected pin in architecture. +Warning 89: bram[0].plr_i[0] unconnected pin in architecture. +Warning 90: bram[0].plr_i[1] unconnected pin in architecture. +Warning 91: bram[0].plr_i[2] unconnected pin in architecture. +Warning 92: bram[0].plr_i[3] unconnected pin in architecture. +Warning 93: bram[0].plr_i[4] unconnected pin in architecture. +Warning 94: bram[0].plr_i[5] unconnected pin in architecture. +Warning 95: bram[0].plr_i[6] unconnected pin in architecture. +Warning 96: bram[0].plr_i[7] unconnected pin in architecture. +Warning 97: bram[0].plr_i[8] unconnected pin in architecture. +Warning 98: bram[0].plr_i[9] unconnected pin in architecture. +Warning 99: bram[0].plr_i[10] unconnected pin in architecture. +Warning 100: bram[0].plr_i[11] unconnected pin in architecture. +Warning 101: bram[0].plr_i[12] unconnected pin in architecture. +Warning 102: bram[0].plr_i[13] unconnected pin in architecture. +Warning 103: bram[0].plr_i[14] unconnected pin in architecture. +Warning 104: bram[0].plr_i[15] unconnected pin in architecture. +Warning 105: bram[0].plr_i[16] unconnected pin in architecture. +Warning 106: bram[0].plr_i[17] unconnected pin in architecture. +Warning 107: bram[0].plr_i[18] unconnected pin in architecture. +Warning 108: bram[0].plr_i[19] unconnected pin in architecture. +Warning 109: bram[0].plr_i[20] unconnected pin in architecture. +Warning 110: bram[0].plr_i[21] unconnected pin in architecture. +Warning 111: bram[0].plr_i[22] unconnected pin in architecture. +Warning 112: bram[0].plr_i[23] unconnected pin in architecture. +Warning 113: bram[0].plr_i[24] unconnected pin in architecture. +Warning 114: bram[0].plr_i[25] unconnected pin in architecture. +Warning 115: bram[0].plr_i[26] unconnected pin in architecture. +Warning 116: bram[0].plr_i[27] unconnected pin in architecture. +Warning 117: bram[0].plr_i[28] unconnected pin in architecture. +Warning 118: bram[0].plr_i[29] unconnected pin in architecture. +Warning 119: bram[0].plr_i[30] unconnected pin in architecture. +Warning 120: bram[0].plr_i[31] unconnected pin in architecture. +Warning 121: bram[0].plr_i[32] unconnected pin in architecture. +Warning 122: bram[0].plr_i[33] unconnected pin in architecture. +Warning 123: bram[0].plr_i[34] unconnected pin in architecture. +Warning 124: bram[0].plr_i[35] unconnected pin in architecture. +Warning 125: bram[0].sr_out[0] unconnected pin in architecture. +Warning 126: bram[0].sr_out[1] unconnected pin in architecture. +Warning 127: bram[0].sr_out[2] unconnected pin in architecture. +Warning 128: bram[0].sr_out[3] unconnected pin in architecture. +Warning 129: bram[0].sr_out[4] unconnected pin in architecture. +Warning 130: bram[0].sr_out[5] unconnected pin in architecture. +Warning 131: bram[0].plr_o[0] unconnected pin in architecture. +Warning 132: bram[0].plr_o[1] unconnected pin in architecture. +Warning 133: bram[0].plr_o[2] unconnected pin in architecture. +Warning 134: bram[0].plr_o[3] unconnected pin in architecture. +Warning 135: bram[0].plr_o[4] unconnected pin in architecture. +Warning 136: bram[0].plr_o[5] unconnected pin in architecture. +Warning 137: bram[0].plr_o[6] unconnected pin in architecture. +Warning 138: bram[0].plr_o[7] unconnected pin in architecture. +Warning 139: bram[0].plr_o[8] unconnected pin in architecture. +Warning 140: bram[0].plr_o[9] unconnected pin in architecture. +Warning 141: bram[0].plr_o[10] unconnected pin in architecture. +Warning 142: bram[0].plr_o[11] unconnected pin in architecture. +Warning 143: bram[0].plr_o[12] unconnected pin in architecture. +Warning 144: bram[0].plr_o[13] unconnected pin in architecture. +Warning 145: bram[0].plr_o[14] unconnected pin in architecture. +Warning 146: bram[0].plr_o[15] unconnected pin in architecture. +Warning 147: bram[0].plr_o[16] unconnected pin in architecture. +Warning 148: bram[0].plr_o[17] unconnected pin in architecture. +Warning 149: bram[0].plr_o[18] unconnected pin in architecture. +Warning 150: bram[0].plr_o[19] unconnected pin in architecture. +Warning 151: bram[0].plr_o[20] unconnected pin in architecture. +Warning 152: bram[0].plr_o[21] unconnected pin in architecture. +Warning 153: bram[0].plr_o[22] unconnected pin in architecture. +Warning 154: bram[0].plr_o[23] unconnected pin in architecture. +Warning 155: bram[0].plr_o[24] unconnected pin in architecture. +Warning 156: bram[0].plr_o[25] unconnected pin in architecture. +Warning 157: bram[0].plr_o[26] unconnected pin in architecture. +Warning 158: bram[0].plr_o[27] unconnected pin in architecture. +Warning 159: bram[0].plr_o[28] unconnected pin in architecture. +Warning 160: bram[0].plr_o[29] unconnected pin in architecture. +Warning 161: bram[0].plr_o[30] unconnected pin in architecture. +Warning 162: bram[0].plr_o[31] unconnected pin in architecture. +Warning 163: bram[0].plr_o[32] unconnected pin in architecture. +Warning 164: bram[0].plr_o[33] unconnected pin in architecture. +Warning 165: bram[0].plr_o[34] unconnected pin in architecture. +Warning 166: bram[0].plr_o[35] unconnected pin in architecture. +# Building complex block graph took 0.04 seconds (max_rss 18.2 MiB, delta_rss +1.1 MiB) +Circuit file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif +# Load circuit +Found constant-zero generator '$false' +Found constant-one generator '$true' +Found constant-zero generator '$undef' +# Load circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.5 MiB) +# Clean circuit +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 13 additional primitive pins as constant generators due to constant inputs +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 0 additional primitive pins as constant generators due to constant inputs +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 0 additional primitive pins as constant generators due to constant inputs +Swept input(s) : 0 +Swept output(s) : 0 (0 dangling, 0 constant) +Swept net(s) : 2 +Swept block(s) : 2 +Constant Pins Marked: 13 +# Clean circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +# Compress circuit +# Compress circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +# Verify circuit +# Verify circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +Circuit Statistics: + Blocks: 69 + .input : 13 + .output: 24 + 0-LUT : 1 + 6-LUT : 30 + dffre : 1 + Nets : 45 + Avg Fanout: 1.3 + Max Fanout: 15.0 + Min Fanout: 1.0 + Netlist Clocks: 1 +# Build Timing Graph + Timing Graph Nodes: 104 + Timing Graph Edges: 94 + Timing Graph Levels: 6 +# Build Timing Graph took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +Netlist contains 1 clocks + Netlist Clock '$clk_buf_$ibuf_CLK_IN' Fanout: 1 pins (1.0%), 1 blocks (1.4%) +# Load Timing Constraints + +SDC file '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc' contained no SDC commands +Setting default timing constraints: + * constrain all primay inputs and primary outputs on netlist clock '$clk_buf_$ibuf_CLK_IN' + * optimize netlist clock to run as fast as possible +Timing constraints created 1 clocks + Constrained Clock '$clk_buf_$ibuf_CLK_IN' Source: '$clk_buf_$ibuf_CLK_IN.inpad[0]' + +# Load Timing Constraints took 0.00 seconds (max_rss 19.0 MiB, delta_rss +0.3 MiB) +# Packing +Begin packing '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif'. + +After removing unused inputs... + total blocks: 69, total nets: 45, total inputs: 13, total outputs: 24 +Begin prepacking. + +There is one chain in this architecture called "carrychain" with the following starting points: + clb[0]/clb_lr[0]/fle[0]/adder[0]/adder_carry[0].cin[0] + +0 attraction groups were created during prepacking. +Finish prepacking. +Using inter-cluster delay: 8.9048e-10 +Packing with pin utilization targets: io_top:1,1 io_right:1,1 io_bottom:1,1 io_left:1,1 clb:0.8,1 dsp:1,1 bram:1,1 +Packing with high fanout thresholds: io_top:128 io_right:128 io_bottom:128 io_left:128 clb:32 dsp:128 bram:128 +Starting Clustering - Clustering Progress: +------------------- -------------------------- --------- +Molecules processed Number of clusters created FPGA size +------------------- -------------------------- --------- + 2/68 2% 1 64 x 46 + 4/68 5% 1 64 x 46 + 6/68 8% 1 64 x 46 + 8/68 11% 1 64 x 46 + 10/68 14% 1 64 x 46 + 12/68 17% 1 64 x 46 + 14/68 20% 1 64 x 46 + 16/68 23% 1 64 x 46 + 18/68 26% 2 64 x 46 + 20/68 29% 2 64 x 46 + 22/68 32% 2 64 x 46 + 24/68 35% 2 64 x 46 + 26/68 38% 2 64 x 46 + 28/68 41% 2 64 x 46 + 30/68 44% 2 64 x 46 + 32/68 47% 2 64 x 46 + 34/68 50% 4 64 x 46 + 36/68 52% 6 64 x 46 + 38/68 55% 8 64 x 46 + 40/68 58% 10 64 x 46 + 42/68 61% 12 64 x 46 + 44/68 64% 14 64 x 46 + 46/68 67% 16 64 x 46 + 48/68 70% 18 64 x 46 + 50/68 73% 20 64 x 46 + 52/68 76% 22 64 x 46 + 54/68 79% 24 64 x 46 + 56/68 82% 26 64 x 46 + 58/68 85% 28 64 x 46 + 60/68 88% 30 64 x 46 + 62/68 91% 32 64 x 46 + 64/68 94% 34 64 x 46 + 66/68 97% 36 64 x 46 + 68/68 100% 38 64 x 46 + +Logic Element (fle) detailed count: + Total number of Logic Elements used : 16 + LEs used for logic and registers : 0 + LEs used for logic only : 16 + LEs used for registers only : 0 + +Incr Slack updates 1 in 3.518e-06 sec +Full Max Req/Worst Slack updates 1 in 6.294e-06 sec +Incr Max Req/Worst Slack updates 0 in 0 sec +Incr Criticality updates 0 in 0 sec +Full Criticality updates 1 in 8.597e-06 sec +FPGA sized to 64 x 46 (castor62x44_heterogeneous) +Device Utilization: 0.00 (target 1.00) + Block Utilization: 0.00 Type: io + Block Utilization: 0.00 Type: clb + +Start the iterative improvement process +the iterative improvement process is done +Clustering Statistics: +---------- -------- ------------------------------------ -------------------------- +Block Type # Blocks Avg. # of input clocks and pins used Avg. # of output pins used +---------- -------- ------------------------------------ -------------------------- + EMPTY 0 0 0 + io 37 0.648649 0.351351 + clb 2 8 13 + dsp 0 0 0 + bram 0 0 0 +Absorbed logical nets 6 out of 45 nets, 39 nets not absorbed. + +Netlist conversion complete. + +# Packing took 0.02 seconds (max_rss 20.9 MiB, delta_rss +1.6 MiB) +# Load packing +Begin loading packed FPGA netlist file. +Netlist generated from file '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net'. +Detected 1 constant generators (to see names run with higher pack verbosity) +Finished loading packed FPGA netlist file (took 0.05 seconds). +# Load packing took 0.05 seconds (max_rss 59.0 MiB, delta_rss +38.1 MiB) +Warning 167: Netlist contains 0 global net to non-global architecture pin connections + +Pb types usage... + io : 37 + io_output : 24 + outpad : 24 + io_input : 13 + inpad : 13 + clb : 2 + clb_lr : 2 + fle : 16 + ble5 : 31 + lut5 : 31 + lut : 31 + ff : 1 + DFFRE : 1 + +# Create Device +## Build Device Grid +FPGA sized to 64 x 46: 2944 grid tiles (castor62x44_heterogeneous) + +Resource usage... + Netlist + 37 blocks of type: io + Architecture + 4320 blocks of type: io_top + 3168 blocks of type: io_right + 4320 blocks of type: io_bottom + 3168 blocks of type: io_left + Netlist + 2 blocks of type: clb + Architecture + 2184 blocks of type: clb + Netlist + 0 blocks of type: dsp + Architecture + 56 blocks of type: dsp + Netlist + 0 blocks of type: bram + Architecture + 56 blocks of type: bram + +Device Utilization: 0.00 (target 1.00) + Physical Tile io_top: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_right: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_bottom: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_left: + Block Utilization: 0.01 Logical Block: io + Physical Tile clb: + Block Utilization: 0.00 Logical Block: clb + Physical Tile dsp: + Block Utilization: 0.00 Logical Block: dsp + Physical Tile bram: + Block Utilization: 0.00 Logical Block: bram + +## Build Device Grid took 0.00 seconds (max_rss 59.1 MiB, delta_rss +0.0 MiB) +Warning 168: Tileable routing resource graph does not support clock modeling yet! Related options are ignored... +## Build tileable routing resource graph +X-direction routing channel width is 160 +Y-direction routing channel width is 160 +Warning 169: Sized nonsensical R=0 transistor to minimum width +Warning 170: Sized nonsensical R=0 transistor to minimum width +Warning 171: Sized nonsensical R=0 transistor to minimum width +Warning 172: Sized nonsensical R=0 transistor to minimum width +## Build tileable routing resource graph took 13.42 seconds (max_rss 473.6 MiB, delta_rss +414.5 MiB) + RR Graph Nodes: 1365608 + RR Graph Edges: 6033268 +# Create Device took 14.03 seconds (max_rss 473.6 MiB, delta_rss +414.5 MiB) + + +Flow timing analysis took 0.00177694 seconds (0.00174604 STA, 3.0901e-05 slack) (1 full updates: 1 setup, 0 hold, 0 combined). +VPR succeeded +The entire flow of VPR took 14.56 seconds (max_rss 473.6 MiB) diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_openfpga.pcf b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_openfpga.pcf new file mode 100644 index 00000000..e69de29b diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_pin_loc.cmd b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_pin_loc.cmd new file mode 100644 index 00000000..b817160f --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_pin_loc.cmd @@ -0,0 +1 @@ +/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/planning --csv /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/Virgo_Pin_Table.csv --blif /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --output I_DELAY_primitive_inst_pin_loc.place --assign_unconstrained_pins in_define_order --clk_map I_DELAY_primitive_inst.temp_file_clkmap --read_repack /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/fpga_repack_constraints.xml --write_repack I_DELAY_primitive_inst_repack_constraints.xml --edits /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/config.json diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_pin_loc.place b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_pin_loc.place new file mode 100644 index 00000000..80741165 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_pin_loc.place @@ -0,0 +1,39 @@ +#Block Name x y z +#------------ -- -- - +$clk_buf_$ibuf_CLK_IN 51 44 23 # device: BOOT_PWM2_GPIO_12 pt_row: 59 Fullchip_N: fpga_pad_c[12] +$ibuf_DLY_ADJ 51 44 22 # device: BOOT_PWM3_GPIO_13 pt_row: 60 Fullchip_N: fpga_pad_c[13] +$ibuf_DLY_INCDEC 51 44 21 # device: BOOT_UART_CTS_GPIO_14 pt_row: 61 Fullchip_N: fpga_pad_c[14] +$ibuf_DLY_LOAD 51 44 20 # device: BOOT_UART_RTS_GPIO_15 pt_row: 62 Fullchip_N: fpga_pad_c[15] +$ibuf_in 48 44 23 # device: BOOT_CONFIG_DONE_GPIO_0 pt_row: 47 Fullchip_N: fpga_pad_c[0] +$ibuf_reset 48 44 22 # device: BOOT_CONFIG_ERROR_GPIO_1 pt_row: 48 Fullchip_N: fpga_pad_c[1] +$ifab_$obuf_DLY_TAP_VALUE[0] 48 44 21 # device: BOOT_UART_TX_GPIO_2 pt_row: 49 Fullchip_N: fpga_pad_c[2] +$ifab_$obuf_DLY_TAP_VALUE[1] 48 44 20 # device: BOOT_UART_RX_GPIO_3 pt_row: 50 Fullchip_N: fpga_pad_c[3] +$ifab_$obuf_DLY_TAP_VALUE[2] 48 44 19 # device: BOOT_SPI_CS_GPIO_4 pt_row: 51 Fullchip_N: fpga_pad_c[4] +$ifab_$obuf_DLY_TAP_VALUE[3] 48 44 18 # device: BOOT_SPI_MOSI_DQ0_GPIO_5 pt_row: 52 Fullchip_N: fpga_pad_c[5] +$ifab_$obuf_DLY_TAP_VALUE[4] 48 44 17 # device: BOOT_SPI_MISO_DQ1_GPIO_6 pt_row: 53 Fullchip_N: fpga_pad_c[6] +$ifab_$obuf_DLY_TAP_VALUE[5] 48 44 16 # device: BOOT_SPI_DQ2_GPIO_7 pt_row: 54 Fullchip_N: fpga_pad_c[7] +$obuf_O 48 44 15 # device: BOOT_SPI_DQ3_GPIO_8 pt_row: 55 Fullchip_N: fpga_pad_c[8] +out:$auto_440 49 44 71 # device: BOOT_CONFIG_DONE_GPIO_0 pt_row: 15 Fullchip_N: fpga_pad_i[0] +out:$auto_441 49 44 70 # device: BOOT_CONFIG_ERROR_GPIO_1 pt_row: 16 Fullchip_N: fpga_pad_i[1] +out:$auto_442 49 44 69 # device: BOOT_UART_TX_GPIO_2 pt_row: 17 Fullchip_N: fpga_pad_i[2] +out:$auto_443 49 44 68 # device: BOOT_UART_RX_GPIO_3 pt_row: 18 Fullchip_N: fpga_pad_i[3] +out:$auto_444 49 44 67 # device: BOOT_SPI_CS_GPIO_4 pt_row: 19 Fullchip_N: fpga_pad_i[4] +out:$auto_445 49 44 66 # device: BOOT_SPI_MOSI_DQ0_GPIO_5 pt_row: 20 Fullchip_N: fpga_pad_i[5] +out:$auto_446 49 44 65 # device: BOOT_SPI_MISO_DQ1_GPIO_6 pt_row: 21 Fullchip_N: fpga_pad_i[6] +out:$auto_447 49 44 64 # device: BOOT_SPI_DQ2_GPIO_7 pt_row: 22 Fullchip_N: fpga_pad_i[7] +out:$auto_448 49 44 63 # device: BOOT_SPI_DQ3_GPIO_8 pt_row: 23 Fullchip_N: fpga_pad_i[8] +out:$auto_449 49 44 62 # device: BOOT_I2C_SDA_GPIO_9 pt_row: 24 Fullchip_N: fpga_pad_i[9] +out:$auto_450 49 44 61 # device: BOOT_PWM0_GPIO_10 pt_row: 25 Fullchip_N: fpga_pad_i[10] +out:$auto_451 49 44 60 # device: BOOT_PWM1_GPIO_11 pt_row: 26 Fullchip_N: fpga_pad_i[11] +out:$auto_452 49 44 59 # device: BOOT_PWM2_GPIO_12 pt_row: 27 Fullchip_N: fpga_pad_i[12] +out:$auto_453 49 44 58 # device: BOOT_PWM3_GPIO_13 pt_row: 28 Fullchip_N: fpga_pad_i[13] +out:$f2g_trx_dly_adj_$ibuf_DLY_ADJ 49 44 57 # device: BOOT_UART_CTS_GPIO_14 pt_row: 29 Fullchip_N: fpga_pad_i[14] +out:$f2g_trx_dly_inc_$ibuf_DLY_INCDEC 49 44 56 # device: BOOT_UART_RTS_GPIO_15 pt_row: 30 Fullchip_N: fpga_pad_i[15] +out:$f2g_trx_dly_ld_$ibuf_DLY_LOAD 51 44 71 # device: BOOT_CONFIG_DONE_GPIO_0 pt_row: 31 Fullchip_N: fpga_pad_oen[0] +out:$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] 51 44 70 # device: BOOT_CONFIG_ERROR_GPIO_1 pt_row: 32 Fullchip_N: fpga_pad_oen[1] +out:$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] 51 44 69 # device: BOOT_UART_TX_GPIO_2 pt_row: 33 Fullchip_N: fpga_pad_oen[2] +out:$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] 51 44 68 # device: BOOT_UART_RX_GPIO_3 pt_row: 34 Fullchip_N: fpga_pad_oen[3] +out:$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] 51 44 67 # device: BOOT_SPI_CS_GPIO_4 pt_row: 35 Fullchip_N: fpga_pad_oen[4] +out:$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] 51 44 66 # device: BOOT_SPI_MOSI_DQ0_GPIO_5 pt_row: 36 Fullchip_N: fpga_pad_oen[5] +out:$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] 51 44 65 # device: BOOT_SPI_MISO_DQ1_GPIO_6 pt_row: 37 Fullchip_N: fpga_pad_oen[6] +$obuf_O 51 44 64 # device: BOOT_SPI_DQ2_GPIO_7 pt_row: 38 Fullchip_N: fpga_pad_oen[7] diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_place.cmd b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_place.cmd new file mode 100644 index 00000000..53426d1c --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_place.cmd @@ -0,0 +1 @@ +/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/vpr /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --sdc_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc --route_chan_width 160 --suppress_warnings check_rr_node_warnings.log,check_rr_node --clock_modeling ideal --absorb_buffer_luts off --skip_sync_clustering_and_routing_results off --constant_net_method route --post_place_timing_report I_DELAY_primitive_inst_post_place_timing.rpt --device castor62x44_heterogeneous --allow_unrelated_clustering on --allow_dangling_combinational_nodes on --place_delta_delay_matrix_calculation_method dijkstra --gen_post_synthesis_netlist on --post_synth_netlist_unconn_inputs gnd --inner_loop_recompute_divider 1 --max_router_iterations 1500 --timing_report_detail detailed --timing_report_npaths 100 --top I_DELAY_primitive_inst --net_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net --place_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place --route_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route --place --fix_clusters I_DELAY_primitive_inst_pin_loc.place diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_repack_constraints.xml b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_repack_constraints.xml new file mode 100644 index 00000000..59707b79 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_repack_constraints.xml @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/check_rr_node_warnings.log b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/check_rr_node_warnings.log new file mode 100644 index 00000000..e69de29b diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/packing_pin_util.rpt b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/packing_pin_util.rpt new file mode 100644 index 00000000..ce61bb36 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/packing_pin_util.rpt @@ -0,0 +1,89 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.09 +Build : 1.2.3 +Hash : 89d4d1b +Date : Sep 19 2024 +Type : Engineering +Log Time : Thu Sep 19 08:36:51 2024 GMT +#Packing pin usage report +Type: io + Input Pin Usage: + Max: 1.00 (0.06) + Avg: 0.65 (0.04) + Min: 0.00 (0.00) + Histogram: + [ 0: 1.8) 37 (100.0%) |************************************************ + [ 1.8: 3.6) 0 ( 0.0%) | + [ 3.6: 5.4) 0 ( 0.0%) | + [ 5.4: 7.2) 0 ( 0.0%) | + [ 7.2: 9) 0 ( 0.0%) | + [ 9: 11) 0 ( 0.0%) | + [ 11: 13) 0 ( 0.0%) | + [ 13: 14) 0 ( 0.0%) | + [ 14: 16) 0 ( 0.0%) | + [ 16: 18) 0 ( 0.0%) | + Output Pin Usage: + Max: 1.00 (0.50) + Avg: 0.35 (0.18) + Min: 0.00 (0.00) + Histogram: + [ 0: 0.2) 24 ( 64.9%) |************************************************ + [ 0.2: 0.4) 0 ( 0.0%) | + [ 0.4: 0.6) 0 ( 0.0%) | + [ 0.6: 0.8) 0 ( 0.0%) | + [ 0.8: 1) 13 ( 35.1%) |************************** + [ 1: 1.2) 0 ( 0.0%) | + [ 1.2: 1.4) 0 ( 0.0%) | + [ 1.4: 1.6) 0 ( 0.0%) | + [ 1.6: 1.8) 0 ( 0.0%) | + [ 1.8: 2) 0 ( 0.0%) | + +Type: clb + Input Pin Usage: + Max: 10.00 (0.14) + Avg: 8.00 (0.11) + Min: 6.00 (0.08) + Histogram: + [ 0: 7.3) 1 ( 50.0%) |************************************************** + [ 7.3: 15) 1 ( 50.0%) |************************************************** + [ 15: 22) 0 ( 0.0%) | + [ 22: 29) 0 ( 0.0%) | + [ 29: 36) 0 ( 0.0%) | + [ 36: 44) 0 ( 0.0%) | + [ 44: 51) 0 ( 0.0%) | + [ 51: 58) 0 ( 0.0%) | + [ 58: 66) 0 ( 0.0%) | + [ 66: 73) 0 ( 0.0%) | + Output Pin Usage: + Max: 16.00 (0.59) + Avg: 13.00 (0.48) + Min: 10.00 (0.37) + Histogram: + [ 0: 2.7) 0 ( 0.0%) | + [ 2.7: 5.4) 0 ( 0.0%) | + [ 5.4: 8.1) 0 ( 0.0%) | + [ 8.1: 11) 1 ( 50.0%) |************************************************** + [ 11: 14) 0 ( 0.0%) | + [ 14: 16) 1 ( 50.0%) |************************************************** + [ 16: 19) 0 ( 0.0%) | + [ 19: 22) 0 ( 0.0%) | + [ 22: 24) 0 ( 0.0%) | + [ 24: 27) 0 ( 0.0%) | + diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/placement.rpt b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/placement.rpt new file mode 100644 index 00000000..bd01d2d8 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/placement.rpt @@ -0,0 +1,971 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.09 +Build : 1.2.3 +Hash : 89d4d1b +Date : Sep 19 2024 +Type : Engineering +Log Time : Thu Sep 19 08:36:51 2024 GMT +VPR FPGA Placement and Routing. +Version: +Revision: +Compiled: +Compiler: GNU 11.2.1 on Linux-3.10.0-1160.90.1.el7.x86_64 x86_64 +Build Info: Release VTR_ASSERT_LEVEL=2 + +University of Toronto +verilogtorouting.org +vtr-users@googlegroups.com +This is free open source code under MIT license. + +VPR was run with the following command-line: +/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/vpr /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --sdc_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc --route_chan_width 160 --suppress_warnings check_rr_node_warnings.log,check_rr_node --clock_modeling ideal --absorb_buffer_luts off --skip_sync_clustering_and_routing_results off --constant_net_method route --post_place_timing_report I_DELAY_primitive_inst_post_place_timing.rpt --device castor62x44_heterogeneous --allow_unrelated_clustering on --allow_dangling_combinational_nodes on --place_delta_delay_matrix_calculation_method dijkstra --gen_post_synthesis_netlist on --post_synth_netlist_unconn_inputs gnd --inner_loop_recompute_divider 1 --max_router_iterations 1500 --timing_report_detail detailed --timing_report_npaths 100 --top I_DELAY_primitive_inst --net_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net --place_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place --route_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route --place --fix_clusters I_DELAY_primitive_inst_pin_loc.place + +Using up to 1 parallel worker(s) + +Architecture file: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml +Circuit name: fabric_I_DELAY_primitive_inst_post_synth + +# Loading Architecture Description +Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 3: Model 'dsp_phy' input port 'sc_in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 4: Model 'dsp_phy' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 5: Model 'dsp_phy' output port 'sc_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 6: Model 'RS_DSP_MULT' input port 'feedback' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 7: Model 'RS_DSP_MULT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 8: Model 'RS_DSP_MULT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 9: Model 'RS_DSP_MULT_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 10: Model 'RS_DSP_MULT_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 11: Model 'RS_DSP_MULT_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 12: Model 'RS_DSP_MULT_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 13: Model 'RS_DSP_MULT_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 14: Model 'RS_DSP_MULT_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 15: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 16: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 17: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 18: Model 'RS_DSP_MULTADD' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 19: Model 'RS_DSP_MULTADD' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 20: Model 'RS_DSP_MULTADD' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 21: Model 'RS_DSP_MULTADD' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 22: Model 'RS_DSP_MULTADD' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 23: Model 'RS_DSP_MULTADD' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 24: Model 'RS_DSP_MULTADD_REGIN' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 25: Model 'RS_DSP_MULTADD_REGIN' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 26: Model 'RS_DSP_MULTADD_REGIN' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 27: Model 'RS_DSP_MULTADD_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 28: Model 'RS_DSP_MULTADD_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 29: Model 'RS_DSP_MULTADD_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 30: Model 'RS_DSP_MULTADD_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 31: Model 'RS_DSP_MULTADD_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 32: Model 'RS_DSP_MULTADD_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 33: Model 'RS_DSP_MULTADD_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 34: Model 'RS_DSP_MULTADD_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 35: Model 'RS_DSP_MULTADD_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 36: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 37: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 38: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 39: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 40: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 41: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 42: Model 'RS_DSP_MULTACC' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 43: Model 'RS_DSP_MULTACC' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 44: Model 'RS_DSP_MULTACC' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 45: Model 'RS_DSP_MULTACC' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 46: Model 'RS_DSP_MULTACC' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 47: Model 'RS_DSP_MULTACC' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 48: Model 'RS_DSP_MULTACC_REGIN' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 49: Model 'RS_DSP_MULTACC_REGIN' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 50: Model 'RS_DSP_MULTACC_REGIN' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 51: Model 'RS_DSP_MULTACC_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 52: Model 'RS_DSP_MULTACC_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 53: Model 'RS_DSP_MULTACC_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 54: Model 'RS_DSP_MULTACC_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 55: Model 'RS_DSP_MULTACC_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 56: Model 'RS_DSP_MULTACC_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 57: Model 'RS_DSP_MULTACC_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 58: Model 'RS_DSP_MULTACC_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 59: Model 'RS_DSP_MULTACC_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 60: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 61: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 62: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 63: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 64: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 65: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 66: Model 'bram_phy' input port 'sc_in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 67: Model 'bram_phy' output port 'sc_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 68: Model 'bram_phy' output port 'PL_DATA_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 69: Model 'bram_phy' output port 'PL_ADDR_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 70: Model 'bram_phy' output port 'PL_WEN_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 71: Model 'bram_phy' output port 'PL_CLK_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 72: Model 'bram_phy' output port 'PL_REN_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 73: Model 'bram_phy' output port 'PL_ENA_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 74: Model 'bram_phy' output port 'PL_INIT_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +mode 'io[physical]' is defined by user to be disabled in packing +mode 'iopad[default]' is defined by user to be disabled in packing +mode 'fle[physical]' is defined by user to be disabled in packing +mode 'fabric[default]' is defined by user to be disabled in packing +mode 'ff_bypass[default]' is defined by user to be disabled in packing +mode 'dsp_lr[physical]' is defined by user to be disabled in packing +mode 'bram_lr[physical]' is defined by user to be disabled in packing +# Loading Architecture Description took 0.06 seconds (max_rss 17.2 MiB, delta_rss +0.0 MiB) + +Timing analysis: ON +Circuit netlist file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net +Circuit placement file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place +Circuit routing file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route +Circuit SDC file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc +Vpr floorplanning constraints file: not specified + +Packer: ENABLED +Placer: ENABLED +Router: DISABLED +Analysis: DISABLED + +VPR was run with the following options: + +NetlistOpts.abosrb_buffer_luts : false +NetlistOpts.sweep_dangling_primary_ios : true +NetlistOpts.sweep_dangling_nets : true +NetlistOpts.sweep_dangling_blocks : true +NetlistOpts.sweep_constant_primary_outputs: false +NetlistOpts.netlist_verbosity : 1 +NetlistOpts.const_gen_inference : COMB_SEQ + +PackerOpts.allow_unrelated_clustering: true +PackerOpts.alpha_clustering: 0.750000 +PackerOpts.beta_clustering: 0.900000 +PackerOpts.cluster_seed_type: BLEND2 +PackerOpts.connection_driven: true +PackerOpts.global_clocks: true +PackerOpts.hill_climbing_flag: false +PackerOpts.inter_cluster_net_delay: 1.000000 +PackerOpts.timing_driven: true +PackerOpts.target_external_pin_util: auto + +PlacerOpts.place_freq: PLACE_ONCE +PlacerOpts.place_algorithm: CRITICALITY_TIMING_PLACE +PlacerOpts.pad_loc_type: FREE +PlacerOpts.constraints_file: Using constraints file 'I_DELAY_primitive_inst_pin_loc.place' +PlacerOpts.place_cost_exp: 1.000000 +PlacerOpts.place_chan_width: 160 +PlacerOpts.inner_loop_recompute_divider: 1 +PlacerOpts.recompute_crit_iter: 1 +PlacerOpts.timing_tradeoff: 0.500000 +PlacerOpts.td_place_exp_first: 1.000000 +PlacerOpts.td_place_exp_last: 8.000000 +PlacerOpts.delay_offset: 0.000000 +PlacerOpts.delay_ramp_delta_threshold: -1 +PlacerOpts.delay_ramp_slope: 0.000000 +PlacerOpts.tsu_rel_margin: 1.000000 +PlacerOpts.tsu_abs_margin: 0.000000 +PlacerOpts.post_place_timing_report_file: I_DELAY_primitive_inst_post_place_timing.rpt +PlacerOpts.allowed_tiles_for_delay_model: +PlacerOpts.delay_model_reducer: MIN +PlacerOpts.delay_model_type: DELTA +PlacerOpts.rlim_escape_fraction: 0.000000 +PlacerOpts.move_stats_file: +PlacerOpts.placement_saves_per_temperature: 0 +PlacerOpts.effort_scaling: CIRCUIT +PlacerOpts.place_delta_delay_matrix_calculation_method: DIJKSTRA_EXPANSION +PlaceOpts.seed: 1 +AnnealSched.type: AUTO_SCHED +AnnealSched.inner_num: 0.500000 + +# Building complex block graph +Warning 75: clb[0].sr_in[0] unconnected pin in architecture. +Warning 76: clb[0].sr_out[0] unconnected pin in architecture. +Warning 77: dsp[0].sr_in[0] unconnected pin in architecture. +Warning 78: dsp[0].sr_in[1] unconnected pin in architecture. +Warning 79: dsp[0].sr_in[2] unconnected pin in architecture. +Warning 80: dsp[0].sr_out[0] unconnected pin in architecture. +Warning 81: dsp[0].sr_out[1] unconnected pin in architecture. +Warning 82: dsp[0].sr_out[2] unconnected pin in architecture. +Warning 83: bram[0].sr_in[0] unconnected pin in architecture. +Warning 84: bram[0].sr_in[1] unconnected pin in architecture. +Warning 85: bram[0].sr_in[2] unconnected pin in architecture. +Warning 86: bram[0].sr_in[3] unconnected pin in architecture. +Warning 87: bram[0].sr_in[4] unconnected pin in architecture. +Warning 88: bram[0].sr_in[5] unconnected pin in architecture. +Warning 89: bram[0].plr_i[0] unconnected pin in architecture. +Warning 90: bram[0].plr_i[1] unconnected pin in architecture. +Warning 91: bram[0].plr_i[2] unconnected pin in architecture. +Warning 92: bram[0].plr_i[3] unconnected pin in architecture. +Warning 93: bram[0].plr_i[4] unconnected pin in architecture. +Warning 94: bram[0].plr_i[5] unconnected pin in architecture. +Warning 95: bram[0].plr_i[6] unconnected pin in architecture. +Warning 96: bram[0].plr_i[7] unconnected pin in architecture. +Warning 97: bram[0].plr_i[8] unconnected pin in architecture. +Warning 98: bram[0].plr_i[9] unconnected pin in architecture. +Warning 99: bram[0].plr_i[10] unconnected pin in architecture. +Warning 100: bram[0].plr_i[11] unconnected pin in architecture. +Warning 101: bram[0].plr_i[12] unconnected pin in architecture. +Warning 102: bram[0].plr_i[13] unconnected pin in architecture. +Warning 103: bram[0].plr_i[14] unconnected pin in architecture. +Warning 104: bram[0].plr_i[15] unconnected pin in architecture. +Warning 105: bram[0].plr_i[16] unconnected pin in architecture. +Warning 106: bram[0].plr_i[17] unconnected pin in architecture. +Warning 107: bram[0].plr_i[18] unconnected pin in architecture. +Warning 108: bram[0].plr_i[19] unconnected pin in architecture. +Warning 109: bram[0].plr_i[20] unconnected pin in architecture. +Warning 110: bram[0].plr_i[21] unconnected pin in architecture. +Warning 111: bram[0].plr_i[22] unconnected pin in architecture. +Warning 112: bram[0].plr_i[23] unconnected pin in architecture. +Warning 113: bram[0].plr_i[24] unconnected pin in architecture. +Warning 114: bram[0].plr_i[25] unconnected pin in architecture. +Warning 115: bram[0].plr_i[26] unconnected pin in architecture. +Warning 116: bram[0].plr_i[27] unconnected pin in architecture. +Warning 117: bram[0].plr_i[28] unconnected pin in architecture. +Warning 118: bram[0].plr_i[29] unconnected pin in architecture. +Warning 119: bram[0].plr_i[30] unconnected pin in architecture. +Warning 120: bram[0].plr_i[31] unconnected pin in architecture. +Warning 121: bram[0].plr_i[32] unconnected pin in architecture. +Warning 122: bram[0].plr_i[33] unconnected pin in architecture. +Warning 123: bram[0].plr_i[34] unconnected pin in architecture. +Warning 124: bram[0].plr_i[35] unconnected pin in architecture. +Warning 125: bram[0].sr_out[0] unconnected pin in architecture. +Warning 126: bram[0].sr_out[1] unconnected pin in architecture. +Warning 127: bram[0].sr_out[2] unconnected pin in architecture. +Warning 128: bram[0].sr_out[3] unconnected pin in architecture. +Warning 129: bram[0].sr_out[4] unconnected pin in architecture. +Warning 130: bram[0].sr_out[5] unconnected pin in architecture. +Warning 131: bram[0].plr_o[0] unconnected pin in architecture. +Warning 132: bram[0].plr_o[1] unconnected pin in architecture. +Warning 133: bram[0].plr_o[2] unconnected pin in architecture. +Warning 134: bram[0].plr_o[3] unconnected pin in architecture. +Warning 135: bram[0].plr_o[4] unconnected pin in architecture. +Warning 136: bram[0].plr_o[5] unconnected pin in architecture. +Warning 137: bram[0].plr_o[6] unconnected pin in architecture. +Warning 138: bram[0].plr_o[7] unconnected pin in architecture. +Warning 139: bram[0].plr_o[8] unconnected pin in architecture. +Warning 140: bram[0].plr_o[9] unconnected pin in architecture. +Warning 141: bram[0].plr_o[10] unconnected pin in architecture. +Warning 142: bram[0].plr_o[11] unconnected pin in architecture. +Warning 143: bram[0].plr_o[12] unconnected pin in architecture. +Warning 144: bram[0].plr_o[13] unconnected pin in architecture. +Warning 145: bram[0].plr_o[14] unconnected pin in architecture. +Warning 146: bram[0].plr_o[15] unconnected pin in architecture. +Warning 147: bram[0].plr_o[16] unconnected pin in architecture. +Warning 148: bram[0].plr_o[17] unconnected pin in architecture. +Warning 149: bram[0].plr_o[18] unconnected pin in architecture. +Warning 150: bram[0].plr_o[19] unconnected pin in architecture. +Warning 151: bram[0].plr_o[20] unconnected pin in architecture. +Warning 152: bram[0].plr_o[21] unconnected pin in architecture. +Warning 153: bram[0].plr_o[22] unconnected pin in architecture. +Warning 154: bram[0].plr_o[23] unconnected pin in architecture. +Warning 155: bram[0].plr_o[24] unconnected pin in architecture. +Warning 156: bram[0].plr_o[25] unconnected pin in architecture. +Warning 157: bram[0].plr_o[26] unconnected pin in architecture. +Warning 158: bram[0].plr_o[27] unconnected pin in architecture. +Warning 159: bram[0].plr_o[28] unconnected pin in architecture. +Warning 160: bram[0].plr_o[29] unconnected pin in architecture. +Warning 161: bram[0].plr_o[30] unconnected pin in architecture. +Warning 162: bram[0].plr_o[31] unconnected pin in architecture. +Warning 163: bram[0].plr_o[32] unconnected pin in architecture. +Warning 164: bram[0].plr_o[33] unconnected pin in architecture. +Warning 165: bram[0].plr_o[34] unconnected pin in architecture. +Warning 166: bram[0].plr_o[35] unconnected pin in architecture. +# Building complex block graph took 0.04 seconds (max_rss 18.2 MiB, delta_rss +1.0 MiB) +Circuit file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif +# Load circuit +Found constant-zero generator '$false' +Found constant-one generator '$true' +Found constant-zero generator '$undef' +# Load circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.5 MiB) +# Clean circuit +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 13 additional primitive pins as constant generators due to constant inputs +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 0 additional primitive pins as constant generators due to constant inputs +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 0 additional primitive pins as constant generators due to constant inputs +Swept input(s) : 0 +Swept output(s) : 0 (0 dangling, 0 constant) +Swept net(s) : 2 +Swept block(s) : 2 +Constant Pins Marked: 13 +# Clean circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +# Compress circuit +# Compress circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +# Verify circuit +# Verify circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +Circuit Statistics: + Blocks: 69 + .input : 13 + .output: 24 + 0-LUT : 1 + 6-LUT : 30 + dffre : 1 + Nets : 45 + Avg Fanout: 1.3 + Max Fanout: 15.0 + Min Fanout: 1.0 + Netlist Clocks: 1 +# Build Timing Graph + Timing Graph Nodes: 104 + Timing Graph Edges: 94 + Timing Graph Levels: 6 +# Build Timing Graph took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +Netlist contains 1 clocks + Netlist Clock '$clk_buf_$ibuf_CLK_IN' Fanout: 1 pins (1.0%), 1 blocks (1.4%) +# Load Timing Constraints + +SDC file '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc' contained no SDC commands +Setting default timing constraints: + * constrain all primay inputs and primary outputs on netlist clock '$clk_buf_$ibuf_CLK_IN' + * optimize netlist clock to run as fast as possible +Timing constraints created 1 clocks + Constrained Clock '$clk_buf_$ibuf_CLK_IN' Source: '$clk_buf_$ibuf_CLK_IN.inpad[0]' + +# Load Timing Constraints took 0.00 seconds (max_rss 19.0 MiB, delta_rss +0.3 MiB) +# Load packing +Begin loading packed FPGA netlist file. +Netlist generated from file '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net'. +Detected 1 constant generators (to see names run with higher pack verbosity) +Finished loading packed FPGA netlist file (took 0.04 seconds). +# Load packing took 0.05 seconds (max_rss 57.9 MiB, delta_rss +38.7 MiB) +Warning 167: Netlist contains 0 global net to non-global architecture pin connections + +Pb types usage... + io : 37 + io_output : 24 + outpad : 24 + io_input : 13 + inpad : 13 + clb : 2 + clb_lr : 2 + fle : 16 + ble5 : 31 + lut5 : 31 + lut : 31 + ff : 1 + DFFRE : 1 + +# Create Device +## Build Device Grid +FPGA sized to 64 x 46: 2944 grid tiles (castor62x44_heterogeneous) + +Resource usage... + Netlist + 37 blocks of type: io + Architecture + 4320 blocks of type: io_top + 3168 blocks of type: io_right + 4320 blocks of type: io_bottom + 3168 blocks of type: io_left + Netlist + 2 blocks of type: clb + Architecture + 2184 blocks of type: clb + Netlist + 0 blocks of type: dsp + Architecture + 56 blocks of type: dsp + Netlist + 0 blocks of type: bram + Architecture + 56 blocks of type: bram + +Device Utilization: 0.00 (target 1.00) + Physical Tile io_top: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_right: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_bottom: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_left: + Block Utilization: 0.01 Logical Block: io + Physical Tile clb: + Block Utilization: 0.00 Logical Block: clb + Physical Tile dsp: + Block Utilization: 0.00 Logical Block: dsp + Physical Tile bram: + Block Utilization: 0.00 Logical Block: bram + +## Build Device Grid took 0.00 seconds (max_rss 58.2 MiB, delta_rss +0.0 MiB) +Warning 168: Tileable routing resource graph does not support clock modeling yet! Related options are ignored... +## Build tileable routing resource graph +X-direction routing channel width is 160 +Y-direction routing channel width is 160 +Warning 169: Sized nonsensical R=0 transistor to minimum width +Warning 170: Sized nonsensical R=0 transistor to minimum width +Warning 171: Sized nonsensical R=0 transistor to minimum width +Warning 172: Sized nonsensical R=0 transistor to minimum width +## Build tileable routing resource graph took 13.46 seconds (max_rss 472.8 MiB, delta_rss +414.6 MiB) + RR Graph Nodes: 1365608 + RR Graph Edges: 6033268 +# Create Device took 14.07 seconds (max_rss 472.8 MiB, delta_rss +414.6 MiB) + +# Computing router lookahead map +## Computing wire lookahead +## Computing wire lookahead took 29.35 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +## Computing src/opin lookahead +Warning 173: Found no more ample locations for SOURCE in io_top +Warning 174: Found no more ample locations for OPIN in io_top +Warning 175: Found no more ample locations for SOURCE in io_right +Warning 176: Found no more ample locations for OPIN in io_right +Warning 177: Found no more ample locations for SOURCE in io_bottom +Warning 178: Found no more ample locations for OPIN in io_bottom +Warning 179: Found no more ample locations for SOURCE in io_left +Warning 180: Found no more ample locations for OPIN in io_left +Warning 181: Found no more ample locations for SOURCE in clb +Warning 182: Found no more ample locations for OPIN in clb +Warning 183: Found no more ample locations for SOURCE in dsp +Warning 184: Found no more ample locations for OPIN in dsp +Warning 185: Found no more ample locations for SOURCE in bram +Warning 186: Found no more ample locations for OPIN in bram +## Computing src/opin lookahead took 0.10 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +# Computing router lookahead map took 29.56 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +# Computing placement delta delay look-up +RR graph channel widths unchanged, skipping RR graph rebuild +## Computing delta delays +Warning 187: Unable to route between blocks at (1,1) and (1,45) to characterize delay (setting to inf) +Warning 188: Unable to route between blocks at (1,1) and (2,45) to characterize delay (setting to inf) +Warning 189: Unable to route between blocks at (1,1) and (3,45) to characterize delay (setting to inf) +Warning 190: Unable to route between blocks at (1,1) and (4,45) to characterize delay (setting to inf) +Warning 191: Unable to route between blocks at (1,1) and (5,45) to characterize delay (setting to inf) +Warning 192: Unable to route between blocks at (1,1) and (6,45) to characterize delay (setting to inf) +Warning 193: Unable to route between blocks at (1,1) and (7,45) to characterize delay (setting to inf) +Warning 194: Unable to route between blocks at (1,1) and (8,45) to characterize delay (setting to inf) +Warning 195: Unable to route between blocks at (1,1) and (9,45) to characterize delay (setting to inf) +Warning 196: Unable to route between blocks at (1,1) and (10,45) to characterize delay (setting to inf) +Warning 197: Unable to route between blocks at (1,1) and (11,45) to characterize delay (setting to inf) +Warning 198: Unable to route between blocks at (1,1) and (12,45) to characterize delay (setting to inf) +Warning 199: Unable to route between blocks at (1,1) and (13,45) to characterize delay (setting to inf) +Warning 200: Unable to route between blocks at (1,1) and (14,45) to characterize delay (setting to inf) +Warning 201: Unable to route between blocks at (1,1) and (15,45) to characterize delay (setting to inf) +Warning 202: Unable to route between blocks at (1,1) and (16,45) to characterize delay (setting to inf) +Warning 203: Unable to route between blocks at (1,1) and (17,45) to characterize delay (setting to inf) +Warning 204: Unable to route between blocks at (1,1) and (18,45) to characterize delay (setting to inf) +Warning 205: Unable to route between blocks at (1,1) and (19,45) to characterize delay (setting to inf) +Warning 206: Unable to route between blocks at (1,1) and (20,45) to characterize delay (setting to inf) +Warning 207: Unable to route between blocks at (1,1) and (21,45) to characterize delay (setting to inf) +Warning 208: Unable to route between blocks at (1,1) and (22,45) to characterize delay (setting to inf) +Warning 209: Unable to route between blocks at (1,1) and (23,45) to characterize delay (setting to inf) +Warning 210: Unable to route between blocks at (1,1) and (24,45) to characterize delay (setting to inf) +Warning 211: Unable to route between blocks at (1,1) and (25,45) to characterize delay (setting to inf) +Warning 212: Unable to route between blocks at (1,1) and (26,45) to characterize delay (setting to inf) +Warning 213: Unable to route between blocks at (1,1) and (27,45) to characterize delay (setting to inf) +Warning 214: Unable to route between blocks at (1,1) and (28,45) to characterize delay (setting to inf) +Warning 215: Unable to route between blocks at (1,1) and (29,45) to characterize delay (setting to inf) +Warning 216: Unable to route between blocks at (1,1) and (30,45) to characterize delay (setting to inf) +Warning 217: Unable to route between blocks at (1,1) and (31,45) to characterize delay (setting to inf) +Warning 218: Unable to route between blocks at (1,1) and (32,45) to characterize delay (setting to inf) +Warning 219: Unable to route between blocks at (1,1) and (33,45) to characterize delay (setting to inf) +Warning 220: Unable to route between blocks at (1,1) and (34,45) to characterize delay (setting to inf) +Warning 221: Unable to route between blocks at (1,1) and (35,45) to characterize delay (setting to inf) +Warning 222: Unable to route between blocks at (1,1) and (36,45) to characterize delay (setting to inf) +Warning 223: Unable to route between blocks at (1,1) and (37,45) to characterize delay (setting to inf) +Warning 224: Unable to route between blocks at (1,1) and (38,45) to characterize delay (setting to inf) +Warning 225: Unable to route between blocks at (1,1) and (39,45) to characterize delay (setting to inf) +Warning 226: Unable to route between blocks at (1,1) and (40,45) to characterize delay (setting to inf) +Warning 227: Unable to route between blocks at (1,1) and (41,45) to characterize delay (setting to inf) +Warning 228: Unable to route between blocks at (1,1) and (42,45) to characterize delay (setting to inf) +Warning 229: Unable to route between blocks at (1,1) and (43,45) to characterize delay (setting to inf) +Warning 230: Unable to route between blocks at (1,1) and (44,45) to characterize delay (setting to inf) +Warning 231: Unable to route between blocks at (1,1) and (45,45) to characterize delay (setting to inf) +Warning 232: Unable to route between blocks at (1,1) and (46,45) to characterize delay (setting to inf) +Warning 233: Unable to route between blocks at (1,1) and (47,45) to characterize delay (setting to inf) +Warning 234: Unable to route between blocks at (1,1) and (48,45) to characterize delay (setting to inf) +Warning 235: Unable to route between blocks at (1,1) and (49,45) to characterize delay (setting to inf) +Warning 236: Unable to route between blocks at (1,1) and (50,45) to characterize delay (setting to inf) +Warning 237: Unable to route between blocks at (1,1) and (51,45) to characterize delay (setting to inf) +Warning 238: Unable to route between blocks at (1,1) and (52,45) to characterize delay (setting to inf) +Warning 239: Unable to route between blocks at (1,1) and (53,45) to characterize delay (setting to inf) +Warning 240: Unable to route between blocks at (1,1) and (54,45) to characterize delay (setting to inf) +Warning 241: Unable to route between blocks at (1,1) and (55,45) to characterize delay (setting to inf) +Warning 242: Unable to route between blocks at (1,1) and (56,45) to characterize delay (setting to inf) +Warning 243: Unable to route between blocks at (1,1) and (57,45) to characterize delay (setting to inf) +Warning 244: Unable to route between blocks at (1,1) and (58,45) to characterize delay (setting to inf) +Warning 245: Unable to route between blocks at (1,1) and (59,45) to characterize delay (setting to inf) +Warning 246: Unable to route between blocks at (1,1) and (60,45) to characterize delay (setting to inf) +Warning 247: Unable to route between blocks at (1,1) and (61,45) to characterize delay (setting to inf) +Warning 248: Unable to route between blocks at (1,1) and (62,45) to characterize delay (setting to inf) +Warning 249: Unable to route between blocks at (1,1) and (63,1) to characterize delay (setting to inf) +Warning 250: Unable to route between blocks at (1,1) and (63,2) to characterize delay (setting to inf) +Warning 251: Unable to route between blocks at (1,1) and (63,3) to characterize delay (setting to inf) +Warning 252: Unable to route between blocks at (1,1) and (63,4) to characterize delay (setting to inf) +Warning 253: Unable to route between blocks at (1,1) and (63,5) to characterize delay (setting to inf) +Warning 254: Unable to route between blocks at (1,1) and (63,6) to characterize delay (setting to inf) +Warning 255: Unable to route between blocks at (1,1) and (63,7) to characterize delay (setting to inf) +Warning 256: Unable to route between blocks at (1,1) and (63,8) to characterize delay (setting to inf) +Warning 257: Unable to route between blocks at (1,1) and (63,9) to characterize delay (setting to inf) +Warning 258: Unable to route between blocks at (1,1) and (63,10) to characterize delay (setting to inf) +Warning 259: Unable to route between blocks at (1,1) and (63,11) to characterize delay (setting to inf) +Warning 260: Unable to route between blocks at (1,1) and (63,12) to characterize delay (setting to inf) +Warning 261: Unable to route between blocks at (1,1) and (63,13) to characterize delay (setting to inf) +Warning 262: Unable to route between blocks at (1,1) and (63,14) to characterize delay (setting to inf) +Warning 263: Unable to route between blocks at (1,1) and (63,15) to characterize delay (setting to inf) +Warning 264: Unable to route between blocks at (1,1) and (63,16) to characterize delay (setting to inf) +Warning 265: Unable to route between blocks at (1,1) and (63,17) to characterize delay (setting to inf) +Warning 266: Unable to route between blocks at (1,1) and (63,18) to characterize delay (setting to inf) +Warning 267: Unable to route between blocks at (1,1) and (63,19) to characterize delay (setting to inf) +Warning 268: Unable to route between blocks at (1,1) and (63,20) to characterize delay (setting to inf) +Warning 269: Unable to route between blocks at (1,1) and (63,21) to characterize delay (setting to inf) +Warning 270: Unable to route between blocks at (1,1) and (63,22) to characterize delay (setting to inf) +Warning 271: Unable to route between blocks at (1,1) and (63,23) to characterize delay (setting to inf) +Warning 272: Unable to route between blocks at (1,1) and (63,24) to characterize delay (setting to inf) +Warning 273: Unable to route between blocks at (1,1) and (63,25) to characterize delay (setting to inf) +Warning 274: Unable to route between blocks at (1,1) and (63,26) to characterize delay (setting to inf) +Warning 275: Unable to route between blocks at (1,1) and (63,27) to characterize delay (setting to inf) +Warning 276: Unable to route between blocks at (1,1) and (63,28) to characterize delay (setting to inf) +Warning 277: Unable to route between blocks at (1,1) and (63,29) to characterize delay (setting to inf) +Warning 278: Unable to route between blocks at (1,1) and (63,30) to characterize delay (setting to inf) +Warning 279: Unable to route between blocks at (1,1) and (63,31) to characterize delay (setting to inf) +Warning 280: Unable to route between blocks at (1,1) and (63,32) to characterize delay (setting to inf) +Warning 281: Unable to route between blocks at (1,1) and (63,33) to characterize delay (setting to inf) +Warning 282: Unable to route between blocks at (1,1) and (63,34) to characterize delay (setting to inf) +Warning 283: Unable to route between blocks at (1,1) and (63,35) to characterize delay (setting to inf) +Warning 284: Unable to route between blocks at (1,1) and (63,36) to characterize delay (setting to inf) +Warning 285: Unable to route between blocks at (1,1) and (63,37) to characterize delay (setting to inf) +Warning 286: Unable to route between blocks at (1,1) and (63,38) to characterize delay (setting to inf) +Warning 287: Unable to route between blocks at (1,1) and (63,39) to characterize delay (setting to inf) +Warning 288: Unable to route between blocks at (1,1) and (63,40) to characterize delay (setting to inf) +Warning 289: Unable to route between blocks at (1,1) and (63,41) to characterize delay (setting to inf) +Warning 290: Unable to route between blocks at (1,1) and (63,42) to characterize delay (setting to inf) +Warning 291: Unable to route between blocks at (1,1) and (63,43) to characterize delay (setting to inf) +Warning 292: Unable to route between blocks at (1,1) and (63,44) to characterize delay (setting to inf) +Warning 293: Unable to route between blocks at (1,1) and (63,45) to characterize delay (setting to inf) +Warning 294: Unable to route between blocks at (4,4) and (4,45) to characterize delay (setting to inf) +Warning 295: Unable to route between blocks at (4,4) and (5,45) to characterize delay (setting to inf) +Warning 296: Unable to route between blocks at (4,4) and (6,45) to characterize delay (setting to inf) +Warning 297: Unable to route between blocks at (4,4) and (7,45) to characterize delay (setting to inf) +Warning 298: Unable to route between blocks at (4,4) and (8,45) to characterize delay (setting to inf) +Warning 299: Unable to route between blocks at (4,4) and (9,45) to characterize delay (setting to inf) +Warning 300: Unable to route between blocks at (4,4) and (10,45) to characterize delay (setting to inf) +Warning 301: Unable to route between blocks at (4,4) and (11,45) to characterize delay (setting to inf) +Warning 302: Unable to route between blocks at (4,4) and (12,45) to characterize delay (setting to inf) +Warning 303: Unable to route between blocks at (4,4) and (13,45) to characterize delay (setting to inf) +Warning 304: Unable to route between blocks at (4,4) and (14,45) to characterize delay (setting to inf) +Warning 305: Unable to route between blocks at (4,4) and (15,45) to characterize delay (setting to inf) +Warning 306: Unable to route between blocks at (4,4) and (16,45) to characterize delay (setting to inf) +Warning 307: Unable to route between blocks at (4,4) and (17,45) to characterize delay (setting to inf) +Warning 308: Unable to route between blocks at (4,4) and (18,45) to characterize delay (setting to inf) +Warning 309: Unable to route between blocks at (4,4) and (19,45) to characterize delay (setting to inf) +Warning 310: Unable to route between blocks at (4,4) and (20,45) to characterize delay (setting to inf) +Warning 311: Unable to route between blocks at (4,4) and (21,45) to characterize delay (setting to inf) +Warning 312: Unable to route between blocks at (4,4) and (22,45) to characterize delay (setting to inf) +Warning 313: Unable to route between blocks at (4,4) and (23,45) to characterize delay (setting to inf) +Warning 314: Unable to route between blocks at (4,4) and (24,45) to characterize delay (setting to inf) +Warning 315: Unable to route between blocks at (4,4) and (25,45) to characterize delay (setting to inf) +Warning 316: Unable to route between blocks at (4,4) and (26,45) to characterize delay (setting to inf) +Warning 317: Unable to route between blocks at (4,4) and (27,45) to characterize delay (setting to inf) +Warning 318: Unable to route between blocks at (4,4) and (28,45) to characterize delay (setting to inf) +Warning 319: Unable to route between blocks at (4,4) and (29,45) to characterize delay (setting to inf) +Warning 320: Unable to route between blocks at (4,4) and (30,45) to characterize delay (setting to inf) +Warning 321: Unable to route between blocks at (4,4) and (31,45) to characterize delay (setting to inf) +Warning 322: Unable to route between blocks at (4,4) and (32,45) to characterize delay (setting to inf) +Warning 323: Unable to route between blocks at (4,4) and (33,45) to characterize delay (setting to inf) +Warning 324: Unable to route between blocks at (4,4) and (34,45) to characterize delay (setting to inf) +Warning 325: Unable to route between blocks at (4,4) and (35,45) to characterize delay (setting to inf) +Warning 326: Unable to route between blocks at (4,4) and (36,45) to characterize delay (setting to inf) +Warning 327: Unable to route between blocks at (4,4) and (37,45) to characterize delay (setting to inf) +Warning 328: Unable to route between blocks at (4,4) and (38,45) to characterize delay (setting to inf) +Warning 329: Unable to route between blocks at (4,4) and (39,45) to characterize delay (setting to inf) +Warning 330: Unable to route between blocks at (4,4) and (40,45) to characterize delay (setting to inf) +Warning 331: Unable to route between blocks at (4,4) and (41,45) to characterize delay (setting to inf) +Warning 332: Unable to route between blocks at (4,4) and (42,45) to characterize delay (setting to inf) +Warning 333: Unable to route between blocks at (4,4) and (43,45) to characterize delay (setting to inf) +Warning 334: Unable to route between blocks at (4,4) and (44,45) to characterize delay (setting to inf) +Warning 335: Unable to route between blocks at (4,4) and (45,45) to characterize delay (setting to inf) +Warning 336: Unable to route between blocks at (4,4) and (46,45) to characterize delay (setting to inf) +Warning 337: Unable to route between blocks at (4,4) and (47,45) to characterize delay (setting to inf) +Warning 338: Unable to route between blocks at (4,4) and (48,45) to characterize delay (setting to inf) +Warning 339: Unable to route between blocks at (4,4) and (49,45) to characterize delay (setting to inf) +Warning 340: Unable to route between blocks at (4,4) and (50,45) to characterize delay (setting to inf) +Warning 341: Unable to route between blocks at (4,4) and (51,45) to characterize delay (setting to inf) +Warning 342: Unable to route between blocks at (4,4) and (52,45) to characterize delay (setting to inf) +Warning 343: Unable to route between blocks at (4,4) and (53,45) to characterize delay (setting to inf) +Warning 344: Unable to route between blocks at (4,4) and (54,45) to characterize delay (setting to inf) +Warning 345: Unable to route between blocks at (4,4) and (55,45) to characterize delay (setting to inf) +Warning 346: Unable to route between blocks at (4,4) and (56,45) to characterize delay (setting to inf) +Warning 347: Unable to route between blocks at (4,4) and (57,45) to characterize delay (setting to inf) +Warning 348: Unable to route between blocks at (4,4) and (58,45) to characterize delay (setting to inf) +Warning 349: Unable to route between blocks at (4,4) and (59,45) to characterize delay (setting to inf) +Warning 350: Unable to route between blocks at (4,4) and (60,45) to characterize delay (setting to inf) +Warning 351: Unable to route between blocks at (4,4) and (61,45) to characterize delay (setting to inf) +Warning 352: Unable to route between blocks at (4,4) and (62,45) to characterize delay (setting to inf) +Warning 353: Unable to route between blocks at (4,4) and (63,4) to characterize delay (setting to inf) +Warning 354: Unable to route between blocks at (4,4) and (63,5) to characterize delay (setting to inf) +Warning 355: Unable to route between blocks at (4,4) and (63,6) to characterize delay (setting to inf) +Warning 356: Unable to route between blocks at (4,4) and (63,7) to characterize delay (setting to inf) +Warning 357: Unable to route between blocks at (4,4) and (63,8) to characterize delay (setting to inf) +Warning 358: Unable to route between blocks at (4,4) and (63,9) to characterize delay (setting to inf) +Warning 359: Unable to route between blocks at (4,4) and (63,10) to characterize delay (setting to inf) +Warning 360: Unable to route between blocks at (4,4) and (63,11) to characterize delay (setting to inf) +Warning 361: Unable to route between blocks at (4,4) and (63,12) to characterize delay (setting to inf) +Warning 362: Unable to route between blocks at (4,4) and (63,13) to characterize delay (setting to inf) +Warning 363: Unable to route between blocks at (4,4) and (63,14) to characterize delay (setting to inf) +Warning 364: Unable to route between blocks at (4,4) and (63,15) to characterize delay (setting to inf) +Warning 365: Unable to route between blocks at (4,4) and (63,16) to characterize delay (setting to inf) +Warning 366: Unable to route between blocks at (4,4) and (63,17) to characterize delay (setting to inf) +Warning 367: Unable to route between blocks at (4,4) and (63,18) to characterize delay (setting to inf) +Warning 368: Unable to route between blocks at (4,4) and (63,19) to characterize delay (setting to inf) +Warning 369: Unable to route between blocks at (4,4) and (63,20) to characterize delay (setting to inf) +Warning 370: Unable to route between blocks at (4,4) and (63,21) to characterize delay (setting to inf) +Warning 371: Unable to route between blocks at (4,4) and (63,22) to characterize delay (setting to inf) +Warning 372: Unable to route between blocks at (4,4) and (63,23) to characterize delay (setting to inf) +Warning 373: Unable to route between blocks at (4,4) and (63,24) to characterize delay (setting to inf) +Warning 374: Unable to route between blocks at (4,4) and (63,25) to characterize delay (setting to inf) +Warning 375: Unable to route between blocks at (4,4) and (63,26) to characterize delay (setting to inf) +Warning 376: Unable to route between blocks at (4,4) and (63,27) to characterize delay (setting to inf) +Warning 377: Unable to route between blocks at (4,4) and (63,28) to characterize delay (setting to inf) +Warning 378: Unable to route between blocks at (4,4) and (63,29) to characterize delay (setting to inf) +Warning 379: Unable to route between blocks at (4,4) and (63,30) to characterize delay (setting to inf) +Warning 380: Unable to route between blocks at (4,4) and (63,31) to characterize delay (setting to inf) +Warning 381: Unable to route between blocks at (4,4) and (63,32) to characterize delay (setting to inf) +Warning 382: Unable to route between blocks at (4,4) and (63,33) to characterize delay (setting to inf) +Warning 383: Unable to route between blocks at (4,4) and (63,34) to characterize delay (setting to inf) +Warning 384: Unable to route between blocks at (4,4) and (63,35) to characterize delay (setting to inf) +Warning 385: Unable to route between blocks at (4,4) and (63,36) to characterize delay (setting to inf) +Warning 386: Unable to route between blocks at (4,4) and (63,37) to characterize delay (setting to inf) +Warning 387: Unable to route between blocks at (4,4) and (63,38) to characterize delay (setting to inf) +Warning 388: Unable to route between blocks at (4,4) and (63,39) to characterize delay (setting to inf) +Warning 389: Unable to route between blocks at (4,4) and (63,40) to characterize delay (setting to inf) +Warning 390: Unable to route between blocks at (4,4) and (63,41) to characterize delay (setting to inf) +Warning 391: Unable to route between blocks at (4,4) and (63,42) to characterize delay (setting to inf) +Warning 392: Unable to route between blocks at (4,4) and (63,43) to characterize delay (setting to inf) +Warning 393: Unable to route between blocks at (4,4) and (63,44) to characterize delay (setting to inf) +Warning 394: Unable to route between blocks at (4,4) and (63,45) to characterize delay (setting to inf) +Warning 395: Unable to route between blocks at (60,42) and (0,0) to characterize delay (setting to inf) +Warning 396: Unable to route between blocks at (60,42) and (0,1) to characterize delay (setting to inf) +Warning 397: Unable to route between blocks at (60,42) and (0,2) to characterize delay (setting to inf) +Warning 398: Unable to route between blocks at (60,42) and (0,3) to characterize delay (setting to inf) +Warning 399: Unable to route between blocks at (60,42) and (0,4) to characterize delay (setting to inf) +Warning 400: Unable to route between blocks at (60,42) and (0,5) to characterize delay (setting to inf) +Warning 401: Unable to route between blocks at (60,42) and (0,6) to characterize delay (setting to inf) +Warning 402: Unable to route between blocks at (60,42) and (0,7) to characterize delay (setting to inf) +Warning 403: Unable to route between blocks at (60,42) and (0,8) to characterize delay (setting to inf) +Warning 404: Unable to route between blocks at (60,42) and (0,9) to characterize delay (setting to inf) +Warning 405: Unable to route between blocks at (60,42) and (0,10) to characterize delay (setting to inf) +Warning 406: Unable to route between blocks at (60,42) and (0,11) to characterize delay (setting to inf) +Warning 407: Unable to route between blocks at (60,42) and (0,12) to characterize delay (setting to inf) +Warning 408: Unable to route between blocks at (60,42) and (0,13) to characterize delay (setting to inf) +Warning 409: Unable to route between blocks at (60,42) and (0,14) to characterize delay (setting to inf) +Warning 410: Unable to route between blocks at (60,42) and (0,15) to characterize delay (setting to inf) +Warning 411: Unable to route between blocks at (60,42) and (0,16) to characterize delay (setting to inf) +Warning 412: Unable to route between blocks at (60,42) and (0,17) to characterize delay (setting to inf) +Warning 413: Unable to route between blocks at (60,42) and (0,18) to characterize delay (setting to inf) +Warning 414: Unable to route between blocks at (60,42) and (0,19) to characterize delay (setting to inf) +Warning 415: Unable to route between blocks at (60,42) and (0,20) to characterize delay (setting to inf) +Warning 416: Unable to route between blocks at (60,42) and (0,21) to characterize delay (setting to inf) +Warning 417: Unable to route between blocks at (60,42) and (0,22) to characterize delay (setting to inf) +Warning 418: Unable to route between blocks at (60,42) and (0,23) to characterize delay (setting to inf) +Warning 419: Unable to route between blocks at (60,42) and (0,24) to characterize delay (setting to inf) +Warning 420: Unable to route between blocks at (60,42) and (0,25) to characterize delay (setting to inf) +Warning 421: Unable to route between blocks at (60,42) and (0,26) to characterize delay (setting to inf) +Warning 422: Unable to route between blocks at (60,42) and (0,27) to characterize delay (setting to inf) +Warning 423: Unable to route between blocks at (60,42) and (0,28) to characterize delay (setting to inf) +Warning 424: Unable to route between blocks at (60,42) and (0,29) to characterize delay (setting to inf) +Warning 425: Unable to route between blocks at (60,42) and (0,30) to characterize delay (setting to inf) +Warning 426: Unable to route between blocks at (60,42) and (0,31) to characterize delay (setting to inf) +Warning 427: Unable to route between blocks at (60,42) and (0,32) to characterize delay (setting to inf) +Warning 428: Unable to route between blocks at (60,42) and (0,33) to characterize delay (setting to inf) +Warning 429: Unable to route between blocks at (60,42) and (0,34) to characterize delay (setting to inf) +Warning 430: Unable to route between blocks at (60,42) and (0,35) to characterize delay (setting to inf) +Warning 431: Unable to route between blocks at (60,42) and (0,36) to characterize delay (setting to inf) +Warning 432: Unable to route between blocks at (60,42) and (0,37) to characterize delay (setting to inf) +Warning 433: Unable to route between blocks at (60,42) and (0,38) to characterize delay (setting to inf) +Warning 434: Unable to route between blocks at (60,42) and (0,39) to characterize delay (setting to inf) +Warning 435: Unable to route between blocks at (60,42) and (0,40) to characterize delay (setting to inf) +Warning 436: Unable to route between blocks at (60,42) and (0,41) to characterize delay (setting to inf) +Warning 437: Unable to route between blocks at (60,42) and (0,42) to characterize delay (setting to inf) +Warning 438: Unable to route between blocks at (60,42) and (1,0) to characterize delay (setting to inf) +Warning 439: Unable to route between blocks at (60,42) and (2,0) to characterize delay (setting to inf) +Warning 440: Unable to route between blocks at (60,42) and (3,0) to characterize delay (setting to inf) +Warning 441: Unable to route between blocks at (60,42) and (4,0) to characterize delay (setting to inf) +Warning 442: Unable to route between blocks at (60,42) and (5,0) to characterize delay (setting to inf) +Warning 443: Unable to route between blocks at (60,42) and (6,0) to characterize delay (setting to inf) +Warning 444: Unable to route between blocks at (60,42) and (7,0) to characterize delay (setting to inf) +Warning 445: Unable to route between blocks at (60,42) and (8,0) to characterize delay (setting to inf) +Warning 446: Unable to route between blocks at (60,42) and (9,0) to characterize delay (setting to inf) +Warning 447: Unable to route between blocks at (60,42) and (10,0) to characterize delay (setting to inf) +Warning 448: Unable to route between blocks at (60,42) and (11,0) to characterize delay (setting to inf) +Warning 449: Unable to route between blocks at (60,42) and (12,0) to characterize delay (setting to inf) +Warning 450: Unable to route between blocks at (60,42) and (13,0) to characterize delay (setting to inf) +Warning 451: Unable to route between blocks at (60,42) and (14,0) to characterize delay (setting to inf) +Warning 452: Unable to route between blocks at (60,42) and (15,0) to characterize delay (setting to inf) +Warning 453: Unable to route between blocks at (60,42) and (16,0) to characterize delay (setting to inf) +Warning 454: Unable to route between blocks at (60,42) and (17,0) to characterize delay (setting to inf) +Warning 455: Unable to route between blocks at (60,42) and (18,0) to characterize delay (setting to inf) +Warning 456: Unable to route between blocks at (60,42) and (19,0) to characterize delay (setting to inf) +Warning 457: Unable to route between blocks at (60,42) and (20,0) to characterize delay (setting to inf) +Warning 458: Unable to route between blocks at (60,42) and (21,0) to characterize delay (setting to inf) +Warning 459: Unable to route between blocks at (60,42) and (22,0) to characterize delay (setting to inf) +Warning 460: Unable to route between blocks at (60,42) and (23,0) to characterize delay (setting to inf) +Warning 461: Unable to route between blocks at (60,42) and (24,0) to characterize delay (setting to inf) +Warning 462: Unable to route between blocks at (60,42) and (25,0) to characterize delay (setting to inf) +Warning 463: Unable to route between blocks at (60,42) and (26,0) to characterize delay (setting to inf) +Warning 464: Unable to route between blocks at (60,42) and (27,0) to characterize delay (setting to inf) +Warning 465: Unable to route between blocks at (60,42) and (28,0) to characterize delay (setting to inf) +Warning 466: Unable to route between blocks at (60,42) and (29,0) to characterize delay (setting to inf) +Warning 467: Unable to route between blocks at (60,42) and (30,0) to characterize delay (setting to inf) +Warning 468: Unable to route between blocks at (60,42) and (31,0) to characterize delay (setting to inf) +Warning 469: Unable to route between blocks at (60,42) and (32,0) to characterize delay (setting to inf) +Warning 470: Unable to route between blocks at (60,42) and (33,0) to characterize delay (setting to inf) +Warning 471: Unable to route between blocks at (60,42) and (34,0) to characterize delay (setting to inf) +Warning 472: Unable to route between blocks at (60,42) and (35,0) to characterize delay (setting to inf) +Warning 473: Unable to route between blocks at (60,42) and (36,0) to characterize delay (setting to inf) +Warning 474: Unable to route between blocks at (60,42) and (37,0) to characterize delay (setting to inf) +Warning 475: Unable to route between blocks at (60,42) and (38,0) to characterize delay (setting to inf) +Warning 476: Unable to route between blocks at (60,42) and (39,0) to characterize delay (setting to inf) +Warning 477: Unable to route between blocks at (60,42) and (40,0) to characterize delay (setting to inf) +Warning 478: Unable to route between blocks at (60,42) and (41,0) to characterize delay (setting to inf) +Warning 479: Unable to route between blocks at (60,42) and (42,0) to characterize delay (setting to inf) +Warning 480: Unable to route between blocks at (60,42) and (43,0) to characterize delay (setting to inf) +Warning 481: Unable to route between blocks at (60,42) and (44,0) to characterize delay (setting to inf) +Warning 482: Unable to route between blocks at (60,42) and (45,0) to characterize delay (setting to inf) +Warning 483: Unable to route between blocks at (60,42) and (46,0) to characterize delay (setting to inf) +Warning 484: Unable to route between blocks at (60,42) and (47,0) to characterize delay (setting to inf) +Warning 485: Unable to route between blocks at (60,42) and (48,0) to characterize delay (setting to inf) +Warning 486: Unable to route between blocks at (60,42) and (49,0) to characterize delay (setting to inf) +Warning 487: Unable to route between blocks at (60,42) and (50,0) to characterize delay (setting to inf) +Warning 488: Unable to route between blocks at (60,42) and (51,0) to characterize delay (setting to inf) +Warning 489: Unable to route between blocks at (60,42) and (52,0) to characterize delay (setting to inf) +Warning 490: Unable to route between blocks at (60,42) and (53,0) to characterize delay (setting to inf) +Warning 491: Unable to route between blocks at (60,42) and (54,0) to characterize delay (setting to inf) +Warning 492: Unable to route between blocks at (60,42) and (55,0) to characterize delay (setting to inf) +Warning 493: Unable to route between blocks at (60,42) and (56,0) to characterize delay (setting to inf) +Warning 494: Unable to route between blocks at (60,42) and (57,0) to characterize delay (setting to inf) +Warning 495: Unable to route between blocks at (60,42) and (58,0) to characterize delay (setting to inf) +Warning 496: Unable to route between blocks at (60,42) and (59,0) to characterize delay (setting to inf) +Warning 497: Unable to route between blocks at (60,42) and (60,0) to characterize delay (setting to inf) +Warning 498: Unable to route between blocks at (60,4) and (0,4) to characterize delay (setting to inf) +Warning 499: Unable to route between blocks at (60,4) and (0,5) to characterize delay (setting to inf) +Warning 500: Unable to route between blocks at (60,4) and (0,6) to characterize delay (setting to inf) +Warning 501: Unable to route between blocks at (60,4) and (0,7) to characterize delay (setting to inf) +Warning 502: Unable to route between blocks at (60,4) and (0,8) to characterize delay (setting to inf) +Warning 503: Unable to route between blocks at (60,4) and (0,9) to characterize delay (setting to inf) +Warning 504: Unable to route between blocks at (60,4) and (0,10) to characterize delay (setting to inf) +Warning 505: Unable to route between blocks at (60,4) and (0,11) to characterize delay (setting to inf) +Warning 506: Unable to route between blocks at (60,4) and (0,12) to characterize delay (setting to inf) +Warning 507: Unable to route between blocks at (60,4) and (0,13) to characterize delay (setting to inf) +Warning 508: Unable to route between blocks at (60,4) and (0,14) to characterize delay (setting to inf) +Warning 509: Unable to route between blocks at (60,4) and (0,15) to characterize delay (setting to inf) +Warning 510: Unable to route between blocks at (60,4) and (0,16) to characterize delay (setting to inf) +Warning 511: Unable to route between blocks at (60,4) and (0,17) to characterize delay (setting to inf) +Warning 512: Unable to route between blocks at (60,4) and (0,18) to characterize delay (setting to inf) +Warning 513: Unable to route between blocks at (60,4) and (0,19) to characterize delay (setting to inf) +Warning 514: Unable to route between blocks at (60,4) and (0,20) to characterize delay (setting to inf) +Warning 515: Unable to route between blocks at (60,4) and (0,21) to characterize delay (setting to inf) +Warning 516: Unable to route between blocks at (60,4) and (0,22) to characterize delay (setting to inf) +Warning 517: Unable to route between blocks at (60,4) and (0,23) to characterize delay (setting to inf) +Warning 518: Unable to route between blocks at (60,4) and (0,24) to characterize delay (setting to inf) +Warning 519: Unable to route between blocks at (60,4) and (0,25) to characterize delay (setting to inf) +Warning 520: Unable to route between blocks at (60,4) and (0,26) to characterize delay (setting to inf) +Warning 521: Unable to route between blocks at (60,4) and (0,27) to characterize delay (setting to inf) +Warning 522: Unable to route between blocks at (60,4) and (0,28) to characterize delay (setting to inf) +Warning 523: Unable to route between blocks at (60,4) and (0,29) to characterize delay (setting to inf) +Warning 524: Unable to route between blocks at (60,4) and (0,30) to characterize delay (setting to inf) +Warning 525: Unable to route between blocks at (60,4) and (0,31) to characterize delay (setting to inf) +Warning 526: Unable to route between blocks at (60,4) and (0,32) to characterize delay (setting to inf) +Warning 527: Unable to route between blocks at (60,4) and (0,33) to characterize delay (setting to inf) +Warning 528: Unable to route between blocks at (60,4) and (0,34) to characterize delay (setting to inf) +Warning 529: Unable to route between blocks at (60,4) and (0,35) to characterize delay (setting to inf) +Warning 530: Unable to route between blocks at (60,4) and (0,36) to characterize delay (setting to inf) +Warning 531: Unable to route between blocks at (60,4) and (0,37) to characterize delay (setting to inf) +Warning 532: Unable to route between blocks at (60,4) and (0,38) to characterize delay (setting to inf) +Warning 533: Unable to route between blocks at (60,4) and (0,39) to characterize delay (setting to inf) +Warning 534: Unable to route between blocks at (60,4) and (0,40) to characterize delay (setting to inf) +Warning 535: Unable to route between blocks at (60,4) and (0,41) to characterize delay (setting to inf) +Warning 536: Unable to route between blocks at (60,4) and (0,42) to characterize delay (setting to inf) +Warning 537: Unable to route between blocks at (60,4) and (0,43) to characterize delay (setting to inf) +Warning 538: Unable to route between blocks at (60,4) and (0,44) to characterize delay (setting to inf) +Warning 539: Unable to route between blocks at (60,4) and (0,45) to characterize delay (setting to inf) +Warning 540: Unable to route between blocks at (60,4) and (1,45) to characterize delay (setting to inf) +Warning 541: Unable to route between blocks at (60,4) and (2,45) to characterize delay (setting to inf) +Warning 542: Unable to route between blocks at (60,4) and (3,45) to characterize delay (setting to inf) +Warning 543: Unable to route between blocks at (60,4) and (4,45) to characterize delay (setting to inf) +Warning 544: Unable to route between blocks at (60,4) and (5,45) to characterize delay (setting to inf) +Warning 545: Unable to route between blocks at (60,4) and (6,45) to characterize delay (setting to inf) +Warning 546: Unable to route between blocks at (60,4) and (7,45) to characterize delay (setting to inf) +Warning 547: Unable to route between blocks at (60,4) and (8,45) to characterize delay (setting to inf) +Warning 548: Unable to route between blocks at (60,4) and (9,45) to characterize delay (setting to inf) +Warning 549: Unable to route between blocks at (60,4) and (10,45) to characterize delay (setting to inf) +Warning 550: Unable to route between blocks at (60,4) and (11,45) to characterize delay (setting to inf) +Warning 551: Unable to route between blocks at (60,4) and (12,45) to characterize delay (setting to inf) +Warning 552: Unable to route between blocks at (60,4) and (13,45) to characterize delay (setting to inf) +Warning 553: Unable to route between blocks at (60,4) and (14,45) to characterize delay (setting to inf) +Warning 554: Unable to route between blocks at (60,4) and (15,45) to characterize delay (setting to inf) +Warning 555: Unable to route between blocks at (60,4) and (16,45) to characterize delay (setting to inf) +Warning 556: Unable to route between blocks at (60,4) and (17,45) to characterize delay (setting to inf) +Warning 557: Unable to route between blocks at (60,4) and (18,45) to characterize delay (setting to inf) +Warning 558: Unable to route between blocks at (60,4) and (19,45) to characterize delay (setting to inf) +Warning 559: Unable to route between blocks at (60,4) and (20,45) to characterize delay (setting to inf) +Warning 560: Unable to route between blocks at (60,4) and (21,45) to characterize delay (setting to inf) +Warning 561: Unable to route between blocks at (60,4) and (22,45) to characterize delay (setting to inf) +Warning 562: Unable to route between blocks at (60,4) and (23,45) to characterize delay (setting to inf) +Warning 563: Unable to route between blocks at (60,4) and (24,45) to characterize delay (setting to inf) +Warning 564: Unable to route between blocks at (60,4) and (25,45) to characterize delay (setting to inf) +Warning 565: Unable to route between blocks at (60,4) and (26,45) to characterize delay (setting to inf) +Warning 566: Unable to route between blocks at (60,4) and (27,45) to characterize delay (setting to inf) +Warning 567: Unable to route between blocks at (60,4) and (28,45) to characterize delay (setting to inf) +Warning 568: Unable to route between blocks at (60,4) and (29,45) to characterize delay (setting to inf) +Warning 569: Unable to route between blocks at (60,4) and (30,45) to characterize delay (setting to inf) +Warning 570: Unable to route between blocks at (60,4) and (31,45) to characterize delay (setting to inf) +Warning 571: Unable to route between blocks at (60,4) and (32,45) to characterize delay (setting to inf) +Warning 572: Unable to route between blocks at (60,4) and (33,45) to characterize delay (setting to inf) +Warning 573: Unable to route between blocks at (60,4) and (34,45) to characterize delay (setting to inf) +Warning 574: Unable to route between blocks at (60,4) and (35,45) to characterize delay (setting to inf) +Warning 575: Unable to route between blocks at (60,4) and (36,45) to characterize delay (setting to inf) +Warning 576: Unable to route between blocks at (60,4) and (37,45) to characterize delay (setting to inf) +Warning 577: Unable to route between blocks at (60,4) and (38,45) to characterize delay (setting to inf) +Warning 578: Unable to route between blocks at (60,4) and (39,45) to characterize delay (setting to inf) +Warning 579: Unable to route between blocks at (60,4) and (40,45) to characterize delay (setting to inf) +Warning 580: Unable to route between blocks at (60,4) and (41,45) to characterize delay (setting to inf) +Warning 581: Unable to route between blocks at (60,4) and (42,45) to characterize delay (setting to inf) +Warning 582: Unable to route between blocks at (60,4) and (43,45) to characterize delay (setting to inf) +Warning 583: Unable to route between blocks at (60,4) and (44,45) to characterize delay (setting to inf) +Warning 584: Unable to route between blocks at (60,4) and (45,45) to characterize delay (setting to inf) +Warning 585: Unable to route between blocks at (60,4) and (46,45) to characterize delay (setting to inf) +Warning 586: Unable to route between blocks at (60,4) and (47,45) to characterize delay (setting to inf) +Warning 587: Unable to route between blocks at (60,4) and (48,45) to characterize delay (setting to inf) +Warning 588: Unable to route between blocks at (60,4) and (49,45) to characterize delay (setting to inf) +Warning 589: Unable to route between blocks at (60,4) and (50,45) to characterize delay (setting to inf) +Warning 590: Unable to route between blocks at (60,4) and (51,45) to characterize delay (setting to inf) +Warning 591: Unable to route between blocks at (60,4) and (52,45) to characterize delay (setting to inf) +Warning 592: Unable to route between blocks at (60,4) and (53,45) to characterize delay (setting to inf) +Warning 593: Unable to route between blocks at (60,4) and (54,45) to characterize delay (setting to inf) +Warning 594: Unable to route between blocks at (60,4) and (55,45) to characterize delay (setting to inf) +Warning 595: Unable to route between blocks at (60,4) and (56,45) to characterize delay (setting to inf) +Warning 596: Unable to route between blocks at (60,4) and (57,45) to characterize delay (setting to inf) +Warning 597: Unable to route between blocks at (60,4) and (58,45) to characterize delay (setting to inf) +Warning 598: Unable to route between blocks at (60,4) and (59,45) to characterize delay (setting to inf) +Warning 599: Unable to route between blocks at (60,4) and (60,45) to characterize delay (setting to inf) +Warning 600: Unable to route between blocks at (4,42) and (4,0) to characterize delay (setting to inf) +Warning 601: Unable to route between blocks at (4,42) and (5,0) to characterize delay (setting to inf) +Warning 602: Unable to route between blocks at (4,42) and (6,0) to characterize delay (setting to inf) +Warning 603: Unable to route between blocks at (4,42) and (7,0) to characterize delay (setting to inf) +Warning 604: Unable to route between blocks at (4,42) and (8,0) to characterize delay (setting to inf) +Warning 605: Unable to route between blocks at (4,42) and (9,0) to characterize delay (setting to inf) +Warning 606: Unable to route between blocks at (4,42) and (10,0) to characterize delay (setting to inf) +Warning 607: Unable to route between blocks at (4,42) and (11,0) to characterize delay (setting to inf) +Warning 608: Unable to route between blocks at (4,42) and (12,0) to characterize delay (setting to inf) +Warning 609: Unable to route between blocks at (4,42) and (13,0) to characterize delay (setting to inf) +Warning 610: Unable to route between blocks at (4,42) and (14,0) to characterize delay (setting to inf) +Warning 611: Unable to route between blocks at (4,42) and (15,0) to characterize delay (setting to inf) +Warning 612: Unable to route between blocks at (4,42) and (16,0) to characterize delay (setting to inf) +Warning 613: Unable to route between blocks at (4,42) and (17,0) to characterize delay (setting to inf) +Warning 614: Unable to route between blocks at (4,42) and (18,0) to characterize delay (setting to inf) +Warning 615: Unable to route between blocks at (4,42) and (19,0) to characterize delay (setting to inf) +Warning 616: Unable to route between blocks at (4,42) and (20,0) to characterize delay (setting to inf) +Warning 617: Unable to route between blocks at (4,42) and (21,0) to characterize delay (setting to inf) +Warning 618: Unable to route between blocks at (4,42) and (22,0) to characterize delay (setting to inf) +Warning 619: Unable to route between blocks at (4,42) and (23,0) to characterize delay (setting to inf) +Warning 620: Unable to route between blocks at (4,42) and (24,0) to characterize delay (setting to inf) +Warning 621: Unable to route between blocks at (4,42) and (25,0) to characterize delay (setting to inf) +Warning 622: Unable to route between blocks at (4,42) and (26,0) to characterize delay (setting to inf) +Warning 623: Unable to route between blocks at (4,42) and (27,0) to characterize delay (setting to inf) +Warning 624: Unable to route between blocks at (4,42) and (28,0) to characterize delay (setting to inf) +Warning 625: Unable to route between blocks at (4,42) and (29,0) to characterize delay (setting to inf) +Warning 626: Unable to route between blocks at (4,42) and (30,0) to characterize delay (setting to inf) +Warning 627: Unable to route between blocks at (4,42) and (31,0) to characterize delay (setting to inf) +Warning 628: Unable to route between blocks at (4,42) and (32,0) to characterize delay (setting to inf) +Warning 629: Unable to route between blocks at (4,42) and (33,0) to characterize delay (setting to inf) +Warning 630: Unable to route between blocks at (4,42) and (34,0) to characterize delay (setting to inf) +Warning 631: Unable to route between blocks at (4,42) and (35,0) to characterize delay (setting to inf) +Warning 632: Unable to route between blocks at (4,42) and (36,0) to characterize delay (setting to inf) +Warning 633: Unable to route between blocks at (4,42) and (37,0) to characterize delay (setting to inf) +Warning 634: Unable to route between blocks at (4,42) and (38,0) to characterize delay (setting to inf) +Warning 635: Unable to route between blocks at (4,42) and (39,0) to characterize delay (setting to inf) +Warning 636: Unable to route between blocks at (4,42) and (40,0) to characterize delay (setting to inf) +Warning 637: Unable to route between blocks at (4,42) and (41,0) to characterize delay (setting to inf) +Warning 638: Unable to route between blocks at (4,42) and (42,0) to characterize delay (setting to inf) +Warning 639: Unable to route between blocks at (4,42) and (43,0) to characterize delay (setting to inf) +Warning 640: Unable to route between blocks at (4,42) and (44,0) to characterize delay (setting to inf) +Warning 641: Unable to route between blocks at (4,42) and (45,0) to characterize delay (setting to inf) +Warning 642: Unable to route between blocks at (4,42) and (46,0) to characterize delay (setting to inf) +Warning 643: Unable to route between blocks at (4,42) and (47,0) to characterize delay (setting to inf) +Warning 644: Unable to route between blocks at (4,42) and (48,0) to characterize delay (setting to inf) +Warning 645: Unable to route between blocks at (4,42) and (49,0) to characterize delay (setting to inf) +Warning 646: Unable to route between blocks at (4,42) and (50,0) to characterize delay (setting to inf) +Warning 647: Unable to route between blocks at (4,42) and (51,0) to characterize delay (setting to inf) +Warning 648: Unable to route between blocks at (4,42) and (52,0) to characterize delay (setting to inf) +Warning 649: Unable to route between blocks at (4,42) and (53,0) to characterize delay (setting to inf) +Warning 650: Unable to route between blocks at (4,42) and (54,0) to characterize delay (setting to inf) +Warning 651: Unable to route between blocks at (4,42) and (55,0) to characterize delay (setting to inf) +Warning 652: Unable to route between blocks at (4,42) and (56,0) to characterize delay (setting to inf) +Warning 653: Unable to route between blocks at (4,42) and (57,0) to characterize delay (setting to inf) +Warning 654: Unable to route between blocks at (4,42) and (58,0) to characterize delay (setting to inf) +Warning 655: Unable to route between blocks at (4,42) and (59,0) to characterize delay (setting to inf) +Warning 656: Unable to route between blocks at (4,42) and (60,0) to characterize delay (setting to inf) +Warning 657: Unable to route between blocks at (4,42) and (61,0) to characterize delay (setting to inf) +Warning 658: Unable to route between blocks at (4,42) and (62,0) to characterize delay (setting to inf) +Warning 659: Unable to route between blocks at (4,42) and (63,0) to characterize delay (setting to inf) +Warning 660: Unable to route between blocks at (4,42) and (63,1) to characterize delay (setting to inf) +Warning 661: Unable to route between blocks at (4,42) and (63,2) to characterize delay (setting to inf) +Warning 662: Unable to route between blocks at (4,42) and (63,3) to characterize delay (setting to inf) +Warning 663: Unable to route between blocks at (4,42) and (63,4) to characterize delay (setting to inf) +Warning 664: Unable to route between blocks at (4,42) and (63,5) to characterize delay (setting to inf) +Warning 665: Unable to route between blocks at (4,42) and (63,6) to characterize delay (setting to inf) +Warning 666: Unable to route between blocks at (4,42) and (63,7) to characterize delay (setting to inf) +Warning 667: Unable to route between blocks at (4,42) and (63,8) to characterize delay (setting to inf) +Warning 668: Unable to route between blocks at (4,42) and (63,9) to characterize delay (setting to inf) +Warning 669: Unable to route between blocks at (4,42) and (63,10) to characterize delay (setting to inf) +Warning 670: Unable to route between blocks at (4,42) and (63,11) to characterize delay (setting to inf) +Warning 671: Unable to route between blocks at (4,42) and (63,12) to characterize delay (setting to inf) +Warning 672: Unable to route between blocks at (4,42) and (63,13) to characterize delay (setting to inf) +Warning 673: Unable to route between blocks at (4,42) and (63,14) to characterize delay (setting to inf) +Warning 674: Unable to route between blocks at (4,42) and (63,15) to characterize delay (setting to inf) +Warning 675: Unable to route between blocks at (4,42) and (63,16) to characterize delay (setting to inf) +Warning 676: Unable to route between blocks at (4,42) and (63,17) to characterize delay (setting to inf) +Warning 677: Unable to route between blocks at (4,42) and (63,18) to characterize delay (setting to inf) +Warning 678: Unable to route between blocks at (4,42) and (63,19) to characterize delay (setting to inf) +Warning 679: Unable to route between blocks at (4,42) and (63,20) to characterize delay (setting to inf) +Warning 680: Unable to route between blocks at (4,42) and (63,21) to characterize delay (setting to inf) +Warning 681: Unable to route between blocks at (4,42) and (63,22) to characterize delay (setting to inf) +Warning 682: Unable to route between blocks at (4,42) and (63,23) to characterize delay (setting to inf) +Warning 683: Unable to route between blocks at (4,42) and (63,24) to characterize delay (setting to inf) +Warning 684: Unable to route between blocks at (4,42) and (63,25) to characterize delay (setting to inf) +Warning 685: Unable to route between blocks at (4,42) and (63,26) to characterize delay (setting to inf) +Warning 686: Unable to route between blocks at (4,42) and (63,27) to characterize delay (setting to inf) +Warning 687: Unable to route between blocks at (4,42) and (63,28) to characterize delay (setting to inf) +Warning 688: Unable to route between blocks at (4,42) and (63,29) to characterize delay (setting to inf) +Warning 689: Unable to route between blocks at (4,42) and (63,30) to characterize delay (setting to inf) +Warning 690: Unable to route between blocks at (4,42) and (63,31) to characterize delay (setting to inf) +Warning 691: Unable to route between blocks at (4,42) and (63,32) to characterize delay (setting to inf) +Warning 692: Unable to route between blocks at (4,42) and (63,33) to characterize delay (setting to inf) +Warning 693: Unable to route between blocks at (4,42) and (63,34) to characterize delay (setting to inf) +Warning 694: Unable to route between blocks at (4,42) and (63,35) to characterize delay (setting to inf) +Warning 695: Unable to route between blocks at (4,42) and (63,36) to characterize delay (setting to inf) +Warning 696: Unable to route between blocks at (4,42) and (63,37) to characterize delay (setting to inf) +Warning 697: Unable to route between blocks at (4,42) and (63,38) to characterize delay (setting to inf) +Warning 698: Unable to route between blocks at (4,42) and (63,39) to characterize delay (setting to inf) +Warning 699: Unable to route between blocks at (4,42) and (63,40) to characterize delay (setting to inf) +Warning 700: Unable to route between blocks at (4,42) and (63,41) to characterize delay (setting to inf) +Warning 701: Unable to route between blocks at (4,42) and (63,42) to characterize delay (setting to inf) +## Computing delta delays took 39.55 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +# Computing placement delta delay look-up took 39.58 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) + +Bounding box mode is Cube + +# Placement +## Initial Placement +Reading I_DELAY_primitive_inst_pin_loc.place. + +## Initial Placement took 0.00 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +# Placement took 0.00 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +Error 1: +Type: Placement +File: /nfs_eda_sw/softwares/Raptor/orgnl/Raptor/Backend/OpenFPGA/vtr-verilog-to-routing/vpr/src/base/read_place.cpp +Line: 294 +Message: The location of cluster $obuf_O (#38) is specified 2 times in the constraints file with conflicting locations. +Its location was last specified with block $obuf_O. + +The entire flow of VPR took 83.72 seconds (max_rss 472.8 MiB) diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/rs_planner.log b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/rs_planner.log new file mode 100644 index 00000000..bcc6b32b --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/rs_planner.log @@ -0,0 +1,249 @@ + pln0338 + compiled: Sep 19 2024 10:03:23 + + pin_c +Flags : +Params : + --assign_unconstrained_pins in_define_order + --blif /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif + --clk_map I_DELAY_primitive_inst.temp_file_clkmap + --csv /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/Virgo_Pin_Table.csv + --edits /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/config.json + --output I_DELAY_primitive_inst_pin_loc.place + --read_repack /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/fpga_repack_constraints.xml + --write_repack I_DELAY_primitive_inst_repack_constraints.xml + +******************************** + + +******************************** + + + === pin_c options === + xml_name (--xml) : + csv_name (--csv) : /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/Virgo_Pin_Table.csv + user_pcf_ (--pcf) : + blif_name (--blif) : /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif + json_name (--port_info) : + edits_file (--edits) : /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/config.json + output_name (--output) : I_DELAY_primitive_inst_pin_loc.place + assign_method= in_define_order + +... reading /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif + +____ BEGIN pinc_check_blif: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif + + (blif_file) #inputs= 13 #outputs= 24 topModel= fabric_I_DELAY_primitive_inst + +>>>>> checking BLIF /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif ... + + +===== passed: YES +----- topModel: fabric_I_DELAY_primitive_inst +----- file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif +----- #inputs= 13 +----- #outputs= 24 +----- #LUTs= 1 +----- #LUT1= 0 +----- #LUT5= 0 +----- #LUT6= 0 +----- #FFs= 1 +----- #I_BUFs= 0 +----- #O_BUFs= 0 +----- #CLK_BUFs= 0 +----- #I_SERDES= 0 +----- #DSP19X= 0 +----- #DSP38= 0 +----- PinGraph: +===== passed: YES + +===== BLIF is OK. + + pinc_check_blif STATUS = PASS + +------ END pinc_check_blif: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif + + (blif_file) #inputs= 13 #outputs= 24 topModel= fabric_I_DELAY_primitive_inst + +pin_c: finished read_blif(). #inputs= 13 #outputs= 24 + +DONE read_design_ports() #udes_inputs= 13 #udes_outputs= 24 + + +read_PT_CSV() __ Reading csv + cvs_name= /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/Virgo_Pin_Table.csv +pin_c CsvReader::read_csv( /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/Virgo_Pin_Table.csv ) num_udes_pins= 37 +pin_c CSV: #rows= 5270 #colums= 76 + #RX_cols= 17 #TX_cols= 17 #GPIO_cols= 1 + +initRows: num_rows= 5270 num_cols= 76 start_GBOX_GPIO_row_= 367 + + + *** pin_c read_PT_CSV SUCCEEDED *** + + + has_edits_ : /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/config.json + +translatePinNames() @ (auto-PCF) + +DONE translatePinNames() @ (auto-PCF) + number of translated pins = 7 + + ---- dumping user_design_inputs_ after translation (13) -- + inp-0 CLK_IN + inp-1 DLY_ADJ + inp-2 DLY_INCDEC + inp-3 DLY_LOAD + inp-4 in + inp-5 reset + inp-6 $ifab_$obuf_DLY_TAP_VALUE[0] + inp-7 $ifab_$obuf_DLY_TAP_VALUE[1] + inp-8 $ifab_$obuf_DLY_TAP_VALUE[2] + inp-9 $ifab_$obuf_DLY_TAP_VALUE[3] + inp-10 $ifab_$obuf_DLY_TAP_VALUE[4] + inp-11 $ifab_$obuf_DLY_TAP_VALUE[5] + inp-12 dff + ---- + ---- dumping user_design_outputs_ after translation (24) -- + out-0 $auto_440 + out-1 $auto_441 + out-2 $auto_442 + out-3 $auto_443 + out-4 $auto_444 + out-5 $auto_445 + out-6 $auto_446 + out-7 $auto_447 + out-8 $auto_448 + out-9 $auto_449 + out-10 $auto_450 + out-11 $auto_451 + out-12 $auto_452 + out-13 $auto_453 + out-14 $f2g_trx_dly_adj_$ibuf_DLY_ADJ + out-15 $f2g_trx_dly_inc_$ibuf_DLY_INCDEC + out-16 $f2g_trx_dly_ld_$ibuf_DLY_LOAD + out-17 $f2g_tx_out_$obuf_DLY_TAP_VALUE[0] + out-18 $f2g_tx_out_$obuf_DLY_TAP_VALUE[1] + out-19 $f2g_tx_out_$obuf_DLY_TAP_VALUE[2] + out-20 $f2g_tx_out_$obuf_DLY_TAP_VALUE[3] + out-21 $f2g_tx_out_$obuf_DLY_TAP_VALUE[4] + out-22 $f2g_tx_out_$obuf_DLY_TAP_VALUE[5] + out-23 dff + ---- + + [CRITICAL_WARNING] pin 'dff' is both input and output (after NL-edits). + + +create_temp_pcf() : 128755.temp_pcf.pcf + +--- writing pcf inputs (13) + +--- writing pcf outputs (24) + +pin_c: reading .pcf from 128755.temp_pcf.pcf + +PcfReader::read_pcf_file( 128755.temp_pcf.pcf ) +pin_c PCF: num_pcf_commands= 37 num_internal_pins= 0 + + *** pin_c read_PCF SUCCEEDED *** +translatePinNames() @ (finalize_edits) + +DONE translatePinNames() @ (finalize_edits) + number of translated pins = 7 +PCF command translation: #input translations= 8 #output translations= 0 +total number of translated PCF commands = 8 + +pin_c: writing .place output file: I_DELAY_primitive_inst_pin_loc.place + +written 37 pins to I_DELAY_primitive_inst_pin_loc.place + min_pt_row= 13 max_pt_row= 60 +pin_c: write_clocks_logical_to_physical().. +pin_c: current directory= /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement + +clock mapping: # user-design clocks = 1 # device clocks = 1pin_c: written OK: I_DELAY_primitive_inst_repack_constraints.xml +full path: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_repack_constraints.xml +input was: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/fpga_repack_constraints.xml +pin_c: removed clock-map file: I_DELAY_primitive_inst.temp_file_clkmap +PinPlacer::map_clocks() returns OK + +pin_c done: read_and_write() succeeded. map_clk_status= 1 + +======== pin_c stats: + --> got 13 inputs and 24 outputs + + ---- inputs(13): ---- + I $clk_buf_$ibuf_CLK_IN trans--> $clk_buf_$ibuf_CLK_IN placed at (51 44 _23) device: BOOT_PWM2_GPIO_12 pt_row: 59 Fullchip_N: fpga_pad_c[12] + I $ibuf_DLY_ADJ trans--> $ibuf_DLY_ADJ placed at (51 44 _22) device: BOOT_PWM3_GPIO_13 pt_row: 60 Fullchip_N: fpga_pad_c[13] + I $ibuf_DLY_INCDEC trans--> $ibuf_DLY_INCDEC placed at (51 44 _21) device: BOOT_UART_CTS_GPIO_14 pt_row: 61 Fullchip_N: fpga_pad_c[14] + I $ibuf_DLY_LOAD trans--> $ibuf_DLY_LOAD placed at (51 44 _20) device: BOOT_UART_RTS_GPIO_15 pt_row: 62 Fullchip_N: fpga_pad_c[15] + I $ibuf_in trans--> $ibuf_in placed at (48 44 _23) device: BOOT_CONFIG_DONE_GPIO_0 pt_row: 47 Fullchip_N: fpga_pad_c[0] + I $ibuf_reset trans--> $ibuf_reset placed at (48 44 _22) device: BOOT_CONFIG_ERROR_GPIO_1 pt_row: 48 Fullchip_N: fpga_pad_c[1] + I $ifab_$obuf_DLY_TAP_VALUE[0] trans--> $ifab_$obuf_DLY_TAP_VALUE[0] placed at (48 44 _21) device: BOOT_UART_TX_GPIO_2 pt_row: 49 Fullchip_N: fpga_pad_c[2] + I $ifab_$obuf_DLY_TAP_VALUE[1] trans--> $ifab_$obuf_DLY_TAP_VALUE[1] placed at (48 44 _20) device: BOOT_UART_RX_GPIO_3 pt_row: 50 Fullchip_N: fpga_pad_c[3] + I $ifab_$obuf_DLY_TAP_VALUE[2] trans--> $ifab_$obuf_DLY_TAP_VALUE[2] placed at (48 44 _19) device: BOOT_SPI_CS_GPIO_4 pt_row: 51 Fullchip_N: fpga_pad_c[4] + I $ifab_$obuf_DLY_TAP_VALUE[3] trans--> $ifab_$obuf_DLY_TAP_VALUE[3] placed at (48 44 _18) device: BOOT_SPI_MOSI_DQ0_GPIO_5 pt_row: 52 Fullchip_N: fpga_pad_c[5] + I $ifab_$obuf_DLY_TAP_VALUE[4] trans--> $ifab_$obuf_DLY_TAP_VALUE[4] placed at (48 44 _17) device: BOOT_SPI_MISO_DQ1_GPIO_6 pt_row: 53 Fullchip_N: fpga_pad_c[6] + I $ifab_$obuf_DLY_TAP_VALUE[5] trans--> $ifab_$obuf_DLY_TAP_VALUE[5] placed at (48 44 _16) device: BOOT_SPI_DQ2_GPIO_7 pt_row: 54 Fullchip_N: fpga_pad_c[7] + I $obuf_O trans--> $obuf_O placed at (48 44 _15) device: BOOT_SPI_DQ3_GPIO_8 pt_row: 55 Fullchip_N: fpga_pad_c[8] + + ---- outputs(24): ---- + O $auto_440 trans--> $auto_440 placed at (49 44 _71) device: BOOT_CONFIG_DONE_GPIO_0 pt_row: 15 Fullchip_N: fpga_pad_i[0] CustomerInternal_BU: SOC_GPIO0_O + O $auto_441 trans--> $auto_441 placed at (49 44 _70) device: BOOT_CONFIG_ERROR_GPIO_1 pt_row: 16 Fullchip_N: fpga_pad_i[1] CustomerInternal_BU: SOC_GPIO1_O + O $auto_442 trans--> $auto_442 placed at (49 44 _69) device: BOOT_UART_TX_GPIO_2 pt_row: 17 Fullchip_N: fpga_pad_i[2] CustomerInternal_BU: SOC_GPIO2_O + O $auto_443 trans--> $auto_443 placed at (49 44 _68) device: BOOT_UART_RX_GPIO_3 pt_row: 18 Fullchip_N: fpga_pad_i[3] CustomerInternal_BU: SOC_GPIO3_O + O $auto_444 trans--> $auto_444 placed at (49 44 _67) device: BOOT_SPI_CS_GPIO_4 pt_row: 19 Fullchip_N: fpga_pad_i[4] CustomerInternal_BU: SOC_GPIO4_O + O $auto_445 trans--> $auto_445 placed at (49 44 _66) device: BOOT_SPI_MOSI_DQ0_GPIO_5 pt_row: 20 Fullchip_N: fpga_pad_i[5] CustomerInternal_BU: SOC_GPIO5_O + O $auto_446 trans--> $auto_446 placed at (49 44 _65) device: BOOT_SPI_MISO_DQ1_GPIO_6 pt_row: 21 Fullchip_N: fpga_pad_i[6] CustomerInternal_BU: SOC_GPIO6_O + O $auto_447 trans--> $auto_447 placed at (49 44 _64) device: BOOT_SPI_DQ2_GPIO_7 pt_row: 22 Fullchip_N: fpga_pad_i[7] CustomerInternal_BU: SOC_GPIO7_O + O $auto_448 trans--> $auto_448 placed at (49 44 _63) device: BOOT_SPI_DQ3_GPIO_8 pt_row: 23 Fullchip_N: fpga_pad_i[8] CustomerInternal_BU: SOC_GPIO16_O + O $auto_449 trans--> $auto_449 placed at (49 44 _62) device: BOOT_I2C_SDA_GPIO_9 pt_row: 24 Fullchip_N: fpga_pad_i[9] CustomerInternal_BU: SOC_GPIO17_O + O $auto_450 trans--> $auto_450 placed at (49 44 _61) device: BOOT_PWM0_GPIO_10 pt_row: 25 Fullchip_N: fpga_pad_i[10] CustomerInternal_BU: SOC_GPIO18_O + O $auto_451 trans--> $auto_451 placed at (49 44 _60) device: BOOT_PWM1_GPIO_11 pt_row: 26 Fullchip_N: fpga_pad_i[11] CustomerInternal_BU: SOC_GPIO19_O + O $auto_452 trans--> $auto_452 placed at (49 44 _59) device: BOOT_PWM2_GPIO_12 pt_row: 27 Fullchip_N: fpga_pad_i[12] CustomerInternal_BU: SOC_GPIO20_O + O $auto_453 trans--> $auto_453 placed at (49 44 _58) device: BOOT_PWM3_GPIO_13 pt_row: 28 Fullchip_N: fpga_pad_i[13] CustomerInternal_BU: SOC_GPIO21_O + O $f2g_trx_dly_adj_$ibuf_DLY_ADJ trans--> $f2g_trx_dly_adj_$ibuf_DLY_ADJ placed at (49 44 _57) device: BOOT_UART_CTS_GPIO_14 pt_row: 29 Fullchip_N: fpga_pad_i[14] CustomerInternal_BU: SOC_GPIO22_O + O $f2g_trx_dly_inc_$ibuf_DLY_INCDEC trans--> $f2g_trx_dly_inc_$ibuf_DLY_INCDEC placed at (49 44 _56) device: BOOT_UART_RTS_GPIO_15 pt_row: 30 Fullchip_N: fpga_pad_i[15] CustomerInternal_BU: SOC_GPIO23_O + O $f2g_trx_dly_ld_$ibuf_DLY_LOAD trans--> $f2g_trx_dly_ld_$ibuf_DLY_LOAD placed at (51 44 _71) device: BOOT_CONFIG_DONE_GPIO_0 pt_row: 31 Fullchip_N: fpga_pad_oen[0] CustomerInternal_BU: SOC_GPIO0_O + O $f2g_tx_out_$obuf_DLY_TAP_VALUE[0] trans--> $f2g_tx_out_$obuf_DLY_TAP_VALUE[0] placed at (51 44 _70) device: BOOT_CONFIG_ERROR_GPIO_1 pt_row: 32 Fullchip_N: fpga_pad_oen[1] CustomerInternal_BU: SOC_GPIO1_O + O $f2g_tx_out_$obuf_DLY_TAP_VALUE[1] trans--> $f2g_tx_out_$obuf_DLY_TAP_VALUE[1] placed at (51 44 _69) device: BOOT_UART_TX_GPIO_2 pt_row: 33 Fullchip_N: fpga_pad_oen[2] CustomerInternal_BU: SOC_GPIO2_O + O $f2g_tx_out_$obuf_DLY_TAP_VALUE[2] trans--> $f2g_tx_out_$obuf_DLY_TAP_VALUE[2] placed at (51 44 _68) device: BOOT_UART_RX_GPIO_3 pt_row: 34 Fullchip_N: fpga_pad_oen[3] CustomerInternal_BU: SOC_GPIO3_O + O $f2g_tx_out_$obuf_DLY_TAP_VALUE[3] trans--> $f2g_tx_out_$obuf_DLY_TAP_VALUE[3] placed at (51 44 _67) device: BOOT_SPI_CS_GPIO_4 pt_row: 35 Fullchip_N: fpga_pad_oen[4] CustomerInternal_BU: SOC_GPIO4_O + O $f2g_tx_out_$obuf_DLY_TAP_VALUE[4] trans--> $f2g_tx_out_$obuf_DLY_TAP_VALUE[4] placed at (51 44 _66) device: BOOT_SPI_MOSI_DQ0_GPIO_5 pt_row: 36 Fullchip_N: fpga_pad_oen[5] CustomerInternal_BU: SOC_GPIO5_O + O $f2g_tx_out_$obuf_DLY_TAP_VALUE[5] trans--> $f2g_tx_out_$obuf_DLY_TAP_VALUE[5] placed at (51 44 _65) device: BOOT_SPI_MISO_DQ1_GPIO_6 pt_row: 37 Fullchip_N: fpga_pad_oen[6] CustomerInternal_BU: SOC_GPIO6_O + O dff trans--> dff + + <----- pin_c got 13 inputs and 24 outputs + <-- pin_c placed 14 inputs and 23 outputs + min_pt_row= 15 max_pt_row= 62 + +ROW-RECORD stats ( numRows= 5270 ) + No_dir : 710 + Input_dir : 1992 + Output_dir : 1320 + HasBoth_dir : 840 + AllEnabled_dir : 408 + #AXI = 0 + #GPIO = 50 + #GBOX_GPIO = 4840 + #inp_colm A2F = 1815 + #out_colm F2A = 3355 +======== end pin_c stats. + +======== pin_c summary: + Pin Table csv : /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/Virgo_Pin_Table.csv + BLIF file : /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif + total design inputs: 13 placed design inputs: 14 + total design outputs: 24 placed design outputs: 23 + pin_c output : I_DELAY_primitive_inst_pin_loc.place + auto-PCF : TRUE + has edits (config.json) : /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/config.json + clk_map_file : I_DELAY_primitive_inst.temp_file_clkmap + check BLIF status : PASS + pinc_trace verbosity= 3 + + [Error] NOTE CRITICAL_WARNINGs (1) + +======== end pin_c summary. + +deal_pinc() succeeded. + diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/vpr_stdout.log b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/vpr_stdout.log new file mode 100644 index 00000000..377ab1f9 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/vpr_stdout.log @@ -0,0 +1,947 @@ +VPR FPGA Placement and Routing. +Version: +Revision: +Compiled: +Compiler: GNU 11.2.1 on Linux-3.10.0-1160.90.1.el7.x86_64 x86_64 +Build Info: Release VTR_ASSERT_LEVEL=2 + +University of Toronto +verilogtorouting.org +vtr-users@googlegroups.com +This is free open source code under MIT license. + +VPR was run with the following command-line: +/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/vpr /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --sdc_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc --route_chan_width 160 --suppress_warnings check_rr_node_warnings.log,check_rr_node --clock_modeling ideal --absorb_buffer_luts off --skip_sync_clustering_and_routing_results off --constant_net_method route --post_place_timing_report I_DELAY_primitive_inst_post_place_timing.rpt --device castor62x44_heterogeneous --allow_unrelated_clustering on --allow_dangling_combinational_nodes on --place_delta_delay_matrix_calculation_method dijkstra --gen_post_synthesis_netlist on --post_synth_netlist_unconn_inputs gnd --inner_loop_recompute_divider 1 --max_router_iterations 1500 --timing_report_detail detailed --timing_report_npaths 100 --top I_DELAY_primitive_inst --net_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net --place_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place --route_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route --place --fix_clusters I_DELAY_primitive_inst_pin_loc.place + +Using up to 1 parallel worker(s) + +Architecture file: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml +Circuit name: fabric_I_DELAY_primitive_inst_post_synth + +# Loading Architecture Description +Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 3: Model 'dsp_phy' input port 'sc_in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 4: Model 'dsp_phy' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 5: Model 'dsp_phy' output port 'sc_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 6: Model 'RS_DSP_MULT' input port 'feedback' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 7: Model 'RS_DSP_MULT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 8: Model 'RS_DSP_MULT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 9: Model 'RS_DSP_MULT_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 10: Model 'RS_DSP_MULT_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 11: Model 'RS_DSP_MULT_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 12: Model 'RS_DSP_MULT_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 13: Model 'RS_DSP_MULT_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 14: Model 'RS_DSP_MULT_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 15: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 16: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 17: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 18: Model 'RS_DSP_MULTADD' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 19: Model 'RS_DSP_MULTADD' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 20: Model 'RS_DSP_MULTADD' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 21: Model 'RS_DSP_MULTADD' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 22: Model 'RS_DSP_MULTADD' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 23: Model 'RS_DSP_MULTADD' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 24: Model 'RS_DSP_MULTADD_REGIN' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 25: Model 'RS_DSP_MULTADD_REGIN' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 26: Model 'RS_DSP_MULTADD_REGIN' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 27: Model 'RS_DSP_MULTADD_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 28: Model 'RS_DSP_MULTADD_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 29: Model 'RS_DSP_MULTADD_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 30: Model 'RS_DSP_MULTADD_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 31: Model 'RS_DSP_MULTADD_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 32: Model 'RS_DSP_MULTADD_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 33: Model 'RS_DSP_MULTADD_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 34: Model 'RS_DSP_MULTADD_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 35: Model 'RS_DSP_MULTADD_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 36: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 37: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 38: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 39: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 40: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 41: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 42: Model 'RS_DSP_MULTACC' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 43: Model 'RS_DSP_MULTACC' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 44: Model 'RS_DSP_MULTACC' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 45: Model 'RS_DSP_MULTACC' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 46: Model 'RS_DSP_MULTACC' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 47: Model 'RS_DSP_MULTACC' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 48: Model 'RS_DSP_MULTACC_REGIN' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 49: Model 'RS_DSP_MULTACC_REGIN' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 50: Model 'RS_DSP_MULTACC_REGIN' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 51: Model 'RS_DSP_MULTACC_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 52: Model 'RS_DSP_MULTACC_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 53: Model 'RS_DSP_MULTACC_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 54: Model 'RS_DSP_MULTACC_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 55: Model 'RS_DSP_MULTACC_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 56: Model 'RS_DSP_MULTACC_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 57: Model 'RS_DSP_MULTACC_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 58: Model 'RS_DSP_MULTACC_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 59: Model 'RS_DSP_MULTACC_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 60: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 61: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 62: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 63: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 64: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 65: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 66: Model 'bram_phy' input port 'sc_in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 67: Model 'bram_phy' output port 'sc_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 68: Model 'bram_phy' output port 'PL_DATA_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 69: Model 'bram_phy' output port 'PL_ADDR_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 70: Model 'bram_phy' output port 'PL_WEN_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 71: Model 'bram_phy' output port 'PL_CLK_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 72: Model 'bram_phy' output port 'PL_REN_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 73: Model 'bram_phy' output port 'PL_ENA_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 74: Model 'bram_phy' output port 'PL_INIT_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +mode 'io[physical]' is defined by user to be disabled in packing +mode 'iopad[default]' is defined by user to be disabled in packing +mode 'fle[physical]' is defined by user to be disabled in packing +mode 'fabric[default]' is defined by user to be disabled in packing +mode 'ff_bypass[default]' is defined by user to be disabled in packing +mode 'dsp_lr[physical]' is defined by user to be disabled in packing +mode 'bram_lr[physical]' is defined by user to be disabled in packing +# Loading Architecture Description took 0.06 seconds (max_rss 17.2 MiB, delta_rss +0.0 MiB) + +Timing analysis: ON +Circuit netlist file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net +Circuit placement file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place +Circuit routing file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route +Circuit SDC file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc +Vpr floorplanning constraints file: not specified + +Packer: ENABLED +Placer: ENABLED +Router: DISABLED +Analysis: DISABLED + +VPR was run with the following options: + +NetlistOpts.abosrb_buffer_luts : false +NetlistOpts.sweep_dangling_primary_ios : true +NetlistOpts.sweep_dangling_nets : true +NetlistOpts.sweep_dangling_blocks : true +NetlistOpts.sweep_constant_primary_outputs: false +NetlistOpts.netlist_verbosity : 1 +NetlistOpts.const_gen_inference : COMB_SEQ + +PackerOpts.allow_unrelated_clustering: true +PackerOpts.alpha_clustering: 0.750000 +PackerOpts.beta_clustering: 0.900000 +PackerOpts.cluster_seed_type: BLEND2 +PackerOpts.connection_driven: true +PackerOpts.global_clocks: true +PackerOpts.hill_climbing_flag: false +PackerOpts.inter_cluster_net_delay: 1.000000 +PackerOpts.timing_driven: true +PackerOpts.target_external_pin_util: auto + +PlacerOpts.place_freq: PLACE_ONCE +PlacerOpts.place_algorithm: CRITICALITY_TIMING_PLACE +PlacerOpts.pad_loc_type: FREE +PlacerOpts.constraints_file: Using constraints file 'I_DELAY_primitive_inst_pin_loc.place' +PlacerOpts.place_cost_exp: 1.000000 +PlacerOpts.place_chan_width: 160 +PlacerOpts.inner_loop_recompute_divider: 1 +PlacerOpts.recompute_crit_iter: 1 +PlacerOpts.timing_tradeoff: 0.500000 +PlacerOpts.td_place_exp_first: 1.000000 +PlacerOpts.td_place_exp_last: 8.000000 +PlacerOpts.delay_offset: 0.000000 +PlacerOpts.delay_ramp_delta_threshold: -1 +PlacerOpts.delay_ramp_slope: 0.000000 +PlacerOpts.tsu_rel_margin: 1.000000 +PlacerOpts.tsu_abs_margin: 0.000000 +PlacerOpts.post_place_timing_report_file: I_DELAY_primitive_inst_post_place_timing.rpt +PlacerOpts.allowed_tiles_for_delay_model: +PlacerOpts.delay_model_reducer: MIN +PlacerOpts.delay_model_type: DELTA +PlacerOpts.rlim_escape_fraction: 0.000000 +PlacerOpts.move_stats_file: +PlacerOpts.placement_saves_per_temperature: 0 +PlacerOpts.effort_scaling: CIRCUIT +PlacerOpts.place_delta_delay_matrix_calculation_method: DIJKSTRA_EXPANSION +PlaceOpts.seed: 1 +AnnealSched.type: AUTO_SCHED +AnnealSched.inner_num: 0.500000 + +# Building complex block graph +Warning 75: clb[0].sr_in[0] unconnected pin in architecture. +Warning 76: clb[0].sr_out[0] unconnected pin in architecture. +Warning 77: dsp[0].sr_in[0] unconnected pin in architecture. +Warning 78: dsp[0].sr_in[1] unconnected pin in architecture. +Warning 79: dsp[0].sr_in[2] unconnected pin in architecture. +Warning 80: dsp[0].sr_out[0] unconnected pin in architecture. +Warning 81: dsp[0].sr_out[1] unconnected pin in architecture. +Warning 82: dsp[0].sr_out[2] unconnected pin in architecture. +Warning 83: bram[0].sr_in[0] unconnected pin in architecture. +Warning 84: bram[0].sr_in[1] unconnected pin in architecture. +Warning 85: bram[0].sr_in[2] unconnected pin in architecture. +Warning 86: bram[0].sr_in[3] unconnected pin in architecture. +Warning 87: bram[0].sr_in[4] unconnected pin in architecture. +Warning 88: bram[0].sr_in[5] unconnected pin in architecture. +Warning 89: bram[0].plr_i[0] unconnected pin in architecture. +Warning 90: bram[0].plr_i[1] unconnected pin in architecture. +Warning 91: bram[0].plr_i[2] unconnected pin in architecture. +Warning 92: bram[0].plr_i[3] unconnected pin in architecture. +Warning 93: bram[0].plr_i[4] unconnected pin in architecture. +Warning 94: bram[0].plr_i[5] unconnected pin in architecture. +Warning 95: bram[0].plr_i[6] unconnected pin in architecture. +Warning 96: bram[0].plr_i[7] unconnected pin in architecture. +Warning 97: bram[0].plr_i[8] unconnected pin in architecture. +Warning 98: bram[0].plr_i[9] unconnected pin in architecture. +Warning 99: bram[0].plr_i[10] unconnected pin in architecture. +Warning 100: bram[0].plr_i[11] unconnected pin in architecture. +Warning 101: bram[0].plr_i[12] unconnected pin in architecture. +Warning 102: bram[0].plr_i[13] unconnected pin in architecture. +Warning 103: bram[0].plr_i[14] unconnected pin in architecture. +Warning 104: bram[0].plr_i[15] unconnected pin in architecture. +Warning 105: bram[0].plr_i[16] unconnected pin in architecture. +Warning 106: bram[0].plr_i[17] unconnected pin in architecture. +Warning 107: bram[0].plr_i[18] unconnected pin in architecture. +Warning 108: bram[0].plr_i[19] unconnected pin in architecture. +Warning 109: bram[0].plr_i[20] unconnected pin in architecture. +Warning 110: bram[0].plr_i[21] unconnected pin in architecture. +Warning 111: bram[0].plr_i[22] unconnected pin in architecture. +Warning 112: bram[0].plr_i[23] unconnected pin in architecture. +Warning 113: bram[0].plr_i[24] unconnected pin in architecture. +Warning 114: bram[0].plr_i[25] unconnected pin in architecture. +Warning 115: bram[0].plr_i[26] unconnected pin in architecture. +Warning 116: bram[0].plr_i[27] unconnected pin in architecture. +Warning 117: bram[0].plr_i[28] unconnected pin in architecture. +Warning 118: bram[0].plr_i[29] unconnected pin in architecture. +Warning 119: bram[0].plr_i[30] unconnected pin in architecture. +Warning 120: bram[0].plr_i[31] unconnected pin in architecture. +Warning 121: bram[0].plr_i[32] unconnected pin in architecture. +Warning 122: bram[0].plr_i[33] unconnected pin in architecture. +Warning 123: bram[0].plr_i[34] unconnected pin in architecture. +Warning 124: bram[0].plr_i[35] unconnected pin in architecture. +Warning 125: bram[0].sr_out[0] unconnected pin in architecture. +Warning 126: bram[0].sr_out[1] unconnected pin in architecture. +Warning 127: bram[0].sr_out[2] unconnected pin in architecture. +Warning 128: bram[0].sr_out[3] unconnected pin in architecture. +Warning 129: bram[0].sr_out[4] unconnected pin in architecture. +Warning 130: bram[0].sr_out[5] unconnected pin in architecture. +Warning 131: bram[0].plr_o[0] unconnected pin in architecture. +Warning 132: bram[0].plr_o[1] unconnected pin in architecture. +Warning 133: bram[0].plr_o[2] unconnected pin in architecture. +Warning 134: bram[0].plr_o[3] unconnected pin in architecture. +Warning 135: bram[0].plr_o[4] unconnected pin in architecture. +Warning 136: bram[0].plr_o[5] unconnected pin in architecture. +Warning 137: bram[0].plr_o[6] unconnected pin in architecture. +Warning 138: bram[0].plr_o[7] unconnected pin in architecture. +Warning 139: bram[0].plr_o[8] unconnected pin in architecture. +Warning 140: bram[0].plr_o[9] unconnected pin in architecture. +Warning 141: bram[0].plr_o[10] unconnected pin in architecture. +Warning 142: bram[0].plr_o[11] unconnected pin in architecture. +Warning 143: bram[0].plr_o[12] unconnected pin in architecture. +Warning 144: bram[0].plr_o[13] unconnected pin in architecture. +Warning 145: bram[0].plr_o[14] unconnected pin in architecture. +Warning 146: bram[0].plr_o[15] unconnected pin in architecture. +Warning 147: bram[0].plr_o[16] unconnected pin in architecture. +Warning 148: bram[0].plr_o[17] unconnected pin in architecture. +Warning 149: bram[0].plr_o[18] unconnected pin in architecture. +Warning 150: bram[0].plr_o[19] unconnected pin in architecture. +Warning 151: bram[0].plr_o[20] unconnected pin in architecture. +Warning 152: bram[0].plr_o[21] unconnected pin in architecture. +Warning 153: bram[0].plr_o[22] unconnected pin in architecture. +Warning 154: bram[0].plr_o[23] unconnected pin in architecture. +Warning 155: bram[0].plr_o[24] unconnected pin in architecture. +Warning 156: bram[0].plr_o[25] unconnected pin in architecture. +Warning 157: bram[0].plr_o[26] unconnected pin in architecture. +Warning 158: bram[0].plr_o[27] unconnected pin in architecture. +Warning 159: bram[0].plr_o[28] unconnected pin in architecture. +Warning 160: bram[0].plr_o[29] unconnected pin in architecture. +Warning 161: bram[0].plr_o[30] unconnected pin in architecture. +Warning 162: bram[0].plr_o[31] unconnected pin in architecture. +Warning 163: bram[0].plr_o[32] unconnected pin in architecture. +Warning 164: bram[0].plr_o[33] unconnected pin in architecture. +Warning 165: bram[0].plr_o[34] unconnected pin in architecture. +Warning 166: bram[0].plr_o[35] unconnected pin in architecture. +# Building complex block graph took 0.04 seconds (max_rss 18.2 MiB, delta_rss +1.0 MiB) +Circuit file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif +# Load circuit +Found constant-zero generator '$false' +Found constant-one generator '$true' +Found constant-zero generator '$undef' +# Load circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.5 MiB) +# Clean circuit +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 13 additional primitive pins as constant generators due to constant inputs +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 0 additional primitive pins as constant generators due to constant inputs +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 0 additional primitive pins as constant generators due to constant inputs +Swept input(s) : 0 +Swept output(s) : 0 (0 dangling, 0 constant) +Swept net(s) : 2 +Swept block(s) : 2 +Constant Pins Marked: 13 +# Clean circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +# Compress circuit +# Compress circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +# Verify circuit +# Verify circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +Circuit Statistics: + Blocks: 69 + .input : 13 + .output: 24 + 0-LUT : 1 + 6-LUT : 30 + dffre : 1 + Nets : 45 + Avg Fanout: 1.3 + Max Fanout: 15.0 + Min Fanout: 1.0 + Netlist Clocks: 1 +# Build Timing Graph + Timing Graph Nodes: 104 + Timing Graph Edges: 94 + Timing Graph Levels: 6 +# Build Timing Graph took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +Netlist contains 1 clocks + Netlist Clock '$clk_buf_$ibuf_CLK_IN' Fanout: 1 pins (1.0%), 1 blocks (1.4%) +# Load Timing Constraints + +SDC file '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc' contained no SDC commands +Setting default timing constraints: + * constrain all primay inputs and primary outputs on netlist clock '$clk_buf_$ibuf_CLK_IN' + * optimize netlist clock to run as fast as possible +Timing constraints created 1 clocks + Constrained Clock '$clk_buf_$ibuf_CLK_IN' Source: '$clk_buf_$ibuf_CLK_IN.inpad[0]' + +# Load Timing Constraints took 0.00 seconds (max_rss 19.0 MiB, delta_rss +0.3 MiB) +# Load packing +Begin loading packed FPGA netlist file. +Netlist generated from file '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net'. +Detected 1 constant generators (to see names run with higher pack verbosity) +Finished loading packed FPGA netlist file (took 0.04 seconds). +# Load packing took 0.05 seconds (max_rss 57.9 MiB, delta_rss +38.7 MiB) +Warning 167: Netlist contains 0 global net to non-global architecture pin connections + +Pb types usage... + io : 37 + io_output : 24 + outpad : 24 + io_input : 13 + inpad : 13 + clb : 2 + clb_lr : 2 + fle : 16 + ble5 : 31 + lut5 : 31 + lut : 31 + ff : 1 + DFFRE : 1 + +# Create Device +## Build Device Grid +FPGA sized to 64 x 46: 2944 grid tiles (castor62x44_heterogeneous) + +Resource usage... + Netlist + 37 blocks of type: io + Architecture + 4320 blocks of type: io_top + 3168 blocks of type: io_right + 4320 blocks of type: io_bottom + 3168 blocks of type: io_left + Netlist + 2 blocks of type: clb + Architecture + 2184 blocks of type: clb + Netlist + 0 blocks of type: dsp + Architecture + 56 blocks of type: dsp + Netlist + 0 blocks of type: bram + Architecture + 56 blocks of type: bram + +Device Utilization: 0.00 (target 1.00) + Physical Tile io_top: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_right: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_bottom: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_left: + Block Utilization: 0.01 Logical Block: io + Physical Tile clb: + Block Utilization: 0.00 Logical Block: clb + Physical Tile dsp: + Block Utilization: 0.00 Logical Block: dsp + Physical Tile bram: + Block Utilization: 0.00 Logical Block: bram + +## Build Device Grid took 0.00 seconds (max_rss 58.2 MiB, delta_rss +0.0 MiB) +Warning 168: Tileable routing resource graph does not support clock modeling yet! Related options are ignored... +## Build tileable routing resource graph +X-direction routing channel width is 160 +Y-direction routing channel width is 160 +Warning 169: Sized nonsensical R=0 transistor to minimum width +Warning 170: Sized nonsensical R=0 transistor to minimum width +Warning 171: Sized nonsensical R=0 transistor to minimum width +Warning 172: Sized nonsensical R=0 transistor to minimum width +## Build tileable routing resource graph took 13.46 seconds (max_rss 472.8 MiB, delta_rss +414.6 MiB) + RR Graph Nodes: 1365608 + RR Graph Edges: 6033268 +# Create Device took 14.07 seconds (max_rss 472.8 MiB, delta_rss +414.6 MiB) + +# Computing router lookahead map +## Computing wire lookahead +## Computing wire lookahead took 29.35 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +## Computing src/opin lookahead +Warning 173: Found no more ample locations for SOURCE in io_top +Warning 174: Found no more ample locations for OPIN in io_top +Warning 175: Found no more ample locations for SOURCE in io_right +Warning 176: Found no more ample locations for OPIN in io_right +Warning 177: Found no more ample locations for SOURCE in io_bottom +Warning 178: Found no more ample locations for OPIN in io_bottom +Warning 179: Found no more ample locations for SOURCE in io_left +Warning 180: Found no more ample locations for OPIN in io_left +Warning 181: Found no more ample locations for SOURCE in clb +Warning 182: Found no more ample locations for OPIN in clb +Warning 183: Found no more ample locations for SOURCE in dsp +Warning 184: Found no more ample locations for OPIN in dsp +Warning 185: Found no more ample locations for SOURCE in bram +Warning 186: Found no more ample locations for OPIN in bram +## Computing src/opin lookahead took 0.10 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +# Computing router lookahead map took 29.56 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +# Computing placement delta delay look-up +RR graph channel widths unchanged, skipping RR graph rebuild +## Computing delta delays +Warning 187: Unable to route between blocks at (1,1) and (1,45) to characterize delay (setting to inf) +Warning 188: Unable to route between blocks at (1,1) and (2,45) to characterize delay (setting to inf) +Warning 189: Unable to route between blocks at (1,1) and (3,45) to characterize delay (setting to inf) +Warning 190: Unable to route between blocks at (1,1) and (4,45) to characterize delay (setting to inf) +Warning 191: Unable to route between blocks at (1,1) and (5,45) to characterize delay (setting to inf) +Warning 192: Unable to route between blocks at (1,1) and (6,45) to characterize delay (setting to inf) +Warning 193: Unable to route between blocks at (1,1) and (7,45) to characterize delay (setting to inf) +Warning 194: Unable to route between blocks at (1,1) and (8,45) to characterize delay (setting to inf) +Warning 195: Unable to route between blocks at (1,1) and (9,45) to characterize delay (setting to inf) +Warning 196: Unable to route between blocks at (1,1) and (10,45) to characterize delay (setting to inf) +Warning 197: Unable to route between blocks at (1,1) and (11,45) to characterize delay (setting to inf) +Warning 198: Unable to route between blocks at (1,1) and (12,45) to characterize delay (setting to inf) +Warning 199: Unable to route between blocks at (1,1) and (13,45) to characterize delay (setting to inf) +Warning 200: Unable to route between blocks at (1,1) and (14,45) to characterize delay (setting to inf) +Warning 201: Unable to route between blocks at (1,1) and (15,45) to characterize delay (setting to inf) +Warning 202: Unable to route between blocks at (1,1) and (16,45) to characterize delay (setting to inf) +Warning 203: Unable to route between blocks at (1,1) and (17,45) to characterize delay (setting to inf) +Warning 204: Unable to route between blocks at (1,1) and (18,45) to characterize delay (setting to inf) +Warning 205: Unable to route between blocks at (1,1) and (19,45) to characterize delay (setting to inf) +Warning 206: Unable to route between blocks at (1,1) and (20,45) to characterize delay (setting to inf) +Warning 207: Unable to route between blocks at (1,1) and (21,45) to characterize delay (setting to inf) +Warning 208: Unable to route between blocks at (1,1) and (22,45) to characterize delay (setting to inf) +Warning 209: Unable to route between blocks at (1,1) and (23,45) to characterize delay (setting to inf) +Warning 210: Unable to route between blocks at (1,1) and (24,45) to characterize delay (setting to inf) +Warning 211: Unable to route between blocks at (1,1) and (25,45) to characterize delay (setting to inf) +Warning 212: Unable to route between blocks at (1,1) and (26,45) to characterize delay (setting to inf) +Warning 213: Unable to route between blocks at (1,1) and (27,45) to characterize delay (setting to inf) +Warning 214: Unable to route between blocks at (1,1) and (28,45) to characterize delay (setting to inf) +Warning 215: Unable to route between blocks at (1,1) and (29,45) to characterize delay (setting to inf) +Warning 216: Unable to route between blocks at (1,1) and (30,45) to characterize delay (setting to inf) +Warning 217: Unable to route between blocks at (1,1) and (31,45) to characterize delay (setting to inf) +Warning 218: Unable to route between blocks at (1,1) and (32,45) to characterize delay (setting to inf) +Warning 219: Unable to route between blocks at (1,1) and (33,45) to characterize delay (setting to inf) +Warning 220: Unable to route between blocks at (1,1) and (34,45) to characterize delay (setting to inf) +Warning 221: Unable to route between blocks at (1,1) and (35,45) to characterize delay (setting to inf) +Warning 222: Unable to route between blocks at (1,1) and (36,45) to characterize delay (setting to inf) +Warning 223: Unable to route between blocks at (1,1) and (37,45) to characterize delay (setting to inf) +Warning 224: Unable to route between blocks at (1,1) and (38,45) to characterize delay (setting to inf) +Warning 225: Unable to route between blocks at (1,1) and (39,45) to characterize delay (setting to inf) +Warning 226: Unable to route between blocks at (1,1) and (40,45) to characterize delay (setting to inf) +Warning 227: Unable to route between blocks at (1,1) and (41,45) to characterize delay (setting to inf) +Warning 228: Unable to route between blocks at (1,1) and (42,45) to characterize delay (setting to inf) +Warning 229: Unable to route between blocks at (1,1) and (43,45) to characterize delay (setting to inf) +Warning 230: Unable to route between blocks at (1,1) and (44,45) to characterize delay (setting to inf) +Warning 231: Unable to route between blocks at (1,1) and (45,45) to characterize delay (setting to inf) +Warning 232: Unable to route between blocks at (1,1) and (46,45) to characterize delay (setting to inf) +Warning 233: Unable to route between blocks at (1,1) and (47,45) to characterize delay (setting to inf) +Warning 234: Unable to route between blocks at (1,1) and (48,45) to characterize delay (setting to inf) +Warning 235: Unable to route between blocks at (1,1) and (49,45) to characterize delay (setting to inf) +Warning 236: Unable to route between blocks at (1,1) and (50,45) to characterize delay (setting to inf) +Warning 237: Unable to route between blocks at (1,1) and (51,45) to characterize delay (setting to inf) +Warning 238: Unable to route between blocks at (1,1) and (52,45) to characterize delay (setting to inf) +Warning 239: Unable to route between blocks at (1,1) and (53,45) to characterize delay (setting to inf) +Warning 240: Unable to route between blocks at (1,1) and (54,45) to characterize delay (setting to inf) +Warning 241: Unable to route between blocks at (1,1) and (55,45) to characterize delay (setting to inf) +Warning 242: Unable to route between blocks at (1,1) and (56,45) to characterize delay (setting to inf) +Warning 243: Unable to route between blocks at (1,1) and (57,45) to characterize delay (setting to inf) +Warning 244: Unable to route between blocks at (1,1) and (58,45) to characterize delay (setting to inf) +Warning 245: Unable to route between blocks at (1,1) and (59,45) to characterize delay (setting to inf) +Warning 246: Unable to route between blocks at (1,1) and (60,45) to characterize delay (setting to inf) +Warning 247: Unable to route between blocks at (1,1) and (61,45) to characterize delay (setting to inf) +Warning 248: Unable to route between blocks at (1,1) and (62,45) to characterize delay (setting to inf) +Warning 249: Unable to route between blocks at (1,1) and (63,1) to characterize delay (setting to inf) +Warning 250: Unable to route between blocks at (1,1) and (63,2) to characterize delay (setting to inf) +Warning 251: Unable to route between blocks at (1,1) and (63,3) to characterize delay (setting to inf) +Warning 252: Unable to route between blocks at (1,1) and (63,4) to characterize delay (setting to inf) +Warning 253: Unable to route between blocks at (1,1) and (63,5) to characterize delay (setting to inf) +Warning 254: Unable to route between blocks at (1,1) and (63,6) to characterize delay (setting to inf) +Warning 255: Unable to route between blocks at (1,1) and (63,7) to characterize delay (setting to inf) +Warning 256: Unable to route between blocks at (1,1) and (63,8) to characterize delay (setting to inf) +Warning 257: Unable to route between blocks at (1,1) and (63,9) to characterize delay (setting to inf) +Warning 258: Unable to route between blocks at (1,1) and (63,10) to characterize delay (setting to inf) +Warning 259: Unable to route between blocks at (1,1) and (63,11) to characterize delay (setting to inf) +Warning 260: Unable to route between blocks at (1,1) and (63,12) to characterize delay (setting to inf) +Warning 261: Unable to route between blocks at (1,1) and (63,13) to characterize delay (setting to inf) +Warning 262: Unable to route between blocks at (1,1) and (63,14) to characterize delay (setting to inf) +Warning 263: Unable to route between blocks at (1,1) and (63,15) to characterize delay (setting to inf) +Warning 264: Unable to route between blocks at (1,1) and (63,16) to characterize delay (setting to inf) +Warning 265: Unable to route between blocks at (1,1) and (63,17) to characterize delay (setting to inf) +Warning 266: Unable to route between blocks at (1,1) and (63,18) to characterize delay (setting to inf) +Warning 267: Unable to route between blocks at (1,1) and (63,19) to characterize delay (setting to inf) +Warning 268: Unable to route between blocks at (1,1) and (63,20) to characterize delay (setting to inf) +Warning 269: Unable to route between blocks at (1,1) and (63,21) to characterize delay (setting to inf) +Warning 270: Unable to route between blocks at (1,1) and (63,22) to characterize delay (setting to inf) +Warning 271: Unable to route between blocks at (1,1) and (63,23) to characterize delay (setting to inf) +Warning 272: Unable to route between blocks at (1,1) and (63,24) to characterize delay (setting to inf) +Warning 273: Unable to route between blocks at (1,1) and (63,25) to characterize delay (setting to inf) +Warning 274: Unable to route between blocks at (1,1) and (63,26) to characterize delay (setting to inf) +Warning 275: Unable to route between blocks at (1,1) and (63,27) to characterize delay (setting to inf) +Warning 276: Unable to route between blocks at (1,1) and (63,28) to characterize delay (setting to inf) +Warning 277: Unable to route between blocks at (1,1) and (63,29) to characterize delay (setting to inf) +Warning 278: Unable to route between blocks at (1,1) and (63,30) to characterize delay (setting to inf) +Warning 279: Unable to route between blocks at (1,1) and (63,31) to characterize delay (setting to inf) +Warning 280: Unable to route between blocks at (1,1) and (63,32) to characterize delay (setting to inf) +Warning 281: Unable to route between blocks at (1,1) and (63,33) to characterize delay (setting to inf) +Warning 282: Unable to route between blocks at (1,1) and (63,34) to characterize delay (setting to inf) +Warning 283: Unable to route between blocks at (1,1) and (63,35) to characterize delay (setting to inf) +Warning 284: Unable to route between blocks at (1,1) and (63,36) to characterize delay (setting to inf) +Warning 285: Unable to route between blocks at (1,1) and (63,37) to characterize delay (setting to inf) +Warning 286: Unable to route between blocks at (1,1) and (63,38) to characterize delay (setting to inf) +Warning 287: Unable to route between blocks at (1,1) and (63,39) to characterize delay (setting to inf) +Warning 288: Unable to route between blocks at (1,1) and (63,40) to characterize delay (setting to inf) +Warning 289: Unable to route between blocks at (1,1) and (63,41) to characterize delay (setting to inf) +Warning 290: Unable to route between blocks at (1,1) and (63,42) to characterize delay (setting to inf) +Warning 291: Unable to route between blocks at (1,1) and (63,43) to characterize delay (setting to inf) +Warning 292: Unable to route between blocks at (1,1) and (63,44) to characterize delay (setting to inf) +Warning 293: Unable to route between blocks at (1,1) and (63,45) to characterize delay (setting to inf) +Warning 294: Unable to route between blocks at (4,4) and (4,45) to characterize delay (setting to inf) +Warning 295: Unable to route between blocks at (4,4) and (5,45) to characterize delay (setting to inf) +Warning 296: Unable to route between blocks at (4,4) and (6,45) to characterize delay (setting to inf) +Warning 297: Unable to route between blocks at (4,4) and (7,45) to characterize delay (setting to inf) +Warning 298: Unable to route between blocks at (4,4) and (8,45) to characterize delay (setting to inf) +Warning 299: Unable to route between blocks at (4,4) and (9,45) to characterize delay (setting to inf) +Warning 300: Unable to route between blocks at (4,4) and (10,45) to characterize delay (setting to inf) +Warning 301: Unable to route between blocks at (4,4) and (11,45) to characterize delay (setting to inf) +Warning 302: Unable to route between blocks at (4,4) and (12,45) to characterize delay (setting to inf) +Warning 303: Unable to route between blocks at (4,4) and (13,45) to characterize delay (setting to inf) +Warning 304: Unable to route between blocks at (4,4) and (14,45) to characterize delay (setting to inf) +Warning 305: Unable to route between blocks at (4,4) and (15,45) to characterize delay (setting to inf) +Warning 306: Unable to route between blocks at (4,4) and (16,45) to characterize delay (setting to inf) +Warning 307: Unable to route between blocks at (4,4) and (17,45) to characterize delay (setting to inf) +Warning 308: Unable to route between blocks at (4,4) and (18,45) to characterize delay (setting to inf) +Warning 309: Unable to route between blocks at (4,4) and (19,45) to characterize delay (setting to inf) +Warning 310: Unable to route between blocks at (4,4) and (20,45) to characterize delay (setting to inf) +Warning 311: Unable to route between blocks at (4,4) and (21,45) to characterize delay (setting to inf) +Warning 312: Unable to route between blocks at (4,4) and (22,45) to characterize delay (setting to inf) +Warning 313: Unable to route between blocks at (4,4) and (23,45) to characterize delay (setting to inf) +Warning 314: Unable to route between blocks at (4,4) and (24,45) to characterize delay (setting to inf) +Warning 315: Unable to route between blocks at (4,4) and (25,45) to characterize delay (setting to inf) +Warning 316: Unable to route between blocks at (4,4) and (26,45) to characterize delay (setting to inf) +Warning 317: Unable to route between blocks at (4,4) and (27,45) to characterize delay (setting to inf) +Warning 318: Unable to route between blocks at (4,4) and (28,45) to characterize delay (setting to inf) +Warning 319: Unable to route between blocks at (4,4) and (29,45) to characterize delay (setting to inf) +Warning 320: Unable to route between blocks at (4,4) and (30,45) to characterize delay (setting to inf) +Warning 321: Unable to route between blocks at (4,4) and (31,45) to characterize delay (setting to inf) +Warning 322: Unable to route between blocks at (4,4) and (32,45) to characterize delay (setting to inf) +Warning 323: Unable to route between blocks at (4,4) and (33,45) to characterize delay (setting to inf) +Warning 324: Unable to route between blocks at (4,4) and (34,45) to characterize delay (setting to inf) +Warning 325: Unable to route between blocks at (4,4) and (35,45) to characterize delay (setting to inf) +Warning 326: Unable to route between blocks at (4,4) and (36,45) to characterize delay (setting to inf) +Warning 327: Unable to route between blocks at (4,4) and (37,45) to characterize delay (setting to inf) +Warning 328: Unable to route between blocks at (4,4) and (38,45) to characterize delay (setting to inf) +Warning 329: Unable to route between blocks at (4,4) and (39,45) to characterize delay (setting to inf) +Warning 330: Unable to route between blocks at (4,4) and (40,45) to characterize delay (setting to inf) +Warning 331: Unable to route between blocks at (4,4) and (41,45) to characterize delay (setting to inf) +Warning 332: Unable to route between blocks at (4,4) and (42,45) to characterize delay (setting to inf) +Warning 333: Unable to route between blocks at (4,4) and (43,45) to characterize delay (setting to inf) +Warning 334: Unable to route between blocks at (4,4) and (44,45) to characterize delay (setting to inf) +Warning 335: Unable to route between blocks at (4,4) and (45,45) to characterize delay (setting to inf) +Warning 336: Unable to route between blocks at (4,4) and (46,45) to characterize delay (setting to inf) +Warning 337: Unable to route between blocks at (4,4) and (47,45) to characterize delay (setting to inf) +Warning 338: Unable to route between blocks at (4,4) and (48,45) to characterize delay (setting to inf) +Warning 339: Unable to route between blocks at (4,4) and (49,45) to characterize delay (setting to inf) +Warning 340: Unable to route between blocks at (4,4) and (50,45) to characterize delay (setting to inf) +Warning 341: Unable to route between blocks at (4,4) and (51,45) to characterize delay (setting to inf) +Warning 342: Unable to route between blocks at (4,4) and (52,45) to characterize delay (setting to inf) +Warning 343: Unable to route between blocks at (4,4) and (53,45) to characterize delay (setting to inf) +Warning 344: Unable to route between blocks at (4,4) and (54,45) to characterize delay (setting to inf) +Warning 345: Unable to route between blocks at (4,4) and (55,45) to characterize delay (setting to inf) +Warning 346: Unable to route between blocks at (4,4) and (56,45) to characterize delay (setting to inf) +Warning 347: Unable to route between blocks at (4,4) and (57,45) to characterize delay (setting to inf) +Warning 348: Unable to route between blocks at (4,4) and (58,45) to characterize delay (setting to inf) +Warning 349: Unable to route between blocks at (4,4) and (59,45) to characterize delay (setting to inf) +Warning 350: Unable to route between blocks at (4,4) and (60,45) to characterize delay (setting to inf) +Warning 351: Unable to route between blocks at (4,4) and (61,45) to characterize delay (setting to inf) +Warning 352: Unable to route between blocks at (4,4) and (62,45) to characterize delay (setting to inf) +Warning 353: Unable to route between blocks at (4,4) and (63,4) to characterize delay (setting to inf) +Warning 354: Unable to route between blocks at (4,4) and (63,5) to characterize delay (setting to inf) +Warning 355: Unable to route between blocks at (4,4) and (63,6) to characterize delay (setting to inf) +Warning 356: Unable to route between blocks at (4,4) and (63,7) to characterize delay (setting to inf) +Warning 357: Unable to route between blocks at (4,4) and (63,8) to characterize delay (setting to inf) +Warning 358: Unable to route between blocks at (4,4) and (63,9) to characterize delay (setting to inf) +Warning 359: Unable to route between blocks at (4,4) and (63,10) to characterize delay (setting to inf) +Warning 360: Unable to route between blocks at (4,4) and (63,11) to characterize delay (setting to inf) +Warning 361: Unable to route between blocks at (4,4) and (63,12) to characterize delay (setting to inf) +Warning 362: Unable to route between blocks at (4,4) and (63,13) to characterize delay (setting to inf) +Warning 363: Unable to route between blocks at (4,4) and (63,14) to characterize delay (setting to inf) +Warning 364: Unable to route between blocks at (4,4) and (63,15) to characterize delay (setting to inf) +Warning 365: Unable to route between blocks at (4,4) and (63,16) to characterize delay (setting to inf) +Warning 366: Unable to route between blocks at (4,4) and (63,17) to characterize delay (setting to inf) +Warning 367: Unable to route between blocks at (4,4) and (63,18) to characterize delay (setting to inf) +Warning 368: Unable to route between blocks at (4,4) and (63,19) to characterize delay (setting to inf) +Warning 369: Unable to route between blocks at (4,4) and (63,20) to characterize delay (setting to inf) +Warning 370: Unable to route between blocks at (4,4) and (63,21) to characterize delay (setting to inf) +Warning 371: Unable to route between blocks at (4,4) and (63,22) to characterize delay (setting to inf) +Warning 372: Unable to route between blocks at (4,4) and (63,23) to characterize delay (setting to inf) +Warning 373: Unable to route between blocks at (4,4) and (63,24) to characterize delay (setting to inf) +Warning 374: Unable to route between blocks at (4,4) and (63,25) to characterize delay (setting to inf) +Warning 375: Unable to route between blocks at (4,4) and (63,26) to characterize delay (setting to inf) +Warning 376: Unable to route between blocks at (4,4) and (63,27) to characterize delay (setting to inf) +Warning 377: Unable to route between blocks at (4,4) and (63,28) to characterize delay (setting to inf) +Warning 378: Unable to route between blocks at (4,4) and (63,29) to characterize delay (setting to inf) +Warning 379: Unable to route between blocks at (4,4) and (63,30) to characterize delay (setting to inf) +Warning 380: Unable to route between blocks at (4,4) and (63,31) to characterize delay (setting to inf) +Warning 381: Unable to route between blocks at (4,4) and (63,32) to characterize delay (setting to inf) +Warning 382: Unable to route between blocks at (4,4) and (63,33) to characterize delay (setting to inf) +Warning 383: Unable to route between blocks at (4,4) and (63,34) to characterize delay (setting to inf) +Warning 384: Unable to route between blocks at (4,4) and (63,35) to characterize delay (setting to inf) +Warning 385: Unable to route between blocks at (4,4) and (63,36) to characterize delay (setting to inf) +Warning 386: Unable to route between blocks at (4,4) and (63,37) to characterize delay (setting to inf) +Warning 387: Unable to route between blocks at (4,4) and (63,38) to characterize delay (setting to inf) +Warning 388: Unable to route between blocks at (4,4) and (63,39) to characterize delay (setting to inf) +Warning 389: Unable to route between blocks at (4,4) and (63,40) to characterize delay (setting to inf) +Warning 390: Unable to route between blocks at (4,4) and (63,41) to characterize delay (setting to inf) +Warning 391: Unable to route between blocks at (4,4) and (63,42) to characterize delay (setting to inf) +Warning 392: Unable to route between blocks at (4,4) and (63,43) to characterize delay (setting to inf) +Warning 393: Unable to route between blocks at (4,4) and (63,44) to characterize delay (setting to inf) +Warning 394: Unable to route between blocks at (4,4) and (63,45) to characterize delay (setting to inf) +Warning 395: Unable to route between blocks at (60,42) and (0,0) to characterize delay (setting to inf) +Warning 396: Unable to route between blocks at (60,42) and (0,1) to characterize delay (setting to inf) +Warning 397: Unable to route between blocks at (60,42) and (0,2) to characterize delay (setting to inf) +Warning 398: Unable to route between blocks at (60,42) and (0,3) to characterize delay (setting to inf) +Warning 399: Unable to route between blocks at (60,42) and (0,4) to characterize delay (setting to inf) +Warning 400: Unable to route between blocks at (60,42) and (0,5) to characterize delay (setting to inf) +Warning 401: Unable to route between blocks at (60,42) and (0,6) to characterize delay (setting to inf) +Warning 402: Unable to route between blocks at (60,42) and (0,7) to characterize delay (setting to inf) +Warning 403: Unable to route between blocks at (60,42) and (0,8) to characterize delay (setting to inf) +Warning 404: Unable to route between blocks at (60,42) and (0,9) to characterize delay (setting to inf) +Warning 405: Unable to route between blocks at (60,42) and (0,10) to characterize delay (setting to inf) +Warning 406: Unable to route between blocks at (60,42) and (0,11) to characterize delay (setting to inf) +Warning 407: Unable to route between blocks at (60,42) and (0,12) to characterize delay (setting to inf) +Warning 408: Unable to route between blocks at (60,42) and (0,13) to characterize delay (setting to inf) +Warning 409: Unable to route between blocks at (60,42) and (0,14) to characterize delay (setting to inf) +Warning 410: Unable to route between blocks at (60,42) and (0,15) to characterize delay (setting to inf) +Warning 411: Unable to route between blocks at (60,42) and (0,16) to characterize delay (setting to inf) +Warning 412: Unable to route between blocks at (60,42) and (0,17) to characterize delay (setting to inf) +Warning 413: Unable to route between blocks at (60,42) and (0,18) to characterize delay (setting to inf) +Warning 414: Unable to route between blocks at (60,42) and (0,19) to characterize delay (setting to inf) +Warning 415: Unable to route between blocks at (60,42) and (0,20) to characterize delay (setting to inf) +Warning 416: Unable to route between blocks at (60,42) and (0,21) to characterize delay (setting to inf) +Warning 417: Unable to route between blocks at (60,42) and (0,22) to characterize delay (setting to inf) +Warning 418: Unable to route between blocks at (60,42) and (0,23) to characterize delay (setting to inf) +Warning 419: Unable to route between blocks at (60,42) and (0,24) to characterize delay (setting to inf) +Warning 420: Unable to route between blocks at (60,42) and (0,25) to characterize delay (setting to inf) +Warning 421: Unable to route between blocks at (60,42) and (0,26) to characterize delay (setting to inf) +Warning 422: Unable to route between blocks at (60,42) and (0,27) to characterize delay (setting to inf) +Warning 423: Unable to route between blocks at (60,42) and (0,28) to characterize delay (setting to inf) +Warning 424: Unable to route between blocks at (60,42) and (0,29) to characterize delay (setting to inf) +Warning 425: Unable to route between blocks at (60,42) and (0,30) to characterize delay (setting to inf) +Warning 426: Unable to route between blocks at (60,42) and (0,31) to characterize delay (setting to inf) +Warning 427: Unable to route between blocks at (60,42) and (0,32) to characterize delay (setting to inf) +Warning 428: Unable to route between blocks at (60,42) and (0,33) to characterize delay (setting to inf) +Warning 429: Unable to route between blocks at (60,42) and (0,34) to characterize delay (setting to inf) +Warning 430: Unable to route between blocks at (60,42) and (0,35) to characterize delay (setting to inf) +Warning 431: Unable to route between blocks at (60,42) and (0,36) to characterize delay (setting to inf) +Warning 432: Unable to route between blocks at (60,42) and (0,37) to characterize delay (setting to inf) +Warning 433: Unable to route between blocks at (60,42) and (0,38) to characterize delay (setting to inf) +Warning 434: Unable to route between blocks at (60,42) and (0,39) to characterize delay (setting to inf) +Warning 435: Unable to route between blocks at (60,42) and (0,40) to characterize delay (setting to inf) +Warning 436: Unable to route between blocks at (60,42) and (0,41) to characterize delay (setting to inf) +Warning 437: Unable to route between blocks at (60,42) and (0,42) to characterize delay (setting to inf) +Warning 438: Unable to route between blocks at (60,42) and (1,0) to characterize delay (setting to inf) +Warning 439: Unable to route between blocks at (60,42) and (2,0) to characterize delay (setting to inf) +Warning 440: Unable to route between blocks at (60,42) and (3,0) to characterize delay (setting to inf) +Warning 441: Unable to route between blocks at (60,42) and (4,0) to characterize delay (setting to inf) +Warning 442: Unable to route between blocks at (60,42) and (5,0) to characterize delay (setting to inf) +Warning 443: Unable to route between blocks at (60,42) and (6,0) to characterize delay (setting to inf) +Warning 444: Unable to route between blocks at (60,42) and (7,0) to characterize delay (setting to inf) +Warning 445: Unable to route between blocks at (60,42) and (8,0) to characterize delay (setting to inf) +Warning 446: Unable to route between blocks at (60,42) and (9,0) to characterize delay (setting to inf) +Warning 447: Unable to route between blocks at (60,42) and (10,0) to characterize delay (setting to inf) +Warning 448: Unable to route between blocks at (60,42) and (11,0) to characterize delay (setting to inf) +Warning 449: Unable to route between blocks at (60,42) and (12,0) to characterize delay (setting to inf) +Warning 450: Unable to route between blocks at (60,42) and (13,0) to characterize delay (setting to inf) +Warning 451: Unable to route between blocks at (60,42) and (14,0) to characterize delay (setting to inf) +Warning 452: Unable to route between blocks at (60,42) and (15,0) to characterize delay (setting to inf) +Warning 453: Unable to route between blocks at (60,42) and (16,0) to characterize delay (setting to inf) +Warning 454: Unable to route between blocks at (60,42) and (17,0) to characterize delay (setting to inf) +Warning 455: Unable to route between blocks at (60,42) and (18,0) to characterize delay (setting to inf) +Warning 456: Unable to route between blocks at (60,42) and (19,0) to characterize delay (setting to inf) +Warning 457: Unable to route between blocks at (60,42) and (20,0) to characterize delay (setting to inf) +Warning 458: Unable to route between blocks at (60,42) and (21,0) to characterize delay (setting to inf) +Warning 459: Unable to route between blocks at (60,42) and (22,0) to characterize delay (setting to inf) +Warning 460: Unable to route between blocks at (60,42) and (23,0) to characterize delay (setting to inf) +Warning 461: Unable to route between blocks at (60,42) and (24,0) to characterize delay (setting to inf) +Warning 462: Unable to route between blocks at (60,42) and (25,0) to characterize delay (setting to inf) +Warning 463: Unable to route between blocks at (60,42) and (26,0) to characterize delay (setting to inf) +Warning 464: Unable to route between blocks at (60,42) and (27,0) to characterize delay (setting to inf) +Warning 465: Unable to route between blocks at (60,42) and (28,0) to characterize delay (setting to inf) +Warning 466: Unable to route between blocks at (60,42) and (29,0) to characterize delay (setting to inf) +Warning 467: Unable to route between blocks at (60,42) and (30,0) to characterize delay (setting to inf) +Warning 468: Unable to route between blocks at (60,42) and (31,0) to characterize delay (setting to inf) +Warning 469: Unable to route between blocks at (60,42) and (32,0) to characterize delay (setting to inf) +Warning 470: Unable to route between blocks at (60,42) and (33,0) to characterize delay (setting to inf) +Warning 471: Unable to route between blocks at (60,42) and (34,0) to characterize delay (setting to inf) +Warning 472: Unable to route between blocks at (60,42) and (35,0) to characterize delay (setting to inf) +Warning 473: Unable to route between blocks at (60,42) and (36,0) to characterize delay (setting to inf) +Warning 474: Unable to route between blocks at (60,42) and (37,0) to characterize delay (setting to inf) +Warning 475: Unable to route between blocks at (60,42) and (38,0) to characterize delay (setting to inf) +Warning 476: Unable to route between blocks at (60,42) and (39,0) to characterize delay (setting to inf) +Warning 477: Unable to route between blocks at (60,42) and (40,0) to characterize delay (setting to inf) +Warning 478: Unable to route between blocks at (60,42) and (41,0) to characterize delay (setting to inf) +Warning 479: Unable to route between blocks at (60,42) and (42,0) to characterize delay (setting to inf) +Warning 480: Unable to route between blocks at (60,42) and (43,0) to characterize delay (setting to inf) +Warning 481: Unable to route between blocks at (60,42) and (44,0) to characterize delay (setting to inf) +Warning 482: Unable to route between blocks at (60,42) and (45,0) to characterize delay (setting to inf) +Warning 483: Unable to route between blocks at (60,42) and (46,0) to characterize delay (setting to inf) +Warning 484: Unable to route between blocks at (60,42) and (47,0) to characterize delay (setting to inf) +Warning 485: Unable to route between blocks at (60,42) and (48,0) to characterize delay (setting to inf) +Warning 486: Unable to route between blocks at (60,42) and (49,0) to characterize delay (setting to inf) +Warning 487: Unable to route between blocks at (60,42) and (50,0) to characterize delay (setting to inf) +Warning 488: Unable to route between blocks at (60,42) and (51,0) to characterize delay (setting to inf) +Warning 489: Unable to route between blocks at (60,42) and (52,0) to characterize delay (setting to inf) +Warning 490: Unable to route between blocks at (60,42) and (53,0) to characterize delay (setting to inf) +Warning 491: Unable to route between blocks at (60,42) and (54,0) to characterize delay (setting to inf) +Warning 492: Unable to route between blocks at (60,42) and (55,0) to characterize delay (setting to inf) +Warning 493: Unable to route between blocks at (60,42) and (56,0) to characterize delay (setting to inf) +Warning 494: Unable to route between blocks at (60,42) and (57,0) to characterize delay (setting to inf) +Warning 495: Unable to route between blocks at (60,42) and (58,0) to characterize delay (setting to inf) +Warning 496: Unable to route between blocks at (60,42) and (59,0) to characterize delay (setting to inf) +Warning 497: Unable to route between blocks at (60,42) and (60,0) to characterize delay (setting to inf) +Warning 498: Unable to route between blocks at (60,4) and (0,4) to characterize delay (setting to inf) +Warning 499: Unable to route between blocks at (60,4) and (0,5) to characterize delay (setting to inf) +Warning 500: Unable to route between blocks at (60,4) and (0,6) to characterize delay (setting to inf) +Warning 501: Unable to route between blocks at (60,4) and (0,7) to characterize delay (setting to inf) +Warning 502: Unable to route between blocks at (60,4) and (0,8) to characterize delay (setting to inf) +Warning 503: Unable to route between blocks at (60,4) and (0,9) to characterize delay (setting to inf) +Warning 504: Unable to route between blocks at (60,4) and (0,10) to characterize delay (setting to inf) +Warning 505: Unable to route between blocks at (60,4) and (0,11) to characterize delay (setting to inf) +Warning 506: Unable to route between blocks at (60,4) and (0,12) to characterize delay (setting to inf) +Warning 507: Unable to route between blocks at (60,4) and (0,13) to characterize delay (setting to inf) +Warning 508: Unable to route between blocks at (60,4) and (0,14) to characterize delay (setting to inf) +Warning 509: Unable to route between blocks at (60,4) and (0,15) to characterize delay (setting to inf) +Warning 510: Unable to route between blocks at (60,4) and (0,16) to characterize delay (setting to inf) +Warning 511: Unable to route between blocks at (60,4) and (0,17) to characterize delay (setting to inf) +Warning 512: Unable to route between blocks at (60,4) and (0,18) to characterize delay (setting to inf) +Warning 513: Unable to route between blocks at (60,4) and (0,19) to characterize delay (setting to inf) +Warning 514: Unable to route between blocks at (60,4) and (0,20) to characterize delay (setting to inf) +Warning 515: Unable to route between blocks at (60,4) and (0,21) to characterize delay (setting to inf) +Warning 516: Unable to route between blocks at (60,4) and (0,22) to characterize delay (setting to inf) +Warning 517: Unable to route between blocks at (60,4) and (0,23) to characterize delay (setting to inf) +Warning 518: Unable to route between blocks at (60,4) and (0,24) to characterize delay (setting to inf) +Warning 519: Unable to route between blocks at (60,4) and (0,25) to characterize delay (setting to inf) +Warning 520: Unable to route between blocks at (60,4) and (0,26) to characterize delay (setting to inf) +Warning 521: Unable to route between blocks at (60,4) and (0,27) to characterize delay (setting to inf) +Warning 522: Unable to route between blocks at (60,4) and (0,28) to characterize delay (setting to inf) +Warning 523: Unable to route between blocks at (60,4) and (0,29) to characterize delay (setting to inf) +Warning 524: Unable to route between blocks at (60,4) and (0,30) to characterize delay (setting to inf) +Warning 525: Unable to route between blocks at (60,4) and (0,31) to characterize delay (setting to inf) +Warning 526: Unable to route between blocks at (60,4) and (0,32) to characterize delay (setting to inf) +Warning 527: Unable to route between blocks at (60,4) and (0,33) to characterize delay (setting to inf) +Warning 528: Unable to route between blocks at (60,4) and (0,34) to characterize delay (setting to inf) +Warning 529: Unable to route between blocks at (60,4) and (0,35) to characterize delay (setting to inf) +Warning 530: Unable to route between blocks at (60,4) and (0,36) to characterize delay (setting to inf) +Warning 531: Unable to route between blocks at (60,4) and (0,37) to characterize delay (setting to inf) +Warning 532: Unable to route between blocks at (60,4) and (0,38) to characterize delay (setting to inf) +Warning 533: Unable to route between blocks at (60,4) and (0,39) to characterize delay (setting to inf) +Warning 534: Unable to route between blocks at (60,4) and (0,40) to characterize delay (setting to inf) +Warning 535: Unable to route between blocks at (60,4) and (0,41) to characterize delay (setting to inf) +Warning 536: Unable to route between blocks at (60,4) and (0,42) to characterize delay (setting to inf) +Warning 537: Unable to route between blocks at (60,4) and (0,43) to characterize delay (setting to inf) +Warning 538: Unable to route between blocks at (60,4) and (0,44) to characterize delay (setting to inf) +Warning 539: Unable to route between blocks at (60,4) and (0,45) to characterize delay (setting to inf) +Warning 540: Unable to route between blocks at (60,4) and (1,45) to characterize delay (setting to inf) +Warning 541: Unable to route between blocks at (60,4) and (2,45) to characterize delay (setting to inf) +Warning 542: Unable to route between blocks at (60,4) and (3,45) to characterize delay (setting to inf) +Warning 543: Unable to route between blocks at (60,4) and (4,45) to characterize delay (setting to inf) +Warning 544: Unable to route between blocks at (60,4) and (5,45) to characterize delay (setting to inf) +Warning 545: Unable to route between blocks at (60,4) and (6,45) to characterize delay (setting to inf) +Warning 546: Unable to route between blocks at (60,4) and (7,45) to characterize delay (setting to inf) +Warning 547: Unable to route between blocks at (60,4) and (8,45) to characterize delay (setting to inf) +Warning 548: Unable to route between blocks at (60,4) and (9,45) to characterize delay (setting to inf) +Warning 549: Unable to route between blocks at (60,4) and (10,45) to characterize delay (setting to inf) +Warning 550: Unable to route between blocks at (60,4) and (11,45) to characterize delay (setting to inf) +Warning 551: Unable to route between blocks at (60,4) and (12,45) to characterize delay (setting to inf) +Warning 552: Unable to route between blocks at (60,4) and (13,45) to characterize delay (setting to inf) +Warning 553: Unable to route between blocks at (60,4) and (14,45) to characterize delay (setting to inf) +Warning 554: Unable to route between blocks at (60,4) and (15,45) to characterize delay (setting to inf) +Warning 555: Unable to route between blocks at (60,4) and (16,45) to characterize delay (setting to inf) +Warning 556: Unable to route between blocks at (60,4) and (17,45) to characterize delay (setting to inf) +Warning 557: Unable to route between blocks at (60,4) and (18,45) to characterize delay (setting to inf) +Warning 558: Unable to route between blocks at (60,4) and (19,45) to characterize delay (setting to inf) +Warning 559: Unable to route between blocks at (60,4) and (20,45) to characterize delay (setting to inf) +Warning 560: Unable to route between blocks at (60,4) and (21,45) to characterize delay (setting to inf) +Warning 561: Unable to route between blocks at (60,4) and (22,45) to characterize delay (setting to inf) +Warning 562: Unable to route between blocks at (60,4) and (23,45) to characterize delay (setting to inf) +Warning 563: Unable to route between blocks at (60,4) and (24,45) to characterize delay (setting to inf) +Warning 564: Unable to route between blocks at (60,4) and (25,45) to characterize delay (setting to inf) +Warning 565: Unable to route between blocks at (60,4) and (26,45) to characterize delay (setting to inf) +Warning 566: Unable to route between blocks at (60,4) and (27,45) to characterize delay (setting to inf) +Warning 567: Unable to route between blocks at (60,4) and (28,45) to characterize delay (setting to inf) +Warning 568: Unable to route between blocks at (60,4) and (29,45) to characterize delay (setting to inf) +Warning 569: Unable to route between blocks at (60,4) and (30,45) to characterize delay (setting to inf) +Warning 570: Unable to route between blocks at (60,4) and (31,45) to characterize delay (setting to inf) +Warning 571: Unable to route between blocks at (60,4) and (32,45) to characterize delay (setting to inf) +Warning 572: Unable to route between blocks at (60,4) and (33,45) to characterize delay (setting to inf) +Warning 573: Unable to route between blocks at (60,4) and (34,45) to characterize delay (setting to inf) +Warning 574: Unable to route between blocks at (60,4) and (35,45) to characterize delay (setting to inf) +Warning 575: Unable to route between blocks at (60,4) and (36,45) to characterize delay (setting to inf) +Warning 576: Unable to route between blocks at (60,4) and (37,45) to characterize delay (setting to inf) +Warning 577: Unable to route between blocks at (60,4) and (38,45) to characterize delay (setting to inf) +Warning 578: Unable to route between blocks at (60,4) and (39,45) to characterize delay (setting to inf) +Warning 579: Unable to route between blocks at (60,4) and (40,45) to characterize delay (setting to inf) +Warning 580: Unable to route between blocks at (60,4) and (41,45) to characterize delay (setting to inf) +Warning 581: Unable to route between blocks at (60,4) and (42,45) to characterize delay (setting to inf) +Warning 582: Unable to route between blocks at (60,4) and (43,45) to characterize delay (setting to inf) +Warning 583: Unable to route between blocks at (60,4) and (44,45) to characterize delay (setting to inf) +Warning 584: Unable to route between blocks at (60,4) and (45,45) to characterize delay (setting to inf) +Warning 585: Unable to route between blocks at (60,4) and (46,45) to characterize delay (setting to inf) +Warning 586: Unable to route between blocks at (60,4) and (47,45) to characterize delay (setting to inf) +Warning 587: Unable to route between blocks at (60,4) and (48,45) to characterize delay (setting to inf) +Warning 588: Unable to route between blocks at (60,4) and (49,45) to characterize delay (setting to inf) +Warning 589: Unable to route between blocks at (60,4) and (50,45) to characterize delay (setting to inf) +Warning 590: Unable to route between blocks at (60,4) and (51,45) to characterize delay (setting to inf) +Warning 591: Unable to route between blocks at (60,4) and (52,45) to characterize delay (setting to inf) +Warning 592: Unable to route between blocks at (60,4) and (53,45) to characterize delay (setting to inf) +Warning 593: Unable to route between blocks at (60,4) and (54,45) to characterize delay (setting to inf) +Warning 594: Unable to route between blocks at (60,4) and (55,45) to characterize delay (setting to inf) +Warning 595: Unable to route between blocks at (60,4) and (56,45) to characterize delay (setting to inf) +Warning 596: Unable to route between blocks at (60,4) and (57,45) to characterize delay (setting to inf) +Warning 597: Unable to route between blocks at (60,4) and (58,45) to characterize delay (setting to inf) +Warning 598: Unable to route between blocks at (60,4) and (59,45) to characterize delay (setting to inf) +Warning 599: Unable to route between blocks at (60,4) and (60,45) to characterize delay (setting to inf) +Warning 600: Unable to route between blocks at (4,42) and (4,0) to characterize delay (setting to inf) +Warning 601: Unable to route between blocks at (4,42) and (5,0) to characterize delay (setting to inf) +Warning 602: Unable to route between blocks at (4,42) and (6,0) to characterize delay (setting to inf) +Warning 603: Unable to route between blocks at (4,42) and (7,0) to characterize delay (setting to inf) +Warning 604: Unable to route between blocks at (4,42) and (8,0) to characterize delay (setting to inf) +Warning 605: Unable to route between blocks at (4,42) and (9,0) to characterize delay (setting to inf) +Warning 606: Unable to route between blocks at (4,42) and (10,0) to characterize delay (setting to inf) +Warning 607: Unable to route between blocks at (4,42) and (11,0) to characterize delay (setting to inf) +Warning 608: Unable to route between blocks at (4,42) and (12,0) to characterize delay (setting to inf) +Warning 609: Unable to route between blocks at (4,42) and (13,0) to characterize delay (setting to inf) +Warning 610: Unable to route between blocks at (4,42) and (14,0) to characterize delay (setting to inf) +Warning 611: Unable to route between blocks at (4,42) and (15,0) to characterize delay (setting to inf) +Warning 612: Unable to route between blocks at (4,42) and (16,0) to characterize delay (setting to inf) +Warning 613: Unable to route between blocks at (4,42) and (17,0) to characterize delay (setting to inf) +Warning 614: Unable to route between blocks at (4,42) and (18,0) to characterize delay (setting to inf) +Warning 615: Unable to route between blocks at (4,42) and (19,0) to characterize delay (setting to inf) +Warning 616: Unable to route between blocks at (4,42) and (20,0) to characterize delay (setting to inf) +Warning 617: Unable to route between blocks at (4,42) and (21,0) to characterize delay (setting to inf) +Warning 618: Unable to route between blocks at (4,42) and (22,0) to characterize delay (setting to inf) +Warning 619: Unable to route between blocks at (4,42) and (23,0) to characterize delay (setting to inf) +Warning 620: Unable to route between blocks at (4,42) and (24,0) to characterize delay (setting to inf) +Warning 621: Unable to route between blocks at (4,42) and (25,0) to characterize delay (setting to inf) +Warning 622: Unable to route between blocks at (4,42) and (26,0) to characterize delay (setting to inf) +Warning 623: Unable to route between blocks at (4,42) and (27,0) to characterize delay (setting to inf) +Warning 624: Unable to route between blocks at (4,42) and (28,0) to characterize delay (setting to inf) +Warning 625: Unable to route between blocks at (4,42) and (29,0) to characterize delay (setting to inf) +Warning 626: Unable to route between blocks at (4,42) and (30,0) to characterize delay (setting to inf) +Warning 627: Unable to route between blocks at (4,42) and (31,0) to characterize delay (setting to inf) +Warning 628: Unable to route between blocks at (4,42) and (32,0) to characterize delay (setting to inf) +Warning 629: Unable to route between blocks at (4,42) and (33,0) to characterize delay (setting to inf) +Warning 630: Unable to route between blocks at (4,42) and (34,0) to characterize delay (setting to inf) +Warning 631: Unable to route between blocks at (4,42) and (35,0) to characterize delay (setting to inf) +Warning 632: Unable to route between blocks at (4,42) and (36,0) to characterize delay (setting to inf) +Warning 633: Unable to route between blocks at (4,42) and (37,0) to characterize delay (setting to inf) +Warning 634: Unable to route between blocks at (4,42) and (38,0) to characterize delay (setting to inf) +Warning 635: Unable to route between blocks at (4,42) and (39,0) to characterize delay (setting to inf) +Warning 636: Unable to route between blocks at (4,42) and (40,0) to characterize delay (setting to inf) +Warning 637: Unable to route between blocks at (4,42) and (41,0) to characterize delay (setting to inf) +Warning 638: Unable to route between blocks at (4,42) and (42,0) to characterize delay (setting to inf) +Warning 639: Unable to route between blocks at (4,42) and (43,0) to characterize delay (setting to inf) +Warning 640: Unable to route between blocks at (4,42) and (44,0) to characterize delay (setting to inf) +Warning 641: Unable to route between blocks at (4,42) and (45,0) to characterize delay (setting to inf) +Warning 642: Unable to route between blocks at (4,42) and (46,0) to characterize delay (setting to inf) +Warning 643: Unable to route between blocks at (4,42) and (47,0) to characterize delay (setting to inf) +Warning 644: Unable to route between blocks at (4,42) and (48,0) to characterize delay (setting to inf) +Warning 645: Unable to route between blocks at (4,42) and (49,0) to characterize delay (setting to inf) +Warning 646: Unable to route between blocks at (4,42) and (50,0) to characterize delay (setting to inf) +Warning 647: Unable to route between blocks at (4,42) and (51,0) to characterize delay (setting to inf) +Warning 648: Unable to route between blocks at (4,42) and (52,0) to characterize delay (setting to inf) +Warning 649: Unable to route between blocks at (4,42) and (53,0) to characterize delay (setting to inf) +Warning 650: Unable to route between blocks at (4,42) and (54,0) to characterize delay (setting to inf) +Warning 651: Unable to route between blocks at (4,42) and (55,0) to characterize delay (setting to inf) +Warning 652: Unable to route between blocks at (4,42) and (56,0) to characterize delay (setting to inf) +Warning 653: Unable to route between blocks at (4,42) and (57,0) to characterize delay (setting to inf) +Warning 654: Unable to route between blocks at (4,42) and (58,0) to characterize delay (setting to inf) +Warning 655: Unable to route between blocks at (4,42) and (59,0) to characterize delay (setting to inf) +Warning 656: Unable to route between blocks at (4,42) and (60,0) to characterize delay (setting to inf) +Warning 657: Unable to route between blocks at (4,42) and (61,0) to characterize delay (setting to inf) +Warning 658: Unable to route between blocks at (4,42) and (62,0) to characterize delay (setting to inf) +Warning 659: Unable to route between blocks at (4,42) and (63,0) to characterize delay (setting to inf) +Warning 660: Unable to route between blocks at (4,42) and (63,1) to characterize delay (setting to inf) +Warning 661: Unable to route between blocks at (4,42) and (63,2) to characterize delay (setting to inf) +Warning 662: Unable to route between blocks at (4,42) and (63,3) to characterize delay (setting to inf) +Warning 663: Unable to route between blocks at (4,42) and (63,4) to characterize delay (setting to inf) +Warning 664: Unable to route between blocks at (4,42) and (63,5) to characterize delay (setting to inf) +Warning 665: Unable to route between blocks at (4,42) and (63,6) to characterize delay (setting to inf) +Warning 666: Unable to route between blocks at (4,42) and (63,7) to characterize delay (setting to inf) +Warning 667: Unable to route between blocks at (4,42) and (63,8) to characterize delay (setting to inf) +Warning 668: Unable to route between blocks at (4,42) and (63,9) to characterize delay (setting to inf) +Warning 669: Unable to route between blocks at (4,42) and (63,10) to characterize delay (setting to inf) +Warning 670: Unable to route between blocks at (4,42) and (63,11) to characterize delay (setting to inf) +Warning 671: Unable to route between blocks at (4,42) and (63,12) to characterize delay (setting to inf) +Warning 672: Unable to route between blocks at (4,42) and (63,13) to characterize delay (setting to inf) +Warning 673: Unable to route between blocks at (4,42) and (63,14) to characterize delay (setting to inf) +Warning 674: Unable to route between blocks at (4,42) and (63,15) to characterize delay (setting to inf) +Warning 675: Unable to route between blocks at (4,42) and (63,16) to characterize delay (setting to inf) +Warning 676: Unable to route between blocks at (4,42) and (63,17) to characterize delay (setting to inf) +Warning 677: Unable to route between blocks at (4,42) and (63,18) to characterize delay (setting to inf) +Warning 678: Unable to route between blocks at (4,42) and (63,19) to characterize delay (setting to inf) +Warning 679: Unable to route between blocks at (4,42) and (63,20) to characterize delay (setting to inf) +Warning 680: Unable to route between blocks at (4,42) and (63,21) to characterize delay (setting to inf) +Warning 681: Unable to route between blocks at (4,42) and (63,22) to characterize delay (setting to inf) +Warning 682: Unable to route between blocks at (4,42) and (63,23) to characterize delay (setting to inf) +Warning 683: Unable to route between blocks at (4,42) and (63,24) to characterize delay (setting to inf) +Warning 684: Unable to route between blocks at (4,42) and (63,25) to characterize delay (setting to inf) +Warning 685: Unable to route between blocks at (4,42) and (63,26) to characterize delay (setting to inf) +Warning 686: Unable to route between blocks at (4,42) and (63,27) to characterize delay (setting to inf) +Warning 687: Unable to route between blocks at (4,42) and (63,28) to characterize delay (setting to inf) +Warning 688: Unable to route between blocks at (4,42) and (63,29) to characterize delay (setting to inf) +Warning 689: Unable to route between blocks at (4,42) and (63,30) to characterize delay (setting to inf) +Warning 690: Unable to route between blocks at (4,42) and (63,31) to characterize delay (setting to inf) +Warning 691: Unable to route between blocks at (4,42) and (63,32) to characterize delay (setting to inf) +Warning 692: Unable to route between blocks at (4,42) and (63,33) to characterize delay (setting to inf) +Warning 693: Unable to route between blocks at (4,42) and (63,34) to characterize delay (setting to inf) +Warning 694: Unable to route between blocks at (4,42) and (63,35) to characterize delay (setting to inf) +Warning 695: Unable to route between blocks at (4,42) and (63,36) to characterize delay (setting to inf) +Warning 696: Unable to route between blocks at (4,42) and (63,37) to characterize delay (setting to inf) +Warning 697: Unable to route between blocks at (4,42) and (63,38) to characterize delay (setting to inf) +Warning 698: Unable to route between blocks at (4,42) and (63,39) to characterize delay (setting to inf) +Warning 699: Unable to route between blocks at (4,42) and (63,40) to characterize delay (setting to inf) +Warning 700: Unable to route between blocks at (4,42) and (63,41) to characterize delay (setting to inf) +Warning 701: Unable to route between blocks at (4,42) and (63,42) to characterize delay (setting to inf) +## Computing delta delays took 39.55 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +# Computing placement delta delay look-up took 39.58 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) + +Bounding box mode is Cube + +# Placement +## Initial Placement +Reading I_DELAY_primitive_inst_pin_loc.place. + +## Initial Placement took 0.00 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +# Placement took 0.00 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +Error 1: +Type: Placement +File: /nfs_eda_sw/softwares/Raptor/orgnl/Raptor/Backend/OpenFPGA/vtr-verilog-to-routing/vpr/src/base/read_place.cpp +Line: 294 +Message: The location of cluster $obuf_O (#38) is specified 2 times in the constraints file with conflicting locations. +Its location was last specified with block $obuf_O. + +The entire flow of VPR took 83.72 seconds (max_rss 472.8 MiB) diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/I_DELAY_primitive_inst.ys b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/I_DELAY_primitive_inst.ys new file mode 100644 index 00000000..94867517 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/I_DELAY_primitive_inst.ys @@ -0,0 +1,26 @@ + +# Yosys synthesis script for I_DELAY_primitive_inst +# Read source files +read_verilog -sv /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog -I../../../.././rtl -I../../../../ -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v + + +# Technology mapping +hierarchy -top I_DELAY_primitive_inst + + + +plugin -i synth-rs + +synth_rs -post_cleanup 1 -legalize_ram_clk_ports -new_iobuf_map 3 -iofab_map 1 -tech genesis3 -de -goal delay -effort high -carry auto -keep_tribuf -new_dsp19x2 -new_tdp36k -max_lut 17472 -max_reg 34944 -max_device_dsp 56 -max_device_bram 56 -max_device_carry_length 336 -max_dsp 56 -max_bram 56 -max_carry_length 336 -fsm_encoding onehot -de_max_threads -1 + +write_verilog -noexpr -nodec -norename -v I_DELAY_primitive_inst_post_synth.v +write_blif -param I_DELAY_primitive_inst_post_synth.eblif + +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_location_I_DELAY_primitive_inst.sdc -json config.json -w wrapper_I_DELAY_primitive_inst_post_synth.v wrapper_I_DELAY_primitive_inst_post_synth.eblif -pr post_pnr_wrapper_I_DELAY_primitive_inst_post_synth.v post_pnr_wrapper_I_DELAY_primitive_inst_post_synth.eblif +write_verilog -noexpr -nodec -norename -v fabric_I_DELAY_primitive_inst_post_synth.v +write_blif -param fabric_I_DELAY_primitive_inst_post_synth.eblif + + \ No newline at end of file diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/I_DELAY_primitive_inst_post_synth.eblif b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/I_DELAY_primitive_inst_post_synth.eblif new file mode 100644 index 00000000..f317ca41 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/I_DELAY_primitive_inst_post_synth.eblif @@ -0,0 +1,50 @@ +# Generated by Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) + +.model I_DELAY_primitive_inst +.inputs reset in DLY_LOAD DLY_ADJ DLY_INCDEC CLK_IN +.outputs DLY_TAP_VALUE[0] DLY_TAP_VALUE[1] DLY_TAP_VALUE[2] DLY_TAP_VALUE[3] DLY_TAP_VALUE[4] DLY_TAP_VALUE[5] O +.names $false +.names $true +1 +.names $undef +.subckt DFFRE C=$clk_buf_$ibuf_CLK_IN D=$abc$192$li0_li0 E=$true Q=dff R=$true +.subckt LUT2 A[0]=$ibuf_reset A[1]=$ibuf_in Y=$abc$192$li0_li0 +.param INIT_VALUE 0100 +.subckt CLK_BUF I=$ibuf_CLK_IN O=$clk_buf_$ibuf_CLK_IN +.subckt O_FAB I=$ibuf_DLY_ADJ O=$f2g_trx_dly_adj_$ibuf_DLY_ADJ +.subckt O_FAB I=$ibuf_DLY_INCDEC O=$f2g_trx_dly_inc_$ibuf_DLY_INCDEC +.subckt O_FAB I=$ibuf_DLY_LOAD O=$f2g_trx_dly_ld_$ibuf_DLY_LOAD +.subckt O_FAB I=$obuf_DLY_TAP_VALUE[0] O=$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] +.subckt O_FAB I=$obuf_DLY_TAP_VALUE[1] O=$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] +.subckt O_FAB I=$obuf_DLY_TAP_VALUE[2] O=$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] +.subckt O_FAB I=$obuf_DLY_TAP_VALUE[3] O=$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] +.subckt O_FAB I=$obuf_DLY_TAP_VALUE[4] O=$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] +.subckt O_FAB I=$obuf_DLY_TAP_VALUE[5] O=$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] +.subckt I_BUF EN=$true I=CLK_IN O=$ibuf_CLK_IN +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$true I=DLY_ADJ O=$ibuf_DLY_ADJ +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$true I=DLY_INCDEC O=$ibuf_DLY_INCDEC +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$true I=DLY_LOAD O=$ibuf_DLY_LOAD +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$true I=in O=$ibuf_in +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$true I=reset O=$ibuf_reset +.param WEAK_KEEPER "NONE" +.subckt I_FAB I=$ifab_$obuf_DLY_TAP_VALUE[0] O=$obuf_DLY_TAP_VALUE[0] +.subckt I_FAB I=$ifab_$obuf_DLY_TAP_VALUE[1] O=$obuf_DLY_TAP_VALUE[1] +.subckt I_FAB I=$ifab_$obuf_DLY_TAP_VALUE[2] O=$obuf_DLY_TAP_VALUE[2] +.subckt I_FAB I=$ifab_$obuf_DLY_TAP_VALUE[3] O=$obuf_DLY_TAP_VALUE[3] +.subckt I_FAB I=$ifab_$obuf_DLY_TAP_VALUE[4] O=$obuf_DLY_TAP_VALUE[4] +.subckt I_FAB I=$ifab_$obuf_DLY_TAP_VALUE[5] O=$obuf_DLY_TAP_VALUE[5] +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] O=DLY_TAP_VALUE[0] T=$true +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] O=DLY_TAP_VALUE[1] T=$true +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] O=DLY_TAP_VALUE[2] T=$true +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] O=DLY_TAP_VALUE[3] T=$true +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] O=DLY_TAP_VALUE[4] T=$true +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] O=DLY_TAP_VALUE[5] T=$true +.subckt O_BUFT I=$obuf_O O=O T=$true +.subckt I_DELAY CLK_IN=$clk_buf_$ibuf_CLK_IN DLY_ADJ=$f2g_trx_dly_adj_$ibuf_DLY_ADJ DLY_INCDEC=$f2g_trx_dly_inc_$ibuf_DLY_INCDEC DLY_LOAD=$f2g_trx_dly_ld_$ibuf_DLY_LOAD DLY_TAP_VALUE[0]=$ifab_$obuf_DLY_TAP_VALUE[0] DLY_TAP_VALUE[1]=$ifab_$obuf_DLY_TAP_VALUE[1] DLY_TAP_VALUE[2]=$ifab_$obuf_DLY_TAP_VALUE[2] DLY_TAP_VALUE[3]=$ifab_$obuf_DLY_TAP_VALUE[3] DLY_TAP_VALUE[4]=$ifab_$obuf_DLY_TAP_VALUE[4] DLY_TAP_VALUE[5]=$ifab_$obuf_DLY_TAP_VALUE[5] I=dff O=$obuf_O +.param DELAY 00000000000000000000000000000000 +.end diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/I_DELAY_primitive_inst_post_synth.v b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/I_DELAY_primitive_inst_post_synth.v new file mode 100644 index 00000000..c53dcb5f --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/I_DELAY_primitive_inst_post_synth.v @@ -0,0 +1,324 @@ +/* Generated by Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) */ + +module I_DELAY_primitive_inst(reset, in, DLY_LOAD, DLY_ADJ, DLY_INCDEC, DLY_TAP_VALUE, CLK_IN, O); + input CLK_IN; + input DLY_ADJ; + input DLY_INCDEC; + input DLY_LOAD; + output [5:0] DLY_TAP_VALUE; + output O; + input in; + input reset; + wire \$abc$192$li0_li0 ; + wire \$clk_buf_$ibuf_CLK_IN ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire \$f2g_trx_dly_adj_$ibuf_DLY_ADJ ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire \$f2g_trx_dly_inc_$ibuf_DLY_INCDEC ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire \$f2g_trx_dly_ld_$ibuf_DLY_LOAD ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" *) + wire \$ibuf_CLK_IN ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire \$ibuf_DLY_ADJ ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire \$ibuf_DLY_INCDEC ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire \$ibuf_DLY_LOAD ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + wire \$ibuf_in ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + wire \$ibuf_reset ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[4] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[5] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$obuf_DLY_TAP_VALUE[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$obuf_DLY_TAP_VALUE[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$obuf_DLY_TAP_VALUE[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$obuf_DLY_TAP_VALUE[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$obuf_DLY_TAP_VALUE[4] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$obuf_DLY_TAP_VALUE[5] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + wire \$obuf_O ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" *) + wire CLK_IN; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire DLY_ADJ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire DLY_INCDEC; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire DLY_LOAD; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire [5:0] DLY_TAP_VALUE; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + wire O; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:14.5-14.8" *) + wire dff; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + wire in; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + wire reset; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) + DFFRE \$abc$192$auto_193 ( + .C(\$clk_buf_$ibuf_CLK_IN ), + .D(\$abc$192$li0_li0 ), + .E(1'h1), + .Q(dff), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h4) + ) \$abc$424$auto_425 ( + .A({ \$ibuf_in , \$ibuf_reset }), + .Y(\$abc$192$li0_li0 ) + ); + (* keep = 32'sh00000001 *) + CLK_BUF \$clkbuf$I_DELAY_primitive_inst.$ibuf_CLK_IN ( + .I(\$ibuf_CLK_IN ), + .O(\$clk_buf_$ibuf_CLK_IN ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_adj_$ibuf_DLY_ADJ_1 ( + .I(\$ibuf_DLY_ADJ ), + .O(\$f2g_trx_dly_adj_$ibuf_DLY_ADJ ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_inc_$ibuf_DLY_INCDEC_1 ( + .I(\$ibuf_DLY_INCDEC ), + .O(\$f2g_trx_dly_inc_$ibuf_DLY_INCDEC ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_ld_$ibuf_DLY_LOAD_1 ( + .I(\$ibuf_DLY_LOAD ), + .O(\$f2g_trx_dly_ld_$ibuf_DLY_LOAD ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_$obuf_DLY_TAP_VALUE[0]_1 ( + .I(\$obuf_DLY_TAP_VALUE[0] ), + .O(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_$obuf_DLY_TAP_VALUE[1]_1 ( + .I(\$obuf_DLY_TAP_VALUE[1] ), + .O(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_$obuf_DLY_TAP_VALUE[2]_1 ( + .I(\$obuf_DLY_TAP_VALUE[2] ), + .O(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_$obuf_DLY_TAP_VALUE[3]_1 ( + .I(\$obuf_DLY_TAP_VALUE[3] ), + .O(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_$obuf_DLY_TAP_VALUE[4]_1 ( + .I(\$obuf_DLY_TAP_VALUE[4] ), + .O(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_$obuf_DLY_TAP_VALUE[5]_1 ( + .I(\$obuf_DLY_TAP_VALUE[5] ), + .O(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$I_DELAY_primitive_inst.$ibuf_CLK_IN ( + .EN(1'h1), + .I(CLK_IN), + .O(\$ibuf_CLK_IN ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_ADJ ( + .EN(1'h1), + .I(DLY_ADJ), + .O(\$ibuf_DLY_ADJ ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_INCDEC ( + .EN(1'h1), + .I(DLY_INCDEC), + .O(\$ibuf_DLY_INCDEC ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_LOAD ( + .EN(1'h1), + .I(DLY_LOAD), + .O(\$ibuf_DLY_LOAD ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$I_DELAY_primitive_inst.$ibuf_in ( + .EN(1'h1), + .I(in), + .O(\$ibuf_in ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$I_DELAY_primitive_inst.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(\$ibuf_reset ) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_$obuf_DLY_TAP_VALUE[0]_1 ( + .I(\$ifab_$obuf_DLY_TAP_VALUE[0] ), + .O(\$obuf_DLY_TAP_VALUE[0] ) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_$obuf_DLY_TAP_VALUE[1]_1 ( + .I(\$ifab_$obuf_DLY_TAP_VALUE[1] ), + .O(\$obuf_DLY_TAP_VALUE[1] ) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_$obuf_DLY_TAP_VALUE[2]_1 ( + .I(\$ifab_$obuf_DLY_TAP_VALUE[2] ), + .O(\$obuf_DLY_TAP_VALUE[2] ) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_$obuf_DLY_TAP_VALUE[3]_1 ( + .I(\$ifab_$obuf_DLY_TAP_VALUE[3] ), + .O(\$obuf_DLY_TAP_VALUE[3] ) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_$obuf_DLY_TAP_VALUE[4]_1 ( + .I(\$ifab_$obuf_DLY_TAP_VALUE[4] ), + .O(\$obuf_DLY_TAP_VALUE[4] ) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_$obuf_DLY_TAP_VALUE[5]_1 ( + .I(\$ifab_$obuf_DLY_TAP_VALUE[5] ), + .O(\$obuf_DLY_TAP_VALUE[5] ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] ), + .O(DLY_TAP_VALUE[0]), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_1 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] ), + .O(DLY_TAP_VALUE[1]), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_2 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] ), + .O(DLY_TAP_VALUE[2]), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_3 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] ), + .O(DLY_TAP_VALUE[3]), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_4 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] ), + .O(DLY_TAP_VALUE[4]), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_5 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] ), + .O(DLY_TAP_VALUE[5]), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$I_DELAY_primitive_inst.$obuf_O ( + .I(\$obuf_O ), + .O(O), + .T(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:18.3-26.2" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) inst ( + .CLK_IN(\$clk_buf_$ibuf_CLK_IN ), + .DLY_ADJ(\$f2g_trx_dly_adj_$ibuf_DLY_ADJ ), + .DLY_INCDEC(\$f2g_trx_dly_inc_$ibuf_DLY_INCDEC ), + .DLY_LOAD(\$f2g_trx_dly_ld_$ibuf_DLY_LOAD ), + .DLY_TAP_VALUE({ \$ifab_$obuf_DLY_TAP_VALUE[5] , \$ifab_$obuf_DLY_TAP_VALUE[4] , \$ifab_$obuf_DLY_TAP_VALUE[3] , \$ifab_$obuf_DLY_TAP_VALUE[2] , \$ifab_$obuf_DLY_TAP_VALUE[1] , \$ifab_$obuf_DLY_TAP_VALUE[0] }), + .I(dff), + .O(\$obuf_O ) + ); +endmodule diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/I_DELAY_primitive_inst_synth.log b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/I_DELAY_primitive_inst_synth.log new file mode 100644 index 00000000..2515ec61 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/I_DELAY_primitive_inst_synth.log @@ -0,0 +1,2306 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) + + +-- Executing script file `I_DELAY_primitive_inst.ys' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v' to AST representation. +Generating RTLIL representation for module `\I_DELAY_primitive_inst'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst + +3.2. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst +Removed 0 unused modules. + +4. Executing synth_rs pass: v0.4.218 + +4.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\inv'. +Generating RTLIL representation for module `\buff'. +Generating RTLIL representation for module `\logic_0'. +Generating RTLIL representation for module `\logic_1'. +Generating RTLIL representation for module `\gclkbuff'. +Successfully finished Verilog frontend. + +4.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v' to AST representation. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v:10.1-33.10. +Generating RTLIL representation for module `\CARRY'. +Successfully finished Verilog frontend. + +4.3. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v' to AST representation. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:20.1-34.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:48.1-62.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:81.1-97.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:115.1-131.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:150.1-166.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:184.1-200.10. +Generating RTLIL representation for module `\LATCHNS'. +Generating RTLIL representation for module `\LATCHSRE'. +Generating RTLIL representation for module `\LATCHNSRE'. +Successfully finished Verilog frontend. + +4.4. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v' to AST representation. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:11.1-81.10. +Generating RTLIL representation for module `\DFFRE'. +Successfully finished Verilog frontend. + +4.5. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v' to AST representation. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:11.1-80.10. +Generating RTLIL representation for module `\DFFNRE'. +Successfully finished Verilog frontend. + +4.6. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v' to AST representation. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v:10.1-20.10. +Generating RTLIL representation for module `\LUT1'. +Successfully finished Verilog frontend. + +4.7. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v' to AST representation. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v:10.1-21.10. +Generating RTLIL representation for module `\LUT2'. +Successfully finished Verilog frontend. + +4.8. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v' to AST representation. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v:10.1-22.10. +Generating RTLIL representation for module `\LUT3'. +Successfully finished Verilog frontend. + +4.9. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v' to AST representation. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v:11.1-25.10. +Generating RTLIL representation for module `\LUT4'. +Successfully finished Verilog frontend. + +4.10. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v' to AST representation. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v:10.1-24.10. +Generating RTLIL representation for module `\LUT5'. +Successfully finished Verilog frontend. + +4.11. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v' to AST representation. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v:10.1-25.10. +Generating RTLIL representation for module `\LUT6'. +Successfully finished Verilog frontend. + +4.12. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v' to AST representation. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v:10.1-25.10. +Generating RTLIL representation for module `\CLK_BUF'. +Successfully finished Verilog frontend. + +4.13. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v' to AST representation. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v:10.1-84.10. +Generating RTLIL representation for module `\O_BUF'. +Successfully finished Verilog frontend. + +4.14. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v' to AST representation. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v:10.1-341.10. +Generating RTLIL representation for module `\DSP38'. +Successfully finished Verilog frontend. + +4.15. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v' to AST representation. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:2.1-29.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:33.1-84.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\RS_DSP3'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:116.1-149.10. +Generating RTLIL representation for module `\DSP19X2'. +Successfully finished Verilog frontend. + +4.16. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v' to AST representation. +Generating RTLIL representation for module `\TDP_BRAM18'. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Generating RTLIL representation for module `\_$_mem_v2_asymmetric'. +Successfully finished Verilog frontend. + +4.17. Executing HIERARCHY pass (managing design hierarchy). + +4.17.1. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst + +4.17.2. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst +Removed 0 unused modules. + +4.18. Executing PROC pass (convert processes to netlists). + +4.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1 in module I_DELAY_primitive_inst. +Removed a total of 0 dead cases. + +4.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 1 redundant assignment. +Promoted 0 assignments to connections. + +4.18.4. Executing PROC_INIT pass (extract init attributes). + +4.18.5. Executing PROC_ARST pass (detect async resets in processes). + +4.18.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +4.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\I_DELAY_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1'. + 1/1: $0\dff[0:0] + +4.18.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +4.18.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\I_DELAY_primitive_inst.\dff' using process `\I_DELAY_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1'. + created $dff cell `$procdff$5' with positive edge clock. + +4.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\I_DELAY_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1'. +Removing empty process `I_DELAY_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1'. +Cleaned up 1 empty switch. + +4.18.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.19. Executing FLATTEN pass (flatten design). + +# -------------------- +# Design entry stats +# -------------------- + +4.20. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 12 + Number of wire bits: 17 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + $mux 1 + I_DELAY 1 + +4.21. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.22. Executing DEMUXMAP pass. + +4.23. Executing FLATTEN pass (flatten design). + +4.24. Executing DEMUXMAP pass. + +4.25. Executing TRIBUF pass. +Warning: Ignored -no_iobuf because -keep_tribuf is used. + +4.26. Executing DEMINOUT pass (demote inout ports to input or output). + +4.27. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 2 unused wires. + + +4.29. Executing CHECK pass (checking for obvious problems). +Checking module I_DELAY_primitive_inst... +Found and reported 0 problems. + +4.30. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + $mux 1 + I_DELAY 1 + +FF init value for cell $procdff$5 ($dff): \dff = 1'x + +4.31. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.32. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.33. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.34. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.35. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.36. Executing OPT_SHARE pass. + +4.37. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.38. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.40. Executing FSM pass (extract and optimize FSM). + +4.40.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.40.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.40.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.40.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.40.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.40.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.41. Executing WREDUCE pass (reducing word size of cells). + +4.42. Executing PEEPOPT pass (run peephole optimizers). + +4.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.44. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.45. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.46. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.47. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.48. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.49. Executing OPT_SHARE pass. + +4.50. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $procdff$5 ($dff) from module I_DELAY_primitive_inst (D = \in, Q = \dff, rval = 1'0). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.51. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 1 unused cells and 1 unused wires. + + +4.52. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.53. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.54. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.55. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.56. Executing OPT_SHARE pass. + +4.57. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.58. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.59. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 2 + +4.60. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.61. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.62. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.63. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.64. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.65. Executing OPT_SHARE pass. + +4.66. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.67. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.68. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.69. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.70. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.71. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.72. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.73. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.74. Executing OPT_SHARE pass. + +4.75. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.76. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.77. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.78. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.79. Executing WREDUCE pass (reducing word size of cells). + +4.80. Executing PEEPOPT pass (run peephole optimizers). + +4.81. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.82. Executing DEMUXMAP pass. + +4.83. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.84. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.85. Executing RS_DSP_MULTADD pass. + +4.86. Executing WREDUCE pass (reducing word size of cells). + +4.87. Executing RS_DSP_MACC pass. + +4.88. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.89. Executing TECHMAP pass (map to technology primitives). + +4.89.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.89.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.90. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.91. Executing TECHMAP pass (map to technology primitives). + +4.91.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.91.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.92. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.93. Executing TECHMAP pass (map to technology primitives). + +4.93.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.93.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.94. Executing TECHMAP pass (map to technology primitives). + +4.94.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.94.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.95. Executing TECHMAP pass (map to technology primitives). + +4.95.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__RS_MUL20X18'. +Generating RTLIL representation for module `\$__RS_MUL10X9'. +Successfully finished Verilog frontend. + +4.95.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.96. Executing RS_DSP_SIMD pass. + +4.97. Executing TECHMAP pass (map to technology primitives). + +4.97.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v' to AST representation. +Generating RTLIL representation for module `\dsp_t1_20x18x64_cfg_ports'. +Generating RTLIL representation for module `\dsp_t1_10x9x32_cfg_params'. +Successfully finished Verilog frontend. + +4.97.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.98. Executing TECHMAP pass (map to technology primitives). + +4.98.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.98.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.99. Executing rs_pack_dsp_regs pass. + +4.100. Executing RS_DSP_IO_REGS pass. + +4.101. Executing TECHMAP pass (map to technology primitives). + +4.101.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSP_MULTACC'. +Generating RTLIL representation for module `\RS_DSP_MULT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN_REGOUT'. +Successfully finished Verilog frontend. + +4.101.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.102. Executing TECHMAP pass (map to technology primitives). + +4.102.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.102.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.103. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.104. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module I_DELAY_primitive_inst: + created 0 $alu and 0 $macc cells. + +4.105. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.106. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.107. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.108. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.109. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.110. Executing OPT_SHARE pass. + +4.111. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.112. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.113. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.114. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.115. Executing MEMORY pass. + +4.115.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.115.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.115.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.115.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.115.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.115.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.115.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.115.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.115.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.115.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.116. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.117. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.118. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.119. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.120. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.121. Executing Rs_BRAM_Split pass. + +4.122. Executing TECHMAP pass (map to technology primitives). + +4.122.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_SDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_SDP'. +Successfully finished Verilog frontend. + +4.122.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.123. Executing TECHMAP pass (map to technology primitives). + +4.123.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Successfully finished Verilog frontend. + +4.123.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.124. Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs). + +4.125. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.126. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.127. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.128. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.129. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.130. Executing OPT_SHARE pass. + +4.131. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.132. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.133. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.134. Executing PMUXTREE pass. + +4.135. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + + +4.136. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +4.137. Executing TECHMAP pass (map to technology primitives). + +4.137.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.137.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_rs_alu'. +Successfully finished Verilog frontend. + +4.137.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $mux. +No more expansions possible. + + +4.138. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $_MUX_ 1 + I_DELAY 1 + +4.139. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.140. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.141. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.142. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.143. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.144. Executing OPT_SHARE pass. + +4.145. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.146. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.147. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.148. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.149. Executing TECHMAP pass (map to technology primitives). + +4.149.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.149.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.150. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $_MUX_ 1 + I_DELAY 1 + +4.151. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.152. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.153. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.154. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.155. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.156. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.157. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.158. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.159. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.160. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.161. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.162. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.163. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.164. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.165. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.166. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.167. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.168. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.169. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.170. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.171. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.172. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.173. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.174. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.175. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.176. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $_MUX_ 1 + I_DELAY 1 + + Number of Generic REGs: 1 + +ABC-DFF iteration : 1 + +4.177. Executing ABC pass (technology mapping using ABC). + +4.177.1. Summary of detected clock domains: + 3 cells in clk=\CLK_IN, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.177.2. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \CLK_IN +Extracted 2 gates and 5 wires to a netlist network with 2 inputs and 1 outputs (dfl=1). + +4.177.2.1. Executing ABC. +[Time = 0.07 sec.] + +4.178. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.179. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.180. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.181. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.182. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.183. Executing OPT_SHARE pass. + +4.184. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.185. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 5 unused wires. + + +4.186. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 2 + +4.187. Executing ABC pass (technology mapping using ABC). + +4.187.1. Summary of detected clock domains: + 3 cells in clk=\CLK_IN, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.187.2. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \CLK_IN +Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 1 outputs (dfl=1). + +4.187.2.1. Executing ABC. +[Time = 0.04 sec.] + +4.188. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.189. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.190. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.191. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.192. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.193. Executing OPT_SHARE pass. + +4.194. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.195. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 5 unused wires. + + +4.196. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 3 + +4.197. Executing ABC pass (technology mapping using ABC). + +4.197.1. Summary of detected clock domains: + 3 cells in clk=\CLK_IN, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.197.2. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \CLK_IN +Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 1 outputs (dfl=2). + +4.197.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.198. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.199. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.200. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.201. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.202. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.203. Executing OPT_SHARE pass. + +4.204. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.205. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 5 unused wires. + + +4.206. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 4 + +4.207. Executing ABC pass (technology mapping using ABC). + +4.207.1. Summary of detected clock domains: + 3 cells in clk=\CLK_IN, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.207.2. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \CLK_IN +Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 1 outputs (dfl=2). + +4.207.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.208. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.209. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.210. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.211. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.212. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.213. Executing OPT_SHARE pass. + +4.214. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.215. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 5 unused wires. + + +4.216. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 +select with DFL1 synthesis (thresh_logic=0.920000, thresh_dff=0.980000) + +4.217. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.218. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.219. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.220. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.221. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.222. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.223. Executing OPT_SHARE pass. + +4.224. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.225. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.226. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.227. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.228. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.229. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.230. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.231. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.232. Executing OPT_SHARE pass. + +4.233. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.234. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.235. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.236. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.237. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.238. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.239. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.240. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.241. Executing OPT_SHARE pass. + +4.242. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.243. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.244. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.245. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.246. Executing BMUXMAP pass. + +4.247. Executing DEMUXMAP pass. + +4.248. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.249. Executing ABC pass (technology mapping using ABC). + +4.249.1. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Extracted 1 gates and 3 wires to a netlist network with 2 inputs and 1 outputs (dfl=1). + +4.249.1.1. Executing ABC. +DE: Version : 7.7 +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.06 sec. at Pass 0]{firstMap}[1] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 1]{initMapFlow}[3] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 2]{map}[9] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.12 sec. at Pass 3]{postMap}[18] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.20 sec. at Pass 4]{map}[54] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.58 sec. at Pass 5]{postMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.64 sec. at Pass 6]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.62 sec. at Pass 7]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.68 sec. at Pass 7]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.56 sec. at Pass 8]{finalMap}[100] +DE: +DE: total time = 3.86 sec. +[Time = 5.92 sec.] + +4.250. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.251. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.252. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.253. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.254. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.255. Executing OPT_SHARE pass. + +4.256. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.257. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 3 unused wires. + + +4.258. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.259. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.260. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.261. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.262. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.263. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.264. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.265. Executing OPT_SHARE pass. + +4.266. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.267. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.268. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.269. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.270. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.271. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.272. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.273. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.274. Executing OPT_SHARE pass. + +4.275. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.276. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.277. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.278. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.279. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $lut 1 + I_DELAY 1 + +4.280. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +4.281. Executing RS_DFFSR_CONV pass. + +4.282. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $lut 1 + I_DELAY 1 + +4.283. Executing TECHMAP pass (map to technology primitives). + +4.283.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.283.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PN0P_'. +Generating RTLIL representation for module `\$_DFFE_PN0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_DFFE_PN1P_'. +Generating RTLIL representation for module `\$_DFFE_PN1N_'. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NN0P_'. +Generating RTLIL representation for module `\$_DFFE_NN0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_NN1P_'. +Generating RTLIL representation for module `\$_DFFE_NN1N_'. +Generating RTLIL representation for module `\$__SHREG_DFF_P_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PN0_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NN0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_PN1_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_NN1_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_PP0_'. +Generating RTLIL representation for module `\$_DLATCH_PN0_'. +Generating RTLIL representation for module `\$_DLATCH_NP0_'. +Generating RTLIL representation for module `\$_DLATCH_NN0_'. +Generating RTLIL representation for module `\$_DLATCH_PP1_'. +Generating RTLIL representation for module `\$_DLATCH_PN1_'. +Generating RTLIL representation for module `\$_DLATCH_NP1_'. +Generating RTLIL representation for module `\$_DLATCH_NN1_'. +Successfully finished Verilog frontend. + +4.283.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $lut. +No more expansions possible. + + +4.284. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + + +4.285. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +4.286. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.287. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.288. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.289. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.290. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.291. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.292. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.293. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.294. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.295. Executing OPT_SHARE pass. + +4.296. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.297. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.298. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.299. Executing TECHMAP pass (map to technology primitives). + +4.299.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.299.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.300. Executing ABC pass (technology mapping using ABC). + +4.300.1. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Extracted 2 gates and 5 wires to a netlist network with 2 inputs and 1 outputs (dfl=1). + +4.300.1.1. Executing ABC. +DE: Version : 7.7 +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 0]{firstMap}[1] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 1]{initMapFlow}[3] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 2]{map}[9] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.12 sec. at Pass 3]{postMap}[18] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.18 sec. at Pass 4]{map}[54] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.52 sec. at Pass 5]{postMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.63 sec. at Pass 6]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.63 sec. at Pass 7]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.64 sec. at Pass 7]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.60 sec. at Pass 8]{finalMap}[100] +DE: +DE: total time = 3.80 sec. +[Time = 5.86 sec.] + +4.301. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.302. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.303. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.304. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.305. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.306. Executing OPT_SHARE pass. + +4.307. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.308. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.309. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.310. Executing HIERARCHY pass (managing design hierarchy). + +4.310.1. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst + +4.310.2. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst +Removed 0 unused modules. + +4.311. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.312. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__IO_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.313. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Replacing existing blackbox module `\BOOT_CLOCK' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:9.1-14.10. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:24.1-31.10. +Generating RTLIL representation for module `\CARRY'. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:41.1-46.10. +Generating RTLIL representation for module `\CLK_BUF'. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:56.1-64.10. +Generating RTLIL representation for module `\DFFNRE'. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:74.1-82.10. +Generating RTLIL representation for module `\DFFRE'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:92.1-126.10. +Generating RTLIL representation for module `\DSP19X2'. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:136.1-162.10. +Generating RTLIL representation for module `\DSP38'. +Replacing existing blackbox module `\FCLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:172.1-176.10. +Generating RTLIL representation for module `\FCLK_BUF'. +Replacing existing blackbox module `\FIFO18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:186.1-233.10. +Generating RTLIL representation for module `\FIFO18KX2'. +Replacing existing blackbox module `\FIFO36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:243.1-268.10. +Generating RTLIL representation for module `\FIFO36K'. +Replacing existing blackbox module `\I_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:278.1-290.10. +Generating RTLIL representation for module `\I_BUF_DS'. +Replacing existing blackbox module `\I_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:300.1-309.10. +Generating RTLIL representation for module `\I_BUF'. +Replacing existing blackbox module `\I_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:319.1-327.10. +Generating RTLIL representation for module `\I_DDR'. +Replacing existing blackbox module `\I_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:337.1-349.10. +Generating RTLIL representation for module `\I_DELAY'. +Replacing existing blackbox module `\I_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:359.1-363.10. +Generating RTLIL representation for module `\I_FAB'. +Replacing existing blackbox module `\I_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:373.1-392.10. +Generating RTLIL representation for module `\I_SERDES'. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:402.1-408.10. +Generating RTLIL representation for module `\LUT1'. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:418.1-424.10. +Generating RTLIL representation for module `\LUT2'. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:434.1-440.10. +Generating RTLIL representation for module `\LUT3'. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:450.1-456.10. +Generating RTLIL representation for module `\LUT4'. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:466.1-472.10. +Generating RTLIL representation for module `\LUT5'. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:482.1-488.10. +Generating RTLIL representation for module `\LUT6'. +Replacing existing blackbox module `\O_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:498.1-510.10. +Generating RTLIL representation for module `\O_BUF_DS'. +Replacing existing blackbox module `\O_BUFT_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:520.1-532.10. +Generating RTLIL representation for module `\O_BUFT_DS'. +Replacing existing blackbox module `\O_BUFT' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:542.1-553.10. +Generating RTLIL representation for module `\O_BUFT'. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:563.1-574.10. +Generating RTLIL representation for module `\O_BUF'. +Replacing existing blackbox module `\O_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:584.1-592.10. +Generating RTLIL representation for module `\O_DDR'. +Replacing existing blackbox module `\O_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:602.1-614.10. +Generating RTLIL representation for module `\O_DELAY'. +Replacing existing blackbox module `\O_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:624.1-628.10. +Generating RTLIL representation for module `\O_FAB'. +Replacing existing blackbox module `\O_SERDES_CLK' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:638.1-647.10. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Replacing existing blackbox module `\O_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:657.1-674.10. +Generating RTLIL representation for module `\O_SERDES'. +Replacing existing blackbox module `\PLL' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:684.1-702.10. +Generating RTLIL representation for module `\PLL'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_M' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:712.1-726.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_S' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:736.1-753.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M0' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:763.1-802.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M1' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:812.1-851.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Replacing existing blackbox module `\SOC_FPGA_INTF_DMA' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:861.1-867.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Replacing existing blackbox module `\SOC_FPGA_INTF_IRQ' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:877.1-883.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Replacing existing blackbox module `\SOC_FPGA_INTF_JTAG' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:893.1-901.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Replacing existing blackbox module `\SOC_FPGA_TEMPERATURE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:911.1-919.10. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:929.1-984.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:994.1-1023.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1040.1-1045.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1053.1-1058.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1067.1-1073.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1081.1-1087.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1096.1-1102.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1111.1-1117.10. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + *************************** + Inserting Input Buffers + *************************** +WARNING: port '\CLK_IN' has no associated I_BUF +WARNING: port '\DLY_ADJ' has no associated I_BUF +WARNING: port '\DLY_INCDEC' has no associated I_BUF +WARNING: port '\DLY_LOAD' has no associated I_BUF +WARNING: port '\in' has no associated I_BUF +WARNING: port '\reset' has no associated I_BUF + *************************** + Inserting Clock Buffers + *************************** +INFO: inserting CLK_BUF before '$ibuf_CLK_IN' + ***************************** + Inserting Output Buffers + ***************************** +WARNING: OUTPUT port '\DLY_TAP_VALUE' has no associated O_BUF +WARNING: OUTPUT port '\O' has no associated O_BUF + ***************************** + Mapping Tri-state Buffers + ***************************** + +4.314. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.315. Executing TECHMAP pass (map to technology primitives). + +4.315.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.315.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.316. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 39 unused wires. + + +4.317. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 19 + Number of wire bits: 29 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 17 + $lut 1 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + O_BUF 7 + +4.318. Executing TECHMAP pass (map to technology primitives). + +4.318.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v' to AST representation. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +4.318.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.319. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 2 unused wires. + + +4.320. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 19 + Number of wire bits: 29 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 17 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + LUT2 1 + O_BUF 7 + + ***************************** + Rewire_Obuft + ***************************** + +========================== +Post Design clean up ... + +Split to bits ... + +4.321. Executing SPLITNETS pass (splitting up multi-bit signals). + +Split into bits ... [0.00 sec.] +Building Sig2cells ... [0.00 sec.] +Building Sig2sig ... [0.00 sec.] +Backward clean up ... [0.00 sec.] +Before cleanup : + +4.322. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 24 + Number of wire bits: 29 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 17 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + LUT2 1 + O_BUFT 7 + + -------------------------- + Removed assigns : 0 + Removed wires : 0 + Removed cells : 0 + -------------------------- +After cleanup : + +4.323. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 24 + Number of wire bits: 29 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 17 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + LUT2 1 + O_BUFT 7 + + +Total time for 'obs_clean' ... + [0.00 sec.] + +4.324. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.325. Executing HIERARCHY pass (managing design hierarchy). + +4.325.1. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst + +4.325.2. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst +Removed 0 unused modules. + +Dumping port properties into 'netlist_info.json' file. + +Inserting I_FAB/O_FAB cells ... + +Skip O_FAB insertion on net '$obuf_O' (Primitive output) + +Inserting I_FAB/O_FAB cells done. + +4.326. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 39 + Number of wire bits: 44 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 32 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + I_FAB 6 + LUT2 1 + O_BUFT 7 + O_FAB 9 + + Number of LUTs: 1 + Number of REGs: 1 + Number of CARRY ADDERs: 0 + +4.327. Executing Verilog backend. +Dumping module `\I_DELAY_primitive_inst'. + +# -------------------- +# Core Synthesis done +# -------------------- + +4.328. Executing Verilog backend. +Dumping module `\I_DELAY_primitive_inst'. + +4.328.1. Executing BLIF backend. +Extracting primitives + +-- Running command `write_rtlil design.rtlil' -- + +4.328.2. Executing RTLIL backend. +Output filename: design.rtlil +Running SplitNets + +4.328.3. Executing SPLITNETS pass (splitting up multi-bit signals). +Gathering Wires Data +Adding wires between directly connected input and output primitives +Upgrading fabric wires to ports +Handling I_BUF->Fabric->CLK_BUF +Handling Dangling outs +Deleting primitive cells and extra wires +Deleting non-primitive cells and upgrading wires to ports in interface module +Handling I_BUF->Fabric->CLK_BUF in interface module +Removing extra wires from interface module +Cleaning fabric netlist +Removing cells from wrapper module +Instantiating fabric and interface modules +Removing extra wires from wrapper module +Fixing wrapper ports +Flattening wrapper module + +4.328.4. Executing FLATTEN pass (flatten design). +Deleting now unused module interface_I_DELAY_primitive_inst. + +Removing extra assigns from wrapper module + +4.328.5. Executing Verilog backend. +Dumping module `\I_DELAY_primitive_inst'. + +4.328.5.1. Executing BLIF backend. + +4.328.5.2. Executing Verilog backend. +Dumping module `\I_DELAY_primitive_inst'. + +4.328.5.2.1. Executing BLIF backend. +Dumping config.json +Updating sdc + +4.328.5.2.2. Executing Verilog backend. +Dumping module `\fabric_I_DELAY_primitive_inst'. + +4.328.5.2.2.1. Executing BLIF backend. + +Warnings: 1 unique messages, 1 total +End of script. Logfile hash: 51223390fa, CPU: user 0.59s system 0.07s, MEM: 23.35 MB peak +Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) +Time spent: 99% 6x abc (181 sec), 0% 43x read_verilog (0 sec), ... diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/config.json b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/config.json new file mode 100644 index 00000000..4159ff7c --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/config.json @@ -0,0 +1,234 @@ +{ + "instances": [ + { + "connectivity": { + "CLK_IN": "$clk_buf_$ibuf_CLK_IN", + "DLY_ADJ": "$f2g_trx_dly_adj_$ibuf_DLY_ADJ", + "DLY_INCDEC": "$f2g_trx_dly_inc_$ibuf_DLY_INCDEC", + "DLY_LOAD": "$f2g_trx_dly_ld_$ibuf_DLY_LOAD", + "DLY_TAP_VALUE": [ + "$ifab_$obuf_DLY_TAP_VALUE[0]", + "$ifab_$obuf_DLY_TAP_VALUE[1]", + "$ifab_$obuf_DLY_TAP_VALUE[2]", + "$ifab_$obuf_DLY_TAP_VALUE[3]", + "$ifab_$obuf_DLY_TAP_VALUE[4]", + "$ifab_$obuf_DLY_TAP_VALUE[5]" + ], + "I": "dff", + "O": "$obuf_O" + }, + "module": "I_DELAY", + "name": "$auto_454.inst" + }, + { + "connectivity": { + "I": "$flatten$auto_454.$ibuf_CLK_IN", + "O": "$clk_buf_$ibuf_CLK_IN" + }, + "direction": "IN", + "index": 1, + "linked_object": "CLK_IN", + "module": "CLK_BUF", + "name": "$flatten$auto_454.$clkbuf$I_DELAY_primitive_inst.$ibuf_CLK_IN" + }, + { + "connectivity": { + "EN": "$auto_440", + "I": "CLK_IN", + "O": "$flatten$auto_454.$ibuf_CLK_IN" + }, + "direction": "IN", + "index": 0, + "linked_object": "CLK_IN", + "module": "I_BUF", + "name": "$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_CLK_IN" + }, + { + "connectivity": { + "EN": "$auto_441", + "I": "DLY_ADJ", + "O": "$ibuf_DLY_ADJ" + }, + "direction": "IN", + "index": 0, + "linked_object": "DLY_ADJ", + "module": "I_BUF", + "name": "$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_ADJ" + }, + { + "connectivity": { + "EN": "$auto_442", + "I": "DLY_INCDEC", + "O": "$ibuf_DLY_INCDEC" + }, + "direction": "IN", + "index": 0, + "linked_object": "DLY_INCDEC", + "module": "I_BUF", + "name": "$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_INCDEC" + }, + { + "connectivity": { + "EN": "$auto_443", + "I": "DLY_LOAD", + "O": "$ibuf_DLY_LOAD" + }, + "direction": "IN", + "index": 0, + "linked_object": "DLY_LOAD", + "module": "I_BUF", + "name": "$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_LOAD" + }, + { + "connectivity": { + "EN": "$auto_444", + "I": "in", + "O": "$ibuf_in" + }, + "direction": "IN", + "index": 0, + "linked_object": "in", + "module": "I_BUF", + "name": "$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_in" + }, + { + "connectivity": { + "EN": "$auto_445", + "I": "reset", + "O": "$ibuf_reset" + }, + "direction": "IN", + "index": 0, + "linked_object": "reset", + "module": "I_BUF", + "name": "$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_reset" + }, + { + "connectivity": { + "I": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[0]", + "O": "DLY_TAP_VALUE[0]", + "T": "$auto_446" + }, + "direction": "OUT", + "index": 0, + "linked_object": "DLY_TAP_VALUE[0]", + "module": "O_BUFT", + "name": "$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE" + }, + { + "connectivity": { + "I": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[1]", + "O": "DLY_TAP_VALUE[1]", + "T": "$auto_447" + }, + "direction": "OUT", + "index": 0, + "linked_object": "DLY_TAP_VALUE[1]", + "module": "O_BUFT", + "name": "$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_1" + }, + { + "connectivity": { + "I": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[2]", + "O": "DLY_TAP_VALUE[2]", + "T": "$auto_448" + }, + "direction": "OUT", + "index": 0, + "linked_object": "DLY_TAP_VALUE[2]", + "module": "O_BUFT", + "name": "$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_2" + }, + { + "connectivity": { + "I": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[3]", + "O": "DLY_TAP_VALUE[3]", + "T": "$auto_449" + }, + "direction": "OUT", + "index": 0, + "linked_object": "DLY_TAP_VALUE[3]", + "module": "O_BUFT", + "name": "$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_3" + }, + { + "connectivity": { + "I": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[4]", + "O": "DLY_TAP_VALUE[4]", + "T": "$auto_450" + }, + "direction": "OUT", + "index": 0, + "linked_object": "DLY_TAP_VALUE[4]", + "module": "O_BUFT", + "name": "$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_4" + }, + { + "connectivity": { + "I": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[5]", + "O": "DLY_TAP_VALUE[5]", + "T": "$auto_451" + }, + "direction": "OUT", + "index": 0, + "linked_object": "DLY_TAP_VALUE[5]", + "module": "O_BUFT", + "name": "$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_5" + }, + { + "connectivity": { + "I": "$auto_453", + "O": "O", + "T": "$auto_452" + }, + "direction": "OUT", + "index": 0, + "linked_object": "O", + "module": "O_BUFT", + "name": "$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_O" + }, + { + "connectivity": { + "$auto_440": "$auto_440", + "$auto_441": "$auto_441", + "$auto_442": "$auto_442", + "$auto_443": "$auto_443", + "$auto_444": "$auto_444", + "$auto_445": "$auto_445", + "$auto_446": "$auto_446", + "$auto_447": "$auto_447", + "$auto_448": "$auto_448", + "$auto_449": "$auto_449", + "$auto_450": "$auto_450", + "$auto_451": "$auto_451", + "$auto_452": "$auto_452", + "$auto_453": "$auto_453", + "$clk_buf_$ibuf_CLK_IN": "$clk_buf_$ibuf_CLK_IN", + "$f2g_trx_dly_adj_$ibuf_DLY_ADJ": "$f2g_trx_dly_adj_$ibuf_DLY_ADJ", + "$f2g_trx_dly_inc_$ibuf_DLY_INCDEC": "$f2g_trx_dly_inc_$ibuf_DLY_INCDEC", + "$f2g_trx_dly_ld_$ibuf_DLY_LOAD": "$f2g_trx_dly_ld_$ibuf_DLY_LOAD", + "$f2g_tx_out_$obuf_DLY_TAP_VALUE[0]": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[0]", + "$f2g_tx_out_$obuf_DLY_TAP_VALUE[1]": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[1]", + "$f2g_tx_out_$obuf_DLY_TAP_VALUE[2]": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[2]", + "$f2g_tx_out_$obuf_DLY_TAP_VALUE[3]": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[3]", + "$f2g_tx_out_$obuf_DLY_TAP_VALUE[4]": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[4]", + "$f2g_tx_out_$obuf_DLY_TAP_VALUE[5]": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[5]", + "$ibuf_DLY_ADJ": "$ibuf_DLY_ADJ", + "$ibuf_DLY_INCDEC": "$ibuf_DLY_INCDEC", + "$ibuf_DLY_LOAD": "$ibuf_DLY_LOAD", + "$ibuf_in": "$ibuf_in", + "$ibuf_reset": "$ibuf_reset", + "$ifab_$obuf_DLY_TAP_VALUE[0]": "$ifab_$obuf_DLY_TAP_VALUE[0]", + "$ifab_$obuf_DLY_TAP_VALUE[1]": "$ifab_$obuf_DLY_TAP_VALUE[1]", + "$ifab_$obuf_DLY_TAP_VALUE[2]": "$ifab_$obuf_DLY_TAP_VALUE[2]", + "$ifab_$obuf_DLY_TAP_VALUE[3]": "$ifab_$obuf_DLY_TAP_VALUE[3]", + "$ifab_$obuf_DLY_TAP_VALUE[4]": "$ifab_$obuf_DLY_TAP_VALUE[4]", + "$ifab_$obuf_DLY_TAP_VALUE[5]": "$ifab_$obuf_DLY_TAP_VALUE[5]", + "$obuf_O": "$obuf_O", + "dff": "dff" + }, + "module": "fabric_I_DELAY_primitive_inst", + "name": "fabric_instance" + } + ] +} diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/core_synthesis.v b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/core_synthesis.v new file mode 100644 index 00000000..427ee707 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/core_synthesis.v @@ -0,0 +1,216 @@ +/* Generated by Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) */ + +module I_DELAY_primitive_inst(reset, in, DLY_LOAD, DLY_ADJ, DLY_INCDEC, DLY_TAP_VALUE, CLK_IN, O); + input CLK_IN; + input DLY_ADJ; + input DLY_INCDEC; + input DLY_LOAD; + output [5:0] DLY_TAP_VALUE; + output O; + input in; + input reset; + wire _00_; + wire _01_; + wire _02_; + wire _03_; + wire _04_; + wire _05_; + wire _06_; + wire _07_; + wire _08_; + wire _09_; + wire _10_; + wire _11_; + wire _12_; + wire _13_; + wire _14_; + wire _15_; + wire _16_; + wire _17_; + wire _18_; + wire _19_; + wire _20_; + wire _21_; + wire _22_; + wire _23_; + wire _24_; + wire _25_; + wire _26_; + wire _27_; + wire _28_; + wire _29_; + wire CLK_IN; + wire DLY_ADJ; + wire DLY_INCDEC; + wire DLY_LOAD; + wire [5:0] DLY_TAP_VALUE; + wire O; + wire dff; + wire in; + wire reset; + DFFRE _30_ ( + .C(_01_), + .D(_00_), + .E(1'b1), + .Q(dff), + .R(1'b1) + ); + LUT2 #( + .INIT_VALUE(4'b0100) + ) _31_ ( + .A({ _15_, _16_ }), + .Y(_00_) + ); + CLK_BUF _32_ ( + .I(_11_), + .O(_01_) + ); + O_FAB _33_ ( + .I(_12_), + .O(_02_) + ); + O_FAB _34_ ( + .I(_13_), + .O(_03_) + ); + O_FAB _35_ ( + .I(_14_), + .O(_04_) + ); + O_FAB _36_ ( + .I(_23_), + .O(_05_) + ); + O_FAB _37_ ( + .I(_24_), + .O(_06_) + ); + O_FAB _38_ ( + .I(_25_), + .O(_07_) + ); + O_FAB _39_ ( + .I(_26_), + .O(_08_) + ); + O_FAB _40_ ( + .I(_27_), + .O(_09_) + ); + O_FAB _41_ ( + .I(_28_), + .O(_10_) + ); + I_BUF #( + .WEAK_KEEPER("NONE") + ) _42_ ( + .EN(1'b1), + .I(CLK_IN), + .O(_11_) + ); + I_BUF #( + .WEAK_KEEPER("NONE") + ) _43_ ( + .EN(1'b1), + .I(DLY_ADJ), + .O(_12_) + ); + I_BUF #( + .WEAK_KEEPER("NONE") + ) _44_ ( + .EN(1'b1), + .I(DLY_INCDEC), + .O(_13_) + ); + I_BUF #( + .WEAK_KEEPER("NONE") + ) _45_ ( + .EN(1'b1), + .I(DLY_LOAD), + .O(_14_) + ); + I_BUF #( + .WEAK_KEEPER("NONE") + ) _46_ ( + .EN(1'b1), + .I(in), + .O(_15_) + ); + I_BUF #( + .WEAK_KEEPER("NONE") + ) _47_ ( + .EN(1'b1), + .I(reset), + .O(_16_) + ); + I_FAB _48_ ( + .I(_17_), + .O(_23_) + ); + I_FAB _49_ ( + .I(_18_), + .O(_24_) + ); + I_FAB _50_ ( + .I(_19_), + .O(_25_) + ); + I_FAB _51_ ( + .I(_20_), + .O(_26_) + ); + I_FAB _52_ ( + .I(_21_), + .O(_27_) + ); + I_FAB _53_ ( + .I(_22_), + .O(_28_) + ); + O_BUFT _54_ ( + .I(_05_), + .O(DLY_TAP_VALUE[0]), + .T(1'b1) + ); + O_BUFT _55_ ( + .I(_06_), + .O(DLY_TAP_VALUE[1]), + .T(1'b1) + ); + O_BUFT _56_ ( + .I(_07_), + .O(DLY_TAP_VALUE[2]), + .T(1'b1) + ); + O_BUFT _57_ ( + .I(_08_), + .O(DLY_TAP_VALUE[3]), + .T(1'b1) + ); + O_BUFT _58_ ( + .I(_09_), + .O(DLY_TAP_VALUE[4]), + .T(1'b1) + ); + O_BUFT _59_ ( + .I(_10_), + .O(DLY_TAP_VALUE[5]), + .T(1'b1) + ); + O_BUFT _60_ ( + .I(_29_), + .O(O), + .T(1'b1) + ); + I_DELAY #( + .DELAY(32'sd0) + ) inst ( + .CLK_IN(_01_), + .DLY_ADJ(_02_), + .DLY_INCDEC(_03_), + .DLY_LOAD(_04_), + .DLY_TAP_VALUE({ _22_, _21_, _20_, _19_, _18_, _17_ }), + .I(dff), + .O(_29_) + ); +endmodule diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/design.rtlil b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/design.rtlil new file mode 100644 index 00000000..4049bb7b --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/design.rtlil @@ -0,0 +1,1908 @@ +# Generated by Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) +autoidx 440 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:9.1-14.10" +module \BOOT_CLOCK + parameter \PERIOD 25 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:12.14-12.15" + wire output 1 \O +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:542.1-951.10" +module \BRAM2x18_SDP + parameter \CFG_ABITS 11 + parameter \CFG_DBITS 18 + parameter \CFG_ENABLE_B 2 + parameter \CFG_ENABLE_D 2 + parameter \CLKPOL2 1 + parameter \CLKPOL3 1 + parameter \INIT0 18432'x + parameter \INIT1 18432'x + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:563.27-563.33" + wire width 11 input 1 \A1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:564.28-564.34" + wire width 18 output 2 \A1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:565.11-565.15" + wire input 3 \A1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:567.27-567.33" + wire width 11 input 4 \B1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:570.30-570.34" + wire width 2 input 7 \B1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:568.27-568.33" + wire width 18 input 5 \B1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:569.11-569.15" + wire input 6 \B1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:572.27-572.33" + wire width 11 input 8 \C1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:573.28-573.34" + wire width 18 output 9 \C1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:574.11-574.15" + wire input 10 \C1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:560.11-560.15" + wire input 11 \CLK1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:561.11-561.15" + wire input 12 \CLK2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:576.27-576.33" + wire width 11 input 13 \D1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:579.30-579.34" + wire width 2 input 16 \D1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:577.27-577.33" + wire width 18 input 14 \D1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:578.11-578.15" + wire input 15 \D1EN +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:112.1-540.10" +module \BRAM2x18_TDP + parameter \CFG_ABITS 11 + parameter \CFG_DBITS 18 + parameter \CFG_ENABLE_B 2 + parameter \CFG_ENABLE_D 2 + parameter \CFG_ENABLE_F 2 + parameter \CFG_ENABLE_H 2 + parameter \CLKPOL2 1 + parameter \CLKPOL3 1 + parameter \INIT0 18432'x + parameter \INIT1 18432'x + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:137.27-137.33" + wire width 11 input 1 \A1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:138.28-138.34" + wire width 18 output 2 \A1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:139.11-139.15" + wire input 3 \A1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:141.27-141.33" + wire width 11 input 4 \B1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:144.30-144.34" + wire width 2 input 7 \B1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:142.27-142.33" + wire width 18 input 5 \B1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:143.11-143.15" + wire input 6 \B1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:146.27-146.33" + wire width 11 input 8 \C1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:147.28-147.34" + wire width 18 output 9 \C1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:148.11-148.15" + wire input 10 \C1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:132.11-132.15" + wire input 11 \CLK1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:133.11-133.15" + wire input 12 \CLK2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:134.11-134.15" + wire input 13 \CLK3 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:135.11-135.15" + wire input 14 \CLK4 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:150.27-150.33" + wire width 11 input 15 \D1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:153.30-153.34" + wire width 2 input 18 \D1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:151.27-151.33" + wire width 18 input 16 \D1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:152.11-152.15" + wire input 17 \D1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:155.27-155.33" + wire width 11 input 19 \E1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:156.28-156.34" + wire width 18 output 20 \E1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:157.11-157.15" + wire input 21 \E1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:159.27-159.33" + wire width 11 input 22 \F1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:162.30-162.34" + wire width 2 input 25 \F1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:160.27-160.33" + wire width 18 input 23 \F1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:161.11-161.15" + wire input 24 \F1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:164.27-164.33" + wire width 11 input 26 \G1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:165.28-165.34" + wire width 18 output 27 \G1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:166.11-166.15" + wire input 28 \G1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:168.27-168.33" + wire width 11 input 29 \H1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:171.30-171.34" + wire width 2 input 32 \H1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:169.27-169.33" + wire width 18 input 30 \H1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:170.11-170.15" + wire input 31 \H1EN +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:24.1-31.10" +module \CARRY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:27.15-27.18" + wire input 3 \CIN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:29.16-29.20" + wire output 5 \COUT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:26.15-26.16" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:28.16-28.17" + wire output 4 \O + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:25.15-25.16" + wire input 1 \P +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:41.1-46.10" +module \CLK_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:42.15-42.16" + wire input 1 \I + attribute \clkbuf_driver 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:44.16-44.17" + wire output 2 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:56.1-64.10" +module \DFFNRE + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:61.15-61.16" + wire input 4 \C + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:57.15-57.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:59.15-59.16" + wire input 3 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:62.14-62.15" + wire output 5 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:58.15-58.16" + wire input 2 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:74.1-82.10" +module \DFFRE + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:79.15-79.16" + wire input 4 \C + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:75.15-75.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:77.15-77.16" + wire input 3 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:80.14-80.15" + wire output 5 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:76.15-76.16" + wire input 2 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:92.1-126.10" +module \DSP19X2 + parameter \DSP_MODE "MULTIPLY_ACCUMULATE" + parameter \COEFF1_0 10'0000000000 + parameter \COEFF1_1 10'0000000000 + parameter \COEFF1_2 10'0000000000 + parameter \COEFF1_3 10'0000000000 + parameter \COEFF2_0 10'0000000000 + parameter \COEFF2_1 10'0000000000 + parameter \COEFF2_2 10'0000000000 + parameter \COEFF2_3 10'0000000000 + parameter \OUTPUT_REG_EN "TRUE" + parameter \INPUT_REG_EN "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:105.21-105.23" + wire width 10 input 1 \A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:109.21-109.23" + wire width 10 input 5 \A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:116.21-116.28" + wire width 5 input 11 \ACC_FIR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:106.21-106.23" + wire width 9 input 2 \B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:110.21-110.23" + wire width 9 input 6 \B2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:114.15-114.18" + wire input 9 \CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:108.22-108.28" + wire width 9 output 4 \DLY_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:112.22-112.28" + wire width 9 output 8 \DLY_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:117.21-117.29" + wire width 3 input 12 \FEEDBACK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:118.15-118.23" + wire input 13 \LOAD_ACC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:115.15-115.20" + wire input 10 \RESET + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:123.15-123.20" + wire input 18 \ROUND + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:121.15-121.23" + wire input 16 \SATURATE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:122.21-122.32" + wire width 5 input 17 \SHIFT_RIGHT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:124.15-124.23" + wire input 19 \SUBTRACT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:119.15-119.25" + wire input 14 \UNSIGNED_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:120.15-120.25" + wire input 15 \UNSIGNED_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:107.23-107.25" + wire width 19 output 3 \Z1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:111.23-111.25" + wire width 19 output 7 \Z2 +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:136.1-162.10" +module \DSP38 + parameter \DSP_MODE "MULTIPLY_ACCUMULATE" + parameter \COEFF_0 20'00000000000000000000 + parameter \COEFF_1 20'00000000000000000000 + parameter \COEFF_2 20'00000000000000000000 + parameter \COEFF_3 20'00000000000000000000 + parameter \OUTPUT_REG_EN "TRUE" + parameter \INPUT_REG_EN "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:145.22-145.23" + wire width 20 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:147.21-147.28" + wire width 6 input 3 \ACC_FIR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:146.22-146.23" + wire width 18 input 2 \B + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:151.15-151.18" + wire input 6 \CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:149.21-149.26" + wire width 18 output 5 \DLY_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:153.21-153.29" + wire width 3 input 8 \FEEDBACK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:154.15-154.23" + wire input 9 \LOAD_ACC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:152.15-152.20" + wire input 7 \RESET + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:157.15-157.20" + wire input 12 \ROUND + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:155.15-155.23" + wire input 10 \SATURATE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:156.21-156.32" + wire width 6 input 11 \SHIFT_RIGHT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:158.15-158.23" + wire input 13 \SUBTRACT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:159.15-159.25" + wire input 14 \UNSIGNED_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:160.15-160.25" + wire input 15 \UNSIGNED_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:148.23-148.24" + wire width 38 output 4 \Z +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:172.1-176.10" +module \FCLK_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:173.15-173.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:174.16-174.17" + wire output 2 \O +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:186.1-233.10" +module \FIFO18KX2 + parameter \DATA_WRITE_WIDTH1 18 + parameter \DATA_READ_WIDTH1 18 + parameter \FIFO_TYPE1 "SYNCHRONOUS" + parameter \PROG_EMPTY_THRESH1 11'00000000100 + parameter \PROG_FULL_THRESH1 11'11111111010 + parameter \DATA_WRITE_WIDTH2 18 + parameter \DATA_READ_WIDTH2 18 + parameter \FIFO_TYPE2 "SYNCHRONOUS" + parameter \PROG_EMPTY_THRESH2 11'00000000100 + parameter \PROG_FULL_THRESH2 11'11111111010 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:209.14-209.27" + wire output 10 \ALMOST_EMPTY1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:226.14-226.27" + wire output 25 \ALMOST_EMPTY2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:210.14-210.26" + wire output 11 \ALMOST_FULL1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:227.14-227.26" + wire output 26 \ALMOST_FULL2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:207.14-207.20" + wire output 8 \EMPTY1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:224.14-224.20" + wire output 23 \EMPTY2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:208.14-208.19" + wire output 9 \FULL1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:225.14-225.19" + wire output 24 \FULL2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:213.14-213.23" + wire output 14 \OVERFLOW1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:230.14-230.23" + wire output 29 \OVERFLOW2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:211.14-211.25" + wire output 12 \PROG_EMPTY1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:228.14-228.25" + wire output 27 \PROG_EMPTY2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:212.14-212.24" + wire output 13 \PROG_FULL1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:229.14-229.24" + wire output 28 \PROG_FULL2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:202.15-202.22" + wire input 3 \RD_CLK1 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:219.15-219.22" + wire input 18 \RD_CLK2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:206.39-206.47" + wire width 18 output 7 \RD_DATA1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:223.39-223.47" + wire width 18 output 22 \RD_DATA2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:204.15-204.21" + wire input 5 \RD_EN1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:221.15-221.21" + wire input 20 \RD_EN2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:198.15-198.21" + wire input 1 \RESET1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:215.15-215.21" + wire input 16 \RESET2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:214.14-214.24" + wire output 15 \UNDERFLOW1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:231.14-231.24" + wire output 30 \UNDERFLOW2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:200.15-200.22" + wire input 2 \WR_CLK1 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:217.15-217.22" + wire input 17 \WR_CLK2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:205.39-205.47" + wire width 18 input 6 \WR_DATA1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:222.39-222.47" + wire width 18 input 21 \WR_DATA2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:203.15-203.21" + wire input 4 \WR_EN1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:220.15-220.21" + wire input 19 \WR_EN2 +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:243.1-268.10" +module \FIFO36K + parameter \DATA_WRITE_WIDTH 36 + parameter \DATA_READ_WIDTH 36 + parameter \FIFO_TYPE "SYNCHRONOUS" + parameter \PROG_EMPTY_THRESH 12'000000000100 + parameter \PROG_FULL_THRESH 12'111111111010 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:261.14-261.26" + wire output 10 \ALMOST_EMPTY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:262.14-262.25" + wire output 11 \ALMOST_FULL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:259.14-259.19" + wire output 8 \EMPTY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:260.14-260.18" + wire output 9 \FULL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:265.14-265.22" + wire output 14 \OVERFLOW + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:263.14-263.24" + wire output 12 \PROG_EMPTY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:264.14-264.23" + wire output 13 \PROG_FULL + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:254.15-254.21" + wire input 3 \RD_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:258.38-258.45" + wire width 36 output 7 \RD_DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:256.15-256.20" + wire input 5 \RD_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:250.15-250.20" + wire input 1 \RESET + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:266.14-266.23" + wire output 15 \UNDERFLOW + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:252.15-252.21" + wire input 2 \WR_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:257.38-257.45" + wire width 36 input 6 \WR_DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:255.15-255.20" + wire input 4 \WR_EN +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:300.1-309.10" +module \I_BUF + parameter \WEAK_KEEPER "NONE" + parameter \IOSTANDARD "DEFAULT" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:306.15-306.17" + wire input 2 \EN + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:305.15-305.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:307.16-307.17" + wire output 3 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:278.1-290.10" +module \I_BUF_DS + parameter \WEAK_KEEPER "NONE" + parameter \IOSTANDARD "DEFAULT" + parameter \DIFFERENTIAL_TERMINATION "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:287.15-287.17" + wire input 3 \EN + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:286.15-286.18" + wire input 2 \I_N + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:284.15-284.18" + wire input 1 \I_P + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:288.14-288.15" + wire output 4 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:319.1-327.10" +module \I_DDR + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:324.15-324.16" + wire input 4 \C + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:320.15-320.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:322.15-322.16" + wire input 3 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:325.20-325.21" + wire width 2 output 5 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:321.15-321.16" + wire input 2 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:337.1-349.10" +module \I_DELAY + parameter \DELAY 0 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:346.15-346.21" + wire input 6 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:342.15-342.22" + wire input 3 \DLY_ADJ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:343.15-343.25" + wire input 4 \DLY_INCDEC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:341.15-341.23" + wire input 2 \DLY_LOAD + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:344.22-344.35" + wire width 6 output 5 \DLY_TAP_VALUE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:340.15-340.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:347.16-347.17" + wire output 7 \O +end +attribute \top 1 +attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:1.1-35.10" +module \I_DELAY_primitive_inst + parameter \DELAY 0 + wire $abc$192$li0_li0 + wire $clk_buf_$ibuf_CLK_IN + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" + wire $f2g_trx_dly_adj_$ibuf_DLY_ADJ + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" + wire $f2g_trx_dly_inc_$ibuf_DLY_INCDEC + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" + wire $f2g_trx_dly_ld_$ibuf_DLY_LOAD + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire $f2g_tx_out_$obuf_DLY_TAP_VALUE[0] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 1 $f2g_tx_out_$obuf_DLY_TAP_VALUE[1] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 2 $f2g_tx_out_$obuf_DLY_TAP_VALUE[2] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 3 $f2g_tx_out_$obuf_DLY_TAP_VALUE[3] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 4 $f2g_tx_out_$obuf_DLY_TAP_VALUE[4] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 5 $f2g_tx_out_$obuf_DLY_TAP_VALUE[5] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" + wire $ibuf_CLK_IN + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" + wire $ibuf_DLY_ADJ + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" + wire $ibuf_DLY_INCDEC + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" + wire $ibuf_DLY_LOAD + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" + wire $ibuf_in + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" + wire $ibuf_reset + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire $ifab_$obuf_DLY_TAP_VALUE[0] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 1 $ifab_$obuf_DLY_TAP_VALUE[1] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 2 $ifab_$obuf_DLY_TAP_VALUE[2] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 3 $ifab_$obuf_DLY_TAP_VALUE[3] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 4 $ifab_$obuf_DLY_TAP_VALUE[4] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 5 $ifab_$obuf_DLY_TAP_VALUE[5] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire $obuf_DLY_TAP_VALUE[0] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 1 $obuf_DLY_TAP_VALUE[1] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 2 $obuf_DLY_TAP_VALUE[2] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 3 $obuf_DLY_TAP_VALUE[3] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 4 $obuf_DLY_TAP_VALUE[4] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire offset 5 $obuf_DLY_TAP_VALUE[5] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" + wire $obuf_O + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" + wire input 7 \CLK_IN + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" + wire input 4 \DLY_ADJ + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" + wire input 5 \DLY_INCDEC + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" + wire input 3 \DLY_LOAD + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" + wire width 6 output 6 \DLY_TAP_VALUE + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" + wire output 8 \O + attribute \init 1'0 + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:14.5-14.8" + wire \dff + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" + wire input 2 \in + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" + wire input 1 \reset + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" + cell \DFFRE $abc$192$auto_193 + connect \C $clk_buf_$ibuf_CLK_IN + connect \D $abc$192$li0_li0 + connect \E 1'1 + connect \Q \dff + connect \R 1'1 + end + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" + cell \LUT2 $abc$424$auto_425 + parameter \INIT_VALUE 4'0100 + connect \A { $ibuf_in $ibuf_reset } + connect \Y $abc$192$li0_li0 + end + attribute \keep 1 + cell \CLK_BUF $clkbuf$I_DELAY_primitive_inst.$ibuf_CLK_IN + connect \I $ibuf_CLK_IN + connect \O $clk_buf_$ibuf_CLK_IN + end + attribute \keep 1 + cell \O_FAB $f2g_trx_dly_adj_$ibuf_DLY_ADJ_1 + connect \I $ibuf_DLY_ADJ + connect \O $f2g_trx_dly_adj_$ibuf_DLY_ADJ + end + attribute \keep 1 + cell \O_FAB $f2g_trx_dly_inc_$ibuf_DLY_INCDEC_1 + connect \I $ibuf_DLY_INCDEC + connect \O $f2g_trx_dly_inc_$ibuf_DLY_INCDEC + end + attribute \keep 1 + cell \O_FAB $f2g_trx_dly_ld_$ibuf_DLY_LOAD_1 + connect \I $ibuf_DLY_LOAD + connect \O $f2g_trx_dly_ld_$ibuf_DLY_LOAD + end + attribute \keep 1 + cell \O_FAB $f2g_tx_out_$obuf_DLY_TAP_VALUE[0]_1 + connect \I $obuf_DLY_TAP_VALUE[0] + connect \O $f2g_tx_out_$obuf_DLY_TAP_VALUE[0] + end + attribute \keep 1 + cell \O_FAB $f2g_tx_out_$obuf_DLY_TAP_VALUE[1]_1 + connect \I $obuf_DLY_TAP_VALUE[1] + connect \O $f2g_tx_out_$obuf_DLY_TAP_VALUE[1] + end + attribute \keep 1 + cell \O_FAB $f2g_tx_out_$obuf_DLY_TAP_VALUE[2]_1 + connect \I $obuf_DLY_TAP_VALUE[2] + connect \O $f2g_tx_out_$obuf_DLY_TAP_VALUE[2] + end + attribute \keep 1 + cell \O_FAB $f2g_tx_out_$obuf_DLY_TAP_VALUE[3]_1 + connect \I $obuf_DLY_TAP_VALUE[3] + connect \O $f2g_tx_out_$obuf_DLY_TAP_VALUE[3] + end + attribute \keep 1 + cell \O_FAB $f2g_tx_out_$obuf_DLY_TAP_VALUE[4]_1 + connect \I $obuf_DLY_TAP_VALUE[4] + connect \O $f2g_tx_out_$obuf_DLY_TAP_VALUE[4] + end + attribute \keep 1 + cell \O_FAB $f2g_tx_out_$obuf_DLY_TAP_VALUE[5]_1 + connect \I $obuf_DLY_TAP_VALUE[5] + connect \O $f2g_tx_out_$obuf_DLY_TAP_VALUE[5] + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" + cell \I_BUF $ibuf$I_DELAY_primitive_inst.$ibuf_CLK_IN + parameter \WEAK_KEEPER "NONE" + connect \EN 1'1 + connect \I \CLK_IN + connect \O $ibuf_CLK_IN + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" + cell \I_BUF $ibuf$I_DELAY_primitive_inst.$ibuf_DLY_ADJ + parameter \WEAK_KEEPER "NONE" + connect \EN 1'1 + connect \I \DLY_ADJ + connect \O $ibuf_DLY_ADJ + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" + cell \I_BUF $ibuf$I_DELAY_primitive_inst.$ibuf_DLY_INCDEC + parameter \WEAK_KEEPER "NONE" + connect \EN 1'1 + connect \I \DLY_INCDEC + connect \O $ibuf_DLY_INCDEC + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" + cell \I_BUF $ibuf$I_DELAY_primitive_inst.$ibuf_DLY_LOAD + parameter \WEAK_KEEPER "NONE" + connect \EN 1'1 + connect \I \DLY_LOAD + connect \O $ibuf_DLY_LOAD + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" + cell \I_BUF $ibuf$I_DELAY_primitive_inst.$ibuf_in + parameter \WEAK_KEEPER "NONE" + connect \EN 1'1 + connect \I \in + connect \O $ibuf_in + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" + cell \I_BUF $ibuf$I_DELAY_primitive_inst.$ibuf_reset + parameter \WEAK_KEEPER "NONE" + connect \EN 1'1 + connect \I \reset + connect \O $ibuf_reset + end + attribute \keep 1 + cell \I_FAB $ifab_$obuf_DLY_TAP_VALUE[0]_1 + connect \I $ifab_$obuf_DLY_TAP_VALUE[0] + connect \O $obuf_DLY_TAP_VALUE[0] + end + attribute \keep 1 + cell \I_FAB $ifab_$obuf_DLY_TAP_VALUE[1]_1 + connect \I $ifab_$obuf_DLY_TAP_VALUE[1] + connect \O $obuf_DLY_TAP_VALUE[1] + end + attribute \keep 1 + cell \I_FAB $ifab_$obuf_DLY_TAP_VALUE[2]_1 + connect \I $ifab_$obuf_DLY_TAP_VALUE[2] + connect \O $obuf_DLY_TAP_VALUE[2] + end + attribute \keep 1 + cell \I_FAB $ifab_$obuf_DLY_TAP_VALUE[3]_1 + connect \I $ifab_$obuf_DLY_TAP_VALUE[3] + connect \O $obuf_DLY_TAP_VALUE[3] + end + attribute \keep 1 + cell \I_FAB $ifab_$obuf_DLY_TAP_VALUE[4]_1 + connect \I $ifab_$obuf_DLY_TAP_VALUE[4] + connect \O $obuf_DLY_TAP_VALUE[4] + end + attribute \keep 1 + cell \I_FAB $ifab_$obuf_DLY_TAP_VALUE[5]_1 + connect \I $ifab_$obuf_DLY_TAP_VALUE[5] + connect \O $obuf_DLY_TAP_VALUE[5] + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" + cell \O_BUFT $obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE + connect \I $f2g_tx_out_$obuf_DLY_TAP_VALUE[0] + connect \O \DLY_TAP_VALUE [0] + connect \T 1'1 + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" + cell \O_BUFT $obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_1 + connect \I $f2g_tx_out_$obuf_DLY_TAP_VALUE[1] + connect \O \DLY_TAP_VALUE [1] + connect \T 1'1 + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" + cell \O_BUFT $obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_2 + connect \I $f2g_tx_out_$obuf_DLY_TAP_VALUE[2] + connect \O \DLY_TAP_VALUE [2] + connect \T 1'1 + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" + cell \O_BUFT $obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_3 + connect \I $f2g_tx_out_$obuf_DLY_TAP_VALUE[3] + connect \O \DLY_TAP_VALUE [3] + connect \T 1'1 + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" + cell \O_BUFT $obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_4 + connect \I $f2g_tx_out_$obuf_DLY_TAP_VALUE[4] + connect \O \DLY_TAP_VALUE [4] + connect \T 1'1 + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" + cell \O_BUFT $obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_5 + connect \I $f2g_tx_out_$obuf_DLY_TAP_VALUE[5] + connect \O \DLY_TAP_VALUE [5] + connect \T 1'1 + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" + cell \O_BUFT $obuf$I_DELAY_primitive_inst.$obuf_O + connect \I $obuf_O + connect \O \O + connect \T 1'1 + end + attribute \module_not_derived 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:18.3-26.2" + cell \I_DELAY \inst + parameter signed \DELAY 0 + connect \CLK_IN $clk_buf_$ibuf_CLK_IN + connect \DLY_ADJ $f2g_trx_dly_adj_$ibuf_DLY_ADJ + connect \DLY_INCDEC $f2g_trx_dly_inc_$ibuf_DLY_INCDEC + connect \DLY_LOAD $f2g_trx_dly_ld_$ibuf_DLY_LOAD + connect \DLY_TAP_VALUE { $ifab_$obuf_DLY_TAP_VALUE[5] $ifab_$obuf_DLY_TAP_VALUE[4] $ifab_$obuf_DLY_TAP_VALUE[3] $ifab_$obuf_DLY_TAP_VALUE[2] $ifab_$obuf_DLY_TAP_VALUE[1] $ifab_$obuf_DLY_TAP_VALUE[0] } + connect \I \dff + connect \O $obuf_O + end +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:359.1-363.10" +module \I_FAB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:360.15-360.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:361.16-361.17" + wire output 2 \O +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:373.1-392.10" +module \I_SERDES + parameter \DATA_RATE "SDR" + parameter \WIDTH 4 + parameter \DPA_MODE "NONE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:380.15-380.26" + wire input 3 \BITSLIP_ADJ + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:383.15-383.21" + wire input 5 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:384.16-384.23" + wire output 6 \CLK_OUT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:378.15-378.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:386.16-386.26" + wire output 8 \DATA_VALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:388.16-388.25" + wire output 10 \DPA_ERROR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:387.16-387.24" + wire output 9 \DPA_LOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:381.15-381.17" + wire input 4 \EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:390.15-390.22" + wire input 12 \PLL_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:389.15-389.23" + wire input 11 \PLL_LOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:385.28-385.29" + wire width 4 output 7 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:379.15-379.18" + wire input 2 \RST +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1040.1-1045.10" +module \LATCH + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1041.9-1041.10" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1042.9-1042.10" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1043.10-1043.11" + wire output 3 \Q +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1053.1-1058.10" +module \LATCHN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1054.9-1054.10" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1055.9-1055.10" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1056.10-1056.11" + wire output 3 \Q +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1096.1-1102.10" +module \LATCHNR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1097.9-1097.10" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1098.9-1098.10" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1099.10-1099.11" + wire output 4 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1100.9-1100.10" + wire input 3 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1111.1-1117.10" +module \LATCHNS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1112.9-1112.10" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1113.9-1113.10" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1114.10-1114.11" + wire output 4 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1115.9-1115.10" + wire input 3 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:265.1-285.10" +module \LATCHNSRE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:266.9-266.10" + wire input 4 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:267.9-267.10" + wire input 6 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:268.9-268.10" + wire input 5 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:269.10-269.11" + wire output 1 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:270.9-270.10" + wire input 3 \R + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:271.9-271.10" + wire input 2 \S +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1067.1-1073.10" +module \LATCHR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1068.9-1068.10" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1069.9-1069.10" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1070.10-1070.11" + wire output 4 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1071.9-1071.10" + wire input 3 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1081.1-1087.10" +module \LATCHS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1082.9-1082.10" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1083.9-1083.10" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1084.10-1084.11" + wire output 4 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1085.9-1085.10" + wire input 3 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:223.1-243.10" +module \LATCHSRE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:224.9-224.10" + wire input 4 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:225.9-225.10" + wire input 6 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:226.9-226.10" + wire input 5 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:227.10-227.11" + wire output 1 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:228.9-228.10" + wire input 3 \R + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:229.9-229.10" + wire input 2 \S +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:402.1-408.10" +module \LUT1 + parameter \INIT_VALUE 2'00 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:405.15-405.16" + wire input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:406.16-406.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:418.1-424.10" +module \LUT2 + parameter \INIT_VALUE 4'0000 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:421.21-421.22" + wire width 2 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:422.16-422.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:434.1-440.10" +module \LUT3 + parameter \INIT_VALUE 8'00000000 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:437.21-437.22" + wire width 3 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:438.16-438.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:450.1-456.10" +module \LUT4 + parameter \INIT_VALUE 16'0000000000000000 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:453.21-453.22" + wire width 4 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:454.16-454.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:466.1-472.10" +module \LUT5 + parameter \INIT_VALUE 0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:469.21-469.22" + wire width 5 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:470.16-470.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:482.1-488.10" +module \LUT6 + parameter \INIT_VALUE 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:485.21-485.22" + wire width 6 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:486.16-486.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:563.1-574.10" +module \O_BUF + parameter \IOSTANDARD "DEFAULT" + parameter \DRIVE_STRENGTH 2 + parameter \SLEW_RATE "SLOW" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:570.15-570.16" + wire input 1 \I + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:572.16-572.17" + wire output 2 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:542.1-553.10" +module \O_BUFT + parameter \WEAK_KEEPER "NONE" + parameter \IOSTANDARD "DEFAULT" + parameter \DRIVE_STRENGTH 2 + parameter \SLEW_RATE "SLOW" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:548.15-548.16" + wire input 1 \I + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:551.16-551.17" + wire output 3 \O + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:549.15-549.16" + wire input 2 \T +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:520.1-532.10" +module \O_BUFT_DS + parameter \WEAK_KEEPER "NONE" + parameter \IOSTANDARD "DEFAULT" + parameter \DIFFERENTIAL_TERMINATION "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:525.15-525.16" + wire input 1 \I + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:530.16-530.19" + wire output 4 \O_N + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:528.16-528.19" + wire output 3 \O_P + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:526.15-526.16" + wire input 2 \T +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:498.1-510.10" +module \O_BUF_DS + parameter \IOSTANDARD "DEFAULT" + parameter \DIFFERENTIAL_TERMINATION "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:504.15-504.16" + wire input 1 \I + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:508.16-508.19" + wire output 3 \O_N + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:506.16-506.19" + wire output 2 \O_P +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:584.1-592.10" +module \O_DDR + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:589.15-589.16" + wire input 4 \C + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:585.21-585.22" + wire width 2 input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:587.15-587.16" + wire input 3 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:590.14-590.15" + wire output 5 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:586.15-586.16" + wire input 2 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:602.1-614.10" +module \O_DELAY + parameter \DELAY 0 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:611.15-611.21" + wire input 6 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:607.15-607.22" + wire input 3 \DLY_ADJ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:608.15-608.25" + wire input 4 \DLY_INCDEC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:606.15-606.23" + wire input 2 \DLY_LOAD + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:609.22-609.35" + wire width 6 output 5 \DLY_TAP_VALUE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:605.15-605.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:612.16-612.17" + wire output 7 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:624.1-628.10" +module \O_FAB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:625.15-625.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:626.16-626.17" + wire output 2 \O +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:657.1-674.10" +module \O_SERDES + parameter \DATA_RATE "SDR" + parameter \WIDTH 4 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:669.15-669.35" + wire input 8 \CHANNEL_BOND_SYNC_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:670.16-670.37" + wire output 9 \CHANNEL_BOND_SYNC_OUT + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:665.15-665.21" + wire input 4 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:661.27-661.28" + wire width 4 input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:663.15-663.25" + wire input 3 \DATA_VALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:666.15-666.20" + wire input 5 \OE_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:667.16-667.22" + wire output 6 \OE_OUT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:672.15-672.22" + wire input 11 \PLL_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:671.15-671.23" + wire input 10 \PLL_LOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:668.16-668.17" + wire output 7 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:662.15-662.18" + wire input 2 \RST +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:638.1-647.10" +module \O_SERDES_CLK + parameter \DATA_RATE "SDR" + parameter \CLOCK_PHASE 0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:642.15-642.21" + wire input 1 \CLK_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:643.14-643.24" + wire output 2 \OUTPUT_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:645.15-645.22" + wire input 4 \PLL_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:644.15-644.23" + wire input 3 \PLL_LOCK +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:684.1-702.10" +module \PLL + parameter \DEV_FAMILY "VIRGO" + parameter \DIVIDE_CLK_IN_BY_2 "FALSE" + parameter \PLL_MULT 16 + parameter \PLL_DIV 1 + parameter \PLL_MULT_FRAC 0 + parameter \PLL_POST_DIV 17 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:694.15-694.21" + wire input 2 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:695.16-695.23" + wire output 3 \CLK_OUT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:696.16-696.28" + wire output 4 \CLK_OUT_DIV2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:697.16-697.28" + wire output 5 \CLK_OUT_DIV3 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:698.16-698.28" + wire output 6 \CLK_OUT_DIV4 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:699.16-699.24" + wire output 7 \FAST_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:700.16-700.20" + wire output 8 \LOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:692.15-692.21" + wire input 1 \PLL_EN +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:89.1-111.10" +module \RS_DSP3 + parameter \MODE_BITS 93'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \DSP_CLK "" + parameter \DSP_RST "" + parameter \DSP_RST_POL "" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:90.24-90.25" + wire width 20 input 1 \a + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:92.24-92.31" + wire width 6 input 3 \acc_fir + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:91.24-91.25" + wire width 18 input 2 \b + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:97.23-97.26" + wire input 6 \clk + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:94.24-94.29" + wire width 18 output 5 \dly_b + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:100.23-100.31" + wire width 3 input 8 \feedback + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:101.23-101.31" + wire input 9 \load_acc + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:98.23-98.28" + wire input 7 \reset + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:104.23-104.31" + wire input 12 \subtract + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:102.23-102.33" + wire input 10 \unsigned_a + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:103.23-103.33" + wire input 11 \unsigned_b + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:93.24-93.25" + wire width 38 output 4 \z +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:712.1-726.10" +module \SOC_FPGA_INTF_AHB_M + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:714.22-714.27" + wire width 32 input 2 \HADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:715.21-715.27" + wire width 3 input 3 \HBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:724.15-724.19" + wire input 12 \HCLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:716.21-716.26" + wire width 4 input 4 \HPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:721.23-721.29" + wire width 32 output 9 \HRDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:722.16-722.22" + wire output 10 \HREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:713.15-713.24" + wire input 1 \HRESETN_I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:723.16-723.21" + wire output 11 \HRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:717.21-717.26" + wire width 3 input 5 \HSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:718.21-718.27" + wire width 3 input 6 \HTRANS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:719.22-719.28" + wire width 32 input 7 \HWDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:720.15-720.22" + wire input 8 \HWWRITE +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:736.1-753.10" +module \SOC_FPGA_INTF_AHB_S + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:738.23-738.28" + wire width 32 output 2 \HADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:739.22-739.28" + wire width 3 output 3 \HBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:751.15-751.19" + wire input 15 \HCLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:740.16-740.25" + wire output 4 \HMASTLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:742.22-742.27" + wire width 4 output 6 \HPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:743.22-743.28" + wire width 32 input 7 \HRDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:741.15-741.21" + wire input 5 \HREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:737.16-737.25" + wire output 1 \HRESETN_I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:744.15-744.20" + wire input 8 \HRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:745.16-745.20" + wire output 9 \HSEL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:746.22-746.27" + wire width 3 output 10 \HSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:747.22-747.28" + wire width 2 output 11 \HTRANS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:748.22-748.26" + wire width 4 output 12 \HWBE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:749.23-749.29" + wire width 32 output 13 \HWDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:750.16-750.22" + wire output 14 \HWRITE +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:763.1-802.10" +module \SOC_FPGA_INTF_AXI_M0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:799.15-799.22" + wire input 36 \M0_ACLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:764.22-764.31" + wire width 32 input 1 \M0_ARADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:765.21-765.31" + wire width 2 input 2 \M0_ARBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:766.21-766.31" + wire width 4 input 3 \M0_ARCACHE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:800.16-800.28" + wire output 37 \M0_ARESETN_I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:767.21-767.28" + wire width 4 input 4 \M0_ARID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:768.21-768.29" + wire width 3 input 5 \M0_ARLEN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:769.15-769.24" + wire input 6 \M0_ARLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:770.21-770.30" + wire width 3 input 7 \M0_ARPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:771.16-771.26" + wire output 8 \M0_ARREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:772.21-772.30" + wire width 3 input 9 \M0_ARSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:773.15-773.25" + wire input 10 \M0_ARVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:774.22-774.31" + wire width 32 input 11 \M0_AWADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:775.21-775.31" + wire width 2 input 12 \M0_AWBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:776.21-776.31" + wire width 4 input 13 \M0_AWCACHE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:777.21-777.28" + wire width 4 input 14 \M0_AWID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:778.21-778.29" + wire width 3 input 15 \M0_AWLEN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:779.15-779.24" + wire input 16 \M0_AWLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:780.21-780.30" + wire width 3 input 17 \M0_AWPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:781.16-781.26" + wire output 18 \M0_AWREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:782.21-782.30" + wire width 3 input 19 \M0_AWSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:783.15-783.25" + wire input 20 \M0_AWVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:784.22-784.28" + wire width 4 output 21 \M0_BID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:785.15-785.24" + wire input 22 \M0_BREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:786.22-786.30" + wire width 2 output 23 \M0_BRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:787.16-787.25" + wire output 24 \M0_BVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:788.23-788.31" + wire width 64 output 25 \M0_RDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:789.22-789.28" + wire width 4 output 26 \M0_RID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:790.16-790.24" + wire output 27 \M0_RLAST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:791.15-791.24" + wire input 28 \M0_RREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:792.22-792.30" + wire width 2 output 29 \M0_RRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:793.16-793.25" + wire output 30 \M0_RVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:794.22-794.30" + wire width 64 input 31 \M0_WDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:795.15-795.23" + wire input 32 \M0_WLAST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:796.16-796.25" + wire output 33 \M0_WREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:797.21-797.29" + wire width 8 input 34 \M0_WSTRB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:798.15-798.24" + wire input 35 \M0_WVALID +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:812.1-851.10" +module \SOC_FPGA_INTF_AXI_M1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:848.15-848.22" + wire input 36 \M1_ACLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:813.22-813.31" + wire width 32 input 1 \M1_ARADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:814.21-814.31" + wire width 2 input 2 \M1_ARBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:815.21-815.31" + wire width 4 input 3 \M1_ARCACHE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:849.16-849.28" + wire output 37 \M1_ARESETN_I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:816.21-816.28" + wire width 4 input 4 \M1_ARID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:817.21-817.29" + wire width 3 input 5 \M1_ARLEN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:818.15-818.24" + wire input 6 \M1_ARLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:819.21-819.30" + wire width 3 input 7 \M1_ARPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:820.16-820.26" + wire output 8 \M1_ARREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:821.21-821.30" + wire width 3 input 9 \M1_ARSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:822.15-822.25" + wire input 10 \M1_ARVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:823.22-823.31" + wire width 32 input 11 \M1_AWADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:824.21-824.31" + wire width 2 input 12 \M1_AWBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:825.21-825.31" + wire width 4 input 13 \M1_AWCACHE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:826.21-826.28" + wire width 4 input 14 \M1_AWID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:827.21-827.29" + wire width 3 input 15 \M1_AWLEN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:828.15-828.24" + wire input 16 \M1_AWLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:829.21-829.30" + wire width 3 input 17 \M1_AWPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:830.16-830.26" + wire output 18 \M1_AWREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:831.21-831.30" + wire width 3 input 19 \M1_AWSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:832.15-832.25" + wire input 20 \M1_AWVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:833.22-833.28" + wire width 4 output 21 \M1_BID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:834.15-834.24" + wire input 22 \M1_BREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:835.22-835.30" + wire width 2 output 23 \M1_BRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:836.16-836.25" + wire output 24 \M1_BVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:837.23-837.31" + wire width 64 output 25 \M1_RDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:838.22-838.28" + wire width 4 output 26 \M1_RID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:839.16-839.24" + wire output 27 \M1_RLAST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:840.15-840.24" + wire input 28 \M1_RREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:841.22-841.30" + wire width 2 output 29 \M1_RRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:842.16-842.25" + wire output 30 \M1_RVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:843.22-843.30" + wire width 64 input 31 \M1_WDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:844.15-844.23" + wire input 32 \M1_WLAST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:845.16-845.25" + wire output 33 \M1_WREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:846.21-846.29" + wire width 8 input 34 \M1_WSTRB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:847.15-847.24" + wire input 35 \M1_WVALID +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:861.1-867.10" +module \SOC_FPGA_INTF_DMA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:863.22-863.29" + wire width 4 output 2 \DMA_ACK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:864.15-864.22" + wire input 3 \DMA_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:862.21-862.28" + wire width 4 input 1 \DMA_REQ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:865.15-865.24" + wire input 4 \DMA_RST_N +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:877.1-883.10" +module \SOC_FPGA_INTF_IRQ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:880.15-880.22" + wire input 3 \IRQ_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:881.15-881.24" + wire input 4 \IRQ_RST_N + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:879.23-879.30" + wire width 16 output 2 \IRQ_SET + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:878.22-878.29" + wire width 16 input 1 \IRQ_SRC +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:893.1-901.10" +module \SOC_FPGA_INTF_JTAG + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:899.15-899.27" + wire input 6 \BOOT_JTAG_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:894.15-894.28" + wire input 1 \BOOT_JTAG_TCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:895.14-895.27" + wire output 2 \BOOT_JTAG_TDI + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:896.15-896.28" + wire input 3 \BOOT_JTAG_TDO + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:897.14-897.27" + wire output 4 \BOOT_JTAG_TMS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:898.14-898.29" + wire output 5 \BOOT_JTAG_TRSTN +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:911.1-919.10" +module \SOC_FPGA_TEMPERATURE + parameter \INITIAL_TEMPERATURE 25 + parameter \TEMPERATURE_FILE "" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:917.14-917.19" + wire output 3 \ERROR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:915.20-915.31" + wire width 8 output 1 \TEMPERATURE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:916.14-916.19" + wire output 2 \VALID +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:7.1-110.10" +module \TDP_BRAM18 + parameter \INITP_00 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_01 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_02 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_03 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_04 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_05 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_06 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_07 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_00 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_01 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_02 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_03 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_04 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_05 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_06 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_07 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_08 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_09 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0B 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0C 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0D 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0E 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0F 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_10 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_11 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_12 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_13 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_14 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_15 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_16 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_17 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_18 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_19 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1B 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1C 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1D 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1E 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1F 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_20 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_21 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_22 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_23 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_24 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_25 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_26 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_27 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_28 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_29 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2B 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2C 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2D 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2E 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2F 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_30 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_31 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_32 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_33 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_34 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_35 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_36 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_37 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_38 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_39 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3B 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3C 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3D 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3E 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3F 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \READ_WIDTH_A 0 + parameter \READ_WIDTH_B 0 + parameter \WRITE_WIDTH_A 0 + parameter \WRITE_WIDTH_B 0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:14.23-14.28" + wire width 14 input 5 \ADDRA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:15.23-15.28" + wire width 14 input 6 \ADDRB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:22.22-22.33" + wire width 2 input 13 \BYTEENABLEA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:23.22-23.33" + wire width 2 input 14 \BYTEENABLEB + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:9.16-9.22" + wire input 1 \CLOCKA + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:11.16-11.22" + wire input 2 \CLOCKB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:28.24-28.33" + wire width 16 output 15 \READDATAA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:30.23-30.33" + wire width 2 output 17 \READDATAAP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:29.24-29.33" + wire width 16 output 16 \READDATAB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:31.23-31.33" + wire width 2 output 18 \READDATABP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:12.16-12.27" + wire input 3 \READENABLEA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:13.16-13.27" + wire input 4 \READENABLEB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:16.23-16.33" + wire width 16 input 7 \WRITEDATAA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:18.22-18.33" + wire width 2 input 9 \WRITEDATAAP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:17.23-17.33" + wire width 16 input 8 \WRITEDATAB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:19.22-19.33" + wire width 2 input 10 \WRITEDATABP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:20.16-20.28" + wire input 11 \WRITEENABLEA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:21.16-21.28" + wire input 12 \WRITEENABLEB +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:929.1-984.10" +module \TDP_RAM18KX2 + parameter \INIT1 16384'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT1_PARITY 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \WRITE_WIDTH_A1 18 + parameter \WRITE_WIDTH_B1 18 + parameter \READ_WIDTH_A1 18 + parameter \READ_WIDTH_B1 18 + parameter \INIT2 16384'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT2_PARITY 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \WRITE_WIDTH_A2 18 + parameter \WRITE_WIDTH_B2 18 + parameter \READ_WIDTH_A2 18 + parameter \READ_WIDTH_B2 18 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:953.22-953.29" + wire width 14 input 9 \ADDR_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:973.22-973.29" + wire width 14 input 27 \ADDR_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:954.22-954.29" + wire width 14 input 10 \ADDR_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:974.22-974.29" + wire width 14 input 28 \ADDR_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:951.21-951.26" + wire width 2 input 7 \BE_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:971.21-971.26" + wire width 2 input 25 \BE_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:952.21-952.26" + wire width 2 input 8 \BE_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:972.21-972.26" + wire width 2 input 26 \BE_B2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:948.15-948.21" + wire input 5 \CLK_A1 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:968.15-968.21" + wire input 23 \CLK_A2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:950.15-950.21" + wire input 6 \CLK_B1 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:970.15-970.21" + wire input 24 \CLK_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:959.21-959.29" + wire width 16 output 15 \RDATA_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:979.21-979.29" + wire width 16 output 33 \RDATA_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:961.21-961.29" + wire width 16 output 17 \RDATA_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:981.21-981.29" + wire width 16 output 35 \RDATA_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:945.15-945.21" + wire input 3 \REN_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:965.15-965.21" + wire input 21 \REN_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:946.15-946.21" + wire input 4 \REN_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:966.15-966.21" + wire input 22 \REN_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:960.20-960.30" + wire width 2 output 16 \RPARITY_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:980.20-980.30" + wire width 2 output 34 \RPARITY_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:962.20-962.30" + wire width 2 output 18 \RPARITY_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:982.20-982.30" + wire width 2 output 36 \RPARITY_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:955.22-955.30" + wire width 16 input 11 \WDATA_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:975.22-975.30" + wire width 16 input 29 \WDATA_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:957.22-957.30" + wire width 16 input 13 \WDATA_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:977.22-977.30" + wire width 16 input 31 \WDATA_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:943.15-943.21" + wire input 1 \WEN_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:963.15-963.21" + wire input 19 \WEN_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:944.15-944.21" + wire input 2 \WEN_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:964.15-964.21" + wire input 20 \WEN_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:956.21-956.31" + wire width 2 input 12 \WPARITY_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:976.21-976.31" + wire width 2 input 30 \WPARITY_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:958.21-958.31" + wire width 2 input 14 \WPARITY_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:978.21-978.31" + wire width 2 input 32 \WPARITY_B2 +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:994.1-1023.10" +module \TDP_RAM36K + parameter \INIT 32768'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_PARITY 4096'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \WRITE_WIDTH_A 36 + parameter \READ_WIDTH_A 36 + parameter \WRITE_WIDTH_B 36 + parameter \READ_WIDTH_B 36 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1012.22-1012.28" + wire width 15 input 9 \ADDR_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1013.22-1013.28" + wire width 15 input 10 \ADDR_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1010.21-1010.25" + wire width 4 input 7 \BE_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1011.21-1011.25" + wire width 4 input 8 \BE_B + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1007.15-1007.20" + wire input 5 \CLK_A + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1009.15-1009.20" + wire input 6 \CLK_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1018.21-1018.28" + wire width 32 output 15 \RDATA_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1020.21-1020.28" + wire width 32 output 17 \RDATA_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1004.15-1004.20" + wire input 3 \REN_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1005.15-1005.20" + wire input 4 \REN_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1019.20-1019.29" + wire width 4 output 16 \RPARITY_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1021.20-1021.29" + wire width 4 output 18 \RPARITY_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1014.22-1014.29" + wire width 32 input 11 \WDATA_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1016.22-1016.29" + wire width 32 input 13 \WDATA_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1002.15-1002.20" + wire input 1 \WEN_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1003.15-1003.20" + wire input 2 \WEN_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1015.21-1015.30" + wire width 4 input 12 \WPARITY_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1017.21-1017.30" + wire width 4 input 14 \WPARITY_B +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:953.1-1356.10" +module \_$_mem_v2_asymmetric + parameter \CFG_ABITS 10 + parameter \CFG_DBITS 36 + parameter \CFG_ENABLE_B 4 + parameter \READ_ADDR_WIDTH 11 + parameter \READ_DATA_WIDTH 16 + parameter \WRITE_ADDR_WIDTH 10 + parameter \WRITE_DATA_WIDTH 32 + parameter \ABITS 0 + parameter \MEMID 0 + parameter \INIT 36864'x + parameter \OFFSET 0 + parameter \RD_ARST_VALUE 0 + parameter \RD_CE_OVER_SRST 0 + parameter \RD_CLK_ENABLE 0 + parameter \RD_CLK_POLARITY 0 + parameter \RD_COLLISION_X_MASK 0 + parameter \RD_PORTS 0 + parameter \RD_SRST_VALUE 0 + parameter \RD_TRANSPARENCY_MASK 0 + parameter \RD_WIDE_CONTINUATION 0 + parameter \SIZE 0 + parameter \WIDTH 0 + parameter \WR_CLK_ENABLE 0 + parameter \WR_CLK_POLARITY 0 + parameter \WR_PORTS 0 + parameter \WR_PRIORITY_MASK 0 + parameter \WR_WIDE_CONTINUATION 0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:998.27-998.34" + wire width 10 input 1 \RD_ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:995.11-995.18" + wire input 2 \RD_ARST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:993.11-993.17" + wire input 3 \RD_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:999.28-999.35" + wire width 36 output 4 \RD_DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:1000.11-1000.16" + wire input 5 \RD_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:996.11-996.18" + wire input 6 \RD_SRST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:1002.27-1002.34" + wire width 10 input 7 \WR_ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:994.11-994.17" + wire input 8 \WR_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:1003.27-1003.34" + wire width 36 input 9 \WR_DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:1004.30-1004.35" + wire width 4 input 10 \WR_EN +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v:11.1-16.10" +module \buff + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v:13.12-13.13" + wire input 2 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v:12.12-12.13" + wire output 1 \Q +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v:31.1-38.10" +module \gclkbuff + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v:32.12-32.13" + wire input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v:33.12-33.13" + wire output 2 \Z +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v:4.1-9.10" +module \inv + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v:6.12-6.13" + wire input 2 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v:5.12-5.13" + wire output 1 \Q +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v:18.1-22.10" +module \logic_0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v:19.12-19.13" + wire output 1 \a +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v:24.1-28.10" +module \logic_1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v:25.12-25.13" + wire output 1 \a +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:8.1-15.12" +module \rs__CLK_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:9.13-9.14" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:10.13-10.14" + wire output 2 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:54.1-64.10" +module \rs__IO_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:56.13-56.14" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:58.13-58.15" + wire inout 3 \IO + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:59.13-59.14" + wire output 4 \O + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:57.13-57.14" + wire input 2 \T +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:23.3-34.10" +module \rs__I_BUF + parameter \WEAK_KEEPER "NONE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:27.12-27.14" + wire input 2 \EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:26.12-26.13" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:28.13-28.14" + wire output 3 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:41.1-48.10" +module \rs__O_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:42.9-42.10" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:43.10-43.11" + wire output 2 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:70.1-80.10" +module \rs__O_BUFT + parameter \WEAK_KEEPER "NONE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:73.13-73.14" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:75.13-75.14" + wire output 3 \O + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:74.13-74.14" + wire input 2 \T +end diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/design_edit.sdc b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/design_edit.sdc new file mode 100644 index 00000000..6434ecd1 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/design_edit.sdc @@ -0,0 +1,155 @@ +############# +# +# Fabric clock assignment +# +############# +# This clock need to route to fabric slot #0 +# set_clock_pin -device_clock clk[0] -design_clock CLK_IN (Physical port name, clock module: CLK_BUF $clkbuf$I_DELAY_primitive_inst.$ibuf_CLK_IN) +# set_clock_pin -device_clock clk[0] -design_clock $clk_buf_$ibuf_CLK_IN (Original clock primitive out-net to fabric) +set_clock_pin -device_clock clk[0] -design_clock $clk_buf_$ibuf_CLK_IN + +############# +# +# Each pin mode and location assignment +# +############# +# Pin location is not assigned +# Pin CLK_IN :: I_BUF |-> CLK_BUF + +# Pin location is not assigned +# Pin DLY_ADJ :: I_BUF + +# Pin location is not assigned +# Pin DLY_INCDEC :: I_BUF + +# Pin location is not assigned +# Pin DLY_LOAD :: I_BUF + +# Pin location is not assigned +# Pin in :: I_BUF + +# Pin location is not assigned +# Pin reset :: I_BUF + +# Pin location is not assigned +# Pin DLY_TAP_VALUE[0] :: O_BUFT + +# Pin location is not assigned +# Pin DLY_TAP_VALUE[1] :: O_BUFT + +# Pin location is not assigned +# Pin DLY_TAP_VALUE[2] :: O_BUFT + +# Pin location is not assigned +# Pin DLY_TAP_VALUE[3] :: O_BUFT + +# Pin location is not assigned +# Pin DLY_TAP_VALUE[4] :: O_BUFT + +# Pin location is not assigned +# Pin DLY_TAP_VALUE[5] :: O_BUFT + +# Pin location is not assigned +# Pin O :: O_BUFT + +############# +# +# Internal Control Signals +# +############# +# Module: I_BUF +# LinkedObject: CLK_IN +# Location: +# Port: EN +# Signal: in:f2g_in_en_{A|B} +# Skip reason: Location does not have any mode to begin with + +# Module: I_BUF +# LinkedObject: DLY_ADJ +# Location: +# Port: EN +# Signal: in:f2g_in_en_{A|B} +# Skip reason: Location does not have any mode to begin with + +# Module: I_BUF +# LinkedObject: DLY_INCDEC +# Location: +# Port: EN +# Signal: in:f2g_in_en_{A|B} +# Skip reason: Location does not have any mode to begin with + +# Module: I_BUF +# LinkedObject: DLY_LOAD +# Location: +# Port: EN +# Signal: in:f2g_in_en_{A|B} +# Skip reason: Location does not have any mode to begin with + +# Module: I_BUF +# LinkedObject: in +# Location: +# Port: EN +# Signal: in:f2g_in_en_{A|B} +# Skip reason: Location does not have any mode to begin with + +# Module: I_BUF +# LinkedObject: reset +# Location: +# Port: EN +# Signal: in:f2g_in_en_{A|B} +# Skip reason: Location does not have any mode to begin with + +# Module: O_BUFT +# LinkedObject: DLY_TAP_VALUE[0] +# Location: +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +# Skip reason: Location does not have any mode to begin with + +# Module: O_BUFT +# LinkedObject: DLY_TAP_VALUE[1] +# Location: +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +# Skip reason: Location does not have any mode to begin with + +# Module: O_BUFT +# LinkedObject: DLY_TAP_VALUE[2] +# Location: +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +# Skip reason: Location does not have any mode to begin with + +# Module: O_BUFT +# LinkedObject: DLY_TAP_VALUE[3] +# Location: +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +# Skip reason: Location does not have any mode to begin with + +# Module: O_BUFT +# LinkedObject: DLY_TAP_VALUE[4] +# Location: +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +# Skip reason: Location does not have any mode to begin with + +# Module: O_BUFT +# LinkedObject: DLY_TAP_VALUE[5] +# Location: +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +# Skip reason: Location does not have any mode to begin with + +# Module: O_BUFT +# LinkedObject: O +# Location: +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +# Skip reason: Location does not have any mode to begin with + +############# +# +# Each gearbox core clock +# +############# diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif new file mode 100644 index 00000000..f548be5f --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif @@ -0,0 +1,56 @@ +# Generated by Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) + +.model fabric_I_DELAY_primitive_inst +.inputs $clk_buf_$ibuf_CLK_IN $ibuf_DLY_ADJ $ibuf_DLY_INCDEC $ibuf_DLY_LOAD $ibuf_in $ibuf_reset $ifab_$obuf_DLY_TAP_VALUE[0] $ifab_$obuf_DLY_TAP_VALUE[1] $ifab_$obuf_DLY_TAP_VALUE[2] $ifab_$obuf_DLY_TAP_VALUE[3] $ifab_$obuf_DLY_TAP_VALUE[4] $ifab_$obuf_DLY_TAP_VALUE[5] $obuf_O +.outputs $auto_440 $auto_441 $auto_442 $auto_443 $auto_444 $auto_445 $auto_446 $auto_447 $auto_448 $auto_449 $auto_450 $auto_451 $auto_452 $auto_453 $f2g_trx_dly_adj_$ibuf_DLY_ADJ $f2g_trx_dly_inc_$ibuf_DLY_INCDEC $f2g_trx_dly_ld_$ibuf_DLY_LOAD $f2g_tx_out_$obuf_DLY_TAP_VALUE[0] $f2g_tx_out_$obuf_DLY_TAP_VALUE[1] $f2g_tx_out_$obuf_DLY_TAP_VALUE[2] $f2g_tx_out_$obuf_DLY_TAP_VALUE[3] $f2g_tx_out_$obuf_DLY_TAP_VALUE[4] $f2g_tx_out_$obuf_DLY_TAP_VALUE[5] dff +.names $false +.names $true +1 +.names $undef +.subckt DFFRE C=$clk_buf_$ibuf_CLK_IN D=$abc$192$li0_li0 E=$true Q=dff R=$true +.subckt LUT2 A[0]=$ibuf_reset A[1]=$ibuf_in Y=$abc$192$li0_li0 +.param INIT_VALUE 0100 +.subckt O_FAB I=$ibuf_DLY_ADJ O=$f2g_trx_dly_adj_$ibuf_DLY_ADJ +.subckt O_FAB I=$ibuf_DLY_INCDEC O=$f2g_trx_dly_inc_$ibuf_DLY_INCDEC +.subckt O_FAB I=$ibuf_DLY_LOAD O=$f2g_trx_dly_ld_$ibuf_DLY_LOAD +.subckt O_FAB I=$obuf_DLY_TAP_VALUE[0] O=$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] +.subckt O_FAB I=$obuf_DLY_TAP_VALUE[1] O=$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] +.subckt O_FAB I=$obuf_DLY_TAP_VALUE[2] O=$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] +.subckt O_FAB I=$obuf_DLY_TAP_VALUE[3] O=$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] +.subckt O_FAB I=$obuf_DLY_TAP_VALUE[4] O=$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] +.subckt O_FAB I=$obuf_DLY_TAP_VALUE[5] O=$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] +.subckt I_FAB I=$ifab_$obuf_DLY_TAP_VALUE[0] O=$obuf_DLY_TAP_VALUE[0] +.subckt I_FAB I=$ifab_$obuf_DLY_TAP_VALUE[1] O=$obuf_DLY_TAP_VALUE[1] +.subckt I_FAB I=$ifab_$obuf_DLY_TAP_VALUE[2] O=$obuf_DLY_TAP_VALUE[2] +.subckt I_FAB I=$ifab_$obuf_DLY_TAP_VALUE[3] O=$obuf_DLY_TAP_VALUE[3] +.subckt I_FAB I=$ifab_$obuf_DLY_TAP_VALUE[4] O=$obuf_DLY_TAP_VALUE[4] +.subckt I_FAB I=$ifab_$obuf_DLY_TAP_VALUE[5] O=$obuf_DLY_TAP_VALUE[5] +.names $true $auto_444 +1 1 +.names $true $auto_443 +1 1 +.names $true $auto_442 +1 1 +.names $true $auto_441 +1 1 +.names $true $auto_440 +1 1 +.names $obuf_O $auto_453 +1 1 +.names $true $auto_447 +1 1 +.names $true $auto_448 +1 1 +.names $true $auto_449 +1 1 +.names $true $auto_451 +1 1 +.names $true $auto_445 +1 1 +.names $true $auto_446 +1 1 +.names $true $auto_450 +1 1 +.names $true $auto_452 +1 1 +.end diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.v b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.v new file mode 100644 index 00000000..8cac0dbd --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.v @@ -0,0 +1,246 @@ +/* Generated by Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) */ + +module fabric_I_DELAY_primitive_inst(\$auto_440 , \$auto_441 , \$auto_442 , \$auto_443 , \$auto_444 , \$auto_445 , \$auto_446 , \$auto_447 , \$auto_448 , \$auto_449 , \$auto_450 , \$auto_451 , \$auto_452 , \$auto_453 , \$clk_buf_$ibuf_CLK_IN , \$f2g_trx_dly_adj_$ibuf_DLY_ADJ , \$f2g_trx_dly_inc_$ibuf_DLY_INCDEC , \$f2g_trx_dly_ld_$ibuf_DLY_LOAD , \$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] , \$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] , \$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] +, \$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] , \$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] , \$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] , \$ibuf_DLY_ADJ , \$ibuf_DLY_INCDEC , \$ibuf_DLY_LOAD , \$ibuf_in , \$ibuf_reset , \$ifab_$obuf_DLY_TAP_VALUE[0] , \$ifab_$obuf_DLY_TAP_VALUE[1] , \$ifab_$obuf_DLY_TAP_VALUE[2] , \$ifab_$obuf_DLY_TAP_VALUE[3] , \$ifab_$obuf_DLY_TAP_VALUE[4] , \$ifab_$obuf_DLY_TAP_VALUE[5] , \$obuf_O , dff); + output \$auto_440 ; + output \$auto_441 ; + output \$auto_442 ; + output \$auto_443 ; + output \$auto_444 ; + output \$auto_445 ; + output \$auto_446 ; + output \$auto_447 ; + output \$auto_448 ; + output \$auto_449 ; + output \$auto_450 ; + output \$auto_451 ; + output \$auto_452 ; + output \$auto_453 ; + input \$clk_buf_$ibuf_CLK_IN ; + output \$f2g_trx_dly_adj_$ibuf_DLY_ADJ ; + output \$f2g_trx_dly_inc_$ibuf_DLY_INCDEC ; + output \$f2g_trx_dly_ld_$ibuf_DLY_LOAD ; + output \$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] ; + output \$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] ; + output \$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] ; + output \$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] ; + output \$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] ; + output \$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] ; + input \$ibuf_DLY_ADJ ; + input \$ibuf_DLY_INCDEC ; + input \$ibuf_DLY_LOAD ; + input \$ibuf_in ; + input \$ibuf_reset ; + input \$ifab_$obuf_DLY_TAP_VALUE[0] ; + input \$ifab_$obuf_DLY_TAP_VALUE[1] ; + input \$ifab_$obuf_DLY_TAP_VALUE[2] ; + input \$ifab_$obuf_DLY_TAP_VALUE[3] ; + input \$ifab_$obuf_DLY_TAP_VALUE[4] ; + input \$ifab_$obuf_DLY_TAP_VALUE[5] ; + input \$obuf_O ; + output dff; + wire \$abc$192$li0_li0 ; + wire \$auto_440 ; + wire \$auto_441 ; + wire \$auto_442 ; + wire \$auto_443 ; + wire \$auto_444 ; + wire \$auto_445 ; + wire \$auto_446 ; + wire \$auto_447 ; + wire \$auto_448 ; + wire \$auto_449 ; + wire \$auto_450 ; + wire \$auto_451 ; + wire \$auto_452 ; + wire \$auto_453 ; + wire \$clk_buf_$ibuf_CLK_IN ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire \$f2g_trx_dly_adj_$ibuf_DLY_ADJ ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire \$f2g_trx_dly_inc_$ibuf_DLY_INCDEC ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire \$f2g_trx_dly_ld_$ibuf_DLY_LOAD ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire \$ibuf_DLY_ADJ ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire \$ibuf_DLY_INCDEC ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire \$ibuf_DLY_LOAD ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + wire \$ibuf_in ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + wire \$ibuf_reset ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[4] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[5] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$obuf_DLY_TAP_VALUE[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$obuf_DLY_TAP_VALUE[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$obuf_DLY_TAP_VALUE[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$obuf_DLY_TAP_VALUE[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$obuf_DLY_TAP_VALUE[4] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$obuf_DLY_TAP_VALUE[5] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + wire \$obuf_O ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:14.5-14.8" *) + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:14.5-14.8" *) + wire dff; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) + DFFRE \$abc$192$auto_193 ( + .C(\$clk_buf_$ibuf_CLK_IN ), + .D(\$abc$192$li0_li0 ), + .E(1'h1), + .Q(dff), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h4) + ) \$abc$424$auto_425 ( + .A({ \$ibuf_in , \$ibuf_reset }), + .Y(\$abc$192$li0_li0 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_adj_$ibuf_DLY_ADJ_1 ( + .I(\$ibuf_DLY_ADJ ), + .O(\$f2g_trx_dly_adj_$ibuf_DLY_ADJ ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_inc_$ibuf_DLY_INCDEC_1 ( + .I(\$ibuf_DLY_INCDEC ), + .O(\$f2g_trx_dly_inc_$ibuf_DLY_INCDEC ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_ld_$ibuf_DLY_LOAD_1 ( + .I(\$ibuf_DLY_LOAD ), + .O(\$f2g_trx_dly_ld_$ibuf_DLY_LOAD ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_$obuf_DLY_TAP_VALUE[0]_1 ( + .I(\$obuf_DLY_TAP_VALUE[0] ), + .O(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_$obuf_DLY_TAP_VALUE[1]_1 ( + .I(\$obuf_DLY_TAP_VALUE[1] ), + .O(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_$obuf_DLY_TAP_VALUE[2]_1 ( + .I(\$obuf_DLY_TAP_VALUE[2] ), + .O(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_$obuf_DLY_TAP_VALUE[3]_1 ( + .I(\$obuf_DLY_TAP_VALUE[3] ), + .O(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_$obuf_DLY_TAP_VALUE[4]_1 ( + .I(\$obuf_DLY_TAP_VALUE[4] ), + .O(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_$obuf_DLY_TAP_VALUE[5]_1 ( + .I(\$obuf_DLY_TAP_VALUE[5] ), + .O(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] ) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_$obuf_DLY_TAP_VALUE[0]_1 ( + .I(\$ifab_$obuf_DLY_TAP_VALUE[0] ), + .O(\$obuf_DLY_TAP_VALUE[0] ) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_$obuf_DLY_TAP_VALUE[1]_1 ( + .I(\$ifab_$obuf_DLY_TAP_VALUE[1] ), + .O(\$obuf_DLY_TAP_VALUE[1] ) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_$obuf_DLY_TAP_VALUE[2]_1 ( + .I(\$ifab_$obuf_DLY_TAP_VALUE[2] ), + .O(\$obuf_DLY_TAP_VALUE[2] ) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_$obuf_DLY_TAP_VALUE[3]_1 ( + .I(\$ifab_$obuf_DLY_TAP_VALUE[3] ), + .O(\$obuf_DLY_TAP_VALUE[3] ) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_$obuf_DLY_TAP_VALUE[4]_1 ( + .I(\$ifab_$obuf_DLY_TAP_VALUE[4] ), + .O(\$obuf_DLY_TAP_VALUE[4] ) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_$obuf_DLY_TAP_VALUE[5]_1 ( + .I(\$ifab_$obuf_DLY_TAP_VALUE[5] ), + .O(\$obuf_DLY_TAP_VALUE[5] ) + ); + assign \$auto_444 = 1'h1; + assign \$auto_443 = 1'h1; + assign \$auto_442 = 1'h1; + assign \$auto_441 = 1'h1; + assign \$auto_440 = 1'h1; + assign \$auto_453 = \$obuf_O ; + assign \$auto_447 = 1'h1; + assign \$auto_448 = 1'h1; + assign \$auto_449 = 1'h1; + assign \$auto_451 = 1'h1; + assign \$auto_445 = 1'h1; + assign \$auto_446 = 1'h1; + assign \$auto_450 = 1'h1; + assign \$auto_452 = 1'h1; +endmodule diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_netlist_info.json b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_netlist_info.json new file mode 100644 index 00000000..cc6221e9 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_netlist_info.json @@ -0,0 +1,9 @@ +{ + "ports": [ + { + "clock": "active_high", + "direction": "input", + "name": "$clk_buf_$ibuf_CLK_IN" + } + ] +} diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/io_config.json b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/io_config.json new file mode 100644 index 00000000..6aea68f3 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/io_config.json @@ -0,0 +1,620 @@ +{ + "status": false, + "messages": [ + "Start of IO Analysis", + " Get Ports", + " Detect input port \\CLK_IN (index=0, width=1, offset=0)", + " Detect input port \\DLY_ADJ (index=0, width=1, offset=0)", + " Detect input port \\DLY_INCDEC (index=0, width=1, offset=0)", + " Detect input port \\DLY_LOAD (index=0, width=1, offset=0)", + " Detect output port \\DLY_TAP_VALUE (index=0, width=6, offset=0)", + " Detect output port \\DLY_TAP_VALUE (index=1, width=6, offset=0)", + " Detect output port \\DLY_TAP_VALUE (index=2, width=6, offset=0)", + " Detect output port \\DLY_TAP_VALUE (index=3, width=6, offset=0)", + " Detect output port \\DLY_TAP_VALUE (index=4, width=6, offset=0)", + " Detect output port \\DLY_TAP_VALUE (index=5, width=6, offset=0)", + " Detect output port \\O (index=0, width=1, offset=0)", + " Detect input port \\in (index=0, width=1, offset=0)", + " Detect input port \\reset (index=0, width=1, offset=0)", + " Get Port/Standalone Primitives", + " Get important connection of cell \\I_BUF $ibuf$I_DELAY_primitive_inst.$ibuf_CLK_IN", + " Cell port \\I is connected to input port \\CLK_IN", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$I_DELAY_primitive_inst.$ibuf_DLY_ADJ", + " Cell port \\I is connected to input port \\DLY_ADJ", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$I_DELAY_primitive_inst.$ibuf_DLY_INCDEC", + " Cell port \\I is connected to input port \\DLY_INCDEC", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$I_DELAY_primitive_inst.$ibuf_DLY_LOAD", + " Cell port \\I is connected to input port \\DLY_LOAD", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$I_DELAY_primitive_inst.$ibuf_in", + " Cell port \\I is connected to input port \\in", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$I_DELAY_primitive_inst.$ibuf_reset", + " Cell port \\I is connected to input port \\reset", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE", + " Cell port \\O is connected to output port \\DLY_TAP_VALUE[0]", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_1", + " Cell port \\O is connected to output port \\DLY_TAP_VALUE[1]", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_2", + " Cell port \\O is connected to output port \\DLY_TAP_VALUE[2]", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_3", + " Cell port \\O is connected to output port \\DLY_TAP_VALUE[3]", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_4", + " Cell port \\O is connected to output port \\DLY_TAP_VALUE[4]", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_5", + " Cell port \\O is connected to output port \\DLY_TAP_VALUE[5]", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$I_DELAY_primitive_inst.$obuf_O", + " Cell port \\O is connected to output port \\O", + " Data Width: -2", + " Trace \\I_BUF --> \\CLK_BUF", + " Try \\I_BUF $ibuf$I_DELAY_primitive_inst.$ibuf_CLK_IN out connection: $ibuf_CLK_IN -> $clkbuf$I_DELAY_primitive_inst.$ibuf_CLK_IN", + " Connected $clkbuf$I_DELAY_primitive_inst.$ibuf_CLK_IN", + " Data Width: -2", + " Trace \\I_BUF_DS --> \\CLK_BUF", + " Trace \\CLK_BUF --> \\PLL", + " Trace \\BOOT_CLOCK --> \\PLL", + " Trace \\I_BUF --> \\I_DELAY", + " Trace \\I_BUF --> \\I_DDR", + " Trace \\I_BUF --> \\I_SERDES", + " Trace \\I_BUF_DS --> \\I_DELAY", + " Trace \\I_BUF_DS --> \\I_DDR", + " Trace \\I_BUF_DS --> \\I_SERDES", + " Trace \\I_DELAY --> \\I_DDR", + " Trace \\I_DELAY --> \\I_SERDES", + " Trace \\O_BUF --> \\O_DELAY", + " Trace \\O_BUF --> \\O_DDR", + " Trace \\O_BUF --> \\O_SERDES", + " Trace \\O_BUFT --> \\O_DELAY", + " Trace \\O_BUFT --> \\O_DDR", + " Trace \\O_BUFT --> \\O_SERDES", + " Trace \\O_BUF_DS --> \\O_DELAY", + " Trace \\O_BUF_DS --> \\O_DDR", + " Trace \\O_BUF_DS --> \\O_SERDES", + " Trace \\O_BUFT_DS --> \\O_DELAY", + " Trace \\O_BUFT_DS --> \\O_DDR", + " Trace \\O_BUFT_DS --> \\O_SERDES", + " Trace \\O_DELAY --> \\O_DDR", + " Trace \\O_DELAY --> \\O_SERDES", + " Trace \\O_BUF --> \\O_SERDES_CLK", + " Trace \\O_BUFT --> \\O_SERDES_CLK", + " Trace \\O_BUF_DS --> \\O_SERDES_CLK", + " Trace \\O_BUFT_DS --> \\O_SERDES_CLK", + " Trace fabric clock buffer", + " Trace gearbox fast clock source", + " Trace Core/Fabric Clock", + " Module \\CLK_BUF $clkbuf$I_DELAY_primitive_inst.$ibuf_CLK_IN: clock port \\O, net $clk_buf_$ibuf_CLK_IN", + " Connected to cell \\DFFRE $abc$192$auto_193", + " Which is not a IO primitive. Send to fabric", + " Connected to cell \\I_DELAY \\inst", + " Which is a primitive", + " This is gearbox core_clk. Send to fabric", + " Use slot 0", + " Double check Core/Fabric Clock", + " Summary", + " |----------------------------------------------------------------------------------|", + " | **************************************************** |", + " IN | CLK_IN * I_BUF |-> CLK_BUF * |", + " IN | DLY_ADJ * I_BUF * |", + " IN | DLY_INCDEC * I_BUF * |", + " IN | DLY_LOAD * I_BUF * |", + " IN | in * I_BUF * |", + " IN | reset * I_BUF * |", + " OUT | * O_BUFT * DLY_TAP_VALUE[0] |", + " OUT | * O_BUFT * DLY_TAP_VALUE[1] |", + " OUT | * O_BUFT * DLY_TAP_VALUE[2] |", + " OUT | * O_BUFT * DLY_TAP_VALUE[3] |", + " OUT | * O_BUFT * DLY_TAP_VALUE[4] |", + " OUT | * O_BUFT * DLY_TAP_VALUE[5] |", + " OUT | * O_BUFT * O |", + " | **************************************************** |", + " |----------------------------------------------------------------------------------|", + " Error: Final checking failed. Design count: 15, Primitive count: 14, Instance count: 14", + " Error: Missing \\I_DELAY (\\inst) in primitive list", + " Error: Missing \\I_DELAY (\\inst) in instance list", + " Cross-check instances vs wrapped-instances", + " Generate SDC", + " Determine data signals", + " Pin object=CLK_IN, location: ", + " Pin location is not assigned", + " Pin object=DLY_ADJ, location: ", + " Pin location is not assigned", + " Pin object=DLY_INCDEC, location: ", + " Pin location is not assigned", + " Pin object=DLY_LOAD, location: ", + " Pin location is not assigned", + " Pin object=in, location: ", + " Pin location is not assigned", + " Pin object=reset, location: ", + " Pin location is not assigned", + " Pin object=DLY_TAP_VALUE[0], location: ", + " Pin location is not assigned", + " Pin object=DLY_TAP_VALUE[1], location: ", + " Pin location is not assigned", + " Pin object=DLY_TAP_VALUE[2], location: ", + " Pin location is not assigned", + " Pin object=DLY_TAP_VALUE[3], location: ", + " Pin location is not assigned", + " Pin object=DLY_TAP_VALUE[4], location: ", + " Pin location is not assigned", + " Pin object=DLY_TAP_VALUE[5], location: ", + " Pin location is not assigned", + " Pin object=O, location: ", + " Pin location is not assigned", + " Determine internal control signals", + " Module=I_BUF LinkedObject=CLK_IN Location= Port=EN Signal=in:f2g_in_en_{A|B}", + " Skip reason: Location does not have any mode to begin with", + " Module=I_BUF LinkedObject=DLY_ADJ Location= Port=EN Signal=in:f2g_in_en_{A|B}", + " Skip reason: Location does not have any mode to begin with", + " Module=I_BUF LinkedObject=DLY_INCDEC Location= Port=EN Signal=in:f2g_in_en_{A|B}", + " Skip reason: Location does not have any mode to begin with", + " Module=I_BUF LinkedObject=DLY_LOAD Location= Port=EN Signal=in:f2g_in_en_{A|B}", + " Skip reason: Location does not have any mode to begin with", + " Module=I_BUF LinkedObject=in Location= Port=EN Signal=in:f2g_in_en_{A|B}", + " Skip reason: Location does not have any mode to begin with", + " Module=I_BUF LinkedObject=reset Location= Port=EN Signal=in:f2g_in_en_{A|B}", + " Skip reason: Location does not have any mode to begin with", + " Module=O_BUFT LinkedObject=DLY_TAP_VALUE[0] Location= Port=T Signal=in:f2g_tx_oe_{A|B}", + " Skip reason: Location does not have any mode to begin with", + " Module=O_BUFT LinkedObject=DLY_TAP_VALUE[1] Location= Port=T Signal=in:f2g_tx_oe_{A|B}", + " Skip reason: Location does not have any mode to begin with", + " Module=O_BUFT LinkedObject=DLY_TAP_VALUE[2] Location= Port=T Signal=in:f2g_tx_oe_{A|B}", + " Skip reason: Location does not have any mode to begin with", + " Module=O_BUFT LinkedObject=DLY_TAP_VALUE[3] Location= Port=T Signal=in:f2g_tx_oe_{A|B}", + " Skip reason: Location does not have any mode to begin with", + " Module=O_BUFT LinkedObject=DLY_TAP_VALUE[4] Location= Port=T Signal=in:f2g_tx_oe_{A|B}", + " Skip reason: Location does not have any mode to begin with", + " Module=O_BUFT LinkedObject=DLY_TAP_VALUE[5] Location= Port=T Signal=in:f2g_tx_oe_{A|B}", + " Skip reason: Location does not have any mode to begin with", + " Module=O_BUFT LinkedObject=O Location= Port=T Signal=in:f2g_tx_oe_{A|B}", + " Skip reason: Location does not have any mode to begin with", + "End of IO Analysis" + ], + "instances": [ + { + "module": "I_BUF", + "name": "$ibuf$I_DELAY_primitive_inst.$ibuf_CLK_IN", + "location_object": "CLK_IN", + "location": "", + "linked_object": "CLK_IN", + "linked_objects": { + "CLK_IN": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "CLK_IN", + "O": "$ibuf_CLK_IN" + }, + "parameters": { + "WEAK_KEEPER": "NONE" + }, + "flags": [ + "I_BUF" + ], + "pre_primitive": "", + "post_primitives": [ + "CLK_BUF" + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "CLK_BUF", + "name": "$clkbuf$I_DELAY_primitive_inst.$ibuf_CLK_IN", + "location_object": "CLK_IN", + "location": "", + "linked_object": "CLK_IN", + "linked_objects": { + "CLK_IN": { + "location": "", + "properties": { + "ROUTE_TO_FABRIC_CLK": "0" + } + } + }, + "connectivity": { + "I": "$ibuf_CLK_IN", + "O": "$clk_buf_$ibuf_CLK_IN" + }, + "parameters": { + "ROUTE_TO_FABRIC_CLK": "0" + }, + "flags": [ + "CLK_BUF", + "PIN_CLOCK_CORE_ONLY" + ], + "pre_primitive": "I_BUF", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "I_BUF", + "name": "$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_ADJ", + "location_object": "DLY_ADJ", + "location": "", + "linked_object": "DLY_ADJ", + "linked_objects": { + "DLY_ADJ": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "DLY_ADJ", + "O": "$ibuf_DLY_ADJ" + }, + "parameters": { + "WEAK_KEEPER": "NONE" + }, + "flags": [ + "I_BUF" + ], + "pre_primitive": "", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "I_BUF", + "name": "$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_INCDEC", + "location_object": "DLY_INCDEC", + "location": "", + "linked_object": "DLY_INCDEC", + "linked_objects": { + "DLY_INCDEC": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "DLY_INCDEC", + "O": "$ibuf_DLY_INCDEC" + }, + "parameters": { + "WEAK_KEEPER": "NONE" + }, + "flags": [ + "I_BUF" + ], + "pre_primitive": "", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "I_BUF", + "name": "$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_LOAD", + "location_object": "DLY_LOAD", + "location": "", + "linked_object": "DLY_LOAD", + "linked_objects": { + "DLY_LOAD": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "DLY_LOAD", + "O": "$ibuf_DLY_LOAD" + }, + "parameters": { + "WEAK_KEEPER": "NONE" + }, + "flags": [ + "I_BUF" + ], + "pre_primitive": "", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "I_BUF", + "name": "$ibuf$I_DELAY_primitive_inst.$ibuf_in", + "location_object": "in", + "location": "", + "linked_object": "in", + "linked_objects": { + "in": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "in", + "O": "$ibuf_in" + }, + "parameters": { + "WEAK_KEEPER": "NONE" + }, + "flags": [ + "I_BUF" + ], + "pre_primitive": "", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "I_BUF", + "name": "$ibuf$I_DELAY_primitive_inst.$ibuf_reset", + "location_object": "reset", + "location": "", + "linked_object": "reset", + "linked_objects": { + "reset": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "reset", + "O": "$ibuf_reset" + }, + "parameters": { + "WEAK_KEEPER": "NONE" + }, + "flags": [ + "I_BUF" + ], + "pre_primitive": "", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "O_BUFT", + "name": "$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE", + "location_object": "DLY_TAP_VALUE[0]", + "location": "", + "linked_object": "DLY_TAP_VALUE[0]", + "linked_objects": { + "DLY_TAP_VALUE[0]": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[0]", + "O": "DLY_TAP_VALUE[0]" + }, + "parameters": { + }, + "flags": [ + "O_BUFT" + ], + "pre_primitive": "", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "O_BUFT", + "name": "$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_1", + "location_object": "DLY_TAP_VALUE[1]", + "location": "", + "linked_object": "DLY_TAP_VALUE[1]", + "linked_objects": { + "DLY_TAP_VALUE[1]": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[1]", + "O": "DLY_TAP_VALUE[1]" + }, + "parameters": { + }, + "flags": [ + "O_BUFT" + ], + "pre_primitive": "", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "O_BUFT", + "name": "$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_2", + "location_object": "DLY_TAP_VALUE[2]", + "location": "", + "linked_object": "DLY_TAP_VALUE[2]", + "linked_objects": { + "DLY_TAP_VALUE[2]": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[2]", + "O": "DLY_TAP_VALUE[2]" + }, + "parameters": { + }, + "flags": [ + "O_BUFT" + ], + "pre_primitive": "", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "O_BUFT", + "name": "$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_3", + "location_object": "DLY_TAP_VALUE[3]", + "location": "", + "linked_object": "DLY_TAP_VALUE[3]", + "linked_objects": { + "DLY_TAP_VALUE[3]": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[3]", + "O": "DLY_TAP_VALUE[3]" + }, + "parameters": { + }, + "flags": [ + "O_BUFT" + ], + "pre_primitive": "", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "O_BUFT", + "name": "$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_4", + "location_object": "DLY_TAP_VALUE[4]", + "location": "", + "linked_object": "DLY_TAP_VALUE[4]", + "linked_objects": { + "DLY_TAP_VALUE[4]": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[4]", + "O": "DLY_TAP_VALUE[4]" + }, + "parameters": { + }, + "flags": [ + "O_BUFT" + ], + "pre_primitive": "", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "O_BUFT", + "name": "$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_5", + "location_object": "DLY_TAP_VALUE[5]", + "location": "", + "linked_object": "DLY_TAP_VALUE[5]", + "linked_objects": { + "DLY_TAP_VALUE[5]": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "$f2g_tx_out_$obuf_DLY_TAP_VALUE[5]", + "O": "DLY_TAP_VALUE[5]" + }, + "parameters": { + }, + "flags": [ + "O_BUFT" + ], + "pre_primitive": "", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + }, + { + "module": "O_BUFT", + "name": "$obuf$I_DELAY_primitive_inst.$obuf_O", + "location_object": "O", + "location": "", + "linked_object": "O", + "linked_objects": { + "O": { + "location": "", + "properties": { + } + } + }, + "connectivity": { + "I": "$obuf_O", + "O": "O" + }, + "parameters": { + }, + "flags": [ + "O_BUFT" + ], + "pre_primitive": "", + "post_primitives": [ + ], + "route_clock_to": { + }, + "errors": [ + ] + } + ] +} diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/netlist_checker.log b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/netlist_checker.log new file mode 100644 index 00000000..e28d91fc --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/netlist_checker.log @@ -0,0 +1,14 @@ +Checking Buffer connections +All IO connections are correct. + +Checking Buffer control signals +================================================================ +================================================================ + +Checking I_DELAY/O_DELAY control signals +================================================================ +================================================================ + +Checking FCLK_BUF connections +================================================================ +================================================================ diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/netlist_info.json b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/netlist_info.json new file mode 100644 index 00000000..a787bac5 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/netlist_info.json @@ -0,0 +1,59 @@ +{ + "top" : "I_DELAY_primitive_inst", + "ports" : [ + { + "name": "DLY_TAP_VALUE[4]", + "direction": "output" + }, + { + "name": "DLY_TAP_VALUE[3]", + "direction": "output" + }, + { + "name": "DLY_TAP_VALUE[2]", + "direction": "output" + }, + { + "name": "DLY_TAP_VALUE[1]", + "direction": "output" + }, + { + "name": "DLY_TAP_VALUE[0]", + "direction": "output" + }, + { + "name": "CLK_IN", + "direction": "input", + "clock": "active_high" + }, + { + "name": "DLY_ADJ", + "direction": "input" + }, + { + "name": "DLY_INCDEC", + "direction": "input" + }, + { + "name": "DLY_LOAD", + "direction": "input" + }, + { + "name": "DLY_TAP_VALUE[5]", + "direction": "output" + }, + { + "name": "O", + "direction": "output" + }, + { + "name": "in", + "direction": "input" + }, + { + "name": "reset", + "direction": "input", + "sync_reset": "active_high" + } + ] +} diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/pin_location_I_DELAY_primitive_inst.sdc b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/pin_location_I_DELAY_primitive_inst.sdc new file mode 100644 index 00000000..e69de29b diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/post_pnr_wrapper_I_DELAY_primitive_inst_post_synth.eblif b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/post_pnr_wrapper_I_DELAY_primitive_inst_post_synth.eblif new file mode 100644 index 00000000..b624e825 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/post_pnr_wrapper_I_DELAY_primitive_inst_post_synth.eblif @@ -0,0 +1,33 @@ +# Generated by Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) + +.model I_DELAY_primitive_inst +.inputs reset in DLY_LOAD DLY_ADJ DLY_INCDEC CLK_IN +.outputs DLY_TAP_VALUE[0] DLY_TAP_VALUE[1] DLY_TAP_VALUE[2] DLY_TAP_VALUE[3] DLY_TAP_VALUE[4] DLY_TAP_VALUE[5] O +.names $false +.names $true +1 +.names $undef +.subckt I_DELAY CLK_IN=$clk_buf_$ibuf_CLK_IN DLY_ADJ=$f2g_trx_dly_adj_$ibuf_DLY_ADJ DLY_INCDEC=$f2g_trx_dly_inc_$ibuf_DLY_INCDEC DLY_LOAD=$f2g_trx_dly_ld_$ibuf_DLY_LOAD DLY_TAP_VALUE[0]=$ifab_$obuf_DLY_TAP_VALUE[0] DLY_TAP_VALUE[1]=$ifab_$obuf_DLY_TAP_VALUE[1] DLY_TAP_VALUE[2]=$ifab_$obuf_DLY_TAP_VALUE[2] DLY_TAP_VALUE[3]=$ifab_$obuf_DLY_TAP_VALUE[3] DLY_TAP_VALUE[4]=$ifab_$obuf_DLY_TAP_VALUE[4] DLY_TAP_VALUE[5]=$ifab_$obuf_DLY_TAP_VALUE[5] I=dff O=$obuf_O +.param DELAY 00000000000000000000000000000000 +.subckt CLK_BUF I=$flatten$auto_454.$ibuf_CLK_IN O=$clk_buf_$ibuf_CLK_IN +.subckt I_BUF EN=$auto_440 I=CLK_IN O=$flatten$auto_454.$ibuf_CLK_IN +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$auto_441 I=DLY_ADJ O=$ibuf_DLY_ADJ +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$auto_442 I=DLY_INCDEC O=$ibuf_DLY_INCDEC +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$auto_443 I=DLY_LOAD O=$ibuf_DLY_LOAD +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$auto_444 I=in O=$ibuf_in +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$auto_445 I=reset O=$ibuf_reset +.param WEAK_KEEPER "NONE" +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] O=DLY_TAP_VALUE[0] T=$auto_446 +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] O=DLY_TAP_VALUE[1] T=$auto_447 +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] O=DLY_TAP_VALUE[2] T=$auto_448 +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] O=DLY_TAP_VALUE[3] T=$auto_449 +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] O=DLY_TAP_VALUE[4] T=$auto_450 +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] O=DLY_TAP_VALUE[5] T=$auto_451 +.subckt O_BUFT I=$auto_453 O=O T=$auto_452 +.subckt fabric_I_DELAY_primitive_inst $auto_440=$auto_440 $auto_441=$auto_441 $auto_442=$auto_442 $auto_443=$auto_443 $auto_444=$auto_444 $auto_445=$auto_445 $auto_446=$auto_446 $auto_447=$auto_447 $auto_448=$auto_448 $auto_449=$auto_449 $auto_450=$auto_450 $auto_451=$auto_451 $auto_452=$auto_452 $auto_453=$auto_453 $clk_buf_$ibuf_CLK_IN=$clk_buf_$ibuf_CLK_IN $f2g_trx_dly_adj_$ibuf_DLY_ADJ=$f2g_trx_dly_adj_$ibuf_DLY_ADJ $f2g_trx_dly_inc_$ibuf_DLY_INCDEC=$f2g_trx_dly_inc_$ibuf_DLY_INCDEC $f2g_trx_dly_ld_$ibuf_DLY_LOAD=$f2g_trx_dly_ld_$ibuf_DLY_LOAD $f2g_tx_out_$obuf_DLY_TAP_VALUE[0]=$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] $f2g_tx_out_$obuf_DLY_TAP_VALUE[1]=$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] $f2g_tx_out_$obuf_DLY_TAP_VALUE[2]=$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] $f2g_tx_out_$obuf_DLY_TAP_VALUE[3]=$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] $f2g_tx_out_$obuf_DLY_TAP_VALUE[4]=$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] $f2g_tx_out_$obuf_DLY_TAP_VALUE[5]=$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] $ibuf_DLY_ADJ=$ibuf_DLY_ADJ $ibuf_DLY_INCDEC=$ibuf_DLY_INCDEC $ibuf_DLY_LOAD=$ibuf_DLY_LOAD $ibuf_in=$ibuf_in $ibuf_reset=$ibuf_reset $ifab_$obuf_DLY_TAP_VALUE[0]=$ifab_$obuf_DLY_TAP_VALUE[0] $ifab_$obuf_DLY_TAP_VALUE[1]=$ifab_$obuf_DLY_TAP_VALUE[1] $ifab_$obuf_DLY_TAP_VALUE[2]=$ifab_$obuf_DLY_TAP_VALUE[2] $ifab_$obuf_DLY_TAP_VALUE[3]=$ifab_$obuf_DLY_TAP_VALUE[3] $ifab_$obuf_DLY_TAP_VALUE[4]=$ifab_$obuf_DLY_TAP_VALUE[4] $ifab_$obuf_DLY_TAP_VALUE[5]=$ifab_$obuf_DLY_TAP_VALUE[5] $obuf_O=$obuf_O dff=dff +.end diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/post_pnr_wrapper_I_DELAY_primitive_inst_post_synth.v b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/post_pnr_wrapper_I_DELAY_primitive_inst_post_synth.v new file mode 100644 index 00000000..aa7c826f --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/post_pnr_wrapper_I_DELAY_primitive_inst_post_synth.v @@ -0,0 +1,351 @@ +/* Generated by Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) */ + +module I_DELAY_primitive_inst(reset, in, DLY_LOAD, DLY_ADJ, DLY_INCDEC, DLY_TAP_VALUE, CLK_IN, O); + input CLK_IN; + input DLY_ADJ; + input DLY_INCDEC; + input DLY_LOAD; + output [5:0] DLY_TAP_VALUE; + output O; + input in; + input reset; + wire \$auto_440 ; + wire \$auto_441 ; + wire \$auto_442 ; + wire \$auto_443 ; + wire \$auto_444 ; + wire \$auto_445 ; + wire \$auto_446 ; + wire \$auto_447 ; + wire \$auto_448 ; + wire \$auto_449 ; + wire \$auto_450 ; + wire \$auto_451 ; + wire \$auto_452 ; + wire \$auto_453 ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" *) + wire \$auto_454.CLK_IN ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire \$auto_454.DLY_ADJ ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire \$auto_454.DLY_INCDEC ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire \$auto_454.DLY_LOAD ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire [5:0] \$auto_454.DLY_TAP_VALUE ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + wire \$auto_454.O ; + (* init = 1'h0 *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:14.5-14.8" *) + wire \$auto_454.dff ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + wire \$auto_454.in ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + wire \$auto_454.reset ; + wire \$clk_buf_$ibuf_CLK_IN ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire \$f2g_trx_dly_adj_$ibuf_DLY_ADJ ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire \$f2g_trx_dly_inc_$ibuf_DLY_INCDEC ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire \$f2g_trx_dly_ld_$ibuf_DLY_LOAD ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] ; + wire \$flatten$auto_454.$auto_440 ; + wire \$flatten$auto_454.$auto_441 ; + wire \$flatten$auto_454.$auto_442 ; + wire \$flatten$auto_454.$auto_443 ; + wire \$flatten$auto_454.$auto_444 ; + wire \$flatten$auto_454.$auto_445 ; + wire \$flatten$auto_454.$auto_446 ; + wire \$flatten$auto_454.$auto_447 ; + wire \$flatten$auto_454.$auto_448 ; + wire \$flatten$auto_454.$auto_449 ; + wire \$flatten$auto_454.$auto_450 ; + wire \$flatten$auto_454.$auto_451 ; + wire \$flatten$auto_454.$auto_452 ; + wire \$flatten$auto_454.$auto_453 ; + wire \$flatten$auto_454.$clk_buf_$ibuf_CLK_IN ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire \$flatten$auto_454.$f2g_trx_dly_adj_$ibuf_DLY_ADJ ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire \$flatten$auto_454.$f2g_trx_dly_inc_$ibuf_DLY_INCDEC ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire \$flatten$auto_454.$f2g_trx_dly_ld_$ibuf_DLY_LOAD ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" *) + wire \$flatten$auto_454.$ibuf_CLK_IN ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire \$flatten$auto_454.$ibuf_DLY_ADJ ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire \$flatten$auto_454.$ibuf_DLY_INCDEC ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire \$flatten$auto_454.$ibuf_DLY_LOAD ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + wire \$flatten$auto_454.$ibuf_in ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + wire \$flatten$auto_454.$ibuf_reset ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$ifab_$obuf_DLY_TAP_VALUE[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$ifab_$obuf_DLY_TAP_VALUE[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$ifab_$obuf_DLY_TAP_VALUE[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$ifab_$obuf_DLY_TAP_VALUE[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$ifab_$obuf_DLY_TAP_VALUE[4] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$ifab_$obuf_DLY_TAP_VALUE[5] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + wire \$flatten$auto_454.$obuf_O ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" *) + wire \$ibuf_CLK_IN ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire \$ibuf_DLY_ADJ ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire \$ibuf_DLY_INCDEC ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire \$ibuf_DLY_LOAD ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + wire \$ibuf_in ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + wire \$ibuf_reset ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[4] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[5] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + wire \$obuf_O ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" *) + wire CLK_IN; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire DLY_ADJ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire DLY_INCDEC; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire DLY_LOAD; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire [5:0] DLY_TAP_VALUE; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + wire O; + (* init = 1'h0 *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:14.5-14.8" *) + wire dff; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + wire in; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + wire reset; + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:18.3-26.2" *) + I_DELAY #( + .DELAY(32'sd0) + ) \$auto_454.inst ( + .CLK_IN(\$clk_buf_$ibuf_CLK_IN ), + .DLY_ADJ(\$f2g_trx_dly_adj_$ibuf_DLY_ADJ ), + .DLY_INCDEC(\$f2g_trx_dly_inc_$ibuf_DLY_INCDEC ), + .DLY_LOAD(\$f2g_trx_dly_ld_$ibuf_DLY_LOAD ), + .DLY_TAP_VALUE({ \$ifab_$obuf_DLY_TAP_VALUE[5] , \$ifab_$obuf_DLY_TAP_VALUE[4] , \$ifab_$obuf_DLY_TAP_VALUE[3] , \$ifab_$obuf_DLY_TAP_VALUE[2] , \$ifab_$obuf_DLY_TAP_VALUE[1] , \$ifab_$obuf_DLY_TAP_VALUE[0] }), + .I(dff), + .O(\$obuf_O ) + ); + (* keep = 32'sd1 *) + CLK_BUF \$flatten$auto_454.$clkbuf$I_DELAY_primitive_inst.$ibuf_CLK_IN ( + .I(\$flatten$auto_454.$ibuf_CLK_IN ), + .O(\$clk_buf_$ibuf_CLK_IN ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_CLK_IN ( + .EN(\$auto_440 ), + .I(CLK_IN), + .O(\$flatten$auto_454.$ibuf_CLK_IN ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_ADJ ( + .EN(\$auto_441 ), + .I(DLY_ADJ), + .O(\$ibuf_DLY_ADJ ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_INCDEC ( + .EN(\$auto_442 ), + .I(DLY_INCDEC), + .O(\$ibuf_DLY_INCDEC ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_LOAD ( + .EN(\$auto_443 ), + .I(DLY_LOAD), + .O(\$ibuf_DLY_LOAD ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_in ( + .EN(\$auto_444 ), + .I(in), + .O(\$ibuf_in ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_reset ( + .EN(\$auto_445 ), + .I(reset), + .O(\$ibuf_reset ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] ), + .O(DLY_TAP_VALUE[0]), + .T(\$auto_446 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_1 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] ), + .O(DLY_TAP_VALUE[1]), + .T(\$auto_447 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_2 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] ), + .O(DLY_TAP_VALUE[2]), + .T(\$auto_448 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_3 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] ), + .O(DLY_TAP_VALUE[3]), + .T(\$auto_449 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_4 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] ), + .O(DLY_TAP_VALUE[4]), + .T(\$auto_450 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_5 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] ), + .O(DLY_TAP_VALUE[5]), + .T(\$auto_451 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_O ( + .I(\$auto_453 ), + .O(O), + .T(\$auto_452 ) + ); + fabric_I_DELAY_primitive_inst fabric_instance ( + .\$auto_440 (\$auto_440 ), + .\$auto_441 (\$auto_441 ), + .\$auto_442 (\$auto_442 ), + .\$auto_443 (\$auto_443 ), + .\$auto_444 (\$auto_444 ), + .\$auto_445 (\$auto_445 ), + .\$auto_446 (\$auto_446 ), + .\$auto_447 (\$auto_447 ), + .\$auto_448 (\$auto_448 ), + .\$auto_449 (\$auto_449 ), + .\$auto_450 (\$auto_450 ), + .\$auto_451 (\$auto_451 ), + .\$auto_452 (\$auto_452 ), + .\$auto_453 (\$auto_453 ), + .\$clk_buf_$ibuf_CLK_IN (\$clk_buf_$ibuf_CLK_IN ), + .\$f2g_trx_dly_adj_$ibuf_DLY_ADJ (\$f2g_trx_dly_adj_$ibuf_DLY_ADJ ), + .\$f2g_trx_dly_inc_$ibuf_DLY_INCDEC (\$f2g_trx_dly_inc_$ibuf_DLY_INCDEC ), + .\$f2g_trx_dly_ld_$ibuf_DLY_LOAD (\$f2g_trx_dly_ld_$ibuf_DLY_LOAD ), + .\$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] (\$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] ), + .\$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] (\$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] ), + .\$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] (\$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] ), + .\$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] (\$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] ), + .\$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] (\$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] ), + .\$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] (\$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] ), + .\$ibuf_DLY_ADJ (\$ibuf_DLY_ADJ ), + .\$ibuf_DLY_INCDEC (\$ibuf_DLY_INCDEC ), + .\$ibuf_DLY_LOAD (\$ibuf_DLY_LOAD ), + .\$ibuf_in (\$ibuf_in ), + .\$ibuf_reset (\$ibuf_reset ), + .\$ifab_$obuf_DLY_TAP_VALUE[0] (\$ifab_$obuf_DLY_TAP_VALUE[0] ), + .\$ifab_$obuf_DLY_TAP_VALUE[1] (\$ifab_$obuf_DLY_TAP_VALUE[1] ), + .\$ifab_$obuf_DLY_TAP_VALUE[2] (\$ifab_$obuf_DLY_TAP_VALUE[2] ), + .\$ifab_$obuf_DLY_TAP_VALUE[3] (\$ifab_$obuf_DLY_TAP_VALUE[3] ), + .\$ifab_$obuf_DLY_TAP_VALUE[4] (\$ifab_$obuf_DLY_TAP_VALUE[4] ), + .\$ifab_$obuf_DLY_TAP_VALUE[5] (\$ifab_$obuf_DLY_TAP_VALUE[5] ), + .\$obuf_O (\$obuf_O ), + .dff(dff) + ); +endmodule diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/reports/synth_design_stat.json b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/reports/synth_design_stat.json new file mode 100644 index 00000000..8833ce31 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/reports/synth_design_stat.json @@ -0,0 +1,40 @@ +[ + { + "": { + "header": [ + "Design statistics", + "" + ], + "data": [ + [ + "CLB LUT packing percentage", + "0 %" + ], + [ + "CLB Register packing percentage", + "0 %" + ], + [ + "Wires", + "0" + ], + [ + "Max Fanout", + "0" + ], + [ + "Average Fanout", + "0" + ], + [ + "Maximum logic level", + "1" + ], + [ + "Average logic level", + "1" + ] + ] + } + } +] \ No newline at end of file diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/reports/synth_utilization.json b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/reports/synth_utilization.json new file mode 100644 index 00000000..0a6594b7 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/reports/synth_utilization.json @@ -0,0 +1,148 @@ +[ + { + "": { + "header": [ + "Logic", + "Used", + "Available", + "%" + ], + "data": [ + [ + "CLB", + "0", + "2184", + "0" + ], + [ + " LUTs", + "1", + "17472", + "0" + ], + [ + " Registers", + "1", + "34944", + "0" + ], + [ + " Flip Flop", + "1", + "34944", + "0" + ], + [ + " Adder Carry", + "0", + "17472", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "Block RAM", + "Used", + "Available", + "%" + ], + "data": [ + [ + "BRAM", + "0", + "56", + "0" + ], + [ + " 18k", + "0", + "112", + "0" + ], + [ + " 36k", + "0", + "56", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "DSP", + "Used", + "Available", + "%" + ], + "data": [ + [ + "DSP Block", + "0", + "56", + "0" + ], + [ + " 9x10", + "0", + "56", + "0" + ], + [ + " 18x20", + "0", + "112", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "I/O", + "Used", + "Available", + "%" + ], + "data": [ + [ + "I/O", + "0", + "240", + "0" + ], + [ + " Inputs", + "0", + "240", + "0" + ], + [ + " Outputs", + "0", + "240", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "Clock", + "Used" + ], + "data": [ + [ + "Clock", + "0" + ] + ] + } + } +] \ No newline at end of file diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/synthesis.rpt b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/synthesis.rpt new file mode 100644 index 00000000..75d73cf5 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/synthesis.rpt @@ -0,0 +1,2330 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.09 +Build : 1.2.3 +Hash : 89d4d1b +Date : Sep 19 2024 +Type : Engineering +Log Time : Thu Sep 19 08:35:13 2024 GMT + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) + + +-- Executing script file `I_DELAY_primitive_inst.ys' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v' to AST representation. +Generating RTLIL representation for module `\I_DELAY_primitive_inst'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst + +3.2. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst +Removed 0 unused modules. + +4. Executing synth_rs pass: v0.4.218 + +4.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\inv'. +Generating RTLIL representation for module `\buff'. +Generating RTLIL representation for module `\logic_0'. +Generating RTLIL representation for module `\logic_1'. +Generating RTLIL representation for module `\gclkbuff'. +Successfully finished Verilog frontend. + +4.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v' to AST representation. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v:10.1-33.10. +Generating RTLIL representation for module `\CARRY'. +Successfully finished Verilog frontend. + +4.3. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v' to AST representation. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:20.1-34.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:48.1-62.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:81.1-97.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:115.1-131.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:150.1-166.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:184.1-200.10. +Generating RTLIL representation for module `\LATCHNS'. +Generating RTLIL representation for module `\LATCHSRE'. +Generating RTLIL representation for module `\LATCHNSRE'. +Successfully finished Verilog frontend. + +4.4. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v' to AST representation. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:11.1-81.10. +Generating RTLIL representation for module `\DFFRE'. +Successfully finished Verilog frontend. + +4.5. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v' to AST representation. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:11.1-80.10. +Generating RTLIL representation for module `\DFFNRE'. +Successfully finished Verilog frontend. + +4.6. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v' to AST representation. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v:10.1-20.10. +Generating RTLIL representation for module `\LUT1'. +Successfully finished Verilog frontend. + +4.7. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v' to AST representation. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v:10.1-21.10. +Generating RTLIL representation for module `\LUT2'. +Successfully finished Verilog frontend. + +4.8. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v' to AST representation. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v:10.1-22.10. +Generating RTLIL representation for module `\LUT3'. +Successfully finished Verilog frontend. + +4.9. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v' to AST representation. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v:11.1-25.10. +Generating RTLIL representation for module `\LUT4'. +Successfully finished Verilog frontend. + +4.10. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v' to AST representation. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v:10.1-24.10. +Generating RTLIL representation for module `\LUT5'. +Successfully finished Verilog frontend. + +4.11. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v' to AST representation. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v:10.1-25.10. +Generating RTLIL representation for module `\LUT6'. +Successfully finished Verilog frontend. + +4.12. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v' to AST representation. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v:10.1-25.10. +Generating RTLIL representation for module `\CLK_BUF'. +Successfully finished Verilog frontend. + +4.13. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v' to AST representation. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v:10.1-84.10. +Generating RTLIL representation for module `\O_BUF'. +Successfully finished Verilog frontend. + +4.14. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v' to AST representation. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v:10.1-341.10. +Generating RTLIL representation for module `\DSP38'. +Successfully finished Verilog frontend. + +4.15. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v' to AST representation. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:2.1-29.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:33.1-84.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\RS_DSP3'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:116.1-149.10. +Generating RTLIL representation for module `\DSP19X2'. +Successfully finished Verilog frontend. + +4.16. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v' to AST representation. +Generating RTLIL representation for module `\TDP_BRAM18'. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Generating RTLIL representation for module `\_$_mem_v2_asymmetric'. +Successfully finished Verilog frontend. + +4.17. Executing HIERARCHY pass (managing design hierarchy). + +4.17.1. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst + +4.17.2. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst +Removed 0 unused modules. + +4.18. Executing PROC pass (convert processes to netlists). + +4.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1 in module I_DELAY_primitive_inst. +Removed a total of 0 dead cases. + +4.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 1 redundant assignment. +Promoted 0 assignments to connections. + +4.18.4. Executing PROC_INIT pass (extract init attributes). + +4.18.5. Executing PROC_ARST pass (detect async resets in processes). + +4.18.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +4.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\I_DELAY_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1'. + 1/1: $0\dff[0:0] + +4.18.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +4.18.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\I_DELAY_primitive_inst.\dff' using process `\I_DELAY_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1'. + created $dff cell `$procdff$5' with positive edge clock. + +4.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\I_DELAY_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1'. +Removing empty process `I_DELAY_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1'. +Cleaned up 1 empty switch. + +4.18.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.19. Executing FLATTEN pass (flatten design). + +# -------------------- +# Design entry stats +# -------------------- + +4.20. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 12 + Number of wire bits: 17 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + $mux 1 + I_DELAY 1 + +4.21. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.22. Executing DEMUXMAP pass. + +4.23. Executing FLATTEN pass (flatten design). + +4.24. Executing DEMUXMAP pass. + +4.25. Executing TRIBUF pass. +Warning: Ignored -no_iobuf because -keep_tribuf is used. + +4.26. Executing DEMINOUT pass (demote inout ports to input or output). + +4.27. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 2 unused wires. + + +4.29. Executing CHECK pass (checking for obvious problems). +Checking module I_DELAY_primitive_inst... +Found and reported 0 problems. + +4.30. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + $mux 1 + I_DELAY 1 + +FF init value for cell $procdff$5 ($dff): \dff = 1'x + +4.31. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.32. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.33. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.34. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.35. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.36. Executing OPT_SHARE pass. + +4.37. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.38. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.40. Executing FSM pass (extract and optimize FSM). + +4.40.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.40.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.40.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.40.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.40.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.40.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.41. Executing WREDUCE pass (reducing word size of cells). + +4.42. Executing PEEPOPT pass (run peephole optimizers). + +4.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.44. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.45. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.46. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.47. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.48. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.49. Executing OPT_SHARE pass. + +4.50. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $procdff$5 ($dff) from module I_DELAY_primitive_inst (D = \in, Q = \dff, rval = 1'0). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.51. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 1 unused cells and 1 unused wires. + + +4.52. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.53. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.54. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.55. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.56. Executing OPT_SHARE pass. + +4.57. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.58. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.59. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 2 + +4.60. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.61. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.62. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.63. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.64. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.65. Executing OPT_SHARE pass. + +4.66. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.67. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.68. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.69. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.70. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.71. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.72. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.73. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.74. Executing OPT_SHARE pass. + +4.75. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.76. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.77. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.78. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.79. Executing WREDUCE pass (reducing word size of cells). + +4.80. Executing PEEPOPT pass (run peephole optimizers). + +4.81. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.82. Executing DEMUXMAP pass. + +4.83. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.84. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.85. Executing RS_DSP_MULTADD pass. + +4.86. Executing WREDUCE pass (reducing word size of cells). + +4.87. Executing RS_DSP_MACC pass. + +4.88. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.89. Executing TECHMAP pass (map to technology primitives). + +4.89.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.89.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.90. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.91. Executing TECHMAP pass (map to technology primitives). + +4.91.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.91.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.92. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.93. Executing TECHMAP pass (map to technology primitives). + +4.93.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.93.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.94. Executing TECHMAP pass (map to technology primitives). + +4.94.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.94.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.95. Executing TECHMAP pass (map to technology primitives). + +4.95.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__RS_MUL20X18'. +Generating RTLIL representation for module `\$__RS_MUL10X9'. +Successfully finished Verilog frontend. + +4.95.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.96. Executing RS_DSP_SIMD pass. + +4.97. Executing TECHMAP pass (map to technology primitives). + +4.97.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v' to AST representation. +Generating RTLIL representation for module `\dsp_t1_20x18x64_cfg_ports'. +Generating RTLIL representation for module `\dsp_t1_10x9x32_cfg_params'. +Successfully finished Verilog frontend. + +4.97.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.98. Executing TECHMAP pass (map to technology primitives). + +4.98.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.98.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.99. Executing rs_pack_dsp_regs pass. + +4.100. Executing RS_DSP_IO_REGS pass. + +4.101. Executing TECHMAP pass (map to technology primitives). + +4.101.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSP_MULTACC'. +Generating RTLIL representation for module `\RS_DSP_MULT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN_REGOUT'. +Successfully finished Verilog frontend. + +4.101.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.102. Executing TECHMAP pass (map to technology primitives). + +4.102.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.102.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.103. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.104. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module I_DELAY_primitive_inst: + created 0 $alu and 0 $macc cells. + +4.105. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.106. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.107. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.108. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.109. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.110. Executing OPT_SHARE pass. + +4.111. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.112. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.113. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.114. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.115. Executing MEMORY pass. + +4.115.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.115.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.115.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.115.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.115.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.115.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.115.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.115.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.115.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.115.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.116. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.117. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.118. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.119. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.120. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.121. Executing Rs_BRAM_Split pass. + +4.122. Executing TECHMAP pass (map to technology primitives). + +4.122.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_SDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_SDP'. +Successfully finished Verilog frontend. + +4.122.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.123. Executing TECHMAP pass (map to technology primitives). + +4.123.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Successfully finished Verilog frontend. + +4.123.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.124. Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs). + +4.125. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.126. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.127. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.128. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.129. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.130. Executing OPT_SHARE pass. + +4.131. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.132. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.133. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.134. Executing PMUXTREE pass. + +4.135. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + + +4.136. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +4.137. Executing TECHMAP pass (map to technology primitives). + +4.137.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.137.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_rs_alu'. +Successfully finished Verilog frontend. + +4.137.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $mux. +No more expansions possible. + + +4.138. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $_MUX_ 1 + I_DELAY 1 + +4.139. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.140. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.141. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.142. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.143. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.144. Executing OPT_SHARE pass. + +4.145. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.146. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.147. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.148. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.149. Executing TECHMAP pass (map to technology primitives). + +4.149.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.149.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.150. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $_MUX_ 1 + I_DELAY 1 + +4.151. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.152. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.153. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.154. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.155. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.156. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.157. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.158. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.159. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.160. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.161. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.162. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.163. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.164. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.165. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.166. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.167. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.168. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.169. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.170. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.171. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.172. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.173. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.174. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.175. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.176. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $_MUX_ 1 + I_DELAY 1 + + Number of Generic REGs: 1 + +ABC-DFF iteration : 1 + +4.177. Executing ABC pass (technology mapping using ABC). + +4.177.1. Summary of detected clock domains: + 3 cells in clk=\CLK_IN, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.177.2. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \CLK_IN +Extracted 2 gates and 5 wires to a netlist network with 2 inputs and 1 outputs (dfl=1). + +4.177.2.1. Executing ABC. +[Time = 0.07 sec.] + +4.178. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.179. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.180. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.181. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.182. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.183. Executing OPT_SHARE pass. + +4.184. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.185. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 5 unused wires. + + +4.186. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 2 + +4.187. Executing ABC pass (technology mapping using ABC). + +4.187.1. Summary of detected clock domains: + 3 cells in clk=\CLK_IN, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.187.2. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \CLK_IN +Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 1 outputs (dfl=1). + +4.187.2.1. Executing ABC. +[Time = 0.04 sec.] + +4.188. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.189. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.190. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.191. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.192. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.193. Executing OPT_SHARE pass. + +4.194. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.195. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 5 unused wires. + + +4.196. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 3 + +4.197. Executing ABC pass (technology mapping using ABC). + +4.197.1. Summary of detected clock domains: + 3 cells in clk=\CLK_IN, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.197.2. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \CLK_IN +Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 1 outputs (dfl=2). + +4.197.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.198. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.199. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.200. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.201. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.202. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.203. Executing OPT_SHARE pass. + +4.204. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.205. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 5 unused wires. + + +4.206. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 4 + +4.207. Executing ABC pass (technology mapping using ABC). + +4.207.1. Summary of detected clock domains: + 3 cells in clk=\CLK_IN, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.207.2. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \CLK_IN +Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 1 outputs (dfl=2). + +4.207.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.208. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.209. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.210. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.211. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.212. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.213. Executing OPT_SHARE pass. + +4.214. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.215. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 5 unused wires. + + +4.216. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 +select with DFL1 synthesis (thresh_logic=0.920000, thresh_dff=0.980000) + +4.217. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.218. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.219. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.220. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.221. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.222. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.223. Executing OPT_SHARE pass. + +4.224. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.225. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.226. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.227. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.228. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.229. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.230. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.231. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.232. Executing OPT_SHARE pass. + +4.233. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.234. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.235. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.236. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.237. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.238. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.239. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.240. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.241. Executing OPT_SHARE pass. + +4.242. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.243. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.244. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.245. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.246. Executing BMUXMAP pass. + +4.247. Executing DEMUXMAP pass. + +4.248. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.249. Executing ABC pass (technology mapping using ABC). + +4.249.1. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Extracted 1 gates and 3 wires to a netlist network with 2 inputs and 1 outputs (dfl=1). + +4.249.1.1. Executing ABC. +DE: Version : 7.7 +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.06 sec. at Pass 0]{firstMap}[1] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 1]{initMapFlow}[3] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 2]{map}[9] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.12 sec. at Pass 3]{postMap}[18] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.20 sec. at Pass 4]{map}[54] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.58 sec. at Pass 5]{postMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.64 sec. at Pass 6]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.62 sec. at Pass 7]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.68 sec. at Pass 7]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.56 sec. at Pass 8]{finalMap}[100] +DE: +DE: total time = 3.86 sec. +[Time = 5.92 sec.] + +4.250. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.251. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.252. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.253. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.254. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.255. Executing OPT_SHARE pass. + +4.256. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.257. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 3 unused wires. + + +4.258. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.259. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.260. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.261. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.262. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.263. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.264. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.265. Executing OPT_SHARE pass. + +4.266. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.267. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.268. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.269. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.270. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.271. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.272. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.273. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.274. Executing OPT_SHARE pass. + +4.275. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.276. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.277. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.278. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.279. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $lut 1 + I_DELAY 1 + +4.280. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +4.281. Executing RS_DFFSR_CONV pass. + +4.282. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $lut 1 + I_DELAY 1 + +4.283. Executing TECHMAP pass (map to technology primitives). + +4.283.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.283.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PN0P_'. +Generating RTLIL representation for module `\$_DFFE_PN0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_DFFE_PN1P_'. +Generating RTLIL representation for module `\$_DFFE_PN1N_'. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NN0P_'. +Generating RTLIL representation for module `\$_DFFE_NN0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_NN1P_'. +Generating RTLIL representation for module `\$_DFFE_NN1N_'. +Generating RTLIL representation for module `\$__SHREG_DFF_P_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PN0_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NN0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_PN1_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_NN1_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_PP0_'. +Generating RTLIL representation for module `\$_DLATCH_PN0_'. +Generating RTLIL representation for module `\$_DLATCH_NP0_'. +Generating RTLIL representation for module `\$_DLATCH_NN0_'. +Generating RTLIL representation for module `\$_DLATCH_PP1_'. +Generating RTLIL representation for module `\$_DLATCH_PN1_'. +Generating RTLIL representation for module `\$_DLATCH_NP1_'. +Generating RTLIL representation for module `\$_DLATCH_NN1_'. +Successfully finished Verilog frontend. + +4.283.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $lut. +No more expansions possible. + + +4.284. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + + +4.285. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +4.286. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.287. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.288. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.289. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.290. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.291. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.292. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.293. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.294. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.295. Executing OPT_SHARE pass. + +4.296. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.297. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.298. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.299. Executing TECHMAP pass (map to technology primitives). + +4.299.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.299.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.300. Executing ABC pass (technology mapping using ABC). + +4.300.1. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Extracted 2 gates and 5 wires to a netlist network with 2 inputs and 1 outputs (dfl=1). + +4.300.1.1. Executing ABC. +DE: Version : 7.7 +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 0]{firstMap}[1] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 1]{initMapFlow}[3] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 2]{map}[9] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.12 sec. at Pass 3]{postMap}[18] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.18 sec. at Pass 4]{map}[54] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.52 sec. at Pass 5]{postMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.63 sec. at Pass 6]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.63 sec. at Pass 7]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.64 sec. at Pass 7]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.60 sec. at Pass 8]{finalMap}[100] +DE: +DE: total time = 3.80 sec. +[Time = 5.86 sec.] + +4.301. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.302. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.303. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.304. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.305. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.306. Executing OPT_SHARE pass. + +4.307. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.308. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.309. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.310. Executing HIERARCHY pass (managing design hierarchy). + +4.310.1. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst + +4.310.2. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst +Removed 0 unused modules. + +4.311. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.312. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__IO_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.313. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Replacing existing blackbox module `\BOOT_CLOCK' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:9.1-14.10. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:24.1-31.10. +Generating RTLIL representation for module `\CARRY'. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:41.1-46.10. +Generating RTLIL representation for module `\CLK_BUF'. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:56.1-64.10. +Generating RTLIL representation for module `\DFFNRE'. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:74.1-82.10. +Generating RTLIL representation for module `\DFFRE'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:92.1-126.10. +Generating RTLIL representation for module `\DSP19X2'. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:136.1-162.10. +Generating RTLIL representation for module `\DSP38'. +Replacing existing blackbox module `\FCLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:172.1-176.10. +Generating RTLIL representation for module `\FCLK_BUF'. +Replacing existing blackbox module `\FIFO18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:186.1-233.10. +Generating RTLIL representation for module `\FIFO18KX2'. +Replacing existing blackbox module `\FIFO36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:243.1-268.10. +Generating RTLIL representation for module `\FIFO36K'. +Replacing existing blackbox module `\I_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:278.1-290.10. +Generating RTLIL representation for module `\I_BUF_DS'. +Replacing existing blackbox module `\I_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:300.1-309.10. +Generating RTLIL representation for module `\I_BUF'. +Replacing existing blackbox module `\I_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:319.1-327.10. +Generating RTLIL representation for module `\I_DDR'. +Replacing existing blackbox module `\I_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:337.1-349.10. +Generating RTLIL representation for module `\I_DELAY'. +Replacing existing blackbox module `\I_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:359.1-363.10. +Generating RTLIL representation for module `\I_FAB'. +Replacing existing blackbox module `\I_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:373.1-392.10. +Generating RTLIL representation for module `\I_SERDES'. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:402.1-408.10. +Generating RTLIL representation for module `\LUT1'. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:418.1-424.10. +Generating RTLIL representation for module `\LUT2'. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:434.1-440.10. +Generating RTLIL representation for module `\LUT3'. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:450.1-456.10. +Generating RTLIL representation for module `\LUT4'. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:466.1-472.10. +Generating RTLIL representation for module `\LUT5'. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:482.1-488.10. +Generating RTLIL representation for module `\LUT6'. +Replacing existing blackbox module `\O_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:498.1-510.10. +Generating RTLIL representation for module `\O_BUF_DS'. +Replacing existing blackbox module `\O_BUFT_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:520.1-532.10. +Generating RTLIL representation for module `\O_BUFT_DS'. +Replacing existing blackbox module `\O_BUFT' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:542.1-553.10. +Generating RTLIL representation for module `\O_BUFT'. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:563.1-574.10. +Generating RTLIL representation for module `\O_BUF'. +Replacing existing blackbox module `\O_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:584.1-592.10. +Generating RTLIL representation for module `\O_DDR'. +Replacing existing blackbox module `\O_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:602.1-614.10. +Generating RTLIL representation for module `\O_DELAY'. +Replacing existing blackbox module `\O_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:624.1-628.10. +Generating RTLIL representation for module `\O_FAB'. +Replacing existing blackbox module `\O_SERDES_CLK' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:638.1-647.10. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Replacing existing blackbox module `\O_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:657.1-674.10. +Generating RTLIL representation for module `\O_SERDES'. +Replacing existing blackbox module `\PLL' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:684.1-702.10. +Generating RTLIL representation for module `\PLL'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_M' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:712.1-726.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_S' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:736.1-753.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M0' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:763.1-802.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M1' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:812.1-851.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Replacing existing blackbox module `\SOC_FPGA_INTF_DMA' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:861.1-867.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Replacing existing blackbox module `\SOC_FPGA_INTF_IRQ' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:877.1-883.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Replacing existing blackbox module `\SOC_FPGA_INTF_JTAG' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:893.1-901.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Replacing existing blackbox module `\SOC_FPGA_TEMPERATURE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:911.1-919.10. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:929.1-984.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:994.1-1023.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1040.1-1045.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1053.1-1058.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1067.1-1073.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1081.1-1087.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1096.1-1102.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1111.1-1117.10. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + *************************** + Inserting Input Buffers + *************************** +WARNING: port '\CLK_IN' has no associated I_BUF +WARNING: port '\DLY_ADJ' has no associated I_BUF +WARNING: port '\DLY_INCDEC' has no associated I_BUF +WARNING: port '\DLY_LOAD' has no associated I_BUF +WARNING: port '\in' has no associated I_BUF +WARNING: port '\reset' has no associated I_BUF + *************************** + Inserting Clock Buffers + *************************** +INFO: inserting CLK_BUF before '$ibuf_CLK_IN' + ***************************** + Inserting Output Buffers + ***************************** +WARNING: OUTPUT port '\DLY_TAP_VALUE' has no associated O_BUF +WARNING: OUTPUT port '\O' has no associated O_BUF + ***************************** + Mapping Tri-state Buffers + ***************************** + +4.314. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.315. Executing TECHMAP pass (map to technology primitives). + +4.315.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.315.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.316. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 39 unused wires. + + +4.317. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 19 + Number of wire bits: 29 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 17 + $lut 1 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + O_BUF 7 + +4.318. Executing TECHMAP pass (map to technology primitives). + +4.318.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v' to AST representation. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +4.318.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.319. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 2 unused wires. + + +4.320. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 19 + Number of wire bits: 29 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 17 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + LUT2 1 + O_BUF 7 + + ***************************** + Rewire_Obuft + ***************************** + +========================== +Post Design clean up ... + +Split to bits ... + +4.321. Executing SPLITNETS pass (splitting up multi-bit signals). + +Split into bits ... [0.00 sec.] +Building Sig2cells ... [0.00 sec.] +Building Sig2sig ... [0.00 sec.] +Backward clean up ... [0.00 sec.] +Before cleanup : + +4.322. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 24 + Number of wire bits: 29 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 17 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + LUT2 1 + O_BUFT 7 + + -------------------------- + Removed assigns : 0 + Removed wires : 0 + Removed cells : 0 + -------------------------- +After cleanup : + +4.323. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 24 + Number of wire bits: 29 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 17 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + LUT2 1 + O_BUFT 7 + + +Total time for 'obs_clean' ... + [0.00 sec.] + +4.324. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.325. Executing HIERARCHY pass (managing design hierarchy). + +4.325.1. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst + +4.325.2. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst +Removed 0 unused modules. + +Dumping port properties into 'netlist_info.json' file. + +Inserting I_FAB/O_FAB cells ... + +Skip O_FAB insertion on net '$obuf_O' (Primitive output) + +Inserting I_FAB/O_FAB cells done. + +4.326. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 39 + Number of wire bits: 44 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 32 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + I_FAB 6 + LUT2 1 + O_BUFT 7 + O_FAB 9 + + Number of LUTs: 1 + Number of REGs: 1 + Number of CARRY ADDERs: 0 + +4.327. Executing Verilog backend. +Dumping module `\I_DELAY_primitive_inst'. + +# -------------------- +# Core Synthesis done +# -------------------- + +4.328. Executing Verilog backend. +Dumping module `\I_DELAY_primitive_inst'. + +4.328.1. Executing BLIF backend. +Extracting primitives + +-- Running command `write_rtlil design.rtlil' -- + +4.328.2. Executing RTLIL backend. +Output filename: design.rtlil +Running SplitNets + +4.328.3. Executing SPLITNETS pass (splitting up multi-bit signals). +Gathering Wires Data +Adding wires between directly connected input and output primitives +Upgrading fabric wires to ports +Handling I_BUF->Fabric->CLK_BUF +Handling Dangling outs +Deleting primitive cells and extra wires +Deleting non-primitive cells and upgrading wires to ports in interface module +Handling I_BUF->Fabric->CLK_BUF in interface module +Removing extra wires from interface module +Cleaning fabric netlist +Removing cells from wrapper module +Instantiating fabric and interface modules +Removing extra wires from wrapper module +Fixing wrapper ports +Flattening wrapper module + +4.328.4. Executing FLATTEN pass (flatten design). +Deleting now unused module interface_I_DELAY_primitive_inst. + +Removing extra assigns from wrapper module + +4.328.5. Executing Verilog backend. +Dumping module `\I_DELAY_primitive_inst'. + +4.328.5.1. Executing BLIF backend. + +4.328.5.2. Executing Verilog backend. +Dumping module `\I_DELAY_primitive_inst'. + +4.328.5.2.1. Executing BLIF backend. +Dumping config.json +Updating sdc + +4.328.5.2.2. Executing Verilog backend. +Dumping module `\fabric_I_DELAY_primitive_inst'. + +4.328.5.2.2.1. Executing BLIF backend. + +Warnings: 1 unique messages, 1 total +End of script. Logfile hash: 51223390fa, CPU: user 0.59s system 0.07s, MEM: 23.35 MB peak +Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) +Time spent: 99% 6x abc (181 sec), 0% 43x read_verilog (0 sec), ... diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/wrapper_I_DELAY_primitive_inst_post_synth.eblif b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/wrapper_I_DELAY_primitive_inst_post_synth.eblif new file mode 100644 index 00000000..b624e825 --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/wrapper_I_DELAY_primitive_inst_post_synth.eblif @@ -0,0 +1,33 @@ +# Generated by Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) + +.model I_DELAY_primitive_inst +.inputs reset in DLY_LOAD DLY_ADJ DLY_INCDEC CLK_IN +.outputs DLY_TAP_VALUE[0] DLY_TAP_VALUE[1] DLY_TAP_VALUE[2] DLY_TAP_VALUE[3] DLY_TAP_VALUE[4] DLY_TAP_VALUE[5] O +.names $false +.names $true +1 +.names $undef +.subckt I_DELAY CLK_IN=$clk_buf_$ibuf_CLK_IN DLY_ADJ=$f2g_trx_dly_adj_$ibuf_DLY_ADJ DLY_INCDEC=$f2g_trx_dly_inc_$ibuf_DLY_INCDEC DLY_LOAD=$f2g_trx_dly_ld_$ibuf_DLY_LOAD DLY_TAP_VALUE[0]=$ifab_$obuf_DLY_TAP_VALUE[0] DLY_TAP_VALUE[1]=$ifab_$obuf_DLY_TAP_VALUE[1] DLY_TAP_VALUE[2]=$ifab_$obuf_DLY_TAP_VALUE[2] DLY_TAP_VALUE[3]=$ifab_$obuf_DLY_TAP_VALUE[3] DLY_TAP_VALUE[4]=$ifab_$obuf_DLY_TAP_VALUE[4] DLY_TAP_VALUE[5]=$ifab_$obuf_DLY_TAP_VALUE[5] I=dff O=$obuf_O +.param DELAY 00000000000000000000000000000000 +.subckt CLK_BUF I=$flatten$auto_454.$ibuf_CLK_IN O=$clk_buf_$ibuf_CLK_IN +.subckt I_BUF EN=$auto_440 I=CLK_IN O=$flatten$auto_454.$ibuf_CLK_IN +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$auto_441 I=DLY_ADJ O=$ibuf_DLY_ADJ +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$auto_442 I=DLY_INCDEC O=$ibuf_DLY_INCDEC +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$auto_443 I=DLY_LOAD O=$ibuf_DLY_LOAD +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$auto_444 I=in O=$ibuf_in +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$auto_445 I=reset O=$ibuf_reset +.param WEAK_KEEPER "NONE" +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] O=DLY_TAP_VALUE[0] T=$auto_446 +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] O=DLY_TAP_VALUE[1] T=$auto_447 +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] O=DLY_TAP_VALUE[2] T=$auto_448 +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] O=DLY_TAP_VALUE[3] T=$auto_449 +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] O=DLY_TAP_VALUE[4] T=$auto_450 +.subckt O_BUFT I=$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] O=DLY_TAP_VALUE[5] T=$auto_451 +.subckt O_BUFT I=$auto_453 O=O T=$auto_452 +.subckt fabric_I_DELAY_primitive_inst $auto_440=$auto_440 $auto_441=$auto_441 $auto_442=$auto_442 $auto_443=$auto_443 $auto_444=$auto_444 $auto_445=$auto_445 $auto_446=$auto_446 $auto_447=$auto_447 $auto_448=$auto_448 $auto_449=$auto_449 $auto_450=$auto_450 $auto_451=$auto_451 $auto_452=$auto_452 $auto_453=$auto_453 $clk_buf_$ibuf_CLK_IN=$clk_buf_$ibuf_CLK_IN $f2g_trx_dly_adj_$ibuf_DLY_ADJ=$f2g_trx_dly_adj_$ibuf_DLY_ADJ $f2g_trx_dly_inc_$ibuf_DLY_INCDEC=$f2g_trx_dly_inc_$ibuf_DLY_INCDEC $f2g_trx_dly_ld_$ibuf_DLY_LOAD=$f2g_trx_dly_ld_$ibuf_DLY_LOAD $f2g_tx_out_$obuf_DLY_TAP_VALUE[0]=$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] $f2g_tx_out_$obuf_DLY_TAP_VALUE[1]=$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] $f2g_tx_out_$obuf_DLY_TAP_VALUE[2]=$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] $f2g_tx_out_$obuf_DLY_TAP_VALUE[3]=$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] $f2g_tx_out_$obuf_DLY_TAP_VALUE[4]=$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] $f2g_tx_out_$obuf_DLY_TAP_VALUE[5]=$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] $ibuf_DLY_ADJ=$ibuf_DLY_ADJ $ibuf_DLY_INCDEC=$ibuf_DLY_INCDEC $ibuf_DLY_LOAD=$ibuf_DLY_LOAD $ibuf_in=$ibuf_in $ibuf_reset=$ibuf_reset $ifab_$obuf_DLY_TAP_VALUE[0]=$ifab_$obuf_DLY_TAP_VALUE[0] $ifab_$obuf_DLY_TAP_VALUE[1]=$ifab_$obuf_DLY_TAP_VALUE[1] $ifab_$obuf_DLY_TAP_VALUE[2]=$ifab_$obuf_DLY_TAP_VALUE[2] $ifab_$obuf_DLY_TAP_VALUE[3]=$ifab_$obuf_DLY_TAP_VALUE[3] $ifab_$obuf_DLY_TAP_VALUE[4]=$ifab_$obuf_DLY_TAP_VALUE[4] $ifab_$obuf_DLY_TAP_VALUE[5]=$ifab_$obuf_DLY_TAP_VALUE[5] $obuf_O=$obuf_O dff=dff +.end diff --git a/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/wrapper_I_DELAY_primitive_inst_post_synth.v b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/wrapper_I_DELAY_primitive_inst_post_synth.v new file mode 100644 index 00000000..aa7c826f --- /dev/null +++ b/EDA-3249/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/wrapper_I_DELAY_primitive_inst_post_synth.v @@ -0,0 +1,351 @@ +/* Generated by Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) */ + +module I_DELAY_primitive_inst(reset, in, DLY_LOAD, DLY_ADJ, DLY_INCDEC, DLY_TAP_VALUE, CLK_IN, O); + input CLK_IN; + input DLY_ADJ; + input DLY_INCDEC; + input DLY_LOAD; + output [5:0] DLY_TAP_VALUE; + output O; + input in; + input reset; + wire \$auto_440 ; + wire \$auto_441 ; + wire \$auto_442 ; + wire \$auto_443 ; + wire \$auto_444 ; + wire \$auto_445 ; + wire \$auto_446 ; + wire \$auto_447 ; + wire \$auto_448 ; + wire \$auto_449 ; + wire \$auto_450 ; + wire \$auto_451 ; + wire \$auto_452 ; + wire \$auto_453 ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" *) + wire \$auto_454.CLK_IN ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire \$auto_454.DLY_ADJ ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire \$auto_454.DLY_INCDEC ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire \$auto_454.DLY_LOAD ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire [5:0] \$auto_454.DLY_TAP_VALUE ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + wire \$auto_454.O ; + (* init = 1'h0 *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:14.5-14.8" *) + wire \$auto_454.dff ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + wire \$auto_454.in ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + wire \$auto_454.reset ; + wire \$clk_buf_$ibuf_CLK_IN ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire \$f2g_trx_dly_adj_$ibuf_DLY_ADJ ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire \$f2g_trx_dly_inc_$ibuf_DLY_INCDEC ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire \$f2g_trx_dly_ld_$ibuf_DLY_LOAD ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] ; + wire \$flatten$auto_454.$auto_440 ; + wire \$flatten$auto_454.$auto_441 ; + wire \$flatten$auto_454.$auto_442 ; + wire \$flatten$auto_454.$auto_443 ; + wire \$flatten$auto_454.$auto_444 ; + wire \$flatten$auto_454.$auto_445 ; + wire \$flatten$auto_454.$auto_446 ; + wire \$flatten$auto_454.$auto_447 ; + wire \$flatten$auto_454.$auto_448 ; + wire \$flatten$auto_454.$auto_449 ; + wire \$flatten$auto_454.$auto_450 ; + wire \$flatten$auto_454.$auto_451 ; + wire \$flatten$auto_454.$auto_452 ; + wire \$flatten$auto_454.$auto_453 ; + wire \$flatten$auto_454.$clk_buf_$ibuf_CLK_IN ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire \$flatten$auto_454.$f2g_trx_dly_adj_$ibuf_DLY_ADJ ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire \$flatten$auto_454.$f2g_trx_dly_inc_$ibuf_DLY_INCDEC ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire \$flatten$auto_454.$f2g_trx_dly_ld_$ibuf_DLY_LOAD ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" *) + wire \$flatten$auto_454.$ibuf_CLK_IN ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire \$flatten$auto_454.$ibuf_DLY_ADJ ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire \$flatten$auto_454.$ibuf_DLY_INCDEC ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire \$flatten$auto_454.$ibuf_DLY_LOAD ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + wire \$flatten$auto_454.$ibuf_in ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + wire \$flatten$auto_454.$ibuf_reset ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$ifab_$obuf_DLY_TAP_VALUE[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$ifab_$obuf_DLY_TAP_VALUE[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$ifab_$obuf_DLY_TAP_VALUE[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$ifab_$obuf_DLY_TAP_VALUE[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$ifab_$obuf_DLY_TAP_VALUE[4] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$flatten$auto_454.$ifab_$obuf_DLY_TAP_VALUE[5] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + wire \$flatten$auto_454.$obuf_O ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" *) + wire \$ibuf_CLK_IN ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire \$ibuf_DLY_ADJ ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire \$ibuf_DLY_INCDEC ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire \$ibuf_DLY_LOAD ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + wire \$ibuf_in ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + wire \$ibuf_reset ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[4] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire \$ifab_$obuf_DLY_TAP_VALUE[5] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + wire \$obuf_O ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:10.9-10.15" *) + wire CLK_IN; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:7.9-7.16" *) + wire DLY_ADJ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:8.9-8.19" *) + wire DLY_INCDEC; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:6.9-6.17" *) + wire DLY_LOAD; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:9.16-9.29" *) + wire [5:0] DLY_TAP_VALUE; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:11.10-11.11" *) + wire O; + (* init = 1'h0 *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:14.5-14.8" *) + wire dff; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:5.9-5.11" *) + wire in; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:4.9-4.14" *) + wire reset; + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:18.3-26.2" *) + I_DELAY #( + .DELAY(32'sd0) + ) \$auto_454.inst ( + .CLK_IN(\$clk_buf_$ibuf_CLK_IN ), + .DLY_ADJ(\$f2g_trx_dly_adj_$ibuf_DLY_ADJ ), + .DLY_INCDEC(\$f2g_trx_dly_inc_$ibuf_DLY_INCDEC ), + .DLY_LOAD(\$f2g_trx_dly_ld_$ibuf_DLY_LOAD ), + .DLY_TAP_VALUE({ \$ifab_$obuf_DLY_TAP_VALUE[5] , \$ifab_$obuf_DLY_TAP_VALUE[4] , \$ifab_$obuf_DLY_TAP_VALUE[3] , \$ifab_$obuf_DLY_TAP_VALUE[2] , \$ifab_$obuf_DLY_TAP_VALUE[1] , \$ifab_$obuf_DLY_TAP_VALUE[0] }), + .I(dff), + .O(\$obuf_O ) + ); + (* keep = 32'sd1 *) + CLK_BUF \$flatten$auto_454.$clkbuf$I_DELAY_primitive_inst.$ibuf_CLK_IN ( + .I(\$flatten$auto_454.$ibuf_CLK_IN ), + .O(\$clk_buf_$ibuf_CLK_IN ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_CLK_IN ( + .EN(\$auto_440 ), + .I(CLK_IN), + .O(\$flatten$auto_454.$ibuf_CLK_IN ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_ADJ ( + .EN(\$auto_441 ), + .I(DLY_ADJ), + .O(\$ibuf_DLY_ADJ ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_INCDEC ( + .EN(\$auto_442 ), + .I(DLY_INCDEC), + .O(\$ibuf_DLY_INCDEC ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_DLY_LOAD ( + .EN(\$auto_443 ), + .I(DLY_LOAD), + .O(\$ibuf_DLY_LOAD ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_in ( + .EN(\$auto_444 ), + .I(in), + .O(\$ibuf_in ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_454.$ibuf$I_DELAY_primitive_inst.$ibuf_reset ( + .EN(\$auto_445 ), + .I(reset), + .O(\$ibuf_reset ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] ), + .O(DLY_TAP_VALUE[0]), + .T(\$auto_446 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_1 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] ), + .O(DLY_TAP_VALUE[1]), + .T(\$auto_447 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_2 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] ), + .O(DLY_TAP_VALUE[2]), + .T(\$auto_448 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_3 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] ), + .O(DLY_TAP_VALUE[3]), + .T(\$auto_449 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_4 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] ), + .O(DLY_TAP_VALUE[4]), + .T(\$auto_450 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_DLY_TAP_VALUE_5 ( + .I(\$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] ), + .O(DLY_TAP_VALUE[5]), + .T(\$auto_451 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_454.$obuf$I_DELAY_primitive_inst.$obuf_O ( + .I(\$auto_453 ), + .O(O), + .T(\$auto_452 ) + ); + fabric_I_DELAY_primitive_inst fabric_instance ( + .\$auto_440 (\$auto_440 ), + .\$auto_441 (\$auto_441 ), + .\$auto_442 (\$auto_442 ), + .\$auto_443 (\$auto_443 ), + .\$auto_444 (\$auto_444 ), + .\$auto_445 (\$auto_445 ), + .\$auto_446 (\$auto_446 ), + .\$auto_447 (\$auto_447 ), + .\$auto_448 (\$auto_448 ), + .\$auto_449 (\$auto_449 ), + .\$auto_450 (\$auto_450 ), + .\$auto_451 (\$auto_451 ), + .\$auto_452 (\$auto_452 ), + .\$auto_453 (\$auto_453 ), + .\$clk_buf_$ibuf_CLK_IN (\$clk_buf_$ibuf_CLK_IN ), + .\$f2g_trx_dly_adj_$ibuf_DLY_ADJ (\$f2g_trx_dly_adj_$ibuf_DLY_ADJ ), + .\$f2g_trx_dly_inc_$ibuf_DLY_INCDEC (\$f2g_trx_dly_inc_$ibuf_DLY_INCDEC ), + .\$f2g_trx_dly_ld_$ibuf_DLY_LOAD (\$f2g_trx_dly_ld_$ibuf_DLY_LOAD ), + .\$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] (\$f2g_tx_out_$obuf_DLY_TAP_VALUE[0] ), + .\$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] (\$f2g_tx_out_$obuf_DLY_TAP_VALUE[1] ), + .\$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] (\$f2g_tx_out_$obuf_DLY_TAP_VALUE[2] ), + .\$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] (\$f2g_tx_out_$obuf_DLY_TAP_VALUE[3] ), + .\$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] (\$f2g_tx_out_$obuf_DLY_TAP_VALUE[4] ), + .\$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] (\$f2g_tx_out_$obuf_DLY_TAP_VALUE[5] ), + .\$ibuf_DLY_ADJ (\$ibuf_DLY_ADJ ), + .\$ibuf_DLY_INCDEC (\$ibuf_DLY_INCDEC ), + .\$ibuf_DLY_LOAD (\$ibuf_DLY_LOAD ), + .\$ibuf_in (\$ibuf_in ), + .\$ibuf_reset (\$ibuf_reset ), + .\$ifab_$obuf_DLY_TAP_VALUE[0] (\$ifab_$obuf_DLY_TAP_VALUE[0] ), + .\$ifab_$obuf_DLY_TAP_VALUE[1] (\$ifab_$obuf_DLY_TAP_VALUE[1] ), + .\$ifab_$obuf_DLY_TAP_VALUE[2] (\$ifab_$obuf_DLY_TAP_VALUE[2] ), + .\$ifab_$obuf_DLY_TAP_VALUE[3] (\$ifab_$obuf_DLY_TAP_VALUE[3] ), + .\$ifab_$obuf_DLY_TAP_VALUE[4] (\$ifab_$obuf_DLY_TAP_VALUE[4] ), + .\$ifab_$obuf_DLY_TAP_VALUE[5] (\$ifab_$obuf_DLY_TAP_VALUE[5] ), + .\$obuf_O (\$obuf_O ), + .dff(dff) + ); +endmodule diff --git a/EDA-3249/raptor.log b/EDA-3249/raptor.log new file mode 100644 index 00000000..20a0271e --- /dev/null +++ b/EDA-3249/raptor.log @@ -0,0 +1,4162 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.09 +Build : 1.2.3 +Hash : 89d4d1b +Date : Sep 19 2024 +Type : Engineering +Log Time : Thu Sep 19 08:34:59 2024 GMT + +INFO: Created design: I_DELAY_primitive_inst. Project type: rtl +INFO: Target device: 1VG28 +INFO: Device version: v1.6.244 +INFO: Adding VERILOG_2001 /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v +INFO: ANL: ################################################## +INFO: ANL: Analysis for design: I_DELAY_primitive_inst +INFO: ANL: ################################################## +INFO: ANL: Analyze command: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/yosys -s /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/I_DELAY_primitive_inst_analyzer.cmd +Command: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/yosys -s /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/I_DELAY_primitive_inst_analyzer.cmd + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) + + +-- Executing script file `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/I_DELAY_primitive_inst_analyzer.cmd' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v' to AST representation. +Generating RTLIL representation for module `\I_DELAY_primitive_inst'. +Successfully finished Verilog frontend. + +-- Running command `hierarchy -top I_DELAY_primitive_inst' -- + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst + +3.2. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst +Removed 0 unused modules. + +Dumping file hier_info.json ... + Process module "I_DELAY" +Dumping file port_info.json ... + +End of script. Logfile hash: 561b84ddef, CPU: user 0.03s system 0.01s, MEM: 15.88 MB peak +Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) +Time spent: 94% 4x read_verilog (0 sec), 3% 1x analyze (0 sec), ... +INFO: ANL: Design I_DELAY_primitive_inst is analyzed +INFO: ANL: Top Modules: I_DELAY_primitive_inst + +INFO: SYN: ################################################## +INFO: SYN: Synthesis for design: I_DELAY_primitive_inst +INFO: SYN: ################################################## +INFO: SYN: RS Synthesis +INFO: SYN: Synthesis command: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/yosys -s I_DELAY_primitive_inst.ys -l I_DELAY_primitive_inst_synth.log +Command: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/yosys -s I_DELAY_primitive_inst.ys -l I_DELAY_primitive_inst_synth.log + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) + + +-- Executing script file `I_DELAY_primitive_inst.ys' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v' to AST representation. +Generating RTLIL representation for module `\I_DELAY_primitive_inst'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst + +3.2. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst +Removed 0 unused modules. + +4. Executing synth_rs pass: v0.4.218 + +4.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\inv'. +Generating RTLIL representation for module `\buff'. +Generating RTLIL representation for module `\logic_0'. +Generating RTLIL representation for module `\logic_1'. +Generating RTLIL representation for module `\gclkbuff'. +Successfully finished Verilog frontend. + +4.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v' to AST representation. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v:10.1-33.10. +Generating RTLIL representation for module `\CARRY'. +Successfully finished Verilog frontend. + +4.3. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v' to AST representation. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:20.1-34.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:48.1-62.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:81.1-97.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:115.1-131.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:150.1-166.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:184.1-200.10. +Generating RTLIL representation for module `\LATCHNS'. +Generating RTLIL representation for module `\LATCHSRE'. +Generating RTLIL representation for module `\LATCHNSRE'. +Successfully finished Verilog frontend. + +4.4. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v' to AST representation. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:11.1-81.10. +Generating RTLIL representation for module `\DFFRE'. +Successfully finished Verilog frontend. + +4.5. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v' to AST representation. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:11.1-80.10. +Generating RTLIL representation for module `\DFFNRE'. +Successfully finished Verilog frontend. + +4.6. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v' to AST representation. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v:10.1-20.10. +Generating RTLIL representation for module `\LUT1'. +Successfully finished Verilog frontend. + +4.7. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v' to AST representation. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v:10.1-21.10. +Generating RTLIL representation for module `\LUT2'. +Successfully finished Verilog frontend. + +4.8. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v' to AST representation. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v:10.1-22.10. +Generating RTLIL representation for module `\LUT3'. +Successfully finished Verilog frontend. + +4.9. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v' to AST representation. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v:11.1-25.10. +Generating RTLIL representation for module `\LUT4'. +Successfully finished Verilog frontend. + +4.10. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v' to AST representation. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v:10.1-24.10. +Generating RTLIL representation for module `\LUT5'. +Successfully finished Verilog frontend. + +4.11. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v' to AST representation. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v:10.1-25.10. +Generating RTLIL representation for module `\LUT6'. +Successfully finished Verilog frontend. + +4.12. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v' to AST representation. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v:10.1-25.10. +Generating RTLIL representation for module `\CLK_BUF'. +Successfully finished Verilog frontend. + +4.13. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v' to AST representation. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v:10.1-84.10. +Generating RTLIL representation for module `\O_BUF'. +Successfully finished Verilog frontend. + +4.14. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v' to AST representation. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v:10.1-341.10. +Generating RTLIL representation for module `\DSP38'. +Successfully finished Verilog frontend. + +4.15. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v' to AST representation. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:2.1-29.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:33.1-84.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\RS_DSP3'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:116.1-149.10. +Generating RTLIL representation for module `\DSP19X2'. +Successfully finished Verilog frontend. + +4.16. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v' to AST representation. +Generating RTLIL representation for module `\TDP_BRAM18'. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Generating RTLIL representation for module `\_$_mem_v2_asymmetric'. +Successfully finished Verilog frontend. + +4.17. Executing HIERARCHY pass (managing design hierarchy). + +4.17.1. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst + +4.17.2. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst +Removed 0 unused modules. + +4.18. Executing PROC pass (convert processes to netlists). + +4.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1 in module I_DELAY_primitive_inst. +Removed a total of 0 dead cases. + +4.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 1 redundant assignment. +Promoted 0 assignments to connections. + +4.18.4. Executing PROC_INIT pass (extract init attributes). + +4.18.5. Executing PROC_ARST pass (detect async resets in processes). + +4.18.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +4.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\I_DELAY_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1'. + 1/1: $0\dff[0:0] + +4.18.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +4.18.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\I_DELAY_primitive_inst.\dff' using process `\I_DELAY_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1'. + created $dff cell `$procdff$5' with positive edge clock. + +4.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\I_DELAY_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1'. +Removing empty process `I_DELAY_primitive_inst.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/./rtl/I_DELAY_primitive_inst.v:28$1'. +Cleaned up 1 empty switch. + +4.18.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.19. Executing FLATTEN pass (flatten design). + +# -------------------- +# Design entry stats +# -------------------- + +4.20. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 12 + Number of wire bits: 17 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + $mux 1 + I_DELAY 1 + +4.21. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.22. Executing DEMUXMAP pass. + +4.23. Executing FLATTEN pass (flatten design). + +4.24. Executing DEMUXMAP pass. + +4.25. Executing TRIBUF pass. +Warning: Ignored -no_iobuf because -keep_tribuf is used. + +4.26. Executing DEMINOUT pass (demote inout ports to input or output). + +4.27. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 2 unused wires. + + +4.29. Executing CHECK pass (checking for obvious problems). +Checking module I_DELAY_primitive_inst... +Found and reported 0 problems. + +4.30. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $dff 1 + $mux 1 + I_DELAY 1 + +FF init value for cell $procdff$5 ($dff): \dff = 1'x + +4.31. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.32. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.33. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.34. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.35. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.36. Executing OPT_SHARE pass. + +4.37. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.38. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.40. Executing FSM pass (extract and optimize FSM). + +4.40.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.40.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.40.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.40.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.40.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.40.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.41. Executing WREDUCE pass (reducing word size of cells). + +4.42. Executing PEEPOPT pass (run peephole optimizers). + +4.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.44. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.45. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.46. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.47. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.48. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.49. Executing OPT_SHARE pass. + +4.50. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $procdff$5 ($dff) from module I_DELAY_primitive_inst (D = \in, Q = \dff, rval = 1'0). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.51. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 1 unused cells and 1 unused wires. + + +4.52. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.53. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.54. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.55. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.56. Executing OPT_SHARE pass. + +4.57. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.58. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.59. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 2 + +4.60. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.61. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.62. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.63. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.64. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.65. Executing OPT_SHARE pass. + +4.66. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.67. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.68. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.69. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.70. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.71. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.72. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.73. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.74. Executing OPT_SHARE pass. + +4.75. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.76. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.77. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.78. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.79. Executing WREDUCE pass (reducing word size of cells). + +4.80. Executing PEEPOPT pass (run peephole optimizers). + +4.81. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.82. Executing DEMUXMAP pass. + +4.83. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.84. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.85. Executing RS_DSP_MULTADD pass. + +4.86. Executing WREDUCE pass (reducing word size of cells). + +4.87. Executing RS_DSP_MACC pass. + +4.88. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.89. Executing TECHMAP pass (map to technology primitives). + +4.89.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.89.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.90. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.91. Executing TECHMAP pass (map to technology primitives). + +4.91.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.91.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.92. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.93. Executing TECHMAP pass (map to technology primitives). + +4.93.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.93.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.94. Executing TECHMAP pass (map to technology primitives). + +4.94.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.94.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.95. Executing TECHMAP pass (map to technology primitives). + +4.95.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__RS_MUL20X18'. +Generating RTLIL representation for module `\$__RS_MUL10X9'. +Successfully finished Verilog frontend. + +4.95.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.96. Executing RS_DSP_SIMD pass. + +4.97. Executing TECHMAP pass (map to technology primitives). + +4.97.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v' to AST representation. +Generating RTLIL representation for module `\dsp_t1_20x18x64_cfg_ports'. +Generating RTLIL representation for module `\dsp_t1_10x9x32_cfg_params'. +Successfully finished Verilog frontend. + +4.97.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.98. Executing TECHMAP pass (map to technology primitives). + +4.98.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.98.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.99. Executing rs_pack_dsp_regs pass. + +4.100. Executing RS_DSP_IO_REGS pass. + +4.101. Executing TECHMAP pass (map to technology primitives). + +4.101.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSP_MULTACC'. +Generating RTLIL representation for module `\RS_DSP_MULT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN_REGOUT'. +Successfully finished Verilog frontend. + +4.101.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.102. Executing TECHMAP pass (map to technology primitives). + +4.102.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.102.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.103. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.104. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module I_DELAY_primitive_inst: + created 0 $alu and 0 $macc cells. + +4.105. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.106. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.107. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.108. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.109. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.110. Executing OPT_SHARE pass. + +4.111. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.112. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.113. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.114. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.115. Executing MEMORY pass. + +4.115.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.115.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.115.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.115.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.115.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.115.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.115.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.115.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.115.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.115.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.116. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 9 + Number of wire bits: 14 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $sdff 1 + I_DELAY 1 + +4.117. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.118. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.119. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.120. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.121. Executing Rs_BRAM_Split pass. + +4.122. Executing TECHMAP pass (map to technology primitives). + +4.122.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_SDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_SDP'. +Successfully finished Verilog frontend. + +4.122.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.123. Executing TECHMAP pass (map to technology primitives). + +4.123.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Successfully finished Verilog frontend. + +4.123.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.124. Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs). + +4.125. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.126. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.127. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.128. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.129. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.130. Executing OPT_SHARE pass. + +4.131. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.132. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.133. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.134. Executing PMUXTREE pass. + +4.135. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + + +4.136. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +4.137. Executing TECHMAP pass (map to technology primitives). + +4.137.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.137.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_rs_alu'. +Successfully finished Verilog frontend. + +4.137.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $mux. +No more expansions possible. + + +4.138. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $_MUX_ 1 + I_DELAY 1 + +4.139. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.140. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.141. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.142. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.143. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.144. Executing OPT_SHARE pass. + +4.145. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.146. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.147. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.148. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.149. Executing TECHMAP pass (map to technology primitives). + +4.149.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.149.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.150. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $_MUX_ 1 + I_DELAY 1 + +4.151. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.152. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.153. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.154. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.155. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.156. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.157. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.158. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.159. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.160. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.161. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.162. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.163. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.164. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.165. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.166. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.167. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.168. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.169. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.170. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.171. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.172. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.173. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.174. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.175. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.176. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $_MUX_ 1 + I_DELAY 1 + + Number of Generic REGs: 1 + +ABC-DFF iteration : 1 + +4.177. Executing ABC pass (technology mapping using ABC). + +4.177.1. Summary of detected clock domains: + 3 cells in clk=\CLK_IN, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.177.2. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \CLK_IN +Extracted 2 gates and 5 wires to a netlist network with 2 inputs and 1 outputs (dfl=1). + +4.177.2.1. Executing ABC. +[Time = 0.07 sec.] + +4.178. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.179. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.180. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.181. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.182. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.183. Executing OPT_SHARE pass. + +4.184. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.185. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 5 unused wires. + + +4.186. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 2 + +4.187. Executing ABC pass (technology mapping using ABC). + +4.187.1. Summary of detected clock domains: + 3 cells in clk=\CLK_IN, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.187.2. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \CLK_IN +Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 1 outputs (dfl=1). + +4.187.2.1. Executing ABC. +[Time = 0.04 sec.] + +4.188. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.189. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.190. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.191. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.192. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.193. Executing OPT_SHARE pass. + +4.194. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.195. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 5 unused wires. + + +4.196. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 3 + +4.197. Executing ABC pass (technology mapping using ABC). + +4.197.1. Summary of detected clock domains: + 3 cells in clk=\CLK_IN, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.197.2. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \CLK_IN +Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 1 outputs (dfl=2). + +4.197.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.198. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.199. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.200. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.201. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.202. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.203. Executing OPT_SHARE pass. + +4.204. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.205. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 5 unused wires. + + +4.206. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 4 + +4.207. Executing ABC pass (technology mapping using ABC). + +4.207.1. Summary of detected clock domains: + 3 cells in clk=\CLK_IN, en={ }, arst={ }, srst={ } + + #logic partitions = 1 + +4.207.2. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Found matching posedge clock domain: \CLK_IN +Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 1 outputs (dfl=2). + +4.207.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.208. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.209. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.210. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.211. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.212. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.213. Executing OPT_SHARE pass. + +4.214. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.215. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 5 unused wires. + + +4.216. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 +select with DFL1 synthesis (thresh_logic=0.920000, thresh_dff=0.980000) + +4.217. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.218. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.219. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.220. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.221. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.222. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.223. Executing OPT_SHARE pass. + +4.224. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.225. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.226. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.227. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.228. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.229. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.230. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.231. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.232. Executing OPT_SHARE pass. + +4.233. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.234. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.235. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.236. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.237. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.238. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.239. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.240. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.241. Executing OPT_SHARE pass. + +4.242. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.243. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.244. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.245. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.246. Executing BMUXMAP pass. + +4.247. Executing DEMUXMAP pass. + +4.248. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.249. Executing ABC pass (technology mapping using ABC). + +4.249.1. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Extracted 1 gates and 3 wires to a netlist network with 2 inputs and 1 outputs (dfl=1). + +4.249.1.1. Executing ABC. +DE: Version : 7.7 +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.06 sec. at Pass 0]{firstMap}[1] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 1]{initMapFlow}[3] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 2]{map}[9] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.12 sec. at Pass 3]{postMap}[18] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.20 sec. at Pass 4]{map}[54] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.58 sec. at Pass 5]{postMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.64 sec. at Pass 6]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.62 sec. at Pass 7]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.68 sec. at Pass 7]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.56 sec. at Pass 8]{finalMap}[100] +DE: +DE: total time = 3.86 sec. +[Time = 5.92 sec.] + +4.250. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.251. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.252. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.253. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.254. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.255. Executing OPT_SHARE pass. + +4.256. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.257. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 3 unused wires. + + +4.258. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.259. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.260. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.261. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.262. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.263. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.264. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.265. Executing OPT_SHARE pass. + +4.266. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.267. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.268. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.269. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.270. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.271. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.272. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.273. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.274. Executing OPT_SHARE pass. + +4.275. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=0, #remove=0, time=0.00 sec.] + +4.276. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=1, #solve=1, #remove=0, time=0.00 sec.] + +4.277. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.278. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.279. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $lut 1 + I_DELAY 1 + +4.280. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +4.281. Executing RS_DFFSR_CONV pass. + +4.282. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 10 + Number of wire bits: 15 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $_DFF_P_ 1 + $lut 1 + I_DELAY 1 + +4.283. Executing TECHMAP pass (map to technology primitives). + +4.283.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.283.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PN0P_'. +Generating RTLIL representation for module `\$_DFFE_PN0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_DFFE_PN1P_'. +Generating RTLIL representation for module `\$_DFFE_PN1N_'. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NN0P_'. +Generating RTLIL representation for module `\$_DFFE_NN0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_NN1P_'. +Generating RTLIL representation for module `\$_DFFE_NN1N_'. +Generating RTLIL representation for module `\$__SHREG_DFF_P_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PN0_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NN0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_PN1_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_NN1_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_PP0_'. +Generating RTLIL representation for module `\$_DLATCH_PN0_'. +Generating RTLIL representation for module `\$_DLATCH_NP0_'. +Generating RTLIL representation for module `\$_DLATCH_NN0_'. +Generating RTLIL representation for module `\$_DLATCH_PP1_'. +Generating RTLIL representation for module `\$_DLATCH_PN1_'. +Generating RTLIL representation for module `\$_DLATCH_NP1_'. +Generating RTLIL representation for module `\$_DLATCH_NN1_'. +Successfully finished Verilog frontend. + +4.283.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $lut. +No more expansions possible. + + +4.284. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + + +4.285. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +4.286. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.287. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.288. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.289. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.290. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.291. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.292. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.293. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.294. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.295. Executing OPT_SHARE pass. + +4.296. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.297. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.298. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.299. Executing TECHMAP pass (map to technology primitives). + +4.299.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.299.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.300. Executing ABC pass (technology mapping using ABC). + +4.300.1. Extracting gate netlist of module `\I_DELAY_primitive_inst' to `/input.blif'.. +Extracted 2 gates and 5 wires to a netlist network with 2 inputs and 1 outputs (dfl=1). + +4.300.1.1. Executing ABC. +DE: Version : 7.7 +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 0]{firstMap}[1] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 1]{initMapFlow}[3] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.08 sec. at Pass 2]{map}[9] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.12 sec. at Pass 3]{postMap}[18] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.18 sec. at Pass 4]{map}[54] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.52 sec. at Pass 5]{postMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.63 sec. at Pass 6]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.63 sec. at Pass 7]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.64 sec. at Pass 7]{pushMap}[100] +DE: #PIs = 2 #Luts = 1 Max Lvl = 1 Avg Lvl = 1.00 [ 0.60 sec. at Pass 8]{finalMap}[100] +DE: +DE: total time = 3.80 sec. +[Time = 5.86 sec.] + +4.301. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +4.302. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.303. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \I_DELAY_primitive_inst.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.304. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \I_DELAY_primitive_inst. +Performed a total of 0 changes. + +4.305. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\I_DELAY_primitive_inst'. +Removed a total of 0 cells. + +4.306. Executing OPT_SHARE pass. + +4.307. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.308. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 4 unused wires. + + +4.309. Executing OPT_EXPR pass (perform const folding). +Optimizing module I_DELAY_primitive_inst. + +RUN-OPT ITERATIONS DONE : 1 + +4.310. Executing HIERARCHY pass (managing design hierarchy). + +4.310.1. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst + +4.310.2. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst +Removed 0 unused modules. + +4.311. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.312. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__IO_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.313. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Replacing existing blackbox module `\BOOT_CLOCK' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:9.1-14.10. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:24.1-31.10. +Generating RTLIL representation for module `\CARRY'. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:41.1-46.10. +Generating RTLIL representation for module `\CLK_BUF'. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:56.1-64.10. +Generating RTLIL representation for module `\DFFNRE'. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:74.1-82.10. +Generating RTLIL representation for module `\DFFRE'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:92.1-126.10. +Generating RTLIL representation for module `\DSP19X2'. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:136.1-162.10. +Generating RTLIL representation for module `\DSP38'. +Replacing existing blackbox module `\FCLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:172.1-176.10. +Generating RTLIL representation for module `\FCLK_BUF'. +Replacing existing blackbox module `\FIFO18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:186.1-233.10. +Generating RTLIL representation for module `\FIFO18KX2'. +Replacing existing blackbox module `\FIFO36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:243.1-268.10. +Generating RTLIL representation for module `\FIFO36K'. +Replacing existing blackbox module `\I_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:278.1-290.10. +Generating RTLIL representation for module `\I_BUF_DS'. +Replacing existing blackbox module `\I_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:300.1-309.10. +Generating RTLIL representation for module `\I_BUF'. +Replacing existing blackbox module `\I_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:319.1-327.10. +Generating RTLIL representation for module `\I_DDR'. +Replacing existing blackbox module `\I_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:337.1-349.10. +Generating RTLIL representation for module `\I_DELAY'. +Replacing existing blackbox module `\I_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:359.1-363.10. +Generating RTLIL representation for module `\I_FAB'. +Replacing existing blackbox module `\I_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:373.1-392.10. +Generating RTLIL representation for module `\I_SERDES'. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:402.1-408.10. +Generating RTLIL representation for module `\LUT1'. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:418.1-424.10. +Generating RTLIL representation for module `\LUT2'. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:434.1-440.10. +Generating RTLIL representation for module `\LUT3'. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:450.1-456.10. +Generating RTLIL representation for module `\LUT4'. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:466.1-472.10. +Generating RTLIL representation for module `\LUT5'. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:482.1-488.10. +Generating RTLIL representation for module `\LUT6'. +Replacing existing blackbox module `\O_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:498.1-510.10. +Generating RTLIL representation for module `\O_BUF_DS'. +Replacing existing blackbox module `\O_BUFT_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:520.1-532.10. +Generating RTLIL representation for module `\O_BUFT_DS'. +Replacing existing blackbox module `\O_BUFT' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:542.1-553.10. +Generating RTLIL representation for module `\O_BUFT'. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:563.1-574.10. +Generating RTLIL representation for module `\O_BUF'. +Replacing existing blackbox module `\O_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:584.1-592.10. +Generating RTLIL representation for module `\O_DDR'. +Replacing existing blackbox module `\O_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:602.1-614.10. +Generating RTLIL representation for module `\O_DELAY'. +Replacing existing blackbox module `\O_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:624.1-628.10. +Generating RTLIL representation for module `\O_FAB'. +Replacing existing blackbox module `\O_SERDES_CLK' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:638.1-647.10. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Replacing existing blackbox module `\O_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:657.1-674.10. +Generating RTLIL representation for module `\O_SERDES'. +Replacing existing blackbox module `\PLL' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:684.1-702.10. +Generating RTLIL representation for module `\PLL'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_M' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:712.1-726.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_S' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:736.1-753.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M0' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:763.1-802.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M1' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:812.1-851.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Replacing existing blackbox module `\SOC_FPGA_INTF_DMA' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:861.1-867.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Replacing existing blackbox module `\SOC_FPGA_INTF_IRQ' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:877.1-883.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Replacing existing blackbox module `\SOC_FPGA_INTF_JTAG' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:893.1-901.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Replacing existing blackbox module `\SOC_FPGA_TEMPERATURE' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:911.1-919.10. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:929.1-984.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:994.1-1023.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1040.1-1045.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1053.1-1058.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1067.1-1073.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1081.1-1087.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1096.1-1102.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1111.1-1117.10. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + *************************** + Inserting Input Buffers + *************************** +WARNING: port '\CLK_IN' has no associated I_BUF +WARNING: port '\DLY_ADJ' has no associated I_BUF +WARNING: port '\DLY_INCDEC' has no associated I_BUF +WARNING: port '\DLY_LOAD' has no associated I_BUF +WARNING: port '\in' has no associated I_BUF +WARNING: port '\reset' has no associated I_BUF + *************************** + Inserting Clock Buffers + *************************** +INFO: inserting CLK_BUF before '$ibuf_CLK_IN' + ***************************** + Inserting Output Buffers + ***************************** +WARNING: OUTPUT port '\DLY_TAP_VALUE' has no associated O_BUF +WARNING: OUTPUT port '\O' has no associated O_BUF + ***************************** + Mapping Tri-state Buffers + ***************************** + +4.314. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. + +4.315. Executing TECHMAP pass (map to technology primitives). + +4.315.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.315.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.316. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 39 unused wires. + + +4.317. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 19 + Number of wire bits: 29 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 17 + $lut 1 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + O_BUF 7 + +4.318. Executing TECHMAP pass (map to technology primitives). + +4.318.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v' to AST representation. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +4.318.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.319. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \I_DELAY_primitive_inst.. +Removed 0 unused cells and 2 unused wires. + + +4.320. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 19 + Number of wire bits: 29 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 17 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + LUT2 1 + O_BUF 7 + + ***************************** + Rewire_Obuft + ***************************** + +========================== +Post Design clean up ... + +Split to bits ... + +4.321. Executing SPLITNETS pass (splitting up multi-bit signals). + +Split into bits ... [0.00 sec.] +Building Sig2cells ... [0.00 sec.] +Building Sig2sig ... [0.00 sec.] +Backward clean up ... [0.00 sec.] +Before cleanup : + +4.322. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 24 + Number of wire bits: 29 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 17 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + LUT2 1 + O_BUFT 7 + + -------------------------- + Removed assigns : 0 + Removed wires : 0 + Removed cells : 0 + -------------------------- +After cleanup : + +4.323. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 24 + Number of wire bits: 29 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 17 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + LUT2 1 + O_BUFT 7 + + +Total time for 'obs_clean' ... + [0.00 sec.] + +4.324. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.325. Executing HIERARCHY pass (managing design hierarchy). + +4.325.1. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst + +4.325.2. Analyzing design hierarchy.. +Top module: \I_DELAY_primitive_inst +Removed 0 unused modules. + +Dumping port properties into 'netlist_info.json' file. + +Inserting I_FAB/O_FAB cells ... + +Skip O_FAB insertion on net '$obuf_O' (Primitive output) + +Inserting I_FAB/O_FAB cells done. + +4.326. Printing statistics. + +=== I_DELAY_primitive_inst === + + Number of wires: 39 + Number of wire bits: 44 + Number of public wires: 9 + Number of public wire bits: 14 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 32 + CLK_BUF 1 + DFFRE 1 + I_BUF 6 + I_DELAY 1 + I_FAB 6 + LUT2 1 + O_BUFT 7 + O_FAB 9 + + Number of LUTs: 1 + Number of REGs: 1 + Number of CARRY ADDERs: 0 + +4.327. Executing Verilog backend. +Dumping module `\I_DELAY_primitive_inst'. + +# -------------------- +# Core Synthesis done +# -------------------- + +4.328. Executing Verilog backend. +Dumping module `\I_DELAY_primitive_inst'. + +4.328.1. Executing BLIF backend. +Extracting primitives + +-- Running command `write_rtlil design.rtlil' -- + +4.328.2. Executing RTLIL backend. +Output filename: design.rtlil +[0.0227222 sec.] +Running SplitNets + +4.328.3. Executing SPLITNETS pass (splitting up multi-bit signals). +[9.6015e-05 sec.] +Gathering Wires Data +[0.000257565 sec.] +Adding wires between directly connected input and output primitives +[7.1203e-05 sec.] +Upgrading fabric wires to ports +[3.72e-05 sec.] +Handling I_BUF->Fabric->CLK_BUF +[3.637e-05 sec.] +Handling Dangling outs +[6.1457e-05 sec.] +Deleting primitive cells and extra wires +[7.347e-05 sec.] +Deleting non-primitive cells and upgrading wires to ports in interface module +[4.2839e-05 sec.] +Handling I_BUF->Fabric->CLK_BUF in interface module +[2.618e-05 sec.] +Removing extra wires from interface module +[1.6189e-05 sec.] +Cleaning fabric netlist +[0.00127975 sec.] +Removing cells from wrapper module +[5.4524e-05 sec.] +Instantiating fabric and interface modules +[0.000107935 sec.] +Removing extra wires from wrapper module +[2.5422e-05 sec.] +Fixing wrapper ports +[7.035e-06 sec.] +Flattening wrapper module + +4.328.4. Executing FLATTEN pass (flatten design). +Deleting now unused module interface_I_DELAY_primitive_inst. + +[0.00080731 sec.] +Removing extra assigns from wrapper module +[6.8693e-05 sec.] + +4.328.5. Executing Verilog backend. +Dumping module `\I_DELAY_primitive_inst'. + +4.328.5.1. Executing BLIF backend. +Run Script + +4.328.5.2. Executing Verilog backend. +Dumping module `\I_DELAY_primitive_inst'. + +4.328.5.2.1. Executing BLIF backend. +Dumping config.json +[0.0132289 sec.] +Updating sdc +[0.0100897 sec.] +Time elapsed in design editing : [0.081964 sec.] + +4.328.5.2.2. Executing Verilog backend. +Dumping module `\fabric_I_DELAY_primitive_inst'. + +4.328.5.2.2.1. Executing BLIF backend. + +Warnings: 1 unique messages, 1 total +End of script. Logfile hash: 51223390fa, CPU: user 0.59s system 0.07s, MEM: 23.35 MB peak +Yosys 0.38 (git sha1 4964457dc, gcc 11.2.1 -fPIC -Os) +Time spent: 99% 6x abc (181 sec), 0% 43x read_verilog (0 sec), ... +INFO: SYN: Design I_DELAY_primitive_inst is synthesized +INFO: PAC: ################################################## +INFO: PAC: Packing for design: I_DELAY_primitive_inst +INFO: PAC: ################################################## +Command: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/vpr /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --sdc_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc --route_chan_width 160 --suppress_warnings check_rr_node_warnings.log,check_rr_node --clock_modeling ideal --absorb_buffer_luts off --skip_sync_clustering_and_routing_results off --constant_net_method route --post_place_timing_report I_DELAY_primitive_inst_post_place_timing.rpt --device castor62x44_heterogeneous --allow_unrelated_clustering on --allow_dangling_combinational_nodes on --place_delta_delay_matrix_calculation_method dijkstra --gen_post_synthesis_netlist on --post_synth_netlist_unconn_inputs gnd --inner_loop_recompute_divider 1 --max_router_iterations 1500 --timing_report_detail detailed --timing_report_npaths 100 --top I_DELAY_primitive_inst --net_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net --place_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place --route_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route --pack +VPR FPGA Placement and Routing. +Version: +Revision: +Compiled: +Compiler: GNU 11.2.1 on Linux-3.10.0-1160.90.1.el7.x86_64 x86_64 +Build Info: Release VTR_ASSERT_LEVEL=2 + +University of Toronto +verilogtorouting.org +vtr-users@googlegroups.com +This is free open source code under MIT license. + +VPR was run with the following command-line: +/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/vpr /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --sdc_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc --route_chan_width 160 --suppress_warnings check_rr_node_warnings.log,check_rr_node --clock_modeling ideal --absorb_buffer_luts off --skip_sync_clustering_and_routing_results off --constant_net_method route --post_place_timing_report I_DELAY_primitive_inst_post_place_timing.rpt --device castor62x44_heterogeneous --allow_unrelated_clustering on --allow_dangling_combinational_nodes on --place_delta_delay_matrix_calculation_method dijkstra --gen_post_synthesis_netlist on --post_synth_netlist_unconn_inputs gnd --inner_loop_recompute_divider 1 --max_router_iterations 1500 --timing_report_detail detailed --timing_report_npaths 100 --top I_DELAY_primitive_inst --net_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net --place_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place --route_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route --pack + +Using up to 1 parallel worker(s) + +Architecture file: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml +Circuit name: fabric_I_DELAY_primitive_inst_post_synth + +# Loading Architecture Description +Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 3: Model 'dsp_phy' input port 'sc_in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 4: Model 'dsp_phy' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 5: Model 'dsp_phy' output port 'sc_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 6: Model 'RS_DSP_MULT' input port 'feedback' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 7: Model 'RS_DSP_MULT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 8: Model 'RS_DSP_MULT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 9: Model 'RS_DSP_MULT_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 10: Model 'RS_DSP_MULT_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 11: Model 'RS_DSP_MULT_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 12: Model 'RS_DSP_MULT_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 13: Model 'RS_DSP_MULT_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 14: Model 'RS_DSP_MULT_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 15: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 16: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 17: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 18: Model 'RS_DSP_MULTADD' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 19: Model 'RS_DSP_MULTADD' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 20: Model 'RS_DSP_MULTADD' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 21: Model 'RS_DSP_MULTADD' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 22: Model 'RS_DSP_MULTADD' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 23: Model 'RS_DSP_MULTADD' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 24: Model 'RS_DSP_MULTADD_REGIN' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 25: Model 'RS_DSP_MULTADD_REGIN' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 26: Model 'RS_DSP_MULTADD_REGIN' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 27: Model 'RS_DSP_MULTADD_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 28: Model 'RS_DSP_MULTADD_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 29: Model 'RS_DSP_MULTADD_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 30: Model 'RS_DSP_MULTADD_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 31: Model 'RS_DSP_MULTADD_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 32: Model 'RS_DSP_MULTADD_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 33: Model 'RS_DSP_MULTADD_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 34: Model 'RS_DSP_MULTADD_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 35: Model 'RS_DSP_MULTADD_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 36: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 37: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 38: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 39: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 40: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 41: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 42: Model 'RS_DSP_MULTACC' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 43: Model 'RS_DSP_MULTACC' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 44: Model 'RS_DSP_MULTACC' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 45: Model 'RS_DSP_MULTACC' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 46: Model 'RS_DSP_MULTACC' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 47: Model 'RS_DSP_MULTACC' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 48: Model 'RS_DSP_MULTACC_REGIN' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 49: Model 'RS_DSP_MULTACC_REGIN' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 50: Model 'RS_DSP_MULTACC_REGIN' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 51: Model 'RS_DSP_MULTACC_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 52: Model 'RS_DSP_MULTACC_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 53: Model 'RS_DSP_MULTACC_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 54: Model 'RS_DSP_MULTACC_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 55: Model 'RS_DSP_MULTACC_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 56: Model 'RS_DSP_MULTACC_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 57: Model 'RS_DSP_MULTACC_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 58: Model 'RS_DSP_MULTACC_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 59: Model 'RS_DSP_MULTACC_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 60: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 61: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 62: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 63: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 64: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 65: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 66: Model 'bram_phy' input port 'sc_in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 67: Model 'bram_phy' output port 'sc_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 68: Model 'bram_phy' output port 'PL_DATA_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 69: Model 'bram_phy' output port 'PL_ADDR_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 70: Model 'bram_phy' output port 'PL_WEN_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 71: Model 'bram_phy' output port 'PL_CLK_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 72: Model 'bram_phy' output port 'PL_REN_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 73: Model 'bram_phy' output port 'PL_ENA_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 74: Model 'bram_phy' output port 'PL_INIT_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +mode 'io[physical]' is defined by user to be disabled in packing +mode 'iopad[default]' is defined by user to be disabled in packing +mode 'fle[physical]' is defined by user to be disabled in packing +mode 'fabric[default]' is defined by user to be disabled in packing +mode 'ff_bypass[default]' is defined by user to be disabled in packing +mode 'dsp_lr[physical]' is defined by user to be disabled in packing +mode 'bram_lr[physical]' is defined by user to be disabled in packing +# Loading Architecture Description took 0.06 seconds (max_rss 17.2 MiB, delta_rss +0.0 MiB) + +Timing analysis: ON +Circuit netlist file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net +Circuit placement file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place +Circuit routing file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route +Circuit SDC file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc +Vpr floorplanning constraints file: not specified + +Packer: ENABLED +Placer: DISABLED +Router: DISABLED +Analysis: DISABLED + +VPR was run with the following options: + +NetlistOpts.abosrb_buffer_luts : false +NetlistOpts.sweep_dangling_primary_ios : true +NetlistOpts.sweep_dangling_nets : true +NetlistOpts.sweep_dangling_blocks : true +NetlistOpts.sweep_constant_primary_outputs: false +NetlistOpts.netlist_verbosity : 1 +NetlistOpts.const_gen_inference : COMB_SEQ + +PackerOpts.allow_unrelated_clustering: true +PackerOpts.alpha_clustering: 0.750000 +PackerOpts.beta_clustering: 0.900000 +PackerOpts.cluster_seed_type: BLEND2 +PackerOpts.connection_driven: true +PackerOpts.global_clocks: true +PackerOpts.hill_climbing_flag: false +PackerOpts.inter_cluster_net_delay: 1.000000 +PackerOpts.timing_driven: true +PackerOpts.target_external_pin_util: auto + +# Building complex block graph +Warning 75: clb[0].sr_in[0] unconnected pin in architecture. +Warning 76: clb[0].sr_out[0] unconnected pin in architecture. +Warning 77: dsp[0].sr_in[0] unconnected pin in architecture. +Warning 78: dsp[0].sr_in[1] unconnected pin in architecture. +Warning 79: dsp[0].sr_in[2] unconnected pin in architecture. +Warning 80: dsp[0].sr_out[0] unconnected pin in architecture. +Warning 81: dsp[0].sr_out[1] unconnected pin in architecture. +Warning 82: dsp[0].sr_out[2] unconnected pin in architecture. +Warning 83: bram[0].sr_in[0] unconnected pin in architecture. +Warning 84: bram[0].sr_in[1] unconnected pin in architecture. +Warning 85: bram[0].sr_in[2] unconnected pin in architecture. +Warning 86: bram[0].sr_in[3] unconnected pin in architecture. +Warning 87: bram[0].sr_in[4] unconnected pin in architecture. +Warning 88: bram[0].sr_in[5] unconnected pin in architecture. +Warning 89: bram[0].plr_i[0] unconnected pin in architecture. +Warning 90: bram[0].plr_i[1] unconnected pin in architecture. +Warning 91: bram[0].plr_i[2] unconnected pin in architecture. +Warning 92: bram[0].plr_i[3] unconnected pin in architecture. +Warning 93: bram[0].plr_i[4] unconnected pin in architecture. +Warning 94: bram[0].plr_i[5] unconnected pin in architecture. +Warning 95: bram[0].plr_i[6] unconnected pin in architecture. +Warning 96: bram[0].plr_i[7] unconnected pin in architecture. +Warning 97: bram[0].plr_i[8] unconnected pin in architecture. +Warning 98: bram[0].plr_i[9] unconnected pin in architecture. +Warning 99: bram[0].plr_i[10] unconnected pin in architecture. +Warning 100: bram[0].plr_i[11] unconnected pin in architecture. +Warning 101: bram[0].plr_i[12] unconnected pin in architecture. +Warning 102: bram[0].plr_i[13] unconnected pin in architecture. +Warning 103: bram[0].plr_i[14] unconnected pin in architecture. +Warning 104: bram[0].plr_i[15] unconnected pin in architecture. +Warning 105: bram[0].plr_i[16] unconnected pin in architecture. +Warning 106: bram[0].plr_i[17] unconnected pin in architecture. +Warning 107: bram[0].plr_i[18] unconnected pin in architecture. +Warning 108: bram[0].plr_i[19] unconnected pin in architecture. +Warning 109: bram[0].plr_i[20] unconnected pin in architecture. +Warning 110: bram[0].plr_i[21] unconnected pin in architecture. +Warning 111: bram[0].plr_i[22] unconnected pin in architecture. +Warning 112: bram[0].plr_i[23] unconnected pin in architecture. +Warning 113: bram[0].plr_i[24] unconnected pin in architecture. +Warning 114: bram[0].plr_i[25] unconnected pin in architecture. +Warning 115: bram[0].plr_i[26] unconnected pin in architecture. +Warning 116: bram[0].plr_i[27] unconnected pin in architecture. +Warning 117: bram[0].plr_i[28] unconnected pin in architecture. +Warning 118: bram[0].plr_i[29] unconnected pin in architecture. +Warning 119: bram[0].plr_i[30] unconnected pin in architecture. +Warning 120: bram[0].plr_i[31] unconnected pin in architecture. +Warning 121: bram[0].plr_i[32] unconnected pin in architecture. +Warning 122: bram[0].plr_i[33] unconnected pin in architecture. +Warning 123: bram[0].plr_i[34] unconnected pin in architecture. +Warning 124: bram[0].plr_i[35] unconnected pin in architecture. +Warning 125: bram[0].sr_out[0] unconnected pin in architecture. +Warning 126: bram[0].sr_out[1] unconnected pin in architecture. +Warning 127: bram[0].sr_out[2] unconnected pin in architecture. +Warning 128: bram[0].sr_out[3] unconnected pin in architecture. +Warning 129: bram[0].sr_out[4] unconnected pin in architecture. +Warning 130: bram[0].sr_out[5] unconnected pin in architecture. +Warning 131: bram[0].plr_o[0] unconnected pin in architecture. +Warning 132: bram[0].plr_o[1] unconnected pin in architecture. +Warning 133: bram[0].plr_o[2] unconnected pin in architecture. +Warning 134: bram[0].plr_o[3] unconnected pin in architecture. +Warning 135: bram[0].plr_o[4] unconnected pin in architecture. +Warning 136: bram[0].plr_o[5] unconnected pin in architecture. +Warning 137: bram[0].plr_o[6] unconnected pin in architecture. +Warning 138: bram[0].plr_o[7] unconnected pin in architecture. +Warning 139: bram[0].plr_o[8] unconnected pin in architecture. +Warning 140: bram[0].plr_o[9] unconnected pin in architecture. +Warning 141: bram[0].plr_o[10] unconnected pin in architecture. +Warning 142: bram[0].plr_o[11] unconnected pin in architecture. +Warning 143: bram[0].plr_o[12] unconnected pin in architecture. +Warning 144: bram[0].plr_o[13] unconnected pin in architecture. +Warning 145: bram[0].plr_o[14] unconnected pin in architecture. +Warning 146: bram[0].plr_o[15] unconnected pin in architecture. +Warning 147: bram[0].plr_o[16] unconnected pin in architecture. +Warning 148: bram[0].plr_o[17] unconnected pin in architecture. +Warning 149: bram[0].plr_o[18] unconnected pin in architecture. +Warning 150: bram[0].plr_o[19] unconnected pin in architecture. +Warning 151: bram[0].plr_o[20] unconnected pin in architecture. +Warning 152: bram[0].plr_o[21] unconnected pin in architecture. +Warning 153: bram[0].plr_o[22] unconnected pin in architecture. +Warning 154: bram[0].plr_o[23] unconnected pin in architecture. +Warning 155: bram[0].plr_o[24] unconnected pin in architecture. +Warning 156: bram[0].plr_o[25] unconnected pin in architecture. +Warning 157: bram[0].plr_o[26] unconnected pin in architecture. +Warning 158: bram[0].plr_o[27] unconnected pin in architecture. +Warning 159: bram[0].plr_o[28] unconnected pin in architecture. +Warning 160: bram[0].plr_o[29] unconnected pin in architecture. +Warning 161: bram[0].plr_o[30] unconnected pin in architecture. +Warning 162: bram[0].plr_o[31] unconnected pin in architecture. +Warning 163: bram[0].plr_o[32] unconnected pin in architecture. +Warning 164: bram[0].plr_o[33] unconnected pin in architecture. +Warning 165: bram[0].plr_o[34] unconnected pin in architecture. +Warning 166: bram[0].plr_o[35] unconnected pin in architecture. +# Building complex block graph took 0.04 seconds (max_rss 18.2 MiB, delta_rss +1.1 MiB) +Circuit file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif +# Load circuit +Found constant-zero generator '$false' +Found constant-one generator '$true' +Found constant-zero generator '$undef' +# Load circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.5 MiB) +# Clean circuit +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 13 additional primitive pins as constant generators due to constant inputs +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 0 additional primitive pins as constant generators due to constant inputs +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 0 additional primitive pins as constant generators due to constant inputs +Swept input(s) : 0 +Swept output(s) : 0 (0 dangling, 0 constant) +Swept net(s) : 2 +Swept block(s) : 2 +Constant Pins Marked: 13 +# Clean circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +# Compress circuit +# Compress circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +# Verify circuit +# Verify circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +Circuit Statistics: + Blocks: 69 + .input : 13 + .output: 24 + 0-LUT : 1 + 6-LUT : 30 + dffre : 1 + Nets : 45 + Avg Fanout: 1.3 + Max Fanout: 15.0 + Min Fanout: 1.0 + Netlist Clocks: 1 +# Build Timing Graph + Timing Graph Nodes: 104 + Timing Graph Edges: 94 + Timing Graph Levels: 6 +# Build Timing Graph took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +Netlist contains 1 clocks + Netlist Clock '$clk_buf_$ibuf_CLK_IN' Fanout: 1 pins (1.0%), 1 blocks (1.4%) +# Load Timing Constraints + +SDC file '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc' contained no SDC commands +Setting default timing constraints: + * constrain all primay inputs and primary outputs on netlist clock '$clk_buf_$ibuf_CLK_IN' + * optimize netlist clock to run as fast as possible +Timing constraints created 1 clocks + Constrained Clock '$clk_buf_$ibuf_CLK_IN' Source: '$clk_buf_$ibuf_CLK_IN.inpad[0]' + +# Load Timing Constraints took 0.00 seconds (max_rss 19.0 MiB, delta_rss +0.3 MiB) +# Packing +Begin packing '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif'. + +After removing unused inputs... + total blocks: 69, total nets: 45, total inputs: 13, total outputs: 24 +Begin prepacking. + +There is one chain in this architecture called "carrychain" with the following starting points: + clb[0]/clb_lr[0]/fle[0]/adder[0]/adder_carry[0].cin[0] + +0 attraction groups were created during prepacking. +Finish prepacking. +Using inter-cluster delay: 8.9048e-10 +Packing with pin utilization targets: io_top:1,1 io_right:1,1 io_bottom:1,1 io_left:1,1 clb:0.8,1 dsp:1,1 bram:1,1 +Packing with high fanout thresholds: io_top:128 io_right:128 io_bottom:128 io_left:128 clb:32 dsp:128 bram:128 +Starting Clustering - Clustering Progress: +------------------- -------------------------- --------- +Molecules processed Number of clusters created FPGA size +------------------- -------------------------- --------- + 2/68 2% 1 64 x 46 + 4/68 5% 1 64 x 46 + 6/68 8% 1 64 x 46 + 8/68 11% 1 64 x 46 + 10/68 14% 1 64 x 46 + 12/68 17% 1 64 x 46 + 14/68 20% 1 64 x 46 + 16/68 23% 1 64 x 46 + 18/68 26% 2 64 x 46 + 20/68 29% 2 64 x 46 + 22/68 32% 2 64 x 46 + 24/68 35% 2 64 x 46 + 26/68 38% 2 64 x 46 + 28/68 41% 2 64 x 46 + 30/68 44% 2 64 x 46 + 32/68 47% 2 64 x 46 + 34/68 50% 4 64 x 46 + 36/68 52% 6 64 x 46 + 38/68 55% 8 64 x 46 + 40/68 58% 10 64 x 46 + 42/68 61% 12 64 x 46 + 44/68 64% 14 64 x 46 + 46/68 67% 16 64 x 46 + 48/68 70% 18 64 x 46 + 50/68 73% 20 64 x 46 + 52/68 76% 22 64 x 46 + 54/68 79% 24 64 x 46 + 56/68 82% 26 64 x 46 + 58/68 85% 28 64 x 46 + 60/68 88% 30 64 x 46 + 62/68 91% 32 64 x 46 + 64/68 94% 34 64 x 46 + 66/68 97% 36 64 x 46 + 68/68 100% 38 64 x 46 + +Logic Element (fle) detailed count: + Total number of Logic Elements used : 16 + LEs used for logic and registers : 0 + LEs used for logic only : 16 + LEs used for registers only : 0 + +Incr Slack updates 1 in 3.518e-06 sec +Full Max Req/Worst Slack updates 1 in 6.294e-06 sec +Incr Max Req/Worst Slack updates 0 in 0 sec +Incr Criticality updates 0 in 0 sec +Full Criticality updates 1 in 8.597e-06 sec +FPGA sized to 64 x 46 (castor62x44_heterogeneous) +Device Utilization: 0.00 (target 1.00) + Block Utilization: 0.00 Type: io + Block Utilization: 0.00 Type: clb + +Start the iterative improvement process +the iterative improvement process is done +Clustering Statistics: +---------- -------- ------------------------------------ -------------------------- +Block Type # Blocks Avg. # of input clocks and pins used Avg. # of output pins used +---------- -------- ------------------------------------ -------------------------- + EMPTY 0 0 0 + io 37 0.648649 0.351351 + clb 2 8 13 + dsp 0 0 0 + bram 0 0 0 +Absorbed logical nets 6 out of 45 nets, 39 nets not absorbed. + +Netlist conversion complete. + +# Packing took 0.02 seconds (max_rss 20.9 MiB, delta_rss +1.6 MiB) +# Load packing +Begin loading packed FPGA netlist file. +Netlist generated from file '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net'. +Detected 1 constant generators (to see names run with higher pack verbosity) +Finished loading packed FPGA netlist file (took 0.05 seconds). +# Load packing took 0.05 seconds (max_rss 59.0 MiB, delta_rss +38.1 MiB) +Warning 167: Netlist contains 0 global net to non-global architecture pin connections +Cluster level netlist and block usage statistics +Netlist num_nets: 39 +Netlist num_blocks: 39 +Netlist EMPTY blocks: 0. +Netlist io blocks: 37. +Netlist clb blocks: 2. +Netlist dsp blocks: 0. +Netlist bram blocks: 0. +Netlist inputs pins: 13 +Netlist output pins: 24 + +Pb types usage... + io : 37 + io_output : 24 + outpad : 24 + io_input : 13 + inpad : 13 + clb : 2 + clb_lr : 2 + fle : 16 + ble5 : 31 + lut5 : 31 + lut : 31 + ff : 1 + DFFRE : 1 + +# Create Device +## Build Device Grid +FPGA sized to 64 x 46: 2944 grid tiles (castor62x44_heterogeneous) + +Resource usage... + Netlist + 37 blocks of type: io + Architecture + 4320 blocks of type: io_top + 3168 blocks of type: io_right + 4320 blocks of type: io_bottom + 3168 blocks of type: io_left + Netlist + 2 blocks of type: clb + Architecture + 2184 blocks of type: clb + Netlist + 0 blocks of type: dsp + Architecture + 56 blocks of type: dsp + Netlist + 0 blocks of type: bram + Architecture + 56 blocks of type: bram + +Device Utilization: 0.00 (target 1.00) + Physical Tile io_top: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_right: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_bottom: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_left: + Block Utilization: 0.01 Logical Block: io + Physical Tile clb: + Block Utilization: 0.00 Logical Block: clb + Physical Tile dsp: + Block Utilization: 0.00 Logical Block: dsp + Physical Tile bram: + Block Utilization: 0.00 Logical Block: bram + +## Build Device Grid took 0.00 seconds (max_rss 59.1 MiB, delta_rss +0.0 MiB) +Warning 168: Tileable routing resource graph does not support clock modeling yet! Related options are ignored... +## Build tileable routing resource graph +X-direction routing channel width is 160 +Y-direction routing channel width is 160 +Warning 169: Sized nonsensical R=0 transistor to minimum width +Warning 170: Sized nonsensical R=0 transistor to minimum width +Warning 171: Sized nonsensical R=0 transistor to minimum width +Warning 172: Sized nonsensical R=0 transistor to minimum width +## Build tileable routing resource graph took 13.42 seconds (max_rss 473.6 MiB, delta_rss +414.5 MiB) + RR Graph Nodes: 1365608 + RR Graph Edges: 6033268 +# Create Device took 14.03 seconds (max_rss 473.6 MiB, delta_rss +414.5 MiB) + + +Flow timing analysis took 0.00177694 seconds (0.00174604 STA, 3.0901e-05 slack) (1 full updates: 1 setup, 0 hold, 0 combined). +VPR succeeded +The entire flow of VPR took 14.56 seconds (max_rss 473.6 MiB) +INFO: PAC: Design I_DELAY_primitive_inst is packed +INFO: PLC: ################################################## +INFO: PLC: Placement for design: I_DELAY_primitive_inst +INFO: PLC: ################################################## +Command: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/planning --csv /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/Virgo_Pin_Table.csv --blif /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --output I_DELAY_primitive_inst_pin_loc.place --assign_unconstrained_pins in_define_order --clk_map I_DELAY_primitive_inst.temp_file_clkmap --read_repack /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/fpga_repack_constraints.xml --write_repack I_DELAY_primitive_inst_repack_constraints.xml --edits /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/config.json + + pln0338 + compiled: Sep 19 2024 10:03:23 + + pin_c +Flags : +Params : + --assign_unconstrained_pins in_define_order + --blif /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif + --clk_map I_DELAY_primitive_inst.temp_file_clkmap + --csv /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/Virgo_Pin_Table.csv + --edits /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/config.json + --output I_DELAY_primitive_inst_pin_loc.place + --read_repack /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/fpga_repack_constraints.xml + --write_repack I_DELAY_primitive_inst_repack_constraints.xml + + +******************************** + + +******************************** + + + + === pin_c options === + xml_name (--xml) : + csv_name (--csv) : /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/Virgo_Pin_Table.csv + user_pcf_ (--pcf) : + blif_name (--blif) : /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif + json_name (--port_info) : + edits_file (--edits) : /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/config.json + output_name (--output) : I_DELAY_primitive_inst_pin_loc.place + assign_method= in_define_order + +... reading /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif + +____ BEGIN pinc_check_blif: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif + + (blif_file) #inputs= 13 #outputs= 24 topModel= fabric_I_DELAY_primitive_inst + +>>>>> checking BLIF /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif ... + + +===== passed: YES +----- topModel: fabric_I_DELAY_primitive_inst +----- file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif +----- #inputs= 13 +----- #outputs= 24 +----- #LUTs= 1 +----- #LUT1= 0 +----- #LUT5= 0 +----- #LUT6= 0 +----- #FFs= 1 +----- #I_BUFs= 0 +----- #O_BUFs= 0 +----- #CLK_BUFs= 0 +----- #I_SERDES= 0 +----- #DSP19X= 0 +----- #DSP38= 0 +----- PinGraph: +===== passed: YES + +===== BLIF is OK. + + pinc_check_blif STATUS = PASS + +------ END pinc_check_blif: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif + + (blif_file) #inputs= 13 #outputs= 24 topModel= fabric_I_DELAY_primitive_inst + +pin_c: finished read_blif(). #inputs= 13 #outputs= 24 + +DONE read_design_ports() #udes_inputs= 13 #udes_outputs= 24 + + +read_PT_CSV() __ Reading csv + cvs_name= /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/Virgo_Pin_Table.csv +pin_c CsvReader::read_csv( /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/Virgo_Pin_Table.csv ) num_udes_pins= 37 +pin_c CSV: #rows= 5270 #colums= 76 + #RX_cols= 17 #TX_cols= 17 #GPIO_cols= 1 + +initRows: num_rows= 5270 num_cols= 76 start_GBOX_GPIO_row_= 367 + + + *** pin_c read_PT_CSV SUCCEEDED *** + + + has_edits_ : /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/config.json + +translatePinNames() @ (auto-PCF) + +DONE translatePinNames() @ (auto-PCF) + number of translated pins = 7 + + ---- dumping user_design_inputs_ after translation (13) -- + inp-0 CLK_IN + inp-1 DLY_ADJ + inp-2 DLY_INCDEC + inp-3 DLY_LOAD + inp-4 in + inp-5 reset + inp-6 $ifab_$obuf_DLY_TAP_VALUE[0] + inp-7 $ifab_$obuf_DLY_TAP_VALUE[1] + inp-8 $ifab_$obuf_DLY_TAP_VALUE[2] + inp-9 $ifab_$obuf_DLY_TAP_VALUE[3] + inp-10 $ifab_$obuf_DLY_TAP_VALUE[4] + inp-11 $ifab_$obuf_DLY_TAP_VALUE[5] + inp-12 dff + ---- + ---- dumping user_design_outputs_ after translation (24) -- + out-0 $auto_440 + out-1 $auto_441 + out-2 $auto_442 + out-3 $auto_443 + out-4 $auto_444 + out-5 $auto_445 + out-6 $auto_446 + out-7 $auto_447 + out-8 $auto_448 + out-9 $auto_449 + out-10 $auto_450 + out-11 $auto_451 + out-12 $auto_452 + out-13 $auto_453 + out-14 $f2g_trx_dly_adj_$ibuf_DLY_ADJ + out-15 $f2g_trx_dly_inc_$ibuf_DLY_INCDEC + out-16 $f2g_trx_dly_ld_$ibuf_DLY_LOAD + out-17 $f2g_tx_out_$obuf_DLY_TAP_VALUE[0] + out-18 $f2g_tx_out_$obuf_DLY_TAP_VALUE[1] + out-19 $f2g_tx_out_$obuf_DLY_TAP_VALUE[2] + out-20 $f2g_tx_out_$obuf_DLY_TAP_VALUE[3] + out-21 $f2g_tx_out_$obuf_DLY_TAP_VALUE[4] + out-22 $f2g_tx_out_$obuf_DLY_TAP_VALUE[5] + out-23 dff + ---- + + [CRITICAL_WARNING] pin 'dff' is both input and output (after NL-edits). + + [CRITICAL_WARNING] pin 'dff' is both input and output (after NL-edits). + + +create_temp_pcf() : 128755.temp_pcf.pcf + +--- writing pcf inputs (13) + +--- writing pcf outputs (24) + +pin_c: reading .pcf from 128755.temp_pcf.pcf + +PcfReader::read_pcf_file( 128755.temp_pcf.pcf ) +pin_c PCF: num_pcf_commands= 37 num_internal_pins= 0 + + *** pin_c read_PCF SUCCEEDED *** +translatePinNames() @ (finalize_edits) + +DONE translatePinNames() @ (finalize_edits) + number of translated pins = 7 +PCF command translation: #input translations= 8 #output translations= 0 +total number of translated PCF commands = 8 + +pin_c: writing .place output file: I_DELAY_primitive_inst_pin_loc.place + +written 37 pins to I_DELAY_primitive_inst_pin_loc.place + min_pt_row= 13 max_pt_row= 60 +pin_c: write_clocks_logical_to_physical().. +pin_c: current directory= /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement + +clock mapping: # user-design clocks = 1 # device clocks = 1pin_c: written OK: I_DELAY_primitive_inst_repack_constraints.xml +full path: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/I_DELAY_primitive_inst_repack_constraints.xml +input was: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/fpga_repack_constraints.xml +pin_c: removed clock-map file: I_DELAY_primitive_inst.temp_file_clkmap +PinPlacer::map_clocks() returns OK + +pin_c done: read_and_write() succeeded. map_clk_status= 1 + +======== pin_c stats: + --> got 13 inputs and 24 outputs + + ---- inputs(13): ---- + I $clk_buf_$ibuf_CLK_IN trans--> $clk_buf_$ibuf_CLK_IN placed at (51 44 _23) device: BOOT_PWM2_GPIO_12 pt_row: 59 Fullchip_N: fpga_pad_c[12] + I $ibuf_DLY_ADJ trans--> $ibuf_DLY_ADJ placed at (51 44 _22) device: BOOT_PWM3_GPIO_13 pt_row: 60 Fullchip_N: fpga_pad_c[13] + I $ibuf_DLY_INCDEC trans--> $ibuf_DLY_INCDEC placed at (51 44 _21) device: BOOT_UART_CTS_GPIO_14 pt_row: 61 Fullchip_N: fpga_pad_c[14] + I $ibuf_DLY_LOAD trans--> $ibuf_DLY_LOAD placed at (51 44 _20) device: BOOT_UART_RTS_GPIO_15 pt_row: 62 Fullchip_N: fpga_pad_c[15] + I $ibuf_in trans--> $ibuf_in placed at (48 44 _23) device: BOOT_CONFIG_DONE_GPIO_0 pt_row: 47 Fullchip_N: fpga_pad_c[0] + I $ibuf_reset trans--> $ibuf_reset placed at (48 44 _22) device: BOOT_CONFIG_ERROR_GPIO_1 pt_row: 48 Fullchip_N: fpga_pad_c[1] + I $ifab_$obuf_DLY_TAP_VALUE[0] trans--> $ifab_$obuf_DLY_TAP_VALUE[0] placed at (48 44 _21) device: BOOT_UART_TX_GPIO_2 pt_row: 49 Fullchip_N: fpga_pad_c[2] + I $ifab_$obuf_DLY_TAP_VALUE[1] trans--> $ifab_$obuf_DLY_TAP_VALUE[1] placed at (48 44 _20) device: BOOT_UART_RX_GPIO_3 pt_row: 50 Fullchip_N: fpga_pad_c[3] + I $ifab_$obuf_DLY_TAP_VALUE[2] trans--> $ifab_$obuf_DLY_TAP_VALUE[2] placed at (48 44 _19) device: BOOT_SPI_CS_GPIO_4 pt_row: 51 Fullchip_N: fpga_pad_c[4] + I $ifab_$obuf_DLY_TAP_VALUE[3] trans--> $ifab_$obuf_DLY_TAP_VALUE[3] placed at (48 44 _18) device: BOOT_SPI_MOSI_DQ0_GPIO_5 pt_row: 52 Fullchip_N: fpga_pad_c[5] + I $ifab_$obuf_DLY_TAP_VALUE[4] trans--> $ifab_$obuf_DLY_TAP_VALUE[4] placed at (48 44 _17) device: BOOT_SPI_MISO_DQ1_GPIO_6 pt_row: 53 Fullchip_N: fpga_pad_c[6] + I $ifab_$obuf_DLY_TAP_VALUE[5] trans--> $ifab_$obuf_DLY_TAP_VALUE[5] placed at (48 44 _16) device: BOOT_SPI_DQ2_GPIO_7 pt_row: 54 Fullchip_N: fpga_pad_c[7] + I $obuf_O trans--> $obuf_O placed at (48 44 _15) device: BOOT_SPI_DQ3_GPIO_8 pt_row: 55 Fullchip_N: fpga_pad_c[8] + + ---- outputs(24): ---- + O $auto_440 trans--> $auto_440 placed at (49 44 _71) device: BOOT_CONFIG_DONE_GPIO_0 pt_row: 15 Fullchip_N: fpga_pad_i[0] CustomerInternal_BU: SOC_GPIO0_O + O $auto_441 trans--> $auto_441 placed at (49 44 _70) device: BOOT_CONFIG_ERROR_GPIO_1 pt_row: 16 Fullchip_N: fpga_pad_i[1] CustomerInternal_BU: SOC_GPIO1_O + O $auto_442 trans--> $auto_442 placed at (49 44 _69) device: BOOT_UART_TX_GPIO_2 pt_row: 17 Fullchip_N: fpga_pad_i[2] CustomerInternal_BU: SOC_GPIO2_O + O $auto_443 trans--> $auto_443 placed at (49 44 _68) device: BOOT_UART_RX_GPIO_3 pt_row: 18 Fullchip_N: fpga_pad_i[3] CustomerInternal_BU: SOC_GPIO3_O + O $auto_444 trans--> $auto_444 placed at (49 44 _67) device: BOOT_SPI_CS_GPIO_4 pt_row: 19 Fullchip_N: fpga_pad_i[4] CustomerInternal_BU: SOC_GPIO4_O + O $auto_445 trans--> $auto_445 placed at (49 44 _66) device: BOOT_SPI_MOSI_DQ0_GPIO_5 pt_row: 20 Fullchip_N: fpga_pad_i[5] CustomerInternal_BU: SOC_GPIO5_O + O $auto_446 trans--> $auto_446 placed at (49 44 _65) device: BOOT_SPI_MISO_DQ1_GPIO_6 pt_row: 21 Fullchip_N: fpga_pad_i[6] CustomerInternal_BU: SOC_GPIO6_O + O $auto_447 trans--> $auto_447 placed at (49 44 _64) device: BOOT_SPI_DQ2_GPIO_7 pt_row: 22 Fullchip_N: fpga_pad_i[7] CustomerInternal_BU: SOC_GPIO7_O + O $auto_448 trans--> $auto_448 placed at (49 44 _63) device: BOOT_SPI_DQ3_GPIO_8 pt_row: 23 Fullchip_N: fpga_pad_i[8] CustomerInternal_BU: SOC_GPIO16_O + O $auto_449 trans--> $auto_449 placed at (49 44 _62) device: BOOT_I2C_SDA_GPIO_9 pt_row: 24 Fullchip_N: fpga_pad_i[9] CustomerInternal_BU: SOC_GPIO17_O + O $auto_450 trans--> $auto_450 placed at (49 44 _61) device: BOOT_PWM0_GPIO_10 pt_row: 25 Fullchip_N: fpga_pad_i[10] CustomerInternal_BU: SOC_GPIO18_O + O $auto_451 trans--> $auto_451 placed at (49 44 _60) device: BOOT_PWM1_GPIO_11 pt_row: 26 Fullchip_N: fpga_pad_i[11] CustomerInternal_BU: SOC_GPIO19_O + O $auto_452 trans--> $auto_452 placed at (49 44 _59) device: BOOT_PWM2_GPIO_12 pt_row: 27 Fullchip_N: fpga_pad_i[12] CustomerInternal_BU: SOC_GPIO20_O + O $auto_453 trans--> $auto_453 placed at (49 44 _58) device: BOOT_PWM3_GPIO_13 pt_row: 28 Fullchip_N: fpga_pad_i[13] CustomerInternal_BU: SOC_GPIO21_O + O $f2g_trx_dly_adj_$ibuf_DLY_ADJ trans--> $f2g_trx_dly_adj_$ibuf_DLY_ADJ placed at (49 44 _57) device: BOOT_UART_CTS_GPIO_14 pt_row: 29 Fullchip_N: fpga_pad_i[14] CustomerInternal_BU: SOC_GPIO22_O + O $f2g_trx_dly_inc_$ibuf_DLY_INCDEC trans--> $f2g_trx_dly_inc_$ibuf_DLY_INCDEC placed at (49 44 _56) device: BOOT_UART_RTS_GPIO_15 pt_row: 30 Fullchip_N: fpga_pad_i[15] CustomerInternal_BU: SOC_GPIO23_O + O $f2g_trx_dly_ld_$ibuf_DLY_LOAD trans--> $f2g_trx_dly_ld_$ibuf_DLY_LOAD placed at (51 44 _71) device: BOOT_CONFIG_DONE_GPIO_0 pt_row: 31 Fullchip_N: fpga_pad_oen[0] CustomerInternal_BU: SOC_GPIO0_O + O $f2g_tx_out_$obuf_DLY_TAP_VALUE[0] trans--> $f2g_tx_out_$obuf_DLY_TAP_VALUE[0] placed at (51 44 _70) device: BOOT_CONFIG_ERROR_GPIO_1 pt_row: 32 Fullchip_N: fpga_pad_oen[1] CustomerInternal_BU: SOC_GPIO1_O + O $f2g_tx_out_$obuf_DLY_TAP_VALUE[1] trans--> $f2g_tx_out_$obuf_DLY_TAP_VALUE[1] placed at (51 44 _69) device: BOOT_UART_TX_GPIO_2 pt_row: 33 Fullchip_N: fpga_pad_oen[2] CustomerInternal_BU: SOC_GPIO2_O + O $f2g_tx_out_$obuf_DLY_TAP_VALUE[2] trans--> $f2g_tx_out_$obuf_DLY_TAP_VALUE[2] placed at (51 44 _68) device: BOOT_UART_RX_GPIO_3 pt_row: 34 Fullchip_N: fpga_pad_oen[3] CustomerInternal_BU: SOC_GPIO3_O + O $f2g_tx_out_$obuf_DLY_TAP_VALUE[3] trans--> $f2g_tx_out_$obuf_DLY_TAP_VALUE[3] placed at (51 44 _67) device: BOOT_SPI_CS_GPIO_4 pt_row: 35 Fullchip_N: fpga_pad_oen[4] CustomerInternal_BU: SOC_GPIO4_O + O $f2g_tx_out_$obuf_DLY_TAP_VALUE[4] trans--> $f2g_tx_out_$obuf_DLY_TAP_VALUE[4] placed at (51 44 _66) device: BOOT_SPI_MOSI_DQ0_GPIO_5 pt_row: 36 Fullchip_N: fpga_pad_oen[5] CustomerInternal_BU: SOC_GPIO5_O + O $f2g_tx_out_$obuf_DLY_TAP_VALUE[5] trans--> $f2g_tx_out_$obuf_DLY_TAP_VALUE[5] placed at (51 44 _65) device: BOOT_SPI_MISO_DQ1_GPIO_6 pt_row: 37 Fullchip_N: fpga_pad_oen[6] CustomerInternal_BU: SOC_GPIO6_O + O dff trans--> dff + + <----- pin_c got 13 inputs and 24 outputs + <-- pin_c placed 14 inputs and 23 outputs + min_pt_row= 15 max_pt_row= 62 + +ROW-RECORD stats ( numRows= 5270 ) + No_dir : 710 + Input_dir : 1992 + Output_dir : 1320 + HasBoth_dir : 840 + AllEnabled_dir : 408 + #AXI = 0 + #GPIO = 50 + #GBOX_GPIO = 4840 + #inp_colm A2F = 1815 + #out_colm F2A = 3355 +======== end pin_c stats. + +======== pin_c summary: + Pin Table csv : /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/Virgo_Pin_Table.csv + BLIF file : /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif + total design inputs: 13 placed design inputs: 14 + total design outputs: 24 placed design outputs: 23 + pin_c output : I_DELAY_primitive_inst_pin_loc.place + auto-PCF : TRUE + has edits (config.json) : /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/config.json + clk_map_file : I_DELAY_primitive_inst.temp_file_clkmap + check BLIF status : PASS + pinc_trace verbosity= 3 + + [Error] NOTE CRITICAL_WARNINGs (1) + + [Error] NOTE CRITICAL_WARNINGs (1) + +======== end pin_c summary. + +deal_pinc() succeeded. + +Command: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/vpr /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --sdc_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc --route_chan_width 160 --suppress_warnings check_rr_node_warnings.log,check_rr_node --clock_modeling ideal --absorb_buffer_luts off --skip_sync_clustering_and_routing_results off --constant_net_method route --post_place_timing_report I_DELAY_primitive_inst_post_place_timing.rpt --device castor62x44_heterogeneous --allow_unrelated_clustering on --allow_dangling_combinational_nodes on --place_delta_delay_matrix_calculation_method dijkstra --gen_post_synthesis_netlist on --post_synth_netlist_unconn_inputs gnd --inner_loop_recompute_divider 1 --max_router_iterations 1500 --timing_report_detail detailed --timing_report_npaths 100 --top I_DELAY_primitive_inst --net_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net --place_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place --route_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route --place --fix_clusters I_DELAY_primitive_inst_pin_loc.place +VPR FPGA Placement and Routing. +Version: +Revision: +Compiled: +Compiler: GNU 11.2.1 on Linux-3.10.0-1160.90.1.el7.x86_64 x86_64 +Build Info: Release VTR_ASSERT_LEVEL=2 + +University of Toronto +verilogtorouting.org +vtr-users@googlegroups.com +This is free open source code under MIT license. + +VPR was run with the following command-line: +/nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/vpr /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --sdc_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc --route_chan_width 160 --suppress_warnings check_rr_node_warnings.log,check_rr_node --clock_modeling ideal --absorb_buffer_luts off --skip_sync_clustering_and_routing_results off --constant_net_method route --post_place_timing_report I_DELAY_primitive_inst_post_place_timing.rpt --device castor62x44_heterogeneous --allow_unrelated_clustering on --allow_dangling_combinational_nodes on --place_delta_delay_matrix_calculation_method dijkstra --gen_post_synthesis_netlist on --post_synth_netlist_unconn_inputs gnd --inner_loop_recompute_divider 1 --max_router_iterations 1500 --timing_report_detail detailed --timing_report_npaths 100 --top I_DELAY_primitive_inst --net_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net --place_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place --route_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route --place --fix_clusters I_DELAY_primitive_inst_pin_loc.place + +Using up to 1 parallel worker(s) + +Architecture file: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml +Circuit name: fabric_I_DELAY_primitive_inst_post_synth + +# Loading Architecture Description +Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 3: Model 'dsp_phy' input port 'sc_in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 4: Model 'dsp_phy' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 5: Model 'dsp_phy' output port 'sc_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 6: Model 'RS_DSP_MULT' input port 'feedback' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 7: Model 'RS_DSP_MULT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 8: Model 'RS_DSP_MULT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 9: Model 'RS_DSP_MULT_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 10: Model 'RS_DSP_MULT_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 11: Model 'RS_DSP_MULT_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 12: Model 'RS_DSP_MULT_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 13: Model 'RS_DSP_MULT_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 14: Model 'RS_DSP_MULT_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 15: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 16: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 17: Model 'RS_DSP_MULT_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 18: Model 'RS_DSP_MULTADD' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 19: Model 'RS_DSP_MULTADD' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 20: Model 'RS_DSP_MULTADD' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 21: Model 'RS_DSP_MULTADD' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 22: Model 'RS_DSP_MULTADD' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 23: Model 'RS_DSP_MULTADD' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 24: Model 'RS_DSP_MULTADD_REGIN' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 25: Model 'RS_DSP_MULTADD_REGIN' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 26: Model 'RS_DSP_MULTADD_REGIN' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 27: Model 'RS_DSP_MULTADD_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 28: Model 'RS_DSP_MULTADD_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 29: Model 'RS_DSP_MULTADD_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 30: Model 'RS_DSP_MULTADD_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 31: Model 'RS_DSP_MULTADD_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 32: Model 'RS_DSP_MULTADD_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 33: Model 'RS_DSP_MULTADD_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 34: Model 'RS_DSP_MULTADD_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 35: Model 'RS_DSP_MULTADD_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 36: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 37: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 38: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 39: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 40: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 41: Model 'RS_DSP_MULTADD_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 42: Model 'RS_DSP_MULTACC' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 43: Model 'RS_DSP_MULTACC' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 44: Model 'RS_DSP_MULTACC' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 45: Model 'RS_DSP_MULTACC' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 46: Model 'RS_DSP_MULTACC' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 47: Model 'RS_DSP_MULTACC' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 48: Model 'RS_DSP_MULTACC_REGIN' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 49: Model 'RS_DSP_MULTACC_REGIN' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 50: Model 'RS_DSP_MULTACC_REGIN' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 51: Model 'RS_DSP_MULTACC_REGIN' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 52: Model 'RS_DSP_MULTACC_REGIN' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 53: Model 'RS_DSP_MULTACC_REGIN' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 54: Model 'RS_DSP_MULTACC_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 55: Model 'RS_DSP_MULTACC_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 56: Model 'RS_DSP_MULTACC_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 57: Model 'RS_DSP_MULTACC_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 58: Model 'RS_DSP_MULTACC_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 59: Model 'RS_DSP_MULTACC_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 60: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'round' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 61: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'shift_right' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 62: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'saturate_enable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 63: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'lreset' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 64: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'unsigned_b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 65: Model 'RS_DSP_MULTACC_REGIN_REGOUT' input port 'unsigned_a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 66: Model 'bram_phy' input port 'sc_in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 67: Model 'bram_phy' output port 'sc_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 68: Model 'bram_phy' output port 'PL_DATA_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 69: Model 'bram_phy' output port 'PL_ADDR_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 70: Model 'bram_phy' output port 'PL_WEN_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 71: Model 'bram_phy' output port 'PL_CLK_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 72: Model 'bram_phy' output port 'PL_REN_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 73: Model 'bram_phy' output port 'PL_ENA_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 74: Model 'bram_phy' output port 'PL_INIT_o' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +mode 'io[physical]' is defined by user to be disabled in packing +mode 'iopad[default]' is defined by user to be disabled in packing +mode 'fle[physical]' is defined by user to be disabled in packing +mode 'fabric[default]' is defined by user to be disabled in packing +mode 'ff_bypass[default]' is defined by user to be disabled in packing +mode 'dsp_lr[physical]' is defined by user to be disabled in packing +mode 'bram_lr[physical]' is defined by user to be disabled in packing +# Loading Architecture Description took 0.06 seconds (max_rss 17.2 MiB, delta_rss +0.0 MiB) + +Timing analysis: ON +Circuit netlist file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net +Circuit placement file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place +Circuit routing file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route +Circuit SDC file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc +Vpr floorplanning constraints file: not specified + +Packer: ENABLED +Placer: ENABLED +Router: DISABLED +Analysis: DISABLED + +VPR was run with the following options: + +NetlistOpts.abosrb_buffer_luts : false +NetlistOpts.sweep_dangling_primary_ios : true +NetlistOpts.sweep_dangling_nets : true +NetlistOpts.sweep_dangling_blocks : true +NetlistOpts.sweep_constant_primary_outputs: false +NetlistOpts.netlist_verbosity : 1 +NetlistOpts.const_gen_inference : COMB_SEQ + +PackerOpts.allow_unrelated_clustering: true +PackerOpts.alpha_clustering: 0.750000 +PackerOpts.beta_clustering: 0.900000 +PackerOpts.cluster_seed_type: BLEND2 +PackerOpts.connection_driven: true +PackerOpts.global_clocks: true +PackerOpts.hill_climbing_flag: false +PackerOpts.inter_cluster_net_delay: 1.000000 +PackerOpts.timing_driven: true +PackerOpts.target_external_pin_util: auto + +PlacerOpts.place_freq: PLACE_ONCE +PlacerOpts.place_algorithm: CRITICALITY_TIMING_PLACE +PlacerOpts.pad_loc_type: FREE +PlacerOpts.constraints_file: Using constraints file 'I_DELAY_primitive_inst_pin_loc.place' +PlacerOpts.place_cost_exp: 1.000000 +PlacerOpts.place_chan_width: 160 +PlacerOpts.inner_loop_recompute_divider: 1 +PlacerOpts.recompute_crit_iter: 1 +PlacerOpts.timing_tradeoff: 0.500000 +PlacerOpts.td_place_exp_first: 1.000000 +PlacerOpts.td_place_exp_last: 8.000000 +PlacerOpts.delay_offset: 0.000000 +PlacerOpts.delay_ramp_delta_threshold: -1 +PlacerOpts.delay_ramp_slope: 0.000000 +PlacerOpts.tsu_rel_margin: 1.000000 +PlacerOpts.tsu_abs_margin: 0.000000 +PlacerOpts.post_place_timing_report_file: I_DELAY_primitive_inst_post_place_timing.rpt +PlacerOpts.allowed_tiles_for_delay_model: +PlacerOpts.delay_model_reducer: MIN +PlacerOpts.delay_model_type: DELTA +PlacerOpts.rlim_escape_fraction: 0.000000 +PlacerOpts.move_stats_file: +PlacerOpts.placement_saves_per_temperature: 0 +PlacerOpts.effort_scaling: CIRCUIT +PlacerOpts.place_delta_delay_matrix_calculation_method: DIJKSTRA_EXPANSION +PlaceOpts.seed: 1 +AnnealSched.type: AUTO_SCHED +AnnealSched.inner_num: 0.500000 + +# Building complex block graph +Warning 75: clb[0].sr_in[0] unconnected pin in architecture. +Warning 76: clb[0].sr_out[0] unconnected pin in architecture. +Warning 77: dsp[0].sr_in[0] unconnected pin in architecture. +Warning 78: dsp[0].sr_in[1] unconnected pin in architecture. +Warning 79: dsp[0].sr_in[2] unconnected pin in architecture. +Warning 80: dsp[0].sr_out[0] unconnected pin in architecture. +Warning 81: dsp[0].sr_out[1] unconnected pin in architecture. +Warning 82: dsp[0].sr_out[2] unconnected pin in architecture. +Warning 83: bram[0].sr_in[0] unconnected pin in architecture. +Warning 84: bram[0].sr_in[1] unconnected pin in architecture. +Warning 85: bram[0].sr_in[2] unconnected pin in architecture. +Warning 86: bram[0].sr_in[3] unconnected pin in architecture. +Warning 87: bram[0].sr_in[4] unconnected pin in architecture. +Warning 88: bram[0].sr_in[5] unconnected pin in architecture. +Warning 89: bram[0].plr_i[0] unconnected pin in architecture. +Warning 90: bram[0].plr_i[1] unconnected pin in architecture. +Warning 91: bram[0].plr_i[2] unconnected pin in architecture. +Warning 92: bram[0].plr_i[3] unconnected pin in architecture. +Warning 93: bram[0].plr_i[4] unconnected pin in architecture. +Warning 94: bram[0].plr_i[5] unconnected pin in architecture. +Warning 95: bram[0].plr_i[6] unconnected pin in architecture. +Warning 96: bram[0].plr_i[7] unconnected pin in architecture. +Warning 97: bram[0].plr_i[8] unconnected pin in architecture. +Warning 98: bram[0].plr_i[9] unconnected pin in architecture. +Warning 99: bram[0].plr_i[10] unconnected pin in architecture. +Warning 100: bram[0].plr_i[11] unconnected pin in architecture. +Warning 101: bram[0].plr_i[12] unconnected pin in architecture. +Warning 102: bram[0].plr_i[13] unconnected pin in architecture. +Warning 103: bram[0].plr_i[14] unconnected pin in architecture. +Warning 104: bram[0].plr_i[15] unconnected pin in architecture. +Warning 105: bram[0].plr_i[16] unconnected pin in architecture. +Warning 106: bram[0].plr_i[17] unconnected pin in architecture. +Warning 107: bram[0].plr_i[18] unconnected pin in architecture. +Warning 108: bram[0].plr_i[19] unconnected pin in architecture. +Warning 109: bram[0].plr_i[20] unconnected pin in architecture. +Warning 110: bram[0].plr_i[21] unconnected pin in architecture. +Warning 111: bram[0].plr_i[22] unconnected pin in architecture. +Warning 112: bram[0].plr_i[23] unconnected pin in architecture. +Warning 113: bram[0].plr_i[24] unconnected pin in architecture. +Warning 114: bram[0].plr_i[25] unconnected pin in architecture. +Warning 115: bram[0].plr_i[26] unconnected pin in architecture. +Warning 116: bram[0].plr_i[27] unconnected pin in architecture. +Warning 117: bram[0].plr_i[28] unconnected pin in architecture. +Warning 118: bram[0].plr_i[29] unconnected pin in architecture. +Warning 119: bram[0].plr_i[30] unconnected pin in architecture. +Warning 120: bram[0].plr_i[31] unconnected pin in architecture. +Warning 121: bram[0].plr_i[32] unconnected pin in architecture. +Warning 122: bram[0].plr_i[33] unconnected pin in architecture. +Warning 123: bram[0].plr_i[34] unconnected pin in architecture. +Warning 124: bram[0].plr_i[35] unconnected pin in architecture. +Warning 125: bram[0].sr_out[0] unconnected pin in architecture. +Warning 126: bram[0].sr_out[1] unconnected pin in architecture. +Warning 127: bram[0].sr_out[2] unconnected pin in architecture. +Warning 128: bram[0].sr_out[3] unconnected pin in architecture. +Warning 129: bram[0].sr_out[4] unconnected pin in architecture. +Warning 130: bram[0].sr_out[5] unconnected pin in architecture. +Warning 131: bram[0].plr_o[0] unconnected pin in architecture. +Warning 132: bram[0].plr_o[1] unconnected pin in architecture. +Warning 133: bram[0].plr_o[2] unconnected pin in architecture. +Warning 134: bram[0].plr_o[3] unconnected pin in architecture. +Warning 135: bram[0].plr_o[4] unconnected pin in architecture. +Warning 136: bram[0].plr_o[5] unconnected pin in architecture. +Warning 137: bram[0].plr_o[6] unconnected pin in architecture. +Warning 138: bram[0].plr_o[7] unconnected pin in architecture. +Warning 139: bram[0].plr_o[8] unconnected pin in architecture. +Warning 140: bram[0].plr_o[9] unconnected pin in architecture. +Warning 141: bram[0].plr_o[10] unconnected pin in architecture. +Warning 142: bram[0].plr_o[11] unconnected pin in architecture. +Warning 143: bram[0].plr_o[12] unconnected pin in architecture. +Warning 144: bram[0].plr_o[13] unconnected pin in architecture. +Warning 145: bram[0].plr_o[14] unconnected pin in architecture. +Warning 146: bram[0].plr_o[15] unconnected pin in architecture. +Warning 147: bram[0].plr_o[16] unconnected pin in architecture. +Warning 148: bram[0].plr_o[17] unconnected pin in architecture. +Warning 149: bram[0].plr_o[18] unconnected pin in architecture. +Warning 150: bram[0].plr_o[19] unconnected pin in architecture. +Warning 151: bram[0].plr_o[20] unconnected pin in architecture. +Warning 152: bram[0].plr_o[21] unconnected pin in architecture. +Warning 153: bram[0].plr_o[22] unconnected pin in architecture. +Warning 154: bram[0].plr_o[23] unconnected pin in architecture. +Warning 155: bram[0].plr_o[24] unconnected pin in architecture. +Warning 156: bram[0].plr_o[25] unconnected pin in architecture. +Warning 157: bram[0].plr_o[26] unconnected pin in architecture. +Warning 158: bram[0].plr_o[27] unconnected pin in architecture. +Warning 159: bram[0].plr_o[28] unconnected pin in architecture. +Warning 160: bram[0].plr_o[29] unconnected pin in architecture. +Warning 161: bram[0].plr_o[30] unconnected pin in architecture. +Warning 162: bram[0].plr_o[31] unconnected pin in architecture. +Warning 163: bram[0].plr_o[32] unconnected pin in architecture. +Warning 164: bram[0].plr_o[33] unconnected pin in architecture. +Warning 165: bram[0].plr_o[34] unconnected pin in architecture. +Warning 166: bram[0].plr_o[35] unconnected pin in architecture. +# Building complex block graph took 0.04 seconds (max_rss 18.2 MiB, delta_rss +1.0 MiB) +Circuit file: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif +# Load circuit +Found constant-zero generator '$false' +Found constant-one generator '$true' +Found constant-zero generator '$undef' +# Load circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.5 MiB) +# Clean circuit +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 13 additional primitive pins as constant generators due to constant inputs +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 0 additional primitive pins as constant generators due to constant inputs +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 0 additional primitive pins as constant generators due to constant inputs +Swept input(s) : 0 +Swept output(s) : 0 (0 dangling, 0 constant) +Swept net(s) : 2 +Swept block(s) : 2 +Constant Pins Marked: 13 +# Clean circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +# Compress circuit +# Compress circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +# Verify circuit +# Verify circuit took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +Circuit Statistics: + Blocks: 69 + .input : 13 + .output: 24 + 0-LUT : 1 + 6-LUT : 30 + dffre : 1 + Nets : 45 + Avg Fanout: 1.3 + Max Fanout: 15.0 + Min Fanout: 1.0 + Netlist Clocks: 1 +# Build Timing Graph + Timing Graph Nodes: 104 + Timing Graph Edges: 94 + Timing Graph Levels: 6 +# Build Timing Graph took 0.00 seconds (max_rss 18.7 MiB, delta_rss +0.0 MiB) +Netlist contains 1 clocks + Netlist Clock '$clk_buf_$ibuf_CLK_IN' Fanout: 1 pins (1.0%), 1 blocks (1.4%) +# Load Timing Constraints + +SDC file '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc' contained no SDC commands +Setting default timing constraints: + * constrain all primay inputs and primary outputs on netlist clock '$clk_buf_$ibuf_CLK_IN' + * optimize netlist clock to run as fast as possible +Timing constraints created 1 clocks + Constrained Clock '$clk_buf_$ibuf_CLK_IN' Source: '$clk_buf_$ibuf_CLK_IN.inpad[0]' + +# Load Timing Constraints took 0.00 seconds (max_rss 19.0 MiB, delta_rss +0.3 MiB) +# Load packing +Begin loading packed FPGA netlist file. +Netlist generated from file '/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net'. +Detected 1 constant generators (to see names run with higher pack verbosity) +Finished loading packed FPGA netlist file (took 0.04 seconds). +# Load packing took 0.05 seconds (max_rss 57.9 MiB, delta_rss +38.7 MiB) +Warning 167: Netlist contains 0 global net to non-global architecture pin connections +Cluster level netlist and block usage statistics +Netlist num_nets: 39 +Netlist num_blocks: 39 +Netlist EMPTY blocks: 0. +Netlist io blocks: 37. +Netlist clb blocks: 2. +Netlist dsp blocks: 0. +Netlist bram blocks: 0. +Netlist inputs pins: 13 +Netlist output pins: 24 + +Pb types usage... + io : 37 + io_output : 24 + outpad : 24 + io_input : 13 + inpad : 13 + clb : 2 + clb_lr : 2 + fle : 16 + ble5 : 31 + lut5 : 31 + lut : 31 + ff : 1 + DFFRE : 1 + +# Create Device +## Build Device Grid +FPGA sized to 64 x 46: 2944 grid tiles (castor62x44_heterogeneous) + +Resource usage... + Netlist + 37 blocks of type: io + Architecture + 4320 blocks of type: io_top + 3168 blocks of type: io_right + 4320 blocks of type: io_bottom + 3168 blocks of type: io_left + Netlist + 2 blocks of type: clb + Architecture + 2184 blocks of type: clb + Netlist + 0 blocks of type: dsp + Architecture + 56 blocks of type: dsp + Netlist + 0 blocks of type: bram + Architecture + 56 blocks of type: bram + +Device Utilization: 0.00 (target 1.00) + Physical Tile io_top: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_right: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_bottom: + Block Utilization: 0.01 Logical Block: io + Physical Tile io_left: + Block Utilization: 0.01 Logical Block: io + Physical Tile clb: + Block Utilization: 0.00 Logical Block: clb + Physical Tile dsp: + Block Utilization: 0.00 Logical Block: dsp + Physical Tile bram: + Block Utilization: 0.00 Logical Block: bram + +## Build Device Grid took 0.00 seconds (max_rss 58.2 MiB, delta_rss +0.0 MiB) +Warning 168: Tileable routing resource graph does not support clock modeling yet! Related options are ignored... +## Build tileable routing resource graph +X-direction routing channel width is 160 +Y-direction routing channel width is 160 +Warning 169: Sized nonsensical R=0 transistor to minimum width +Warning 170: Sized nonsensical R=0 transistor to minimum width +Warning 171: Sized nonsensical R=0 transistor to minimum width +Warning 172: Sized nonsensical R=0 transistor to minimum width +## Build tileable routing resource graph took 13.46 seconds (max_rss 472.8 MiB, delta_rss +414.6 MiB) + RR Graph Nodes: 1365608 + RR Graph Edges: 6033268 +# Create Device took 14.07 seconds (max_rss 472.8 MiB, delta_rss +414.6 MiB) + +# Computing router lookahead map +## Computing wire lookahead +## Computing wire lookahead took 29.35 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +## Computing src/opin lookahead +Warning 173: Found no more ample locations for SOURCE in io_top +Warning 174: Found no more ample locations for OPIN in io_top +Warning 175: Found no more ample locations for SOURCE in io_right +Warning 176: Found no more ample locations for OPIN in io_right +Warning 177: Found no more ample locations for SOURCE in io_bottom +Warning 178: Found no more ample locations for OPIN in io_bottom +Warning 179: Found no more ample locations for SOURCE in io_left +Warning 180: Found no more ample locations for OPIN in io_left +Warning 181: Found no more ample locations for SOURCE in clb +Warning 182: Found no more ample locations for OPIN in clb +Warning 183: Found no more ample locations for SOURCE in dsp +Warning 184: Found no more ample locations for OPIN in dsp +Warning 185: Found no more ample locations for SOURCE in bram +Warning 186: Found no more ample locations for OPIN in bram +## Computing src/opin lookahead took 0.10 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +# Computing router lookahead map took 29.56 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +# Computing placement delta delay look-up +RR graph channel widths unchanged, skipping RR graph rebuild +## Computing delta delays +Warning 187: Unable to route between blocks at (1,1) and (1,45) to characterize delay (setting to inf) +Warning 188: Unable to route between blocks at (1,1) and (2,45) to characterize delay (setting to inf) +Warning 189: Unable to route between blocks at (1,1) and (3,45) to characterize delay (setting to inf) +Warning 190: Unable to route between blocks at (1,1) and (4,45) to characterize delay (setting to inf) +Warning 191: Unable to route between blocks at (1,1) and (5,45) to characterize delay (setting to inf) +Warning 192: Unable to route between blocks at (1,1) and (6,45) to characterize delay (setting to inf) +Warning 193: Unable to route between blocks at (1,1) and (7,45) to characterize delay (setting to inf) +Warning 194: Unable to route between blocks at (1,1) and (8,45) to characterize delay (setting to inf) +Warning 195: Unable to route between blocks at (1,1) and (9,45) to characterize delay (setting to inf) +Warning 196: Unable to route between blocks at (1,1) and (10,45) to characterize delay (setting to inf) +Warning 197: Unable to route between blocks at (1,1) and (11,45) to characterize delay (setting to inf) +Warning 198: Unable to route between blocks at (1,1) and (12,45) to characterize delay (setting to inf) +Warning 199: Unable to route between blocks at (1,1) and (13,45) to characterize delay (setting to inf) +Warning 200: Unable to route between blocks at (1,1) and (14,45) to characterize delay (setting to inf) +Warning 201: Unable to route between blocks at (1,1) and (15,45) to characterize delay (setting to inf) +Warning 202: Unable to route between blocks at (1,1) and (16,45) to characterize delay (setting to inf) +Warning 203: Unable to route between blocks at (1,1) and (17,45) to characterize delay (setting to inf) +Warning 204: Unable to route between blocks at (1,1) and (18,45) to characterize delay (setting to inf) +Warning 205: Unable to route between blocks at (1,1) and (19,45) to characterize delay (setting to inf) +Warning 206: Unable to route between blocks at (1,1) and (20,45) to characterize delay (setting to inf) +Warning 207: Unable to route between blocks at (1,1) and (21,45) to characterize delay (setting to inf) +Warning 208: Unable to route between blocks at (1,1) and (22,45) to characterize delay (setting to inf) +Warning 209: Unable to route between blocks at (1,1) and (23,45) to characterize delay (setting to inf) +Warning 210: Unable to route between blocks at (1,1) and (24,45) to characterize delay (setting to inf) +Warning 211: Unable to route between blocks at (1,1) and (25,45) to characterize delay (setting to inf) +Warning 212: Unable to route between blocks at (1,1) and (26,45) to characterize delay (setting to inf) +Warning 213: Unable to route between blocks at (1,1) and (27,45) to characterize delay (setting to inf) +Warning 214: Unable to route between blocks at (1,1) and (28,45) to characterize delay (setting to inf) +Warning 215: Unable to route between blocks at (1,1) and (29,45) to characterize delay (setting to inf) +Warning 216: Unable to route between blocks at (1,1) and (30,45) to characterize delay (setting to inf) +Warning 217: Unable to route between blocks at (1,1) and (31,45) to characterize delay (setting to inf) +Warning 218: Unable to route between blocks at (1,1) and (32,45) to characterize delay (setting to inf) +Warning 219: Unable to route between blocks at (1,1) and (33,45) to characterize delay (setting to inf) +Warning 220: Unable to route between blocks at (1,1) and (34,45) to characterize delay (setting to inf) +Warning 221: Unable to route between blocks at (1,1) and (35,45) to characterize delay (setting to inf) +Warning 222: Unable to route between blocks at (1,1) and (36,45) to characterize delay (setting to inf) +Warning 223: Unable to route between blocks at (1,1) and (37,45) to characterize delay (setting to inf) +Warning 224: Unable to route between blocks at (1,1) and (38,45) to characterize delay (setting to inf) +Warning 225: Unable to route between blocks at (1,1) and (39,45) to characterize delay (setting to inf) +Warning 226: Unable to route between blocks at (1,1) and (40,45) to characterize delay (setting to inf) +Warning 227: Unable to route between blocks at (1,1) and (41,45) to characterize delay (setting to inf) +Warning 228: Unable to route between blocks at (1,1) and (42,45) to characterize delay (setting to inf) +Warning 229: Unable to route between blocks at (1,1) and (43,45) to characterize delay (setting to inf) +Warning 230: Unable to route between blocks at (1,1) and (44,45) to characterize delay (setting to inf) +Warning 231: Unable to route between blocks at (1,1) and (45,45) to characterize delay (setting to inf) +Warning 232: Unable to route between blocks at (1,1) and (46,45) to characterize delay (setting to inf) +Warning 233: Unable to route between blocks at (1,1) and (47,45) to characterize delay (setting to inf) +Warning 234: Unable to route between blocks at (1,1) and (48,45) to characterize delay (setting to inf) +Warning 235: Unable to route between blocks at (1,1) and (49,45) to characterize delay (setting to inf) +Warning 236: Unable to route between blocks at (1,1) and (50,45) to characterize delay (setting to inf) +Warning 237: Unable to route between blocks at (1,1) and (51,45) to characterize delay (setting to inf) +Warning 238: Unable to route between blocks at (1,1) and (52,45) to characterize delay (setting to inf) +Warning 239: Unable to route between blocks at (1,1) and (53,45) to characterize delay (setting to inf) +Warning 240: Unable to route between blocks at (1,1) and (54,45) to characterize delay (setting to inf) +Warning 241: Unable to route between blocks at (1,1) and (55,45) to characterize delay (setting to inf) +Warning 242: Unable to route between blocks at (1,1) and (56,45) to characterize delay (setting to inf) +Warning 243: Unable to route between blocks at (1,1) and (57,45) to characterize delay (setting to inf) +Warning 244: Unable to route between blocks at (1,1) and (58,45) to characterize delay (setting to inf) +Warning 245: Unable to route between blocks at (1,1) and (59,45) to characterize delay (setting to inf) +Warning 246: Unable to route between blocks at (1,1) and (60,45) to characterize delay (setting to inf) +Warning 247: Unable to route between blocks at (1,1) and (61,45) to characterize delay (setting to inf) +Warning 248: Unable to route between blocks at (1,1) and (62,45) to characterize delay (setting to inf) +Warning 249: Unable to route between blocks at (1,1) and (63,1) to characterize delay (setting to inf) +Warning 250: Unable to route between blocks at (1,1) and (63,2) to characterize delay (setting to inf) +Warning 251: Unable to route between blocks at (1,1) and (63,3) to characterize delay (setting to inf) +Warning 252: Unable to route between blocks at (1,1) and (63,4) to characterize delay (setting to inf) +Warning 253: Unable to route between blocks at (1,1) and (63,5) to characterize delay (setting to inf) +Warning 254: Unable to route between blocks at (1,1) and (63,6) to characterize delay (setting to inf) +Warning 255: Unable to route between blocks at (1,1) and (63,7) to characterize delay (setting to inf) +Warning 256: Unable to route between blocks at (1,1) and (63,8) to characterize delay (setting to inf) +Warning 257: Unable to route between blocks at (1,1) and (63,9) to characterize delay (setting to inf) +Warning 258: Unable to route between blocks at (1,1) and (63,10) to characterize delay (setting to inf) +Warning 259: Unable to route between blocks at (1,1) and (63,11) to characterize delay (setting to inf) +Warning 260: Unable to route between blocks at (1,1) and (63,12) to characterize delay (setting to inf) +Warning 261: Unable to route between blocks at (1,1) and (63,13) to characterize delay (setting to inf) +Warning 262: Unable to route between blocks at (1,1) and (63,14) to characterize delay (setting to inf) +Warning 263: Unable to route between blocks at (1,1) and (63,15) to characterize delay (setting to inf) +Warning 264: Unable to route between blocks at (1,1) and (63,16) to characterize delay (setting to inf) +Warning 265: Unable to route between blocks at (1,1) and (63,17) to characterize delay (setting to inf) +Warning 266: Unable to route between blocks at (1,1) and (63,18) to characterize delay (setting to inf) +Warning 267: Unable to route between blocks at (1,1) and (63,19) to characterize delay (setting to inf) +Warning 268: Unable to route between blocks at (1,1) and (63,20) to characterize delay (setting to inf) +Warning 269: Unable to route between blocks at (1,1) and (63,21) to characterize delay (setting to inf) +Warning 270: Unable to route between blocks at (1,1) and (63,22) to characterize delay (setting to inf) +Warning 271: Unable to route between blocks at (1,1) and (63,23) to characterize delay (setting to inf) +Warning 272: Unable to route between blocks at (1,1) and (63,24) to characterize delay (setting to inf) +Warning 273: Unable to route between blocks at (1,1) and (63,25) to characterize delay (setting to inf) +Warning 274: Unable to route between blocks at (1,1) and (63,26) to characterize delay (setting to inf) +Warning 275: Unable to route between blocks at (1,1) and (63,27) to characterize delay (setting to inf) +Warning 276: Unable to route between blocks at (1,1) and (63,28) to characterize delay (setting to inf) +Warning 277: Unable to route between blocks at (1,1) and (63,29) to characterize delay (setting to inf) +Warning 278: Unable to route between blocks at (1,1) and (63,30) to characterize delay (setting to inf) +Warning 279: Unable to route between blocks at (1,1) and (63,31) to characterize delay (setting to inf) +Warning 280: Unable to route between blocks at (1,1) and (63,32) to characterize delay (setting to inf) +Warning 281: Unable to route between blocks at (1,1) and (63,33) to characterize delay (setting to inf) +Warning 282: Unable to route between blocks at (1,1) and (63,34) to characterize delay (setting to inf) +Warning 283: Unable to route between blocks at (1,1) and (63,35) to characterize delay (setting to inf) +Warning 284: Unable to route between blocks at (1,1) and (63,36) to characterize delay (setting to inf) +Warning 285: Unable to route between blocks at (1,1) and (63,37) to characterize delay (setting to inf) +Warning 286: Unable to route between blocks at (1,1) and (63,38) to characterize delay (setting to inf) +Warning 287: Unable to route between blocks at (1,1) and (63,39) to characterize delay (setting to inf) +Warning 288: Unable to route between blocks at (1,1) and (63,40) to characterize delay (setting to inf) +Warning 289: Unable to route between blocks at (1,1) and (63,41) to characterize delay (setting to inf) +Warning 290: Unable to route between blocks at (1,1) and (63,42) to characterize delay (setting to inf) +Warning 291: Unable to route between blocks at (1,1) and (63,43) to characterize delay (setting to inf) +Warning 292: Unable to route between blocks at (1,1) and (63,44) to characterize delay (setting to inf) +Warning 293: Unable to route between blocks at (1,1) and (63,45) to characterize delay (setting to inf) +Warning 294: Unable to route between blocks at (4,4) and (4,45) to characterize delay (setting to inf) +Warning 295: Unable to route between blocks at (4,4) and (5,45) to characterize delay (setting to inf) +Warning 296: Unable to route between blocks at (4,4) and (6,45) to characterize delay (setting to inf) +Warning 297: Unable to route between blocks at (4,4) and (7,45) to characterize delay (setting to inf) +Warning 298: Unable to route between blocks at (4,4) and (8,45) to characterize delay (setting to inf) +Warning 299: Unable to route between blocks at (4,4) and (9,45) to characterize delay (setting to inf) +Warning 300: Unable to route between blocks at (4,4) and (10,45) to characterize delay (setting to inf) +Warning 301: Unable to route between blocks at (4,4) and (11,45) to characterize delay (setting to inf) +Warning 302: Unable to route between blocks at (4,4) and (12,45) to characterize delay (setting to inf) +Warning 303: Unable to route between blocks at (4,4) and (13,45) to characterize delay (setting to inf) +Warning 304: Unable to route between blocks at (4,4) and (14,45) to characterize delay (setting to inf) +Warning 305: Unable to route between blocks at (4,4) and (15,45) to characterize delay (setting to inf) +Warning 306: Unable to route between blocks at (4,4) and (16,45) to characterize delay (setting to inf) +Warning 307: Unable to route between blocks at (4,4) and (17,45) to characterize delay (setting to inf) +Warning 308: Unable to route between blocks at (4,4) and (18,45) to characterize delay (setting to inf) +Warning 309: Unable to route between blocks at (4,4) and (19,45) to characterize delay (setting to inf) +Warning 310: Unable to route between blocks at (4,4) and (20,45) to characterize delay (setting to inf) +Warning 311: Unable to route between blocks at (4,4) and (21,45) to characterize delay (setting to inf) +Warning 312: Unable to route between blocks at (4,4) and (22,45) to characterize delay (setting to inf) +Warning 313: Unable to route between blocks at (4,4) and (23,45) to characterize delay (setting to inf) +Warning 314: Unable to route between blocks at (4,4) and (24,45) to characterize delay (setting to inf) +Warning 315: Unable to route between blocks at (4,4) and (25,45) to characterize delay (setting to inf) +Warning 316: Unable to route between blocks at (4,4) and (26,45) to characterize delay (setting to inf) +Warning 317: Unable to route between blocks at (4,4) and (27,45) to characterize delay (setting to inf) +Warning 318: Unable to route between blocks at (4,4) and (28,45) to characterize delay (setting to inf) +Warning 319: Unable to route between blocks at (4,4) and (29,45) to characterize delay (setting to inf) +Warning 320: Unable to route between blocks at (4,4) and (30,45) to characterize delay (setting to inf) +Warning 321: Unable to route between blocks at (4,4) and (31,45) to characterize delay (setting to inf) +Warning 322: Unable to route between blocks at (4,4) and (32,45) to characterize delay (setting to inf) +Warning 323: Unable to route between blocks at (4,4) and (33,45) to characterize delay (setting to inf) +Warning 324: Unable to route between blocks at (4,4) and (34,45) to characterize delay (setting to inf) +Warning 325: Unable to route between blocks at (4,4) and (35,45) to characterize delay (setting to inf) +Warning 326: Unable to route between blocks at (4,4) and (36,45) to characterize delay (setting to inf) +Warning 327: Unable to route between blocks at (4,4) and (37,45) to characterize delay (setting to inf) +Warning 328: Unable to route between blocks at (4,4) and (38,45) to characterize delay (setting to inf) +Warning 329: Unable to route between blocks at (4,4) and (39,45) to characterize delay (setting to inf) +Warning 330: Unable to route between blocks at (4,4) and (40,45) to characterize delay (setting to inf) +Warning 331: Unable to route between blocks at (4,4) and (41,45) to characterize delay (setting to inf) +Warning 332: Unable to route between blocks at (4,4) and (42,45) to characterize delay (setting to inf) +Warning 333: Unable to route between blocks at (4,4) and (43,45) to characterize delay (setting to inf) +Warning 334: Unable to route between blocks at (4,4) and (44,45) to characterize delay (setting to inf) +Warning 335: Unable to route between blocks at (4,4) and (45,45) to characterize delay (setting to inf) +Warning 336: Unable to route between blocks at (4,4) and (46,45) to characterize delay (setting to inf) +Warning 337: Unable to route between blocks at (4,4) and (47,45) to characterize delay (setting to inf) +Warning 338: Unable to route between blocks at (4,4) and (48,45) to characterize delay (setting to inf) +Warning 339: Unable to route between blocks at (4,4) and (49,45) to characterize delay (setting to inf) +Warning 340: Unable to route between blocks at (4,4) and (50,45) to characterize delay (setting to inf) +Warning 341: Unable to route between blocks at (4,4) and (51,45) to characterize delay (setting to inf) +Warning 342: Unable to route between blocks at (4,4) and (52,45) to characterize delay (setting to inf) +Warning 343: Unable to route between blocks at (4,4) and (53,45) to characterize delay (setting to inf) +Warning 344: Unable to route between blocks at (4,4) and (54,45) to characterize delay (setting to inf) +Warning 345: Unable to route between blocks at (4,4) and (55,45) to characterize delay (setting to inf) +Warning 346: Unable to route between blocks at (4,4) and (56,45) to characterize delay (setting to inf) +Warning 347: Unable to route between blocks at (4,4) and (57,45) to characterize delay (setting to inf) +Warning 348: Unable to route between blocks at (4,4) and (58,45) to characterize delay (setting to inf) +Warning 349: Unable to route between blocks at (4,4) and (59,45) to characterize delay (setting to inf) +Warning 350: Unable to route between blocks at (4,4) and (60,45) to characterize delay (setting to inf) +Warning 351: Unable to route between blocks at (4,4) and (61,45) to characterize delay (setting to inf) +Warning 352: Unable to route between blocks at (4,4) and (62,45) to characterize delay (setting to inf) +Warning 353: Unable to route between blocks at (4,4) and (63,4) to characterize delay (setting to inf) +Warning 354: Unable to route between blocks at (4,4) and (63,5) to characterize delay (setting to inf) +Warning 355: Unable to route between blocks at (4,4) and (63,6) to characterize delay (setting to inf) +Warning 356: Unable to route between blocks at (4,4) and (63,7) to characterize delay (setting to inf) +Warning 357: Unable to route between blocks at (4,4) and (63,8) to characterize delay (setting to inf) +Warning 358: Unable to route between blocks at (4,4) and (63,9) to characterize delay (setting to inf) +Warning 359: Unable to route between blocks at (4,4) and (63,10) to characterize delay (setting to inf) +Warning 360: Unable to route between blocks at (4,4) and (63,11) to characterize delay (setting to inf) +Warning 361: Unable to route between blocks at (4,4) and (63,12) to characterize delay (setting to inf) +Warning 362: Unable to route between blocks at (4,4) and (63,13) to characterize delay (setting to inf) +Warning 363: Unable to route between blocks at (4,4) and (63,14) to characterize delay (setting to inf) +Warning 364: Unable to route between blocks at (4,4) and (63,15) to characterize delay (setting to inf) +Warning 365: Unable to route between blocks at (4,4) and (63,16) to characterize delay (setting to inf) +Warning 366: Unable to route between blocks at (4,4) and (63,17) to characterize delay (setting to inf) +Warning 367: Unable to route between blocks at (4,4) and (63,18) to characterize delay (setting to inf) +Warning 368: Unable to route between blocks at (4,4) and (63,19) to characterize delay (setting to inf) +Warning 369: Unable to route between blocks at (4,4) and (63,20) to characterize delay (setting to inf) +Warning 370: Unable to route between blocks at (4,4) and (63,21) to characterize delay (setting to inf) +Warning 371: Unable to route between blocks at (4,4) and (63,22) to characterize delay (setting to inf) +Warning 372: Unable to route between blocks at (4,4) and (63,23) to characterize delay (setting to inf) +Warning 373: Unable to route between blocks at (4,4) and (63,24) to characterize delay (setting to inf) +Warning 374: Unable to route between blocks at (4,4) and (63,25) to characterize delay (setting to inf) +Warning 375: Unable to route between blocks at (4,4) and (63,26) to characterize delay (setting to inf) +Warning 376: Unable to route between blocks at (4,4) and (63,27) to characterize delay (setting to inf) +Warning 377: Unable to route between blocks at (4,4) and (63,28) to characterize delay (setting to inf) +Warning 378: Unable to route between blocks at (4,4) and (63,29) to characterize delay (setting to inf) +Warning 379: Unable to route between blocks at (4,4) and (63,30) to characterize delay (setting to inf) +Warning 380: Unable to route between blocks at (4,4) and (63,31) to characterize delay (setting to inf) +Warning 381: Unable to route between blocks at (4,4) and (63,32) to characterize delay (setting to inf) +Warning 382: Unable to route between blocks at (4,4) and (63,33) to characterize delay (setting to inf) +Warning 383: Unable to route between blocks at (4,4) and (63,34) to characterize delay (setting to inf) +Warning 384: Unable to route between blocks at (4,4) and (63,35) to characterize delay (setting to inf) +Warning 385: Unable to route between blocks at (4,4) and (63,36) to characterize delay (setting to inf) +Warning 386: Unable to route between blocks at (4,4) and (63,37) to characterize delay (setting to inf) +Warning 387: Unable to route between blocks at (4,4) and (63,38) to characterize delay (setting to inf) +Warning 388: Unable to route between blocks at (4,4) and (63,39) to characterize delay (setting to inf) +Warning 389: Unable to route between blocks at (4,4) and (63,40) to characterize delay (setting to inf) +Warning 390: Unable to route between blocks at (4,4) and (63,41) to characterize delay (setting to inf) +Warning 391: Unable to route between blocks at (4,4) and (63,42) to characterize delay (setting to inf) +Warning 392: Unable to route between blocks at (4,4) and (63,43) to characterize delay (setting to inf) +Warning 393: Unable to route between blocks at (4,4) and (63,44) to characterize delay (setting to inf) +Warning 394: Unable to route between blocks at (4,4) and (63,45) to characterize delay (setting to inf) +Warning 395: Unable to route between blocks at (60,42) and (0,0) to characterize delay (setting to inf) +Warning 396: Unable to route between blocks at (60,42) and (0,1) to characterize delay (setting to inf) +Warning 397: Unable to route between blocks at (60,42) and (0,2) to characterize delay (setting to inf) +Warning 398: Unable to route between blocks at (60,42) and (0,3) to characterize delay (setting to inf) +Warning 399: Unable to route between blocks at (60,42) and (0,4) to characterize delay (setting to inf) +Warning 400: Unable to route between blocks at (60,42) and (0,5) to characterize delay (setting to inf) +Warning 401: Unable to route between blocks at (60,42) and (0,6) to characterize delay (setting to inf) +Warning 402: Unable to route between blocks at (60,42) and (0,7) to characterize delay (setting to inf) +Warning 403: Unable to route between blocks at (60,42) and (0,8) to characterize delay (setting to inf) +Warning 404: Unable to route between blocks at (60,42) and (0,9) to characterize delay (setting to inf) +Warning 405: Unable to route between blocks at (60,42) and (0,10) to characterize delay (setting to inf) +Warning 406: Unable to route between blocks at (60,42) and (0,11) to characterize delay (setting to inf) +Warning 407: Unable to route between blocks at (60,42) and (0,12) to characterize delay (setting to inf) +Warning 408: Unable to route between blocks at (60,42) and (0,13) to characterize delay (setting to inf) +Warning 409: Unable to route between blocks at (60,42) and (0,14) to characterize delay (setting to inf) +Warning 410: Unable to route between blocks at (60,42) and (0,15) to characterize delay (setting to inf) +Warning 411: Unable to route between blocks at (60,42) and (0,16) to characterize delay (setting to inf) +Warning 412: Unable to route between blocks at (60,42) and (0,17) to characterize delay (setting to inf) +Warning 413: Unable to route between blocks at (60,42) and (0,18) to characterize delay (setting to inf) +Warning 414: Unable to route between blocks at (60,42) and (0,19) to characterize delay (setting to inf) +Warning 415: Unable to route between blocks at (60,42) and (0,20) to characterize delay (setting to inf) +Warning 416: Unable to route between blocks at (60,42) and (0,21) to characterize delay (setting to inf) +Warning 417: Unable to route between blocks at (60,42) and (0,22) to characterize delay (setting to inf) +Warning 418: Unable to route between blocks at (60,42) and (0,23) to characterize delay (setting to inf) +Warning 419: Unable to route between blocks at (60,42) and (0,24) to characterize delay (setting to inf) +Warning 420: Unable to route between blocks at (60,42) and (0,25) to characterize delay (setting to inf) +Warning 421: Unable to route between blocks at (60,42) and (0,26) to characterize delay (setting to inf) +Warning 422: Unable to route between blocks at (60,42) and (0,27) to characterize delay (setting to inf) +Warning 423: Unable to route between blocks at (60,42) and (0,28) to characterize delay (setting to inf) +Warning 424: Unable to route between blocks at (60,42) and (0,29) to characterize delay (setting to inf) +Warning 425: Unable to route between blocks at (60,42) and (0,30) to characterize delay (setting to inf) +Warning 426: Unable to route between blocks at (60,42) and (0,31) to characterize delay (setting to inf) +Warning 427: Unable to route between blocks at (60,42) and (0,32) to characterize delay (setting to inf) +Warning 428: Unable to route between blocks at (60,42) and (0,33) to characterize delay (setting to inf) +Warning 429: Unable to route between blocks at (60,42) and (0,34) to characterize delay (setting to inf) +Warning 430: Unable to route between blocks at (60,42) and (0,35) to characterize delay (setting to inf) +Warning 431: Unable to route between blocks at (60,42) and (0,36) to characterize delay (setting to inf) +Warning 432: Unable to route between blocks at (60,42) and (0,37) to characterize delay (setting to inf) +Warning 433: Unable to route between blocks at (60,42) and (0,38) to characterize delay (setting to inf) +Warning 434: Unable to route between blocks at (60,42) and (0,39) to characterize delay (setting to inf) +Warning 435: Unable to route between blocks at (60,42) and (0,40) to characterize delay (setting to inf) +Warning 436: Unable to route between blocks at (60,42) and (0,41) to characterize delay (setting to inf) +Warning 437: Unable to route between blocks at (60,42) and (0,42) to characterize delay (setting to inf) +Warning 438: Unable to route between blocks at (60,42) and (1,0) to characterize delay (setting to inf) +Warning 439: Unable to route between blocks at (60,42) and (2,0) to characterize delay (setting to inf) +Warning 440: Unable to route between blocks at (60,42) and (3,0) to characterize delay (setting to inf) +Warning 441: Unable to route between blocks at (60,42) and (4,0) to characterize delay (setting to inf) +Warning 442: Unable to route between blocks at (60,42) and (5,0) to characterize delay (setting to inf) +Warning 443: Unable to route between blocks at (60,42) and (6,0) to characterize delay (setting to inf) +Warning 444: Unable to route between blocks at (60,42) and (7,0) to characterize delay (setting to inf) +Warning 445: Unable to route between blocks at (60,42) and (8,0) to characterize delay (setting to inf) +Warning 446: Unable to route between blocks at (60,42) and (9,0) to characterize delay (setting to inf) +Warning 447: Unable to route between blocks at (60,42) and (10,0) to characterize delay (setting to inf) +Warning 448: Unable to route between blocks at (60,42) and (11,0) to characterize delay (setting to inf) +Warning 449: Unable to route between blocks at (60,42) and (12,0) to characterize delay (setting to inf) +Warning 450: Unable to route between blocks at (60,42) and (13,0) to characterize delay (setting to inf) +Warning 451: Unable to route between blocks at (60,42) and (14,0) to characterize delay (setting to inf) +Warning 452: Unable to route between blocks at (60,42) and (15,0) to characterize delay (setting to inf) +Warning 453: Unable to route between blocks at (60,42) and (16,0) to characterize delay (setting to inf) +Warning 454: Unable to route between blocks at (60,42) and (17,0) to characterize delay (setting to inf) +Warning 455: Unable to route between blocks at (60,42) and (18,0) to characterize delay (setting to inf) +Warning 456: Unable to route between blocks at (60,42) and (19,0) to characterize delay (setting to inf) +Warning 457: Unable to route between blocks at (60,42) and (20,0) to characterize delay (setting to inf) +Warning 458: Unable to route between blocks at (60,42) and (21,0) to characterize delay (setting to inf) +Warning 459: Unable to route between blocks at (60,42) and (22,0) to characterize delay (setting to inf) +Warning 460: Unable to route between blocks at (60,42) and (23,0) to characterize delay (setting to inf) +Warning 461: Unable to route between blocks at (60,42) and (24,0) to characterize delay (setting to inf) +Warning 462: Unable to route between blocks at (60,42) and (25,0) to characterize delay (setting to inf) +Warning 463: Unable to route between blocks at (60,42) and (26,0) to characterize delay (setting to inf) +Warning 464: Unable to route between blocks at (60,42) and (27,0) to characterize delay (setting to inf) +Warning 465: Unable to route between blocks at (60,42) and (28,0) to characterize delay (setting to inf) +Warning 466: Unable to route between blocks at (60,42) and (29,0) to characterize delay (setting to inf) +Warning 467: Unable to route between blocks at (60,42) and (30,0) to characterize delay (setting to inf) +Warning 468: Unable to route between blocks at (60,42) and (31,0) to characterize delay (setting to inf) +Warning 469: Unable to route between blocks at (60,42) and (32,0) to characterize delay (setting to inf) +Warning 470: Unable to route between blocks at (60,42) and (33,0) to characterize delay (setting to inf) +Warning 471: Unable to route between blocks at (60,42) and (34,0) to characterize delay (setting to inf) +Warning 472: Unable to route between blocks at (60,42) and (35,0) to characterize delay (setting to inf) +Warning 473: Unable to route between blocks at (60,42) and (36,0) to characterize delay (setting to inf) +Warning 474: Unable to route between blocks at (60,42) and (37,0) to characterize delay (setting to inf) +Warning 475: Unable to route between blocks at (60,42) and (38,0) to characterize delay (setting to inf) +Warning 476: Unable to route between blocks at (60,42) and (39,0) to characterize delay (setting to inf) +Warning 477: Unable to route between blocks at (60,42) and (40,0) to characterize delay (setting to inf) +Warning 478: Unable to route between blocks at (60,42) and (41,0) to characterize delay (setting to inf) +Warning 479: Unable to route between blocks at (60,42) and (42,0) to characterize delay (setting to inf) +Warning 480: Unable to route between blocks at (60,42) and (43,0) to characterize delay (setting to inf) +Warning 481: Unable to route between blocks at (60,42) and (44,0) to characterize delay (setting to inf) +Warning 482: Unable to route between blocks at (60,42) and (45,0) to characterize delay (setting to inf) +Warning 483: Unable to route between blocks at (60,42) and (46,0) to characterize delay (setting to inf) +Warning 484: Unable to route between blocks at (60,42) and (47,0) to characterize delay (setting to inf) +Warning 485: Unable to route between blocks at (60,42) and (48,0) to characterize delay (setting to inf) +Warning 486: Unable to route between blocks at (60,42) and (49,0) to characterize delay (setting to inf) +Warning 487: Unable to route between blocks at (60,42) and (50,0) to characterize delay (setting to inf) +Warning 488: Unable to route between blocks at (60,42) and (51,0) to characterize delay (setting to inf) +Warning 489: Unable to route between blocks at (60,42) and (52,0) to characterize delay (setting to inf) +Warning 490: Unable to route between blocks at (60,42) and (53,0) to characterize delay (setting to inf) +Warning 491: Unable to route between blocks at (60,42) and (54,0) to characterize delay (setting to inf) +Warning 492: Unable to route between blocks at (60,42) and (55,0) to characterize delay (setting to inf) +Warning 493: Unable to route between blocks at (60,42) and (56,0) to characterize delay (setting to inf) +Warning 494: Unable to route between blocks at (60,42) and (57,0) to characterize delay (setting to inf) +Warning 495: Unable to route between blocks at (60,42) and (58,0) to characterize delay (setting to inf) +Warning 496: Unable to route between blocks at (60,42) and (59,0) to characterize delay (setting to inf) +Warning 497: Unable to route between blocks at (60,42) and (60,0) to characterize delay (setting to inf) +Warning 498: Unable to route between blocks at (60,4) and (0,4) to characterize delay (setting to inf) +Warning 499: Unable to route between blocks at (60,4) and (0,5) to characterize delay (setting to inf) +Warning 500: Unable to route between blocks at (60,4) and (0,6) to characterize delay (setting to inf) +Warning 501: Unable to route between blocks at (60,4) and (0,7) to characterize delay (setting to inf) +Warning 502: Unable to route between blocks at (60,4) and (0,8) to characterize delay (setting to inf) +Warning 503: Unable to route between blocks at (60,4) and (0,9) to characterize delay (setting to inf) +Warning 504: Unable to route between blocks at (60,4) and (0,10) to characterize delay (setting to inf) +Warning 505: Unable to route between blocks at (60,4) and (0,11) to characterize delay (setting to inf) +Warning 506: Unable to route between blocks at (60,4) and (0,12) to characterize delay (setting to inf) +Warning 507: Unable to route between blocks at (60,4) and (0,13) to characterize delay (setting to inf) +Warning 508: Unable to route between blocks at (60,4) and (0,14) to characterize delay (setting to inf) +Warning 509: Unable to route between blocks at (60,4) and (0,15) to characterize delay (setting to inf) +Warning 510: Unable to route between blocks at (60,4) and (0,16) to characterize delay (setting to inf) +Warning 511: Unable to route between blocks at (60,4) and (0,17) to characterize delay (setting to inf) +Warning 512: Unable to route between blocks at (60,4) and (0,18) to characterize delay (setting to inf) +Warning 513: Unable to route between blocks at (60,4) and (0,19) to characterize delay (setting to inf) +Warning 514: Unable to route between blocks at (60,4) and (0,20) to characterize delay (setting to inf) +Warning 515: Unable to route between blocks at (60,4) and (0,21) to characterize delay (setting to inf) +Warning 516: Unable to route between blocks at (60,4) and (0,22) to characterize delay (setting to inf) +Warning 517: Unable to route between blocks at (60,4) and (0,23) to characterize delay (setting to inf) +Warning 518: Unable to route between blocks at (60,4) and (0,24) to characterize delay (setting to inf) +Warning 519: Unable to route between blocks at (60,4) and (0,25) to characterize delay (setting to inf) +Warning 520: Unable to route between blocks at (60,4) and (0,26) to characterize delay (setting to inf) +Warning 521: Unable to route between blocks at (60,4) and (0,27) to characterize delay (setting to inf) +Warning 522: Unable to route between blocks at (60,4) and (0,28) to characterize delay (setting to inf) +Warning 523: Unable to route between blocks at (60,4) and (0,29) to characterize delay (setting to inf) +Warning 524: Unable to route between blocks at (60,4) and (0,30) to characterize delay (setting to inf) +Warning 525: Unable to route between blocks at (60,4) and (0,31) to characterize delay (setting to inf) +Warning 526: Unable to route between blocks at (60,4) and (0,32) to characterize delay (setting to inf) +Warning 527: Unable to route between blocks at (60,4) and (0,33) to characterize delay (setting to inf) +Warning 528: Unable to route between blocks at (60,4) and (0,34) to characterize delay (setting to inf) +Warning 529: Unable to route between blocks at (60,4) and (0,35) to characterize delay (setting to inf) +Warning 530: Unable to route between blocks at (60,4) and (0,36) to characterize delay (setting to inf) +Warning 531: Unable to route between blocks at (60,4) and (0,37) to characterize delay (setting to inf) +Warning 532: Unable to route between blocks at (60,4) and (0,38) to characterize delay (setting to inf) +Warning 533: Unable to route between blocks at (60,4) and (0,39) to characterize delay (setting to inf) +Warning 534: Unable to route between blocks at (60,4) and (0,40) to characterize delay (setting to inf) +Warning 535: Unable to route between blocks at (60,4) and (0,41) to characterize delay (setting to inf) +Warning 536: Unable to route between blocks at (60,4) and (0,42) to characterize delay (setting to inf) +Warning 537: Unable to route between blocks at (60,4) and (0,43) to characterize delay (setting to inf) +Warning 538: Unable to route between blocks at (60,4) and (0,44) to characterize delay (setting to inf) +Warning 539: Unable to route between blocks at (60,4) and (0,45) to characterize delay (setting to inf) +Warning 540: Unable to route between blocks at (60,4) and (1,45) to characterize delay (setting to inf) +Warning 541: Unable to route between blocks at (60,4) and (2,45) to characterize delay (setting to inf) +Warning 542: Unable to route between blocks at (60,4) and (3,45) to characterize delay (setting to inf) +Warning 543: Unable to route between blocks at (60,4) and (4,45) to characterize delay (setting to inf) +Warning 544: Unable to route between blocks at (60,4) and (5,45) to characterize delay (setting to inf) +Warning 545: Unable to route between blocks at (60,4) and (6,45) to characterize delay (setting to inf) +Warning 546: Unable to route between blocks at (60,4) and (7,45) to characterize delay (setting to inf) +Warning 547: Unable to route between blocks at (60,4) and (8,45) to characterize delay (setting to inf) +Warning 548: Unable to route between blocks at (60,4) and (9,45) to characterize delay (setting to inf) +Warning 549: Unable to route between blocks at (60,4) and (10,45) to characterize delay (setting to inf) +Warning 550: Unable to route between blocks at (60,4) and (11,45) to characterize delay (setting to inf) +Warning 551: Unable to route between blocks at (60,4) and (12,45) to characterize delay (setting to inf) +Warning 552: Unable to route between blocks at (60,4) and (13,45) to characterize delay (setting to inf) +Warning 553: Unable to route between blocks at (60,4) and (14,45) to characterize delay (setting to inf) +Warning 554: Unable to route between blocks at (60,4) and (15,45) to characterize delay (setting to inf) +Warning 555: Unable to route between blocks at (60,4) and (16,45) to characterize delay (setting to inf) +Warning 556: Unable to route between blocks at (60,4) and (17,45) to characterize delay (setting to inf) +Warning 557: Unable to route between blocks at (60,4) and (18,45) to characterize delay (setting to inf) +Warning 558: Unable to route between blocks at (60,4) and (19,45) to characterize delay (setting to inf) +Warning 559: Unable to route between blocks at (60,4) and (20,45) to characterize delay (setting to inf) +Warning 560: Unable to route between blocks at (60,4) and (21,45) to characterize delay (setting to inf) +Warning 561: Unable to route between blocks at (60,4) and (22,45) to characterize delay (setting to inf) +Warning 562: Unable to route between blocks at (60,4) and (23,45) to characterize delay (setting to inf) +Warning 563: Unable to route between blocks at (60,4) and (24,45) to characterize delay (setting to inf) +Warning 564: Unable to route between blocks at (60,4) and (25,45) to characterize delay (setting to inf) +Warning 565: Unable to route between blocks at (60,4) and (26,45) to characterize delay (setting to inf) +Warning 566: Unable to route between blocks at (60,4) and (27,45) to characterize delay (setting to inf) +Warning 567: Unable to route between blocks at (60,4) and (28,45) to characterize delay (setting to inf) +Warning 568: Unable to route between blocks at (60,4) and (29,45) to characterize delay (setting to inf) +Warning 569: Unable to route between blocks at (60,4) and (30,45) to characterize delay (setting to inf) +Warning 570: Unable to route between blocks at (60,4) and (31,45) to characterize delay (setting to inf) +Warning 571: Unable to route between blocks at (60,4) and (32,45) to characterize delay (setting to inf) +Warning 572: Unable to route between blocks at (60,4) and (33,45) to characterize delay (setting to inf) +Warning 573: Unable to route between blocks at (60,4) and (34,45) to characterize delay (setting to inf) +Warning 574: Unable to route between blocks at (60,4) and (35,45) to characterize delay (setting to inf) +Warning 575: Unable to route between blocks at (60,4) and (36,45) to characterize delay (setting to inf) +Warning 576: Unable to route between blocks at (60,4) and (37,45) to characterize delay (setting to inf) +Warning 577: Unable to route between blocks at (60,4) and (38,45) to characterize delay (setting to inf) +Warning 578: Unable to route between blocks at (60,4) and (39,45) to characterize delay (setting to inf) +Warning 579: Unable to route between blocks at (60,4) and (40,45) to characterize delay (setting to inf) +Warning 580: Unable to route between blocks at (60,4) and (41,45) to characterize delay (setting to inf) +Warning 581: Unable to route between blocks at (60,4) and (42,45) to characterize delay (setting to inf) +Warning 582: Unable to route between blocks at (60,4) and (43,45) to characterize delay (setting to inf) +Warning 583: Unable to route between blocks at (60,4) and (44,45) to characterize delay (setting to inf) +Warning 584: Unable to route between blocks at (60,4) and (45,45) to characterize delay (setting to inf) +Warning 585: Unable to route between blocks at (60,4) and (46,45) to characterize delay (setting to inf) +Warning 586: Unable to route between blocks at (60,4) and (47,45) to characterize delay (setting to inf) +Warning 587: Unable to route between blocks at (60,4) and (48,45) to characterize delay (setting to inf) +Warning 588: Unable to route between blocks at (60,4) and (49,45) to characterize delay (setting to inf) +Warning 589: Unable to route between blocks at (60,4) and (50,45) to characterize delay (setting to inf) +Warning 590: Unable to route between blocks at (60,4) and (51,45) to characterize delay (setting to inf) +Warning 591: Unable to route between blocks at (60,4) and (52,45) to characterize delay (setting to inf) +Warning 592: Unable to route between blocks at (60,4) and (53,45) to characterize delay (setting to inf) +Warning 593: Unable to route between blocks at (60,4) and (54,45) to characterize delay (setting to inf) +Warning 594: Unable to route between blocks at (60,4) and (55,45) to characterize delay (setting to inf) +Warning 595: Unable to route between blocks at (60,4) and (56,45) to characterize delay (setting to inf) +Warning 596: Unable to route between blocks at (60,4) and (57,45) to characterize delay (setting to inf) +Warning 597: Unable to route between blocks at (60,4) and (58,45) to characterize delay (setting to inf) +Warning 598: Unable to route between blocks at (60,4) and (59,45) to characterize delay (setting to inf) +Warning 599: Unable to route between blocks at (60,4) and (60,45) to characterize delay (setting to inf) +Warning 600: Unable to route between blocks at (4,42) and (4,0) to characterize delay (setting to inf) +Warning 601: Unable to route between blocks at (4,42) and (5,0) to characterize delay (setting to inf) +Warning 602: Unable to route between blocks at (4,42) and (6,0) to characterize delay (setting to inf) +Warning 603: Unable to route between blocks at (4,42) and (7,0) to characterize delay (setting to inf) +Warning 604: Unable to route between blocks at (4,42) and (8,0) to characterize delay (setting to inf) +Warning 605: Unable to route between blocks at (4,42) and (9,0) to characterize delay (setting to inf) +Warning 606: Unable to route between blocks at (4,42) and (10,0) to characterize delay (setting to inf) +Warning 607: Unable to route between blocks at (4,42) and (11,0) to characterize delay (setting to inf) +Warning 608: Unable to route between blocks at (4,42) and (12,0) to characterize delay (setting to inf) +Warning 609: Unable to route between blocks at (4,42) and (13,0) to characterize delay (setting to inf) +Warning 610: Unable to route between blocks at (4,42) and (14,0) to characterize delay (setting to inf) +Warning 611: Unable to route between blocks at (4,42) and (15,0) to characterize delay (setting to inf) +Warning 612: Unable to route between blocks at (4,42) and (16,0) to characterize delay (setting to inf) +Warning 613: Unable to route between blocks at (4,42) and (17,0) to characterize delay (setting to inf) +Warning 614: Unable to route between blocks at (4,42) and (18,0) to characterize delay (setting to inf) +Warning 615: Unable to route between blocks at (4,42) and (19,0) to characterize delay (setting to inf) +Warning 616: Unable to route between blocks at (4,42) and (20,0) to characterize delay (setting to inf) +Warning 617: Unable to route between blocks at (4,42) and (21,0) to characterize delay (setting to inf) +Warning 618: Unable to route between blocks at (4,42) and (22,0) to characterize delay (setting to inf) +Warning 619: Unable to route between blocks at (4,42) and (23,0) to characterize delay (setting to inf) +Warning 620: Unable to route between blocks at (4,42) and (24,0) to characterize delay (setting to inf) +Warning 621: Unable to route between blocks at (4,42) and (25,0) to characterize delay (setting to inf) +Warning 622: Unable to route between blocks at (4,42) and (26,0) to characterize delay (setting to inf) +Warning 623: Unable to route between blocks at (4,42) and (27,0) to characterize delay (setting to inf) +Warning 624: Unable to route between blocks at (4,42) and (28,0) to characterize delay (setting to inf) +Warning 625: Unable to route between blocks at (4,42) and (29,0) to characterize delay (setting to inf) +Warning 626: Unable to route between blocks at (4,42) and (30,0) to characterize delay (setting to inf) +Warning 627: Unable to route between blocks at (4,42) and (31,0) to characterize delay (setting to inf) +Warning 628: Unable to route between blocks at (4,42) and (32,0) to characterize delay (setting to inf) +Warning 629: Unable to route between blocks at (4,42) and (33,0) to characterize delay (setting to inf) +Warning 630: Unable to route between blocks at (4,42) and (34,0) to characterize delay (setting to inf) +Warning 631: Unable to route between blocks at (4,42) and (35,0) to characterize delay (setting to inf) +Warning 632: Unable to route between blocks at (4,42) and (36,0) to characterize delay (setting to inf) +Warning 633: Unable to route between blocks at (4,42) and (37,0) to characterize delay (setting to inf) +Warning 634: Unable to route between blocks at (4,42) and (38,0) to characterize delay (setting to inf) +Warning 635: Unable to route between blocks at (4,42) and (39,0) to characterize delay (setting to inf) +Warning 636: Unable to route between blocks at (4,42) and (40,0) to characterize delay (setting to inf) +Warning 637: Unable to route between blocks at (4,42) and (41,0) to characterize delay (setting to inf) +Warning 638: Unable to route between blocks at (4,42) and (42,0) to characterize delay (setting to inf) +Warning 639: Unable to route between blocks at (4,42) and (43,0) to characterize delay (setting to inf) +Warning 640: Unable to route between blocks at (4,42) and (44,0) to characterize delay (setting to inf) +Warning 641: Unable to route between blocks at (4,42) and (45,0) to characterize delay (setting to inf) +Warning 642: Unable to route between blocks at (4,42) and (46,0) to characterize delay (setting to inf) +Warning 643: Unable to route between blocks at (4,42) and (47,0) to characterize delay (setting to inf) +Warning 644: Unable to route between blocks at (4,42) and (48,0) to characterize delay (setting to inf) +Warning 645: Unable to route between blocks at (4,42) and (49,0) to characterize delay (setting to inf) +Warning 646: Unable to route between blocks at (4,42) and (50,0) to characterize delay (setting to inf) +Warning 647: Unable to route between blocks at (4,42) and (51,0) to characterize delay (setting to inf) +Warning 648: Unable to route between blocks at (4,42) and (52,0) to characterize delay (setting to inf) +Warning 649: Unable to route between blocks at (4,42) and (53,0) to characterize delay (setting to inf) +Warning 650: Unable to route between blocks at (4,42) and (54,0) to characterize delay (setting to inf) +Warning 651: Unable to route between blocks at (4,42) and (55,0) to characterize delay (setting to inf) +Warning 652: Unable to route between blocks at (4,42) and (56,0) to characterize delay (setting to inf) +Warning 653: Unable to route between blocks at (4,42) and (57,0) to characterize delay (setting to inf) +Warning 654: Unable to route between blocks at (4,42) and (58,0) to characterize delay (setting to inf) +Warning 655: Unable to route between blocks at (4,42) and (59,0) to characterize delay (setting to inf) +Warning 656: Unable to route between blocks at (4,42) and (60,0) to characterize delay (setting to inf) +Warning 657: Unable to route between blocks at (4,42) and (61,0) to characterize delay (setting to inf) +Warning 658: Unable to route between blocks at (4,42) and (62,0) to characterize delay (setting to inf) +Warning 659: Unable to route between blocks at (4,42) and (63,0) to characterize delay (setting to inf) +Warning 660: Unable to route between blocks at (4,42) and (63,1) to characterize delay (setting to inf) +Warning 661: Unable to route between blocks at (4,42) and (63,2) to characterize delay (setting to inf) +Warning 662: Unable to route between blocks at (4,42) and (63,3) to characterize delay (setting to inf) +Warning 663: Unable to route between blocks at (4,42) and (63,4) to characterize delay (setting to inf) +Warning 664: Unable to route between blocks at (4,42) and (63,5) to characterize delay (setting to inf) +Warning 665: Unable to route between blocks at (4,42) and (63,6) to characterize delay (setting to inf) +Warning 666: Unable to route between blocks at (4,42) and (63,7) to characterize delay (setting to inf) +Warning 667: Unable to route between blocks at (4,42) and (63,8) to characterize delay (setting to inf) +Warning 668: Unable to route between blocks at (4,42) and (63,9) to characterize delay (setting to inf) +Warning 669: Unable to route between blocks at (4,42) and (63,10) to characterize delay (setting to inf) +Warning 670: Unable to route between blocks at (4,42) and (63,11) to characterize delay (setting to inf) +Warning 671: Unable to route between blocks at (4,42) and (63,12) to characterize delay (setting to inf) +Warning 672: Unable to route between blocks at (4,42) and (63,13) to characterize delay (setting to inf) +Warning 673: Unable to route between blocks at (4,42) and (63,14) to characterize delay (setting to inf) +Warning 674: Unable to route between blocks at (4,42) and (63,15) to characterize delay (setting to inf) +Warning 675: Unable to route between blocks at (4,42) and (63,16) to characterize delay (setting to inf) +Warning 676: Unable to route between blocks at (4,42) and (63,17) to characterize delay (setting to inf) +Warning 677: Unable to route between blocks at (4,42) and (63,18) to characterize delay (setting to inf) +Warning 678: Unable to route between blocks at (4,42) and (63,19) to characterize delay (setting to inf) +Warning 679: Unable to route between blocks at (4,42) and (63,20) to characterize delay (setting to inf) +Warning 680: Unable to route between blocks at (4,42) and (63,21) to characterize delay (setting to inf) +Warning 681: Unable to route between blocks at (4,42) and (63,22) to characterize delay (setting to inf) +Warning 682: Unable to route between blocks at (4,42) and (63,23) to characterize delay (setting to inf) +Warning 683: Unable to route between blocks at (4,42) and (63,24) to characterize delay (setting to inf) +Warning 684: Unable to route between blocks at (4,42) and (63,25) to characterize delay (setting to inf) +Warning 685: Unable to route between blocks at (4,42) and (63,26) to characterize delay (setting to inf) +Warning 686: Unable to route between blocks at (4,42) and (63,27) to characterize delay (setting to inf) +Warning 687: Unable to route between blocks at (4,42) and (63,28) to characterize delay (setting to inf) +Warning 688: Unable to route between blocks at (4,42) and (63,29) to characterize delay (setting to inf) +Warning 689: Unable to route between blocks at (4,42) and (63,30) to characterize delay (setting to inf) +Warning 690: Unable to route between blocks at (4,42) and (63,31) to characterize delay (setting to inf) +Warning 691: Unable to route between blocks at (4,42) and (63,32) to characterize delay (setting to inf) +Warning 692: Unable to route between blocks at (4,42) and (63,33) to characterize delay (setting to inf) +Warning 693: Unable to route between blocks at (4,42) and (63,34) to characterize delay (setting to inf) +Warning 694: Unable to route between blocks at (4,42) and (63,35) to characterize delay (setting to inf) +Warning 695: Unable to Error 1: +Type: Placement +File: /nfs_eda_sw/softwares/Raptor/orgnl/Raptor/Backend/OpenFPGA/vtr-verilog-to-routing/vpr/src/base/read_place.cpp +Line: 294 +Message: The location of cluster $obuf_O (#38) is specified 2 times in the constraints file with conflicting locations. +Its location was last specified with block $obuf_O. + +route between blocks at (4,42) and (63,36) to characterize delay (setting to inf) +Warning 696: Unable to route between blocks at (4,42) and (63,37) to characterize delay (setting to inf) +Warning 697: Unable to route between blocks at (4,42) and (63,38) to characterize delay (setting to inf) +Warning 698: Unable to route between blocks at (4,42) and (63,39) to characterize delay (setting to inf) +Warning 699: Unable to route between blocks at (4,42) and (63,40) to characterize delay (setting to inf) +Warning 700: Unable to route between blocks at (4,42) and (63,41) to characterize delay (setting to inf) +Warning 701: Unable to route between blocks at (4,42) and (63,42) to characterize delay (setting to inf) +## Computing delta delays took 39.55 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +# Computing placement delta delay look-up took 39.58 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) + +Bounding box mode is Cube + +# Placement +## Initial Placement +Reading I_DELAY_primitive_inst_pin_loc.place. + +## Initial Placement took 0.00 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +# Placement took 0.00 seconds (max_rss 472.8 MiB, delta_rss +0.0 MiB) +The entire flow of VPR took 83.72 seconds (max_rss 472.8 MiB) +ERROR: PLC: Design I_DELAY_primitive_inst placement failed +Design I_DELAY_primitive_inst placement failed + while executing +"place" + (file "raptor.tcl" line 12) diff --git a/EDA-3249/raptor.tcl b/EDA-3249/raptor.tcl new file mode 100644 index 00000000..9f102643 --- /dev/null +++ b/EDA-3249/raptor.tcl @@ -0,0 +1,15 @@ +create_design I_DELAY_primitive_inst +target_device 1VG28 +add_include_path ./rtl +add_library_path ./rtl +add_library_ext .v .sv +add_design_file ./rtl/I_DELAY_primitive_inst.v +set_top_module I_DELAY_primitive_inst +analyze +synthesize delay +packing +place +route +sta +power +bitstream diff --git a/EDA-3249/raptor_cmd.tcl b/EDA-3249/raptor_cmd.tcl new file mode 100644 index 00000000..7bebed99 --- /dev/null +++ b/EDA-3249/raptor_cmd.tcl @@ -0,0 +1,23 @@ +# /******************************************************************************* +# Copyright (c) 2022-2024 Rapid Silicon +# This source code contains proprietary information belonging to Rapid Silicon +# (the "licensor") released under license and non-disclosure agreement to the +# recipient (the "licensee"). +# The information shared and protected by the license and non-disclosure agreement +# includes but is not limited to the following: +# * operational algorithms of the product +# * logos, graphics, source code, and visual presentation of the product +# * confidential operational information of the licensor +# The recipient of this source code is NOT permitted to publicly disclose, +# re-use, archive beyond the period of the license agreement, transfer to a +# sub-licensee, or re-implement any portion of the content covered by the license +# and non-disclosure agreement without the prior written consent of the licensor. +# *********************************************************************************/ +# Version : 2024.09 +# Build : 1.2.3 +# Hash : 89d4d1b +# Date : Sep 19 2024 +# Type : Engineering +# Log Time : Thu Sep 19 08:34:59 2024 GMT +source /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/init/flow.tcl +source /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/init/sim_helpers.tcl diff --git a/EDA-3249/raptor_perf.log b/EDA-3249/raptor_perf.log new file mode 100644 index 00000000..b24543a8 --- /dev/null +++ b/EDA-3249/raptor_perf.log @@ -0,0 +1,39 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.09 +Build : 1.2.3 +Hash : 89d4d1b +Date : Sep 19 2024 +Type : Engineering +Log Time : Thu Sep 19 08:34:59 2024 GMT + +[ 13:35:00 ] Analysis has started +[ 13:35:00 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/yosys -s /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/analysis/I_DELAY_primitive_inst_analyzer.cmd +[ 13:35:00 ] Duration: 80 ms. Max utilization: 43 MB +[ 13:35:00 ] Synthesize has started +[ 13:35:00 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/yosys -s I_DELAY_primitive_inst.ys -l I_DELAY_primitive_inst_synth.log +[ 13:35:12 ] Duration: 12792 ms. Max utilization: 62 MB +[ 13:35:13 ] Packing has started +[ 13:35:13 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/vpr /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --sdc_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc --route_chan_width 160 --suppress_warnings check_rr_node_warnings.log,check_rr_node --clock_modeling ideal --absorb_buffer_luts off --skip_sync_clustering_and_routing_results off --constant_net_method route --post_place_timing_report I_DELAY_primitive_inst_post_place_timing.rpt --device castor62x44_heterogeneous --allow_unrelated_clustering on --allow_dangling_combinational_nodes on --place_delta_delay_matrix_calculation_method dijkstra --gen_post_synthesis_netlist on --post_synth_netlist_unconn_inputs gnd --inner_loop_recompute_divider 1 --max_router_iterations 1500 --timing_report_detail detailed --timing_report_npaths 100 --top I_DELAY_primitive_inst --net_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net --place_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place --route_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route --pack +[ 13:35:27 ] Duration: 14685 ms. Max utilization: 1145 MB +[ 13:35:27 ] Placement has started +[ 13:35:27 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/planning --csv /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/Virgo_Pin_Table.csv --blif /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --output I_DELAY_primitive_inst_pin_loc.place --assign_unconstrained_pins in_define_order --clk_map I_DELAY_primitive_inst.temp_file_clkmap --read_repack /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/fpga_repack_constraints.xml --write_repack I_DELAY_primitive_inst_repack_constraints.xml --edits /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/config.json +[ 13:35:28 ] Duration: 287 ms. Max utilization: 284 MB +[ 13:35:28 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/bin/vpr /nfs_eda_sw/softwares/Raptor/instl_dir/09_19_2024_09_15_02/share/raptor/etc/devices/gemini_compact_62x44/gemini_vpr.xml /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/synthesis/fabric_I_DELAY_primitive_inst_post_synth.eblif --sdc_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_openfpga.sdc --route_chan_width 160 --suppress_warnings check_rr_node_warnings.log,check_rr_node --clock_modeling ideal --absorb_buffer_luts off --skip_sync_clustering_and_routing_results off --constant_net_method route --post_place_timing_report I_DELAY_primitive_inst_post_place_timing.rpt --device castor62x44_heterogeneous --allow_unrelated_clustering on --allow_dangling_combinational_nodes on --place_delta_delay_matrix_calculation_method dijkstra --gen_post_synthesis_netlist on --post_synth_netlist_unconn_inputs gnd --inner_loop_recompute_divider 1 --max_router_iterations 1500 --timing_report_detail detailed --timing_report_npaths 100 --top I_DELAY_primitive_inst --net_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/packing/fabric_I_DELAY_primitive_inst_post_synth.net --place_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/placement/fabric_I_DELAY_primitive_inst_post_synth.place --route_file /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/I_DELAY_primitive_inst/I_DELAY_primitive_inst/run_1/synth_1_1/impl_1_1_1/routing/fabric_I_DELAY_primitive_inst_post_synth.route --place --fix_clusters I_DELAY_primitive_inst_pin_loc.place +[ 13:36:51 ] Duration: 83817 ms. Max utilization: 711 MB diff --git a/EDA-3249/rtl/I_DELAY_primitive_inst.v b/EDA-3249/rtl/I_DELAY_primitive_inst.v new file mode 100644 index 00000000..4c1042b6 --- /dev/null +++ b/EDA-3249/rtl/I_DELAY_primitive_inst.v @@ -0,0 +1,35 @@ +module I_DELAY_primitive_inst #( + parameter DELAY = 0 // TAP delay value (0-63) +) ( + input reset, + input in, // Data Input (Connect to input port or buffer) + input DLY_LOAD, // Delay load input + input DLY_ADJ, // Delay adjust input + input DLY_INCDEC, // Delay increment / decrement input + output [5:0] DLY_TAP_VALUE, // Delay tap value output + input CLK_IN, // Clock input + output O // Data output +); + +reg dff; + +I_DELAY #( + .DELAY(0) +) inst ( + .I(dff), // Data Input (Connect to input port or buffer) + .DLY_LOAD(DLY_LOAD), // Delay load input + .DLY_ADJ(DLY_ADJ), // Delay adjust input + .DLY_INCDEC(DLY_INCDEC), // Delay increment / decrement input + .DLY_TAP_VALUE(DLY_TAP_VALUE), // Delay tap value output + .CLK_IN(CLK_IN), // Clock input + .O(O) +); + +always @(posedge CLK_IN) begin + if (reset) + dff <= 0; + else + dff <= in; +end + +endmodule