diff --git a/EDA-3164/GJC48.v b/EDA-3164/GJC48.v new file mode 100644 index 00000000..c3c0c867 --- /dev/null +++ b/EDA-3164/GJC48.v @@ -0,0 +1,38 @@ +module GJC48 ( + input wire clk, + input wire reset_n, + input wire [3:0] dma_req_in, + output reg [3:0] dma_ack_out +); + + reg [3:0] dma_req_reg; + reg [3:0] dma_ack_reg; + + // Instantiate the DMA module + SOC_FPGA_INTF_DMA dma_inst ( + .DMA_REQ (dma_req_reg), + .DMA_ACK (dma_ack_reg), + .DMA_CLK (clk), + .DMA_RST_N (reset_n) + ); + + // Input registers + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + dma_req_reg <= 4'b0; + end else begin + dma_req_reg <= dma_req_in; + end + end + + // Connect output register to top-level output + // Input registers + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + dma_ack_out <= 4'b0; + end else begin + dma_ack_out <= dma_ack_reg; + end + end + +endmodule diff --git a/EDA-3164/GJC48/GJC48.ospr b/EDA-3164/GJC48/GJC48.ospr new file mode 100644 index 00000000..e3bc590a --- /dev/null +++ b/EDA-3164/GJC48/GJC48.ospr @@ -0,0 +1,77 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/EDA-3164/GJC48/run_1/synth_1_1/analysis/GJC48_analyzer.cmd b/EDA-3164/GJC48/run_1/synth_1_1/analysis/GJC48_analyzer.cmd new file mode 100644 index 00000000..52555e46 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/analysis/GJC48_analyzer.cmd @@ -0,0 +1,5 @@ +read_verilog -sv /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v + +analyze -top GJC48 diff --git a/EDA-3164/GJC48/run_1/synth_1_1/analysis/analysis.rpt b/EDA-3164/GJC48/run_1/synth_1_1/analysis/analysis.rpt new file mode 100644 index 00000000..88071e84 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/analysis/analysis.rpt @@ -0,0 +1,125 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.08 +Build : 1.1.51 +Hash : c3b8064 +Date : Aug 27 2024 +Type : Engineering +Log Time : Tue Aug 27 07:56:02 2024 GMT + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) + + +-- Executing script file `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48/run_1/synth_1_1/analysis/GJC48_analyzer.cmd' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v' to AST representation. +Generating RTLIL representation for module `\GJC48'. +Successfully finished Verilog frontend. + +-- Running command `hierarchy -top GJC48' -- + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \GJC48 + +3.2. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +Dumping file hier_info.json ... + Process module "SOC_FPGA_INTF_DMA" +Dumping file port_info.json ... + +End of script. Logfile hash: 5a1a282c91, CPU: user 0.05s system 0.02s, MEM: 112.07 MB peak +Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) +Time spent: 95% 4x read_verilog (0 sec), 3% 1x analyze (0 sec), ... diff --git a/EDA-3164/GJC48/run_1/synth_1_1/analysis/hier_info.json b/EDA-3164/GJC48/run_1/synth_1_1/analysis/hier_info.json new file mode 100644 index 00000000..71a8a134 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/analysis/hier_info.json @@ -0,0 +1,125 @@ +{ + "fileIDs": { + "1": "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v", + "2": "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v" + }, + "hierTree": [ + { + "file": "2", + "internalSignals": [ + { + "name": "dma_ack_reg", + "range": { + "lsb": 0, + "msb": 3 + }, + "type": "LOGIC" + }, + { + "name": "dma_req_reg", + "range": { + "lsb": 0, + "msb": 3 + }, + "type": "LOGIC" + } + ], + "language": "SystemVerilog", + "line": 1, + "moduleInsts": [ + { + "file": "2", + "instName": "dma_inst", + "line": 12, + "module": "SOC_FPGA_INTF_DMA", + "parameters": [] + } + ], + "ports": [ + { + "direction": "Input", + "name": "clk", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "reset_n", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "dma_req_in", + "range": { + "lsb": 0, + "msb": 3 + }, + "type": "LOGIC" + }, + { + "direction": "Output", + "name": "dma_ack_out", + "range": { + "lsb": 0, + "msb": 3 + }, + "type": "LOGIC" + } + ], + "topModule": "GJC48" + } + ], + "modules": { + "SOC_FPGA_INTF_DMA": { + "file": "1", + "language": "SystemVerilog", + "line": 861, + "module": "SOC_FPGA_INTF_DMA", + "ports": [ + { + "direction": "Input", + "name": "DMA_REQ", + "range": { + "lsb": 0, + "msb": 3 + }, + "type": "LOGIC" + }, + { + "direction": "Output", + "name": "DMA_ACK", + "range": { + "lsb": 0, + "msb": 3 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "DMA_CLK", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "DMA_RST_N", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + } + ] + } + } +} diff --git a/EDA-3164/GJC48/run_1/synth_1_1/analysis/port_info.json b/EDA-3164/GJC48/run_1/synth_1_1/analysis/port_info.json new file mode 100644 index 00000000..c40a5ca6 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/analysis/port_info.json @@ -0,0 +1,43 @@ +[ + { + "ports": [ + { + "direction": "Input", + "name": "clk", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "reset_n", + "range": { + "lsb": 0, + "msb": 0 + }, + "type": "LOGIC" + }, + { + "direction": "Input", + "name": "dma_req_in", + "range": { + "lsb": 0, + "msb": 3 + }, + "type": "LOGIC" + }, + { + "direction": "Output", + "name": "dma_ack_out", + "range": { + "lsb": 0, + "msb": 3 + }, + "type": "LOGIC" + } + ], + "topModule": "GJC48" + } +] diff --git a/EDA-3164/GJC48/run_1/synth_1_1/impl_1_1_1/impl_1_1_1_settings/Tasks_Placement.json b/EDA-3164/GJC48/run_1/synth_1_1/impl_1_1_1/impl_1_1_1_settings/Tasks_Placement.json new file mode 100644 index 00000000..cbf8e132 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/impl_1_1_1/impl_1_1_1_settings/Tasks_Placement.json @@ -0,0 +1 @@ +{"Tasks":{"Placement":{"pin_selection_radiobtn":{"userValue":"In Define Order"}}}} \ No newline at end of file diff --git a/EDA-3164/GJC48/run_1/synth_1_1/impl_1_1_1/impl_1_1_1_settings/Tasks_Timing Analysis.json b/EDA-3164/GJC48/run_1/synth_1_1/impl_1_1_1/impl_1_1_1_settings/Tasks_Timing Analysis.json new file mode 100644 index 00000000..7039b132 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/impl_1_1_1/impl_1_1_1_settings/Tasks_Timing Analysis.json @@ -0,0 +1 @@ +{"Tasks":{"Timing Analysis":{"engine_radiobtn":{"userValue":"Tatum"}}}} \ No newline at end of file diff --git a/EDA-3164/GJC48/run_1/synth_1_1/simulate_gate/GJC48_comp_simulation.cmd b/EDA-3164/GJC48/run_1/synth_1_1/simulate_gate/GJC48_comp_simulation.cmd new file mode 100644 index 00000000..8c91f1b5 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/simulate_gate/GJC48_comp_simulation.cmd @@ -0,0 +1 @@ +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/HDL_simulator/iverilog/bin/iverilog -DIVERILOG=1 -v -s co_sim_GJC48 -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl -g2001 /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/co_sim_GJC48.v /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48/run_1/synth_1_1/synthesis/GJC48_post_synth.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/simlib.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/brams_sim.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/llatches_sim.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AXI_M0.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_IRQ.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUFT.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_BUF_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_JTAG.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO36K.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FCLK_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AXI_M1.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES_CLK.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO18KX2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_FAB.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DDR.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/TDP_RAM36K.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUFT_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AHB_M.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DDR.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_FAB.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/TDP_RAM18KX2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AHB_S.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_SERDES.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP19X2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_DMA.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/PLL.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/BOOT_CLOCK.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_TEMPERATURE.v diff --git a/EDA-3164/GJC48/run_1/synth_1_1/simulate_gate/simulation_gate.rpt b/EDA-3164/GJC48/run_1/synth_1_1/simulate_gate/simulation_gate.rpt new file mode 100644 index 00000000..ae6828e7 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/simulate_gate/simulation_gate.rpt @@ -0,0 +1,128 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.08 +Build : 1.1.51 +Hash : c3b8064 +Date : Aug 27 2024 +Type : Engineering +Log Time : Tue Aug 27 07:56:04 2024 GMT +Icarus Verilog Preprocessor version 13.0 (devel) (s20221226-498-g52d049b51) + +Copyright (c) 1999-2024 Stephen Williams (steve@icarus.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +Using language generation: IEEE1364-2001,no-specify,no-interconnect,xtypes,icarus-misc +PARSING INPUT +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO36K.v:193: error: block end label requires SystemVerilog. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO36K.v:232: parameter declarations are not permitted in generate blocks +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO36K.v:233: parameter declarations are not permitted in generate blocks +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO36K.v:637: error: block end label requires SystemVerilog. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:33: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:33: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:36: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:38: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:39: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:43: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:46: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:46: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:51: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:52: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:53: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:54: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:56: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:57: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:57: error: Syntax error in left side of continuous assignment. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:64: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:65: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:66: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:67: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:68: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:69: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:70: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:71: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:73: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:74: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:75: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:76: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:77: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:33: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:33: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:36: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:38: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:39: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:43: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:46: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:46: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:51: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:52: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:53: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:54: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:56: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:57: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:57: error: Syntax error in left side of continuous assignment. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:64: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:65: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:66: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:67: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:68: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:69: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:70: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:71: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:73: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:74: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:75: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:76: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES.v:43: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES.v:44: warning: Using SystemVerilog 'N bit vector. Use at least -g2005-sv to remove this warning. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES.v:43: error: Incomprehensible for loop. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/PLL.v:106: warning: Using SystemVerilog 'N bit vector. Use at least -g2005-sv to remove this warning. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/PLL.v:115: warning: Using SystemVerilog 'N bit vector. Use at least -g2005-sv to remove this warning. +/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/co_sim_GJC48.v:39: error: Empty function argument list requires SystemVerilog. +/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/co_sim_GJC48.v:55: warning: task definition for "compare" has an empty port declaration list! +Icarus Verilog version 13.0 (devel) (s20221226-498-g52d049b51) + +Copyright (c) 2000-2024 Stephen Williams (steve@icarus.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + +translate: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/ivlpp -v -L -F"/tmp/ivrlg26add4779" -f"/tmp/ivrlg6add4779" -p"/tmp/ivrli6add4779" |/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/ivl -v -C"/tmp/ivrlh6add4779" -C"/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/vvp.conf" -- - diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synth_1_1_settings/Tasks_Synthesis.json b/EDA-3164/GJC48/run_1/synth_1_1/synth_1_1_settings/Tasks_Synthesis.json new file mode 100644 index 00000000..f00904d9 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synth_1_1_settings/Tasks_Synthesis.json @@ -0,0 +1 @@ +{"Tasks":{"Synthesis":{"carry_chain_spinbox_ex":{"userValue":336},"bram_spinbox_ex":{"userValue":56},"dsp_spinbox_ex":{"userValue":56}}}} \ No newline at end of file diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/GJC48.ys b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/GJC48.ys new file mode 100644 index 00000000..54583e92 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/GJC48.ys @@ -0,0 +1,27 @@ + +# Yosys synthesis script for GJC48 +# Read source files +read_verilog -sv /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v + + +# Technology mapping +hierarchy -top GJC48 + +setattr -set keep 1 w:\clk + + +plugin -i synth-rs + +synth_rs -post_cleanup 1 -legalize_ram_clk_ports -new_iobuf_map 3 -iofab_map 1 -tech genesis3 -de -goal mixed -effort high -carry auto -keep_tribuf -new_dsp19x2 -new_tdp36k -max_lut 17472 -max_reg 34944 -max_device_dsp 56 -max_device_bram 56 -max_device_carry_length 336 -max_dsp 56 -max_bram 56 -max_carry_length 336 -fsm_encoding onehot -de_max_threads -1 + +write_verilog -noexpr -nodec -norename -v GJC48_post_synth.v +write_blif -param GJC48_post_synth.eblif + +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_location_GJC48.sdc -json config.json -w wrapper_GJC48_post_synth.v wrapper_GJC48_post_synth.eblif -pr post_pnr_wrapper_GJC48_post_synth.v post_pnr_wrapper_GJC48_post_synth.eblif +write_verilog -noexpr -nodec -norename -v fabric_GJC48_post_synth.v +write_blif -param fabric_GJC48_post_synth.eblif + + \ No newline at end of file diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/GJC48_post_synth.eblif b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/GJC48_post_synth.eblif new file mode 100644 index 00000000..1643e460 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/GJC48_post_synth.eblif @@ -0,0 +1,36 @@ +# Generated by Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) + +.model GJC48 +.inputs clk reset_n dma_req_in[0] dma_req_in[1] dma_req_in[2] dma_req_in[3] +.outputs dma_ack_out[0] dma_ack_out[1] dma_ack_out[2] dma_ack_out[3] +.names $false +.names $true +1 +.names $undef +.subckt DFFRE C=$clk_buf_$ibuf_clk D=dma_ack_reg[0] E=$true Q=$obuf_dma_ack_out[0] R=$ibuf_reset_n +.subckt DFFRE C=$clk_buf_$ibuf_clk D=dma_ack_reg[1] E=$true Q=$obuf_dma_ack_out[1] R=$ibuf_reset_n +.subckt DFFRE C=$clk_buf_$ibuf_clk D=dma_ack_reg[2] E=$true Q=$obuf_dma_ack_out[2] R=$ibuf_reset_n +.subckt DFFRE C=$clk_buf_$ibuf_clk D=dma_ack_reg[3] E=$true Q=$obuf_dma_ack_out[3] R=$ibuf_reset_n +.subckt DFFRE C=$clk_buf_$ibuf_clk D=$ibuf_dma_req_in[0] E=$true Q=dma_req_reg[0] R=$ibuf_reset_n +.subckt DFFRE C=$clk_buf_$ibuf_clk D=$ibuf_dma_req_in[1] E=$true Q=dma_req_reg[1] R=$ibuf_reset_n +.subckt DFFRE C=$clk_buf_$ibuf_clk D=$ibuf_dma_req_in[2] E=$true Q=dma_req_reg[2] R=$ibuf_reset_n +.subckt DFFRE C=$clk_buf_$ibuf_clk D=$ibuf_dma_req_in[3] E=$true Q=dma_req_reg[3] R=$ibuf_reset_n +.subckt CLK_BUF I=$ibuf_clk O=$clk_buf_$ibuf_clk +.subckt I_BUF EN=$true I=clk O=$ibuf_clk +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$true I=dma_req_in[0] O=$ibuf_dma_req_in[0] +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$true I=dma_req_in[1] O=$ibuf_dma_req_in[1] +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$true I=dma_req_in[2] O=$ibuf_dma_req_in[2] +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$true I=dma_req_in[3] O=$ibuf_dma_req_in[3] +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$true I=reset_n O=$ibuf_reset_n +.param WEAK_KEEPER "NONE" +.subckt O_BUFT I=$obuf_dma_ack_out[0] O=dma_ack_out[0] T=$true +.subckt O_BUFT I=$obuf_dma_ack_out[1] O=dma_ack_out[1] T=$true +.subckt O_BUFT I=$obuf_dma_ack_out[2] O=dma_ack_out[2] T=$true +.subckt O_BUFT I=$obuf_dma_ack_out[3] O=dma_ack_out[3] T=$true +.subckt SOC_FPGA_INTF_DMA DMA_ACK[0]=dma_ack_reg[0] DMA_ACK[1]=dma_ack_reg[1] DMA_ACK[2]=dma_ack_reg[2] DMA_ACK[3]=dma_ack_reg[3] DMA_CLK=$ibuf_clk DMA_REQ[0]=dma_req_reg[0] DMA_REQ[1]=dma_req_reg[1] DMA_REQ[2]=dma_req_reg[2] DMA_REQ[3]=dma_req_reg[3] DMA_RST_N=$ibuf_reset_n +.end diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/GJC48_post_synth.v b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/GJC48_post_synth.v new file mode 100644 index 00000000..3432e8c5 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/GJC48_post_synth.v @@ -0,0 +1,247 @@ +/* Generated by Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) */ + +module GJC48(clk, reset_n, dma_req_in, dma_ack_out); + input clk; + output [3:0] dma_ack_out; + input [3:0] dma_req_in; + input reset_n; + wire \$clk_buf_$ibuf_clk ; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" *) + wire \$ibuf_clk ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + wire \$ibuf_reset_n ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[0] ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[1] ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[2] ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[3] ; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" *) + wire clk; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire [3:0] dma_ack_out; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire [3:0] dma_req_in; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[0] ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[1] ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[2] ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + wire reset_n; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_268 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\dma_ack_reg[0] ), + .E(1'h1), + .Q(\$obuf_dma_ack_out[0] ), + .R(\$ibuf_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_269 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\dma_ack_reg[1] ), + .E(1'h1), + .Q(\$obuf_dma_ack_out[1] ), + .R(\$ibuf_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_270 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\dma_ack_reg[2] ), + .E(1'h1), + .Q(\$obuf_dma_ack_out[2] ), + .R(\$ibuf_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_271 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\dma_ack_reg[3] ), + .E(1'h1), + .Q(\$obuf_dma_ack_out[3] ), + .R(\$ibuf_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_272 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\$ibuf_dma_req_in[0] ), + .E(1'h1), + .Q(\dma_req_reg[0] ), + .R(\$ibuf_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_273 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\$ibuf_dma_req_in[1] ), + .E(1'h1), + .Q(\dma_req_reg[1] ), + .R(\$ibuf_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_274 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\$ibuf_dma_req_in[2] ), + .E(1'h1), + .Q(\dma_req_reg[2] ), + .R(\$ibuf_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_275 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\$ibuf_dma_req_in[3] ), + .E(1'h1), + .Q(\dma_req_reg[3] ), + .R(\$ibuf_reset_n ) + ); + (* keep = 32'sh00000001 *) + CLK_BUF \$clkbuf$GJC48.$ibuf_clk ( + .I(\$ibuf_clk ), + .O(\$clk_buf_$ibuf_clk ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC48.$ibuf_clk ( + .EN(1'h1), + .I(clk), + .O(\$ibuf_clk ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC48.$ibuf_dma_req_in ( + .EN(1'h1), + .I(dma_req_in[0]), + .O(\$ibuf_dma_req_in[0] ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC48.$ibuf_dma_req_in_1 ( + .EN(1'h1), + .I(dma_req_in[1]), + .O(\$ibuf_dma_req_in[1] ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC48.$ibuf_dma_req_in_2 ( + .EN(1'h1), + .I(dma_req_in[2]), + .O(\$ibuf_dma_req_in[2] ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC48.$ibuf_dma_req_in_3 ( + .EN(1'h1), + .I(dma_req_in[3]), + .O(\$ibuf_dma_req_in[3] ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC48.$ibuf_reset_n ( + .EN(1'h1), + .I(reset_n), + .O(\$ibuf_reset_n ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC48.$obuf_dma_ack_out ( + .I(\$obuf_dma_ack_out[0] ), + .O(dma_ack_out[0]), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC48.$obuf_dma_ack_out_1 ( + .I(\$obuf_dma_ack_out[1] ), + .O(dma_ack_out[1]), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC48.$obuf_dma_ack_out_2 ( + .I(\$obuf_dma_ack_out[2] ), + .O(dma_ack_out[2]), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC48.$obuf_dma_ack_out_3 ( + .I(\$obuf_dma_ack_out[3] ), + .O(dma_ack_out[3]), + .T(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:12.21-17.4" *) + SOC_FPGA_INTF_DMA dma_inst ( + .DMA_ACK({ \dma_ack_reg[3] , \dma_ack_reg[2] , \dma_ack_reg[1] , \dma_ack_reg[0] }), + .DMA_CLK(\$ibuf_clk ), + .DMA_REQ({ \dma_req_reg[3] , \dma_req_reg[2] , \dma_req_reg[1] , \dma_req_reg[0] }), + .DMA_RST_N(\$ibuf_reset_n ) + ); +endmodule diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/GJC48_synth.log b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/GJC48_synth.log new file mode 100644 index 00000000..1f256860 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/GJC48_synth.log @@ -0,0 +1,2199 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) + + +-- Executing script file `GJC48.ys' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v' to AST representation. +Generating RTLIL representation for module `\GJC48'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \GJC48 + +3.2. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +4. Executing synth_rs pass: v0.4.218 + +4.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\inv'. +Generating RTLIL representation for module `\buff'. +Generating RTLIL representation for module `\logic_0'. +Generating RTLIL representation for module `\logic_1'. +Generating RTLIL representation for module `\gclkbuff'. +Successfully finished Verilog frontend. + +4.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v' to AST representation. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v:10.1-33.10. +Generating RTLIL representation for module `\CARRY'. +Successfully finished Verilog frontend. + +4.3. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v' to AST representation. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:20.1-34.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:48.1-62.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:81.1-97.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:115.1-131.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:150.1-166.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:184.1-200.10. +Generating RTLIL representation for module `\LATCHNS'. +Generating RTLIL representation for module `\LATCHSRE'. +Generating RTLIL representation for module `\LATCHNSRE'. +Successfully finished Verilog frontend. + +4.4. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v' to AST representation. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:11.1-81.10. +Generating RTLIL representation for module `\DFFRE'. +Successfully finished Verilog frontend. + +4.5. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v' to AST representation. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:11.1-80.10. +Generating RTLIL representation for module `\DFFNRE'. +Successfully finished Verilog frontend. + +4.6. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v' to AST representation. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v:10.1-20.10. +Generating RTLIL representation for module `\LUT1'. +Successfully finished Verilog frontend. + +4.7. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v' to AST representation. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v:10.1-21.10. +Generating RTLIL representation for module `\LUT2'. +Successfully finished Verilog frontend. + +4.8. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v' to AST representation. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v:10.1-22.10. +Generating RTLIL representation for module `\LUT3'. +Successfully finished Verilog frontend. + +4.9. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v' to AST representation. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v:11.1-25.10. +Generating RTLIL representation for module `\LUT4'. +Successfully finished Verilog frontend. + +4.10. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v' to AST representation. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v:10.1-24.10. +Generating RTLIL representation for module `\LUT5'. +Successfully finished Verilog frontend. + +4.11. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v' to AST representation. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v:10.1-25.10. +Generating RTLIL representation for module `\LUT6'. +Successfully finished Verilog frontend. + +4.12. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v' to AST representation. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v:10.1-25.10. +Generating RTLIL representation for module `\CLK_BUF'. +Successfully finished Verilog frontend. + +4.13. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v' to AST representation. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v:10.1-84.10. +Generating RTLIL representation for module `\O_BUF'. +Successfully finished Verilog frontend. + +4.14. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v' to AST representation. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v:10.1-341.10. +Generating RTLIL representation for module `\DSP38'. +Successfully finished Verilog frontend. + +4.15. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v' to AST representation. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:2.1-29.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:33.1-84.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\RS_DSP3'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:116.1-149.10. +Generating RTLIL representation for module `\DSP19X2'. +Successfully finished Verilog frontend. + +4.16. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v' to AST representation. +Generating RTLIL representation for module `\TDP_BRAM18'. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Generating RTLIL representation for module `\_$_mem_v2_asymmetric'. +Successfully finished Verilog frontend. + +4.17. Executing HIERARCHY pass (managing design hierarchy). + +4.17.1. Analyzing design hierarchy.. +Top module: \GJC48 + +4.17.2. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +4.18. Executing PROC pass (convert processes to netlists). + +4.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3 in module GJC48. +Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1 in module GJC48. +Removed a total of 0 dead cases. + +4.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 2 redundant assignments. +Promoted 0 assignments to connections. + +4.18.4. Executing PROC_INIT pass (extract init attributes). + +4.18.5. Executing PROC_ARST pass (detect async resets in processes). +Found async reset \reset_n in `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3'. +Found async reset \reset_n in `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1'. + +4.18.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +4.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3'. + 1/1: $0\dma_ack_out[3:0] +Creating decoders for process `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1'. + 1/1: $0\dma_req_reg[3:0] + +4.18.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +4.18.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\GJC48.\dma_ack_out' using process `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3'. + created $adff cell `$procdff$5' with positive edge clock and negative level reset. +Creating register for signal `\GJC48.\dma_req_reg' using process `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1'. + created $adff cell `$procdff$6' with positive edge clock and negative level reset. + +4.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3'. +Removing empty process `GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1'. +Cleaned up 0 empty switches. + +4.18.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.19. Executing FLATTEN pass (flatten design). + +# -------------------- +# Design entry stats +# -------------------- + +4.20. Printing statistics. + +=== GJC48 === + + Number of wires: 10 + Number of wire bits: 28 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + $adff 2 + $logic_not 2 + SOC_FPGA_INTF_DMA 1 + +4.21. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.22. Executing DEMUXMAP pass. + +4.23. Executing FLATTEN pass (flatten design). + +4.24. Executing DEMUXMAP pass. + +4.25. Executing TRIBUF pass. +Warning: Ignored -no_iobuf because -keep_tribuf is used. + +4.26. Executing DEMINOUT pass (demote inout ports to input or output). + +4.27. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 2 unused cells and 4 unused wires. + + +4.29. Executing CHECK pass (checking for obvious problems). +Checking module GJC48... +Found and reported 0 problems. + +4.30. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.31. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.32. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.33. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.34. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.35. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.36. Executing OPT_SHARE pass. + +4.37. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.38. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.40. Executing FSM pass (extract and optimize FSM). + +4.40.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.40.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.40.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.40.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.40.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.40.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.41. Executing WREDUCE pass (reducing word size of cells). + +4.42. Executing PEEPOPT pass (run peephole optimizers). + +4.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.44. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.45. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.46. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.47. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.48. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.49. Executing OPT_SHARE pass. + +4.50. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.51. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.52. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.53. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.54. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.55. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.56. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.57. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.58. Executing OPT_SHARE pass. + +4.59. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.60. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.61. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.62. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.63. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.64. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.65. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.66. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.67. Executing OPT_SHARE pass. + +4.68. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.69. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=4, #remove=0, time=0.00 sec.] + +4.70. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.71. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.72. Executing WREDUCE pass (reducing word size of cells). + +4.73. Executing PEEPOPT pass (run peephole optimizers). + +4.74. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.75. Executing DEMUXMAP pass. + +4.76. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.77. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.78. Executing RS_DSP_MULTADD pass. + +4.79. Executing WREDUCE pass (reducing word size of cells). + +4.80. Executing RS_DSP_MACC pass. + +4.81. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.82. Executing TECHMAP pass (map to technology primitives). + +4.82.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.82.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.83. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.84. Executing TECHMAP pass (map to technology primitives). + +4.84.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.84.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.85. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.86. Executing TECHMAP pass (map to technology primitives). + +4.86.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.86.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.87. Executing TECHMAP pass (map to technology primitives). + +4.87.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.87.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.88. Executing TECHMAP pass (map to technology primitives). + +4.88.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__RS_MUL20X18'. +Generating RTLIL representation for module `\$__RS_MUL10X9'. +Successfully finished Verilog frontend. + +4.88.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.89. Executing RS_DSP_SIMD pass. + +4.90. Executing TECHMAP pass (map to technology primitives). + +4.90.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v' to AST representation. +Generating RTLIL representation for module `\dsp_t1_20x18x64_cfg_ports'. +Generating RTLIL representation for module `\dsp_t1_10x9x32_cfg_params'. +Successfully finished Verilog frontend. + +4.90.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.91. Executing TECHMAP pass (map to technology primitives). + +4.91.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.91.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.92. Executing rs_pack_dsp_regs pass. + +4.93. Executing RS_DSP_IO_REGS pass. + +4.94. Executing TECHMAP pass (map to technology primitives). + +4.94.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSP_MULTACC'. +Generating RTLIL representation for module `\RS_DSP_MULT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN_REGOUT'. +Successfully finished Verilog frontend. + +4.94.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.95. Executing TECHMAP pass (map to technology primitives). + +4.95.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.95.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.96. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.97. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module GJC48: + created 0 $alu and 0 $macc cells. + +4.98. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.99. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.100. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.101. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.102. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.103. Executing OPT_SHARE pass. + +4.104. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.105. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.106. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.107. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.108. Executing MEMORY pass. + +4.108.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.108.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.108.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.108.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.108.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.108.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.108.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.108.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.108.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.108.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.109. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.110. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.111. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.112. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.113. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.114. Executing Rs_BRAM_Split pass. + +4.115. Executing TECHMAP pass (map to technology primitives). + +4.115.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_SDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_SDP'. +Successfully finished Verilog frontend. + +4.115.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.116. Executing TECHMAP pass (map to technology primitives). + +4.116.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Successfully finished Verilog frontend. + +4.116.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.117. Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs). + +4.118. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.119. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.120. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.121. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.122. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.123. Executing OPT_SHARE pass. + +4.124. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.125. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.126. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.127. Executing PMUXTREE pass. + +4.128. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.129. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +4.130. Executing TECHMAP pass (map to technology primitives). + +4.130.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.130.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_rs_alu'. +Successfully finished Verilog frontend. + +4.130.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $adff. +No more expansions possible. + + +4.131. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + +4.132. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.133. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.134. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.135. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.136. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.137. Executing OPT_SHARE pass. + +4.138. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.139. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.140. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.141. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.142. Executing TECHMAP pass (map to technology primitives). + +4.142.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.142.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.143. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + +4.144. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.145. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.146. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.147. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.148. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.149. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.150. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.151. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.152. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.153. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.154. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.155. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.156. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.157. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.158. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.159. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.160. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.161. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.162. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.163. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.164. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.165. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.166. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=4, #remove=0, time=0.00 sec.] + +4.167. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.168. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.169. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + + Number of Generic REGs: 8 + +ABC-DFF iteration : 1 + +4.170. Executing ABC pass (technology mapping using ABC). + +4.170.1. Summary of detected clock domains: + 9 cells in clk=\clk, en={ }, arst=!\reset_n, srst={ } + + #logic partitions = 1 + +4.170.2. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Found matching posedge clock domain: \clk, asynchronously reset by !\reset_n +Extracted 8 gates and 16 wires to a netlist network with 8 inputs and 8 outputs (dfl=1). + +4.170.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.171. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.172. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.173. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.174. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.175. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.176. Executing OPT_SHARE pass. + +4.177. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.178. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.179. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 2 + +4.180. Executing ABC pass (technology mapping using ABC). + +4.180.1. Summary of detected clock domains: + 9 cells in clk=\clk, en={ }, arst=!\reset_n, srst={ } + + #logic partitions = 1 + +4.180.2. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Found matching posedge clock domain: \clk, asynchronously reset by !\reset_n +Extracted 8 gates and 16 wires to a netlist network with 8 inputs and 8 outputs (dfl=1). + +4.180.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.181. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.182. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.183. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.184. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.185. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.186. Executing OPT_SHARE pass. + +4.187. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.188. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.189. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 3 + +4.190. Executing ABC pass (technology mapping using ABC). + +4.190.1. Summary of detected clock domains: + 9 cells in clk=\clk, en={ }, arst=!\reset_n, srst={ } + + #logic partitions = 1 + +4.190.2. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Found matching posedge clock domain: \clk, asynchronously reset by !\reset_n +Extracted 8 gates and 16 wires to a netlist network with 8 inputs and 8 outputs (dfl=2). + +4.190.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.191. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.192. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.193. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.194. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.195. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.196. Executing OPT_SHARE pass. + +4.197. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.198. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.199. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 4 + +4.200. Executing ABC pass (technology mapping using ABC). + +4.200.1. Summary of detected clock domains: + 9 cells in clk=\clk, en={ }, arst=!\reset_n, srst={ } + + #logic partitions = 1 + +4.200.2. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Found matching posedge clock domain: \clk, asynchronously reset by !\reset_n +Extracted 8 gates and 16 wires to a netlist network with 8 inputs and 8 outputs (dfl=2). + +4.200.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.201. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.202. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.203. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.204. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.205. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.206. Executing OPT_SHARE pass. + +4.207. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.208. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.209. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 +select with DFL2 synthesis (thresh-logic=0.920000, thresh_dff=0.980000) + +4.210. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.211. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.212. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.213. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.214. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.215. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.216. Executing OPT_SHARE pass. + +4.217. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.218. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.219. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.220. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.221. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.222. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.223. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.224. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.225. Executing OPT_SHARE pass. + +4.226. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.227. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.228. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.229. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.230. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.231. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.232. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.233. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.234. Executing OPT_SHARE pass. + +4.235. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.236. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=4, #remove=0, time=0.00 sec.] + +4.237. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.238. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.239. Executing BMUXMAP pass. + +4.240. Executing DEMUXMAP pass. + +4.241. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.242. Executing ABC pass (technology mapping using ABC). + +4.242.1. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs (dfl=1). +Don't call ABC as there is nothing to map. + +4.243. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.244. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.245. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.246. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.247. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.248. Executing OPT_SHARE pass. + +4.249. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.250. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.251. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.252. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.253. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.254. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.255. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.256. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.257. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.258. Executing OPT_SHARE pass. + +4.259. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.260. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.261. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.262. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.263. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.264. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.265. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.266. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.267. Executing OPT_SHARE pass. + +4.268. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.269. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=4, #remove=0, time=0.00 sec.] + +4.270. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.271. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.272. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + +4.273. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +4.274. Executing RS_DFFSR_CONV pass. + +4.275. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + +4.276. Executing TECHMAP pass (map to technology primitives). + +4.276.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.276.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PN0P_'. +Generating RTLIL representation for module `\$_DFFE_PN0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_DFFE_PN1P_'. +Generating RTLIL representation for module `\$_DFFE_PN1N_'. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NN0P_'. +Generating RTLIL representation for module `\$_DFFE_NN0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_NN1P_'. +Generating RTLIL representation for module `\$_DFFE_NN1N_'. +Generating RTLIL representation for module `\$__SHREG_DFF_P_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PN0_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NN0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_PN1_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_NN1_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_PP0_'. +Generating RTLIL representation for module `\$_DLATCH_PN0_'. +Generating RTLIL representation for module `\$_DLATCH_NP0_'. +Generating RTLIL representation for module `\$_DLATCH_NN0_'. +Generating RTLIL representation for module `\$_DLATCH_PP1_'. +Generating RTLIL representation for module `\$_DLATCH_PN1_'. +Generating RTLIL representation for module `\$_DLATCH_NP1_'. +Generating RTLIL representation for module `\$_DLATCH_NN1_'. +Successfully finished Verilog frontend. + +4.276.3. Continuing TECHMAP pass. +No more expansions possible. + + +4.277. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.278. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +4.279. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.280. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.281. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.282. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.283. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.284. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.285. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.286. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.287. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.288. Executing OPT_SHARE pass. + +4.289. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.290. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.291. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.292. Executing TECHMAP pass (map to technology primitives). + +4.292.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.292.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.293. Executing ABC pass (technology mapping using ABC). + +4.293.1. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs (dfl=1). +Don't call ABC as there is nothing to map. + +4.294. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.295. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.296. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.297. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.298. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.299. Executing OPT_SHARE pass. + +4.300. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.301. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.302. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.303. Executing HIERARCHY pass (managing design hierarchy). + +4.303.1. Analyzing design hierarchy.. +Top module: \GJC48 + +4.303.2. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +4.304. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.305. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__IO_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.306. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Replacing existing blackbox module `\BOOT_CLOCK' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:9.1-14.10. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:24.1-31.10. +Generating RTLIL representation for module `\CARRY'. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:41.1-46.10. +Generating RTLIL representation for module `\CLK_BUF'. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:56.1-64.10. +Generating RTLIL representation for module `\DFFNRE'. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:74.1-82.10. +Generating RTLIL representation for module `\DFFRE'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:92.1-126.10. +Generating RTLIL representation for module `\DSP19X2'. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:136.1-162.10. +Generating RTLIL representation for module `\DSP38'. +Replacing existing blackbox module `\FCLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:172.1-176.10. +Generating RTLIL representation for module `\FCLK_BUF'. +Replacing existing blackbox module `\FIFO18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:186.1-233.10. +Generating RTLIL representation for module `\FIFO18KX2'. +Replacing existing blackbox module `\FIFO36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:243.1-268.10. +Generating RTLIL representation for module `\FIFO36K'. +Replacing existing blackbox module `\I_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:278.1-290.10. +Generating RTLIL representation for module `\I_BUF_DS'. +Replacing existing blackbox module `\I_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:300.1-309.10. +Generating RTLIL representation for module `\I_BUF'. +Replacing existing blackbox module `\I_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:319.1-327.10. +Generating RTLIL representation for module `\I_DDR'. +Replacing existing blackbox module `\I_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:337.1-349.10. +Generating RTLIL representation for module `\I_DELAY'. +Replacing existing blackbox module `\I_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:359.1-363.10. +Generating RTLIL representation for module `\I_FAB'. +Replacing existing blackbox module `\I_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:373.1-392.10. +Generating RTLIL representation for module `\I_SERDES'. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:402.1-408.10. +Generating RTLIL representation for module `\LUT1'. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:418.1-424.10. +Generating RTLIL representation for module `\LUT2'. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:434.1-440.10. +Generating RTLIL representation for module `\LUT3'. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:450.1-456.10. +Generating RTLIL representation for module `\LUT4'. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:466.1-472.10. +Generating RTLIL representation for module `\LUT5'. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:482.1-488.10. +Generating RTLIL representation for module `\LUT6'. +Replacing existing blackbox module `\O_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:498.1-510.10. +Generating RTLIL representation for module `\O_BUF_DS'. +Replacing existing blackbox module `\O_BUFT_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:520.1-532.10. +Generating RTLIL representation for module `\O_BUFT_DS'. +Replacing existing blackbox module `\O_BUFT' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:542.1-553.10. +Generating RTLIL representation for module `\O_BUFT'. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:563.1-574.10. +Generating RTLIL representation for module `\O_BUF'. +Replacing existing blackbox module `\O_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:584.1-592.10. +Generating RTLIL representation for module `\O_DDR'. +Replacing existing blackbox module `\O_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:602.1-614.10. +Generating RTLIL representation for module `\O_DELAY'. +Replacing existing blackbox module `\O_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:624.1-628.10. +Generating RTLIL representation for module `\O_FAB'. +Replacing existing blackbox module `\O_SERDES_CLK' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:638.1-647.10. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Replacing existing blackbox module `\O_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:657.1-674.10. +Generating RTLIL representation for module `\O_SERDES'. +Replacing existing blackbox module `\PLL' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:684.1-702.10. +Generating RTLIL representation for module `\PLL'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_M' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:712.1-726.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_S' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:736.1-753.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M0' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:763.1-802.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M1' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:812.1-851.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Replacing existing blackbox module `\SOC_FPGA_INTF_DMA' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:861.1-867.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Replacing existing blackbox module `\SOC_FPGA_INTF_IRQ' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:877.1-883.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Replacing existing blackbox module `\SOC_FPGA_INTF_JTAG' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:893.1-901.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Replacing existing blackbox module `\SOC_FPGA_TEMPERATURE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:911.1-919.10. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:929.1-984.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:994.1-1023.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1040.1-1045.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1053.1-1058.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1067.1-1073.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1081.1-1087.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1096.1-1102.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1111.1-1117.10. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + *************************** + Inserting Input Buffers + *************************** +WARNING: port '\clk' has no associated I_BUF +WARNING: port '\dma_req_in' has no associated I_BUF +WARNING: port '\reset_n' has no associated I_BUF + *************************** + Inserting Clock Buffers + *************************** +INFO: inserting CLK_BUF before '$ibuf_clk' + ***************************** + Inserting Output Buffers + ***************************** +WARNING: OUTPUT port '\dma_ack_out' has no associated O_BUF + ***************************** + Mapping Tri-state Buffers + ***************************** + +4.307. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.308. Executing TECHMAP pass (map to technology primitives). + +4.308.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.308.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.309. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 30 unused wires. + + +4.310. Printing statistics. + +=== GJC48 === + + Number of wires: 11 + Number of wire bits: 29 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUF 4 + SOC_FPGA_INTF_DMA 1 + +4.311. Executing TECHMAP pass (map to technology primitives). + +4.311.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v' to AST representation. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +4.311.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.312. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.313. Printing statistics. + +=== GJC48 === + + Number of wires: 11 + Number of wire bits: 29 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUF 4 + SOC_FPGA_INTF_DMA 1 + + ***************************** + Rewire_Obuft + ***************************** + +========================== +Post Design clean up ... + +Split to bits ... + +4.314. Executing SPLITNETS pass (splitting up multi-bit signals). + +Split into bits ... [0.00 sec.] +Building Sig2cells ... [0.00 sec.] +Building Sig2sig ... [0.00 sec.] +Backward clean up ... [0.00 sec.] +Before cleanup : + +4.315. Printing statistics. + +=== GJC48 === + + Number of wires: 23 + Number of wire bits: 29 + Number of public wires: 12 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUFT 4 + SOC_FPGA_INTF_DMA 1 + + -------------------------- + Removed assigns : 0 + Removed wires : 0 + Removed cells : 0 + -------------------------- +After cleanup : + +4.316. Printing statistics. + +=== GJC48 === + + Number of wires: 23 + Number of wire bits: 29 + Number of public wires: 12 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUFT 4 + SOC_FPGA_INTF_DMA 1 + + +Total time for 'obs_clean' ... + [0.00 sec.] + +4.317. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.318. Executing HIERARCHY pass (managing design hierarchy). + +4.318.1. Analyzing design hierarchy.. +Top module: \GJC48 + +4.318.2. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +Dumping port properties into 'netlist_info.json' file. + + +Inserting I_FAB/O_FAB cells ... + + +Inserting I_FAB/O_FAB cells done. + +4.319. Printing statistics. + +=== GJC48 === + + Number of wires: 23 + Number of wire bits: 29 + Number of public wires: 12 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUFT 4 + SOC_FPGA_INTF_DMA 1 + + Number of LUTs: 0 + Number of REGs: 8 + Number of CARRY ADDERs: 0 + +4.320. Executing Verilog backend. +Dumping module `\GJC48'. + +# -------------------- +# Core Synthesis done +# -------------------- + +4.321. Executing Verilog backend. +Dumping module `\GJC48'. + +4.321.1. Executing BLIF backend. + +-- Running command `write_rtlil design.rtlil' -- + +4.321.2. Executing RTLIL backend. +Output filename: design.rtlil + +4.321.3. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.321.4. Executing FLATTEN pass (flatten design). +Deleting now unused module interface_GJC48. + + +4.321.5. Executing Verilog backend. +Dumping module `\GJC48'. + +4.321.5.1. Executing BLIF backend. + +4.321.5.2. Executing Verilog backend. +Dumping module `\GJC48'. + +4.321.5.2.1. Executing BLIF backend. + +4.321.5.2.2. Executing Verilog backend. +Dumping module `\fabric_GJC48'. + +4.321.5.2.2.1. Executing BLIF backend. + +Warnings: 1 unique messages, 1 total +End of script. Logfile hash: 0f3c69f369, CPU: user 0.72s system 0.09s, MEM: 112.07 MB peak +Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) +Time spent: 31% 43x read_verilog (0 sec), 19% 6x abc (0 sec), ... diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/config.json b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/config.json new file mode 100644 index 00000000..522af522 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/config.json @@ -0,0 +1,553 @@ +{ + "instances": [ + { + "connectivity": { + "$auto_524": "$auto_524", + "$auto_525": "$auto_525", + "$auto_526": "$auto_526", + "$auto_527": "$auto_527", + "$auto_528": "$auto_528", + "$auto_529": "$auto_529", + "$auto_530": "$auto_530", + "$auto_531": "$auto_531", + "$auto_532": "$auto_532", + "$auto_533": "$auto_533", + "$clk_buf_$ibuf_clk": "$clk_buf_$ibuf_clk", + "$ibuf_dma_req_in[0]": "$ibuf_dma_req_in[0]", + "$ibuf_dma_req_in[1]": "$ibuf_dma_req_in[1]", + "$ibuf_dma_req_in[2]": "$ibuf_dma_req_in[2]", + "$ibuf_dma_req_in[3]": "$ibuf_dma_req_in[3]", + "$ibuf_reset_n": "$ibuf_reset_n", + "$obuf_dma_ack_out[0]": "$obuf_dma_ack_out[0]", + "$obuf_dma_ack_out[1]": "$obuf_dma_ack_out[1]", + "$obuf_dma_ack_out[2]": "$obuf_dma_ack_out[2]", + "$obuf_dma_ack_out[3]": "$obuf_dma_ack_out[3]", + "dma_ack_reg[0]": "dma_ack_reg[0]", + "dma_ack_reg[1]": "dma_ack_reg[1]", + "dma_ack_reg[2]": "dma_ack_reg[2]", + "dma_ack_reg[3]": "dma_ack_reg[3]", + "dma_req_reg[0]": "dma_req_reg[0]", + "dma_req_reg[1]": "dma_req_reg[1]", + "dma_req_reg[2]": "dma_req_reg[2]", + "dma_req_reg[3]": "dma_req_reg[3]" + }, + "module": "fabric_GJC48", + "name": "$auto_534" + }, + { + "connectivity": { + "DMA_ACK": [ + "$auto_535.dma_ack_reg[0]", + "$auto_535.dma_ack_reg[1]", + "$auto_535.dma_ack_reg[2]", + "$auto_535.dma_ack_reg[3]" + ], + "DMA_CLK": "$flatten$auto_535.$ibuf_clk", + "DMA_REQ": [ + "$auto_535.dma_req_reg[0]", + "$auto_535.dma_req_reg[1]", + "$auto_535.dma_req_reg[2]", + "$auto_535.dma_req_reg[3]" + ], + "DMA_RST_N": "$flatten$auto_535.$ibuf_reset_n" + }, + "module": "SOC_FPGA_INTF_DMA", + "name": "$auto_535.dma_inst" + }, + { + "connectivity": { + "I": "$flatten$auto_535.$ibuf_clk", + "O": "$flatten$auto_535.$clk_buf_$ibuf_clk" + }, + "direction": "IN", + "index": 2, + "linked_object": "clk", + "module": "CLK_BUF", + "name": "$flatten$auto_535.$clkbuf$GJC48.$ibuf_clk" + }, + { + "connectivity": { + "EN": "$flatten$auto_535.$auto_524", + "I": "$auto_535.clk", + "O": "$flatten$auto_535.$ibuf_clk" + }, + "direction": "IN", + "index": 1, + "linked_object": "clk", + "module": "I_BUF", + "name": "$flatten$auto_535.$ibuf$GJC48.$ibuf_clk" + }, + { + "connectivity": { + "EN": "$flatten$auto_535.$auto_525", + "I": "$auto_535.dma_req_in[0]", + "O": "$flatten$auto_535.$ibuf_dma_req_in[0]" + }, + "direction": "IN", + "index": 1, + "linked_object": "dma_req_in[0]", + "module": "I_BUF", + "name": "$flatten$auto_535.$ibuf$GJC48.$ibuf_dma_req_in" + }, + { + "connectivity": { + "EN": "$flatten$auto_535.$auto_526", + "I": "$auto_535.dma_req_in[1]", + "O": "$flatten$auto_535.$ibuf_dma_req_in[1]" + }, + "direction": "IN", + "index": 1, + "linked_object": "dma_req_in[1]", + "module": "I_BUF", + "name": "$flatten$auto_535.$ibuf$GJC48.$ibuf_dma_req_in_1" + }, + { + "connectivity": { + "EN": "$flatten$auto_535.$auto_527", + "I": "$auto_535.dma_req_in[2]", + "O": "$flatten$auto_535.$ibuf_dma_req_in[2]" + }, + "direction": "IN", + "index": 1, + "linked_object": "dma_req_in[2]", + "module": "I_BUF", + "name": "$flatten$auto_535.$ibuf$GJC48.$ibuf_dma_req_in_2" + }, + { + "connectivity": { + "EN": "$flatten$auto_535.$auto_528", + "I": "$auto_535.dma_req_in[3]", + "O": "$flatten$auto_535.$ibuf_dma_req_in[3]" + }, + "direction": "IN", + "index": 1, + "linked_object": "dma_req_in[3]", + "module": "I_BUF", + "name": "$flatten$auto_535.$ibuf$GJC48.$ibuf_dma_req_in_3" + }, + { + "connectivity": { + "EN": "$flatten$auto_535.$auto_529", + "I": "$auto_535.reset_n", + "O": "$flatten$auto_535.$ibuf_reset_n" + }, + "direction": "IN", + "index": 1, + "linked_object": "reset_n", + "module": "I_BUF", + "name": "$flatten$auto_535.$ibuf$GJC48.$ibuf_reset_n" + }, + { + "connectivity": { + "I": "$flatten$auto_535.$obuf_dma_ack_out[0]", + "O": "$auto_535.dma_ack_out[0]", + "T": "$flatten$auto_535.$auto_530" + }, + "direction": "OUT", + "index": 1, + "linked_object": "dma_ack_out[0]", + "module": "O_BUFT", + "name": "$flatten$auto_535.$obuf$GJC48.$obuf_dma_ack_out" + }, + { + "connectivity": { + "I": "$flatten$auto_535.$obuf_dma_ack_out[1]", + "O": "$auto_535.dma_ack_out[1]", + "T": "$flatten$auto_535.$auto_531" + }, + "direction": "OUT", + "index": 1, + "linked_object": "dma_ack_out[1]", + "module": "O_BUFT", + "name": "$flatten$auto_535.$obuf$GJC48.$obuf_dma_ack_out_1" + }, + { + "connectivity": { + "I": "$flatten$auto_535.$obuf_dma_ack_out[2]", + "O": "$auto_535.dma_ack_out[2]", + "T": "$flatten$auto_535.$auto_532" + }, + "direction": "OUT", + "index": 1, + "linked_object": "dma_ack_out[2]", + "module": "O_BUFT", + "name": "$flatten$auto_535.$obuf$GJC48.$obuf_dma_ack_out_2" + }, + { + "connectivity": { + "I": "$flatten$auto_535.$obuf_dma_ack_out[3]", + "O": "$auto_535.dma_ack_out[3]", + "T": "$flatten$auto_535.$auto_533" + }, + "direction": "OUT", + "index": 1, + "linked_object": "dma_ack_out[3]", + "module": "O_BUFT", + "name": "$flatten$auto_535.$obuf$GJC48.$obuf_dma_ack_out_3" + }, + { + "connectivity": { + "I": "$auto_533", + "O": "$flatten$auto_535.$auto_533" + }, + "module": "WIRE", + "name": "wire0" + }, + { + "connectivity": { + "I": "$auto_532", + "O": "$flatten$auto_535.$auto_532" + }, + "module": "WIRE", + "name": "wire1" + }, + { + "connectivity": { + "I": "$auto_531", + "O": "$flatten$auto_535.$auto_531" + }, + "module": "WIRE", + "name": "wire2" + }, + { + "connectivity": { + "I": "$auto_530", + "O": "$flatten$auto_535.$auto_530" + }, + "module": "WIRE", + "name": "wire3" + }, + { + "connectivity": { + "I": "$auto_529", + "O": "$flatten$auto_535.$auto_529" + }, + "module": "WIRE", + "name": "wire4" + }, + { + "connectivity": { + "I": "$auto_528", + "O": "$flatten$auto_535.$auto_528" + }, + "module": "WIRE", + "name": "wire5" + }, + { + "connectivity": { + "I": "$auto_527", + "O": "$flatten$auto_535.$auto_527" + }, + "module": "WIRE", + "name": "wire6" + }, + { + "connectivity": { + "I": "$auto_526", + "O": "$flatten$auto_535.$auto_526" + }, + "module": "WIRE", + "name": "wire7" + }, + { + "connectivity": { + "I": "$auto_525", + "O": "$flatten$auto_535.$auto_525" + }, + "module": "WIRE", + "name": "wire8" + }, + { + "connectivity": { + "I": "$auto_524", + "O": "$flatten$auto_535.$auto_524" + }, + "module": "WIRE", + "name": "wire9" + }, + { + "connectivity": { + "I": "$flatten$auto_535.$clk_buf_$ibuf_clk", + "O": "$clk_buf_$ibuf_clk" + }, + "direction": "IN", + "index": 3, + "linked_object": "clk", + "module": "WIRE", + "name": "wire10" + }, + { + "connectivity": { + "I": "$flatten$auto_535.$ibuf_dma_req_in[0]", + "O": "$ibuf_dma_req_in[0]" + }, + "direction": "IN", + "index": 2, + "linked_object": "dma_req_in[0]", + "module": "WIRE", + "name": "wire11" + }, + { + "connectivity": { + "I": "$flatten$auto_535.$ibuf_dma_req_in[1]", + "O": "$ibuf_dma_req_in[1]" + }, + "direction": "IN", + "index": 2, + "linked_object": "dma_req_in[1]", + "module": "WIRE", + "name": "wire12" + }, + { + "connectivity": { + "I": "$flatten$auto_535.$ibuf_dma_req_in[2]", + "O": "$ibuf_dma_req_in[2]" + }, + "direction": "IN", + "index": 2, + "linked_object": "dma_req_in[2]", + "module": "WIRE", + "name": "wire13" + }, + { + "connectivity": { + "I": "$flatten$auto_535.$ibuf_dma_req_in[3]", + "O": "$ibuf_dma_req_in[3]" + }, + "direction": "IN", + "index": 2, + "linked_object": "dma_req_in[3]", + "module": "WIRE", + "name": "wire14" + }, + { + "connectivity": { + "I": "$flatten$auto_535.$ibuf_reset_n", + "O": "$ibuf_reset_n" + }, + "direction": "IN", + "index": 2, + "linked_object": "reset_n", + "module": "WIRE", + "name": "wire15" + }, + { + "connectivity": { + "I": "$obuf_dma_ack_out[0]", + "O": "$flatten$auto_535.$obuf_dma_ack_out[0]" + }, + "direction": "OUT", + "index": 2, + "linked_object": "dma_ack_out[0]", + "module": "WIRE", + "name": "wire16" + }, + { + "connectivity": { + "I": "$obuf_dma_ack_out[1]", + "O": "$flatten$auto_535.$obuf_dma_ack_out[1]" + }, + "direction": "OUT", + "index": 2, + "linked_object": "dma_ack_out[1]", + "module": "WIRE", + "name": "wire17" + }, + { + "connectivity": { + "I": "$obuf_dma_ack_out[2]", + "O": "$flatten$auto_535.$obuf_dma_ack_out[2]" + }, + "direction": "OUT", + "index": 2, + "linked_object": "dma_ack_out[2]", + "module": "WIRE", + "name": "wire18" + }, + { + "connectivity": { + "I": "$obuf_dma_ack_out[3]", + "O": "$flatten$auto_535.$obuf_dma_ack_out[3]" + }, + "direction": "OUT", + "index": 2, + "linked_object": "dma_ack_out[3]", + "module": "WIRE", + "name": "wire19" + }, + { + "connectivity": { + "I": "clk", + "O": "$auto_535.clk" + }, + "direction": "IN", + "index": 0, + "linked_object": "clk", + "module": "WIRE", + "name": "wire20" + }, + { + "connectivity": { + "I": "$auto_535.dma_ack_out[0]", + "O": "dma_ack_out[0]" + }, + "direction": "OUT", + "index": 0, + "linked_object": "dma_ack_out[0]", + "module": "WIRE", + "name": "wire21" + }, + { + "connectivity": { + "I": "$auto_535.dma_ack_out[1]", + "O": "dma_ack_out[1]" + }, + "direction": "OUT", + "index": 0, + "linked_object": "dma_ack_out[1]", + "module": "WIRE", + "name": "wire22" + }, + { + "connectivity": { + "I": "$auto_535.dma_ack_out[2]", + "O": "dma_ack_out[2]" + }, + "direction": "OUT", + "index": 0, + "linked_object": "dma_ack_out[2]", + "module": "WIRE", + "name": "wire23" + }, + { + "connectivity": { + "I": "$auto_535.dma_ack_out[3]", + "O": "dma_ack_out[3]" + }, + "direction": "OUT", + "index": 0, + "linked_object": "dma_ack_out[3]", + "module": "WIRE", + "name": "wire24" + }, + { + "connectivity": { + "I": "$auto_535.dma_ack_reg[0]", + "O": "dma_ack_reg[0]" + }, + "module": "WIRE", + "name": "wire25" + }, + { + "connectivity": { + "I": "$auto_535.dma_ack_reg[1]", + "O": "dma_ack_reg[1]" + }, + "module": "WIRE", + "name": "wire26" + }, + { + "connectivity": { + "I": "$auto_535.dma_ack_reg[2]", + "O": "dma_ack_reg[2]" + }, + "module": "WIRE", + "name": "wire27" + }, + { + "connectivity": { + "I": "$auto_535.dma_ack_reg[3]", + "O": "dma_ack_reg[3]" + }, + "module": "WIRE", + "name": "wire28" + }, + { + "connectivity": { + "I": "dma_req_in[0]", + "O": "$auto_535.dma_req_in[0]" + }, + "direction": "IN", + "index": 0, + "linked_object": "dma_req_in[0]", + "module": "WIRE", + "name": "wire29" + }, + { + "connectivity": { + "I": "dma_req_in[1]", + "O": "$auto_535.dma_req_in[1]" + }, + "direction": "IN", + "index": 0, + "linked_object": "dma_req_in[1]", + "module": "WIRE", + "name": "wire30" + }, + { + "connectivity": { + "I": "dma_req_in[2]", + "O": "$auto_535.dma_req_in[2]" + }, + "direction": "IN", + "index": 0, + "linked_object": "dma_req_in[2]", + "module": "WIRE", + "name": "wire31" + }, + { + "connectivity": { + "I": "dma_req_in[3]", + "O": "$auto_535.dma_req_in[3]" + }, + "direction": "IN", + "index": 0, + "linked_object": "dma_req_in[3]", + "module": "WIRE", + "name": "wire32" + }, + { + "connectivity": { + "I": "dma_req_reg[0]", + "O": "$auto_535.dma_req_reg[0]" + }, + "module": "WIRE", + "name": "wire33" + }, + { + "connectivity": { + "I": "dma_req_reg[1]", + "O": "$auto_535.dma_req_reg[1]" + }, + "module": "WIRE", + "name": "wire34" + }, + { + "connectivity": { + "I": "dma_req_reg[2]", + "O": "$auto_535.dma_req_reg[2]" + }, + "module": "WIRE", + "name": "wire35" + }, + { + "connectivity": { + "I": "dma_req_reg[3]", + "O": "$auto_535.dma_req_reg[3]" + }, + "module": "WIRE", + "name": "wire36" + }, + { + "connectivity": { + "I": "reset_n", + "O": "$auto_535.reset_n" + }, + "direction": "IN", + "index": 0, + "linked_object": "reset_n", + "module": "WIRE", + "name": "wire37" + } + ] +} diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/core_synthesis.v b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/core_synthesis.v new file mode 100644 index 00000000..7fc361bd --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/core_synthesis.v @@ -0,0 +1,159 @@ +/* Generated by Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) */ + +module GJC48(clk, reset_n, dma_req_in, dma_ack_out); + input clk; + output [3:0] dma_ack_out; + input [3:0] dma_req_in; + input reset_n; + wire _00_; + wire _01_; + wire _02_; + wire _03_; + wire _04_; + wire _05_; + wire _06_; + wire _07_; + wire _08_; + wire _09_; + wire _10_; + wire clk; + wire [3:0] dma_ack_out; + wire \dma_ack_reg[0] ; + wire \dma_ack_reg[1] ; + wire \dma_ack_reg[2] ; + wire \dma_ack_reg[3] ; + wire [3:0] dma_req_in; + wire \dma_req_reg[0] ; + wire \dma_req_reg[1] ; + wire \dma_req_reg[2] ; + wire \dma_req_reg[3] ; + wire reset_n; + DFFRE _11_ ( + .C(_00_), + .D(\dma_ack_reg[0] ), + .E(1'b1), + .Q(_07_), + .R(_06_) + ); + DFFRE _12_ ( + .C(_00_), + .D(\dma_ack_reg[1] ), + .E(1'b1), + .Q(_08_), + .R(_06_) + ); + DFFRE _13_ ( + .C(_00_), + .D(\dma_ack_reg[2] ), + .E(1'b1), + .Q(_09_), + .R(_06_) + ); + DFFRE _14_ ( + .C(_00_), + .D(\dma_ack_reg[3] ), + .E(1'b1), + .Q(_10_), + .R(_06_) + ); + DFFRE _15_ ( + .C(_00_), + .D(_02_), + .E(1'b1), + .Q(\dma_req_reg[0] ), + .R(_06_) + ); + DFFRE _16_ ( + .C(_00_), + .D(_03_), + .E(1'b1), + .Q(\dma_req_reg[1] ), + .R(_06_) + ); + DFFRE _17_ ( + .C(_00_), + .D(_04_), + .E(1'b1), + .Q(\dma_req_reg[2] ), + .R(_06_) + ); + DFFRE _18_ ( + .C(_00_), + .D(_05_), + .E(1'b1), + .Q(\dma_req_reg[3] ), + .R(_06_) + ); + CLK_BUF _19_ ( + .I(_01_), + .O(_00_) + ); + I_BUF #( + .WEAK_KEEPER("NONE") + ) _20_ ( + .EN(1'b1), + .I(clk), + .O(_01_) + ); + I_BUF #( + .WEAK_KEEPER("NONE") + ) _21_ ( + .EN(1'b1), + .I(dma_req_in[0]), + .O(_02_) + ); + I_BUF #( + .WEAK_KEEPER("NONE") + ) _22_ ( + .EN(1'b1), + .I(dma_req_in[1]), + .O(_03_) + ); + I_BUF #( + .WEAK_KEEPER("NONE") + ) _23_ ( + .EN(1'b1), + .I(dma_req_in[2]), + .O(_04_) + ); + I_BUF #( + .WEAK_KEEPER("NONE") + ) _24_ ( + .EN(1'b1), + .I(dma_req_in[3]), + .O(_05_) + ); + I_BUF #( + .WEAK_KEEPER("NONE") + ) _25_ ( + .EN(1'b1), + .I(reset_n), + .O(_06_) + ); + O_BUFT _26_ ( + .I(_07_), + .O(dma_ack_out[0]), + .T(1'b1) + ); + O_BUFT _27_ ( + .I(_08_), + .O(dma_ack_out[1]), + .T(1'b1) + ); + O_BUFT _28_ ( + .I(_09_), + .O(dma_ack_out[2]), + .T(1'b1) + ); + O_BUFT _29_ ( + .I(_10_), + .O(dma_ack_out[3]), + .T(1'b1) + ); + SOC_FPGA_INTF_DMA dma_inst ( + .DMA_ACK({ \dma_ack_reg[3] , \dma_ack_reg[2] , \dma_ack_reg[1] , \dma_ack_reg[0] }), + .DMA_CLK(_01_), + .DMA_REQ({ \dma_req_reg[3] , \dma_req_reg[2] , \dma_req_reg[1] , \dma_req_reg[0] }), + .DMA_RST_N(_06_) + ); +endmodule diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/design.rtlil b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/design.rtlil new file mode 100644 index 00000000..3b1f63cd --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/design.rtlil @@ -0,0 +1,1838 @@ +# Generated by Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) +autoidx 524 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:9.1-14.10" +module \BOOT_CLOCK + parameter \PERIOD 25 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:12.14-12.15" + wire output 1 \O +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:542.1-951.10" +module \BRAM2x18_SDP + parameter \CFG_ABITS 11 + parameter \CFG_DBITS 18 + parameter \CFG_ENABLE_B 2 + parameter \CFG_ENABLE_D 2 + parameter \CLKPOL2 1 + parameter \CLKPOL3 1 + parameter \INIT0 18432'x + parameter \INIT1 18432'x + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:563.27-563.33" + wire width 11 input 1 \A1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:564.28-564.34" + wire width 18 output 2 \A1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:565.11-565.15" + wire input 3 \A1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:567.27-567.33" + wire width 11 input 4 \B1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:570.30-570.34" + wire width 2 input 7 \B1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:568.27-568.33" + wire width 18 input 5 \B1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:569.11-569.15" + wire input 6 \B1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:572.27-572.33" + wire width 11 input 8 \C1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:573.28-573.34" + wire width 18 output 9 \C1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:574.11-574.15" + wire input 10 \C1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:560.11-560.15" + wire input 11 \CLK1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:561.11-561.15" + wire input 12 \CLK2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:576.27-576.33" + wire width 11 input 13 \D1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:579.30-579.34" + wire width 2 input 16 \D1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:577.27-577.33" + wire width 18 input 14 \D1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:578.11-578.15" + wire input 15 \D1EN +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:112.1-540.10" +module \BRAM2x18_TDP + parameter \CFG_ABITS 11 + parameter \CFG_DBITS 18 + parameter \CFG_ENABLE_B 2 + parameter \CFG_ENABLE_D 2 + parameter \CFG_ENABLE_F 2 + parameter \CFG_ENABLE_H 2 + parameter \CLKPOL2 1 + parameter \CLKPOL3 1 + parameter \INIT0 18432'x + parameter \INIT1 18432'x + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:137.27-137.33" + wire width 11 input 1 \A1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:138.28-138.34" + wire width 18 output 2 \A1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:139.11-139.15" + wire input 3 \A1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:141.27-141.33" + wire width 11 input 4 \B1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:144.30-144.34" + wire width 2 input 7 \B1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:142.27-142.33" + wire width 18 input 5 \B1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:143.11-143.15" + wire input 6 \B1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:146.27-146.33" + wire width 11 input 8 \C1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:147.28-147.34" + wire width 18 output 9 \C1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:148.11-148.15" + wire input 10 \C1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:132.11-132.15" + wire input 11 \CLK1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:133.11-133.15" + wire input 12 \CLK2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:134.11-134.15" + wire input 13 \CLK3 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:135.11-135.15" + wire input 14 \CLK4 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:150.27-150.33" + wire width 11 input 15 \D1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:153.30-153.34" + wire width 2 input 18 \D1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:151.27-151.33" + wire width 18 input 16 \D1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:152.11-152.15" + wire input 17 \D1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:155.27-155.33" + wire width 11 input 19 \E1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:156.28-156.34" + wire width 18 output 20 \E1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:157.11-157.15" + wire input 21 \E1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:159.27-159.33" + wire width 11 input 22 \F1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:162.30-162.34" + wire width 2 input 25 \F1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:160.27-160.33" + wire width 18 input 23 \F1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:161.11-161.15" + wire input 24 \F1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:164.27-164.33" + wire width 11 input 26 \G1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:165.28-165.34" + wire width 18 output 27 \G1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:166.11-166.15" + wire input 28 \G1EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:168.27-168.33" + wire width 11 input 29 \H1ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:171.30-171.34" + wire width 2 input 32 \H1BE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:169.27-169.33" + wire width 18 input 30 \H1DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:170.11-170.15" + wire input 31 \H1EN +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:24.1-31.10" +module \CARRY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:27.15-27.18" + wire input 3 \CIN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:29.16-29.20" + wire output 5 \COUT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:26.15-26.16" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:28.16-28.17" + wire output 4 \O + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:25.15-25.16" + wire input 1 \P +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:41.1-46.10" +module \CLK_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:42.15-42.16" + wire input 1 \I + attribute \clkbuf_driver 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:44.16-44.17" + wire output 2 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:56.1-64.10" +module \DFFNRE + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:61.15-61.16" + wire input 4 \C + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:57.15-57.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:59.15-59.16" + wire input 3 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:62.14-62.15" + wire output 5 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:58.15-58.16" + wire input 2 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:74.1-82.10" +module \DFFRE + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:79.15-79.16" + wire input 4 \C + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:75.15-75.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:77.15-77.16" + wire input 3 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:80.14-80.15" + wire output 5 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:76.15-76.16" + wire input 2 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:92.1-126.10" +module \DSP19X2 + parameter \DSP_MODE "MULTIPLY_ACCUMULATE" + parameter \COEFF1_0 10'0000000000 + parameter \COEFF1_1 10'0000000000 + parameter \COEFF1_2 10'0000000000 + parameter \COEFF1_3 10'0000000000 + parameter \COEFF2_0 10'0000000000 + parameter \COEFF2_1 10'0000000000 + parameter \COEFF2_2 10'0000000000 + parameter \COEFF2_3 10'0000000000 + parameter \OUTPUT_REG_EN "TRUE" + parameter \INPUT_REG_EN "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:105.21-105.23" + wire width 10 input 1 \A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:109.21-109.23" + wire width 10 input 5 \A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:116.21-116.28" + wire width 5 input 11 \ACC_FIR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:106.21-106.23" + wire width 9 input 2 \B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:110.21-110.23" + wire width 9 input 6 \B2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:114.15-114.18" + wire input 9 \CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:108.22-108.28" + wire width 9 output 4 \DLY_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:112.22-112.28" + wire width 9 output 8 \DLY_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:117.21-117.29" + wire width 3 input 12 \FEEDBACK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:118.15-118.23" + wire input 13 \LOAD_ACC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:115.15-115.20" + wire input 10 \RESET + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:123.15-123.20" + wire input 18 \ROUND + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:121.15-121.23" + wire input 16 \SATURATE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:122.21-122.32" + wire width 5 input 17 \SHIFT_RIGHT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:124.15-124.23" + wire input 19 \SUBTRACT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:119.15-119.25" + wire input 14 \UNSIGNED_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:120.15-120.25" + wire input 15 \UNSIGNED_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:107.23-107.25" + wire width 19 output 3 \Z1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:111.23-111.25" + wire width 19 output 7 \Z2 +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:136.1-162.10" +module \DSP38 + parameter \DSP_MODE "MULTIPLY_ACCUMULATE" + parameter \COEFF_0 20'00000000000000000000 + parameter \COEFF_1 20'00000000000000000000 + parameter \COEFF_2 20'00000000000000000000 + parameter \COEFF_3 20'00000000000000000000 + parameter \OUTPUT_REG_EN "TRUE" + parameter \INPUT_REG_EN "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:145.22-145.23" + wire width 20 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:147.21-147.28" + wire width 6 input 3 \ACC_FIR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:146.22-146.23" + wire width 18 input 2 \B + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:151.15-151.18" + wire input 6 \CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:149.21-149.26" + wire width 18 output 5 \DLY_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:153.21-153.29" + wire width 3 input 8 \FEEDBACK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:154.15-154.23" + wire input 9 \LOAD_ACC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:152.15-152.20" + wire input 7 \RESET + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:157.15-157.20" + wire input 12 \ROUND + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:155.15-155.23" + wire input 10 \SATURATE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:156.21-156.32" + wire width 6 input 11 \SHIFT_RIGHT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:158.15-158.23" + wire input 13 \SUBTRACT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:159.15-159.25" + wire input 14 \UNSIGNED_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:160.15-160.25" + wire input 15 \UNSIGNED_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:148.23-148.24" + wire width 38 output 4 \Z +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:172.1-176.10" +module \FCLK_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:173.15-173.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:174.16-174.17" + wire output 2 \O +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:186.1-233.10" +module \FIFO18KX2 + parameter \DATA_WRITE_WIDTH1 18 + parameter \DATA_READ_WIDTH1 18 + parameter \FIFO_TYPE1 "SYNCHRONOUS" + parameter \PROG_EMPTY_THRESH1 11'00000000100 + parameter \PROG_FULL_THRESH1 11'11111111010 + parameter \DATA_WRITE_WIDTH2 18 + parameter \DATA_READ_WIDTH2 18 + parameter \FIFO_TYPE2 "SYNCHRONOUS" + parameter \PROG_EMPTY_THRESH2 11'00000000100 + parameter \PROG_FULL_THRESH2 11'11111111010 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:209.14-209.27" + wire output 10 \ALMOST_EMPTY1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:226.14-226.27" + wire output 25 \ALMOST_EMPTY2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:210.14-210.26" + wire output 11 \ALMOST_FULL1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:227.14-227.26" + wire output 26 \ALMOST_FULL2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:207.14-207.20" + wire output 8 \EMPTY1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:224.14-224.20" + wire output 23 \EMPTY2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:208.14-208.19" + wire output 9 \FULL1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:225.14-225.19" + wire output 24 \FULL2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:213.14-213.23" + wire output 14 \OVERFLOW1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:230.14-230.23" + wire output 29 \OVERFLOW2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:211.14-211.25" + wire output 12 \PROG_EMPTY1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:228.14-228.25" + wire output 27 \PROG_EMPTY2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:212.14-212.24" + wire output 13 \PROG_FULL1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:229.14-229.24" + wire output 28 \PROG_FULL2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:202.15-202.22" + wire input 3 \RD_CLK1 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:219.15-219.22" + wire input 18 \RD_CLK2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:206.39-206.47" + wire width 18 output 7 \RD_DATA1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:223.39-223.47" + wire width 18 output 22 \RD_DATA2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:204.15-204.21" + wire input 5 \RD_EN1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:221.15-221.21" + wire input 20 \RD_EN2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:198.15-198.21" + wire input 1 \RESET1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:215.15-215.21" + wire input 16 \RESET2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:214.14-214.24" + wire output 15 \UNDERFLOW1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:231.14-231.24" + wire output 30 \UNDERFLOW2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:200.15-200.22" + wire input 2 \WR_CLK1 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:217.15-217.22" + wire input 17 \WR_CLK2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:205.39-205.47" + wire width 18 input 6 \WR_DATA1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:222.39-222.47" + wire width 18 input 21 \WR_DATA2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:203.15-203.21" + wire input 4 \WR_EN1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:220.15-220.21" + wire input 19 \WR_EN2 +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:243.1-268.10" +module \FIFO36K + parameter \DATA_WRITE_WIDTH 36 + parameter \DATA_READ_WIDTH 36 + parameter \FIFO_TYPE "SYNCHRONOUS" + parameter \PROG_EMPTY_THRESH 12'000000000100 + parameter \PROG_FULL_THRESH 12'111111111010 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:261.14-261.26" + wire output 10 \ALMOST_EMPTY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:262.14-262.25" + wire output 11 \ALMOST_FULL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:259.14-259.19" + wire output 8 \EMPTY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:260.14-260.18" + wire output 9 \FULL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:265.14-265.22" + wire output 14 \OVERFLOW + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:263.14-263.24" + wire output 12 \PROG_EMPTY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:264.14-264.23" + wire output 13 \PROG_FULL + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:254.15-254.21" + wire input 3 \RD_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:258.38-258.45" + wire width 36 output 7 \RD_DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:256.15-256.20" + wire input 5 \RD_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:250.15-250.20" + wire input 1 \RESET + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:266.14-266.23" + wire output 15 \UNDERFLOW + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:252.15-252.21" + wire input 2 \WR_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:257.38-257.45" + wire width 36 input 6 \WR_DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:255.15-255.20" + wire input 4 \WR_EN +end +attribute \top 1 +attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:1.1-38.10" +module \GJC48 + wire $clk_buf_$ibuf_clk + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" + wire $ibuf_clk + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" + wire $ibuf_dma_req_in[0] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" + wire offset 1 $ibuf_dma_req_in[1] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" + wire offset 2 $ibuf_dma_req_in[2] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" + wire offset 3 $ibuf_dma_req_in[3] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" + wire $ibuf_reset_n + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" + wire $obuf_dma_ack_out[0] + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" + wire offset 1 $obuf_dma_ack_out[1] + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" + wire offset 2 $obuf_dma_ack_out[2] + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" + wire offset 3 $obuf_dma_ack_out[3] + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" + wire input 1 \clk + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" + wire width 4 output 4 \dma_ack_out + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" + wire \dma_ack_reg[0] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" + wire offset 1 \dma_ack_reg[1] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" + wire offset 2 \dma_ack_reg[2] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" + wire offset 3 \dma_ack_reg[3] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" + wire width 4 input 3 \dma_req_in + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" + wire \dma_req_reg[0] + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" + wire offset 1 \dma_req_reg[1] + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" + wire offset 2 \dma_req_reg[2] + attribute \keep 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" + wire offset 3 \dma_req_reg[3] + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" + wire input 2 \reset_n + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" + cell \DFFRE $abc$267$auto_268 + connect \C $clk_buf_$ibuf_clk + connect \D \dma_ack_reg[0] + connect \E 1'1 + connect \Q $obuf_dma_ack_out[0] + connect \R $ibuf_reset_n + end + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" + cell \DFFRE $abc$267$auto_269 + connect \C $clk_buf_$ibuf_clk + connect \D \dma_ack_reg[1] + connect \E 1'1 + connect \Q $obuf_dma_ack_out[1] + connect \R $ibuf_reset_n + end + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" + cell \DFFRE $abc$267$auto_270 + connect \C $clk_buf_$ibuf_clk + connect \D \dma_ack_reg[2] + connect \E 1'1 + connect \Q $obuf_dma_ack_out[2] + connect \R $ibuf_reset_n + end + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" + cell \DFFRE $abc$267$auto_271 + connect \C $clk_buf_$ibuf_clk + connect \D \dma_ack_reg[3] + connect \E 1'1 + connect \Q $obuf_dma_ack_out[3] + connect \R $ibuf_reset_n + end + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" + cell \DFFRE $abc$267$auto_272 + connect \C $clk_buf_$ibuf_clk + connect \D $ibuf_dma_req_in[0] + connect \E 1'1 + connect \Q \dma_req_reg[0] + connect \R $ibuf_reset_n + end + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" + cell \DFFRE $abc$267$auto_273 + connect \C $clk_buf_$ibuf_clk + connect \D $ibuf_dma_req_in[1] + connect \E 1'1 + connect \Q \dma_req_reg[1] + connect \R $ibuf_reset_n + end + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" + cell \DFFRE $abc$267$auto_274 + connect \C $clk_buf_$ibuf_clk + connect \D $ibuf_dma_req_in[2] + connect \E 1'1 + connect \Q \dma_req_reg[2] + connect \R $ibuf_reset_n + end + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" + cell \DFFRE $abc$267$auto_275 + connect \C $clk_buf_$ibuf_clk + connect \D $ibuf_dma_req_in[3] + connect \E 1'1 + connect \Q \dma_req_reg[3] + connect \R $ibuf_reset_n + end + attribute \keep 1 + cell \CLK_BUF $clkbuf$GJC48.$ibuf_clk + connect \I $ibuf_clk + connect \O $clk_buf_$ibuf_clk + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" + cell \I_BUF $ibuf$GJC48.$ibuf_clk + parameter \WEAK_KEEPER "NONE" + connect \EN 1'1 + connect \I \clk + connect \O $ibuf_clk + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" + cell \I_BUF $ibuf$GJC48.$ibuf_dma_req_in + parameter \WEAK_KEEPER "NONE" + connect \EN 1'1 + connect \I \dma_req_in [0] + connect \O $ibuf_dma_req_in[0] + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" + cell \I_BUF $ibuf$GJC48.$ibuf_dma_req_in_1 + parameter \WEAK_KEEPER "NONE" + connect \EN 1'1 + connect \I \dma_req_in [1] + connect \O $ibuf_dma_req_in[1] + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" + cell \I_BUF $ibuf$GJC48.$ibuf_dma_req_in_2 + parameter \WEAK_KEEPER "NONE" + connect \EN 1'1 + connect \I \dma_req_in [2] + connect \O $ibuf_dma_req_in[2] + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" + cell \I_BUF $ibuf$GJC48.$ibuf_dma_req_in_3 + parameter \WEAK_KEEPER "NONE" + connect \EN 1'1 + connect \I \dma_req_in [3] + connect \O $ibuf_dma_req_in[3] + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" + cell \I_BUF $ibuf$GJC48.$ibuf_reset_n + parameter \WEAK_KEEPER "NONE" + connect \EN 1'1 + connect \I \reset_n + connect \O $ibuf_reset_n + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" + cell \O_BUFT $obuf$GJC48.$obuf_dma_ack_out + connect \I $obuf_dma_ack_out[0] + connect \O \dma_ack_out [0] + connect \T 1'1 + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" + cell \O_BUFT $obuf$GJC48.$obuf_dma_ack_out_1 + connect \I $obuf_dma_ack_out[1] + connect \O \dma_ack_out [1] + connect \T 1'1 + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" + cell \O_BUFT $obuf$GJC48.$obuf_dma_ack_out_2 + connect \I $obuf_dma_ack_out[2] + connect \O \dma_ack_out [2] + connect \T 1'1 + end + attribute \keep 1 + attribute \module_not_derived 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" + cell \O_BUFT $obuf$GJC48.$obuf_dma_ack_out_3 + connect \I $obuf_dma_ack_out[3] + connect \O \dma_ack_out [3] + connect \T 1'1 + end + attribute \module_not_derived 1 + attribute \src "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:12.21-17.4" + cell \SOC_FPGA_INTF_DMA \dma_inst + connect \DMA_ACK { \dma_ack_reg[3] \dma_ack_reg[2] \dma_ack_reg[1] \dma_ack_reg[0] } + connect \DMA_CLK $ibuf_clk + connect \DMA_REQ { \dma_req_reg[3] \dma_req_reg[2] \dma_req_reg[1] \dma_req_reg[0] } + connect \DMA_RST_N $ibuf_reset_n + end +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:300.1-309.10" +module \I_BUF + parameter \WEAK_KEEPER "NONE" + parameter \IOSTANDARD "DEFAULT" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:306.15-306.17" + wire input 2 \EN + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:305.15-305.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:307.16-307.17" + wire output 3 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:278.1-290.10" +module \I_BUF_DS + parameter \WEAK_KEEPER "NONE" + parameter \IOSTANDARD "DEFAULT" + parameter \DIFFERENTIAL_TERMINATION "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:287.15-287.17" + wire input 3 \EN + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:286.15-286.18" + wire input 2 \I_N + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:284.15-284.18" + wire input 1 \I_P + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:288.14-288.15" + wire output 4 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:319.1-327.10" +module \I_DDR + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:324.15-324.16" + wire input 4 \C + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:320.15-320.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:322.15-322.16" + wire input 3 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:325.20-325.21" + wire width 2 output 5 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:321.15-321.16" + wire input 2 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:337.1-349.10" +module \I_DELAY + parameter \DELAY 0 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:346.15-346.21" + wire input 6 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:342.15-342.22" + wire input 3 \DLY_ADJ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:343.15-343.25" + wire input 4 \DLY_INCDEC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:341.15-341.23" + wire input 2 \DLY_LOAD + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:344.22-344.35" + wire width 6 output 5 \DLY_TAP_VALUE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:340.15-340.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:347.16-347.17" + wire output 7 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:359.1-363.10" +module \I_FAB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:360.15-360.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:361.16-361.17" + wire output 2 \O +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:373.1-392.10" +module \I_SERDES + parameter \DATA_RATE "SDR" + parameter \WIDTH 4 + parameter \DPA_MODE "NONE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:380.15-380.26" + wire input 3 \BITSLIP_ADJ + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:383.15-383.21" + wire input 5 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:384.16-384.23" + wire output 6 \CLK_OUT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:378.15-378.16" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:386.16-386.26" + wire output 8 \DATA_VALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:388.16-388.25" + wire output 10 \DPA_ERROR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:387.16-387.24" + wire output 9 \DPA_LOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:381.15-381.17" + wire input 4 \EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:390.15-390.22" + wire input 12 \PLL_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:389.15-389.23" + wire input 11 \PLL_LOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:385.28-385.29" + wire width 4 output 7 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:379.15-379.18" + wire input 2 \RST +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1040.1-1045.10" +module \LATCH + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1041.9-1041.10" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1042.9-1042.10" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1043.10-1043.11" + wire output 3 \Q +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1053.1-1058.10" +module \LATCHN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1054.9-1054.10" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1055.9-1055.10" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1056.10-1056.11" + wire output 3 \Q +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1096.1-1102.10" +module \LATCHNR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1097.9-1097.10" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1098.9-1098.10" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1099.10-1099.11" + wire output 4 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1100.9-1100.10" + wire input 3 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1111.1-1117.10" +module \LATCHNS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1112.9-1112.10" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1113.9-1113.10" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1114.10-1114.11" + wire output 4 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1115.9-1115.10" + wire input 3 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:265.1-285.10" +module \LATCHNSRE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:266.9-266.10" + wire input 4 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:267.9-267.10" + wire input 6 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:268.9-268.10" + wire input 5 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:269.10-269.11" + wire output 1 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:270.9-270.10" + wire input 3 \R + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:271.9-271.10" + wire input 2 \S +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1067.1-1073.10" +module \LATCHR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1068.9-1068.10" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1069.9-1069.10" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1070.10-1070.11" + wire output 4 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1071.9-1071.10" + wire input 3 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1081.1-1087.10" +module \LATCHS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1082.9-1082.10" + wire input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1083.9-1083.10" + wire input 2 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1084.10-1084.11" + wire output 4 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1085.9-1085.10" + wire input 3 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:223.1-243.10" +module \LATCHSRE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:224.9-224.10" + wire input 4 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:225.9-225.10" + wire input 6 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:226.9-226.10" + wire input 5 \G + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:227.10-227.11" + wire output 1 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:228.9-228.10" + wire input 3 \R + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:229.9-229.10" + wire input 2 \S +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:402.1-408.10" +module \LUT1 + parameter \INIT_VALUE 2'00 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:405.15-405.16" + wire input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:406.16-406.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:418.1-424.10" +module \LUT2 + parameter \INIT_VALUE 4'0000 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:421.21-421.22" + wire width 2 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:422.16-422.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:434.1-440.10" +module \LUT3 + parameter \INIT_VALUE 8'00000000 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:437.21-437.22" + wire width 3 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:438.16-438.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:450.1-456.10" +module \LUT4 + parameter \INIT_VALUE 16'0000000000000000 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:453.21-453.22" + wire width 4 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:454.16-454.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:466.1-472.10" +module \LUT5 + parameter \INIT_VALUE 0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:469.21-469.22" + wire width 5 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:470.16-470.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:482.1-488.10" +module \LUT6 + parameter \INIT_VALUE 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:485.21-485.22" + wire width 6 input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:486.16-486.17" + wire output 2 \Y +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:563.1-574.10" +module \O_BUF + parameter \IOSTANDARD "DEFAULT" + parameter \DRIVE_STRENGTH 2 + parameter \SLEW_RATE "SLOW" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:570.15-570.16" + wire input 1 \I + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:572.16-572.17" + wire output 2 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:542.1-553.10" +module \O_BUFT + parameter \WEAK_KEEPER "NONE" + parameter \IOSTANDARD "DEFAULT" + parameter \DRIVE_STRENGTH 2 + parameter \SLEW_RATE "SLOW" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:548.15-548.16" + wire input 1 \I + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:551.16-551.17" + wire output 3 \O + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:549.15-549.16" + wire input 2 \T +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:520.1-532.10" +module \O_BUFT_DS + parameter \WEAK_KEEPER "NONE" + parameter \IOSTANDARD "DEFAULT" + parameter \DIFFERENTIAL_TERMINATION "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:525.15-525.16" + wire input 1 \I + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:530.16-530.19" + wire output 4 \O_N + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:528.16-528.19" + wire output 3 \O_P + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:526.15-526.16" + wire input 2 \T +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:498.1-510.10" +module \O_BUF_DS + parameter \IOSTANDARD "DEFAULT" + parameter \DIFFERENTIAL_TERMINATION "TRUE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:504.15-504.16" + wire input 1 \I + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:508.16-508.19" + wire output 3 \O_N + attribute \iopad_external_pin 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:506.16-506.19" + wire output 2 \O_P +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:584.1-592.10" +module \O_DDR + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:589.15-589.16" + wire input 4 \C + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:585.21-585.22" + wire width 2 input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:587.15-587.16" + wire input 3 \E + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:590.14-590.15" + wire output 5 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:586.15-586.16" + wire input 2 \R +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:602.1-614.10" +module \O_DELAY + parameter \DELAY 0 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:611.15-611.21" + wire input 6 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:607.15-607.22" + wire input 3 \DLY_ADJ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:608.15-608.25" + wire input 4 \DLY_INCDEC + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:606.15-606.23" + wire input 2 \DLY_LOAD + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:609.22-609.35" + wire width 6 output 5 \DLY_TAP_VALUE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:605.15-605.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:612.16-612.17" + wire output 7 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:624.1-628.10" +module \O_FAB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:625.15-625.16" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:626.16-626.17" + wire output 2 \O +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:657.1-674.10" +module \O_SERDES + parameter \DATA_RATE "SDR" + parameter \WIDTH 4 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:669.15-669.35" + wire input 8 \CHANNEL_BOND_SYNC_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:670.16-670.37" + wire output 9 \CHANNEL_BOND_SYNC_OUT + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:665.15-665.21" + wire input 4 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:661.27-661.28" + wire width 4 input 1 \D + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:663.15-663.25" + wire input 3 \DATA_VALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:666.15-666.20" + wire input 5 \OE_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:667.16-667.22" + wire output 6 \OE_OUT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:672.15-672.22" + wire input 11 \PLL_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:671.15-671.23" + wire input 10 \PLL_LOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:668.16-668.17" + wire output 7 \Q + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:662.15-662.18" + wire input 2 \RST +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:638.1-647.10" +module \O_SERDES_CLK + parameter \DATA_RATE "SDR" + parameter \CLOCK_PHASE 0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:642.15-642.21" + wire input 1 \CLK_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:643.14-643.24" + wire output 2 \OUTPUT_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:645.15-645.22" + wire input 4 \PLL_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:644.15-644.23" + wire input 3 \PLL_LOCK +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:684.1-702.10" +module \PLL + parameter \DEV_FAMILY "VIRGO" + parameter \DIVIDE_CLK_IN_BY_2 "FALSE" + parameter \PLL_MULT 16 + parameter \PLL_DIV 1 + parameter \PLL_MULT_FRAC 0 + parameter \PLL_POST_DIV 17 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:694.15-694.21" + wire input 2 \CLK_IN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:695.16-695.23" + wire output 3 \CLK_OUT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:696.16-696.28" + wire output 4 \CLK_OUT_DIV2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:697.16-697.28" + wire output 5 \CLK_OUT_DIV3 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:698.16-698.28" + wire output 6 \CLK_OUT_DIV4 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:699.16-699.24" + wire output 7 \FAST_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:700.16-700.20" + wire output 8 \LOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:692.15-692.21" + wire input 1 \PLL_EN +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:89.1-111.10" +module \RS_DSP3 + parameter \MODE_BITS 93'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \DSP_CLK "" + parameter \DSP_RST "" + parameter \DSP_RST_POL "" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:90.24-90.25" + wire width 20 input 1 \a + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:92.24-92.31" + wire width 6 input 3 \acc_fir + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:91.24-91.25" + wire width 18 input 2 \b + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:97.23-97.26" + wire input 6 \clk + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:94.24-94.29" + wire width 18 output 5 \dly_b + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:100.23-100.31" + wire width 3 input 8 \feedback + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:101.23-101.31" + wire input 9 \load_acc + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:98.23-98.28" + wire input 7 \reset + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:104.23-104.31" + wire input 12 \subtract + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:102.23-102.33" + wire input 10 \unsigned_a + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:103.23-103.33" + wire input 11 \unsigned_b + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:93.24-93.25" + wire width 38 output 4 \z +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:712.1-726.10" +module \SOC_FPGA_INTF_AHB_M + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:714.22-714.27" + wire width 32 input 2 \HADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:715.21-715.27" + wire width 3 input 3 \HBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:724.15-724.19" + wire input 12 \HCLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:716.21-716.26" + wire width 4 input 4 \HPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:721.23-721.29" + wire width 32 output 9 \HRDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:722.16-722.22" + wire output 10 \HREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:713.15-713.24" + wire input 1 \HRESETN_I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:723.16-723.21" + wire output 11 \HRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:717.21-717.26" + wire width 3 input 5 \HSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:718.21-718.27" + wire width 3 input 6 \HTRANS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:719.22-719.28" + wire width 32 input 7 \HWDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:720.15-720.22" + wire input 8 \HWWRITE +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:736.1-753.10" +module \SOC_FPGA_INTF_AHB_S + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:738.23-738.28" + wire width 32 output 2 \HADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:739.22-739.28" + wire width 3 output 3 \HBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:751.15-751.19" + wire input 15 \HCLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:740.16-740.25" + wire output 4 \HMASTLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:742.22-742.27" + wire width 4 output 6 \HPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:743.22-743.28" + wire width 32 input 7 \HRDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:741.15-741.21" + wire input 5 \HREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:737.16-737.25" + wire output 1 \HRESETN_I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:744.15-744.20" + wire input 8 \HRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:745.16-745.20" + wire output 9 \HSEL + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:746.22-746.27" + wire width 3 output 10 \HSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:747.22-747.28" + wire width 2 output 11 \HTRANS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:748.22-748.26" + wire width 4 output 12 \HWBE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:749.23-749.29" + wire width 32 output 13 \HWDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:750.16-750.22" + wire output 14 \HWRITE +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:763.1-802.10" +module \SOC_FPGA_INTF_AXI_M0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:799.15-799.22" + wire input 36 \M0_ACLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:764.22-764.31" + wire width 32 input 1 \M0_ARADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:765.21-765.31" + wire width 2 input 2 \M0_ARBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:766.21-766.31" + wire width 4 input 3 \M0_ARCACHE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:800.16-800.28" + wire output 37 \M0_ARESETN_I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:767.21-767.28" + wire width 4 input 4 \M0_ARID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:768.21-768.29" + wire width 3 input 5 \M0_ARLEN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:769.15-769.24" + wire input 6 \M0_ARLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:770.21-770.30" + wire width 3 input 7 \M0_ARPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:771.16-771.26" + wire output 8 \M0_ARREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:772.21-772.30" + wire width 3 input 9 \M0_ARSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:773.15-773.25" + wire input 10 \M0_ARVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:774.22-774.31" + wire width 32 input 11 \M0_AWADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:775.21-775.31" + wire width 2 input 12 \M0_AWBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:776.21-776.31" + wire width 4 input 13 \M0_AWCACHE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:777.21-777.28" + wire width 4 input 14 \M0_AWID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:778.21-778.29" + wire width 3 input 15 \M0_AWLEN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:779.15-779.24" + wire input 16 \M0_AWLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:780.21-780.30" + wire width 3 input 17 \M0_AWPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:781.16-781.26" + wire output 18 \M0_AWREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:782.21-782.30" + wire width 3 input 19 \M0_AWSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:783.15-783.25" + wire input 20 \M0_AWVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:784.22-784.28" + wire width 4 output 21 \M0_BID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:785.15-785.24" + wire input 22 \M0_BREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:786.22-786.30" + wire width 2 output 23 \M0_BRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:787.16-787.25" + wire output 24 \M0_BVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:788.23-788.31" + wire width 64 output 25 \M0_RDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:789.22-789.28" + wire width 4 output 26 \M0_RID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:790.16-790.24" + wire output 27 \M0_RLAST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:791.15-791.24" + wire input 28 \M0_RREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:792.22-792.30" + wire width 2 output 29 \M0_RRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:793.16-793.25" + wire output 30 \M0_RVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:794.22-794.30" + wire width 64 input 31 \M0_WDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:795.15-795.23" + wire input 32 \M0_WLAST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:796.16-796.25" + wire output 33 \M0_WREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:797.21-797.29" + wire width 8 input 34 \M0_WSTRB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:798.15-798.24" + wire input 35 \M0_WVALID +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:812.1-851.10" +module \SOC_FPGA_INTF_AXI_M1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:848.15-848.22" + wire input 36 \M1_ACLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:813.22-813.31" + wire width 32 input 1 \M1_ARADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:814.21-814.31" + wire width 2 input 2 \M1_ARBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:815.21-815.31" + wire width 4 input 3 \M1_ARCACHE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:849.16-849.28" + wire output 37 \M1_ARESETN_I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:816.21-816.28" + wire width 4 input 4 \M1_ARID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:817.21-817.29" + wire width 3 input 5 \M1_ARLEN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:818.15-818.24" + wire input 6 \M1_ARLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:819.21-819.30" + wire width 3 input 7 \M1_ARPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:820.16-820.26" + wire output 8 \M1_ARREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:821.21-821.30" + wire width 3 input 9 \M1_ARSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:822.15-822.25" + wire input 10 \M1_ARVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:823.22-823.31" + wire width 32 input 11 \M1_AWADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:824.21-824.31" + wire width 2 input 12 \M1_AWBURST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:825.21-825.31" + wire width 4 input 13 \M1_AWCACHE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:826.21-826.28" + wire width 4 input 14 \M1_AWID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:827.21-827.29" + wire width 3 input 15 \M1_AWLEN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:828.15-828.24" + wire input 16 \M1_AWLOCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:829.21-829.30" + wire width 3 input 17 \M1_AWPROT + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:830.16-830.26" + wire output 18 \M1_AWREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:831.21-831.30" + wire width 3 input 19 \M1_AWSIZE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:832.15-832.25" + wire input 20 \M1_AWVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:833.22-833.28" + wire width 4 output 21 \M1_BID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:834.15-834.24" + wire input 22 \M1_BREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:835.22-835.30" + wire width 2 output 23 \M1_BRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:836.16-836.25" + wire output 24 \M1_BVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:837.23-837.31" + wire width 64 output 25 \M1_RDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:838.22-838.28" + wire width 4 output 26 \M1_RID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:839.16-839.24" + wire output 27 \M1_RLAST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:840.15-840.24" + wire input 28 \M1_RREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:841.22-841.30" + wire width 2 output 29 \M1_RRESP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:842.16-842.25" + wire output 30 \M1_RVALID + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:843.22-843.30" + wire width 64 input 31 \M1_WDATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:844.15-844.23" + wire input 32 \M1_WLAST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:845.16-845.25" + wire output 33 \M1_WREADY + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:846.21-846.29" + wire width 8 input 34 \M1_WSTRB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:847.15-847.24" + wire input 35 \M1_WVALID +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:861.1-867.10" +module \SOC_FPGA_INTF_DMA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:863.22-863.29" + wire width 4 output 2 \DMA_ACK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:864.15-864.22" + wire input 3 \DMA_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:862.21-862.28" + wire width 4 input 1 \DMA_REQ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:865.15-865.24" + wire input 4 \DMA_RST_N +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:877.1-883.10" +module \SOC_FPGA_INTF_IRQ + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:880.15-880.22" + wire input 3 \IRQ_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:881.15-881.24" + wire input 4 \IRQ_RST_N + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:879.23-879.30" + wire width 16 output 2 \IRQ_SET + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:878.22-878.29" + wire width 16 input 1 \IRQ_SRC +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:893.1-901.10" +module \SOC_FPGA_INTF_JTAG + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:899.15-899.27" + wire input 6 \BOOT_JTAG_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:894.15-894.28" + wire input 1 \BOOT_JTAG_TCK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:895.14-895.27" + wire output 2 \BOOT_JTAG_TDI + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:896.15-896.28" + wire input 3 \BOOT_JTAG_TDO + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:897.14-897.27" + wire output 4 \BOOT_JTAG_TMS + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:898.14-898.29" + wire output 5 \BOOT_JTAG_TRSTN +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:911.1-919.10" +module \SOC_FPGA_TEMPERATURE + parameter \INITIAL_TEMPERATURE 25 + parameter \TEMPERATURE_FILE "" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:917.14-917.19" + wire output 3 \ERROR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:915.20-915.31" + wire width 8 output 1 \TEMPERATURE + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:916.14-916.19" + wire output 2 \VALID +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:7.1-110.10" +module \TDP_BRAM18 + parameter \INITP_00 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_01 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_02 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_03 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_04 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_05 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_06 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INITP_07 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_00 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_01 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_02 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_03 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_04 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_05 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_06 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_07 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_08 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_09 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0B 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0C 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0D 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0E 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_0F 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_10 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_11 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_12 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_13 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_14 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_15 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_16 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_17 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_18 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_19 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1B 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1C 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1D 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1E 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_1F 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_20 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_21 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_22 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_23 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_24 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_25 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_26 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_27 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_28 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_29 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2B 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2C 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2D 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2E 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_2F 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_30 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_31 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_32 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_33 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_34 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_35 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_36 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_37 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_38 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_39 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3B 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3C 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3D 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3E 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_3F 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \READ_WIDTH_A 0 + parameter \READ_WIDTH_B 0 + parameter \WRITE_WIDTH_A 0 + parameter \WRITE_WIDTH_B 0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:14.23-14.28" + wire width 14 input 5 \ADDRA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:15.23-15.28" + wire width 14 input 6 \ADDRB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:22.22-22.33" + wire width 2 input 13 \BYTEENABLEA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:23.22-23.33" + wire width 2 input 14 \BYTEENABLEB + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:9.16-9.22" + wire input 1 \CLOCKA + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:11.16-11.22" + wire input 2 \CLOCKB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:28.24-28.33" + wire width 16 output 15 \READDATAA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:30.23-30.33" + wire width 2 output 17 \READDATAAP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:29.24-29.33" + wire width 16 output 16 \READDATAB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:31.23-31.33" + wire width 2 output 18 \READDATABP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:12.16-12.27" + wire input 3 \READENABLEA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:13.16-13.27" + wire input 4 \READENABLEB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:16.23-16.33" + wire width 16 input 7 \WRITEDATAA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:18.22-18.33" + wire width 2 input 9 \WRITEDATAAP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:17.23-17.33" + wire width 16 input 8 \WRITEDATAB + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:19.22-19.33" + wire width 2 input 10 \WRITEDATABP + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:20.16-20.28" + wire input 11 \WRITEENABLEA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:21.16-21.28" + wire input 12 \WRITEENABLEB +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:929.1-984.10" +module \TDP_RAM18KX2 + parameter \INIT1 16384'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT1_PARITY 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \WRITE_WIDTH_A1 18 + parameter \WRITE_WIDTH_B1 18 + parameter \READ_WIDTH_A1 18 + parameter \READ_WIDTH_B1 18 + parameter \INIT2 16384'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT2_PARITY 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \WRITE_WIDTH_A2 18 + parameter \WRITE_WIDTH_B2 18 + parameter \READ_WIDTH_A2 18 + parameter \READ_WIDTH_B2 18 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:953.22-953.29" + wire width 14 input 9 \ADDR_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:973.22-973.29" + wire width 14 input 27 \ADDR_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:954.22-954.29" + wire width 14 input 10 \ADDR_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:974.22-974.29" + wire width 14 input 28 \ADDR_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:951.21-951.26" + wire width 2 input 7 \BE_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:971.21-971.26" + wire width 2 input 25 \BE_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:952.21-952.26" + wire width 2 input 8 \BE_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:972.21-972.26" + wire width 2 input 26 \BE_B2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:948.15-948.21" + wire input 5 \CLK_A1 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:968.15-968.21" + wire input 23 \CLK_A2 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:950.15-950.21" + wire input 6 \CLK_B1 + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:970.15-970.21" + wire input 24 \CLK_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:959.21-959.29" + wire width 16 output 15 \RDATA_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:979.21-979.29" + wire width 16 output 33 \RDATA_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:961.21-961.29" + wire width 16 output 17 \RDATA_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:981.21-981.29" + wire width 16 output 35 \RDATA_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:945.15-945.21" + wire input 3 \REN_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:965.15-965.21" + wire input 21 \REN_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:946.15-946.21" + wire input 4 \REN_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:966.15-966.21" + wire input 22 \REN_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:960.20-960.30" + wire width 2 output 16 \RPARITY_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:980.20-980.30" + wire width 2 output 34 \RPARITY_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:962.20-962.30" + wire width 2 output 18 \RPARITY_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:982.20-982.30" + wire width 2 output 36 \RPARITY_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:955.22-955.30" + wire width 16 input 11 \WDATA_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:975.22-975.30" + wire width 16 input 29 \WDATA_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:957.22-957.30" + wire width 16 input 13 \WDATA_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:977.22-977.30" + wire width 16 input 31 \WDATA_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:943.15-943.21" + wire input 1 \WEN_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:963.15-963.21" + wire input 19 \WEN_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:944.15-944.21" + wire input 2 \WEN_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:964.15-964.21" + wire input 20 \WEN_B2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:956.21-956.31" + wire width 2 input 12 \WPARITY_A1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:976.21-976.31" + wire width 2 input 30 \WPARITY_A2 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:958.21-958.31" + wire width 2 input 14 \WPARITY_B1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:978.21-978.31" + wire width 2 input 32 \WPARITY_B2 +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:994.1-1023.10" +module \TDP_RAM36K + parameter \INIT 32768'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \INIT_PARITY 4096'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + parameter \WRITE_WIDTH_A 36 + parameter \READ_WIDTH_A 36 + parameter \WRITE_WIDTH_B 36 + parameter \READ_WIDTH_B 36 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1012.22-1012.28" + wire width 15 input 9 \ADDR_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1013.22-1013.28" + wire width 15 input 10 \ADDR_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1010.21-1010.25" + wire width 4 input 7 \BE_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1011.21-1011.25" + wire width 4 input 8 \BE_B + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1007.15-1007.20" + wire input 5 \CLK_A + attribute \clkbuf_sink 1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1009.15-1009.20" + wire input 6 \CLK_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1018.21-1018.28" + wire width 32 output 15 \RDATA_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1020.21-1020.28" + wire width 32 output 17 \RDATA_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1004.15-1004.20" + wire input 3 \REN_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1005.15-1005.20" + wire input 4 \REN_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1019.20-1019.29" + wire width 4 output 16 \RPARITY_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1021.20-1021.29" + wire width 4 output 18 \RPARITY_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1014.22-1014.29" + wire width 32 input 11 \WDATA_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1016.22-1016.29" + wire width 32 input 13 \WDATA_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1002.15-1002.20" + wire input 1 \WEN_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1003.15-1003.20" + wire input 2 \WEN_B + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1015.21-1015.30" + wire width 4 input 12 \WPARITY_A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1017.21-1017.30" + wire width 4 input 14 \WPARITY_B +end +attribute \dynports 1 +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:953.1-1356.10" +module \_$_mem_v2_asymmetric + parameter \CFG_ABITS 10 + parameter \CFG_DBITS 36 + parameter \CFG_ENABLE_B 4 + parameter \READ_ADDR_WIDTH 11 + parameter \READ_DATA_WIDTH 16 + parameter \WRITE_ADDR_WIDTH 10 + parameter \WRITE_DATA_WIDTH 32 + parameter \ABITS 0 + parameter \MEMID 0 + parameter \INIT 36864'x + parameter \OFFSET 0 + parameter \RD_ARST_VALUE 0 + parameter \RD_CE_OVER_SRST 0 + parameter \RD_CLK_ENABLE 0 + parameter \RD_CLK_POLARITY 0 + parameter \RD_COLLISION_X_MASK 0 + parameter \RD_PORTS 0 + parameter \RD_SRST_VALUE 0 + parameter \RD_TRANSPARENCY_MASK 0 + parameter \RD_WIDE_CONTINUATION 0 + parameter \SIZE 0 + parameter \WIDTH 0 + parameter \WR_CLK_ENABLE 0 + parameter \WR_CLK_POLARITY 0 + parameter \WR_PORTS 0 + parameter \WR_PRIORITY_MASK 0 + parameter \WR_WIDE_CONTINUATION 0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:998.27-998.34" + wire width 10 input 1 \RD_ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:995.11-995.18" + wire input 2 \RD_ARST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:993.11-993.17" + wire input 3 \RD_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:999.28-999.35" + wire width 36 output 4 \RD_DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:1000.11-1000.16" + wire input 5 \RD_EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:996.11-996.18" + wire input 6 \RD_SRST + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:1002.27-1002.34" + wire width 10 input 7 \WR_ADDR + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:994.11-994.17" + wire input 8 \WR_CLK + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:1003.27-1003.34" + wire width 36 input 9 \WR_DATA + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v:1004.30-1004.35" + wire width 4 input 10 \WR_EN +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:11.1-16.10" +module \buff + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:13.12-13.13" + wire input 2 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:12.12-12.13" + wire output 1 \Q +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:31.1-38.10" +module \gclkbuff + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:32.12-32.13" + wire input 1 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:33.12-33.13" + wire output 2 \Z +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:4.1-9.10" +module \inv + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:6.12-6.13" + wire input 2 \A + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:5.12-5.13" + wire output 1 \Q +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:18.1-22.10" +module \logic_0 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:19.12-19.13" + wire output 1 \a +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:24.1-28.10" +module \logic_1 + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v:25.12-25.13" + wire output 1 \a +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:8.1-15.12" +module \rs__CLK_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:9.13-9.14" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:10.13-10.14" + wire output 2 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:54.1-64.10" +module \rs__IO_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:56.13-56.14" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:58.13-58.15" + wire inout 3 \IO + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:59.13-59.14" + wire output 4 \O + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:57.13-57.14" + wire input 2 \T +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:23.3-34.10" +module \rs__I_BUF + parameter \WEAK_KEEPER "NONE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:27.12-27.14" + wire input 2 \EN + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:26.12-26.13" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:28.13-28.14" + wire output 3 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:41.1-48.10" +module \rs__O_BUF + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:42.9-42.10" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:43.10-43.11" + wire output 2 \O +end +attribute \blackbox 1 +attribute \cells_not_processed 1 +attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:70.1-80.10" +module \rs__O_BUFT + parameter \WEAK_KEEPER "NONE" + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:73.13-73.14" + wire input 1 \I + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:75.13-75.14" + wire output 3 \O + attribute \src "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v:74.13-74.14" + wire input 2 \T +end diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/design_edit.sdc b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/design_edit.sdc new file mode 100644 index 00000000..1030de01 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/design_edit.sdc @@ -0,0 +1,143 @@ +############# +# +# Fabric clock assignment +# +############# +# This clock need to route to fabric slot #0 +# set_clock_pin -device_clock clk[0] -design_clock clk (Physical port name, clock module: CLK_BUF $clkbuf$GJC48.$ibuf_clk) +# set_clock_pin -device_clock clk[0] -design_clock $clk_buf_$ibuf_clk (Original clock primitive out-net to fabric) +set_clock_pin -device_clock clk[0] -design_clock $clk_buf_$ibuf_clk + +############# +# +# Each pin mode and location assignment +# +############# +# Clock data from object clk port O is not routed to fabric +# Pin clk :: I_BUF |-> CLK_BUF + +# Pin dma_req_in[0] :: I_BUF +# set_mode MODE_BP_DIR_A_RX HP_1_4_2P +# set_io dma_req_in[0] HP_1_4_2P --> (original) +set_io $ibuf_dma_req_in[0] HP_1_4_2P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A + +# Pin dma_req_in[1] :: I_BUF +# set_mode MODE_BP_DIR_A_RX HP_1_6_3P +# set_io dma_req_in[1] HP_1_6_3P --> (original) +set_io $ibuf_dma_req_in[1] HP_1_6_3P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A + +# Pin dma_req_in[2] :: I_BUF +# set_mode MODE_BP_DIR_A_RX HP_1_8_4P +# set_io dma_req_in[2] HP_1_8_4P --> (original) +set_io $ibuf_dma_req_in[2] HP_1_8_4P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A + +# Pin dma_req_in[3] :: I_BUF +# set_mode MODE_BP_DIR_A_RX HP_1_10_5P +# set_io dma_req_in[3] HP_1_10_5P --> (original) +set_io $ibuf_dma_req_in[3] HP_1_10_5P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A + +# Pin reset_n :: I_BUF +# set_mode MODE_BP_DIR_A_RX HP_1_2_1P +# set_io reset_n HP_1_2_1P --> (original) +set_io $ibuf_reset_n HP_1_2_1P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A + +# Pin dma_ack_out[0] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HP_1_12_6P +# set_io dma_ack_out[0] HP_1_12_6P --> (original) +set_io $obuf_dma_ack_out[0] HP_1_12_6P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin dma_ack_out[1] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HP_1_14_7P +# set_io dma_ack_out[1] HP_1_14_7P --> (original) +set_io $obuf_dma_ack_out[1] HP_1_14_7P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin dma_ack_out[2] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HP_1_20_10P +# set_io dma_ack_out[2] HP_1_20_10P --> (original) +set_io $obuf_dma_ack_out[2] HP_1_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin dma_ack_out[3] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HP_1_22_11P +# set_io dma_ack_out[3] HP_1_22_11P --> (original) +set_io $obuf_dma_ack_out[3] HP_1_22_11P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +############# +# +# Internal Control Signals +# +############# +# Module: I_BUF +# LinkedObject: clk +# Location: HP_1_CC_18_9P +# Port: EN +# Signal: in:f2g_in_en_{A|B} +set_io $auto_524 HP_1_CC_18_9P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A + +# Module: I_BUF +# LinkedObject: dma_req_in[0] +# Location: HP_1_4_2P +# Port: EN +# Signal: in:f2g_in_en_{A|B} +set_io $auto_525 HP_1_4_2P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A + +# Module: I_BUF +# LinkedObject: dma_req_in[1] +# Location: HP_1_6_3P +# Port: EN +# Signal: in:f2g_in_en_{A|B} +set_io $auto_526 HP_1_6_3P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A + +# Module: I_BUF +# LinkedObject: dma_req_in[2] +# Location: HP_1_8_4P +# Port: EN +# Signal: in:f2g_in_en_{A|B} +set_io $auto_527 HP_1_8_4P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A + +# Module: I_BUF +# LinkedObject: dma_req_in[3] +# Location: HP_1_10_5P +# Port: EN +# Signal: in:f2g_in_en_{A|B} +set_io $auto_528 HP_1_10_5P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A + +# Module: I_BUF +# LinkedObject: reset_n +# Location: HP_1_2_1P +# Port: EN +# Signal: in:f2g_in_en_{A|B} +set_io $auto_529 HP_1_2_1P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A + +# Module: O_BUFT +# LinkedObject: dma_ack_out[0] +# Location: HP_1_12_6P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_530 HP_1_12_6P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A + +# Module: O_BUFT +# LinkedObject: dma_ack_out[1] +# Location: HP_1_14_7P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_531 HP_1_14_7P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A + +# Module: O_BUFT +# LinkedObject: dma_ack_out[2] +# Location: HP_1_20_10P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_532 HP_1_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A + +# Module: O_BUFT +# LinkedObject: dma_ack_out[3] +# Location: HP_1_22_11P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_533 HP_1_22_11P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A + +############# +# +# Each gearbox core clock +# +############# diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/fabric_GJC48_post_synth.eblif b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/fabric_GJC48_post_synth.eblif new file mode 100644 index 00000000..56c2626f --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/fabric_GJC48_post_synth.eblif @@ -0,0 +1,38 @@ +# Generated by Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) + +.model fabric_GJC48 +.inputs $clk_buf_$ibuf_clk $ibuf_dma_req_in[0] $ibuf_dma_req_in[1] $ibuf_dma_req_in[2] $ibuf_dma_req_in[3] $ibuf_reset_n dma_ack_reg[0] dma_ack_reg[1] dma_ack_reg[2] dma_ack_reg[3] +.outputs $auto_524 $auto_525 $auto_526 $auto_527 $auto_528 $auto_529 $auto_530 $auto_531 $auto_532 $auto_533 $obuf_dma_ack_out[0] $obuf_dma_ack_out[1] $obuf_dma_ack_out[2] $obuf_dma_ack_out[3] dma_req_reg[0] dma_req_reg[1] dma_req_reg[2] dma_req_reg[3] +.names $false +.names $true +1 +.names $undef +.subckt DFFRE C=$clk_buf_$ibuf_clk D=dma_ack_reg[0] E=$true Q=$obuf_dma_ack_out[0] R=$ibuf_reset_n +.subckt DFFRE C=$clk_buf_$ibuf_clk D=dma_ack_reg[1] E=$true Q=$obuf_dma_ack_out[1] R=$ibuf_reset_n +.subckt DFFRE C=$clk_buf_$ibuf_clk D=dma_ack_reg[2] E=$true Q=$obuf_dma_ack_out[2] R=$ibuf_reset_n +.subckt DFFRE C=$clk_buf_$ibuf_clk D=dma_ack_reg[3] E=$true Q=$obuf_dma_ack_out[3] R=$ibuf_reset_n +.subckt DFFRE C=$clk_buf_$ibuf_clk D=$ibuf_dma_req_in[0] E=$true Q=dma_req_reg[0] R=$ibuf_reset_n +.subckt DFFRE C=$clk_buf_$ibuf_clk D=$ibuf_dma_req_in[1] E=$true Q=dma_req_reg[1] R=$ibuf_reset_n +.subckt DFFRE C=$clk_buf_$ibuf_clk D=$ibuf_dma_req_in[2] E=$true Q=dma_req_reg[2] R=$ibuf_reset_n +.subckt DFFRE C=$clk_buf_$ibuf_clk D=$ibuf_dma_req_in[3] E=$true Q=dma_req_reg[3] R=$ibuf_reset_n +.names $true $auto_528 +1 1 +.names $true $auto_527 +1 1 +.names $true $auto_526 +1 1 +.names $true $auto_525 +1 1 +.names $true $auto_524 +1 1 +.names $true $auto_533 +1 1 +.names $true $auto_530 +1 1 +.names $true $auto_529 +1 1 +.names $true $auto_531 +1 1 +.names $true $auto_532 +1 1 +.end diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/fabric_GJC48_post_synth.v b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/fabric_GJC48_post_synth.v new file mode 100644 index 00000000..71713e62 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/fabric_GJC48_post_synth.v @@ -0,0 +1,193 @@ +/* Generated by Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) */ + +module fabric_GJC48(\$auto_524 , \$auto_525 , \$auto_526 , \$auto_527 , \$auto_528 , \$auto_529 , \$auto_530 , \$auto_531 , \$auto_532 , \$auto_533 , \$clk_buf_$ibuf_clk , \$ibuf_dma_req_in[0] , \$ibuf_dma_req_in[1] , \$ibuf_dma_req_in[2] , \$ibuf_dma_req_in[3] , \$ibuf_reset_n , \$obuf_dma_ack_out[0] , \$obuf_dma_ack_out[1] , \$obuf_dma_ack_out[2] , \$obuf_dma_ack_out[3] , \dma_ack_reg[0] +, \dma_ack_reg[1] , \dma_ack_reg[2] , \dma_ack_reg[3] , \dma_req_reg[0] , \dma_req_reg[1] , \dma_req_reg[2] , \dma_req_reg[3] ); + output \$auto_524 ; + output \$auto_525 ; + output \$auto_526 ; + output \$auto_527 ; + output \$auto_528 ; + output \$auto_529 ; + output \$auto_530 ; + output \$auto_531 ; + output \$auto_532 ; + output \$auto_533 ; + input \$clk_buf_$ibuf_clk ; + input \$ibuf_dma_req_in[0] ; + input \$ibuf_dma_req_in[1] ; + input \$ibuf_dma_req_in[2] ; + input \$ibuf_dma_req_in[3] ; + input \$ibuf_reset_n ; + output \$obuf_dma_ack_out[0] ; + output \$obuf_dma_ack_out[1] ; + output \$obuf_dma_ack_out[2] ; + output \$obuf_dma_ack_out[3] ; + input \dma_ack_reg[0] ; + input \dma_ack_reg[1] ; + input \dma_ack_reg[2] ; + input \dma_ack_reg[3] ; + output \dma_req_reg[0] ; + output \dma_req_reg[1] ; + output \dma_req_reg[2] ; + output \dma_req_reg[3] ; + wire \$auto_524 ; + wire \$auto_525 ; + wire \$auto_526 ; + wire \$auto_527 ; + wire \$auto_528 ; + wire \$auto_529 ; + wire \$auto_530 ; + wire \$auto_531 ; + wire \$auto_532 ; + wire \$auto_533 ; + wire \$clk_buf_$ibuf_clk ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + wire \$ibuf_reset_n ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[0] ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[1] ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[2] ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[3] ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[0] ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[1] ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[2] ; + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[3] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_268 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\dma_ack_reg[0] ), + .E(1'h1), + .Q(\$obuf_dma_ack_out[0] ), + .R(\$ibuf_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_269 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\dma_ack_reg[1] ), + .E(1'h1), + .Q(\$obuf_dma_ack_out[1] ), + .R(\$ibuf_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_270 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\dma_ack_reg[2] ), + .E(1'h1), + .Q(\$obuf_dma_ack_out[2] ), + .R(\$ibuf_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_271 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\dma_ack_reg[3] ), + .E(1'h1), + .Q(\$obuf_dma_ack_out[3] ), + .R(\$ibuf_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_272 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\$ibuf_dma_req_in[0] ), + .E(1'h1), + .Q(\dma_req_reg[0] ), + .R(\$ibuf_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_273 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\$ibuf_dma_req_in[1] ), + .E(1'h1), + .Q(\dma_req_reg[1] ), + .R(\$ibuf_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_274 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\$ibuf_dma_req_in[2] ), + .E(1'h1), + .Q(\dma_req_reg[2] ), + .R(\$ibuf_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:28.11-28.67" *) + DFFRE \$abc$267$auto_275 ( + .C(\$clk_buf_$ibuf_clk ), + .D(\$ibuf_dma_req_in[3] ), + .E(1'h1), + .Q(\dma_req_reg[3] ), + .R(\$ibuf_reset_n ) + ); + assign \$auto_528 = 1'h1; + assign \$auto_527 = 1'h1; + assign \$auto_526 = 1'h1; + assign \$auto_525 = 1'h1; + assign \$auto_524 = 1'h1; + assign \$auto_533 = 1'h1; + assign \$auto_530 = 1'h1; + assign \$auto_529 = 1'h1; + assign \$auto_531 = 1'h1; + assign \$auto_532 = 1'h1; +endmodule diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/fabric_netlist_info.json b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/fabric_netlist_info.json new file mode 100644 index 00000000..26d3e8f4 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/fabric_netlist_info.json @@ -0,0 +1,9 @@ +{ + "ports": [ + { + "clock": "active_high", + "direction": "input", + "name": "$clk_buf_$ibuf_clk" + } + ] +} diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/io_config.json b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/io_config.json new file mode 100644 index 00000000..f5606c16 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/io_config.json @@ -0,0 +1,514 @@ +{ + "messages" : [ + "Start of IO Analysis", + " Get Ports", + " Detect input port \\clk (index=0, width=1, offset=0)", + " Detect output port \\dma_ack_out (index=0, width=4, offset=0)", + " Detect output port \\dma_ack_out (index=1, width=4, offset=0)", + " Detect output port \\dma_ack_out (index=2, width=4, offset=0)", + " Detect output port \\dma_ack_out (index=3, width=4, offset=0)", + " Detect input port \\dma_req_in (index=0, width=4, offset=0)", + " Detect input port \\dma_req_in (index=1, width=4, offset=0)", + " Detect input port \\dma_req_in (index=2, width=4, offset=0)", + " Detect input port \\dma_req_in (index=3, width=4, offset=0)", + " Detect input port \\reset_n (index=0, width=1, offset=0)", + " Get Port/Standalone Primitives", + " Get important connection of cell \\I_BUF $ibuf$GJC48.$ibuf_clk", + " Cell port \\I is connected to input port \\clk", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$GJC48.$ibuf_dma_req_in", + " Cell port \\I is connected to input port \\dma_req_in[0]", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$GJC48.$ibuf_dma_req_in_1", + " Cell port \\I is connected to input port \\dma_req_in[1]", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$GJC48.$ibuf_dma_req_in_2", + " Cell port \\I is connected to input port \\dma_req_in[2]", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$GJC48.$ibuf_dma_req_in_3", + " Cell port \\I is connected to input port \\dma_req_in[3]", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$GJC48.$ibuf_reset_n", + " Cell port \\I is connected to input port \\reset_n", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$GJC48.$obuf_dma_ack_out", + " Cell port \\O is connected to output port \\dma_ack_out[0]", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$GJC48.$obuf_dma_ack_out_1", + " Cell port \\O is connected to output port \\dma_ack_out[1]", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$GJC48.$obuf_dma_ack_out_2", + " Cell port \\O is connected to output port \\dma_ack_out[2]", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$GJC48.$obuf_dma_ack_out_3", + " Cell port \\O is connected to output port \\dma_ack_out[3]", + " Data Width: -2", + " Trace \\I_BUF --> \\CLK_BUF", + " Try \\I_BUF $ibuf$GJC48.$ibuf_clk out connection: $ibuf_clk -> $clkbuf$GJC48.$ibuf_clk", + " Connected $clkbuf$GJC48.$ibuf_clk", + " Data Width: -2", + " Trace \\I_BUF_DS --> \\CLK_BUF", + " Trace \\CLK_BUF --> \\PLL", + " Trace \\BOOT_CLOCK --> \\PLL", + " Trace \\I_BUF --> \\I_DELAY", + " Trace \\I_BUF --> \\I_DDR", + " Trace \\I_BUF --> \\I_SERDES", + " Trace \\I_BUF_DS --> \\I_DELAY", + " Trace \\I_BUF_DS --> \\I_DDR", + " Trace \\I_BUF_DS --> \\I_SERDES", + " Trace \\I_DELAY --> \\I_DDR", + " Trace \\I_DELAY --> \\I_SERDES", + " Trace \\O_BUF --> \\O_DELAY", + " Trace \\O_BUF --> \\O_DDR", + " Trace \\O_BUF --> \\O_SERDES", + " Trace \\O_BUFT --> \\O_DELAY", + " Trace \\O_BUFT --> \\O_DDR", + " Trace \\O_BUFT --> \\O_SERDES", + " Trace \\O_BUF_DS --> \\O_DELAY", + " Trace \\O_BUF_DS --> \\O_DDR", + " Trace \\O_BUF_DS --> \\O_SERDES", + " Trace \\O_BUFT_DS --> \\O_DELAY", + " Trace \\O_BUFT_DS --> \\O_DDR", + " Trace \\O_BUFT_DS --> \\O_SERDES", + " Trace \\O_DELAY --> \\O_DDR", + " Trace \\O_DELAY --> \\O_SERDES", + " Trace \\O_BUF --> \\O_SERDES_CLK", + " Trace \\O_BUFT --> \\O_SERDES_CLK", + " Trace \\O_BUF_DS --> \\O_SERDES_CLK", + " Trace \\O_BUFT_DS --> \\O_SERDES_CLK", + " Trace fabric clock buffer", + " Trace gearbox fast clock source", + " Trace Core/Fabric Clock", + " Module \\CLK_BUF $clkbuf$GJC48.$ibuf_clk: clock port \\O, net $clk_buf_$ibuf_clk", + " Connected to cell \\DFFRE $abc$267$auto_268", + " Which is not a IO primitive. Send to fabric", + " Connected to cell \\DFFRE $abc$267$auto_269", + " Connected to cell \\DFFRE $abc$267$auto_270", + " Connected to cell \\DFFRE $abc$267$auto_271", + " Connected to cell \\DFFRE $abc$267$auto_272", + " Connected to cell \\DFFRE $abc$267$auto_273", + " Connected to cell \\DFFRE $abc$267$auto_274", + " Connected to cell \\DFFRE $abc$267$auto_275", + " Use slot 0", + " Double check Core/Fabric Clock", + " Summary", + " |-----------------------------------------------------------------------------------|", + " | **************************************************** |", + " IN | clk * I_BUF |-> CLK_BUF * |", + " IN | dma_req_in[0] * I_BUF * |", + " IN | dma_req_in[1] * I_BUF * |", + " IN | dma_req_in[2] * I_BUF * |", + " IN | dma_req_in[3] * I_BUF * |", + " IN | reset_n * I_BUF * |", + " OUT | * O_BUFT * dma_ack_out[0] |", + " OUT | * O_BUFT * dma_ack_out[1] |", + " OUT | * O_BUFT * dma_ack_out[2] |", + " OUT | * O_BUFT * dma_ack_out[3] |", + " | **************************************************** |", + " |-----------------------------------------------------------------------------------|", + " Final checking is good", + " Assign location HP_1_CC_18_9P (and properties) to Port clk", + " Assign location HP_1_2_1P (and properties) to Port reset_n", + " Assign location HP_1_4_2P (and properties) to Port dma_req_in[0]", + " Assign location HP_1_6_3P (and properties) to Port dma_req_in[1]", + " Assign location HP_1_8_4P (and properties) to Port dma_req_in[2]", + " Assign location HP_1_10_5P (and properties) to Port dma_req_in[3]", + " Assign location HP_1_12_6P (and properties) to Port dma_ack_out[0]", + " Assign location HP_1_14_7P (and properties) to Port dma_ack_out[1]", + " Assign location HP_1_20_10P (and properties) to Port dma_ack_out[2]", + " Assign location HP_1_22_11P (and properties) to Port dma_ack_out[3]", + " Cross-check instances vs wrapped-instances", + " Generate SDC", + " Determine data signals", + " Pin object=clk, location: HP_1_CC_18_9P", + " Data signal from object clk", + " Module=I_BUF Linked-object=clk Port=O Net=$flatten$auto_535.$ibuf_clk - Not found", + " Fail reason: Clock data from object clk port O is not routed to fabric", + " Pin object=dma_req_in[0], location: HP_1_4_2P", + " Data signal from object dma_req_in[0]", + " Module=I_BUF Linked-object=dma_req_in[0] Port=O Net=$ibuf_dma_req_in[0] - Found", + " Pin object=dma_req_in[1], location: HP_1_6_3P", + " Data signal from object dma_req_in[1]", + " Module=I_BUF Linked-object=dma_req_in[1] Port=O Net=$ibuf_dma_req_in[1] - Found", + " Pin object=dma_req_in[2], location: HP_1_8_4P", + " Data signal from object dma_req_in[2]", + " Module=I_BUF Linked-object=dma_req_in[2] Port=O Net=$ibuf_dma_req_in[2] - Found", + " Pin object=dma_req_in[3], location: HP_1_10_5P", + " Data signal from object dma_req_in[3]", + " Module=I_BUF Linked-object=dma_req_in[3] Port=O Net=$ibuf_dma_req_in[3] - Found", + " Pin object=reset_n, location: HP_1_2_1P", + " Data signal from object reset_n", + " Module=I_BUF Linked-object=reset_n Port=O Net=$ibuf_reset_n - Found", + " Pin object=dma_ack_out[0], location: HP_1_12_6P", + " Data signal from object dma_ack_out[0]", + " Module=O_BUFT Linked-object=dma_ack_out[0] Port=I Net=$obuf_dma_ack_out[0] - Found", + " Pin object=dma_ack_out[1], location: HP_1_14_7P", + " Data signal from object dma_ack_out[1]", + " Module=O_BUFT Linked-object=dma_ack_out[1] Port=I Net=$obuf_dma_ack_out[1] - Found", + " Pin object=dma_ack_out[2], location: HP_1_20_10P", + " Data signal from object dma_ack_out[2]", + " Module=O_BUFT Linked-object=dma_ack_out[2] Port=I Net=$obuf_dma_ack_out[2] - Found", + " Pin object=dma_ack_out[3], location: HP_1_22_11P", + " Data signal from object dma_ack_out[3]", + " Module=O_BUFT Linked-object=dma_ack_out[3] Port=I Net=$obuf_dma_ack_out[3] - Found", + " Determine internal control signals", + " Module=I_BUF LinkedObject=clk Location=HP_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=I_BUF LinkedObject=dma_req_in[0] Location=HP_1_4_2P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=I_BUF LinkedObject=dma_req_in[1] Location=HP_1_6_3P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=I_BUF LinkedObject=dma_req_in[2] Location=HP_1_8_4P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=I_BUF LinkedObject=dma_req_in[3] Location=HP_1_10_5P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=I_BUF LinkedObject=reset_n Location=HP_1_2_1P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=O_BUFT LinkedObject=dma_ack_out[0] Location=HP_1_12_6P Port=T Signal=in:f2g_tx_oe_{A|B}", + " Module=O_BUFT LinkedObject=dma_ack_out[1] Location=HP_1_14_7P Port=T Signal=in:f2g_tx_oe_{A|B}", + " Module=O_BUFT LinkedObject=dma_ack_out[2] Location=HP_1_20_10P Port=T Signal=in:f2g_tx_oe_{A|B}", + " Module=O_BUFT LinkedObject=dma_ack_out[3] Location=HP_1_22_11P Port=T Signal=in:f2g_tx_oe_{A|B}", + "End of IO Analysis" + ], + "instances" : [ + { + "module" : "I_BUF", + "name" : "$ibuf$GJC48.$ibuf_clk", + "location_object" : "clk", + "location" : "HP_1_CC_18_9P", + "linked_object" : "clk", + "linked_objects" : { + "clk" : { + "location" : "HP_1_CC_18_9P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "clk", + "O" : "$ibuf_clk" + }, + "parameters" : { + "WEAK_KEEPER" : "NONE" + }, + "flags" : [ + "I_BUF" + ], + "pre_primitive" : "", + "post_primitives" : [ + "CLK_BUF" + ], + "route_clock_to" : { + }, + "errors" : [ + ] + }, + { + "module" : "CLK_BUF", + "name" : "$clkbuf$GJC48.$ibuf_clk", + "location_object" : "clk", + "location" : "HP_1_CC_18_9P", + "linked_object" : "clk", + "linked_objects" : { + "clk" : { + "location" : "HP_1_CC_18_9P", + "properties" : { + "ROUTE_TO_FABRIC_CLK" : "0" + } + } + }, + "connectivity" : { + "I" : "$ibuf_clk", + "O" : "$clk_buf_$ibuf_clk" + }, + "parameters" : { + "ROUTE_TO_FABRIC_CLK" : "0" + }, + "flags" : [ + "CLK_BUF" + ], + "pre_primitive" : "I_BUF", + "post_primitives" : [ + ], + "route_clock_to" : { + }, + "errors" : [ + ] + }, + { + "module" : "I_BUF", + "name" : "$ibuf$GJC48.$ibuf_dma_req_in", + "location_object" : "dma_req_in[0]", + "location" : "HP_1_4_2P", + "linked_object" : "dma_req_in[0]", + "linked_objects" : { + "dma_req_in[0]" : { + "location" : "HP_1_4_2P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "dma_req_in[0]", + "O" : "$ibuf_dma_req_in[0]" + }, + "parameters" : { + "WEAK_KEEPER" : "NONE" + }, + "flags" : [ + "I_BUF" + ], + "pre_primitive" : "", + "post_primitives" : [ + ], + "route_clock_to" : { + }, + "errors" : [ + ] + }, + { + "module" : "I_BUF", + "name" : "$ibuf$GJC48.$ibuf_dma_req_in_1", + "location_object" : "dma_req_in[1]", + "location" : "HP_1_6_3P", + "linked_object" : "dma_req_in[1]", + "linked_objects" : { + "dma_req_in[1]" : { + "location" : "HP_1_6_3P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "dma_req_in[1]", + "O" : "$ibuf_dma_req_in[1]" + }, + "parameters" : { + "WEAK_KEEPER" : "NONE" + }, + "flags" : [ + "I_BUF" + ], + "pre_primitive" : "", + "post_primitives" : [ + ], + "route_clock_to" : { + }, + "errors" : [ + ] + }, + { + "module" : "I_BUF", + "name" : "$ibuf$GJC48.$ibuf_dma_req_in_2", + "location_object" : "dma_req_in[2]", + "location" : "HP_1_8_4P", + "linked_object" : "dma_req_in[2]", + "linked_objects" : { + "dma_req_in[2]" : { + "location" : "HP_1_8_4P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "dma_req_in[2]", + "O" : "$ibuf_dma_req_in[2]" + }, + "parameters" : { + "WEAK_KEEPER" : "NONE" + }, + "flags" : [ + "I_BUF" + ], + "pre_primitive" : "", + "post_primitives" : [ + ], + "route_clock_to" : { + }, + "errors" : [ + ] + }, + { + "module" : "I_BUF", + "name" : "$ibuf$GJC48.$ibuf_dma_req_in_3", + "location_object" : "dma_req_in[3]", + "location" : "HP_1_10_5P", + "linked_object" : "dma_req_in[3]", + "linked_objects" : { + "dma_req_in[3]" : { + "location" : "HP_1_10_5P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "dma_req_in[3]", + "O" : "$ibuf_dma_req_in[3]" + }, + "parameters" : { + "WEAK_KEEPER" : "NONE" + }, + "flags" : [ + "I_BUF" + ], + "pre_primitive" : "", + "post_primitives" : [ + ], + "route_clock_to" : { + }, + "errors" : [ + ] + }, + { + "module" : "I_BUF", + "name" : "$ibuf$GJC48.$ibuf_reset_n", + "location_object" : "reset_n", + "location" : "HP_1_2_1P", + "linked_object" : "reset_n", + "linked_objects" : { + "reset_n" : { + "location" : "HP_1_2_1P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "reset_n", + "O" : "$ibuf_reset_n" + }, + "parameters" : { + "WEAK_KEEPER" : "NONE" + }, + "flags" : [ + "I_BUF" + ], + "pre_primitive" : "", + "post_primitives" : [ + ], + "route_clock_to" : { + }, + "errors" : [ + ] + }, + { + "module" : "O_BUFT", + "name" : "$obuf$GJC48.$obuf_dma_ack_out", + "location_object" : "dma_ack_out[0]", + "location" : "HP_1_12_6P", + "linked_object" : "dma_ack_out[0]", + "linked_objects" : { + "dma_ack_out[0]" : { + "location" : "HP_1_12_6P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "$obuf_dma_ack_out[0]", + "O" : "dma_ack_out[0]" + }, + "parameters" : { + }, + "flags" : [ + "O_BUFT" + ], + "pre_primitive" : "", + "post_primitives" : [ + ], + "route_clock_to" : { + }, + "errors" : [ + ] + }, + { + "module" : "O_BUFT", + "name" : "$obuf$GJC48.$obuf_dma_ack_out_1", + "location_object" : "dma_ack_out[1]", + "location" : "HP_1_14_7P", + "linked_object" : "dma_ack_out[1]", + "linked_objects" : { + "dma_ack_out[1]" : { + "location" : "HP_1_14_7P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "$obuf_dma_ack_out[1]", + "O" : "dma_ack_out[1]" + }, + "parameters" : { + }, + "flags" : [ + "O_BUFT" + ], + "pre_primitive" : "", + "post_primitives" : [ + ], + "route_clock_to" : { + }, + "errors" : [ + ] + }, + { + "module" : "O_BUFT", + "name" : "$obuf$GJC48.$obuf_dma_ack_out_2", + "location_object" : "dma_ack_out[2]", + "location" : "HP_1_20_10P", + "linked_object" : "dma_ack_out[2]", + "linked_objects" : { + "dma_ack_out[2]" : { + "location" : "HP_1_20_10P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "$obuf_dma_ack_out[2]", + "O" : "dma_ack_out[2]" + }, + "parameters" : { + }, + "flags" : [ + "O_BUFT" + ], + "pre_primitive" : "", + "post_primitives" : [ + ], + "route_clock_to" : { + }, + "errors" : [ + ] + }, + { + "module" : "O_BUFT", + "name" : "$obuf$GJC48.$obuf_dma_ack_out_3", + "location_object" : "dma_ack_out[3]", + "location" : "HP_1_22_11P", + "linked_object" : "dma_ack_out[3]", + "linked_objects" : { + "dma_ack_out[3]" : { + "location" : "HP_1_22_11P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "$obuf_dma_ack_out[3]", + "O" : "dma_ack_out[3]" + }, + "parameters" : { + }, + "flags" : [ + "O_BUFT" + ], + "pre_primitive" : "", + "post_primitives" : [ + ], + "route_clock_to" : { + }, + "errors" : [ + ] + } + ] +} diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/io_config.simple.json b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/io_config.simple.json new file mode 100644 index 00000000..ef26a0e0 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/io_config.simple.json @@ -0,0 +1,458 @@ +{ + "messages" : [ + "Start of IO Analysis", + " Get Ports", + " Detect input port \\clk (index=0, width=1, offset=0)", + " Detect output port \\dma_ack_out (index=0, width=4, offset=0)", + " Detect output port \\dma_ack_out (index=1, width=4, offset=0)", + " Detect output port \\dma_ack_out (index=2, width=4, offset=0)", + " Detect output port \\dma_ack_out (index=3, width=4, offset=0)", + " Detect input port \\dma_req_in (index=0, width=4, offset=0)", + " Detect input port \\dma_req_in (index=1, width=4, offset=0)", + " Detect input port \\dma_req_in (index=2, width=4, offset=0)", + " Detect input port \\dma_req_in (index=3, width=4, offset=0)", + " Detect input port \\reset_n (index=0, width=1, offset=0)", + " Get Port/Standalone Primitives", + " Get important connection of cell \\I_BUF $ibuf$GJC48.$ibuf_clk", + " Cell port \\I is connected to input port \\clk", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$GJC48.$ibuf_dma_req_in", + " Cell port \\I is connected to input port \\dma_req_in[0]", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$GJC48.$ibuf_dma_req_in_1", + " Cell port \\I is connected to input port \\dma_req_in[1]", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$GJC48.$ibuf_dma_req_in_2", + " Cell port \\I is connected to input port \\dma_req_in[2]", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$GJC48.$ibuf_dma_req_in_3", + " Cell port \\I is connected to input port \\dma_req_in[3]", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\I_BUF $ibuf$GJC48.$ibuf_reset_n", + " Cell port \\I is connected to input port \\reset_n", + " Parameter \\WEAK_KEEPER: \"NONE\"", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$GJC48.$obuf_dma_ack_out", + " Cell port \\O is connected to output port \\dma_ack_out[0]", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$GJC48.$obuf_dma_ack_out_1", + " Cell port \\O is connected to output port \\dma_ack_out[1]", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$GJC48.$obuf_dma_ack_out_2", + " Cell port \\O is connected to output port \\dma_ack_out[2]", + " Data Width: -2", + " Get important connection of cell \\O_BUFT $obuf$GJC48.$obuf_dma_ack_out_3", + " Cell port \\O is connected to output port \\dma_ack_out[3]", + " Data Width: -2", + " Trace \\I_BUF --> \\CLK_BUF", + " Try \\I_BUF $ibuf$GJC48.$ibuf_clk out connection: $ibuf_clk -> $clkbuf$GJC48.$ibuf_clk", + " Connected $clkbuf$GJC48.$ibuf_clk", + " Data Width: -2", + " Trace \\I_BUF_DS --> \\CLK_BUF", + " Trace \\CLK_BUF --> \\PLL", + " Trace \\BOOT_CLOCK --> \\PLL", + " Trace \\I_BUF --> \\I_DELAY", + " Trace \\I_BUF --> \\I_DDR", + " Trace \\I_BUF --> \\I_SERDES", + " Trace \\I_BUF_DS --> \\I_DELAY", + " Trace \\I_BUF_DS --> \\I_DDR", + " Trace \\I_BUF_DS --> \\I_SERDES", + " Trace \\I_DELAY --> \\I_DDR", + " Trace \\I_DELAY --> \\I_SERDES", + " Trace \\O_BUF --> \\O_DELAY", + " Trace \\O_BUF --> \\O_DDR", + " Trace \\O_BUF --> \\O_SERDES", + " Trace \\O_BUFT --> \\O_DELAY", + " Trace \\O_BUFT --> \\O_DDR", + " Trace \\O_BUFT --> \\O_SERDES", + " Trace \\O_BUF_DS --> \\O_DELAY", + " Trace \\O_BUF_DS --> \\O_DDR", + " Trace \\O_BUF_DS --> \\O_SERDES", + " Trace \\O_BUFT_DS --> \\O_DELAY", + " Trace \\O_BUFT_DS --> \\O_DDR", + " Trace \\O_BUFT_DS --> \\O_SERDES", + " Trace \\O_DELAY --> \\O_DDR", + " Trace \\O_DELAY --> \\O_SERDES", + " Trace \\O_BUF --> \\O_SERDES_CLK", + " Trace \\O_BUFT --> \\O_SERDES_CLK", + " Trace \\O_BUF_DS --> \\O_SERDES_CLK", + " Trace \\O_BUFT_DS --> \\O_SERDES_CLK", + " Trace fabric clock buffer", + " Trace gearbox fast clock source", + " Trace Core/Fabric Clock", + " Module \\CLK_BUF $clkbuf$GJC48.$ibuf_clk: clock port \\O, net $clk_buf_$ibuf_clk", + " Connected to cell \\DFFRE $abc$267$auto_268", + " Which is not a IO primitive. Send to fabric", + " Connected to cell \\DFFRE $abc$267$auto_269", + " Connected to cell \\DFFRE $abc$267$auto_270", + " Connected to cell \\DFFRE $abc$267$auto_271", + " Connected to cell \\DFFRE $abc$267$auto_272", + " Connected to cell \\DFFRE $abc$267$auto_273", + " Connected to cell \\DFFRE $abc$267$auto_274", + " Connected to cell \\DFFRE $abc$267$auto_275", + " Use slot 0", + " Double check Core/Fabric Clock", + " Summary", + " |-----------------------------------------------------------------------------------|", + " | **************************************************** |", + " IN | clk * I_BUF |-> CLK_BUF * |", + " IN | dma_req_in[0] * I_BUF * |", + " IN | dma_req_in[1] * I_BUF * |", + " IN | dma_req_in[2] * I_BUF * |", + " IN | dma_req_in[3] * I_BUF * |", + " IN | reset_n * I_BUF * |", + " OUT | * O_BUFT * dma_ack_out[0] |", + " OUT | * O_BUFT * dma_ack_out[1] |", + " OUT | * O_BUFT * dma_ack_out[2] |", + " OUT | * O_BUFT * dma_ack_out[3] |", + " | **************************************************** |", + " |-----------------------------------------------------------------------------------|", + " Final checking is good", + " Assign location HP_1_CC_18_9P (and properties) to Port clk", + " Assign location HP_1_2_1P (and properties) to Port reset_n", + " Assign location HP_1_4_2P (and properties) to Port dma_req_in[0]", + " Assign location HP_1_6_3P (and properties) to Port dma_req_in[1]", + " Assign location HP_1_8_4P (and properties) to Port dma_req_in[2]", + " Assign location HP_1_10_5P (and properties) to Port dma_req_in[3]", + " Assign location HP_1_12_6P (and properties) to Port dma_ack_out[0]", + " Assign location HP_1_14_7P (and properties) to Port dma_ack_out[1]", + " Assign location HP_1_20_10P (and properties) to Port dma_ack_out[2]", + " Assign location HP_1_22_11P (and properties) to Port dma_ack_out[3]", + " Cross-check instances vs wrapped-instances", + " Generate SDC", + " Determine data signals", + " Pin object=clk, location: HP_1_CC_18_9P", + " Data signal from object clk", + " Module=I_BUF Linked-object=clk Port=O Net=$flatten$auto_535.$ibuf_clk - Not found", + " Fail reason: Clock data from object clk port O is not routed to fabric", + " Pin object=dma_req_in[0], location: HP_1_4_2P", + " Data signal from object dma_req_in[0]", + " Module=I_BUF Linked-object=dma_req_in[0] Port=O Net=$ibuf_dma_req_in[0] - Found", + " Pin object=dma_req_in[1], location: HP_1_6_3P", + " Data signal from object dma_req_in[1]", + " Module=I_BUF Linked-object=dma_req_in[1] Port=O Net=$ibuf_dma_req_in[1] - Found", + " Pin object=dma_req_in[2], location: HP_1_8_4P", + " Data signal from object dma_req_in[2]", + " Module=I_BUF Linked-object=dma_req_in[2] Port=O Net=$ibuf_dma_req_in[2] - Found", + " Pin object=dma_req_in[3], location: HP_1_10_5P", + " Data signal from object dma_req_in[3]", + " Module=I_BUF Linked-object=dma_req_in[3] Port=O Net=$ibuf_dma_req_in[3] - Found", + " Pin object=reset_n, location: HP_1_2_1P", + " Data signal from object reset_n", + " Module=I_BUF Linked-object=reset_n Port=O Net=$ibuf_reset_n - Found", + " Pin object=dma_ack_out[0], location: HP_1_12_6P", + " Data signal from object dma_ack_out[0]", + " Module=O_BUFT Linked-object=dma_ack_out[0] Port=I Net=$obuf_dma_ack_out[0] - Found", + " Pin object=dma_ack_out[1], location: HP_1_14_7P", + " Data signal from object dma_ack_out[1]", + " Module=O_BUFT Linked-object=dma_ack_out[1] Port=I Net=$obuf_dma_ack_out[1] - Found", + " Pin object=dma_ack_out[2], location: HP_1_20_10P", + " Data signal from object dma_ack_out[2]", + " Module=O_BUFT Linked-object=dma_ack_out[2] Port=I Net=$obuf_dma_ack_out[2] - Found", + " Pin object=dma_ack_out[3], location: HP_1_22_11P", + " Data signal from object dma_ack_out[3]", + " Module=O_BUFT Linked-object=dma_ack_out[3] Port=I Net=$obuf_dma_ack_out[3] - Found", + " Determine internal control signals", + " Module=I_BUF LinkedObject=clk Location=HP_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=I_BUF LinkedObject=dma_req_in[0] Location=HP_1_4_2P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=I_BUF LinkedObject=dma_req_in[1] Location=HP_1_6_3P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=I_BUF LinkedObject=dma_req_in[2] Location=HP_1_8_4P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=I_BUF LinkedObject=dma_req_in[3] Location=HP_1_10_5P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=I_BUF LinkedObject=reset_n Location=HP_1_2_1P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=O_BUFT LinkedObject=dma_ack_out[0] Location=HP_1_12_6P Port=T Signal=in:f2g_tx_oe_{A|B}", + " Module=O_BUFT LinkedObject=dma_ack_out[1] Location=HP_1_14_7P Port=T Signal=in:f2g_tx_oe_{A|B}", + " Module=O_BUFT LinkedObject=dma_ack_out[2] Location=HP_1_20_10P Port=T Signal=in:f2g_tx_oe_{A|B}", + " Module=O_BUFT LinkedObject=dma_ack_out[3] Location=HP_1_22_11P Port=T Signal=in:f2g_tx_oe_{A|B}", + "End of IO Analysis" + ], + "instances" : [ + { + "module" : "I_BUF", + "name" : "$ibuf$GJC48.$ibuf_clk", + "location_object" : "clk", + "location" : "HP_1_CC_18_9P", + "linked_object" : "clk", + "linked_objects" : { + "clk" : { + "location" : "HP_1_CC_18_9P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "clk", + "O" : "$ibuf_clk" + }, + "parameters" : { + "WEAK_KEEPER" : "NONE" + }, + "flags" : [ + "I_BUF" + ], + "errors" : [ + ] + }, + { + "module" : "CLK_BUF", + "name" : "$clkbuf$GJC48.$ibuf_clk", + "location_object" : "clk", + "location" : "HP_1_CC_18_9P", + "linked_object" : "clk", + "linked_objects" : { + "clk" : { + "location" : "HP_1_CC_18_9P", + "properties" : { + "ROUTE_TO_FABRIC_CLK" : "0" + } + } + }, + "connectivity" : { + "I" : "$ibuf_clk", + "O" : "$clk_buf_$ibuf_clk" + }, + "parameters" : { + "ROUTE_TO_FABRIC_CLK" : "0" + }, + "flags" : [ + "CLK_BUF" + ], + "errors" : [ + ] + }, + { + "module" : "I_BUF", + "name" : "$ibuf$GJC48.$ibuf_dma_req_in", + "location_object" : "dma_req_in[0]", + "location" : "HP_1_4_2P", + "linked_object" : "dma_req_in[0]", + "linked_objects" : { + "dma_req_in[0]" : { + "location" : "HP_1_4_2P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "dma_req_in[0]", + "O" : "$ibuf_dma_req_in[0]" + }, + "parameters" : { + "WEAK_KEEPER" : "NONE" + }, + "flags" : [ + "I_BUF" + ], + "errors" : [ + ] + }, + { + "module" : "I_BUF", + "name" : "$ibuf$GJC48.$ibuf_dma_req_in_1", + "location_object" : "dma_req_in[1]", + "location" : "HP_1_6_3P", + "linked_object" : "dma_req_in[1]", + "linked_objects" : { + "dma_req_in[1]" : { + "location" : "HP_1_6_3P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "dma_req_in[1]", + "O" : "$ibuf_dma_req_in[1]" + }, + "parameters" : { + "WEAK_KEEPER" : "NONE" + }, + "flags" : [ + "I_BUF" + ], + "errors" : [ + ] + }, + { + "module" : "I_BUF", + "name" : "$ibuf$GJC48.$ibuf_dma_req_in_2", + "location_object" : "dma_req_in[2]", + "location" : "HP_1_8_4P", + "linked_object" : "dma_req_in[2]", + "linked_objects" : { + "dma_req_in[2]" : { + "location" : "HP_1_8_4P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "dma_req_in[2]", + "O" : "$ibuf_dma_req_in[2]" + }, + "parameters" : { + "WEAK_KEEPER" : "NONE" + }, + "flags" : [ + "I_BUF" + ], + "errors" : [ + ] + }, + { + "module" : "I_BUF", + "name" : "$ibuf$GJC48.$ibuf_dma_req_in_3", + "location_object" : "dma_req_in[3]", + "location" : "HP_1_10_5P", + "linked_object" : "dma_req_in[3]", + "linked_objects" : { + "dma_req_in[3]" : { + "location" : "HP_1_10_5P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "dma_req_in[3]", + "O" : "$ibuf_dma_req_in[3]" + }, + "parameters" : { + "WEAK_KEEPER" : "NONE" + }, + "flags" : [ + "I_BUF" + ], + "errors" : [ + ] + }, + { + "module" : "I_BUF", + "name" : "$ibuf$GJC48.$ibuf_reset_n", + "location_object" : "reset_n", + "location" : "HP_1_2_1P", + "linked_object" : "reset_n", + "linked_objects" : { + "reset_n" : { + "location" : "HP_1_2_1P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "reset_n", + "O" : "$ibuf_reset_n" + }, + "parameters" : { + "WEAK_KEEPER" : "NONE" + }, + "flags" : [ + "I_BUF" + ], + "errors" : [ + ] + }, + { + "module" : "O_BUFT", + "name" : "$obuf$GJC48.$obuf_dma_ack_out", + "location_object" : "dma_ack_out[0]", + "location" : "HP_1_12_6P", + "linked_object" : "dma_ack_out[0]", + "linked_objects" : { + "dma_ack_out[0]" : { + "location" : "HP_1_12_6P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "$obuf_dma_ack_out[0]", + "O" : "dma_ack_out[0]" + }, + "parameters" : { + }, + "flags" : [ + "O_BUFT" + ], + "errors" : [ + ] + }, + { + "module" : "O_BUFT", + "name" : "$obuf$GJC48.$obuf_dma_ack_out_1", + "location_object" : "dma_ack_out[1]", + "location" : "HP_1_14_7P", + "linked_object" : "dma_ack_out[1]", + "linked_objects" : { + "dma_ack_out[1]" : { + "location" : "HP_1_14_7P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "$obuf_dma_ack_out[1]", + "O" : "dma_ack_out[1]" + }, + "parameters" : { + }, + "flags" : [ + "O_BUFT" + ], + "errors" : [ + ] + }, + { + "module" : "O_BUFT", + "name" : "$obuf$GJC48.$obuf_dma_ack_out_2", + "location_object" : "dma_ack_out[2]", + "location" : "HP_1_20_10P", + "linked_object" : "dma_ack_out[2]", + "linked_objects" : { + "dma_ack_out[2]" : { + "location" : "HP_1_20_10P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "$obuf_dma_ack_out[2]", + "O" : "dma_ack_out[2]" + }, + "parameters" : { + }, + "flags" : [ + "O_BUFT" + ], + "errors" : [ + ] + }, + { + "module" : "O_BUFT", + "name" : "$obuf$GJC48.$obuf_dma_ack_out_3", + "location_object" : "dma_ack_out[3]", + "location" : "HP_1_22_11P", + "linked_object" : "dma_ack_out[3]", + "linked_objects" : { + "dma_ack_out[3]" : { + "location" : "HP_1_22_11P", + "properties" : { + } + } + }, + "connectivity" : { + "I" : "$obuf_dma_ack_out[3]", + "O" : "dma_ack_out[3]" + }, + "parameters" : { + }, + "flags" : [ + "O_BUFT" + ], + "errors" : [ + ] + } + ] +} diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/netlist_checker.log b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/netlist_checker.log new file mode 100644 index 00000000..e28d91fc --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/netlist_checker.log @@ -0,0 +1,14 @@ +Checking Buffer connections +All IO connections are correct. + +Checking Buffer control signals +================================================================ +================================================================ + +Checking I_DELAY/O_DELAY control signals +================================================================ +================================================================ + +Checking FCLK_BUF connections +================================================================ +================================================================ diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/netlist_info.json b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/netlist_info.json new file mode 100644 index 00000000..cf1620f7 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/netlist_info.json @@ -0,0 +1,47 @@ +{ + "top" : "GJC48", + "ports" : [ + { + "name": "dma_ack_out[1]", + "direction": "output" + }, + { + "name": "dma_ack_out[0]", + "direction": "output" + }, + { + "name": "dma_req_in[3]", + "direction": "input" + }, + { + "name": "dma_req_in[2]", + "direction": "input" + }, + { + "name": "dma_req_in[1]", + "direction": "input" + }, + { + "name": "dma_req_in[0]", + "direction": "input" + }, + { + "name": "clk", + "direction": "input", + "clock": "active_high" + }, + { + "name": "dma_ack_out[3]", + "direction": "output" + }, + { + "name": "dma_ack_out[2]", + "direction": "output" + }, + { + "name": "reset_n", + "direction": "input", + "async_reset": "active_low" + } + ] +} diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/pin_location_GJC48.sdc b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/pin_location_GJC48.sdc new file mode 100644 index 00000000..251b88b6 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/pin_location_GJC48.sdc @@ -0,0 +1,10 @@ +set_pin_loc clk HP_1_CC_18_9P +set_pin_loc reset_n HP_1_2_1P +set_pin_loc dma_req_in[0] HP_1_4_2P +set_pin_loc dma_req_in[1] HP_1_6_3P +set_pin_loc dma_req_in[2] HP_1_8_4P +set_pin_loc dma_req_in[3] HP_1_10_5P +set_pin_loc dma_ack_out[0] HP_1_12_6P +set_pin_loc dma_ack_out[1] HP_1_14_7P +set_pin_loc dma_ack_out[2] HP_1_20_10P +set_pin_loc dma_ack_out[3] HP_1_22_11P diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/post_pnr_wrapper_GJC48_post_synth.eblif b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/post_pnr_wrapper_GJC48_post_synth.eblif new file mode 100644 index 00000000..fb14443f --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/post_pnr_wrapper_GJC48_post_synth.eblif @@ -0,0 +1,105 @@ +# Generated by Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) + +.model GJC48 +.inputs clk reset_n dma_req_in[0] dma_req_in[1] dma_req_in[2] dma_req_in[3] +.outputs dma_ack_out[0] dma_ack_out[1] dma_ack_out[2] dma_ack_out[3] +.names $false +.names $true +1 +.names $undef +.subckt fabric_GJC48 $auto_524=$auto_524 $auto_525=$auto_525 $auto_526=$auto_526 $auto_527=$auto_527 $auto_528=$auto_528 $auto_529=$auto_529 $auto_530=$auto_530 $auto_531=$auto_531 $auto_532=$auto_532 $auto_533=$auto_533 $clk_buf_$ibuf_clk=$clk_buf_$ibuf_clk $ibuf_dma_req_in[0]=$ibuf_dma_req_in[0] $ibuf_dma_req_in[1]=$ibuf_dma_req_in[1] $ibuf_dma_req_in[2]=$ibuf_dma_req_in[2] $ibuf_dma_req_in[3]=$ibuf_dma_req_in[3] $ibuf_reset_n=$ibuf_reset_n $obuf_dma_ack_out[0]=$obuf_dma_ack_out[0] $obuf_dma_ack_out[1]=$obuf_dma_ack_out[1] $obuf_dma_ack_out[2]=$obuf_dma_ack_out[2] $obuf_dma_ack_out[3]=$obuf_dma_ack_out[3] dma_ack_reg[0]=dma_ack_reg[0] dma_ack_reg[1]=dma_ack_reg[1] dma_ack_reg[2]=dma_ack_reg[2] dma_ack_reg[3]=dma_ack_reg[3] dma_req_reg[0]=dma_req_reg[0] dma_req_reg[1]=dma_req_reg[1] dma_req_reg[2]=dma_req_reg[2] dma_req_reg[3]=dma_req_reg[3] +.subckt SOC_FPGA_INTF_DMA DMA_ACK[0]=$auto_535.dma_ack_reg[0] DMA_ACK[1]=$auto_535.dma_ack_reg[1] DMA_ACK[2]=$auto_535.dma_ack_reg[2] DMA_ACK[3]=$auto_535.dma_ack_reg[3] DMA_CLK=$flatten$auto_535.$ibuf_clk DMA_REQ[0]=$auto_535.dma_req_reg[0] DMA_REQ[1]=$auto_535.dma_req_reg[1] DMA_REQ[2]=$auto_535.dma_req_reg[2] DMA_REQ[3]=$auto_535.dma_req_reg[3] DMA_RST_N=$flatten$auto_535.$ibuf_reset_n +.subckt CLK_BUF I=$flatten$auto_535.$ibuf_clk O=$flatten$auto_535.$clk_buf_$ibuf_clk +.subckt I_BUF EN=$flatten$auto_535.$auto_524 I=$auto_535.clk O=$flatten$auto_535.$ibuf_clk +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$flatten$auto_535.$auto_525 I=$auto_535.dma_req_in[0] O=$flatten$auto_535.$ibuf_dma_req_in[0] +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$flatten$auto_535.$auto_526 I=$auto_535.dma_req_in[1] O=$flatten$auto_535.$ibuf_dma_req_in[1] +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$flatten$auto_535.$auto_527 I=$auto_535.dma_req_in[2] O=$flatten$auto_535.$ibuf_dma_req_in[2] +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$flatten$auto_535.$auto_528 I=$auto_535.dma_req_in[3] O=$flatten$auto_535.$ibuf_dma_req_in[3] +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$flatten$auto_535.$auto_529 I=$auto_535.reset_n O=$flatten$auto_535.$ibuf_reset_n +.param WEAK_KEEPER "NONE" +.subckt O_BUFT I=$flatten$auto_535.$obuf_dma_ack_out[0] O=$auto_535.dma_ack_out[0] T=$flatten$auto_535.$auto_530 +.subckt O_BUFT I=$flatten$auto_535.$obuf_dma_ack_out[1] O=$auto_535.dma_ack_out[1] T=$flatten$auto_535.$auto_531 +.subckt O_BUFT I=$flatten$auto_535.$obuf_dma_ack_out[2] O=$auto_535.dma_ack_out[2] T=$flatten$auto_535.$auto_532 +.subckt O_BUFT I=$flatten$auto_535.$obuf_dma_ack_out[3] O=$auto_535.dma_ack_out[3] T=$flatten$auto_535.$auto_533 +.names $auto_533 $flatten$auto_535.$auto_533 +1 1 +.names $auto_532 $flatten$auto_535.$auto_532 +1 1 +.names $auto_531 $flatten$auto_535.$auto_531 +1 1 +.names $auto_530 $flatten$auto_535.$auto_530 +1 1 +.names $auto_529 $flatten$auto_535.$auto_529 +1 1 +.names $auto_528 $flatten$auto_535.$auto_528 +1 1 +.names $auto_527 $flatten$auto_535.$auto_527 +1 1 +.names $auto_526 $flatten$auto_535.$auto_526 +1 1 +.names $auto_525 $flatten$auto_535.$auto_525 +1 1 +.names $auto_524 $flatten$auto_535.$auto_524 +1 1 +.names $flatten$auto_535.$clk_buf_$ibuf_clk $clk_buf_$ibuf_clk +1 1 +.names $flatten$auto_535.$ibuf_dma_req_in[0] $ibuf_dma_req_in[0] +1 1 +.names $flatten$auto_535.$ibuf_dma_req_in[1] $ibuf_dma_req_in[1] +1 1 +.names $flatten$auto_535.$ibuf_dma_req_in[2] $ibuf_dma_req_in[2] +1 1 +.names $flatten$auto_535.$ibuf_dma_req_in[3] $ibuf_dma_req_in[3] +1 1 +.names $flatten$auto_535.$ibuf_reset_n $ibuf_reset_n +1 1 +.names $obuf_dma_ack_out[0] $flatten$auto_535.$obuf_dma_ack_out[0] +1 1 +.names $obuf_dma_ack_out[1] $flatten$auto_535.$obuf_dma_ack_out[1] +1 1 +.names $obuf_dma_ack_out[2] $flatten$auto_535.$obuf_dma_ack_out[2] +1 1 +.names $obuf_dma_ack_out[3] $flatten$auto_535.$obuf_dma_ack_out[3] +1 1 +.names clk $auto_535.clk +1 1 +.names $auto_535.dma_ack_out[0] dma_ack_out[0] +1 1 +.names $auto_535.dma_ack_out[1] dma_ack_out[1] +1 1 +.names $auto_535.dma_ack_out[2] dma_ack_out[2] +1 1 +.names $auto_535.dma_ack_out[3] dma_ack_out[3] +1 1 +.names $auto_535.dma_ack_reg[0] dma_ack_reg[0] +1 1 +.names $auto_535.dma_ack_reg[1] dma_ack_reg[1] +1 1 +.names $auto_535.dma_ack_reg[2] dma_ack_reg[2] +1 1 +.names $auto_535.dma_ack_reg[3] dma_ack_reg[3] +1 1 +.names dma_req_in[0] $auto_535.dma_req_in[0] +1 1 +.names dma_req_in[1] $auto_535.dma_req_in[1] +1 1 +.names dma_req_in[2] $auto_535.dma_req_in[2] +1 1 +.names dma_req_in[3] $auto_535.dma_req_in[3] +1 1 +.names dma_req_reg[0] $auto_535.dma_req_reg[0] +1 1 +.names dma_req_reg[1] $auto_535.dma_req_reg[1] +1 1 +.names dma_req_reg[2] $auto_535.dma_req_reg[2] +1 1 +.names dma_req_reg[3] $auto_535.dma_req_reg[3] +1 1 +.names reset_n $auto_535.reset_n +1 1 +.end diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/post_pnr_wrapper_GJC48_post_synth.v b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/post_pnr_wrapper_GJC48_post_synth.v new file mode 100644 index 00000000..822e22fa --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/post_pnr_wrapper_GJC48_post_synth.v @@ -0,0 +1,313 @@ +/* Generated by Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) */ + +module GJC48(clk, reset_n, dma_req_in, dma_ack_out); + input clk; + output [3:0] dma_ack_out; + input [3:0] dma_req_in; + input reset_n; + wire \$auto_524 ; + wire \$auto_525 ; + wire \$auto_526 ; + wire \$auto_527 ; + wire \$auto_528 ; + wire \$auto_529 ; + wire \$auto_530 ; + wire \$auto_531 ; + wire \$auto_532 ; + wire \$auto_533 ; + (* keep = 32'd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" *) + wire \$auto_535.clk ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire [3:0] \$auto_535.dma_ack_out ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \$auto_535.dma_ack_reg[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \$auto_535.dma_ack_reg[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \$auto_535.dma_ack_reg[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \$auto_535.dma_ack_reg[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire [3:0] \$auto_535.dma_req_in ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \$auto_535.dma_req_reg[0] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \$auto_535.dma_req_reg[1] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \$auto_535.dma_req_reg[2] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \$auto_535.dma_req_reg[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + wire \$auto_535.reset_n ; + wire \$clk_buf_$ibuf_clk ; + wire \$flatten$auto_535.$auto_524 ; + wire \$flatten$auto_535.$auto_525 ; + wire \$flatten$auto_535.$auto_526 ; + wire \$flatten$auto_535.$auto_527 ; + wire \$flatten$auto_535.$auto_528 ; + wire \$flatten$auto_535.$auto_529 ; + wire \$flatten$auto_535.$auto_530 ; + wire \$flatten$auto_535.$auto_531 ; + wire \$flatten$auto_535.$auto_532 ; + wire \$flatten$auto_535.$auto_533 ; + wire \$flatten$auto_535.$clk_buf_$ibuf_clk ; + (* keep = 32'd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" *) + wire \$flatten$auto_535.$ibuf_clk ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$flatten$auto_535.$ibuf_dma_req_in[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$flatten$auto_535.$ibuf_dma_req_in[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$flatten$auto_535.$ibuf_dma_req_in[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$flatten$auto_535.$ibuf_dma_req_in[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + wire \$flatten$auto_535.$ibuf_reset_n ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$flatten$auto_535.$obuf_dma_ack_out[0] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$flatten$auto_535.$obuf_dma_ack_out[1] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$flatten$auto_535.$obuf_dma_ack_out[2] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$flatten$auto_535.$obuf_dma_ack_out[3] ; + (* keep = 32'd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" *) + wire \$ibuf_clk ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + wire \$ibuf_reset_n ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[0] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[1] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[2] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[3] ; + (* keep = 32'd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" *) + (* keep = 32'd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" *) + wire clk; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire [3:0] dma_ack_out; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire [3:0] dma_req_in; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[0] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[1] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[2] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + wire reset_n; + fabric_GJC48 \$auto_534 ( + .\$auto_524 (\$auto_524 ), + .\$auto_525 (\$auto_525 ), + .\$auto_526 (\$auto_526 ), + .\$auto_527 (\$auto_527 ), + .\$auto_528 (\$auto_528 ), + .\$auto_529 (\$auto_529 ), + .\$auto_530 (\$auto_530 ), + .\$auto_531 (\$auto_531 ), + .\$auto_532 (\$auto_532 ), + .\$auto_533 (\$auto_533 ), + .\$clk_buf_$ibuf_clk (\$clk_buf_$ibuf_clk ), + .\$ibuf_dma_req_in[0] (\$ibuf_dma_req_in[0] ), + .\$ibuf_dma_req_in[1] (\$ibuf_dma_req_in[1] ), + .\$ibuf_dma_req_in[2] (\$ibuf_dma_req_in[2] ), + .\$ibuf_dma_req_in[3] (\$ibuf_dma_req_in[3] ), + .\$ibuf_reset_n (\$ibuf_reset_n ), + .\$obuf_dma_ack_out[0] (\$obuf_dma_ack_out[0] ), + .\$obuf_dma_ack_out[1] (\$obuf_dma_ack_out[1] ), + .\$obuf_dma_ack_out[2] (\$obuf_dma_ack_out[2] ), + .\$obuf_dma_ack_out[3] (\$obuf_dma_ack_out[3] ), + .\dma_ack_reg[0] (\dma_ack_reg[0] ), + .\dma_ack_reg[1] (\dma_ack_reg[1] ), + .\dma_ack_reg[2] (\dma_ack_reg[2] ), + .\dma_ack_reg[3] (\dma_ack_reg[3] ), + .\dma_req_reg[0] (\dma_req_reg[0] ), + .\dma_req_reg[1] (\dma_req_reg[1] ), + .\dma_req_reg[2] (\dma_req_reg[2] ), + .\dma_req_reg[3] (\dma_req_reg[3] ) + ); + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:12.21-17.4" *) + SOC_FPGA_INTF_DMA \$auto_535.dma_inst ( + .DMA_ACK({ \$auto_535.dma_ack_reg[3] , \$auto_535.dma_ack_reg[2] , \$auto_535.dma_ack_reg[1] , \$auto_535.dma_ack_reg[0] }), + .DMA_CLK(\$flatten$auto_535.$ibuf_clk ), + .DMA_REQ({ \$auto_535.dma_req_reg[3] , \$auto_535.dma_req_reg[2] , \$auto_535.dma_req_reg[1] , \$auto_535.dma_req_reg[0] }), + .DMA_RST_N(\$flatten$auto_535.$ibuf_reset_n ) + ); + (* keep = 32'sd1 *) + CLK_BUF \$flatten$auto_535.$clkbuf$GJC48.$ibuf_clk ( + .I(\$flatten$auto_535.$ibuf_clk ), + .O(\$flatten$auto_535.$clk_buf_$ibuf_clk ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_535.$ibuf$GJC48.$ibuf_clk ( + .EN(\$flatten$auto_535.$auto_524 ), + .I(\$auto_535.clk ), + .O(\$flatten$auto_535.$ibuf_clk ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_535.$ibuf$GJC48.$ibuf_dma_req_in ( + .EN(\$flatten$auto_535.$auto_525 ), + .I(\$auto_535.dma_req_in [0]), + .O(\$flatten$auto_535.$ibuf_dma_req_in[0] ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_535.$ibuf$GJC48.$ibuf_dma_req_in_1 ( + .EN(\$flatten$auto_535.$auto_526 ), + .I(\$auto_535.dma_req_in [1]), + .O(\$flatten$auto_535.$ibuf_dma_req_in[1] ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_535.$ibuf$GJC48.$ibuf_dma_req_in_2 ( + .EN(\$flatten$auto_535.$auto_527 ), + .I(\$auto_535.dma_req_in [2]), + .O(\$flatten$auto_535.$ibuf_dma_req_in[2] ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_535.$ibuf$GJC48.$ibuf_dma_req_in_3 ( + .EN(\$flatten$auto_535.$auto_528 ), + .I(\$auto_535.dma_req_in [3]), + .O(\$flatten$auto_535.$ibuf_dma_req_in[3] ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_535.$ibuf$GJC48.$ibuf_reset_n ( + .EN(\$flatten$auto_535.$auto_529 ), + .I(\$auto_535.reset_n ), + .O(\$flatten$auto_535.$ibuf_reset_n ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_535.$obuf$GJC48.$obuf_dma_ack_out ( + .I(\$flatten$auto_535.$obuf_dma_ack_out[0] ), + .O(\$auto_535.dma_ack_out [0]), + .T(\$flatten$auto_535.$auto_530 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_535.$obuf$GJC48.$obuf_dma_ack_out_1 ( + .I(\$flatten$auto_535.$obuf_dma_ack_out[1] ), + .O(\$auto_535.dma_ack_out [1]), + .T(\$flatten$auto_535.$auto_531 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_535.$obuf$GJC48.$obuf_dma_ack_out_2 ( + .I(\$flatten$auto_535.$obuf_dma_ack_out[2] ), + .O(\$auto_535.dma_ack_out [2]), + .T(\$flatten$auto_535.$auto_532 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_535.$obuf$GJC48.$obuf_dma_ack_out_3 ( + .I(\$flatten$auto_535.$obuf_dma_ack_out[3] ), + .O(\$auto_535.dma_ack_out [3]), + .T(\$flatten$auto_535.$auto_533 ) + ); + assign \$flatten$auto_535.$auto_533 = \$auto_533 ; + assign \$flatten$auto_535.$auto_532 = \$auto_532 ; + assign \$flatten$auto_535.$auto_531 = \$auto_531 ; + assign \$flatten$auto_535.$auto_530 = \$auto_530 ; + assign \$flatten$auto_535.$auto_529 = \$auto_529 ; + assign \$flatten$auto_535.$auto_528 = \$auto_528 ; + assign \$flatten$auto_535.$auto_527 = \$auto_527 ; + assign \$flatten$auto_535.$auto_526 = \$auto_526 ; + assign \$flatten$auto_535.$auto_525 = \$auto_525 ; + assign \$flatten$auto_535.$auto_524 = \$auto_524 ; + assign \$clk_buf_$ibuf_clk = \$flatten$auto_535.$clk_buf_$ibuf_clk ; + assign \$ibuf_dma_req_in[0] = \$flatten$auto_535.$ibuf_dma_req_in[0] ; + assign \$ibuf_dma_req_in[1] = \$flatten$auto_535.$ibuf_dma_req_in[1] ; + assign \$ibuf_dma_req_in[2] = \$flatten$auto_535.$ibuf_dma_req_in[2] ; + assign \$ibuf_dma_req_in[3] = \$flatten$auto_535.$ibuf_dma_req_in[3] ; + assign \$ibuf_reset_n = \$flatten$auto_535.$ibuf_reset_n ; + assign \$flatten$auto_535.$obuf_dma_ack_out[0] = \$obuf_dma_ack_out[0] ; + assign \$flatten$auto_535.$obuf_dma_ack_out[1] = \$obuf_dma_ack_out[1] ; + assign \$flatten$auto_535.$obuf_dma_ack_out[2] = \$obuf_dma_ack_out[2] ; + assign \$flatten$auto_535.$obuf_dma_ack_out[3] = \$obuf_dma_ack_out[3] ; + assign \$auto_535.clk = clk; + assign dma_ack_out = \$auto_535.dma_ack_out ; + assign \dma_ack_reg[0] = \$auto_535.dma_ack_reg[0] ; + assign \dma_ack_reg[1] = \$auto_535.dma_ack_reg[1] ; + assign \dma_ack_reg[2] = \$auto_535.dma_ack_reg[2] ; + assign \dma_ack_reg[3] = \$auto_535.dma_ack_reg[3] ; + assign \$auto_535.dma_req_in = dma_req_in; + assign \$auto_535.dma_req_reg[0] = \dma_req_reg[0] ; + assign \$auto_535.dma_req_reg[1] = \dma_req_reg[1] ; + assign \$auto_535.dma_req_reg[2] = \dma_req_reg[2] ; + assign \$auto_535.dma_req_reg[3] = \dma_req_reg[3] ; + assign \$auto_535.reset_n = reset_n; +endmodule diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/reports/synth_design_stat.json b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/reports/synth_design_stat.json new file mode 100644 index 00000000..5684716e --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/reports/synth_design_stat.json @@ -0,0 +1,40 @@ +[ + { + "": { + "header": [ + "Design statistics", + "" + ], + "data": [ + [ + "CLB LUT packing percentage", + "0 %" + ], + [ + "CLB Register packing percentage", + "0 %" + ], + [ + "Wires", + "0" + ], + [ + "Max Fanout", + "0" + ], + [ + "Average Fanout", + "0" + ], + [ + "Maximum logic level", + "0" + ], + [ + "Average logic level", + "0" + ] + ] + } + } +] \ No newline at end of file diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/reports/synth_utilization.json b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/reports/synth_utilization.json new file mode 100644 index 00000000..975f99a1 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/reports/synth_utilization.json @@ -0,0 +1,148 @@ +[ + { + "": { + "header": [ + "Logic", + "Used", + "Available", + "%" + ], + "data": [ + [ + "CLB", + "0", + "2184", + "0" + ], + [ + " LUTs", + "0", + "17472", + "0" + ], + [ + " Registers", + "8", + "34944", + "0" + ], + [ + " Flip Flop", + "8", + "34944", + "0" + ], + [ + " Adder Carry", + "0", + "17472", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "Block RAM", + "Used", + "Available", + "%" + ], + "data": [ + [ + "BRAM", + "0", + "56", + "0" + ], + [ + " 18k", + "0", + "112", + "0" + ], + [ + " 36k", + "0", + "56", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "DSP", + "Used", + "Available", + "%" + ], + "data": [ + [ + "DSP Block", + "0", + "56", + "0" + ], + [ + " 9x10", + "0", + "56", + "0" + ], + [ + " 18x20", + "0", + "112", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "I/O", + "Used", + "Available", + "%" + ], + "data": [ + [ + "I/O", + "0", + "240", + "0" + ], + [ + " Inputs", + "0", + "240", + "0" + ], + [ + " Outputs", + "0", + "240", + "0" + ] + ] + } + }, + { + "": { + "header": [ + "Clock", + "Used" + ], + "data": [ + [ + "Clock", + "0" + ] + ] + } + } +] \ No newline at end of file diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/synthesis.rpt b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/synthesis.rpt new file mode 100644 index 00000000..19e9b0c8 --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/synthesis.rpt @@ -0,0 +1,2223 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.08 +Build : 1.1.51 +Hash : c3b8064 +Date : Aug 27 2024 +Type : Engineering +Log Time : Tue Aug 27 07:56:04 2024 GMT + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) + + +-- Executing script file `GJC48.ys' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v' to AST representation. +Generating RTLIL representation for module `\GJC48'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \GJC48 + +3.2. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +4. Executing synth_rs pass: v0.4.218 + +4.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\inv'. +Generating RTLIL representation for module `\buff'. +Generating RTLIL representation for module `\logic_0'. +Generating RTLIL representation for module `\logic_1'. +Generating RTLIL representation for module `\gclkbuff'. +Successfully finished Verilog frontend. + +4.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v' to AST representation. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v:10.1-33.10. +Generating RTLIL representation for module `\CARRY'. +Successfully finished Verilog frontend. + +4.3. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v' to AST representation. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:20.1-34.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:48.1-62.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:81.1-97.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:115.1-131.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:150.1-166.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:184.1-200.10. +Generating RTLIL representation for module `\LATCHNS'. +Generating RTLIL representation for module `\LATCHSRE'. +Generating RTLIL representation for module `\LATCHNSRE'. +Successfully finished Verilog frontend. + +4.4. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v' to AST representation. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:11.1-81.10. +Generating RTLIL representation for module `\DFFRE'. +Successfully finished Verilog frontend. + +4.5. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v' to AST representation. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:11.1-80.10. +Generating RTLIL representation for module `\DFFNRE'. +Successfully finished Verilog frontend. + +4.6. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v' to AST representation. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v:10.1-20.10. +Generating RTLIL representation for module `\LUT1'. +Successfully finished Verilog frontend. + +4.7. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v' to AST representation. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v:10.1-21.10. +Generating RTLIL representation for module `\LUT2'. +Successfully finished Verilog frontend. + +4.8. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v' to AST representation. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v:10.1-22.10. +Generating RTLIL representation for module `\LUT3'. +Successfully finished Verilog frontend. + +4.9. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v' to AST representation. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v:11.1-25.10. +Generating RTLIL representation for module `\LUT4'. +Successfully finished Verilog frontend. + +4.10. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v' to AST representation. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v:10.1-24.10. +Generating RTLIL representation for module `\LUT5'. +Successfully finished Verilog frontend. + +4.11. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v' to AST representation. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v:10.1-25.10. +Generating RTLIL representation for module `\LUT6'. +Successfully finished Verilog frontend. + +4.12. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v' to AST representation. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v:10.1-25.10. +Generating RTLIL representation for module `\CLK_BUF'. +Successfully finished Verilog frontend. + +4.13. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v' to AST representation. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v:10.1-84.10. +Generating RTLIL representation for module `\O_BUF'. +Successfully finished Verilog frontend. + +4.14. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v' to AST representation. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v:10.1-341.10. +Generating RTLIL representation for module `\DSP38'. +Successfully finished Verilog frontend. + +4.15. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v' to AST representation. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:2.1-29.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:33.1-84.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\RS_DSP3'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:116.1-149.10. +Generating RTLIL representation for module `\DSP19X2'. +Successfully finished Verilog frontend. + +4.16. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v' to AST representation. +Generating RTLIL representation for module `\TDP_BRAM18'. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Generating RTLIL representation for module `\_$_mem_v2_asymmetric'. +Successfully finished Verilog frontend. + +4.17. Executing HIERARCHY pass (managing design hierarchy). + +4.17.1. Analyzing design hierarchy.. +Top module: \GJC48 + +4.17.2. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +4.18. Executing PROC pass (convert processes to netlists). + +4.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3 in module GJC48. +Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1 in module GJC48. +Removed a total of 0 dead cases. + +4.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 2 redundant assignments. +Promoted 0 assignments to connections. + +4.18.4. Executing PROC_INIT pass (extract init attributes). + +4.18.5. Executing PROC_ARST pass (detect async resets in processes). +Found async reset \reset_n in `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3'. +Found async reset \reset_n in `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1'. + +4.18.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +4.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3'. + 1/1: $0\dma_ack_out[3:0] +Creating decoders for process `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1'. + 1/1: $0\dma_req_reg[3:0] + +4.18.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +4.18.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\GJC48.\dma_ack_out' using process `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3'. + created $adff cell `$procdff$5' with positive edge clock and negative level reset. +Creating register for signal `\GJC48.\dma_req_reg' using process `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1'. + created $adff cell `$procdff$6' with positive edge clock and negative level reset. + +4.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3'. +Removing empty process `GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1'. +Cleaned up 0 empty switches. + +4.18.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.19. Executing FLATTEN pass (flatten design). + +# -------------------- +# Design entry stats +# -------------------- + +4.20. Printing statistics. + +=== GJC48 === + + Number of wires: 10 + Number of wire bits: 28 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + $adff 2 + $logic_not 2 + SOC_FPGA_INTF_DMA 1 + +4.21. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.22. Executing DEMUXMAP pass. + +4.23. Executing FLATTEN pass (flatten design). + +4.24. Executing DEMUXMAP pass. + +4.25. Executing TRIBUF pass. +Warning: Ignored -no_iobuf because -keep_tribuf is used. + +4.26. Executing DEMINOUT pass (demote inout ports to input or output). + +4.27. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 2 unused cells and 4 unused wires. + + +4.29. Executing CHECK pass (checking for obvious problems). +Checking module GJC48... +Found and reported 0 problems. + +4.30. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.31. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.32. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.33. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.34. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.35. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.36. Executing OPT_SHARE pass. + +4.37. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.38. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.40. Executing FSM pass (extract and optimize FSM). + +4.40.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.40.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.40.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.40.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.40.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.40.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.41. Executing WREDUCE pass (reducing word size of cells). + +4.42. Executing PEEPOPT pass (run peephole optimizers). + +4.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.44. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.45. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.46. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.47. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.48. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.49. Executing OPT_SHARE pass. + +4.50. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.51. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.52. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.53. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.54. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.55. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.56. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.57. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.58. Executing OPT_SHARE pass. + +4.59. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.60. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.61. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.62. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.63. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.64. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.65. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.66. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.67. Executing OPT_SHARE pass. + +4.68. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.69. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=4, #remove=0, time=0.00 sec.] + +4.70. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.71. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.72. Executing WREDUCE pass (reducing word size of cells). + +4.73. Executing PEEPOPT pass (run peephole optimizers). + +4.74. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.75. Executing DEMUXMAP pass. + +4.76. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.77. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.78. Executing RS_DSP_MULTADD pass. + +4.79. Executing WREDUCE pass (reducing word size of cells). + +4.80. Executing RS_DSP_MACC pass. + +4.81. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.82. Executing TECHMAP pass (map to technology primitives). + +4.82.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.82.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.83. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.84. Executing TECHMAP pass (map to technology primitives). + +4.84.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.84.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.85. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.86. Executing TECHMAP pass (map to technology primitives). + +4.86.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.86.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.87. Executing TECHMAP pass (map to technology primitives). + +4.87.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.87.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.88. Executing TECHMAP pass (map to technology primitives). + +4.88.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__RS_MUL20X18'. +Generating RTLIL representation for module `\$__RS_MUL10X9'. +Successfully finished Verilog frontend. + +4.88.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.89. Executing RS_DSP_SIMD pass. + +4.90. Executing TECHMAP pass (map to technology primitives). + +4.90.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v' to AST representation. +Generating RTLIL representation for module `\dsp_t1_20x18x64_cfg_ports'. +Generating RTLIL representation for module `\dsp_t1_10x9x32_cfg_params'. +Successfully finished Verilog frontend. + +4.90.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.91. Executing TECHMAP pass (map to technology primitives). + +4.91.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.91.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.92. Executing rs_pack_dsp_regs pass. + +4.93. Executing RS_DSP_IO_REGS pass. + +4.94. Executing TECHMAP pass (map to technology primitives). + +4.94.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSP_MULTACC'. +Generating RTLIL representation for module `\RS_DSP_MULT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN_REGOUT'. +Successfully finished Verilog frontend. + +4.94.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.95. Executing TECHMAP pass (map to technology primitives). + +4.95.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.95.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.96. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.97. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module GJC48: + created 0 $alu and 0 $macc cells. + +4.98. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.99. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.100. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.101. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.102. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.103. Executing OPT_SHARE pass. + +4.104. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.105. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.106. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.107. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.108. Executing MEMORY pass. + +4.108.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.108.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.108.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.108.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.108.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.108.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.108.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.108.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.108.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.108.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.109. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.110. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.111. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.112. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.113. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.114. Executing Rs_BRAM_Split pass. + +4.115. Executing TECHMAP pass (map to technology primitives). + +4.115.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_SDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_SDP'. +Successfully finished Verilog frontend. + +4.115.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.116. Executing TECHMAP pass (map to technology primitives). + +4.116.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Successfully finished Verilog frontend. + +4.116.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.117. Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs). + +4.118. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.119. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.120. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.121. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.122. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.123. Executing OPT_SHARE pass. + +4.124. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.125. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.126. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.127. Executing PMUXTREE pass. + +4.128. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.129. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +4.130. Executing TECHMAP pass (map to technology primitives). + +4.130.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.130.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_rs_alu'. +Successfully finished Verilog frontend. + +4.130.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $adff. +No more expansions possible. + + +4.131. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + +4.132. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.133. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.134. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.135. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.136. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.137. Executing OPT_SHARE pass. + +4.138. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.139. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.140. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.141. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.142. Executing TECHMAP pass (map to technology primitives). + +4.142.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.142.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.143. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + +4.144. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.145. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.146. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.147. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.148. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.149. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.150. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.151. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.152. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.153. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.154. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.155. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.156. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.157. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.158. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.159. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.160. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.161. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.162. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.163. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.164. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.165. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.166. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=4, #remove=0, time=0.00 sec.] + +4.167. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.168. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.169. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + + Number of Generic REGs: 8 + +ABC-DFF iteration : 1 + +4.170. Executing ABC pass (technology mapping using ABC). + +4.170.1. Summary of detected clock domains: + 9 cells in clk=\clk, en={ }, arst=!\reset_n, srst={ } + + #logic partitions = 1 + +4.170.2. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Found matching posedge clock domain: \clk, asynchronously reset by !\reset_n +Extracted 8 gates and 16 wires to a netlist network with 8 inputs and 8 outputs (dfl=1). + +4.170.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.171. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.172. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.173. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.174. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.175. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.176. Executing OPT_SHARE pass. + +4.177. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.178. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.179. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 2 + +4.180. Executing ABC pass (technology mapping using ABC). + +4.180.1. Summary of detected clock domains: + 9 cells in clk=\clk, en={ }, arst=!\reset_n, srst={ } + + #logic partitions = 1 + +4.180.2. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Found matching posedge clock domain: \clk, asynchronously reset by !\reset_n +Extracted 8 gates and 16 wires to a netlist network with 8 inputs and 8 outputs (dfl=1). + +4.180.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.181. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.182. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.183. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.184. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.185. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.186. Executing OPT_SHARE pass. + +4.187. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.188. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.189. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 3 + +4.190. Executing ABC pass (technology mapping using ABC). + +4.190.1. Summary of detected clock domains: + 9 cells in clk=\clk, en={ }, arst=!\reset_n, srst={ } + + #logic partitions = 1 + +4.190.2. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Found matching posedge clock domain: \clk, asynchronously reset by !\reset_n +Extracted 8 gates and 16 wires to a netlist network with 8 inputs and 8 outputs (dfl=2). + +4.190.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.191. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.192. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.193. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.194. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.195. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.196. Executing OPT_SHARE pass. + +4.197. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.198. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.199. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 4 + +4.200. Executing ABC pass (technology mapping using ABC). + +4.200.1. Summary of detected clock domains: + 9 cells in clk=\clk, en={ }, arst=!\reset_n, srst={ } + + #logic partitions = 1 + +4.200.2. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Found matching posedge clock domain: \clk, asynchronously reset by !\reset_n +Extracted 8 gates and 16 wires to a netlist network with 8 inputs and 8 outputs (dfl=2). + +4.200.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.201. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.202. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.203. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.204. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.205. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.206. Executing OPT_SHARE pass. + +4.207. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.208. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.209. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 +select with DFL2 synthesis (thresh-logic=0.920000, thresh_dff=0.980000) + +4.210. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.211. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.212. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.213. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.214. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.215. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.216. Executing OPT_SHARE pass. + +4.217. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.218. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.219. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.220. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.221. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.222. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.223. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.224. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.225. Executing OPT_SHARE pass. + +4.226. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.227. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.228. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.229. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.230. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.231. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.232. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.233. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.234. Executing OPT_SHARE pass. + +4.235. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.236. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=4, #remove=0, time=0.00 sec.] + +4.237. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.238. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.239. Executing BMUXMAP pass. + +4.240. Executing DEMUXMAP pass. + +4.241. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.242. Executing ABC pass (technology mapping using ABC). + +4.242.1. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs (dfl=1). +Don't call ABC as there is nothing to map. + +4.243. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.244. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.245. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.246. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.247. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.248. Executing OPT_SHARE pass. + +4.249. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.250. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.251. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.252. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.253. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.254. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.255. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.256. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.257. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.258. Executing OPT_SHARE pass. + +4.259. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.260. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.261. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.262. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.263. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.264. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.265. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.266. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.267. Executing OPT_SHARE pass. + +4.268. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.269. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=4, #remove=0, time=0.00 sec.] + +4.270. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.271. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.272. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + +4.273. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +4.274. Executing RS_DFFSR_CONV pass. + +4.275. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + +4.276. Executing TECHMAP pass (map to technology primitives). + +4.276.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.276.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PN0P_'. +Generating RTLIL representation for module `\$_DFFE_PN0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_DFFE_PN1P_'. +Generating RTLIL representation for module `\$_DFFE_PN1N_'. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NN0P_'. +Generating RTLIL representation for module `\$_DFFE_NN0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_NN1P_'. +Generating RTLIL representation for module `\$_DFFE_NN1N_'. +Generating RTLIL representation for module `\$__SHREG_DFF_P_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PN0_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NN0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_PN1_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_NN1_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_PP0_'. +Generating RTLIL representation for module `\$_DLATCH_PN0_'. +Generating RTLIL representation for module `\$_DLATCH_NP0_'. +Generating RTLIL representation for module `\$_DLATCH_NN0_'. +Generating RTLIL representation for module `\$_DLATCH_PP1_'. +Generating RTLIL representation for module `\$_DLATCH_PN1_'. +Generating RTLIL representation for module `\$_DLATCH_NP1_'. +Generating RTLIL representation for module `\$_DLATCH_NN1_'. +Successfully finished Verilog frontend. + +4.276.3. Continuing TECHMAP pass. +No more expansions possible. + + +4.277. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.278. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +4.279. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.280. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.281. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.282. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.283. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.284. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.285. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.286. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.287. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.288. Executing OPT_SHARE pass. + +4.289. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.290. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.291. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.292. Executing TECHMAP pass (map to technology primitives). + +4.292.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.292.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.293. Executing ABC pass (technology mapping using ABC). + +4.293.1. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs (dfl=1). +Don't call ABC as there is nothing to map. + +4.294. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.295. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.296. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.297. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.298. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.299. Executing OPT_SHARE pass. + +4.300. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.301. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.302. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.303. Executing HIERARCHY pass (managing design hierarchy). + +4.303.1. Analyzing design hierarchy.. +Top module: \GJC48 + +4.303.2. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +4.304. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.305. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__IO_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.306. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Replacing existing blackbox module `\BOOT_CLOCK' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:9.1-14.10. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:24.1-31.10. +Generating RTLIL representation for module `\CARRY'. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:41.1-46.10. +Generating RTLIL representation for module `\CLK_BUF'. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:56.1-64.10. +Generating RTLIL representation for module `\DFFNRE'. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:74.1-82.10. +Generating RTLIL representation for module `\DFFRE'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:92.1-126.10. +Generating RTLIL representation for module `\DSP19X2'. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:136.1-162.10. +Generating RTLIL representation for module `\DSP38'. +Replacing existing blackbox module `\FCLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:172.1-176.10. +Generating RTLIL representation for module `\FCLK_BUF'. +Replacing existing blackbox module `\FIFO18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:186.1-233.10. +Generating RTLIL representation for module `\FIFO18KX2'. +Replacing existing blackbox module `\FIFO36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:243.1-268.10. +Generating RTLIL representation for module `\FIFO36K'. +Replacing existing blackbox module `\I_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:278.1-290.10. +Generating RTLIL representation for module `\I_BUF_DS'. +Replacing existing blackbox module `\I_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:300.1-309.10. +Generating RTLIL representation for module `\I_BUF'. +Replacing existing blackbox module `\I_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:319.1-327.10. +Generating RTLIL representation for module `\I_DDR'. +Replacing existing blackbox module `\I_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:337.1-349.10. +Generating RTLIL representation for module `\I_DELAY'. +Replacing existing blackbox module `\I_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:359.1-363.10. +Generating RTLIL representation for module `\I_FAB'. +Replacing existing blackbox module `\I_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:373.1-392.10. +Generating RTLIL representation for module `\I_SERDES'. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:402.1-408.10. +Generating RTLIL representation for module `\LUT1'. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:418.1-424.10. +Generating RTLIL representation for module `\LUT2'. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:434.1-440.10. +Generating RTLIL representation for module `\LUT3'. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:450.1-456.10. +Generating RTLIL representation for module `\LUT4'. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:466.1-472.10. +Generating RTLIL representation for module `\LUT5'. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:482.1-488.10. +Generating RTLIL representation for module `\LUT6'. +Replacing existing blackbox module `\O_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:498.1-510.10. +Generating RTLIL representation for module `\O_BUF_DS'. +Replacing existing blackbox module `\O_BUFT_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:520.1-532.10. +Generating RTLIL representation for module `\O_BUFT_DS'. +Replacing existing blackbox module `\O_BUFT' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:542.1-553.10. +Generating RTLIL representation for module `\O_BUFT'. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:563.1-574.10. +Generating RTLIL representation for module `\O_BUF'. +Replacing existing blackbox module `\O_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:584.1-592.10. +Generating RTLIL representation for module `\O_DDR'. +Replacing existing blackbox module `\O_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:602.1-614.10. +Generating RTLIL representation for module `\O_DELAY'. +Replacing existing blackbox module `\O_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:624.1-628.10. +Generating RTLIL representation for module `\O_FAB'. +Replacing existing blackbox module `\O_SERDES_CLK' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:638.1-647.10. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Replacing existing blackbox module `\O_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:657.1-674.10. +Generating RTLIL representation for module `\O_SERDES'. +Replacing existing blackbox module `\PLL' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:684.1-702.10. +Generating RTLIL representation for module `\PLL'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_M' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:712.1-726.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_S' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:736.1-753.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M0' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:763.1-802.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M1' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:812.1-851.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Replacing existing blackbox module `\SOC_FPGA_INTF_DMA' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:861.1-867.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Replacing existing blackbox module `\SOC_FPGA_INTF_IRQ' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:877.1-883.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Replacing existing blackbox module `\SOC_FPGA_INTF_JTAG' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:893.1-901.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Replacing existing blackbox module `\SOC_FPGA_TEMPERATURE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:911.1-919.10. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:929.1-984.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:994.1-1023.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1040.1-1045.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1053.1-1058.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1067.1-1073.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1081.1-1087.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1096.1-1102.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1111.1-1117.10. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + *************************** + Inserting Input Buffers + *************************** +WARNING: port '\clk' has no associated I_BUF +WARNING: port '\dma_req_in' has no associated I_BUF +WARNING: port '\reset_n' has no associated I_BUF + *************************** + Inserting Clock Buffers + *************************** +INFO: inserting CLK_BUF before '$ibuf_clk' + ***************************** + Inserting Output Buffers + ***************************** +WARNING: OUTPUT port '\dma_ack_out' has no associated O_BUF + ***************************** + Mapping Tri-state Buffers + ***************************** + +4.307. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.308. Executing TECHMAP pass (map to technology primitives). + +4.308.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.308.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.309. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 30 unused wires. + + +4.310. Printing statistics. + +=== GJC48 === + + Number of wires: 11 + Number of wire bits: 29 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUF 4 + SOC_FPGA_INTF_DMA 1 + +4.311. Executing TECHMAP pass (map to technology primitives). + +4.311.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v' to AST representation. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +4.311.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.312. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.313. Printing statistics. + +=== GJC48 === + + Number of wires: 11 + Number of wire bits: 29 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUF 4 + SOC_FPGA_INTF_DMA 1 + + ***************************** + Rewire_Obuft + ***************************** + +========================== +Post Design clean up ... + +Split to bits ... + +4.314. Executing SPLITNETS pass (splitting up multi-bit signals). + +Split into bits ... [0.00 sec.] +Building Sig2cells ... [0.00 sec.] +Building Sig2sig ... [0.00 sec.] +Backward clean up ... [0.00 sec.] +Before cleanup : + +4.315. Printing statistics. + +=== GJC48 === + + Number of wires: 23 + Number of wire bits: 29 + Number of public wires: 12 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUFT 4 + SOC_FPGA_INTF_DMA 1 + + -------------------------- + Removed assigns : 0 + Removed wires : 0 + Removed cells : 0 + -------------------------- +After cleanup : + +4.316. Printing statistics. + +=== GJC48 === + + Number of wires: 23 + Number of wire bits: 29 + Number of public wires: 12 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUFT 4 + SOC_FPGA_INTF_DMA 1 + + +Total time for 'obs_clean' ... + [0.00 sec.] + +4.317. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.318. Executing HIERARCHY pass (managing design hierarchy). + +4.318.1. Analyzing design hierarchy.. +Top module: \GJC48 + +4.318.2. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +Dumping port properties into 'netlist_info.json' file. + + +Inserting I_FAB/O_FAB cells ... + + +Inserting I_FAB/O_FAB cells done. + +4.319. Printing statistics. + +=== GJC48 === + + Number of wires: 23 + Number of wire bits: 29 + Number of public wires: 12 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUFT 4 + SOC_FPGA_INTF_DMA 1 + + Number of LUTs: 0 + Number of REGs: 8 + Number of CARRY ADDERs: 0 + +4.320. Executing Verilog backend. +Dumping module `\GJC48'. + +# -------------------- +# Core Synthesis done +# -------------------- + +4.321. Executing Verilog backend. +Dumping module `\GJC48'. + +4.321.1. Executing BLIF backend. + +-- Running command `write_rtlil design.rtlil' -- + +4.321.2. Executing RTLIL backend. +Output filename: design.rtlil + +4.321.3. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.321.4. Executing FLATTEN pass (flatten design). +Deleting now unused module interface_GJC48. + + +4.321.5. Executing Verilog backend. +Dumping module `\GJC48'. + +4.321.5.1. Executing BLIF backend. + +4.321.5.2. Executing Verilog backend. +Dumping module `\GJC48'. + +4.321.5.2.1. Executing BLIF backend. + +4.321.5.2.2. Executing Verilog backend. +Dumping module `\fabric_GJC48'. + +4.321.5.2.2.1. Executing BLIF backend. + +Warnings: 1 unique messages, 1 total +End of script. Logfile hash: 0f3c69f369, CPU: user 0.72s system 0.09s, MEM: 112.07 MB peak +Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) +Time spent: 31% 43x read_verilog (0 sec), 19% 6x abc (0 sec), ... diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/wrapper_GJC48_post_synth.eblif b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/wrapper_GJC48_post_synth.eblif new file mode 100644 index 00000000..fb14443f --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/wrapper_GJC48_post_synth.eblif @@ -0,0 +1,105 @@ +# Generated by Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) + +.model GJC48 +.inputs clk reset_n dma_req_in[0] dma_req_in[1] dma_req_in[2] dma_req_in[3] +.outputs dma_ack_out[0] dma_ack_out[1] dma_ack_out[2] dma_ack_out[3] +.names $false +.names $true +1 +.names $undef +.subckt fabric_GJC48 $auto_524=$auto_524 $auto_525=$auto_525 $auto_526=$auto_526 $auto_527=$auto_527 $auto_528=$auto_528 $auto_529=$auto_529 $auto_530=$auto_530 $auto_531=$auto_531 $auto_532=$auto_532 $auto_533=$auto_533 $clk_buf_$ibuf_clk=$clk_buf_$ibuf_clk $ibuf_dma_req_in[0]=$ibuf_dma_req_in[0] $ibuf_dma_req_in[1]=$ibuf_dma_req_in[1] $ibuf_dma_req_in[2]=$ibuf_dma_req_in[2] $ibuf_dma_req_in[3]=$ibuf_dma_req_in[3] $ibuf_reset_n=$ibuf_reset_n $obuf_dma_ack_out[0]=$obuf_dma_ack_out[0] $obuf_dma_ack_out[1]=$obuf_dma_ack_out[1] $obuf_dma_ack_out[2]=$obuf_dma_ack_out[2] $obuf_dma_ack_out[3]=$obuf_dma_ack_out[3] dma_ack_reg[0]=dma_ack_reg[0] dma_ack_reg[1]=dma_ack_reg[1] dma_ack_reg[2]=dma_ack_reg[2] dma_ack_reg[3]=dma_ack_reg[3] dma_req_reg[0]=dma_req_reg[0] dma_req_reg[1]=dma_req_reg[1] dma_req_reg[2]=dma_req_reg[2] dma_req_reg[3]=dma_req_reg[3] +.subckt SOC_FPGA_INTF_DMA DMA_ACK[0]=$auto_535.dma_ack_reg[0] DMA_ACK[1]=$auto_535.dma_ack_reg[1] DMA_ACK[2]=$auto_535.dma_ack_reg[2] DMA_ACK[3]=$auto_535.dma_ack_reg[3] DMA_CLK=$flatten$auto_535.$ibuf_clk DMA_REQ[0]=$auto_535.dma_req_reg[0] DMA_REQ[1]=$auto_535.dma_req_reg[1] DMA_REQ[2]=$auto_535.dma_req_reg[2] DMA_REQ[3]=$auto_535.dma_req_reg[3] DMA_RST_N=$flatten$auto_535.$ibuf_reset_n +.subckt CLK_BUF I=$flatten$auto_535.$ibuf_clk O=$flatten$auto_535.$clk_buf_$ibuf_clk +.subckt I_BUF EN=$flatten$auto_535.$auto_524 I=$auto_535.clk O=$flatten$auto_535.$ibuf_clk +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$flatten$auto_535.$auto_525 I=$auto_535.dma_req_in[0] O=$flatten$auto_535.$ibuf_dma_req_in[0] +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$flatten$auto_535.$auto_526 I=$auto_535.dma_req_in[1] O=$flatten$auto_535.$ibuf_dma_req_in[1] +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$flatten$auto_535.$auto_527 I=$auto_535.dma_req_in[2] O=$flatten$auto_535.$ibuf_dma_req_in[2] +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$flatten$auto_535.$auto_528 I=$auto_535.dma_req_in[3] O=$flatten$auto_535.$ibuf_dma_req_in[3] +.param WEAK_KEEPER "NONE" +.subckt I_BUF EN=$flatten$auto_535.$auto_529 I=$auto_535.reset_n O=$flatten$auto_535.$ibuf_reset_n +.param WEAK_KEEPER "NONE" +.subckt O_BUFT I=$flatten$auto_535.$obuf_dma_ack_out[0] O=$auto_535.dma_ack_out[0] T=$flatten$auto_535.$auto_530 +.subckt O_BUFT I=$flatten$auto_535.$obuf_dma_ack_out[1] O=$auto_535.dma_ack_out[1] T=$flatten$auto_535.$auto_531 +.subckt O_BUFT I=$flatten$auto_535.$obuf_dma_ack_out[2] O=$auto_535.dma_ack_out[2] T=$flatten$auto_535.$auto_532 +.subckt O_BUFT I=$flatten$auto_535.$obuf_dma_ack_out[3] O=$auto_535.dma_ack_out[3] T=$flatten$auto_535.$auto_533 +.names $auto_533 $flatten$auto_535.$auto_533 +1 1 +.names $auto_532 $flatten$auto_535.$auto_532 +1 1 +.names $auto_531 $flatten$auto_535.$auto_531 +1 1 +.names $auto_530 $flatten$auto_535.$auto_530 +1 1 +.names $auto_529 $flatten$auto_535.$auto_529 +1 1 +.names $auto_528 $flatten$auto_535.$auto_528 +1 1 +.names $auto_527 $flatten$auto_535.$auto_527 +1 1 +.names $auto_526 $flatten$auto_535.$auto_526 +1 1 +.names $auto_525 $flatten$auto_535.$auto_525 +1 1 +.names $auto_524 $flatten$auto_535.$auto_524 +1 1 +.names $flatten$auto_535.$clk_buf_$ibuf_clk $clk_buf_$ibuf_clk +1 1 +.names $flatten$auto_535.$ibuf_dma_req_in[0] $ibuf_dma_req_in[0] +1 1 +.names $flatten$auto_535.$ibuf_dma_req_in[1] $ibuf_dma_req_in[1] +1 1 +.names $flatten$auto_535.$ibuf_dma_req_in[2] $ibuf_dma_req_in[2] +1 1 +.names $flatten$auto_535.$ibuf_dma_req_in[3] $ibuf_dma_req_in[3] +1 1 +.names $flatten$auto_535.$ibuf_reset_n $ibuf_reset_n +1 1 +.names $obuf_dma_ack_out[0] $flatten$auto_535.$obuf_dma_ack_out[0] +1 1 +.names $obuf_dma_ack_out[1] $flatten$auto_535.$obuf_dma_ack_out[1] +1 1 +.names $obuf_dma_ack_out[2] $flatten$auto_535.$obuf_dma_ack_out[2] +1 1 +.names $obuf_dma_ack_out[3] $flatten$auto_535.$obuf_dma_ack_out[3] +1 1 +.names clk $auto_535.clk +1 1 +.names $auto_535.dma_ack_out[0] dma_ack_out[0] +1 1 +.names $auto_535.dma_ack_out[1] dma_ack_out[1] +1 1 +.names $auto_535.dma_ack_out[2] dma_ack_out[2] +1 1 +.names $auto_535.dma_ack_out[3] dma_ack_out[3] +1 1 +.names $auto_535.dma_ack_reg[0] dma_ack_reg[0] +1 1 +.names $auto_535.dma_ack_reg[1] dma_ack_reg[1] +1 1 +.names $auto_535.dma_ack_reg[2] dma_ack_reg[2] +1 1 +.names $auto_535.dma_ack_reg[3] dma_ack_reg[3] +1 1 +.names dma_req_in[0] $auto_535.dma_req_in[0] +1 1 +.names dma_req_in[1] $auto_535.dma_req_in[1] +1 1 +.names dma_req_in[2] $auto_535.dma_req_in[2] +1 1 +.names dma_req_in[3] $auto_535.dma_req_in[3] +1 1 +.names dma_req_reg[0] $auto_535.dma_req_reg[0] +1 1 +.names dma_req_reg[1] $auto_535.dma_req_reg[1] +1 1 +.names dma_req_reg[2] $auto_535.dma_req_reg[2] +1 1 +.names dma_req_reg[3] $auto_535.dma_req_reg[3] +1 1 +.names reset_n $auto_535.reset_n +1 1 +.end diff --git a/EDA-3164/GJC48/run_1/synth_1_1/synthesis/wrapper_GJC48_post_synth.v b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/wrapper_GJC48_post_synth.v new file mode 100644 index 00000000..822e22fa --- /dev/null +++ b/EDA-3164/GJC48/run_1/synth_1_1/synthesis/wrapper_GJC48_post_synth.v @@ -0,0 +1,313 @@ +/* Generated by Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) */ + +module GJC48(clk, reset_n, dma_req_in, dma_ack_out); + input clk; + output [3:0] dma_ack_out; + input [3:0] dma_req_in; + input reset_n; + wire \$auto_524 ; + wire \$auto_525 ; + wire \$auto_526 ; + wire \$auto_527 ; + wire \$auto_528 ; + wire \$auto_529 ; + wire \$auto_530 ; + wire \$auto_531 ; + wire \$auto_532 ; + wire \$auto_533 ; + (* keep = 32'd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" *) + wire \$auto_535.clk ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire [3:0] \$auto_535.dma_ack_out ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \$auto_535.dma_ack_reg[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \$auto_535.dma_ack_reg[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \$auto_535.dma_ack_reg[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \$auto_535.dma_ack_reg[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire [3:0] \$auto_535.dma_req_in ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \$auto_535.dma_req_reg[0] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \$auto_535.dma_req_reg[1] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \$auto_535.dma_req_reg[2] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \$auto_535.dma_req_reg[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + wire \$auto_535.reset_n ; + wire \$clk_buf_$ibuf_clk ; + wire \$flatten$auto_535.$auto_524 ; + wire \$flatten$auto_535.$auto_525 ; + wire \$flatten$auto_535.$auto_526 ; + wire \$flatten$auto_535.$auto_527 ; + wire \$flatten$auto_535.$auto_528 ; + wire \$flatten$auto_535.$auto_529 ; + wire \$flatten$auto_535.$auto_530 ; + wire \$flatten$auto_535.$auto_531 ; + wire \$flatten$auto_535.$auto_532 ; + wire \$flatten$auto_535.$auto_533 ; + wire \$flatten$auto_535.$clk_buf_$ibuf_clk ; + (* keep = 32'd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" *) + wire \$flatten$auto_535.$ibuf_clk ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$flatten$auto_535.$ibuf_dma_req_in[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$flatten$auto_535.$ibuf_dma_req_in[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$flatten$auto_535.$ibuf_dma_req_in[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$flatten$auto_535.$ibuf_dma_req_in[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + wire \$flatten$auto_535.$ibuf_reset_n ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$flatten$auto_535.$obuf_dma_ack_out[0] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$flatten$auto_535.$obuf_dma_ack_out[1] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$flatten$auto_535.$obuf_dma_ack_out[2] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$flatten$auto_535.$obuf_dma_ack_out[3] ; + (* keep = 32'd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" *) + wire \$ibuf_clk ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire \$ibuf_dma_req_in[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + wire \$ibuf_reset_n ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[0] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[1] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[2] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire \$obuf_dma_ack_out[3] ; + (* keep = 32'd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" *) + (* keep = 32'd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:2.14-2.17" *) + wire clk; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:5.20-5.31" *) + wire [3:0] dma_ack_out; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[0] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[1] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[2] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:9.13-9.24" *) + wire \dma_ack_reg[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:4.20-4.30" *) + wire [3:0] dma_req_in; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[0] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[1] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[2] ; + (* keep = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:8.13-8.24" *) + wire \dma_req_reg[3] ; + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:3.14-3.21" *) + wire reset_n; + fabric_GJC48 \$auto_534 ( + .\$auto_524 (\$auto_524 ), + .\$auto_525 (\$auto_525 ), + .\$auto_526 (\$auto_526 ), + .\$auto_527 (\$auto_527 ), + .\$auto_528 (\$auto_528 ), + .\$auto_529 (\$auto_529 ), + .\$auto_530 (\$auto_530 ), + .\$auto_531 (\$auto_531 ), + .\$auto_532 (\$auto_532 ), + .\$auto_533 (\$auto_533 ), + .\$clk_buf_$ibuf_clk (\$clk_buf_$ibuf_clk ), + .\$ibuf_dma_req_in[0] (\$ibuf_dma_req_in[0] ), + .\$ibuf_dma_req_in[1] (\$ibuf_dma_req_in[1] ), + .\$ibuf_dma_req_in[2] (\$ibuf_dma_req_in[2] ), + .\$ibuf_dma_req_in[3] (\$ibuf_dma_req_in[3] ), + .\$ibuf_reset_n (\$ibuf_reset_n ), + .\$obuf_dma_ack_out[0] (\$obuf_dma_ack_out[0] ), + .\$obuf_dma_ack_out[1] (\$obuf_dma_ack_out[1] ), + .\$obuf_dma_ack_out[2] (\$obuf_dma_ack_out[2] ), + .\$obuf_dma_ack_out[3] (\$obuf_dma_ack_out[3] ), + .\dma_ack_reg[0] (\dma_ack_reg[0] ), + .\dma_ack_reg[1] (\dma_ack_reg[1] ), + .\dma_ack_reg[2] (\dma_ack_reg[2] ), + .\dma_ack_reg[3] (\dma_ack_reg[3] ), + .\dma_req_reg[0] (\dma_req_reg[0] ), + .\dma_req_reg[1] (\dma_req_reg[1] ), + .\dma_req_reg[2] (\dma_req_reg[2] ), + .\dma_req_reg[3] (\dma_req_reg[3] ) + ); + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:12.21-17.4" *) + SOC_FPGA_INTF_DMA \$auto_535.dma_inst ( + .DMA_ACK({ \$auto_535.dma_ack_reg[3] , \$auto_535.dma_ack_reg[2] , \$auto_535.dma_ack_reg[1] , \$auto_535.dma_ack_reg[0] }), + .DMA_CLK(\$flatten$auto_535.$ibuf_clk ), + .DMA_REQ({ \$auto_535.dma_req_reg[3] , \$auto_535.dma_req_reg[2] , \$auto_535.dma_req_reg[1] , \$auto_535.dma_req_reg[0] }), + .DMA_RST_N(\$flatten$auto_535.$ibuf_reset_n ) + ); + (* keep = 32'sd1 *) + CLK_BUF \$flatten$auto_535.$clkbuf$GJC48.$ibuf_clk ( + .I(\$flatten$auto_535.$ibuf_clk ), + .O(\$flatten$auto_535.$clk_buf_$ibuf_clk ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_535.$ibuf$GJC48.$ibuf_clk ( + .EN(\$flatten$auto_535.$auto_524 ), + .I(\$auto_535.clk ), + .O(\$flatten$auto_535.$ibuf_clk ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_535.$ibuf$GJC48.$ibuf_dma_req_in ( + .EN(\$flatten$auto_535.$auto_525 ), + .I(\$auto_535.dma_req_in [0]), + .O(\$flatten$auto_535.$ibuf_dma_req_in[0] ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_535.$ibuf$GJC48.$ibuf_dma_req_in_1 ( + .EN(\$flatten$auto_535.$auto_526 ), + .I(\$auto_535.dma_req_in [1]), + .O(\$flatten$auto_535.$ibuf_dma_req_in[1] ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_535.$ibuf$GJC48.$ibuf_dma_req_in_2 ( + .EN(\$flatten$auto_535.$auto_527 ), + .I(\$auto_535.dma_req_in [2]), + .O(\$flatten$auto_535.$ibuf_dma_req_in[2] ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_535.$ibuf$GJC48.$ibuf_dma_req_in_3 ( + .EN(\$flatten$auto_535.$auto_528 ), + .I(\$auto_535.dma_req_in [3]), + .O(\$flatten$auto_535.$ibuf_dma_req_in[3] ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$flatten$auto_535.$ibuf$GJC48.$ibuf_reset_n ( + .EN(\$flatten$auto_535.$auto_529 ), + .I(\$auto_535.reset_n ), + .O(\$flatten$auto_535.$ibuf_reset_n ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_535.$obuf$GJC48.$obuf_dma_ack_out ( + .I(\$flatten$auto_535.$obuf_dma_ack_out[0] ), + .O(\$auto_535.dma_ack_out [0]), + .T(\$flatten$auto_535.$auto_530 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_535.$obuf$GJC48.$obuf_dma_ack_out_1 ( + .I(\$flatten$auto_535.$obuf_dma_ack_out[1] ), + .O(\$auto_535.dma_ack_out [1]), + .T(\$flatten$auto_535.$auto_531 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_535.$obuf$GJC48.$obuf_dma_ack_out_2 ( + .I(\$flatten$auto_535.$obuf_dma_ack_out[2] ), + .O(\$auto_535.dma_ack_out [2]), + .T(\$flatten$auto_535.$auto_532 ) + ); + (* keep = 32'sd1 *) + (* module_not_derived = 32'sd1 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$flatten$auto_535.$obuf$GJC48.$obuf_dma_ack_out_3 ( + .I(\$flatten$auto_535.$obuf_dma_ack_out[3] ), + .O(\$auto_535.dma_ack_out [3]), + .T(\$flatten$auto_535.$auto_533 ) + ); + assign \$flatten$auto_535.$auto_533 = \$auto_533 ; + assign \$flatten$auto_535.$auto_532 = \$auto_532 ; + assign \$flatten$auto_535.$auto_531 = \$auto_531 ; + assign \$flatten$auto_535.$auto_530 = \$auto_530 ; + assign \$flatten$auto_535.$auto_529 = \$auto_529 ; + assign \$flatten$auto_535.$auto_528 = \$auto_528 ; + assign \$flatten$auto_535.$auto_527 = \$auto_527 ; + assign \$flatten$auto_535.$auto_526 = \$auto_526 ; + assign \$flatten$auto_535.$auto_525 = \$auto_525 ; + assign \$flatten$auto_535.$auto_524 = \$auto_524 ; + assign \$clk_buf_$ibuf_clk = \$flatten$auto_535.$clk_buf_$ibuf_clk ; + assign \$ibuf_dma_req_in[0] = \$flatten$auto_535.$ibuf_dma_req_in[0] ; + assign \$ibuf_dma_req_in[1] = \$flatten$auto_535.$ibuf_dma_req_in[1] ; + assign \$ibuf_dma_req_in[2] = \$flatten$auto_535.$ibuf_dma_req_in[2] ; + assign \$ibuf_dma_req_in[3] = \$flatten$auto_535.$ibuf_dma_req_in[3] ; + assign \$ibuf_reset_n = \$flatten$auto_535.$ibuf_reset_n ; + assign \$flatten$auto_535.$obuf_dma_ack_out[0] = \$obuf_dma_ack_out[0] ; + assign \$flatten$auto_535.$obuf_dma_ack_out[1] = \$obuf_dma_ack_out[1] ; + assign \$flatten$auto_535.$obuf_dma_ack_out[2] = \$obuf_dma_ack_out[2] ; + assign \$flatten$auto_535.$obuf_dma_ack_out[3] = \$obuf_dma_ack_out[3] ; + assign \$auto_535.clk = clk; + assign dma_ack_out = \$auto_535.dma_ack_out ; + assign \dma_ack_reg[0] = \$auto_535.dma_ack_reg[0] ; + assign \dma_ack_reg[1] = \$auto_535.dma_ack_reg[1] ; + assign \dma_ack_reg[2] = \$auto_535.dma_ack_reg[2] ; + assign \dma_ack_reg[3] = \$auto_535.dma_ack_reg[3] ; + assign \$auto_535.dma_req_in = dma_req_in; + assign \$auto_535.dma_req_reg[0] = \dma_req_reg[0] ; + assign \$auto_535.dma_req_reg[1] = \dma_req_reg[1] ; + assign \$auto_535.dma_req_reg[2] = \dma_req_reg[2] ; + assign \$auto_535.dma_req_reg[3] = \dma_req_reg[3] ; + assign \$auto_535.reset_n = reset_n; +endmodule diff --git a/EDA-3164/co_sim_GJC48.v b/EDA-3164/co_sim_GJC48.v new file mode 100644 index 00000000..8fa9acf6 --- /dev/null +++ b/EDA-3164/co_sim_GJC48.v @@ -0,0 +1,69 @@ +`timescale 1ns/1ps +module co_sim_GJC48; +// Clock signals + reg clk; +// Reset signals + reg reset_n; + + reg [3:0] dma_req_in; + wire [3:0] dma_ack_out , dma_ack_out_netlist; + integer mismatch = 0; + +GJC48 golden (.*); + +`ifdef PNR + GJC48_post_route route_net (.*, .dma_ack_out(dma_ack_out_netlist) ); +`else + GJC48_post_synth synth_net (.*, .dma_ack_out(dma_ack_out_netlist) ); +`endif + +// clock initialization for clk +initial begin + clk = 1'b0; + forever #1 clk = ~clk; +end +//Reset Stimulus generation +initial begin + reset_n <= 0; + @(negedge clk); + {dma_req_in } <= 'd0; + reset_n <= 1; + @(negedge clk); + $display ("***Reset Test is applied***"); + @(negedge clk); + @(negedge clk); + compare(); + $display ("***Reset Test is ended***"); + //Random stimulus generation + repeat(100) @ (negedge clk) begin + dma_req_in <= $urandom(); + compare(); +end + + // ----------- Corner Case stimulus generation ----------- + dma_req_in <= 15; + compare(); + + if(mismatch == 0) + $display("**** All Comparison Matched *** \n Simulation Passed\n"); + else + $display("%0d comparison(s) mismatched\nERROR: SIM: Simulation Failed", mismatch); + repeat(200) @(posedge clk); + $finish; +end + +task compare(); + if ( dma_ack_out !== dma_ack_out_netlist ) begin + $display("Data Mismatch: Actual output: %0d, Netlist Output %0d, Time: %0t ", dma_ack_out, dma_ack_out_netlist, $time); + mismatch = mismatch+1; + end + else + $display("Data Matched: Actual output: %0d, Netlist Output %0d, Time: %0t ", dma_ack_out, dma_ack_out_netlist, $time); +endtask + +initial begin + $dumpfile("tb.vcd"); + $dumpvars; +end + +endmodule diff --git a/EDA-3164/constraints.sdc b/EDA-3164/constraints.sdc new file mode 100644 index 00000000..dfb900b4 --- /dev/null +++ b/EDA-3164/constraints.sdc @@ -0,0 +1 @@ +create_clock -period 10 clk \ No newline at end of file diff --git a/EDA-3164/pin_constraints.pin b/EDA-3164/pin_constraints.pin new file mode 100644 index 00000000..566df81a --- /dev/null +++ b/EDA-3164/pin_constraints.pin @@ -0,0 +1,12 @@ +set_pin_loc clk HP_1_CC_18_9P +set_pin_loc reset_n HP_1_2_1P + +set_pin_loc dma_req_in[0] HP_1_4_2P +set_pin_loc dma_req_in[1] HP_1_6_3P +set_pin_loc dma_req_in[2] HP_1_8_4P +set_pin_loc dma_req_in[3] HP_1_10_5P + +set_pin_loc dma_ack_out[0] HP_1_12_6P +set_pin_loc dma_ack_out[1] HP_1_14_7P +set_pin_loc dma_ack_out[2] HP_1_20_10P +set_pin_loc dma_ack_out[3] HP_1_22_11P diff --git a/EDA-3164/raptor.log b/EDA-3164/raptor.log new file mode 100644 index 00000000..aeba6175 --- /dev/null +++ b/EDA-3164/raptor.log @@ -0,0 +1,2570 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.08 +Build : 1.1.51 +Hash : c3b8064 +Date : Aug 27 2024 +Type : Engineering +Log Time : Tue Aug 27 07:54:43 2024 GMT + +INFO: Target device: 1VG28 +INFO: Device version: v1.6.244 +INFO: Target device: 1VG28 +INFO: Device version: v1.6.244 +INFO: ANL: ################################################## +INFO: ANL: Analysis for design: GJC48 +INFO: ANL: ################################################## +INFO: ANL: Analyze command: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/yosys -s /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48/run_1/synth_1_1/analysis/GJC48_analyzer.cmd +Command: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/yosys -s /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48/run_1/synth_1_1/analysis/GJC48_analyzer.cmd + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) + + +-- Executing script file `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48/run_1/synth_1_1/analysis/GJC48_analyzer.cmd' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v' to AST representation. +Generating RTLIL representation for module `\GJC48'. +Successfully finished Verilog frontend. + +-- Running command `hierarchy -auto-top' -- + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Finding top of design hierarchy.. +root of 1 design levels: GJC48 +Automatically selected GJC48 as design top module. + +3.2. Analyzing design hierarchy.. +Top module: \GJC48 + +3.3. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +Dumping file hier_info.json ... + Process module "SOC_FPGA_INTF_DMA" +Dumping file port_info.json ... + +End of script. Logfile hash: a43fb108da, CPU: user 0.03s system 0.01s, MEM: 111.64 MB peak +Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) +Time spent: 94% 4x read_verilog (0 sec), 4% 1x analyze (0 sec), ... +INFO: ANL: Design GJC48 is analyzed +INFO: ANL: Top Modules: GJC48 + +INFO: SYN: ################################################## +INFO: SYN: Synthesis for design: GJC48 +INFO: SYN: ################################################## +INFO: SYN: RS Synthesis +INFO: SYN: ################################################## +INFO: SYN: Analysis for design: GJC48 +INFO: SYN: ################################################## +INFO: SYN: Analyze command: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/yosys -s /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48/run_1/synth_1_1/analysis/GJC48_analyzer.cmd +Command: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/yosys -s /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48/run_1/synth_1_1/analysis/GJC48_analyzer.cmd + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) + + +-- Executing script file `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48/run_1/synth_1_1/analysis/GJC48_analyzer.cmd' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v' to AST representation. +Generating RTLIL representation for module `\GJC48'. +Successfully finished Verilog frontend. + +-- Running command `hierarchy -top GJC48' -- + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \GJC48 + +3.2. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +Dumping file hier_info.json ... + Process module "SOC_FPGA_INTF_DMA" +Dumping file port_info.json ... + +End of script. Logfile hash: 5a1a282c91, CPU: user 0.05s system 0.02s, MEM: 112.07 MB peak +Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) +Time spent: 95% 4x read_verilog (0 sec), 3% 1x analyze (0 sec), ... +INFO: SYN: Design GJC48 is analyzed +INFO: SYN: Top Modules: GJC48 + +INFO: SYN: Synthesis command: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/yosys -s GJC48.ys -l GJC48_synth.log +Command: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/yosys -s GJC48.ys -l GJC48_synth.log + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) + + +-- Executing script file `GJC48.ys' -- + +1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Generating RTLIL representation for module `\CARRY'. +Generating RTLIL representation for module `\CLK_BUF'. +Generating RTLIL representation for module `\DFFNRE'. +Generating RTLIL representation for module `\DFFRE'. +Generating RTLIL representation for module `\DSP19X2'. +Generating RTLIL representation for module `\DSP38'. +Generating RTLIL representation for module `\FCLK_BUF'. +Generating RTLIL representation for module `\FIFO18KX2'. +Generating RTLIL representation for module `\FIFO36K'. +Generating RTLIL representation for module `\I_BUF_DS'. +Generating RTLIL representation for module `\I_BUF'. +Generating RTLIL representation for module `\I_DDR'. +Generating RTLIL representation for module `\I_DELAY'. +Generating RTLIL representation for module `\I_FAB'. +Generating RTLIL representation for module `\I_SERDES'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\O_BUF_DS'. +Generating RTLIL representation for module `\O_BUFT_DS'. +Generating RTLIL representation for module `\O_BUFT'. +Generating RTLIL representation for module `\O_BUF'. +Generating RTLIL representation for module `\O_DDR'. +Generating RTLIL representation for module `\O_DELAY'. +Generating RTLIL representation for module `\O_FAB'. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Generating RTLIL representation for module `\O_SERDES'. +Generating RTLIL representation for module `\PLL'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\TDP_RAM36K'. +Generating RTLIL representation for module `\LATCH'. +Generating RTLIL representation for module `\LATCHN'. +Generating RTLIL representation for module `\LATCHR'. +Generating RTLIL representation for module `\LATCHS'. +Generating RTLIL representation for module `\LATCHNR'. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v +Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v' to AST representation. +Generating RTLIL representation for module `\GJC48'. +Successfully finished Verilog frontend. + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \GJC48 + +3.2. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +4. Executing synth_rs pass: v0.4.218 + +4.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/common/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\inv'. +Generating RTLIL representation for module `\buff'. +Generating RTLIL representation for module `\logic_0'. +Generating RTLIL representation for module `\logic_1'. +Generating RTLIL representation for module `\gclkbuff'. +Successfully finished Verilog frontend. + +4.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v' to AST representation. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v:10.1-33.10. +Generating RTLIL representation for module `\CARRY'. +Successfully finished Verilog frontend. + +4.3. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v' to AST representation. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:20.1-34.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:48.1-62.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:81.1-97.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:115.1-131.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:150.1-166.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v:184.1-200.10. +Generating RTLIL representation for module `\LATCHNS'. +Generating RTLIL representation for module `\LATCHSRE'. +Generating RTLIL representation for module `\LATCHNSRE'. +Successfully finished Verilog frontend. + +4.4. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v' to AST representation. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:11.1-81.10. +Generating RTLIL representation for module `\DFFRE'. +Successfully finished Verilog frontend. + +4.5. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v' to AST representation. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:11.1-80.10. +Generating RTLIL representation for module `\DFFNRE'. +Successfully finished Verilog frontend. + +4.6. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v' to AST representation. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v:10.1-20.10. +Generating RTLIL representation for module `\LUT1'. +Successfully finished Verilog frontend. + +4.7. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v' to AST representation. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v:10.1-21.10. +Generating RTLIL representation for module `\LUT2'. +Successfully finished Verilog frontend. + +4.8. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v' to AST representation. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v:10.1-22.10. +Generating RTLIL representation for module `\LUT3'. +Successfully finished Verilog frontend. + +4.9. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v' to AST representation. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v:11.1-25.10. +Generating RTLIL representation for module `\LUT4'. +Successfully finished Verilog frontend. + +4.10. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v' to AST representation. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v:10.1-24.10. +Generating RTLIL representation for module `\LUT5'. +Successfully finished Verilog frontend. + +4.11. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v' to AST representation. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v:10.1-25.10. +Generating RTLIL representation for module `\LUT6'. +Successfully finished Verilog frontend. + +4.12. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v' to AST representation. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v:10.1-25.10. +Generating RTLIL representation for module `\CLK_BUF'. +Successfully finished Verilog frontend. + +4.13. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v' to AST representation. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v:10.1-84.10. +Generating RTLIL representation for module `\O_BUF'. +Successfully finished Verilog frontend. + +4.14. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v' to AST representation. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v:10.1-341.10. +Generating RTLIL representation for module `\DSP38'. +Successfully finished Verilog frontend. + +4.15. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v' to AST representation. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:2.1-29.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:33.1-84.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Generating RTLIL representation for module `\RS_DSP3'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v:116.1-149.10. +Generating RTLIL representation for module `\DSP19X2'. +Successfully finished Verilog frontend. + +4.16. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v' to AST representation. +Generating RTLIL representation for module `\TDP_BRAM18'. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Generating RTLIL representation for module `\_$_mem_v2_asymmetric'. +Successfully finished Verilog frontend. + +4.17. Executing HIERARCHY pass (managing design hierarchy). + +4.17.1. Analyzing design hierarchy.. +Top module: \GJC48 + +4.17.2. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +4.18. Executing PROC pass (convert processes to netlists). + +4.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3 in module GJC48. +Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1 in module GJC48. +Removed a total of 0 dead cases. + +4.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 2 redundant assignments. +Promoted 0 assignments to connections. + +4.18.4. Executing PROC_INIT pass (extract init attributes). + +4.18.5. Executing PROC_ARST pass (detect async resets in processes). +Found async reset \reset_n in `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3'. +Found async reset \reset_n in `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1'. + +4.18.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +4.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3'. + 1/1: $0\dma_ack_out[3:0] +Creating decoders for process `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1'. + 1/1: $0\dma_req_reg[3:0] + +4.18.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +4.18.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\GJC48.\dma_ack_out' using process `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3'. + created $adff cell `$procdff$5' with positive edge clock and negative level reset. +Creating register for signal `\GJC48.\dma_req_reg' using process `\GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1'. + created $adff cell `$procdff$6' with positive edge clock and negative level reset. + +4.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:30$3'. +Removing empty process `GJC48.$proc$/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48.v:20$1'. +Cleaned up 0 empty switches. + +4.18.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.19. Executing FLATTEN pass (flatten design). + +# -------------------- +# Design entry stats +# -------------------- + +4.20. Printing statistics. + +=== GJC48 === + + Number of wires: 10 + Number of wire bits: 28 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + $adff 2 + $logic_not 2 + SOC_FPGA_INTF_DMA 1 + +4.21. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.22. Executing DEMUXMAP pass. + +4.23. Executing FLATTEN pass (flatten design). + +4.24. Executing DEMUXMAP pass. + +4.25. Executing TRIBUF pass. +Warning: Ignored -no_iobuf because -keep_tribuf is used. + +4.26. Executing DEMINOUT pass (demote inout ports to input or output). + +4.27. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 2 unused cells and 4 unused wires. + + +4.29. Executing CHECK pass (checking for obvious problems). +Checking module GJC48... +Found and reported 0 problems. + +4.30. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.31. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.32. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.33. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.34. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.35. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.36. Executing OPT_SHARE pass. + +4.37. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.38. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.40. Executing FSM pass (extract and optimize FSM). + +4.40.1. Executing FSM_DETECT pass (finding FSMs in design). + +4.40.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +4.40.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.40.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +4.40.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +4.40.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +4.40.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +4.41. Executing WREDUCE pass (reducing word size of cells). + +4.42. Executing PEEPOPT pass (run peephole optimizers). + +4.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.44. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.45. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.46. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.47. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.48. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.49. Executing OPT_SHARE pass. + +4.50. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.51. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.52. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.53. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.54. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.55. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.56. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.57. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.58. Executing OPT_SHARE pass. + +4.59. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.60. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.61. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.62. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.63. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.64. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.65. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.66. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.67. Executing OPT_SHARE pass. + +4.68. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.69. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=4, #remove=0, time=0.00 sec.] + +4.70. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.71. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.72. Executing WREDUCE pass (reducing word size of cells). + +4.73. Executing PEEPOPT pass (run peephole optimizers). + +4.74. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.75. Executing DEMUXMAP pass. + +4.76. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.77. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.78. Executing RS_DSP_MULTADD pass. + +4.79. Executing WREDUCE pass (reducing word size of cells). + +4.80. Executing RS_DSP_MACC pass. + +4.81. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.82. Executing TECHMAP pass (map to technology primitives). + +4.82.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.82.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.83. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.84. Executing TECHMAP pass (map to technology primitives). + +4.84.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.84.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.85. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.86. Executing TECHMAP pass (map to technology primitives). + +4.86.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.86.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.87. Executing TECHMAP pass (map to technology primitives). + +4.87.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.87.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.88. Executing TECHMAP pass (map to technology primitives). + +4.88.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__RS_MUL20X18'. +Generating RTLIL representation for module `\$__RS_MUL10X9'. +Successfully finished Verilog frontend. + +4.88.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.89. Executing RS_DSP_SIMD pass. + +4.90. Executing TECHMAP pass (map to technology primitives). + +4.90.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v' to AST representation. +Generating RTLIL representation for module `\dsp_t1_20x18x64_cfg_ports'. +Generating RTLIL representation for module `\dsp_t1_10x9x32_cfg_params'. +Successfully finished Verilog frontend. + +4.90.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.91. Executing TECHMAP pass (map to technology primitives). + +4.91.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.91.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.92. Executing rs_pack_dsp_regs pass. + +4.93. Executing RS_DSP_IO_REGS pass. + +4.94. Executing TECHMAP pass (map to technology primitives). + +4.94.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSP_MULTACC'. +Generating RTLIL representation for module `\RS_DSP_MULT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN_REGOUT'. +Successfully finished Verilog frontend. + +4.94.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.95. Executing TECHMAP pass (map to technology primitives). + +4.95.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC'. +Generating RTLIL representation for module `\RS_DSPX2_MULT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'. +Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'. +Generating RTLIL representation for module `\RS_DSP3'. +Successfully finished Verilog frontend. + +4.95.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.96. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.97. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module GJC48: + created 0 $alu and 0 $macc cells. + +4.98. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.99. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.100. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.101. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.102. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.103. Executing OPT_SHARE pass. + +4.104. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.105. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.106. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.107. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.108. Executing MEMORY pass. + +4.108.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.108.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.108.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +4.108.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.108.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +4.108.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.108.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +4.108.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.108.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.108.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.109. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3 + $adff 2 + SOC_FPGA_INTF_DMA 1 + +4.110. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.111. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.112. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.113. Executing MEMORY_LIBMAP pass (mapping memories to cells). + +4.114. Executing Rs_BRAM_Split pass. + +4.115. Executing TECHMAP pass (map to technology primitives). + +4.115.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_TDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_SDP'. +Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_SDP'. +Successfully finished Verilog frontend. + +4.115.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.116. Executing TECHMAP pass (map to technology primitives). + +4.116.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v' to AST representation. +Generating RTLIL representation for module `\BRAM2x18_TDP'. +Generating RTLIL representation for module `\BRAM2x18_SDP'. +Successfully finished Verilog frontend. + +4.116.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.117. Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs). + +4.118. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.119. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.120. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.121. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.122. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.123. Executing OPT_SHARE pass. + +4.124. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=2, #solve=0, #remove=0, time=0.00 sec.] + +4.125. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.126. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.127. Executing PMUXTREE pass. + +4.128. Executing MUXPACK pass ($mux cell cascades to $pmux). +Converted 0 (p)mux cells into 0 pmux cells. + +4.129. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +4.130. Executing TECHMAP pass (map to technology primitives). + +4.130.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.130.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_rs_alu'. +Successfully finished Verilog frontend. + +4.130.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $adff. +No more expansions possible. + + +4.131. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + +4.132. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.133. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.134. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.135. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.136. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.137. Executing OPT_SHARE pass. + +4.138. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.139. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.140. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.141. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.142. Executing TECHMAP pass (map to technology primitives). + +4.142.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.142.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.143. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + +4.144. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.145. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.146. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.147. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.148. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.149. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.150. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.151. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.152. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.153. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.154. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.155. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.156. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.157. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.158. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.159. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.160. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.161. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.162. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.163. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.164. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.165. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.166. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=4, #remove=0, time=0.00 sec.] + +4.167. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.168. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.169. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + + Number of Generic REGs: 8 + +ABC-DFF iteration : 1 + +4.170. Executing ABC pass (technology mapping using ABC). + +4.170.1. Summary of detected clock domains: + 9 cells in clk=\clk, en={ }, arst=!\reset_n, srst={ } + + #logic partitions = 1 + +4.170.2. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Found matching posedge clock domain: \clk, asynchronously reset by !\reset_n +Extracted 8 gates and 16 wires to a netlist network with 8 inputs and 8 outputs (dfl=1). + +4.170.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.171. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.172. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.173. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.174. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.175. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.176. Executing OPT_SHARE pass. + +4.177. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.178. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.179. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 2 + +4.180. Executing ABC pass (technology mapping using ABC). + +4.180.1. Summary of detected clock domains: + 9 cells in clk=\clk, en={ }, arst=!\reset_n, srst={ } + + #logic partitions = 1 + +4.180.2. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Found matching posedge clock domain: \clk, asynchronously reset by !\reset_n +Extracted 8 gates and 16 wires to a netlist network with 8 inputs and 8 outputs (dfl=1). + +4.180.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.181. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.182. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.183. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.184. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.185. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.186. Executing OPT_SHARE pass. + +4.187. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.188. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.189. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 3 + +4.190. Executing ABC pass (technology mapping using ABC). + +4.190.1. Summary of detected clock domains: + 9 cells in clk=\clk, en={ }, arst=!\reset_n, srst={ } + + #logic partitions = 1 + +4.190.2. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Found matching posedge clock domain: \clk, asynchronously reset by !\reset_n +Extracted 8 gates and 16 wires to a netlist network with 8 inputs and 8 outputs (dfl=2). + +4.190.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.191. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.192. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.193. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.194. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.195. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.196. Executing OPT_SHARE pass. + +4.197. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.198. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.199. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +ABC-DFF iteration : 4 + +4.200. Executing ABC pass (technology mapping using ABC). + +4.200.1. Summary of detected clock domains: + 9 cells in clk=\clk, en={ }, arst=!\reset_n, srst={ } + + #logic partitions = 1 + +4.200.2. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Found matching posedge clock domain: \clk, asynchronously reset by !\reset_n +Extracted 8 gates and 16 wires to a netlist network with 8 inputs and 8 outputs (dfl=2). + +4.200.2.1. Executing ABC. +[Time = 0.05 sec.] + +4.201. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.202. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.203. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.204. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.205. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.206. Executing OPT_SHARE pass. + +4.207. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.208. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.209. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 +select with DFL2 synthesis (thresh-logic=0.920000, thresh_dff=0.980000) + +4.210. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.211. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.212. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.213. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.214. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.215. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.216. Executing OPT_SHARE pass. + +4.217. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.218. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.219. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.220. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.221. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.222. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.223. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.224. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.225. Executing OPT_SHARE pass. + +4.226. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.227. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.228. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.229. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.230. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.231. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.232. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.233. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.234. Executing OPT_SHARE pass. + +4.235. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.236. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=4, #remove=0, time=0.00 sec.] + +4.237. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.238. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.239. Executing BMUXMAP pass. + +4.240. Executing DEMUXMAP pass. + +4.241. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.242. Executing ABC pass (technology mapping using ABC). + +4.242.1. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs (dfl=1). +Don't call ABC as there is nothing to map. + +4.243. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.244. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.245. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.246. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.247. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.248. Executing OPT_SHARE pass. + +4.249. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.250. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.251. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.252. Executing OPT_FFINV pass (push inverters through FFs). +Discovering LUTs. +Pushed 0 inverters. + +4.253. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.254. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.255. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.256. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.257. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.258. Executing OPT_SHARE pass. + +4.259. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.260. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.261. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.262. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.263. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.264. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.265. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.266. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.267. Executing OPT_SHARE pass. + +4.268. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=0, #remove=0, time=0.00 sec.] + +4.269. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=8, #solve=4, #remove=0, time=0.00 sec.] + +4.270. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.271. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.272. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + +4.273. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +4.274. Executing RS_DFFSR_CONV pass. + +4.275. Printing statistics. + +=== GJC48 === + + Number of wires: 6 + Number of wire bits: 18 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 9 + $_DFF_PN0_ 8 + SOC_FPGA_INTF_DMA 1 + +4.276. Executing TECHMAP pass (map to technology primitives). + +4.276.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.276.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PN0P_'. +Generating RTLIL representation for module `\$_DFFE_PN0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_DFFE_PN1P_'. +Generating RTLIL representation for module `\$_DFFE_PN1N_'. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NN0P_'. +Generating RTLIL representation for module `\$_DFFE_NN0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_NN1P_'. +Generating RTLIL representation for module `\$_DFFE_NN1N_'. +Generating RTLIL representation for module `\$__SHREG_DFF_P_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PN0_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NN0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_PN1_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_NN1_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_PP0_'. +Generating RTLIL representation for module `\$_DLATCH_PN0_'. +Generating RTLIL representation for module `\$_DLATCH_NP0_'. +Generating RTLIL representation for module `\$_DLATCH_NN0_'. +Generating RTLIL representation for module `\$_DLATCH_PP1_'. +Generating RTLIL representation for module `\$_DLATCH_PN1_'. +Generating RTLIL representation for module `\$_DLATCH_NP1_'. +Generating RTLIL representation for module `\$_DLATCH_NN1_'. +Successfully finished Verilog frontend. + +4.276.3. Continuing TECHMAP pass. +No more expansions possible. + + +4.277. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.278. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +4.279. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.280. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.281. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.282. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 32 unused wires. + + +4.283. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.284. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.285. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.286. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.287. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.288. Executing OPT_SHARE pass. + +4.289. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.290. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.291. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.292. Executing TECHMAP pass (map to technology primitives). + +4.292.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +4.292.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.293. Executing ABC pass (technology mapping using ABC). + +4.293.1. Extracting gate netlist of module `\GJC48' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs (dfl=1). +Don't call ABC as there is nothing to map. + +4.294. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +4.295. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.296. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \GJC48.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.297. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \GJC48. +Performed a total of 0 changes. + +4.298. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\GJC48'. +Removed a total of 0 cells. + +4.299. Executing OPT_SHARE pass. + +4.300. Executing OPT_DFF pass (perform DFF optimizations). +[#visit=0, #solve=0, #remove=0, time=0.00 sec.] + +4.301. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.302. Executing OPT_EXPR pass (perform const folding). +Optimizing module GJC48. + +RUN-OPT ITERATIONS DONE : 1 + +4.303. Executing HIERARCHY pass (managing design hierarchy). + +4.303.1. Analyzing design hierarchy.. +Top module: \GJC48 + +4.303.2. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +4.304. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.305. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cells_map1.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__IO_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.306. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation. +Replacing existing blackbox module `\BOOT_CLOCK' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:9.1-14.10. +Generating RTLIL representation for module `\BOOT_CLOCK'. +Replacing existing blackbox module `\CARRY' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:24.1-31.10. +Generating RTLIL representation for module `\CARRY'. +Replacing existing blackbox module `\CLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:41.1-46.10. +Generating RTLIL representation for module `\CLK_BUF'. +Replacing existing blackbox module `\DFFNRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:56.1-64.10. +Generating RTLIL representation for module `\DFFNRE'. +Replacing existing blackbox module `\DFFRE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:74.1-82.10. +Generating RTLIL representation for module `\DFFRE'. +Replacing existing blackbox module `\DSP19X2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:92.1-126.10. +Generating RTLIL representation for module `\DSP19X2'. +Replacing existing blackbox module `\DSP38' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:136.1-162.10. +Generating RTLIL representation for module `\DSP38'. +Replacing existing blackbox module `\FCLK_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:172.1-176.10. +Generating RTLIL representation for module `\FCLK_BUF'. +Replacing existing blackbox module `\FIFO18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:186.1-233.10. +Generating RTLIL representation for module `\FIFO18KX2'. +Replacing existing blackbox module `\FIFO36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:243.1-268.10. +Generating RTLIL representation for module `\FIFO36K'. +Replacing existing blackbox module `\I_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:278.1-290.10. +Generating RTLIL representation for module `\I_BUF_DS'. +Replacing existing blackbox module `\I_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:300.1-309.10. +Generating RTLIL representation for module `\I_BUF'. +Replacing existing blackbox module `\I_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:319.1-327.10. +Generating RTLIL representation for module `\I_DDR'. +Replacing existing blackbox module `\I_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:337.1-349.10. +Generating RTLIL representation for module `\I_DELAY'. +Replacing existing blackbox module `\I_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:359.1-363.10. +Generating RTLIL representation for module `\I_FAB'. +Replacing existing blackbox module `\I_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:373.1-392.10. +Generating RTLIL representation for module `\I_SERDES'. +Replacing existing blackbox module `\LUT1' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:402.1-408.10. +Generating RTLIL representation for module `\LUT1'. +Replacing existing blackbox module `\LUT2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:418.1-424.10. +Generating RTLIL representation for module `\LUT2'. +Replacing existing blackbox module `\LUT3' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:434.1-440.10. +Generating RTLIL representation for module `\LUT3'. +Replacing existing blackbox module `\LUT4' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:450.1-456.10. +Generating RTLIL representation for module `\LUT4'. +Replacing existing blackbox module `\LUT5' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:466.1-472.10. +Generating RTLIL representation for module `\LUT5'. +Replacing existing blackbox module `\LUT6' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:482.1-488.10. +Generating RTLIL representation for module `\LUT6'. +Replacing existing blackbox module `\O_BUF_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:498.1-510.10. +Generating RTLIL representation for module `\O_BUF_DS'. +Replacing existing blackbox module `\O_BUFT_DS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:520.1-532.10. +Generating RTLIL representation for module `\O_BUFT_DS'. +Replacing existing blackbox module `\O_BUFT' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:542.1-553.10. +Generating RTLIL representation for module `\O_BUFT'. +Replacing existing blackbox module `\O_BUF' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:563.1-574.10. +Generating RTLIL representation for module `\O_BUF'. +Replacing existing blackbox module `\O_DDR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:584.1-592.10. +Generating RTLIL representation for module `\O_DDR'. +Replacing existing blackbox module `\O_DELAY' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:602.1-614.10. +Generating RTLIL representation for module `\O_DELAY'. +Replacing existing blackbox module `\O_FAB' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:624.1-628.10. +Generating RTLIL representation for module `\O_FAB'. +Replacing existing blackbox module `\O_SERDES_CLK' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:638.1-647.10. +Generating RTLIL representation for module `\O_SERDES_CLK'. +Replacing existing blackbox module `\O_SERDES' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:657.1-674.10. +Generating RTLIL representation for module `\O_SERDES'. +Replacing existing blackbox module `\PLL' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:684.1-702.10. +Generating RTLIL representation for module `\PLL'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_M' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:712.1-726.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AHB_S' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:736.1-753.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M0' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:763.1-802.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'. +Replacing existing blackbox module `\SOC_FPGA_INTF_AXI_M1' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:812.1-851.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'. +Replacing existing blackbox module `\SOC_FPGA_INTF_DMA' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:861.1-867.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'. +Replacing existing blackbox module `\SOC_FPGA_INTF_IRQ' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:877.1-883.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'. +Replacing existing blackbox module `\SOC_FPGA_INTF_JTAG' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:893.1-901.10. +Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'. +Replacing existing blackbox module `\SOC_FPGA_TEMPERATURE' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:911.1-919.10. +Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'. +Replacing existing blackbox module `\TDP_RAM18KX2' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:929.1-984.10. +Generating RTLIL representation for module `\TDP_RAM18KX2'. +Replacing existing blackbox module `\TDP_RAM36K' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:994.1-1023.10. +Generating RTLIL representation for module `\TDP_RAM36K'. +Replacing existing blackbox module `\LATCH' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1040.1-1045.10. +Generating RTLIL representation for module `\LATCH'. +Replacing existing blackbox module `\LATCHN' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1053.1-1058.10. +Generating RTLIL representation for module `\LATCHN'. +Replacing existing blackbox module `\LATCHR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1067.1-1073.10. +Generating RTLIL representation for module `\LATCHR'. +Replacing existing blackbox module `\LATCHS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1081.1-1087.10. +Generating RTLIL representation for module `\LATCHS'. +Replacing existing blackbox module `\LATCHNR' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1096.1-1102.10. +Generating RTLIL representation for module `\LATCHNR'. +Replacing existing blackbox module `\LATCHNS' at /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1111.1-1117.10. +Generating RTLIL representation for module `\LATCHNS'. +Successfully finished Verilog frontend. + *************************** + Inserting Input Buffers + *************************** +WARNING: port '\clk' has no associated I_BUF +WARNING: port '\dma_req_in' has no associated I_BUF +WARNING: port '\reset_n' has no associated I_BUF + *************************** + Inserting Clock Buffers + *************************** +INFO: inserting CLK_BUF before '$ibuf_clk' + ***************************** + Inserting Output Buffers + ***************************** +WARNING: OUTPUT port '\dma_ack_out' has no associated O_BUF + ***************************** + Mapping Tri-state Buffers + ***************************** + +4.307. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.308. Executing TECHMAP pass (map to technology primitives). + +4.308.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v' to AST representation. +Generating RTLIL representation for module `\rs__CLK_BUF'. +Generating RTLIL representation for module `\rs__I_BUF'. +Generating RTLIL representation for module `\rs__O_BUF'. +Generating RTLIL representation for module `\rs__O_BUFT'. +Successfully finished Verilog frontend. + +4.308.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.309. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. +Removed 0 unused cells and 30 unused wires. + + +4.310. Printing statistics. + +=== GJC48 === + + Number of wires: 11 + Number of wire bits: 29 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUF 4 + SOC_FPGA_INTF_DMA 1 + +4.311. Executing TECHMAP pass (map to technology primitives). + +4.311.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v +Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v' to AST representation. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +4.311.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.312. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \GJC48.. + +4.313. Printing statistics. + +=== GJC48 === + + Number of wires: 11 + Number of wire bits: 29 + Number of public wires: 6 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUF 4 + SOC_FPGA_INTF_DMA 1 + + ***************************** + Rewire_Obuft + ***************************** + +========================== +Post Design clean up ... + +Split to bits ... + +4.314. Executing SPLITNETS pass (splitting up multi-bit signals). + +Split into bits ... [0.00 sec.] +Building Sig2cells ... [0.00 sec.] +Building Sig2sig ... [0.00 sec.] +Backward clean up ... [0.00 sec.] +Before cleanup : + +4.315. Printing statistics. + +=== GJC48 === + + Number of wires: 23 + Number of wire bits: 29 + Number of public wires: 12 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUFT 4 + SOC_FPGA_INTF_DMA 1 + + -------------------------- + Removed assigns : 0 + Removed wires : 0 + Removed cells : 0 + -------------------------- +After cleanup : + +4.316. Printing statistics. + +=== GJC48 === + + Number of wires: 23 + Number of wire bits: 29 + Number of public wires: 12 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUFT 4 + SOC_FPGA_INTF_DMA 1 + + +Total time for 'obs_clean' ... + [0.00 sec.] + +4.317. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.318. Executing HIERARCHY pass (managing design hierarchy). + +4.318.1. Analyzing design hierarchy.. +Top module: \GJC48 + +4.318.2. Analyzing design hierarchy.. +Top module: \GJC48 +Removed 0 unused modules. + +Dumping port properties into 'netlist_info.json' file. + + +Inserting I_FAB/O_FAB cells ... + + +Inserting I_FAB/O_FAB cells done. + +4.319. Printing statistics. + +=== GJC48 === + + Number of wires: 23 + Number of wire bits: 29 + Number of public wires: 12 + Number of public wire bits: 18 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 20 + CLK_BUF 1 + DFFRE 8 + I_BUF 6 + O_BUFT 4 + SOC_FPGA_INTF_DMA 1 + + Number of LUTs: 0 + Number of REGs: 8 + Number of CARRY ADDERs: 0 + +4.320. Executing Verilog backend. +Dumping module `\GJC48'. + +# -------------------- +# Core Synthesis done +# -------------------- + +4.321. Executing Verilog backend. +Dumping module `\GJC48'. + +4.321.1. Executing BLIF backend. + +-- Running command `write_rtlil design.rtlil' -- + +4.321.2. Executing RTLIL backend. +Output filename: design.rtlil + +4.321.3. Executing SPLITNETS pass (splitting up multi-bit signals). + +4.321.4. Executing FLATTEN pass (flatten design). +Deleting now unused module interface_GJC48. + + +4.321.5. Executing Verilog backend. +Dumping module `\GJC48'. + +4.321.5.1. Executing BLIF backend. +Run Script + +4.321.5.2. Executing Verilog backend. +Dumping module `\GJC48'. + +4.321.5.2.1. Executing BLIF backend. + +4.321.5.2.2. Executing Verilog backend. +Dumping module `\fabric_GJC48'. + +4.321.5.2.2.1. Executing BLIF backend. + +Warnings: 1 unique messages, 1 total +End of script. Logfile hash: 0f3c69f369, CPU: user 0.72s system 0.09s, MEM: 112.07 MB peak +Yosys 0.38 (git sha1 2b36bfab5, gcc 11.2.1 -fPIC -Os) +Time spent: 31% 43x read_verilog (0 sec), 19% 6x abc (0 sec), ... +INFO: SYN: Design GJC48 is synthesized +INFO: SGT: ################################################## +INFO: SGT: Gate simulation for design: GJC48 +INFO: SGT: ################################################## +Command: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/HDL_simulator/iverilog/bin/iverilog -DIVERILOG=1 -v -s co_sim_GJC48 -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl -g2001 /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/co_sim_GJC48.v /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48/run_1/synth_1_1/synthesis/GJC48_post_synth.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/simlib.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/brams_sim.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/llatches_sim.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AXI_M0.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_IRQ.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUFT.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_BUF_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_JTAG.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO36K.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FCLK_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AXI_M1.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES_CLK.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO18KX2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_FAB.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DDR.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/TDP_RAM36K.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUFT_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AHB_M.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DDR.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_FAB.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/TDP_RAM18KX2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AHB_S.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_SERDES.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP19X2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_DMA.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/PLL.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/BOOT_CLOCK.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_TEMPERATURE.v +Icarus Verilog Preprocessor version 13.0 (devel) (s20221226-498-g52d049b51) + +Copyright (c) 1999-2024 Stephen Williams (steve@icarus.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +Using language generation: IEEE1364-2001,no-specify,no-interconnect,xtypes,icarus-misc +PARSING INPUT +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO36K.v:193: error: block end label requires SystemVerilog. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO36K.v:232: parameter declarations are not permitted in generate blocks +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO36K.v:233: parameter declarations are not permitted in generate blocks +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO36K.v:637: error: block end label requires SystemVerilog. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:33: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:33: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:36: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:38: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:39: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:43: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:46: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:46: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:51: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:52: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:53: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:54: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:56: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:57: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v:57: error: Syntax error in left side of continuous assignment. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:64: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:65: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:66: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:67: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:68: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:69: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:70: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:71: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:73: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:74: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:75: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:76: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v:77: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:33: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:33: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:36: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:38: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:39: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:43: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:46: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:46: error: Invalid module instantiation +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:51: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:52: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:53: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:54: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:56: error: Invalid module item. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:57: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v:57: error: Syntax error in left side of continuous assignment. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:64: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:65: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:66: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:67: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:68: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:69: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:70: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:71: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:73: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:74: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:75: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v:76: warning: Timing checks are not supported. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES.v:43: syntax error +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES.v:44: warning: Using SystemVerilog 'N bit vector. Use at least -g2005-sv to remove this warning. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES.v:43: error: Incomprehensible for loop. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/PLL.v:106: warning: Using SystemVerilog 'N bit vector. Use at least -g2005-sv to remove this warning. +/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/PLL.v:115: warning: Using SystemVerilog 'N bit vector. Use at least -g2005-sv to remove this warning. +/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/co_sim_GJC48.v:39: error: Empty function argument list requires SystemVerilog. +/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/co_sim_GJC48.v:55: warning: task definition for "compare" has an empty port declaration list! +Icarus Verilog version 13.0 (devel) (s20221226-498-g52d049b51) + +Copyright (c) 2000-2024 Stephen Williams (steve@icarus.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + +translate: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/ivlpp -v -L -F"/tmp/ivrlg26add4779" -f"/tmp/ivrlg6add4779" -p"/tmp/ivrli6add4779" |/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/ivl -v -C"/tmp/ivrlh6add4779" -C"/nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/HDL_simulator/iverilog/lib/ivl/vvp.conf" -- - +ERROR: SGT: Design GJC48 simulation compilation failed! + +ERROR: SGT: Design GJC48 simulation failed! + diff --git a/EDA-3164/raptor_cmd.tcl b/EDA-3164/raptor_cmd.tcl new file mode 100644 index 00000000..c79c7ce4 --- /dev/null +++ b/EDA-3164/raptor_cmd.tcl @@ -0,0 +1,28 @@ +# /******************************************************************************* +# Copyright (c) 2022-2024 Rapid Silicon +# This source code contains proprietary information belonging to Rapid Silicon +# (the "licensor") released under license and non-disclosure agreement to the +# recipient (the "licensee"). +# The information shared and protected by the license and non-disclosure agreement +# includes but is not limited to the following: +# * operational algorithms of the product +# * logos, graphics, source code, and visual presentation of the product +# * confidential operational information of the licensor +# The recipient of this source code is NOT permitted to publicly disclose, +# re-use, archive beyond the period of the license agreement, transfer to a +# sub-licensee, or re-implement any portion of the content covered by the license +# and non-disclosure agreement without the prior written consent of the licensor. +# *********************************************************************************/ +# Version : 2024.08 +# Build : 1.1.51 +# Hash : c3b8064 +# Date : Aug 27 2024 +# Type : Engineering +# Log Time : Tue Aug 27 07:54:43 2024 GMT +source /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/etc/init/sim_helpers.tcl +source /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/etc/init/flow.tcl +gui_start +ipgenerate +analyze +synth +simulate gate diff --git a/EDA-3164/raptor_perf.log b/EDA-3164/raptor_perf.log new file mode 100644 index 00000000..96da24c4 --- /dev/null +++ b/EDA-3164/raptor_perf.log @@ -0,0 +1,37 @@ +/******************************************************************************* +Copyright (c) 2022-2024 Rapid Silicon +This source code contains proprietary information belonging to Rapid Silicon +(the "licensor") released under license and non-disclosure agreement to the +recipient (the "licensee"). + +The information shared and protected by the license and non-disclosure agreement +includes but is not limited to the following: +* operational algorithms of the product +* logos, graphics, source code, and visual presentation of the product +* confidential operational information of the licensor + +The recipient of this source code is NOT permitted to publicly disclose, +re-use, archive beyond the period of the license agreement, transfer to a +sub-licensee, or re-implement any portion of the content covered by the license +and non-disclosure agreement without the prior written consent of the licensor. +*********************************************************************************/ + +Version : 2024.08 +Build : 1.1.51 +Hash : c3b8064 +Date : Aug 27 2024 +Type : Engineering +Log Time : Tue Aug 27 07:54:43 2024 GMT + +[ 12:56:02 ] Analysis has started +[ 12:56:02 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/yosys -s /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48/run_1/synth_1_1/analysis/GJC48_analyzer.cmd +[ 12:56:02 ] Duration: 82 ms. Max utilization: 43 MB +[ 12:56:02 ] Synthesize has started +[ 12:56:02 ] Analysis has started +[ 12:56:02 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/yosys -s /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48/run_1/synth_1_1/analysis/GJC48_analyzer.cmd +[ 12:56:02 ] Duration: 112 ms. Max utilization: 43 MB +[ 12:56:02 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/yosys -s GJC48.ys -l GJC48_synth.log +[ 12:56:04 ] Duration: 1153 ms. Max utilization: 65 MB +[ 12:56:04 ] Gate Simulation has started +[ 12:56:04 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/bin/HDL_simulator/iverilog/bin/iverilog -DIVERILOG=1 -v -s co_sim_GJC48 -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl -g2001 /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/co_sim_GJC48.v /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/GJC-IO-Testcases/GJC48/rtl/GJC48/run_1/synth_1_1/synthesis/GJC48_post_synth.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/simlib.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/brams_sim.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/llatches_sim.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AXI_M0.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_IRQ.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUFT.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_BUF_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_JTAG.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO36K.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FCLK_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AXI_M1.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES_CLK.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/FIFO18KX2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DELAY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_FAB.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DDR.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/TDP_RAM36K.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUFT_DS.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AHB_M.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_DELAY.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_DDR.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_FAB.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/TDP_RAM18KX2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_AHB_S.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_BUF.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/I_SERDES.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP19X2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_SERDES.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_INTF_DMA.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/PLL.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/BOOT_CLOCK.v -l /nfs_eda_sw/softwares/Raptor/instl_dir/08_27_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/SOC_FPGA_TEMPERATURE.v +[ 12:56:04 ] Duration: 120 ms. Max utilization: 4 MB