diff --git a/EDA-3283/raptor_sdc.sdc b/EDA-3283/raptor_sdc.sdc
new file mode 100644
index 00000000..c910057f
--- /dev/null
+++ b/EDA-3283/raptor_sdc.sdc
@@ -0,0 +1,4 @@
+create_clock -period 2.5 clk_i
+set_input_delay 0 -clock clk_i [get_ports {*}]
+set_output_delay 0 -clock clk_i [get_ports {*}]
+
diff --git a/EDA-3283/raptor_tcl.tcl b/EDA-3283/raptor_tcl.tcl
new file mode 100644
index 00000000..d67acad5
--- /dev/null
+++ b/EDA-3283/raptor_tcl.tcl
@@ -0,0 +1,66 @@
+create_design hmac
+target_device 1VG28
+add_include_path ./rtl/
+add_library_path ./rtl/
+add_library_ext .v .sv
+add_design_file -SV_2012 ./rtl/prim_secded_pkg.sv
+add_design_file -SV_2012 ./rtl/prim_subreg_pkg.sv
+add_design_file -SV_2012 ./rtl/prim_util_pkg.sv
+add_design_file -SV_2012 ./rtl/pwrmgr_reg_pkg.sv
+add_design_file -SV_2012 ./rtl/pwrmgr_pkg.sv
+add_design_file -SV_2012 ./rtl/prim_ram_1p_pkg.sv
+add_design_file -SV_2012 ./rtl/prim_mubi_pkg.sv
+add_design_file -SV_2012 ./rtl/prim_pkg.sv
+add_design_file -SV_2012 ./rtl/prim_cipher_pkg.sv
+add_design_file -SV_2012 ./rtl/prim_alert_pkg.sv
+add_design_file -SV_2012 ./rtl/prim_count_pkg.sv
+add_design_file -SV_2012 ./rtl/jtag_pkg.sv
+add_design_file -SV_2012 ./rtl/entropy_src_pkg.sv
+add_design_file -SV_2012 ./rtl/edn_pkg.sv
+add_design_file -SV_2012 ./rtl/top_pkg.sv
+add_design_file -SV_2012 ./rtl/flash_ctrl_reg_pkg.sv
+add_design_file -SV_2012 ./rtl/flash_ctrl_pkg.sv
+add_design_file -SV_2012 ./rtl/flash_phy_pkg.sv
+add_design_file -SV_2012 ./rtl/hmac_reg_pkg.sv
+add_design_file -SV_2012 ./rtl/hmac_pkg.sv
+add_design_file -SV_2012 ./rtl/lc_ctrl_pkg.sv
+add_design_file -SV_2012 ./rtl/otp_ctrl_reg_pkg.sv
+add_design_file -SV_2012 ./rtl/otp_ctrl_pkg.sv
+add_design_file -SV_2012 ./rtl/tlul_pkg.sv
+add_design_file -SV_2012 ./rtl/ast_pkg.sv
+add_design_file -SV_2012 ./rtl/hmac.sv
+add_design_file -SV_2012 ./rtl/hmac_core.sv
+add_design_file -SV_2012 ./rtl/hmac_reg_top.sv
+add_design_file -SV_2012 ./rtl/prim_alert_sender.sv
+add_design_file -SV_2012 ./rtl/prim_buf.sv
+add_design_file -SV_2012 ./rtl/prim_diff_decode.sv
+add_design_file -SV_2012 ./rtl/prim_fifo_sync.sv
+add_design_file -SV_2012 ./rtl/prim_flop_2sync.sv
+add_design_file -SV_2012 ./rtl/prim_generic_buf.sv
+add_design_file -SV_2012 ./rtl/prim_generic_flop.sv
+add_design_file -SV_2012 ./rtl/prim_generic_flop_2sync.sv
+add_design_file -SV_2012 ./rtl/prim_intr_hw.sv
+add_design_file -SV_2012 ./rtl/prim_packer.sv
+add_design_file -SV_2012 ./rtl/prim_secded_inv_39_32_dec.sv
+add_design_file -SV_2012 ./rtl/prim_secded_inv_39_32_enc.sv
+add_design_file -SV_2012 ./rtl/prim_secded_inv_64_57_dec.sv
+add_design_file -SV_2012 ./rtl/prim_secded_inv_64_57_enc.sv
+add_design_file -SV_2012 ./rtl/prim_subreg.sv
+add_design_file -SV_2012 ./rtl/prim_subreg_ext.sv
+add_design_file -SV_2012 ./rtl/sha2.sv
+add_design_file -SV_2012 ./rtl/sha2_pad.sv
+add_design_file -SV_2012 ./rtl/tlul_adapter_reg.sv
+add_design_file -SV_2012 ./rtl/tlul_adapter_sram.sv
+add_design_file -SV_2012 ./rtl/tlul_cmd_intg_chk.sv
+add_design_file -SV_2012 ./rtl/tlul_data_integ_dec.sv
+add_design_file -SV_2012 ./rtl/tlul_data_integ_enc.sv
+add_design_file -SV_2012 ./rtl/tlul_err.sv
+add_design_file -SV_2012 ./rtl/tlul_err_resp.sv
+add_design_file -SV_2012 ./rtl/tlul_fifo_sync.sv
+add_design_file -SV_2012 ./rtl/tlul_rsp_intg_gen.sv
+add_design_file -SV_2012 ./rtl/tlul_socket_1n.sv
+set_top_module hmac
+add_constraint_file ./raptor_sdc.sdc
+analyze
+synth_options -effort high
+synthesize delay
diff --git a/EDA-3283/results_dir/hmac/hmac.ospr b/EDA-3283/results_dir/hmac/hmac.ospr
new file mode 100644
index 00000000..2430769b
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/hmac.ospr
@@ -0,0 +1,184 @@
+
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diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/analysis.rpt b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/analysis.rpt
new file mode 100644
index 00000000..a34a7c72
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/analysis.rpt
@@ -0,0 +1,528 @@
+/*******************************************************************************
+Copyright (c) 2022-2024 Rapid Silicon
+This source code contains proprietary information belonging to Rapid Silicon
+(the "licensor") released under license and non-disclosure agreement to the
+recipient (the "licensee").
+
+The information shared and protected by the license and non-disclosure agreement
+includes but is not limited to the following:
+* operational algorithms of the product
+* logos, graphics, source code, and visual presentation of the product
+* confidential operational information of the licensor
+
+The recipient of this source code is NOT permitted to publicly disclose,
+re-use, archive beyond the period of the license agreement, transfer to a
+sub-licensee, or re-implement any portion of the content covered by the license
+and non-disclosure agreement without the prior written consent of the licensor.
+*********************************************************************************/
+
+Version : 2024.10
+Build : 1.2.12
+Hash : 6f00985
+Date : Oct 1 2024
+Type : Engineering
+Log Time : Tue Oct 1 20:41:06 2024 GMT
+/*******************************************************************************
+Copyright (c) 2022-2024 Rapid Silicon
+This source code contains proprietary information belonging to Rapid Silicon
+(the "licensor") released under license and non-disclosure agreement to the
+recipient (the "licensee").
+
+The information shared and protected by the license and non-disclosure agreement
+includes but is not limited to the following:
+* operational algorithms of the product
+* logos, graphics, source code, and visual presentation of the product
+* confidential operational information of the licensor
+
+The recipient of this source code is NOT permitted to publicly disclose,
+re-use, archive beyond the period of the license agreement, transfer to a
+sub-licensee, or re-implement any portion of the content covered by the license
+and non-disclosure agreement without the prior written consent of the licensor.
+*********************************************************************************/
+
+Version : 2024.10
+Build : 1.2.12
+Hash : 6f00985
+Date : Oct 1 2024
+Type : Engineering
+Log Time : Tue Oct 1 20:41:06 2024 GMT
+/*******************************************************************************
+Copyright (c) 2022-2024 Rapid Silicon
+This source code contains proprietary information belonging to Rapid Silicon
+(the "licensor") released under license and non-disclosure agreement to the
+recipient (the "licensee").
+
+The information shared and protected by the license and non-disclosure agreement
+includes but is not limited to the following:
+* operational algorithms of the product
+* logos, graphics, source code, and visual presentation of the product
+* confidential operational information of the licensor
+
+The recipient of this source code is NOT permitted to publicly disclose,
+re-use, archive beyond the period of the license agreement, transfer to a
+sub-licensee, or re-implement any portion of the content covered by the license
+and non-disclosure agreement without the prior written consent of the licensor.
+*********************************************************************************/
+
+Version : 2024.10
+Build : 1.2.12
+Hash : 6f00985
+Date : Oct 1 2024
+Type : Engineering
+Log Time : Tue Oct 1 20:41:06 2024 GMT
+
+ /----------------------------------------------------------------------------\
+ | yosys -- Yosys Open SYnthesis Suite |
+ | Copyright (C) 2012 - 2024 Claire Xenia Wolf |
+ | Distributed under an ISC-like license, type "license" to see terms |
+ \----------------------------------------------------------------------------/
+
+ Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3)
+
+-- Executing script file `/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/hmac_analyzer.cmd' --
+
+1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v
+Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation.
+Generating RTLIL representation for module `\BOOT_CLOCK'.
+Generating RTLIL representation for module `\CARRY'.
+Generating RTLIL representation for module `\CLK_BUF'.
+Generating RTLIL representation for module `\DFFNRE'.
+Generating RTLIL representation for module `\DFFRE'.
+Generating RTLIL representation for module `\DSP19X2'.
+Generating RTLIL representation for module `\DSP38'.
+Generating RTLIL representation for module `\FCLK_BUF'.
+Generating RTLIL representation for module `\FIFO18KX2'.
+Generating RTLIL representation for module `\FIFO36K'.
+Generating RTLIL representation for module `\I_BUF_DS'.
+Generating RTLIL representation for module `\I_BUF'.
+Generating RTLIL representation for module `\I_DDR'.
+Generating RTLIL representation for module `\I_DELAY'.
+Generating RTLIL representation for module `\I_FAB'.
+Generating RTLIL representation for module `\I_SERDES'.
+Generating RTLIL representation for module `\LATCHNR'.
+Generating RTLIL representation for module `\LATCHNS'.
+Generating RTLIL representation for module `\LATCHN'.
+Generating RTLIL representation for module `\LATCHR'.
+Generating RTLIL representation for module `\LATCHS'.
+Generating RTLIL representation for module `\LATCH'.
+Generating RTLIL representation for module `\LUT1'.
+Generating RTLIL representation for module `\LUT2'.
+Generating RTLIL representation for module `\LUT3'.
+Generating RTLIL representation for module `\LUT4'.
+Generating RTLIL representation for module `\LUT5'.
+Generating RTLIL representation for module `\LUT6'.
+Generating RTLIL representation for module `\MIPI_RX'.
+Generating RTLIL representation for module `\MIPI_TX'.
+Generating RTLIL representation for module `\O_BUF_DS'.
+Generating RTLIL representation for module `\O_BUFT_DS'.
+Generating RTLIL representation for module `\O_BUFT'.
+Generating RTLIL representation for module `\O_BUF'.
+Generating RTLIL representation for module `\O_DDR'.
+Generating RTLIL representation for module `\O_DELAY'.
+Generating RTLIL representation for module `\O_FAB'.
+Generating RTLIL representation for module `\O_SERDES_CLK'.
+Generating RTLIL representation for module `\O_SERDES'.
+Generating RTLIL representation for module `\PLL'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'.
+Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'.
+Generating RTLIL representation for module `\TDP_RAM18KX2'.
+Generating RTLIL representation for module `\TDP_RAM36K'.
+Successfully finished Verilog frontend.
+Warning: Using synlig as yosys plugin is deprecated. It is recommended to build synlig as standalone binary.
+
+2. Executing SystemVerilog frontend.
+[INF:CM0023] Creating log file "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/surelog.log".
+[INF:CP0300] Compilation...
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_pkg.sv:8:1: Compile package "prim_secded_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg_pkg.sv:5:1: Compile package "prim_subreg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_util_pkg.sv:9:1: Compile package "prim_util_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/pwrmgr_reg_pkg.sv:7:1: Compile package "pwrmgr_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/pwrmgr_pkg.sv:8:1: Compile package "pwrmgr_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_ram_1p_pkg.sv:6:1: Compile package "prim_ram_1p_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:13:1: Compile package "prim_mubi_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_pkg.sv:11:1: Compile package "prim_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:17:1: Compile package "prim_cipher_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_pkg.sv:5:1: Compile package "prim_alert_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_count_pkg.sv:8:1: Compile package "prim_count_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/jtag_pkg.sv:6:1: Compile package "jtag_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/entropy_src_pkg.sv:7:1: Compile package "entropy_src_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/edn_pkg.sv:7:1: Compile package "edn_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/top_pkg.sv:6:1: Compile package "top_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_ctrl_reg_pkg.sv:7:1: Compile package "flash_ctrl_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_ctrl_pkg.sv:8:1: Compile package "flash_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_phy_pkg.sv:8:1: Compile package "flash_phy_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_pkg.sv:7:1: Compile package "hmac_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:6:1: Compile package "hmac_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/lc_ctrl_pkg.sv:6:1: Compile package "lc_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/otp_ctrl_reg_pkg.sv:7:1: Compile package "otp_ctrl_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/otp_ctrl_pkg.sv:6:1: Compile package "otp_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:6:1: Compile package "tlul_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/ast_pkg.sv:12:1: Compile package "ast_pkg".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:9:1: Compile module "work@hmac".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:7:1: Compile module "work@hmac_core".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:8:1: Compile module "work@hmac_reg_top".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:32:1: Compile module "work@prim_alert_sender".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:16:1: Compile module "work@prim_buf".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:19:1: Compile module "work@prim_diff_decode".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:6:1: Compile module "work@prim_fifo_sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:13:1: Compile module "work@prim_flop_2sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_buf.sv:6:1: Compile module "work@prim_generic_buf".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:7:1: Compile module "work@prim_generic_flop".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop_2sync.sv:9:1: Compile module "work@prim_generic_flop_2sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:10:1: Compile module "work@prim_intr_hw".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:8:1: Compile module "work@prim_packer".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:7:1: Compile module "work@prim_secded_inv_39_32_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_enc.sv:7:1: Compile module "work@prim_secded_inv_39_32_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:7:1: Compile module "work@prim_secded_inv_64_57_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_enc.sv:7:1: Compile module "work@prim_secded_inv_64_57_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:7:1: Compile module "work@prim_subreg".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg_ext.sv:7:1: Compile module "work@prim_subreg_ext".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:8:1: Compile module "work@sha2".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:9:1: Compile module "work@sha2_pad".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:10:1: Compile module "work@tlul_adapter_reg".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:13:1: Compile module "work@tlul_adapter_sram".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:3:1: Compile module "work@tlul_cmd_intg_chk".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_data_integ_dec.sv:10:1: Compile module "work@tlul_data_integ_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_data_integ_enc.sv:10:1: Compile module "work@tlul_data_integ_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:7:1: Compile module "work@tlul_err".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:6:1: Compile module "work@tlul_err_resp".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:9:1: Compile module "work@tlul_fifo_sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:9:1: Compile module "work@tlul_rsp_intg_gen".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:35:1: Compile module "work@tlul_socket_1n".
+[INF:CP0302] Compile class "work@mailbox".
+[INF:CP0302] Compile class "work@process".
+[INF:CP0302] Compile class "work@semaphore".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:41:17: Implicit port type (wire) for "sha_message_length".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:21:27: Implicit port type (wire) for "wready",
+there are 3 more instances of this message.
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:24:23: Implicit port type (wire) for "hw2reg_intr_state_de_o",
+there are 1 more instances of this message.
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:19:27: Implicit port type (wire) for "ready_o".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:24:29: Implicit port type (wire) for "spare_req_o",
+there are 1 more instances of this message.
+[INF:EL0526] Design Elaboration...
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[2]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[3]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[4]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[5]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[6]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[7]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_hmac_done.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_fifo_empty.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_hmac_err.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:122:14: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_depth_gt1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:132:23: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_pass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:172:12: Compile generate block "work@hmac.u_tlul_adapter.gen_no_wordwidthadapt".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:206:12: Compile generate block "work@hmac.u_tlul_adapter.gen_writes_allowed".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:210:23: Compile generate block "work@hmac.u_tlul_adapter.gen_no_reads".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:135:14: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_nopass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:135:14: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_nopass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:132:23: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_pass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:19:25: Compile generate block "work@hmac.u_reg.u_rsp_intg_gen.gen_rsp_intg".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:34:26: Compile generate block "work@hmac.u_reg.u_rsp_intg_gen.gen_data_intg".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:124:36: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:124:36: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[2]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:177:36: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:177:36: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_hmac_done.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_fifo_empty.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_hmac_err.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_hmac_done.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_fifo_empty.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_hmac_err.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_err_code.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_msg_length_lower.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_msg_length_upper.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:460:42: Compile generate block "work@hmac.gen_alert_tx[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:44:16: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_n.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:44:16: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_n.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:30:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:30:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_n.gen_generic".
+[NTE:EL0503] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:9:1: Top level module "work@hmac".
+[NTE:EL0508] Nb Top level modules: 1.
+[NTE:EL0509] Max instance depth: 9.
+[NTE:EL0510] Nb instances: 98.
+[NTE:EL0511] Nb leaf instances: 32.
+[INF:UH0706] Creating UHDM Model...
+[INF:UH0707] Elaborating UHDM...
+[ FATAL] : 0
+[ SYNTAX] : 0
+[ ERROR] : 0
+[WARNING] : 0
+[ NOTE] : 10
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_util_pkg.sv:34: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:80: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:106: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:209: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:235: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:338: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:364: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:467: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:493: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:71: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:82: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:293: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:304: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:315: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:328: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:337: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:346: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:355: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:364: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:373: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:382: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:391: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_ctrl_pkg.sv:553: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:128: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:322: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:488: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:185: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:253: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:53: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:87: Post-decrementation operations are handled as pre-decrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:97: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:112: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:116: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:122: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:144: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:156: Post-incrementation operations are handled as pre-incrementation.
+Generating RTLIL representation for module `$paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000'.
+Generating RTLIL representation for module `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg'.
+Generating RTLIL representation for module `$paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101'.
+Generating RTLIL representation for module `$paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001'.
+Generating RTLIL representation for module `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp'.
+Generating RTLIL representation for module `$paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_diff_decode\AsyncOn=1'1'.
+Generating RTLIL representation for module `$paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf'.
+Generating RTLIL representation for module `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg'.
+Generating RTLIL representation for module `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender'.
+Generating RTLIL representation for module `\sha2'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1'.
+Generating RTLIL representation for module `\hmac'.
+Generating RTLIL representation for module `$paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1'.
+Generating RTLIL representation for module `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg'.
+Generating RTLIL representation for module `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0'.
+Generating RTLIL representation for module `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk'.
+Generating RTLIL representation for module `$paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0'.
+Generating RTLIL representation for module `$paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1'.
+Generating RTLIL representation for module `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err'.
+Generating RTLIL representation for module `\hmac_core'.
+Warning: reg '\sel_msglen' is assigned in a continuous assignment at /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:179.10-179.67.
+Generating RTLIL representation for module `$paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1'.
+Generating RTLIL representation for module `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top'.
+Generating RTLIL representation for module `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen'.
+Generating RTLIL representation for module `\sha2_pad'.
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:83: Warning: Range select [127:124] out of bounds on signal `\fifo_rdata': Setting all 4 result bits to undef.
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:84: Warning: Range select [127:124] out of bounds on signal `\fifo_rdata': Setting all 4 result bits to undef.
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:85: Warning: Range select [127:124] out of bounds on signal `\fifo_rdata': Setting all 4 result bits to undef.
+Generating RTLIL representation for module `\prim_secded_inv_64_57_dec'.
+Generating RTLIL representation for module `$paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec'.
+Generating RTLIL representation for module `\prim_secded_inv_39_32_dec'.
+Generating RTLIL representation for module `\prim_generic_buf'.
+Generating RTLIL representation for module `\prim_secded_inv_64_57_enc'.
+Generating RTLIL representation for module `$paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc'.
+Generating RTLIL representation for module `\prim_secded_inv_39_32_enc'.
+Generating RTLIL representation for module `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n'.
+
+-- Running command `hierarchy -top hmac' --
+
+3. Executing HIERARCHY pass (managing design hierarchy).
+
+3.1. Analyzing design hierarchy..
+Top module: \hmac
+Used module: $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top
+Used module: $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001
+Used module: $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg
+Used module: $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg
+Used module: $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err
+Used module: $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp
+Used module: $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync
+Used module: $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync
+Used module: $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync
+Used module: $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync
+Used module: $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync
+Used module: $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync
+Used module: $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc
+Used module: \prim_secded_inv_39_32_enc
+Used module: \prim_secded_inv_64_57_enc
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec
+Used module: \prim_secded_inv_39_32_dec
+Used module: \prim_secded_inv_64_57_dec
+Used module: \sha2
+Used module: \sha2_pad
+Used module: \hmac_core
+Used module: $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer
+Used module: $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram
+Used module: $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync
+Used module: $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync
+Used module: $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync
+Used module: $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync
+Used module: $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1
+Used module: $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender
+Used module: $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf
+Used module: \prim_generic_buf
+Used module: $paramod\prim_diff_decode\AsyncOn=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+
+3.2. Analyzing design hierarchy..
+Top module: \hmac
+Used module: $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top
+Used module: $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001
+Used module: $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg
+Used module: $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg
+Used module: $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err
+Used module: $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp
+Used module: $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync
+Used module: $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync
+Used module: $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync
+Used module: $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync
+Used module: $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync
+Used module: $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync
+Used module: $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc
+Used module: \prim_secded_inv_39_32_enc
+Used module: \prim_secded_inv_64_57_enc
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec
+Used module: \prim_secded_inv_39_32_dec
+Used module: \prim_secded_inv_64_57_dec
+Used module: \sha2
+Used module: \sha2_pad
+Used module: \hmac_core
+Used module: $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer
+Used module: $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram
+Used module: $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync
+Used module: $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync
+Used module: $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync
+Used module: $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync
+Used module: $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1
+Used module: $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender
+Used module: $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf
+Used module: \prim_generic_buf
+Used module: $paramod\prim_diff_decode\AsyncOn=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Removed 0 unused modules.
+Warning: Resizing cell port $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.gen_rsp_intg.u_rsp_gen.data_i from 6 bits to 57 bits.
+Warning: Resizing cell port $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.u_socket.dev_select_i from 1 bits to 2 bits.
+Warning: Resizing cell port $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.u_chk.data_i from 50 bits to 64 bits.
+Warning: Resizing cell port hmac.u_sha2.digest from 256 bits to 32 bits.
+
+Dumping file hier_info.json ...
+ Process module "$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\\prim_fifo_sync"
+ Process module "$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\\prim_subreg"
+ Process module "$paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\\prim_fifo_sync"
+ Process module "$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\\prim_alert_sender"
+ Process module "$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\\prim_packer"
+ Process module "$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\\tlul_rsp_intg_gen"
+ Process module "$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\\hmac_reg_top"
+ Process module "$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\\tlul_socket_1n"
+ Process module "$paramod$58742bab91a003d79034aeb644264cbb951eb306\\prim_fifo_sync"
+ Process module "$paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\\prim_fifo_sync"
+ Process module "$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\\prim_subreg"
+ Process module "$paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\\tlul_fifo_sync"
+ Process module "$paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\\prim_fifo_sync"
+ Process module "$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\\prim_fifo_sync"
+ Process module "$paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\\prim_buf"
+ Process module "$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\\tlul_adapter_sram"
+ Process module "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_cmd_intg_chk"
+ Process module "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_data_integ_dec"
+ Process module "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_data_integ_enc"
+ Process module "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_err"
+ Process module "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_err_resp"
+ Process module "$paramod$b652f3dfdeef7584c496ced680b0643f32807516\\tlul_adapter_reg"
+ Process module "$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\\prim_fifo_sync"
+ Process module "$paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\\tlul_fifo_sync"
+ Process module "$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\\prim_subreg"
+ Process module "$paramod$f519e51f824927b1da80ae7de12f65225cc31206\\prim_fifo_sync"
+ Process module "$paramod\\prim_diff_decode\\AsyncOn=1'1"
+ Process module "$paramod\\prim_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0"
+ Process module "$paramod\\prim_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1"
+ Process module "$paramod\\prim_generic_flop\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0"
+ Process module "$paramod\\prim_generic_flop\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1"
+ Process module "$paramod\\prim_generic_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0"
+ Process module "$paramod\\prim_generic_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1"
+ Process module "$paramod\\prim_intr_hw\\Width=32'00000000000000000000000000000001\\FlopOutput=1'1"
+ Process module "$paramod\\prim_subreg_ext\\DW=32'00000000000000000000000000000001"
+ Process module "$paramod\\prim_subreg_ext\\DW=32'00000000000000000000000000000101"
+ Process module "$paramod\\prim_subreg_ext\\DW=32'00000000000000000000000000100000"
+ Process module "hmac_core"
+ Process module "prim_generic_buf"
+ Process module "prim_secded_inv_39_32_dec"
+ Process module "prim_secded_inv_39_32_enc"
+ Process module "prim_secded_inv_64_57_dec"
+ Process module "prim_secded_inv_64_57_enc"
+ Process module "sha2"
+ Process module "sha2_pad"
+Dumping file port_info.json ...
+
+Warnings: 43 unique messages, 45 total
+End of script. Logfile hash: a31f120628, CPU: user 14.84s system 0.68s, MEM: 990.51 MB peak
+Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3)
+Time spent: 98% 2x read_systemverilog (15 sec), 0% 1x analyze (0 sec), ...
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/hier_info.json b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/hier_info.json
new file mode 100644
index 00000000..a1a6a9a0
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/hier_info.json
@@ -0,0 +1,194334 @@
+{
+ "fileIDs": {
+ "1": "/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v",
+ "2": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv",
+ "3": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv",
+ "4": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv",
+ "5": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv",
+ "6": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv",
+ "7": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv",
+ "8": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv",
+ "9": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv",
+ "10": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop_2sync.sv",
+ "11": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv",
+ "12": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv",
+ "13": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_data_integ_dec.sv",
+ "14": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv",
+ "15": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv",
+ "16": "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_data_integ_enc.sv"
+ },
+ "hierTree": [
+ {
+ "file": "7",
+ "internalSignals": [
+ {
+ "name": "alert_test",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "alerts",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "cfg_block",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "cfg_reg",
+ "range": {
+ "lsb": 0,
+ "msb": 7
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "digest",
+ "range": {
+ "lsb": 0,
+ "msb": 255
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "digest_swap",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "endian_swap",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "err_code",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "err_valid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "event_intr",
+ "range": {
+ "lsb": 0,
+ "msb": 2
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "fifo_depth",
+ "range": {
+ "lsb": 0,
+ "msb": 4
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "fifo_empty",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "fifo_empty_event",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "fifo_empty_q",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "fifo_full",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "fifo_rdata",
+ "range": {
+ "lsb": 0,
+ "msb": 35
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "fifo_rready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "fifo_rvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "fifo_wdata",
+ "range": {
+ "lsb": 0,
+ "msb": 35
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "fifo_wready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "fifo_wvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hash_start",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hash_start_active",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hash_start_sha_disabled",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hmac_core_idle",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hmac_en",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hmac_fifo_wdata_sel",
+ "range": {
+ "lsb": 0,
+ "msb": 2
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hmac_fifo_wsel",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hmac_fifo_wvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$465.$result",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$466.$result",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$467.$result",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$468.$result",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
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+ "moduleInsts": [
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+ "file": "7",
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+ "module": "$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\\prim_alert_sender",
+ "parameters": []
+ },
+ {
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+ "module": "$paramod\\prim_intr_hw\\Width=32'00000000000000000000000000000001\\FlopOutput=1'1",
+ "parameters": []
+ },
+ {
+ "file": "7",
+ "instName": "intr_hw_hmac_done",
+ "line": 213,
+ "module": "$paramod\\prim_intr_hw\\Width=32'00000000000000000000000000000001\\FlopOutput=1'1",
+ "parameters": []
+ },
+ {
+ "file": "7",
+ "instName": "intr_hw_hmac_err",
+ "line": 237,
+ "module": "$paramod\\prim_intr_hw\\Width=32'00000000000000000000000000000001\\FlopOutput=1'1",
+ "parameters": []
+ },
+ {
+ "file": "7",
+ "instName": "u_hmac",
+ "line": 374,
+ "module": "hmac_core",
+ "parameters": []
+ },
+ {
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+ "instName": "u_msg_fifo",
+ "line": 270,
+ "module": "$paramod$f519e51f824927b1da80ae7de12f65225cc31206\\prim_fifo_sync",
+ "parameters": []
+ },
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+ "instName": "u_packer",
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+ "module": "$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\\prim_packer",
+ "parameters": []
+ },
+ {
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+ "instName": "u_reg",
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+ "module": "$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\\hmac_reg_top",
+ "parameters": []
+ },
+ {
+ "file": "7",
+ "instName": "u_sha2",
+ "line": 411,
+ "module": "sha2",
+ "parameters": []
+ },
+ {
+ "file": "7",
+ "instName": "u_tlul_adapter",
+ "line": 291,
+ "module": "$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\\tlul_adapter_sram",
+ "parameters": []
+ }
+ ],
+ "parameters": [
+ {
+ "name": "AlertAsyncOn",
+ "value": 0
+ },
+ {
+ "name": "BlockAw",
+ "value": 0
+ },
+ {
+ "name": "HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "NumWords",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
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+ {
+ "name": "ast_pkg::Ot0Sel",
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+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
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+ },
+ {
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+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
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+ "name": "ast_pkg::Pad2AstInWidth",
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+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
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+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
+ },
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+ "value": 0
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+ "value": 0
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+ {
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+ "value": 0
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+ {
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+ "value": 0
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+ {
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+ "value": 0
+ },
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+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ },
+ {
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+ "value": 0
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+ "value": 0
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
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+ "value": 0
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+ {
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+ "value": 0
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
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+ {
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+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
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+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
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+ "value": 0
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+ {
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+ },
+ {
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+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
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+ {
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+ "value": 0
+ },
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+ "value": 0
+ },
+ {
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+ "value": 0
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "clr_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "wready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wdata",
+ "range": {
+ "lsb": 0,
+ "msb": 32
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "rvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "rdata",
+ "range": {
+ "lsb": 0,
+ "msb": 32
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "depth",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\\prim_subreg": {
+ "file": "2",
+ "internalSignals": [
+ {
+ "name": "wr_data",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "wr_en",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 240,
+ "module": "$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\\prim_subreg",
+ "parameters": [
+ {
+ "name": "DW",
+ "value": 0
+ },
+ {
+ "name": "RESVAL",
+ "value": 0
+ },
+ {
+ "name": "SwAccess",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "we",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wd",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "de",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "d",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "qe",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "q",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "qs",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\\prim_fifo_sync": {
+ "file": "4",
+ "internalSignals": [
+ {
+ "name": "gen_passthru_fifo.unused_clr",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 63,
+ "module": "$paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\\prim_fifo_sync",
+ "parameters": [
+ {
+ "name": "Depth",
+ "value": 0
+ },
+ {
+ "name": "OutputZeroIfEmpty",
+ "value": 0
+ },
+ {
+ "name": "Pass",
+ "value": 0
+ },
+ {
+ "name": "Width",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
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+ },
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+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
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+ },
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+ "value": 0
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+ "value": 0
+ },
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ {
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+ "value": 0
+ },
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
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+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
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+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
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+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
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+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
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+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
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+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
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+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
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+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
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+ "value": 0
+ },
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
+ },
+ {
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+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
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+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
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+ {
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+ "value": 0
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+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
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+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
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+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
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+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
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+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
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+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
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+ "value": 0
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+ "name": "prim_secded_pkg::Secded2216ZeroWord",
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+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
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+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
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+ "value": 0
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+ "value": 0
+ },
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+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
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+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
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+ },
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+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
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+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
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+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
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+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
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+ },
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+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
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+ "value": 0
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+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
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+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
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+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
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+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
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+ "value": 0
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+ {
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+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
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+ "value": 0
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+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
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+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
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+ "value": 0
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+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
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+ "value": 0
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+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
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+ "name": "tlul_pkg::DataMaxWidth",
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+ "name": "tlul_pkg::H2DCmdFullWidth",
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+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
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+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
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+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
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+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
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+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
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+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
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+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
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+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
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+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
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+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
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+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
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+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
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+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
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+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
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+ "value": 0
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+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
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+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
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+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
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+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
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+ "value": 0
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+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
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+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
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+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
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+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
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+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
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+ "value": 0
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+ "value": 0
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+ {
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+ "value": 0
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+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
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+ "name": "pwrmgr_pkg::PowerDomains",
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+ "value": 0
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+ "value": 0
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+ "value": 0
+ },
+ {
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+ "value": 0
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+ {
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+ {
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
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+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
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+ "value": 0
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+ "value": 0
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+ {
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "msb": 0
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+ "type": "LOGIC"
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+ },
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+ "msb": 31
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+ "parameters": []
+ },
+ {
+ "file": "2",
+ "instName": "gen_rsp_intg.u_rsp_gen",
+ "line": 25,
+ "module": "prim_secded_inv_64_57_enc",
+ "parameters": []
+ }
+ ],
+ "parameters": [
+ {
+ "name": "ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "EnableDataIntgGen",
+ "value": 0
+ },
+ {
+ "name": "EnableRspIntgGen",
+ "value": 0
+ },
+ {
+ "name": "H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "TL_D_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Output",
+ "name": "tl_o",
+ "range": {
+ "lsb": 0,
+ "msb": 65
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "tl_i",
+ "range": {
+ "lsb": 0,
+ "msb": 65
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\\hmac_reg_top": {
+ "file": "7",
+ "internalSignals": [
+ {
+ "name": "addr_hit",
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+ "msb": 26
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+ "type": "LOGIC"
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+ {
+ "name": "addrmiss",
+ "range": {
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+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "alert_test_wd",
+ "range": {
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+ "msb": 0
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+ "type": "LOGIC"
+ },
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+ "value": 0
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+ "value": 0
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+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
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+ },
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+ "value": 0
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+ {
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+ "value": 0
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+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
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+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
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+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
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+ "name": "lc_ctrl_pkg::A7",
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+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
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+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
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+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
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+ },
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+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "intg_err_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "devmode_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "tl_o",
+ "range": {
+ "lsb": 0,
+ "msb": 65
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "tl_i",
+ "range": {
+ "lsb": 0,
+ "msb": 108
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "reg2hw",
+ "range": {
+ "lsb": 0,
+ "msb": 322
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "hw2reg",
+ "range": {
+ "lsb": 0,
+ "msb": 627
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "tl_win_o",
+ "range": {
+ "lsb": 0,
+ "msb": 108
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "tl_win_i",
+ "range": {
+ "lsb": 0,
+ "msb": 65
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\\tlul_socket_1n": {
+ "file": "2",
+ "internalSignals": [
+ {
+ "name": "accept_t_req",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "accept_t_rsp",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "dev_select_outstanding",
+ "range": {
+ "lsb": 0,
+ "msb": 1
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "dev_select_t",
+ "range": {
+ "lsb": 0,
+ "msb": 1
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hfifo_reqready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hold_all_requests",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "num_req_outstanding",
+ "range": {
+ "lsb": 0,
+ "msb": 8
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "tl_t_i",
+ "range": {
+ "lsb": 0,
+ "msb": 65
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "tl_t_o",
+ "range": {
+ "lsb": 0,
+ "msb": 108
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "tl_t_p",
+ "range": {
+ "lsb": 0,
+ "msb": 65
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "tl_u_i",
+ "range": {
+ "lsb": 0,
+ "msb": 197
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "tl_u_o",
+ "range": {
+ "lsb": 0,
+ "msb": 326
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 96,
+ "module": "$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\\tlul_socket_1n",
+ "moduleInsts": [
+ {
+ "file": "2",
+ "instName": "err_resp",
+ "line": 207,
+ "module": "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_err_resp",
+ "parameters": []
+ },
+ {
+ "file": "2",
+ "instName": "fifo_h",
+ "line": 67,
+ "module": "$paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\\tlul_fifo_sync",
+ "parameters": []
+ },
+ {
+ "file": "2",
+ "instName": "gen_dfifo[0].fifo_d",
+ "line": 178,
+ "module": "$paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\\tlul_fifo_sync",
+ "parameters": []
+ },
+ {
+ "file": "2",
+ "instName": "gen_dfifo[1].fifo_d",
+ "line": 178,
+ "module": "$paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\\tlul_fifo_sync",
+ "parameters": []
+ }
+ ],
+ "parameters": [
+ {
+ "name": "DReqDepth",
+ "value": 0
+ },
+ {
+ "name": "DReqPass",
+ "value": 0
+ },
+ {
+ "name": "DRspDepth",
+ "value": 0
+ },
+ {
+ "name": "DRspPass",
+ "value": 0
+ },
+ {
+ "name": "HReqDepth",
+ "value": 0
+ },
+ {
+ "name": "HReqPass",
+ "value": 0
+ },
+ {
+ "name": "HRspDepth",
+ "value": 0
+ },
+ {
+ "name": "HRspPass",
+ "value": 0
+ },
+ {
+ "name": "N",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "dev_select_i",
+ "range": {
+ "lsb": 0,
+ "msb": 1
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "tl_h_i",
+ "range": {
+ "lsb": 0,
+ "msb": 108
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "tl_h_o",
+ "range": {
+ "lsb": 0,
+ "msb": 65
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "tl_d_o",
+ "range": {
+ "lsb": 0,
+ "msb": 217
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "tl_d_i",
+ "range": {
+ "lsb": 0,
+ "msb": 131
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$58742bab91a003d79034aeb644264cbb951eb306\\prim_fifo_sync": {
+ "file": "4",
+ "internalSignals": [
+ {
+ "name": "gen_passthru_fifo.unused_clr",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 32,
+ "module": "$paramod$58742bab91a003d79034aeb644264cbb951eb306\\prim_fifo_sync",
+ "parameters": [
+ {
+ "name": "Depth",
+ "value": 0
+ },
+ {
+ "name": "OutputZeroIfEmpty",
+ "value": 0
+ },
+ {
+ "name": "Pass",
+ "value": 0
+ },
+ {
+ "name": "Width",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "clr_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "wready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wdata",
+ "range": {
+ "lsb": 0,
+ "msb": 108
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "rvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "rdata",
+ "range": {
+ "lsb": 0,
+ "msb": 108
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "depth",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\\prim_fifo_sync": {
+ "file": "4",
+ "internalSignals": [
+ {
+ "name": "gen_passthru_fifo.unused_clr",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 63,
+ "module": "$paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\\prim_fifo_sync",
+ "parameters": [
+ {
+ "name": "Depth",
+ "value": 0
+ },
+ {
+ "name": "OutputZeroIfEmpty",
+ "value": 0
+ },
+ {
+ "name": "Pass",
+ "value": 0
+ },
+ {
+ "name": "Width",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "clr_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "wready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wdata",
+ "range": {
+ "lsb": 0,
+ "msb": 64
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "rvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "rdata",
+ "range": {
+ "lsb": 0,
+ "msb": 64
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "depth",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\\prim_subreg": {
+ "file": "2",
+ "internalSignals": [
+ {
+ "name": "wr_data",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "wr_en",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 317,
+ "module": "$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\\prim_subreg",
+ "parameters": [
+ {
+ "name": "DW",
+ "value": 0
+ },
+ {
+ "name": "RESVAL",
+ "value": 0
+ },
+ {
+ "name": "SwAccess",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
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+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
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+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
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+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
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+ "value": 0
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+ "value": 0
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+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
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+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
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+ "name": "clk_i",
+ "range": {
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+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
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+ "msb": 0
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+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "we",
+ "range": {
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+ "msb": 0
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+ "type": "LOGIC"
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+ "name": "wd",
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+ "msb": 0
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+ "type": "LOGIC"
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+ "direction": "Input",
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+ "msb": 0
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+ "type": "LOGIC"
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+ "msb": 0
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+ "name": "qe",
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+ "msb": 0
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+ "type": "LOGIC"
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+ {
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+ "name": "q",
+ "range": {
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+ "msb": 0
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+ "type": "LOGIC"
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+ {
+ "direction": "Output",
+ "name": "qs",
+ "range": {
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+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\\tlul_fifo_sync": {
+ "file": "3",
+ "language": "SystemVerilog",
+ "line": 178,
+ "module": "$paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\\tlul_fifo_sync",
+ "moduleInsts": [
+ {
+ "file": "3",
+ "instName": "reqfifo",
+ "line": 32,
+ "module": "$paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\\prim_fifo_sync",
+ "parameters": []
+ },
+ {
+ "file": "3",
+ "instName": "rspfifo",
+ "line": 63,
+ "module": "$paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\\prim_fifo_sync",
+ "parameters": []
+ }
+ ],
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+ "name": "ReqDepth",
+ "value": 0
+ },
+ {
+ "name": "ReqPass",
+ "value": 0
+ },
+ {
+ "name": "RspDepth",
+ "value": 0
+ },
+ {
+ "name": "RspPass",
+ "value": 0
+ },
+ {
+ "name": "SpareReqW",
+ "value": 0
+ },
+ {
+ "name": "SpareRspW",
+ "value": 0
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+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
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+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
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+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
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+ "value": 0
+ },
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
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+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
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+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
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+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
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+ "value": 0
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+ "value": 0
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+ {
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+ "value": 0
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+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
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+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
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+ "value": 0
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+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
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+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
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+ "value": 0
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+ "value": 0
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+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
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+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
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+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "spare_req_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "spare_req_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "spare_rsp_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "spare_rsp_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "tl_h_i",
+ "range": {
+ "lsb": 0,
+ "msb": 108
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "tl_h_o",
+ "range": {
+ "lsb": 0,
+ "msb": 65
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "tl_d_o",
+ "range": {
+ "lsb": 0,
+ "msb": 108
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "tl_d_i",
+ "range": {
+ "lsb": 0,
+ "msb": 65
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\\prim_fifo_sync": {
+ "file": "4",
+ "internalSignals": [
+ {
+ "name": "gen_passthru_fifo.unused_clr",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 32,
+ "module": "$paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\\prim_fifo_sync",
+ "parameters": [
+ {
+ "name": "Depth",
+ "value": 0
+ },
+ {
+ "name": "OutputZeroIfEmpty",
+ "value": 0
+ },
+ {
+ "name": "Pass",
+ "value": 0
+ },
+ {
+ "name": "Width",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
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+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
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+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
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+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
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+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
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+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
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+ "value": 0
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+ {
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+ "value": 0
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+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
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+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
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+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
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+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
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+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
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+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
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+ "msb": 107
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+ "type": "LOGIC"
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+ "msb": 0
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+ "msb": 0
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+ "msb": 107
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+ "file": "6",
+ "internalSignals": [
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+ "range": {
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+ "type": "LOGIC"
+ },
+ {
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+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
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+ "msb": 0
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+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.fifo_incr_wptr",
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+ "msb": 0
+ },
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+ {
+ "name": "gen_normal_fifo.fifo_rptr",
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+ "msb": 1
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+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.fifo_wptr",
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+ "msb": 1
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+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.full",
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+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.rdata_int",
+ "range": {
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+ "msb": 12
+ },
+ "type": "LOGIC"
+ },
+ {
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+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.rptr_value",
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+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.storage",
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+ "msb": 12
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+ "type": "LOGIC"
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+ {
+ "name": "gen_normal_fifo.storage_rdata",
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+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.wptr_msb",
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+ "msb": 0
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+ },
+ {
+ "name": "gen_normal_fifo.wptr_value",
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+ "msb": 0
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+ "type": "LOGIC"
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+ "language": "SystemVerilog",
+ "line": 289,
+ "module": "$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\\prim_fifo_sync",
+ "parameters": [
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+ "name": "ast_pkg::NumAlerts",
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+ "name": "ast_pkg::Pad2AstInWidth",
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+ "value": 0
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+ {
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+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
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+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
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+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
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+ "value": 0
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+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
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+ "value": 0
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+ {
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
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+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
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+ "name": "TL_D_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "req_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "gnt_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "we_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "addr_o",
+ "range": {
+ "lsb": 0,
+ "msb": 8
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "wdata_o",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "wmask_o",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rdata_i",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rvalid_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rerror_i",
+ "range": {
+ "lsb": 0,
+ "msb": 1
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "tl_o",
+ "range": {
+ "lsb": 0,
+ "msb": 65
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
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+ {
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+ "moduleInsts": [
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+ "parameters": []
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+ "parameters": []
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+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
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+ "msb": 0
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+ "msb": 108
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+ "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_data_integ_dec": {
+ "file": "12",
+ "internalSignals": [
+ {
+ "name": "data_err",
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+ "msb": 1
+ },
+ "type": "LOGIC"
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+ ],
+ "language": "SystemVerilog",
+ "line": 23,
+ "module": "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_data_integ_dec",
+ "moduleInsts": [
+ {
+ "file": "12",
+ "instName": "u_data_chk",
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+ "module": "prim_secded_inv_39_32_dec",
+ "parameters": []
+ }
+ ],
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ {
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+ "value": 0
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+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ {
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+ "value": 0
+ },
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+ "value": 0
+ },
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
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+ "value": 0
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+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
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+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
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+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
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+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
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+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
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+ {
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+ "value": 0
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+ "value": 0
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+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
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+ "value": 0
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+ "value": 0
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+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
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+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
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+ "value": 0
+ },
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+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
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+ "value": 0
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+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
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+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
+ },
+ {
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+ "value": 0
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+ "value": 0
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+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
+ },
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+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
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+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
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+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "data_intg_i",
+ "range": {
+ "lsb": 0,
+ "msb": 38
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "data_err_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_data_integ_enc": {
+ "file": "15",
+ "language": "SystemVerilog",
+ "line": 36,
+ "module": "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_data_integ_enc",
+ "moduleInsts": [
+ {
+ "file": "15",
+ "instName": "u_data_gen",
+ "line": 16,
+ "module": "prim_secded_inv_39_32_enc",
+ "parameters": []
+ }
+ ],
+ "parameters": [
+ {
+ "name": "ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "TL_D_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
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+ "value": 0
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+ "value": 0
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+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
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+ "value": 0
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+ {
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+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
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+ {
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
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+ {
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+ "value": 0
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+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
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+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
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+ {
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+ "value": 0
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+ {
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+ "value": 0
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+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
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+ "value": 0
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+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
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+ "value": 0
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+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
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+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
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+ "value": 0
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+ {
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+ "value": 0
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+ {
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+ "value": 0
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+ {
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+ },
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+ "value": 0
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
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+ "value": 0
+ },
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
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+ },
+ {
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+ "value": 0
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+ {
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+ "value": 0
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+ {
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+ },
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
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+ "value": 0
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+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
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+ "value": 0
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+ },
+ {
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
+ },
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ {
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+ "value": 0
+ },
+ {
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
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+ "value": 0
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+ ],
+ "ports": [
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+ "name": "clk_i",
+ "range": {
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+ "msb": 0
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+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
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+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "err_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "tl_i",
+ "range": {
+ "lsb": 0,
+ "msb": 108
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_err_resp": {
+ "file": "3",
+ "internalSignals": [
+ {
+ "name": "err_req_pending",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
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+ "msb": 0
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+ "type": "LOGIC"
+ },
+ {
+ "name": "err_size",
+ "range": {
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+ "msb": 1
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "err_source",
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+ "lsb": 0,
+ "msb": 7
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 207,
+ "module": "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_err_resp",
+ "parameters": [
+ {
+ "name": "ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "D2HRspIntgWidth",
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+ "value": 0
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+ "name": "DataFullWidth",
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ {
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+ "value": 0
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+ {
+ "name": "TL_A_USER_DEFAULT",
+ "value": 0
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+ "name": "TL_D_USER_DEFAULT",
+ "value": 0
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+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ {
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+ "value": 0
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+ "value": 0
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+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
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+ {
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+ {
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
+ },
+ {
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+ "value": 0
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+ "value": 0
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+ {
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+ "value": 0
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+ {
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
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+ "value": 0
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+ {
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+ "value": 0
+ },
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+ "value": 0
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+ "value": 0
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+ "value": 0
+ },
+ {
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+ "value": 0
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+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
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+ {
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+ "value": 0
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+ {
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+ "value": 0
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+ "value": 0
+ },
+ {
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+ "value": 0
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
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+ {
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+ "value": 0
+ },
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+ "value": 0
+ },
+ {
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+ "value": 0
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+ {
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
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+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
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+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "tl_h_i",
+ "range": {
+ "lsb": 0,
+ "msb": 108
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "tl_h_o",
+ "range": {
+ "lsb": 0,
+ "msb": 65
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$b652f3dfdeef7584c496ced680b0643f32807516\\tlul_adapter_reg": {
+ "file": "2",
+ "internalSignals": [
+ {
+ "name": "a_ack",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "addr_align_err",
+ "range": {
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+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "d_ack",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "err_internal",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "error",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "malformed_meta_err",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "outstanding",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "rd_req",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "rdata",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "reqid",
+ "range": {
+ "lsb": 0,
+ "msb": 7
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "reqsz",
+ "range": {
+ "lsb": 0,
+ "msb": 1
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "rspop",
+ "range": {
+ "lsb": 0,
+ "msb": 2
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "tl_err",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "wr_req",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 134,
+ "module": "$paramod$b652f3dfdeef7584c496ced680b0643f32807516\\tlul_adapter_reg",
+ "moduleInsts": [
+ {
+ "file": "2",
+ "instName": "u_err",
+ "line": 131,
+ "module": "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_err",
+ "parameters": []
+ }
+ ],
+ "parameters": [
+ {
+ "name": "ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "EnableDataIntgGen",
+ "value": 0
+ },
+ {
+ "name": "H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "RegAw",
+ "value": 0
+ },
+ {
+ "name": "RegDw",
+ "value": 0
+ },
+ {
+ "name": "TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "TL_D_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
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+ {
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+ "value": 0
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+ {
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+ "value": 0
+ },
+ {
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+ "value": 0
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+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
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+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
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+ {
+ "name": "lc_ctrl_pkg::A5",
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+ {
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+ {
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+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
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+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
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+ },
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+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
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+ },
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+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
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+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
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+ "value": 0
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+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
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+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
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+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
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+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
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+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
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+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
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+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
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+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
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+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
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+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
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+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
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+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
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+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
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+ "name": "tlul_pkg::D2HRspFullWidth",
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+ "name": "gen_normal_fifo.wptr_value",
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+ "msb": 0
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+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 310,
+ "module": "$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\\prim_fifo_sync",
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ "value": 0
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+ {
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+ "value": 0
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+ {
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+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
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+ "value": 0
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+ {
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+ "value": 0
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+ {
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+ "value": 0
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+ {
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+ "value": 0
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+ {
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+ "value": 0
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+ "value": 0
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
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+ {
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
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+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "clr_i",
+ "range": {
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+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "wready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wdata",
+ "range": {
+ "lsb": 0,
+ "msb": 4
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "rvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rready",
+ "range": {
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+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
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+ "name": "rdata",
+ "range": {
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+ "msb": 4
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "depth",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\\tlul_fifo_sync": {
+ "file": "3",
+ "language": "SystemVerilog",
+ "line": 67,
+ "module": "$paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\\tlul_fifo_sync",
+ "moduleInsts": [
+ {
+ "file": "3",
+ "instName": "reqfifo",
+ "line": 32,
+ "module": "$paramod$58742bab91a003d79034aeb644264cbb951eb306\\prim_fifo_sync",
+ "parameters": []
+ },
+ {
+ "file": "3",
+ "instName": "rspfifo",
+ "line": 63,
+ "module": "$paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\\prim_fifo_sync",
+ "parameters": []
+ }
+ ],
+ "parameters": [
+ {
+ "name": "ReqDepth",
+ "value": 0
+ },
+ {
+ "name": "ReqPass",
+ "value": 0
+ },
+ {
+ "name": "RspDepth",
+ "value": 0
+ },
+ {
+ "name": "RspPass",
+ "value": 0
+ },
+ {
+ "name": "SpareReqW",
+ "value": 0
+ },
+ {
+ "name": "SpareRspW",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "spare_req_i",
+ "range": {
+ "lsb": 0,
+ "msb": 1
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "spare_req_o",
+ "range": {
+ "lsb": 0,
+ "msb": 1
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "spare_rsp_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "spare_rsp_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "tl_h_i",
+ "range": {
+ "lsb": 0,
+ "msb": 108
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "tl_h_o",
+ "range": {
+ "lsb": 0,
+ "msb": 65
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "tl_d_o",
+ "range": {
+ "lsb": 0,
+ "msb": 108
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "tl_d_i",
+ "range": {
+ "lsb": 0,
+ "msb": 65
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\\prim_subreg": {
+ "file": "2",
+ "internalSignals": [
+ {
+ "name": "wr_data",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "wr_en",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 584,
+ "module": "$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\\prim_subreg",
+ "parameters": [
+ {
+ "name": "DW",
+ "value": 0
+ },
+ {
+ "name": "RESVAL",
+ "value": 0
+ },
+ {
+ "name": "SwAccess",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "we",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wd",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "de",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "d",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "qe",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "q",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "qs",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod$f519e51f824927b1da80ae7de12f65225cc31206\\prim_fifo_sync": {
+ "file": "7",
+ "internalSignals": [
+ {
+ "name": "gen_normal_fifo.empty",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.fifo_empty",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.fifo_incr_rptr",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.fifo_incr_wptr",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.fifo_rptr",
+ "range": {
+ "lsb": 0,
+ "msb": 4
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.fifo_wptr",
+ "range": {
+ "lsb": 0,
+ "msb": 4
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.full",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.rdata_int",
+ "range": {
+ "lsb": 0,
+ "msb": 35
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.rptr_msb",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.rptr_value",
+ "range": {
+ "lsb": 0,
+ "msb": 3
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.storage",
+ "range": {
+ "lsb": 0,
+ "msb": 575
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.storage_rdata",
+ "range": {
+ "lsb": 0,
+ "msb": 35
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.wptr_msb",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_normal_fifo.wptr_value",
+ "range": {
+ "lsb": 0,
+ "msb": 3
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 270,
+ "module": "$paramod$f519e51f824927b1da80ae7de12f65225cc31206\\prim_fifo_sync",
+ "parameters": [
+ {
+ "name": "Depth",
+ "value": 0
+ },
+ {
+ "name": "OutputZeroIfEmpty",
+ "value": 0
+ },
+ {
+ "name": "Pass",
+ "value": 0
+ },
+ {
+ "name": "Width",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "clr_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "wready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wdata",
+ "range": {
+ "lsb": 0,
+ "msb": 35
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "rvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "rdata",
+ "range": {
+ "lsb": 0,
+ "msb": 35
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "depth",
+ "range": {
+ "lsb": 0,
+ "msb": 4
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod\\prim_diff_decode\\AsyncOn=1'1": {
+ "file": "5",
+ "internalSignals": [
+ {
+ "name": "gen_async.diff_check_ok",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_async.diff_n_edge",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_async.diff_nd",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_async.diff_nq",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_async.diff_p_edge",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_async.diff_pd",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_async.diff_pq",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_async.level",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_async.state_d",
+ "range": {
+ "lsb": 0,
+ "msb": 1
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "gen_async.state_q",
+ "range": {
+ "lsb": 0,
+ "msb": 1
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "level_d",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "level_q",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 55,
+ "module": "$paramod\\prim_diff_decode\\AsyncOn=1'1",
+ "moduleInsts": [
+ {
+ "file": "5",
+ "instName": "gen_async.i_sync_n",
+ "line": 63,
+ "module": "$paramod\\prim_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1",
+ "parameters": []
+ },
+ {
+ "file": "5",
+ "instName": "gen_async.i_sync_p",
+ "line": 53,
+ "module": "$paramod\\prim_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0",
+ "parameters": []
+ }
+ ],
+ "parameters": [
+ {
+ "name": "AsyncOn",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "diff_pi",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "diff_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "level_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "rise_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "fall_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "event_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "sigint_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod\\prim_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0": {
+ "file": "9",
+ "language": "SystemVerilog",
+ "line": 53,
+ "module": "$paramod\\prim_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0",
+ "moduleInsts": [
+ {
+ "file": "9",
+ "instName": "gen_generic.u_impl_generic",
+ "line": 29,
+ "module": "$paramod\\prim_generic_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0",
+ "parameters": []
+ }
+ ],
+ "parameters": [
+ {
+ "name": "ResetValue",
+ "value": 0
+ },
+ {
+ "name": "Width",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "d_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "q_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod\\prim_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1": {
+ "file": "9",
+ "language": "SystemVerilog",
+ "line": 63,
+ "module": "$paramod\\prim_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1",
+ "moduleInsts": [
+ {
+ "file": "9",
+ "instName": "gen_generic.u_impl_generic",
+ "line": 29,
+ "module": "$paramod\\prim_generic_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1",
+ "parameters": []
+ }
+ ],
+ "parameters": [
+ {
+ "name": "ResetValue",
+ "value": 0
+ },
+ {
+ "name": "Width",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "d_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "q_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod\\prim_generic_flop\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0": {
+ "file": "10",
+ "language": "SystemVerilog",
+ "line": 22,
+ "module": "$paramod\\prim_generic_flop\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0",
+ "parameters": [
+ {
+ "name": "ResetValue",
+ "value": 0
+ },
+ {
+ "name": "Width",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "d_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "q_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod\\prim_generic_flop\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1": {
+ "file": "10",
+ "language": "SystemVerilog",
+ "line": 22,
+ "module": "$paramod\\prim_generic_flop\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1",
+ "parameters": [
+ {
+ "name": "ResetValue",
+ "value": 0
+ },
+ {
+ "name": "Width",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "d_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "q_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod\\prim_generic_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0": {
+ "file": "8",
+ "internalSignals": [
+ {
+ "name": "intq",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 29,
+ "module": "$paramod\\prim_generic_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0",
+ "moduleInsts": [
+ {
+ "file": "8",
+ "instName": "u_sync_1",
+ "line": 22,
+ "module": "$paramod\\prim_generic_flop\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0",
+ "parameters": []
+ },
+ {
+ "file": "8",
+ "instName": "u_sync_2",
+ "line": 32,
+ "module": "$paramod\\prim_generic_flop\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0",
+ "parameters": []
+ }
+ ],
+ "parameters": [
+ {
+ "name": "ResetValue",
+ "value": 0
+ },
+ {
+ "name": "Width",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "d_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "q_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod\\prim_generic_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1": {
+ "file": "8",
+ "internalSignals": [
+ {
+ "name": "intq",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 29,
+ "module": "$paramod\\prim_generic_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1",
+ "moduleInsts": [
+ {
+ "file": "8",
+ "instName": "u_sync_1",
+ "line": 22,
+ "module": "$paramod\\prim_generic_flop\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1",
+ "parameters": []
+ },
+ {
+ "file": "8",
+ "instName": "u_sync_2",
+ "line": 32,
+ "module": "$paramod\\prim_generic_flop\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1",
+ "parameters": []
+ }
+ ],
+ "parameters": [
+ {
+ "name": "ResetValue",
+ "value": 0
+ },
+ {
+ "name": "Width",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "d_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "q_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod\\prim_intr_hw\\Width=32'00000000000000000000000000000001\\FlopOutput=1'1": {
+ "file": "7",
+ "internalSignals": [
+ {
+ "name": "new_event",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 213,
+ "module": "$paramod\\prim_intr_hw\\Width=32'00000000000000000000000000000001\\FlopOutput=1'1",
+ "parameters": [
+ {
+ "name": "FlopOutput",
+ "value": 0
+ },
+ {
+ "name": "Width",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "event_intr_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "reg2hw_intr_enable_q_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "reg2hw_intr_test_q_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "reg2hw_intr_test_qe_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "reg2hw_intr_state_q_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "hw2reg_intr_state_de_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "hw2reg_intr_state_d_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "intr_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod\\prim_subreg_ext\\DW=32'00000000000000000000000000000001": {
+ "file": "2",
+ "language": "SystemVerilog",
+ "line": 394,
+ "module": "$paramod\\prim_subreg_ext\\DW=32'00000000000000000000000000000001",
+ "parameters": [
+ {
+ "name": "DW",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "re",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "we",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wd",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "d",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "qe",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "qre",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "q",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "qs",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod\\prim_subreg_ext\\DW=32'00000000000000000000000000000101": {
+ "file": "2",
+ "language": "SystemVerilog",
+ "line": 569,
+ "module": "$paramod\\prim_subreg_ext\\DW=32'00000000000000000000000000000101",
+ "parameters": [
+ {
+ "name": "DW",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "re",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "we",
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+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wd",
+ "range": {
+ "lsb": 0,
+ "msb": 4
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "d",
+ "range": {
+ "lsb": 0,
+ "msb": 4
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "qe",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "qre",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "q",
+ "range": {
+ "lsb": 0,
+ "msb": 4
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "qs",
+ "range": {
+ "lsb": 0,
+ "msb": 4
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "$paramod\\prim_subreg_ext\\DW=32'00000000000000000000000000100000": {
+ "file": "2",
+ "language": "SystemVerilog",
+ "line": 610,
+ "module": "$paramod\\prim_subreg_ext\\DW=32'00000000000000000000000000100000",
+ "parameters": [
+ {
+ "name": "DW",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "re",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "we",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wd",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "d",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "qe",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "qre",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "q",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "qs",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "hmac_core": {
+ "file": "7",
+ "internalSignals": [
+ {
+ "name": "clr_fifo_wdata_sel",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "clr_txcount",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hash_process",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hash_start",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hmac_hash_done",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hmac_sha_rvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "i_pad",
+ "range": {
+ "lsb": 0,
+ "msb": 511
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "inc_txcount",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "o_pad",
+ "range": {
+ "lsb": 0,
+ "msb": 511
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "pad_index",
+ "range": {
+ "lsb": 0,
+ "msb": 3
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "reg_hash_process_flag",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "round_d",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "round_q",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "sel_msglen",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "sel_rdata",
+ "range": {
+ "lsb": 0,
+ "msb": 1
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "st_d",
+ "range": {
+ "lsb": 0,
+ "msb": 2
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "st_q",
+ "range": {
+ "lsb": 0,
+ "msb": 2
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "txcnt_eq_blksz",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "txcount",
+ "range": {
+ "lsb": 0,
+ "msb": 63
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "update_round",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 374,
+ "module": "hmac_core",
+ "parameters": [
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "secret_key",
+ "range": {
+ "lsb": 0,
+ "msb": 255
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wipe_secret",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wipe_v",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "hmac_en",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "reg_hash_start",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "reg_hash_process",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "hash_done",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "sha_hash_start",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "sha_hash_process",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "sha_hash_done",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "sha_rvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "sha_rready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "fifo_rvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "fifo_rready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "fifo_wsel",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "fifo_wvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "fifo_wdata_sel",
+ "range": {
+ "lsb": 0,
+ "msb": 2
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "fifo_wready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "message_length",
+ "range": {
+ "lsb": 0,
+ "msb": 63
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "sha_message_length",
+ "range": {
+ "lsb": 0,
+ "msb": 63
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "idle",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "fifo_rdata",
+ "range": {
+ "lsb": 0,
+ "msb": 35
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "sha_rdata",
+ "range": {
+ "lsb": 0,
+ "msb": 35
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "prim_generic_buf": {
+ "file": "14",
+ "language": "SystemVerilog",
+ "line": 31,
+ "module": "prim_generic_buf",
+ "parameters": [
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "in_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "out_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "prim_secded_inv_39_32_dec": {
+ "file": "13",
+ "language": "SystemVerilog",
+ "line": 17,
+ "module": "prim_secded_inv_39_32_dec",
+ "parameters": [
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "data_i",
+ "range": {
+ "lsb": 0,
+ "msb": 38
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "data_o",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "syndrome_o",
+ "range": {
+ "lsb": 0,
+ "msb": 6
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "err_o",
+ "range": {
+ "lsb": 0,
+ "msb": 1
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "prim_secded_inv_39_32_enc": {
+ "file": "16",
+ "language": "SystemVerilog",
+ "line": 16,
+ "module": "prim_secded_inv_39_32_enc",
+ "parameters": [
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "data_i",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "data_o",
+ "range": {
+ "lsb": 0,
+ "msb": 38
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "prim_secded_inv_64_57_dec": {
+ "file": "12",
+ "language": "SystemVerilog",
+ "line": 16,
+ "module": "prim_secded_inv_64_57_dec",
+ "parameters": [
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "data_i",
+ "range": {
+ "lsb": 0,
+ "msb": 63
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "data_o",
+ "range": {
+ "lsb": 0,
+ "msb": 56
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "syndrome_o",
+ "range": {
+ "lsb": 0,
+ "msb": 6
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "err_o",
+ "range": {
+ "lsb": 0,
+ "msb": 1
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "prim_secded_inv_64_57_enc": {
+ "file": "15",
+ "language": "SystemVerilog",
+ "line": 25,
+ "module": "prim_secded_inv_64_57_enc",
+ "parameters": [
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
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+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wipe_secret",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wipe_v",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "fifo_rvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "fifo_rready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "sha_en",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "hash_start",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "hash_process",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "hash_done",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "message_length",
+ "range": {
+ "lsb": 0,
+ "msb": 63
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "digest",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "idle",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "fifo_rdata",
+ "range": {
+ "lsb": 0,
+ "msb": 35
+ },
+ "type": "LOGIC"
+ }
+ ]
+ },
+ "sha2_pad": {
+ "file": "11",
+ "internalSignals": [
+ {
+ "name": "fifo_partial",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "hash_process_flag",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "inc_txcount",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "sel_data",
+ "range": {
+ "lsb": 0,
+ "msb": 2
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "st_d",
+ "range": {
+ "lsb": 0,
+ "msb": 2
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "st_q",
+ "range": {
+ "lsb": 0,
+ "msb": 2
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "tx_count",
+ "range": {
+ "lsb": 0,
+ "msb": 63
+ },
+ "type": "LOGIC"
+ },
+ {
+ "name": "txcnt_eq_1a0",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "language": "SystemVerilog",
+ "line": 296,
+ "module": "sha2_pad",
+ "parameters": [
+ {
+ "name": "ast_pkg::AST_RST_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcChannels",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AdcDataWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::AsSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ast2PadOutWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::CgSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::EntropyStreams",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::FlaSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::GdSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Hc2LcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Lc2HcTrCyc",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::NumIoRails",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot0Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot1Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot2Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot3Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot4Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Ot5Sel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::OtpSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::Pad2AstInWidth",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsHiSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::TsLoSel",
+ "value": 0
+ },
+ {
+ "name": "ast_pkg::UsbCalibWidth",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_MODE_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::EDN_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "edn_pkg::FIPS_ENDPOINT_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::CSRNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::FIPS_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "entropy_src_pkg::RNG_BUS_WIDTH",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::AllPagesW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrByteW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmRes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusPgmResWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::BusWordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowRead",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CfgAllowReadProgErase",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::CreatorSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataByteWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::EdnWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FLASH_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::FifoDepthW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwDataRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoPageAttr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::HwInfoRules",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoPartitionEndAddr",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypeSize",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::IsolatedPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::KeyWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::LfsrWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::MpRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::NumSeeds",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerInfoPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::OwnerSeedIdx",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::PhyAddrStart",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RmaWipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstAddrKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstDataKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrPermDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::RndCnstLfsrSeedDefault",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoPageSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedInfoSel",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::SeedWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WipeEntries",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::BytesPerWord",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::ExecEn",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_EN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_RD_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::MemAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos0",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos1",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumInfos2",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::NumRegions",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBankWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegBusPgmResBytes",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegNumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPageWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::RegPagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_ctrl_reg_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::AddrBitsRemain",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BankW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusBankAddrW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::BusWordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::CipherCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::DataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::EccWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::FullDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::GfMultCycles",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfoTypesWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::InfosPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::KeySize",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::LsbAddrBit",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::MetaDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBanks",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::NumBuf",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PageW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::PagesPerBank",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ProgTypes",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderDepth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::RspOrderFifoWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::ScrDataWidth",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WidthMultiple",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordSelW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordW",
+ "value": 0
+ },
+ {
+ "name": "flash_phy_pkg::WordsPerPage",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::BlockAw",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_FATAL_FAULT_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_DIGEST_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_ENDIAN_SWAP_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CFG_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_DIGEST_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_HMAC_ERR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_KEY_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_FIFO_SIZE",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_LOWER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_MSG_LENGTH_UPPER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_FIFO_EMPTY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::HMAC_WIPE_SECRET_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "hmac_reg_pkg::NumWords",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_REQ_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "jtag_pkg::JTAG_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A11",
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+ },
+ {
+ "name": "lc_ctrl_pkg::A2",
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+ {
+ "name": "lc_ctrl_pkg::A3",
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+ },
+ {
+ "name": "lc_ctrl_pkg::A4",
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+ {
+ "name": "lc_ctrl_pkg::A5",
+ "value": 0
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+ {
+ "name": "lc_ctrl_pkg::A6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::A9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::B9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::C9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D1",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D10",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D11",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D12",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D13",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D14",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D15",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D2",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D3",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D4",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D5",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D6",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D7",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D8",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::D9",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::DecLcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::E0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::F0",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LC_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcCountWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcIdStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcKeymgrDivWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcStateWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcTokenWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::LcValueWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcCountValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStateValues",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumLcStates",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::NumTokens",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::RmaSeedWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TokenIdxWidth",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TransTokenIdxMatrix",
+ "value": 0
+ },
+ {
+ "name": "lc_ctrl_pkg::TxWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ConstSelWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DaiCmdWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EdnDataWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::FlashKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::KeyMgrKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestSets",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPartWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumPresentRounds",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumScrmblKeys",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_KEYMGR_KEY_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OTP_LC_DATA_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtbnNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrShift",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpDepth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpErrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpIfWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpPwrSeqWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpSizeWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OtpWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestConstDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstDigestIVDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstKeyDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RndCnstRawUnlockTokenDefault",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockHalfWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblBlockWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::ScrmblKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeySeedWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramKeyWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SramNonceWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::SwWindowAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CoreAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorRootKeyShare1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgAstInitEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashDataDefaultCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgFlashInfoBootDataCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgKeyIsValidSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRngEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgRomExtSkuSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifyOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::CreatorSwCfgUseSwRsaVerifySize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::DeviceIdSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnCsrngSwAppReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwOverSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnEntropySrcFwReadSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::EnSramIfetchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashAddrKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::FlashDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::HwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LcTransitionCntSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::LifeCycleSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ManufStateSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumAlerts",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDaiWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDebugWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumDigestWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumErrorEntries",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumPart",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSramKeyReqSlots",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::NumSwCfgWindowWords",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CORE_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CHECK_PENDING_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_DAI_IDLE_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LCI_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_SW_CFG_WINDOW_SIZE",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OtpByteAddrWidth",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::OwnerSwCfgSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::PrimAw",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RmaTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertAccumThreshSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertEscalationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertPhaseCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomAlertTimeoutCyclesSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomBootstrapEnSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomErrorReportingSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomFaultResponseSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::RomLocalAlertClassificationSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::ScratchSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret0Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret1Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2DigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Offset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::Secret2Size",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::SramDataKeySeedSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestExitTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::TestUnlockTokenSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestDigestSize",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestOffset",
+ "value": 0
+ },
+ {
+ "name": "otp_ctrl_reg_pkg::VendorTestSize",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_RX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_alert_pkg::ALERT_TX_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM32_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_PERM64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRESENT_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ALPHA_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_ROUND_CONST",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SBOX4_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS64_INV",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST0",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST1",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST2",
+ "value": 0
+ },
+ {
+ "name": "prim_cipher_pkg::PRINCE_SHIFT_ROWS_CONST3",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi12Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi16Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi4Width",
+ "value": 0
+ },
+ {
+ "name": "prim_mubi_pkg::MuBi8Width",
+ "value": 0
+ },
+ {
+ "name": "prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::Secded7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv2822ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv6457ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInv7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming2216ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming3932ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7264ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroEcc",
+ "value": 0
+ },
+ {
+ "name": "prim_secded_pkg::SecdedInvHamming7668ZeroWord",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ALWAYS_ON_DOMAIN",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::HwResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::NumSwRstReq",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_AST_RSP_SYNC_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_CPU_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_FLASH_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_LC_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_OTP_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PWR_RST_RSP_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::PowerDomains",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::RSTREQS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetEscIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetMainPwrIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::ResetSwReqIdx",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::TotalResetWidth",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_pkg::WAKEUPS_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumRstReqs",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::NumWkups",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_PERMIT",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::ArbiterImpl",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::D2HRspMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::DataMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdFullWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdIntgWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::H2DCmdMaxWidth",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_A_USER_DEFAULT",
+ "value": 0
+ },
+ {
+ "name": "tlul_pkg::TL_D_USER_DEFAULT",
+ "value": 0
+ }
+ ],
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wipe_secret",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "wipe_v",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "fifo_rvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "fifo_rready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "shaf_rvalid",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "shaf_rdata",
+ "range": {
+ "lsb": 0,
+ "msb": 31
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "shaf_rready",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "sha_en",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "hash_start",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "hash_process",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "hash_done",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "message_length",
+ "range": {
+ "lsb": 0,
+ "msb": 63
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "msg_feed_complete",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "fifo_rdata",
+ "range": {
+ "lsb": 0,
+ "msb": 35
+ },
+ "type": "LOGIC"
+ }
+ ]
+ }
+ }
+}
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/hmac_analyzer.cmd b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/hmac_analyzer.cmd
new file mode 100644
index 00000000..ef148b33
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/hmac_analyzer.cmd
@@ -0,0 +1,60 @@
+read_verilog -sv /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v
+plugin -i systemverilog
+read_systemverilog -synth -top hmac -y ../../../../.././rtl/ -I../../../../.././rtl/ -I../../../../.. -I/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl +libext+.v+.sv -sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_util_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/pwrmgr_reg_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/pwrmgr_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_ram_1p_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_mubi_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_cipher_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_alert_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_count_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/jtag_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/entropy_src_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/edn_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/top_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_ctrl_reg_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_ctrl_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_phy_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_reg_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/lc_ctrl_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/otp_ctrl_reg_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/otp_ctrl_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/ast_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_core.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_reg_top.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_alert_sender.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_buf.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_diff_decode.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_fifo_sync.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_flop_2sync.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_buf.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_flop.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_flop_2sync.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_intr_hw.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_packer.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_39_32_dec.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_39_32_enc.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_64_57_dec.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_64_57_enc.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg_ext.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/sha2.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/sha2_pad.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_adapter_reg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_adapter_sram.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_cmd_intg_chk.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_data_integ_dec.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_data_integ_enc.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_err.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_err_resp.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_fifo_sync.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_rsp_intg_gen.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_socket_1n.sv \
+
+analyze -top hmac
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/port_info.json b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/port_info.json
new file mode 100644
index 00000000..0b582156
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/port_info.json
@@ -0,0 +1,97 @@
+[
+ {
+ "ports": [
+ {
+ "direction": "Input",
+ "name": "clk_i",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "rst_ni",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "intr_hmac_done_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "intr_fifo_empty_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "intr_hmac_err_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "idle_o",
+ "range": {
+ "lsb": 0,
+ "msb": 0
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "alert_rx_i",
+ "range": {
+ "lsb": 0,
+ "msb": 3
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "alert_tx_o",
+ "range": {
+ "lsb": 0,
+ "msb": 1
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Output",
+ "name": "tl_o",
+ "range": {
+ "lsb": 0,
+ "msb": 65
+ },
+ "type": "LOGIC"
+ },
+ {
+ "direction": "Input",
+ "name": "tl_i",
+ "range": {
+ "lsb": 0,
+ "msb": 108
+ },
+ "type": "LOGIC"
+ }
+ ],
+ "topModule": "hmac"
+ }
+]
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/file.lst b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/file.lst
new file mode 100644
index 00000000..debb6973
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/file.lst
@@ -0,0 +1,56 @@
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_subreg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_util_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/pwrmgr_reg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/pwrmgr_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_ram_1p_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_mubi_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_cipher_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_alert_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_count_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/jtag_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/entropy_src_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/edn_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/top_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/flash_ctrl_reg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/flash_ctrl_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/flash_phy_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_reg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/lc_ctrl_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/otp_ctrl_reg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/otp_ctrl_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/ast_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_core.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_reg_top.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_alert_sender.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_buf.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_diff_decode.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_fifo_sync.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_flop_2sync.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_generic_buf.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_generic_flop.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_generic_flop_2sync.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_intr_hw.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_packer.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_dec.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_enc.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_dec.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_enc.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_subreg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_subreg_ext.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/sha2.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/sha2_pad.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_adapter_reg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_adapter_sram.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_cmd_intg_chk.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_data_integ_dec.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_data_integ_enc.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_err.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_err_resp.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_fifo_sync.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_rsp_intg_gen.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_socket_1n.sv
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/file_elab.lst b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/file_elab.lst
new file mode 100644
index 00000000..debb6973
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/file_elab.lst
@@ -0,0 +1,56 @@
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_subreg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_util_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/pwrmgr_reg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/pwrmgr_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_ram_1p_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_mubi_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_cipher_pkg.sv
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diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/file_map.lst b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/file_map.lst
new file mode 100644
index 00000000..81d77f8d
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/file_map.lst
@@ -0,0 +1,56 @@
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diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/ast_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/ast_pkg.sv
new file mode 100644
index 00000000..080a0f21
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/ast_pkg.sv
@@ -0,0 +1,165 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//############################################################################
+// *Name: ast_pkg
+// *Module Description: AST Package
+//############################################################################
+
+
+
+
+package ast_pkg;
+
+// Alerts
+parameter int unsigned NumAlerts = 13;
+parameter int unsigned NumIoRails = 2;
+parameter int unsigned AsSel = 0;
+parameter int unsigned CgSel = 1;
+parameter int unsigned GdSel = 2;
+parameter int unsigned TsHiSel = 3;
+parameter int unsigned TsLoSel = 4;
+parameter int unsigned FlaSel = 5;
+parameter int unsigned OtpSel = 6;
+parameter int unsigned Ot0Sel = 7;
+parameter int unsigned Ot1Sel = 8;
+parameter int unsigned Ot2Sel = 9;
+parameter int unsigned Ot3Sel = 10;
+parameter int unsigned Ot4Sel = 11;
+parameter int unsigned Ot5Sel = 12;
+//
+parameter int unsigned Lc2HcTrCyc = 104; // (100+4)x5 = 520 us
+parameter int unsigned Hc2LcTrCyc = 40; // (36+4)x5 = 200 us
+//
+parameter int unsigned EntropyStreams = 4;
+parameter int unsigned AdcChannels = 2;
+parameter int unsigned AdcDataWidth = 10;
+parameter int unsigned UsbCalibWidth = 20;
+parameter int unsigned Ast2PadOutWidth = 9;
+parameter int unsigned Pad2AstInWidth = 9;
+
+// These LFSR parameters have been generated with
+// $ ./util/design/gen-lfsr-seed.py --width 64 --seed 691876113 --prefix ""
+parameter int LfsrWidth = 64;
+typedef logic [LfsrWidth-1:0] lfsr_seed_t;
+typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
+parameter lfsr_seed_t RndCnstLfsrSeedDefault = 64'h22d326255bd24320;
+parameter lfsr_perm_t RndCnstLfsrPermDefault = {
+ 128'h16108c9f9008aa37e5118d1ec1df64a7,
+ 256'h24f3f1b73537f42d38383ee8f897286df81d49ab54b6bbbb666cbd1a16c41252
+};
+
+// Memories Read-Write Margin Interface
+typedef struct packed {
+ logic marg_en_a;
+ logic [4-1:0] marg_a;
+ logic marg_en_b;
+ logic [4-1:0] marg_b;
+} dpm_rm_t;
+
+typedef struct packed {
+ logic marg_en;
+ logic [4-1:0] marg;
+} spm_rm_t;
+
+// ADC Interface
+typedef struct packed {
+ logic [AdcChannels-1:0] channel_sel;
+ logic pd;
+} adc_ast_req_t;
+
+typedef struct packed {
+ logic [AdcDataWidth-1:0] data;
+ logic data_valid;
+} adc_ast_rsp_t;
+
+// Analog Signal
+
+
+
+typedef logic awire_t;
+
+
+// Clock & Resets Interface
+typedef struct packed {
+ logic clk_sys;
+ logic clk_io;
+ logic clk_usb;
+ logic clk_aon;
+} ast_clks_t;
+
+typedef struct packed {
+ logic aon_pok;
+} ast_rst_t;
+
+parameter ast_rst_t AST_RST_DEFAULT = '{
+ aon_pok: 1'b1
+};
+
+typedef struct packed {
+ logic [NumIoRails-1:0] io_pok;
+} ast_status_t;
+
+typedef struct packed {
+ logic aon_pok;
+ logic vcc_pok;
+ logic main_pok;
+ logic [NumIoRails-1:0] io_pok;
+} ast_pwst_t;
+
+// Alerts Interface
+typedef struct packed {
+ logic p;
+ logic n;
+} ast_dif_t;
+
+typedef struct packed {
+ ast_dif_t [NumAlerts-1:0] alerts;
+} ast_alert_req_t;
+
+typedef struct packed {
+ ast_dif_t [NumAlerts-1:0] alerts_ack;
+ ast_dif_t [NumAlerts-1:0] alerts_trig;
+} ast_alert_rsp_t;
+
+// Ack mode enumerations
+typedef enum logic {
+ ImmAck = 0,
+ SwAck = 1
+} ast_ack_mode_e;
+
+// Clocks Oschillator Bypass
+typedef struct packed {
+ logic usb;
+ logic sys;
+ logic io;
+ logic aon;
+} clks_osc_byp_t;
+
+typedef enum logic [4-1:0] {
+ ObsNon = 4'h0, // No module observed (disable)
+ ObsAst = 4'h1, // Observe AST
+ ObsFla = 4'h2, // Observe FLASH
+ ObsOtp = 4'h3, // Observe OTP
+ ObsOt0 = 4'h4, // Observe OT0
+ ObsOt1 = 4'h5, // Observe OT1
+ ObsOt2 = 4'h6, // Observe OT2
+ ObsOt3 = 4'h7, // Observe OT3
+ ObsRs0 = 4'h8, // RESERVED
+ ObsRs1 = 4'h9, // RESERVED
+ ObsRs2 = 4'hA, // RESERVED
+ ObsRs3 = 4'hB, // RESERVED
+ ObsRs4 = 4'hC, // RESERVED
+ ObsRs5 = 4'hD, // RESERVED
+ ObsRs6 = 4'hE, // RESERVED
+ ObsRs7 = 4'hF // RESERVED
+} ast_omdl_e;
+
+typedef struct packed {
+ logic [4-1:0] obgsl;
+ ast_omdl_e obmsl;
+ prim_mubi_pkg::mubi4_t obmen;
+} ast_obs_ctrl_t;
+
+endpackage // of ast_pkg
+
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/edn_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/edn_pkg.sv
new file mode 100644
index 00000000..b156b0a3
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/edn_pkg.sv
@@ -0,0 +1,35 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+//`include "entropy_src_pkg.sv"
+package edn_pkg;
+ ///////////////////////////
+ // Peripheral Interfaces //
+ ///////////////////////////
+
+ parameter int unsigned ENDPOINT_BUS_WIDTH = 32;
+ parameter int unsigned FIPS_ENDPOINT_BUS_WIDTH = entropy_src_pkg::FIPS_BUS_WIDTH +
+ ENDPOINT_BUS_WIDTH;
+
+ // EDN request interface
+ typedef struct packed {
+ logic edn_req;
+ } edn_req_t;
+ typedef struct packed {
+ logic edn_ack;
+ logic edn_fips;
+ logic [ENDPOINT_BUS_WIDTH-1:0] edn_bus;
+ } edn_rsp_t;
+
+ parameter edn_req_t EDN_REQ_DEFAULT = '0;
+ parameter edn_rsp_t EDN_RSP_DEFAULT = '0;
+
+ // Sparse four-value signal type
+ parameter int EDN_MODE_WIDTH = 4;
+ typedef enum logic [EDN_MODE_WIDTH-1:0] {
+ EDN_FIELD_ON = 4'b1010
+ } edn_enb_e;
+
+endpackage : edn_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/entropy_src_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/entropy_src_pkg.sv
new file mode 100644
index 00000000..69cc8425
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/entropy_src_pkg.sv
@@ -0,0 +1,66 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+
+package entropy_src_pkg;
+
+ //-------------------------
+ // Entropy Interface
+ //-------------------------
+
+ parameter int RNG_BUS_WIDTH = 4;
+ parameter int CSRNG_BUS_WIDTH = 384;
+ parameter int FIPS_BUS_WIDTH = 1;
+
+ // es entropy i/f
+ typedef struct packed {
+ logic es_ack;
+ logic [CSRNG_BUS_WIDTH-1:0] es_bits;
+ logic [FIPS_BUS_WIDTH-1:0] es_fips;
+ } entropy_src_hw_if_rsp_t;
+
+ typedef struct packed {
+ logic es_req;
+ } entropy_src_hw_if_req_t;
+
+ parameter entropy_src_hw_if_req_t ENTROPY_SRC_HW_IF_REQ_DEFAULT = '{default: '0};
+ parameter entropy_src_hw_if_rsp_t ENTROPY_SRC_HW_IF_RSP_DEFAULT = '{default: '0};
+
+
+ // ast rng i/f
+ typedef struct packed {
+ logic rng_enable;
+ } entropy_src_rng_req_t;
+
+ typedef struct packed {
+ logic rng_valid;
+ logic [RNG_BUS_WIDTH-1:0] rng_b;
+ } entropy_src_rng_rsp_t;
+
+ parameter entropy_src_rng_req_t ENTROPY_SRC_RNG_REQ_DEFAULT = '{default: '0};
+ parameter entropy_src_rng_rsp_t ENTROPY_SRC_RNG_RSP_DEFAULT = '{default: '0};
+
+ // external health test i/f
+ typedef struct packed {
+ logic [RNG_BUS_WIDTH-1:0] entropy_bit;
+ logic entropy_bit_valid;
+ logic clear;
+ logic active;
+ logic [15:0] thresh_hi;
+ logic [15:0] thresh_lo;
+ logic [15:0] window;
+ } entropy_src_xht_req_t;
+
+ typedef struct packed {
+ logic[15:0] test_cnt;
+ logic test_fail_hi_pulse;
+ logic test_fail_lo_pulse;
+ } entropy_src_xht_rsp_t;
+
+ parameter entropy_src_xht_req_t ENTROPY_SRC_XHT_REQ_DEFAULT = '{default: '0};
+ parameter entropy_src_xht_rsp_t ENTROPY_SRC_XHT_RSP_DEFAULT = '{default: '0};
+
+
+endpackage : entropy_src_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/flash_ctrl_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/flash_ctrl_pkg.sv
new file mode 100644
index 00000000..bd07ee4d
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/flash_ctrl_pkg.sv
@@ -0,0 +1,597 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Flash Controller module.
+//
+
+package flash_ctrl_pkg;
+
+ // design parameters that can be altered through topgen
+ parameter int unsigned NumBanks = flash_ctrl_reg_pkg::RegNumBanks;
+ parameter int unsigned PagesPerBank = flash_ctrl_reg_pkg::RegPagesPerBank;
+ parameter int unsigned BusPgmResBytes = flash_ctrl_reg_pkg::RegBusPgmResBytes;
+
+ // fixed parameters of flash derived from topgen parameters
+ parameter int DataWidth = 64;
+ parameter int MetaDataWidth = 12;
+ parameter int InfoTypes = 3; // How many types of info per bank
+
+// The following hard-wired values are there to work-around verilator.
+// For some reason if the values are assigned through parameters verilator thinks
+// they are not constant
+ parameter int InfoTypeSize [InfoTypes] = '{
+ 10,
+ 1,
+ 2
+ };
+ parameter int InfosPerBank = max_info_pages('{
+ 10,
+ 1,
+ 2
+ });
+ parameter int WordsPerPage = 256; // Number of flash words per page
+ parameter int BusWidth = top_pkg::TL_DW;
+ parameter int MpRegions = 8; // flash controller protection regions
+ parameter int FifoDepth = 16; // rd / prog fifos
+ parameter int InfoTypesWidth = prim_util_pkg::vbits(InfoTypes);
+
+ // flash phy parameters
+ parameter int DataByteWidth = prim_util_pkg::vbits(DataWidth / 8);
+ parameter int BankW = prim_util_pkg::vbits(NumBanks);
+ parameter int InfoPageW = prim_util_pkg::vbits(InfosPerBank);
+ parameter int PageW = prim_util_pkg::vbits(PagesPerBank);
+ parameter int WordW = prim_util_pkg::vbits(WordsPerPage);
+ parameter int AddrW = BankW + PageW + WordW; // all flash range
+ parameter int BankAddrW = PageW + WordW; // 1 bank of flash range
+ parameter int AllPagesW = BankW + PageW;
+
+ // flash ctrl / bus parameters
+ // flash / bus width may be different from actual flash word width
+ parameter int BusBytes = BusWidth / 8;
+ parameter int BusByteWidth = prim_util_pkg::vbits(BusBytes);
+ parameter int WidthMultiple = DataWidth / BusWidth;
+ // Number of bus words that can be programmed at once
+ parameter int BusPgmRes = BusPgmResBytes / BusBytes;
+ parameter int BusPgmResWidth = prim_util_pkg::vbits(BusPgmRes);
+ parameter int BusWordsPerPage = WordsPerPage * WidthMultiple;
+ parameter int BusWordW = prim_util_pkg::vbits(BusWordsPerPage);
+ parameter int BusAddrW = BankW + PageW + BusWordW;
+ parameter int BusAddrByteW = BusAddrW + BusByteWidth;
+ parameter int BusBankAddrW = PageW + BusWordW;
+ parameter int PhyAddrStart = BusWordW - WordW;
+
+
+ // fifo parameters
+ parameter int FifoDepthW = prim_util_pkg::vbits(FifoDepth+1);
+
+ // The end address in bus words for each kind of partition in each bank
+ parameter logic [PageW-1:0] DataPartitionEndAddr = PageW'(PagesPerBank - 1);
+ //parameter logic [PageW-1:0] InfoPartitionEndAddr [InfoTypes] = '{
+ // 9,
+ // 0,
+ // 1
+ //};
+ parameter logic [PageW-1:0] InfoPartitionEndAddr [InfoTypes] = '{
+ PageW'(InfoTypeSize[0] - 1),
+ PageW'(InfoTypeSize[1] - 1),
+ PageW'(InfoTypeSize[2] - 1)
+ };
+
+ ////////////////////////////
+ // All memory protection, seed related parameters
+ // Those related for seed pages should be template candidates
+ ////////////////////////////
+
+ // parameters for connected components
+ parameter int SeedWidth = 256;
+ parameter int KeyWidth = 128;
+ parameter int EdnWidth = edn_pkg::ENDPOINT_BUS_WIDTH;
+ typedef logic [KeyWidth-1:0] flash_key_t;
+
+ // Default Lfsr configurations
+ // These LFSR parameters have been generated with
+ // $ util/design/gen-lfsr-seed.py --width 32 --seed 1274809145 --prefix ""
+ parameter int LfsrWidth = 32;
+ typedef logic [LfsrWidth-1:0] lfsr_seed_t;
+ typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
+ parameter lfsr_seed_t RndCnstLfsrSeedDefault = 32'ha8cee782;
+ parameter lfsr_perm_t RndCnstLfsrPermDefault = {
+ 160'hd60bc7d86445da9347e0ccdd05b281df95238bb5
+ };
+
+ // These LFSR parameters have been generated with
+ // $ util/design/gen-lfsr-seed.py --width 64 --seed 691876113 --prefix ""
+
+
+ // lcmgr phase enum
+ typedef enum logic [1:0] {
+ PhaseSeed,
+ PhaseRma,
+ PhaseNone,
+ PhaseInvalid
+ } flash_lcmgr_phase_e;
+
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t;
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_region_cfg_shadowed_mreg_t;
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_bank0_info0_page_cfg_shadowed_mreg_t;
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_default_region_shadowed_reg_t;
+
+ typedef flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t sw_bank_cfg_t;
+ typedef flash_ctrl_reg2hw_mp_region_cfg_shadowed_mreg_t sw_region_cfg_t;
+ typedef flash_ctrl_reg2hw_default_region_shadowed_reg_t sw_default_cfg_t;
+ typedef flash_ctrl_reg2hw_bank0_info0_page_cfg_shadowed_mreg_t sw_info_cfg_t;
+
+ // alias for super long reg_pkg typedef
+ typedef struct packed {
+ logic q;
+ } bank_cfg_t;
+
+ // This is identical to the reg structures but do not have err_updates / storage
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } rd_en;
+ struct packed {
+ logic q;
+ } prog_en;
+ struct packed {
+ logic q;
+ } erase_en;
+ struct packed {
+ logic q;
+ } scramble_en;
+ struct packed {
+ logic q;
+ } ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
+ } info_page_cfg_t;
+
+ // This is identical to the reg structures but do not have err_updates / storage
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } rd_en;
+ struct packed {
+ logic q;
+ } prog_en;
+ struct packed {
+ logic q;
+ } erase_en;
+ struct packed {
+ logic q;
+ } scramble_en;
+ struct packed {
+ logic q;
+ } ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
+ struct packed {
+ logic [8:0] q;
+ } base;
+ struct packed {
+ logic [9:0] q;
+ } size;
+ } mp_region_cfg_t;
+
+ // memory protection specific structs
+ typedef struct packed {
+ logic [InfoTypesWidth-1:0] sel;
+ logic [AllPagesW-1:0] addr;
+ } page_addr_t;
+
+ typedef struct packed {
+ page_addr_t page;
+ flash_lcmgr_phase_e phase;
+ info_page_cfg_t cfg;
+ } info_page_attr_t;
+
+ typedef struct packed {
+ flash_lcmgr_phase_e phase;
+ mp_region_cfg_t cfg;
+ } data_region_attr_t;
+
+ // flash life cycle / key manager management constants
+ // One page for creator seeds
+ // One page for owner seeds
+ // One page for isolated flash page
+ parameter int NumSeeds = 2;
+ parameter bit [BankW-1:0] SeedBank = 0;
+ parameter bit [InfoTypesWidth-1:0] SeedInfoSel = 0;
+ parameter bit [0:0] CreatorSeedIdx = 0;
+ parameter bit [0:0] OwnerSeedIdx = 1;
+ parameter bit [PageW-1:0] CreatorInfoPage = 1;
+ parameter bit [PageW-1:0] OwnerInfoPage = 2;
+ parameter bit [PageW-1:0] IsolatedInfoPage = 3;
+
+ // which page of which info type of which bank for seed selection
+ parameter page_addr_t SeedInfoPageSel [NumSeeds] = '{
+ '{
+ sel: SeedInfoSel,
+ addr: {SeedBank, CreatorInfoPage}
+ },
+
+ '{
+ sel: SeedInfoSel,
+ addr: {SeedBank, OwnerInfoPage}
+ }
+ };
+
+ // which page of which info type of which bank for isolated partition
+ parameter page_addr_t IsolatedPageSel = '{
+ sel: SeedInfoSel,
+ addr: {SeedBank, IsolatedInfoPage}
+ };
+
+ // hardware interface memory protection rules
+ parameter int HwInfoRules = 5;
+ parameter int HwDataRules = 1;
+
+ parameter info_page_cfg_t CfgAllowRead = '{
+ en: 1'b1,
+ rd_en: 1'b1,
+ prog_en: 1'b0,
+ erase_en: 1'b0,
+ scramble_en: 1'b0,
+ ecc_en: 1'b0, // TBD, update to 1 once tb supports ECC
+ he_en: 1'b1
+ };
+
+ parameter info_page_cfg_t CfgAllowReadProgErase = '{
+ en: 1'b1,
+ rd_en: 1'b1,
+ prog_en: 1'b1,
+ erase_en: 1'b1,
+ scramble_en: 1'b1,
+ ecc_en: 1'b1,
+ he_en: 1'b1 // HW assumes high endurance
+ };
+
+ parameter info_page_attr_t HwInfoPageAttr[HwInfoRules] = '{
+ '{
+ page: SeedInfoPageSel[CreatorSeedIdx],
+ phase: PhaseSeed,
+ cfg: CfgAllowRead
+ },
+
+ '{
+ page: SeedInfoPageSel[OwnerSeedIdx],
+ phase: PhaseSeed,
+ cfg: CfgAllowRead
+ },
+
+ '{
+ page: SeedInfoPageSel[CreatorSeedIdx],
+ phase: PhaseRma,
+ cfg: CfgAllowReadProgErase
+ },
+
+ '{
+ page: SeedInfoPageSel[OwnerSeedIdx],
+ phase: PhaseRma,
+ cfg: CfgAllowReadProgErase
+ },
+
+ '{
+ page: IsolatedPageSel,
+ phase: PhaseRma,
+ cfg: CfgAllowReadProgErase
+ }
+ };
+
+ parameter data_region_attr_t HwDataAttr[HwDataRules] = '{
+ '{
+ phase: PhaseRma,
+ cfg: '{
+ en: 1'b1,
+ rd_en: 1'b1,
+ prog_en: 1'b1,
+ erase_en: 1'b1,
+ scramble_en: 1'b1,
+ ecc_en: 1'b1,
+ he_en: 1'b1, // HW assumes high endurance
+ base: '0,
+ size: '1
+ }
+ }
+ };
+
+
+ ////////////////////////////
+ // Design time constants
+ ////////////////////////////
+ parameter flash_key_t RndCnstAddrKeyDefault =
+ 128'h5d707f8a2d01d400928fa691c6a6e0a4;
+ parameter flash_key_t RndCnstDataKeyDefault =
+ 128'h39953618f2ca6f674af39f64975ea1f5;
+
+ ////////////////////////////
+ // Flash operation related enums
+ ////////////////////////////
+
+ // Flash Operations Supported
+ typedef enum logic [1:0] {
+ FlashOpRead = 2'h0,
+ FlashOpProgram = 2'h1,
+ FlashOpErase = 2'h2,
+ FlashOpInvalid = 2'h3
+ } flash_op_e;
+
+ // Flash Program Operations Supported
+ typedef enum logic {
+ FlashProgNormal = 0,
+ FlashProgRepair = 1
+ } flash_prog_e;
+ parameter int ProgTypes = 2;
+
+ // Flash Erase Operations Supported
+ typedef enum logic {
+ FlashErasePage = 0,
+ FlashEraseBank = 1
+ } flash_erase_e;
+
+ // Flash function select
+ typedef enum logic [1:0] {
+ NoneSel,
+ SwSel,
+ HwSel
+ } flash_sel_e;
+
+ // Flash tlul to fifo direction
+ typedef enum logic {
+ WriteDir = 1'b0,
+ ReadDir = 1'b1
+ } flash_flfo_dir_e;
+
+ // Flash partition type
+ typedef enum logic {
+ FlashPartData = 1'b0,
+ FlashPartInfo = 1'b1
+ } flash_part_e;
+
+ // Flash controller to memory
+ typedef struct packed {
+ logic req;
+ logic scramble_en;
+ logic ecc_en;
+ logic he_en;
+ logic rd_buf_en;
+ logic rd;
+ logic prog;
+ logic pg_erase;
+ logic bk_erase;
+ logic erase_suspend;
+ flash_part_e part;
+ logic [InfoTypesWidth-1:0] info_sel;
+ logic [BusAddrW-1:0] addr;
+ logic [BusWidth-1:0] prog_data;
+ logic prog_last;
+ flash_prog_e prog_type;
+ mp_region_cfg_t [MpRegions:0] region_cfgs;
+ logic [KeyWidth-1:0] addr_key;
+ logic [KeyWidth-1:0] data_key;
+ logic [KeyWidth-1:0] rand_addr_key;
+ logic [KeyWidth-1:0] rand_data_key;
+ logic alert_trig;
+ logic alert_ack;
+ jtag_pkg::jtag_req_t jtag_req;
+ logic intg_err;
+ prim_mubi_pkg::mubi4_t flash_disable;
+ } flash_req_t;
+
+ // default value of flash_req_t (for dangling ports)
+ parameter flash_req_t FLASH_REQ_DEFAULT = '{
+ req: '0,
+ scramble_en: '0,
+ ecc_en: '0,
+ he_en: '0,
+ rd_buf_en: 1'b0,
+ rd: '0,
+ prog: '0,
+ pg_erase: '0,
+ bk_erase: '0,
+ erase_suspend: '0,
+ part: FlashPartData,
+ info_sel: '0,
+ addr: '0,
+ prog_data: '0,
+ prog_last: '0,
+ prog_type: FlashProgNormal,
+ region_cfgs: '0,
+ addr_key: RndCnstAddrKeyDefault,
+ data_key: RndCnstDataKeyDefault,
+ rand_addr_key: '0,
+ rand_data_key: '0,
+ alert_trig: 1'b0,
+ alert_ack: 1'b0,
+ jtag_req: '0,
+ intg_err: '0,
+ flash_disable: prim_mubi_pkg::MuBi4False
+ };
+
+ // memory to flash controller
+ typedef struct packed {
+ logic [ProgTypes-1:0] prog_type_avail;
+ logic rd_done;
+ logic prog_done;
+ logic erase_done;
+ logic rd_err;
+ logic [BusWidth-1:0] rd_data;
+ logic init_busy;
+ logic flash_err;
+ logic [NumBanks-1:0] ecc_single_err;
+ logic [NumBanks-1:0][BusAddrW-1:0] ecc_addr;
+ jtag_pkg::jtag_rsp_t jtag_rsp;
+ logic intg_err;
+ } flash_rsp_t;
+
+ // default value of flash_rsp_t (for dangling ports)
+ parameter flash_rsp_t FLASH_RSP_DEFAULT = '{
+ prog_type_avail: {ProgTypes{1'b1}},
+ rd_done: 1'b0,
+ prog_done: 1'b0,
+ erase_done: 1'b0,
+ rd_err: '0,
+ rd_data: '0,
+ init_busy: 1'b0,
+ flash_err: 1'b0,
+ ecc_single_err: '0,
+ ecc_addr: '0,
+ jtag_rsp: '0,
+ intg_err: '0
+ };
+
+ // RMA entries
+ typedef struct packed {
+ logic [BankW-1:0] bank;
+ flash_part_e part;
+ logic [InfoTypesWidth-1:0] info_sel;
+ logic [PageW:0] start_page;
+ logic [PageW:0] num_pages;
+ } rma_wipe_entry_t;
+
+ // entries to be wiped
+ parameter int WipeEntries = 5;
+ parameter rma_wipe_entry_t RmaWipeEntries[WipeEntries] = '{
+ '{
+ bank: SeedBank,
+ part: FlashPartInfo,
+ info_sel: SeedInfoSel,
+ start_page: {1'b0, CreatorInfoPage},
+ num_pages: 1
+ },
+
+ '{
+ bank: SeedBank,
+ part: FlashPartInfo,
+ info_sel: SeedInfoSel,
+ start_page: {1'b0, OwnerInfoPage},
+ num_pages: 1
+ },
+
+ '{
+ bank: SeedBank,
+ part: FlashPartInfo,
+ info_sel: SeedInfoSel,
+ start_page: {1'b0, IsolatedInfoPage},
+ num_pages: 1
+ },
+
+ '{
+ bank: 0,
+ part: FlashPartData,
+ info_sel: 0,
+ start_page: 0,
+ num_pages: (PageW + 1)'(PagesPerBank)
+ },
+
+ '{
+ bank: 1,
+ part: FlashPartData,
+ info_sel: 0,
+ start_page: 0,
+ num_pages: (PageW + 1)'(PagesPerBank)
+ }
+ };
+
+
+ // flash_ctrl to keymgr
+ typedef struct packed {
+ logic [NumSeeds-1:0][SeedWidth-1:0] seeds;
+ } keymgr_flash_t;
+
+ parameter keymgr_flash_t KEYMGR_FLASH_DEFAULT = '{
+ seeds: '{
+ 256'h9152e32c9380a4bcc3e0ab263581e6b0e8825186e1e445631646e8bef8c45d47,
+ 256'hfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78
+ }
+ };
+
+ // dft_en jtag selection
+ typedef enum logic [2:0] {
+ FlashLcTckSel,
+ FlashLcTdiSel,
+ FlashLcTmsSel,
+ FlashLcTdoSel,
+ FlashBistSel,
+ FlashLcDftLast
+ } flash_lc_jtag_e;
+
+ // Error bit positioning
+ typedef struct packed {
+ logic oob_err;
+ logic mp_err;
+ logic rd_err;
+ logic prog_win_err;
+ logic prog_type_err;
+ logic phy_err;
+ } flash_ctrl_err_t;
+
+ // interrupt bit positioning
+ typedef enum logic[2:0] {
+ ProgEmpty,
+ ProgLvl,
+ RdFull,
+ RdLvl,
+ OpDone,
+ CorrErr,
+ LastIntrIdx
+ } flash_ctrl_intr_e;
+
+ // find the max number pages among info types
+ function automatic integer max_info_pages(int infos[InfoTypes]);
+ int current_max = 0;
+ for (int i = 0; i < InfoTypes; i++) begin
+ if (infos[i] > current_max) begin
+ current_max = infos[i];
+ end
+ end
+ return current_max;
+ endfunction // max_info_banks
+
+ // RMA control FSM encoding
+ // Encoding generated with:
+ // $ ./util/design/sparse-fsm-encode.py -d 5 -m 7 -n 10 // -s 3319803877 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: |||||||||||||||||||| (47.62%)
+ // 6: |||||||||||||||| (38.10%)
+ // 7: |||| (9.52%)
+ // 8: || (4.76%)
+ // 9: --
+ // 10: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 8
+ // Minimum Hamming weight: 3
+ // Maximum Hamming weight: 6
+ //
+ localparam int RmaStateWidth = 10;
+ typedef enum logic [RmaStateWidth-1:0] {
+ StRmaIdle = 10'b1101000011,
+ StRmaPageSel = 10'b0010111001,
+ StRmaErase = 10'b1111010100,
+ StRmaEraseWait = 10'b0111010101,
+ StRmaWordSel = 10'b0001011111,
+ StRmaProgram = 10'b0110001110,
+ StRmaProgramWait = 10'b1000110110,
+ StRmaRdVerify = 10'b1011101010,
+ StRmaInvalid = 10'b1100101101
+ } rma_state_e;
+
+endpackage : flash_ctrl_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/flash_ctrl_reg_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/flash_ctrl_reg_pkg.sv
new file mode 100644
index 00000000..d2ac6ff9
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/flash_ctrl_reg_pkg.sv
@@ -0,0 +1,1094 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package flash_ctrl_reg_pkg;
+
+ // Param list
+ parameter int RegNumBanks = 2;
+ parameter int RegPagesPerBank = 256;
+ parameter int RegBusPgmResBytes = 512;
+ parameter int RegPageWidth = 8;
+ parameter int RegBankWidth = 1;
+ parameter int NumRegions = 8;
+ parameter int NumInfos0 = 10;
+ parameter int NumInfos1 = 1;
+ parameter int NumInfos2 = 2;
+ parameter int WordsPerPage = 256;
+ parameter int BytesPerWord = 8;
+ parameter int BytesPerPage = 2048;
+ parameter int BytesPerBank = 524288;
+ parameter int ExecEn = 2724870391;
+ parameter int NumAlerts = 2;
+
+ // Address widths within the block
+ parameter int CoreAw = 9;
+ parameter int PrimAw = 1;
+ parameter int MemAw = 1;
+
+ ///////////////////////////////////////////////
+ // Typedefs for registers for core interface //
+ ///////////////////////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } prog_empty;
+ struct packed {
+ logic q;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ } rd_full;
+ struct packed {
+ logic q;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ } op_done;
+ struct packed {
+ logic q;
+ } corr_err;
+ } flash_ctrl_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } prog_empty;
+ struct packed {
+ logic q;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ } rd_full;
+ struct packed {
+ logic q;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ } op_done;
+ struct packed {
+ logic q;
+ } corr_err;
+ } flash_ctrl_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } prog_empty;
+ struct packed {
+ logic q;
+ logic qe;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ logic qe;
+ } rd_full;
+ struct packed {
+ logic q;
+ logic qe;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ logic qe;
+ } op_done;
+ struct packed {
+ logic q;
+ logic qe;
+ } corr_err;
+ } flash_ctrl_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } recov_err;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_err;
+ } flash_ctrl_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } flash_ctrl_reg2hw_dis_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } flash_ctrl_reg2hw_exec_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_init_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } start;
+ struct packed {
+ logic [1:0] q;
+ } op;
+ struct packed {
+ logic q;
+ } prog_sel;
+ struct packed {
+ logic q;
+ } erase_sel;
+ struct packed {
+ logic q;
+ } partition_sel;
+ struct packed {
+ logic [1:0] q;
+ } info_sel;
+ struct packed {
+ logic [11:0] q;
+ } num;
+ } flash_ctrl_reg2hw_control_reg_t;
+
+ typedef struct packed {
+ logic [19:0] q;
+ } flash_ctrl_reg2hw_addr_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } normal;
+ struct packed {
+ logic q;
+ } repair;
+ } flash_ctrl_reg2hw_prog_type_en_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_erase_suspend_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ struct packed {
+ logic [8:0] q;
+ logic err_update;
+ logic err_storage;
+ } base;
+ struct packed {
+ logic [9:0] q;
+ logic err_update;
+ logic err_storage;
+ } size;
+ } flash_ctrl_reg2hw_mp_region_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_default_region_shadowed_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank0_info0_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank0_info1_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank0_info2_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank1_info0_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank1_info1_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank1_info2_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } mp_err;
+ struct packed {
+ logic q;
+ } rd_err;
+ struct packed {
+ logic q;
+ } prog_win_err;
+ struct packed {
+ logic q;
+ } prog_type_err;
+ struct packed {
+ logic q;
+ } flash_phy_err;
+ struct packed {
+ logic q;
+ } reg_intg_err;
+ struct packed {
+ logic q;
+ } phy_intg_err;
+ struct packed {
+ logic q;
+ } lcmgr_err;
+ struct packed {
+ logic q;
+ } arb_fsm_err;
+ struct packed {
+ logic q;
+ } storage_err;
+ } flash_ctrl_reg2hw_fault_status_reg_t;
+
+ typedef struct packed {
+ logic [7:0] q;
+ } flash_ctrl_reg2hw_ecc_single_err_cnt_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } alert_ack;
+ struct packed {
+ logic q;
+ } alert_trig;
+ } flash_ctrl_reg2hw_phy_alert_cfg_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } flash_ctrl_reg2hw_scratch_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [4:0] q;
+ } prog;
+ struct packed {
+ logic [4:0] q;
+ } rd;
+ } flash_ctrl_reg2hw_fifo_lvl_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_fifo_rst_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } prog_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_lvl;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_full;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_lvl;
+ struct packed {
+ logic d;
+ logic de;
+ } op_done;
+ struct packed {
+ logic d;
+ logic de;
+ } corr_err;
+ } flash_ctrl_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ logic d;
+ } flash_ctrl_hw2reg_ctrl_regwen_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } start;
+ } flash_ctrl_hw2reg_control_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } flash_ctrl_hw2reg_erase_suspend_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } done;
+ struct packed {
+ logic d;
+ logic de;
+ } err;
+ } flash_ctrl_hw2reg_op_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } rd_full;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_full;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } init_wip;
+ } flash_ctrl_hw2reg_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } mp_err;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_win_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_type_err;
+ struct packed {
+ logic d;
+ logic de;
+ } flash_phy_err;
+ struct packed {
+ logic d;
+ logic de;
+ } update_err;
+ } flash_ctrl_hw2reg_err_code_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } mp_err;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_win_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_type_err;
+ struct packed {
+ logic d;
+ logic de;
+ } flash_phy_err;
+ struct packed {
+ logic d;
+ logic de;
+ } reg_intg_err;
+ struct packed {
+ logic d;
+ logic de;
+ } phy_intg_err;
+ struct packed {
+ logic d;
+ logic de;
+ } lcmgr_err;
+ struct packed {
+ logic d;
+ logic de;
+ } arb_fsm_err;
+ struct packed {
+ logic d;
+ logic de;
+ } storage_err;
+ } flash_ctrl_hw2reg_fault_status_reg_t;
+
+ typedef struct packed {
+ logic [19:0] d;
+ logic de;
+ } flash_ctrl_hw2reg_err_addr_reg_t;
+
+ typedef struct packed {
+ logic [7:0] d;
+ logic de;
+ } flash_ctrl_hw2reg_ecc_single_err_cnt_mreg_t;
+
+ typedef struct packed {
+ logic [19:0] d;
+ logic de;
+ } flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } init_wip;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_normal_avail;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_repair_avail;
+ } flash_ctrl_hw2reg_phy_status_reg_t;
+
+ // Register -> HW type for core interface
+ typedef struct packed {
+ flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [576:571]
+ flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [570:565]
+ flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [564:553]
+ flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [552:549]
+ flash_ctrl_reg2hw_dis_reg_t dis; // [548:545]
+ flash_ctrl_reg2hw_exec_reg_t exec; // [544:513]
+ flash_ctrl_reg2hw_init_reg_t init; // [512:512]
+ flash_ctrl_reg2hw_control_reg_t control; // [511:492]
+ flash_ctrl_reg2hw_addr_reg_t addr; // [491:472]
+ flash_ctrl_reg2hw_prog_type_en_reg_t prog_type_en; // [471:470]
+ flash_ctrl_reg2hw_erase_suspend_reg_t erase_suspend; // [469:469]
+ flash_ctrl_reg2hw_mp_region_cfg_shadowed_mreg_t [7:0] mp_region_cfg_shadowed; // [468:261]
+ flash_ctrl_reg2hw_default_region_shadowed_reg_t default_region_shadowed; // [260:255]
+ flash_ctrl_reg2hw_bank0_info0_page_cfg_shadowed_mreg_t [9:0]
+ bank0_info0_page_cfg_shadowed; // [254:185]
+ flash_ctrl_reg2hw_bank0_info1_page_cfg_shadowed_mreg_t [0:0]
+ bank0_info1_page_cfg_shadowed; // [184:178]
+ flash_ctrl_reg2hw_bank0_info2_page_cfg_shadowed_mreg_t [1:0]
+ bank0_info2_page_cfg_shadowed; // [177:164]
+ flash_ctrl_reg2hw_bank1_info0_page_cfg_shadowed_mreg_t [9:0]
+ bank1_info0_page_cfg_shadowed; // [163:94]
+ flash_ctrl_reg2hw_bank1_info1_page_cfg_shadowed_mreg_t [0:0]
+ bank1_info1_page_cfg_shadowed; // [93:87]
+ flash_ctrl_reg2hw_bank1_info2_page_cfg_shadowed_mreg_t [1:0]
+ bank1_info2_page_cfg_shadowed; // [86:73]
+ flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t [1:0] mp_bank_cfg_shadowed; // [72:71]
+ flash_ctrl_reg2hw_fault_status_reg_t fault_status; // [70:61]
+ flash_ctrl_reg2hw_ecc_single_err_cnt_mreg_t [1:0] ecc_single_err_cnt; // [60:45]
+ flash_ctrl_reg2hw_phy_alert_cfg_reg_t phy_alert_cfg; // [44:43]
+ flash_ctrl_reg2hw_scratch_reg_t scratch; // [42:11]
+ flash_ctrl_reg2hw_fifo_lvl_reg_t fifo_lvl; // [10:1]
+ flash_ctrl_reg2hw_fifo_rst_reg_t fifo_rst; // [0:0]
+ } flash_ctrl_core_reg2hw_t;
+
+ // HW -> register type for core interface
+ typedef struct packed {
+ flash_ctrl_hw2reg_intr_state_reg_t intr_state; // [149:138]
+ flash_ctrl_hw2reg_ctrl_regwen_reg_t ctrl_regwen; // [137:137]
+ flash_ctrl_hw2reg_control_reg_t control; // [136:135]
+ flash_ctrl_hw2reg_erase_suspend_reg_t erase_suspend; // [134:133]
+ flash_ctrl_hw2reg_op_status_reg_t op_status; // [132:129]
+ flash_ctrl_hw2reg_status_reg_t status; // [128:119]
+ flash_ctrl_hw2reg_err_code_reg_t err_code; // [118:107]
+ flash_ctrl_hw2reg_fault_status_reg_t fault_status; // [106:87]
+ flash_ctrl_hw2reg_err_addr_reg_t err_addr; // [86:66]
+ flash_ctrl_hw2reg_ecc_single_err_cnt_mreg_t [1:0] ecc_single_err_cnt; // [65:48]
+ flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t [1:0] ecc_single_err_addr; // [47:6]
+ flash_ctrl_hw2reg_phy_status_reg_t phy_status; // [5:0]
+ } flash_ctrl_core_hw2reg_t;
+
+ // Register offsets for core interface
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INTR_STATE_OFFSET = 9'h0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INTR_ENABLE_OFFSET = 9'h4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INTR_TEST_OFFSET = 9'h8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ALERT_TEST_OFFSET = 9'hc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_DIS_OFFSET = 9'h10;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_EXEC_OFFSET = 9'h14;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INIT_OFFSET = 9'h18;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_CTRL_REGWEN_OFFSET = 9'h1c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_CONTROL_OFFSET = 9'h20;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ADDR_OFFSET = 9'h24;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_TYPE_EN_OFFSET = 9'h28;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ERASE_SUSPEND_OFFSET = 9'h2c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET = 9'h30;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET = 9'h34;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET = 9'h38;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET = 9'h3c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET = 9'h40;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET = 9'h44;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET = 9'h48;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET = 9'h4c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET = 9'h50;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET = 9'h54;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET = 9'h58;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET = 9'h5c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET = 9'h60;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET = 9'h64;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET = 9'h68;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET = 9'h6c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET = 9'h70;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET = 9'h74;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET = 9'h78;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET = 9'h7c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET = 9'h80;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET = 9'h84;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET = 9'h88;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET = 9'h8c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET = 9'h90;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET = 9'h94;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET = 9'h98;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET = 9'h9c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET = 9'ha0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET = 9'ha4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET = 9'ha8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET = 9'hac;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET = 9'hb0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET = 9'hb4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET = 9'hb8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET = 9'hbc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET = 9'hc0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET = 9'hc4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET = 9'hc8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET = 9'hcc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET = 9'hd0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET = 9'hd4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET = 9'hd8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET = 9'hdc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET = 9'he0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET = 9'he4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET = 9'he8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET = 9'hec;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET = 9'hf0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET = 9'hf4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET = 9'hf8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET = 9'hfc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET = 9'h100;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET = 9'h104;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET = 9'h108;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET = 9'h10c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET = 9'h110;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET = 9'h114;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET = 9'h118;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET = 9'h11c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET = 9'h120;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET = 9'h124;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET = 9'h128;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET = 9'h12c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET = 9'h130;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET = 9'h134;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET = 9'h138;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET = 9'h13c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET = 9'h140;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 9'h144;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET = 9'h148;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_OP_STATUS_OFFSET = 9'h14c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_STATUS_OFFSET = 9'h150;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_CODE_OFFSET = 9'h154;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FAULT_STATUS_OFFSET = 9'h158;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_ADDR_OFFSET = 9'h15c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET = 9'h160;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET = 9'h164;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET = 9'h168;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ALERT_CFG_OFFSET = 9'h16c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h170;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h174;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h178;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h17c;
+
+ // Reset values for hwext registers and their fields for core interface
+ parameter logic [5:0] FLASH_CTRL_INTR_TEST_RESVAL = 6'h0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL = 1'h0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL = 1'h0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL = 1'h0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL = 1'h0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL = 1'h0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL = 1'h0;
+ parameter logic [1:0] FLASH_CTRL_ALERT_TEST_RESVAL = 2'h0;
+ parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL = 1'h0;
+ parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL = 1'h0;
+ parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_RESVAL = 1'h1;
+ parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_EN_RESVAL = 1'h1;
+
+ // Window parameters for core interface
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h180;
+ parameter int unsigned FLASH_CTRL_PROG_FIFO_SIZE = 'h4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h184;
+ parameter int unsigned FLASH_CTRL_RD_FIFO_SIZE = 'h4;
+
+ // Register index for core interface
+ typedef enum int {
+ FLASH_CTRL_INTR_STATE,
+ FLASH_CTRL_INTR_ENABLE,
+ FLASH_CTRL_INTR_TEST,
+ FLASH_CTRL_ALERT_TEST,
+ FLASH_CTRL_DIS,
+ FLASH_CTRL_EXEC,
+ FLASH_CTRL_INIT,
+ FLASH_CTRL_CTRL_REGWEN,
+ FLASH_CTRL_CONTROL,
+ FLASH_CTRL_ADDR,
+ FLASH_CTRL_PROG_TYPE_EN,
+ FLASH_CTRL_ERASE_SUSPEND,
+ FLASH_CTRL_REGION_CFG_REGWEN_0,
+ FLASH_CTRL_REGION_CFG_REGWEN_1,
+ FLASH_CTRL_REGION_CFG_REGWEN_2,
+ FLASH_CTRL_REGION_CFG_REGWEN_3,
+ FLASH_CTRL_REGION_CFG_REGWEN_4,
+ FLASH_CTRL_REGION_CFG_REGWEN_5,
+ FLASH_CTRL_REGION_CFG_REGWEN_6,
+ FLASH_CTRL_REGION_CFG_REGWEN_7,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_0,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_1,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_2,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_3,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_4,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_5,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_6,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_7,
+ FLASH_CTRL_DEFAULT_REGION_SHADOWED,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_0,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_1,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_2,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_3,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_4,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_5,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_6,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_7,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_8,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_9,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9,
+ FLASH_CTRL_BANK0_INFO1_REGWEN,
+ FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED,
+ FLASH_CTRL_BANK0_INFO2_REGWEN_0,
+ FLASH_CTRL_BANK0_INFO2_REGWEN_1,
+ FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0,
+ FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_0,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_1,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_2,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_3,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_4,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_5,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_6,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_7,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_8,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_9,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9,
+ FLASH_CTRL_BANK1_INFO1_REGWEN,
+ FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED,
+ FLASH_CTRL_BANK1_INFO2_REGWEN_0,
+ FLASH_CTRL_BANK1_INFO2_REGWEN_1,
+ FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0,
+ FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1,
+ FLASH_CTRL_BANK_CFG_REGWEN,
+ FLASH_CTRL_MP_BANK_CFG_SHADOWED,
+ FLASH_CTRL_OP_STATUS,
+ FLASH_CTRL_STATUS,
+ FLASH_CTRL_ERR_CODE,
+ FLASH_CTRL_FAULT_STATUS,
+ FLASH_CTRL_ERR_ADDR,
+ FLASH_CTRL_ECC_SINGLE_ERR_CNT,
+ FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0,
+ FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1,
+ FLASH_CTRL_PHY_ALERT_CFG,
+ FLASH_CTRL_PHY_STATUS,
+ FLASH_CTRL_SCRATCH,
+ FLASH_CTRL_FIFO_LVL,
+ FLASH_CTRL_FIFO_RST
+ } flash_ctrl_core_id_e;
+
+ // Register width information to check illegal writes for core interface
+ parameter logic [3:0] FLASH_CTRL_CORE_PERMIT [96] = '{
+ 4'b0001, // index[ 0] FLASH_CTRL_INTR_STATE
+ 4'b0001, // index[ 1] FLASH_CTRL_INTR_ENABLE
+ 4'b0001, // index[ 2] FLASH_CTRL_INTR_TEST
+ 4'b0001, // index[ 3] FLASH_CTRL_ALERT_TEST
+ 4'b0001, // index[ 4] FLASH_CTRL_DIS
+ 4'b1111, // index[ 5] FLASH_CTRL_EXEC
+ 4'b0001, // index[ 6] FLASH_CTRL_INIT
+ 4'b0001, // index[ 7] FLASH_CTRL_CTRL_REGWEN
+ 4'b1111, // index[ 8] FLASH_CTRL_CONTROL
+ 4'b0111, // index[ 9] FLASH_CTRL_ADDR
+ 4'b0001, // index[10] FLASH_CTRL_PROG_TYPE_EN
+ 4'b0001, // index[11] FLASH_CTRL_ERASE_SUSPEND
+ 4'b0001, // index[12] FLASH_CTRL_REGION_CFG_REGWEN_0
+ 4'b0001, // index[13] FLASH_CTRL_REGION_CFG_REGWEN_1
+ 4'b0001, // index[14] FLASH_CTRL_REGION_CFG_REGWEN_2
+ 4'b0001, // index[15] FLASH_CTRL_REGION_CFG_REGWEN_3
+ 4'b0001, // index[16] FLASH_CTRL_REGION_CFG_REGWEN_4
+ 4'b0001, // index[17] FLASH_CTRL_REGION_CFG_REGWEN_5
+ 4'b0001, // index[18] FLASH_CTRL_REGION_CFG_REGWEN_6
+ 4'b0001, // index[19] FLASH_CTRL_REGION_CFG_REGWEN_7
+ 4'b1111, // index[20] FLASH_CTRL_MP_REGION_CFG_SHADOWED_0
+ 4'b1111, // index[21] FLASH_CTRL_MP_REGION_CFG_SHADOWED_1
+ 4'b1111, // index[22] FLASH_CTRL_MP_REGION_CFG_SHADOWED_2
+ 4'b1111, // index[23] FLASH_CTRL_MP_REGION_CFG_SHADOWED_3
+ 4'b1111, // index[24] FLASH_CTRL_MP_REGION_CFG_SHADOWED_4
+ 4'b1111, // index[25] FLASH_CTRL_MP_REGION_CFG_SHADOWED_5
+ 4'b1111, // index[26] FLASH_CTRL_MP_REGION_CFG_SHADOWED_6
+ 4'b1111, // index[27] FLASH_CTRL_MP_REGION_CFG_SHADOWED_7
+ 4'b0001, // index[28] FLASH_CTRL_DEFAULT_REGION_SHADOWED
+ 4'b0001, // index[29] FLASH_CTRL_BANK0_INFO0_REGWEN_0
+ 4'b0001, // index[30] FLASH_CTRL_BANK0_INFO0_REGWEN_1
+ 4'b0001, // index[31] FLASH_CTRL_BANK0_INFO0_REGWEN_2
+ 4'b0001, // index[32] FLASH_CTRL_BANK0_INFO0_REGWEN_3
+ 4'b0001, // index[33] FLASH_CTRL_BANK0_INFO0_REGWEN_4
+ 4'b0001, // index[34] FLASH_CTRL_BANK0_INFO0_REGWEN_5
+ 4'b0001, // index[35] FLASH_CTRL_BANK0_INFO0_REGWEN_6
+ 4'b0001, // index[36] FLASH_CTRL_BANK0_INFO0_REGWEN_7
+ 4'b0001, // index[37] FLASH_CTRL_BANK0_INFO0_REGWEN_8
+ 4'b0001, // index[38] FLASH_CTRL_BANK0_INFO0_REGWEN_9
+ 4'b0001, // index[39] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0
+ 4'b0001, // index[40] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1
+ 4'b0001, // index[41] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2
+ 4'b0001, // index[42] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3
+ 4'b0001, // index[43] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4
+ 4'b0001, // index[44] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5
+ 4'b0001, // index[45] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6
+ 4'b0001, // index[46] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7
+ 4'b0001, // index[47] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8
+ 4'b0001, // index[48] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9
+ 4'b0001, // index[49] FLASH_CTRL_BANK0_INFO1_REGWEN
+ 4'b0001, // index[50] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED
+ 4'b0001, // index[51] FLASH_CTRL_BANK0_INFO2_REGWEN_0
+ 4'b0001, // index[52] FLASH_CTRL_BANK0_INFO2_REGWEN_1
+ 4'b0001, // index[53] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0
+ 4'b0001, // index[54] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1
+ 4'b0001, // index[55] FLASH_CTRL_BANK1_INFO0_REGWEN_0
+ 4'b0001, // index[56] FLASH_CTRL_BANK1_INFO0_REGWEN_1
+ 4'b0001, // index[57] FLASH_CTRL_BANK1_INFO0_REGWEN_2
+ 4'b0001, // index[58] FLASH_CTRL_BANK1_INFO0_REGWEN_3
+ 4'b0001, // index[59] FLASH_CTRL_BANK1_INFO0_REGWEN_4
+ 4'b0001, // index[60] FLASH_CTRL_BANK1_INFO0_REGWEN_5
+ 4'b0001, // index[61] FLASH_CTRL_BANK1_INFO0_REGWEN_6
+ 4'b0001, // index[62] FLASH_CTRL_BANK1_INFO0_REGWEN_7
+ 4'b0001, // index[63] FLASH_CTRL_BANK1_INFO0_REGWEN_8
+ 4'b0001, // index[64] FLASH_CTRL_BANK1_INFO0_REGWEN_9
+ 4'b0001, // index[65] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0
+ 4'b0001, // index[66] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1
+ 4'b0001, // index[67] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2
+ 4'b0001, // index[68] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3
+ 4'b0001, // index[69] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4
+ 4'b0001, // index[70] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5
+ 4'b0001, // index[71] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6
+ 4'b0001, // index[72] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7
+ 4'b0001, // index[73] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8
+ 4'b0001, // index[74] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9
+ 4'b0001, // index[75] FLASH_CTRL_BANK1_INFO1_REGWEN
+ 4'b0001, // index[76] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED
+ 4'b0001, // index[77] FLASH_CTRL_BANK1_INFO2_REGWEN_0
+ 4'b0001, // index[78] FLASH_CTRL_BANK1_INFO2_REGWEN_1
+ 4'b0001, // index[79] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0
+ 4'b0001, // index[80] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1
+ 4'b0001, // index[81] FLASH_CTRL_BANK_CFG_REGWEN
+ 4'b0001, // index[82] FLASH_CTRL_MP_BANK_CFG_SHADOWED
+ 4'b0001, // index[83] FLASH_CTRL_OP_STATUS
+ 4'b0001, // index[84] FLASH_CTRL_STATUS
+ 4'b0001, // index[85] FLASH_CTRL_ERR_CODE
+ 4'b0011, // index[86] FLASH_CTRL_FAULT_STATUS
+ 4'b0111, // index[87] FLASH_CTRL_ERR_ADDR
+ 4'b0011, // index[88] FLASH_CTRL_ECC_SINGLE_ERR_CNT
+ 4'b0111, // index[89] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0
+ 4'b0111, // index[90] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1
+ 4'b0001, // index[91] FLASH_CTRL_PHY_ALERT_CFG
+ 4'b0001, // index[92] FLASH_CTRL_PHY_STATUS
+ 4'b1111, // index[93] FLASH_CTRL_SCRATCH
+ 4'b0011, // index[94] FLASH_CTRL_FIFO_LVL
+ 4'b0001 // index[95] FLASH_CTRL_FIFO_RST
+ };
+
+endpackage
+
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/flash_phy_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/flash_phy_pkg.sv
new file mode 100644
index 00000000..5cdec0f7
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/flash_phy_pkg.sv
@@ -0,0 +1,125 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Flash phy module package
+//
+
+package flash_phy_pkg;
+
+ // flash phy parameters
+ parameter int NumBanks = flash_ctrl_pkg::NumBanks;
+ parameter int InfosPerBank = flash_ctrl_pkg::InfosPerBank;
+ parameter int PagesPerBank = flash_ctrl_pkg::PagesPerBank;
+ parameter int WordsPerPage = flash_ctrl_pkg::WordsPerPage;
+ parameter int BankW = flash_ctrl_pkg::BankW;
+ parameter int PageW = flash_ctrl_pkg::PageW;
+ parameter int WordW = flash_ctrl_pkg::WordW;
+ parameter int BankAddrW = flash_ctrl_pkg::BankAddrW;
+ parameter int DataWidth = flash_ctrl_pkg::DataWidth;
+ parameter int EccWidth = 8;
+ parameter int MetaDataWidth = flash_ctrl_pkg::MetaDataWidth;
+ parameter int WidthMultiple = flash_ctrl_pkg::WidthMultiple;
+ parameter int NumBuf = 4; // number of flash read buffers
+ parameter int RspOrderDepth = 2; // this should be DataWidth / BusWidth
+ // will switch to this after bus widening
+ parameter int ScrDataWidth = DataWidth + EccWidth;
+ parameter int FullDataWidth = DataWidth + MetaDataWidth;
+ parameter int InfoTypes = flash_ctrl_pkg::InfoTypes;
+ parameter int InfoTypesWidth = flash_ctrl_pkg::InfoTypesWidth;
+
+ // flash ctrl / bus parameters
+ parameter int BusWidth = flash_ctrl_pkg::BusWidth;
+ parameter int BusBankAddrW = flash_ctrl_pkg::BusBankAddrW;
+ parameter int BusWordW = flash_ctrl_pkg::BusWordW;
+ parameter int ProgTypes = flash_ctrl_pkg::ProgTypes;
+
+ // address bits remain must be 0
+ parameter int AddrBitsRemain = DataWidth % BusWidth;
+
+ // base index
+ // This is the lsb position of the prim flash address when looking at the bus address
+ parameter int LsbAddrBit = $clog2(WidthMultiple);
+ parameter int WordSelW = WidthMultiple == 1 ? 1 : LsbAddrBit;
+
+ // scramble / de-scramble parameters
+ // Number of cycles the gf_mult is given to complete
+ parameter int KeySize = 128;
+ parameter int GfMultCycles = 2;
+ // If this value is greater than 1, constraints must be updated for multicycle paths
+ parameter int CipherCycles = 2;
+
+ // Read buffer metadata
+ typedef enum logic [1:0] {
+ Invalid = 2'h0,
+ Wip = 2'h1,
+ Valid = 2'h2,
+ Undef = 2'h3
+ } rd_buf_attr_e;
+
+ typedef struct packed {
+ logic [DataWidth-1:0] data;
+ logic [BankAddrW-1:0] addr; // all address bits preserved to pick return portion
+ logic part;
+ logic [InfoTypesWidth-1:0] info_sel;
+ rd_buf_attr_e attr;
+ } rd_buf_t;
+
+ typedef struct packed {
+ logic [NumBuf-1:0] buf_sel;
+ logic [WordSelW-1:0] word_sel;
+ } rsp_fifo_entry_t;
+
+ parameter int RspOrderFifoWidth = $bits(rsp_fifo_entry_t);
+
+ typedef struct packed {
+ logic [BankAddrW-1:0] addr;
+ logic descramble;
+ logic ecc;
+ } rd_attr_t;
+
+ // Flash Operations Supported
+ typedef enum logic [2:0] {
+ PhyRead = 3'h0,
+ PhyProg = 3'h1,
+ PhyPgErase = 3'h2,
+ PhyBkErase = 3'h3,
+ PhyOps = 3'h4
+ } flash_phy_op_e;
+
+ // Flash Operations Selected
+ typedef enum logic [1:0] {
+ None = 2'h0,
+ Host = 2'h1,
+ Ctrl = 2'h2
+ } flash_phy_op_sel_e;
+
+ typedef enum logic {
+ ScrambleOp = 1'b0,
+ DeScrambleOp = 1'b1
+ } cipher_ops_e;
+
+ // Connections to prim_flash
+ typedef struct packed {
+ logic rd_req;
+ logic prog_req;
+ logic prog_last;
+ flash_ctrl_pkg::flash_prog_e prog_type;
+ logic pg_erase_req;
+ logic bk_erase_req;
+ logic erase_suspend_req;
+ logic he;
+ logic [BankAddrW-1:0] addr;
+ flash_ctrl_pkg::flash_part_e part;
+ logic [InfoTypesWidth-1:0] info_sel;
+ logic [FullDataWidth-1:0] prog_full_data;
+ } flash_phy_prim_flash_req_t;
+
+ typedef struct packed {
+ logic ack;
+ logic done;
+ logic [FullDataWidth-1:0] rdata;
+ logic erase_suspend_done;
+ } flash_phy_prim_flash_rsp_t;
+
+endpackage // flash_phy_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac.sv
new file mode 100644
index 00000000..6cca40d5
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac.sv
@@ -0,0 +1,565 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// HMAC-SHA256
+
+
+
+module hmac
+ import hmac_pkg::*;
+ import hmac_reg_pkg::*;
+#(
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}
+) (
+ input clk_i,
+ input rst_ni,
+
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+
+ output logic intr_hmac_done_o,
+ output logic intr_fifo_empty_o,
+ output logic intr_hmac_err_o,
+
+ output logic idle_o
+);
+
+
+ /////////////////////////
+ // Signal declarations //
+ /////////////////////////
+ hmac_reg2hw_t reg2hw;
+ hmac_hw2reg_t hw2reg;
+
+ tlul_pkg::tl_h2d_t tl_win_h2d;
+ tlul_pkg::tl_d2h_t tl_win_d2h;
+
+ logic [255:0] secret_key;
+
+ logic wipe_secret;
+ logic [31:0] wipe_v;
+
+ logic fifo_rvalid;
+ logic fifo_rready;
+ sha_fifo_t fifo_rdata;
+
+ logic fifo_wvalid, fifo_wready;
+ sha_fifo_t fifo_wdata;
+ logic fifo_full;
+ logic fifo_empty;
+ logic [4:0] fifo_depth;
+
+ logic msg_fifo_req;
+ logic msg_fifo_gnt;
+ logic msg_fifo_we;
+ logic [31:0] msg_fifo_wdata;
+ logic [31:0] msg_fifo_wmask;
+ logic [31:0] msg_fifo_rdata;
+ logic msg_fifo_rvalid;
+ logic [1:0] msg_fifo_rerror;
+ logic [31:0] msg_fifo_wdata_endian;
+ logic [31:0] msg_fifo_wmask_endian;
+
+ logic packer_ready;
+ logic packer_flush_done;
+
+ logic reg_fifo_wvalid;
+ sha_word_t reg_fifo_wdata;
+ sha_word_t reg_fifo_wmask;
+ logic hmac_fifo_wsel;
+ logic hmac_fifo_wvalid;
+ logic [2:0] hmac_fifo_wdata_sel;
+
+ logic shaf_rvalid;
+ sha_fifo_t shaf_rdata;
+ logic shaf_rready;
+
+ logic sha_en;
+ logic hmac_en;
+ logic endian_swap;
+ logic digest_swap;
+
+ logic reg_hash_start;
+ logic sha_hash_start;
+ logic hash_start; // Valid hash_start_signal
+ logic reg_hash_process;
+ logic sha_hash_process;
+
+ logic reg_hash_done;
+ logic sha_hash_done;
+
+ logic [63:0] message_length;
+ logic [63:0] sha_message_length;
+
+ err_code_e err_code;
+ logic err_valid;
+
+ sha_word_t [7:0] digest;
+
+ hmac_reg2hw_cfg_reg_t cfg_reg;
+ logic cfg_block; // Prevent changing config
+ logic msg_allowed; // MSG_FIFO from software is allowed
+
+ logic hmac_core_idle;
+ logic sha_core_idle;
+
+ ///////////////////////
+ // Connect registers //
+ ///////////////////////
+ assign hw2reg.status.fifo_full.d = fifo_full;
+ assign hw2reg.status.fifo_empty.d = fifo_empty;
+ assign hw2reg.status.fifo_depth.d = fifo_depth;
+
+ // secret key
+ assign wipe_secret = reg2hw.wipe_secret.qe;
+ assign wipe_v = reg2hw.wipe_secret.q;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ secret_key <= '0;
+ end else if (wipe_secret) begin
+ secret_key <= {8{wipe_v}};
+ end else if (!cfg_block) begin
+ // Allow updating secret key only when the engine is in Idle.
+ for (int i = 0; i < 8; i++) begin
+ if (reg2hw.key[7-i].qe) begin
+ secret_key[32*i+:32] <= reg2hw.key[7-i].q;
+ end
+ end
+ end
+ end
+
+ for (genvar i = 0; i < 8; i++) begin : gen_key_digest
+ assign hw2reg.key[7-i].d = '0;
+ // digest
+ assign hw2reg.digest[i].d = conv_endian(digest[i], digest_swap);
+ end
+
+ logic [3:0] unused_cfg_qe;
+
+ assign unused_cfg_qe = {cfg_reg.sha_en.qe, cfg_reg.hmac_en.qe,
+ cfg_reg.endian_swap.qe, cfg_reg.digest_swap.qe};
+
+ assign sha_en = cfg_reg.sha_en.q;
+ assign hmac_en = cfg_reg.hmac_en.q;
+ assign endian_swap = cfg_reg.endian_swap.q;
+ assign digest_swap = cfg_reg.digest_swap.q;
+ assign hw2reg.cfg.hmac_en.d = cfg_reg.hmac_en.q;
+ assign hw2reg.cfg.sha_en.d = cfg_reg.sha_en.q;
+ assign hw2reg.cfg.endian_swap.d = cfg_reg.endian_swap.q;
+ assign hw2reg.cfg.digest_swap.d = cfg_reg.digest_swap.q;
+
+ assign reg_hash_start = reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q;
+ assign reg_hash_process = reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q;
+
+ // Error code register
+ assign hw2reg.err_code.de = err_valid;
+ assign hw2reg.err_code.d = err_code;
+
+ /////////////////////
+ // Control signals //
+ /////////////////////
+ assign hash_start = reg_hash_start & sha_en & ~cfg_block;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ cfg_block <= '0;
+ end else if (hash_start) begin
+ cfg_block <= 1'b1;
+ end else if (reg_hash_done) begin
+ cfg_block <= 1'b0;
+ end
+ end
+ // Hold the configuration during the process
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ cfg_reg <= '{endian_swap: '{q: 1'b1, qe: 1'b0}, default:'0};
+ end else if (!cfg_block && reg2hw.cfg.hmac_en.qe) begin
+ cfg_reg <= reg2hw.cfg ;
+ end
+ end
+
+ // Open up the MSG_FIFO from the TL-UL port when it is ready
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ msg_allowed <= '0;
+ end else if (hash_start) begin
+ msg_allowed <= 1'b1;
+ end else if (packer_flush_done) begin
+ msg_allowed <= 1'b0;
+ end
+ end
+ ////////////////
+ // Interrupts //
+ ////////////////
+ logic fifo_empty_q, fifo_empty_event;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_empty_q <= '1; // By default, it is empty
+ end else if (!hmac_fifo_wsel) begin
+ fifo_empty_q <= fifo_empty;
+ end
+ end
+ assign fifo_empty_event = fifo_empty & ~fifo_empty_q;
+
+ logic [2:0] event_intr;
+ assign event_intr = {err_valid, fifo_empty_event, reg_hash_done};
+
+ // instantiate interrupt hardware primitive
+ prim_intr_hw #(.Width(1)) intr_hw_hmac_done (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (event_intr[0]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.hmac_done.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.hmac_done.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.hmac_done.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.hmac_done.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.hmac_done.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.hmac_done.d),
+ .intr_o (intr_hmac_done_o)
+ );
+ prim_intr_hw #(.Width(1)) intr_hw_fifo_empty (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (event_intr[1]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.fifo_empty.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.fifo_empty.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.fifo_empty.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.fifo_empty.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.fifo_empty.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.fifo_empty.d),
+ .intr_o (intr_fifo_empty_o)
+ );
+ prim_intr_hw #(.Width(1)) intr_hw_hmac_err (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (event_intr[2]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.hmac_err.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.hmac_err.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.hmac_err.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.hmac_err.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.hmac_err.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.hmac_err.d),
+ .intr_o (intr_hmac_err_o)
+ );
+
+ ///////////////
+ // Instances //
+ ///////////////
+
+ assign msg_fifo_rvalid = msg_fifo_req & ~msg_fifo_we;
+ assign msg_fifo_rdata = '1; // Return all F
+ assign msg_fifo_rerror = '1; // Return error for read access
+ assign msg_fifo_gnt = msg_fifo_req & ~hmac_fifo_wsel & packer_ready;
+
+ // FIFO control
+ sha_fifo_t reg_fifo_wentry;
+ assign reg_fifo_wentry.data = conv_endian(reg_fifo_wdata, 1'b1); // always convert
+ assign reg_fifo_wentry.mask = {reg_fifo_wmask[0], reg_fifo_wmask[8],
+ reg_fifo_wmask[16], reg_fifo_wmask[24]};
+ assign fifo_full = ~fifo_wready;
+ assign fifo_empty = ~fifo_rvalid;
+ assign fifo_wvalid = (hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid;
+ assign fifo_wdata = (hmac_fifo_wsel) ? '{data: digest[hmac_fifo_wdata_sel], mask: '1}
+ : reg_fifo_wentry;
+
+ prim_fifo_sync #(
+ .Width ($bits(sha_fifo_t)),
+ .Pass (1'b1),
+ .Depth (MsgFifoDepth)
+ ) u_msg_fifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0),
+
+ .wvalid(fifo_wvalid & sha_en),
+ .wready(fifo_wready),
+ .wdata (fifo_wdata),
+
+ .depth (fifo_depth),
+
+ .rvalid(fifo_rvalid),
+ .rready(fifo_rready),
+ .rdata(fifo_rdata)
+ );
+
+ // TL ADAPTER SRAM
+ tlul_adapter_sram #(
+ .SramAw (9),
+ .SramDw (32),
+ .Outstanding (1),
+ .ByteAccess (1),
+ .ErrOnRead (1)
+ ) u_tlul_adapter (
+ .clk_i,
+ .rst_ni,
+ .tl_i (tl_win_h2d),
+ .tl_o (tl_win_d2h),
+ .req_o (msg_fifo_req ),
+ .gnt_i (msg_fifo_gnt ),
+ .we_o (msg_fifo_we ),
+ .addr_o ( ), // Doesn't care the address other than sub-word
+ .wdata_o (msg_fifo_wdata ),
+ .wmask_o (msg_fifo_wmask ),
+ .rdata_i (msg_fifo_rdata ),
+ .rvalid_i (msg_fifo_rvalid),
+ .rerror_i (msg_fifo_rerror)
+ );
+
+ // TL-UL to MSG_FIFO byte write handling
+ logic msg_write;
+
+ assign msg_write = msg_fifo_req & msg_fifo_we & ~hmac_fifo_wsel & msg_allowed;
+
+ logic [$clog2(32+1)-1:0] wmask_ones;
+
+ always_comb begin
+ wmask_ones = '0;
+ for (int i = 0 ; i < 32 ; i++) begin
+ wmask_ones = wmask_ones + msg_fifo_wmask[i];
+ end
+ end
+
+ // Calculate written message
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ message_length <= '0;
+ end else if (hash_start) begin
+ message_length <= '0;
+ end else if (msg_write && sha_en && packer_ready) begin
+ message_length <= message_length + 64'(wmask_ones);
+ end
+ end
+
+ assign hw2reg.msg_length_upper.de = 1'b1;
+ assign hw2reg.msg_length_upper.d = message_length[63:32];
+ assign hw2reg.msg_length_lower.de = 1'b1;
+ assign hw2reg.msg_length_lower.d = message_length[31:0];
+
+
+ // Convert endian here
+ // prim_packer always packs to the right, but SHA engine assumes incoming
+ // to be big-endian, [31:24] comes first. So, the data is reverted after
+ // prim_packer before the message fifo. here to reverse if not big-endian
+ // before pushing to the packer.
+ assign msg_fifo_wdata_endian = conv_endian(msg_fifo_wdata, ~endian_swap);
+ assign msg_fifo_wmask_endian = conv_endian(msg_fifo_wmask, ~endian_swap);
+
+ prim_packer #(
+ .InW (32),
+ .OutW (32)
+ ) u_packer (
+ .clk_i,
+ .rst_ni,
+
+ .valid_i (msg_write & sha_en),
+ .data_i (msg_fifo_wdata_endian),
+ .mask_i (msg_fifo_wmask_endian),
+ .ready_o (packer_ready),
+
+ .valid_o (reg_fifo_wvalid),
+ .data_o (reg_fifo_wdata),
+ .mask_o (reg_fifo_wmask),
+ .ready_i (fifo_wready & ~hmac_fifo_wsel),
+
+ .flush_i (reg_hash_process),
+ .flush_done_o (packer_flush_done) // ignore at this moment
+ );
+
+
+ hmac_core u_hmac (
+ .clk_i,
+ .rst_ni,
+
+ .secret_key,
+
+ .wipe_secret,
+ .wipe_v,
+
+ .hmac_en,
+
+ .reg_hash_start (hash_start),
+ .reg_hash_process (packer_flush_done), // Trigger after all msg written
+ .hash_done (reg_hash_done),
+ .sha_hash_start,
+ .sha_hash_process,
+ .sha_hash_done,
+
+ .sha_rvalid (shaf_rvalid),
+ .sha_rdata (shaf_rdata),
+ .sha_rready (shaf_rready),
+
+ .fifo_rvalid,
+ .fifo_rdata,
+ .fifo_rready,
+
+ .fifo_wsel (hmac_fifo_wsel),
+ .fifo_wvalid (hmac_fifo_wvalid),
+ .fifo_wdata_sel (hmac_fifo_wdata_sel),
+ .fifo_wready,
+
+ .message_length,
+ .sha_message_length,
+
+ .idle (hmac_core_idle)
+ );
+
+ sha2 u_sha2 (
+ .clk_i,
+ .rst_ni,
+
+ .wipe_secret,
+ .wipe_v,
+
+ .fifo_rvalid (shaf_rvalid),
+ .fifo_rdata (shaf_rdata),
+ .fifo_rready (shaf_rready),
+
+ .sha_en,
+ .hash_start (sha_hash_start),
+ .hash_process (sha_hash_process),
+ .hash_done (sha_hash_done),
+
+ .message_length (sha_message_length),
+
+ .digest,
+
+ .idle (sha_core_idle)
+ );
+
+ // Register top
+ logic [NumAlerts-1:0] alert_test, alerts;
+ hmac_reg_top u_reg (
+ .clk_i,
+ .rst_ni,
+
+ .tl_i,
+ .tl_o,
+
+ .tl_win_o (tl_win_h2d),
+ .tl_win_i (tl_win_d2h),
+
+ .reg2hw,
+ .hw2reg,
+
+ // SEC_CM: BUS.INTEGRITY
+ .intg_err_o (alerts[0]),
+ .devmode_i (1'b1)
+ );
+
+ // Alerts
+ assign alert_test = {
+ reg2hw.alert_test.q &
+ reg2hw.alert_test.qe
+ };
+
+ for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[i]),
+ .IsFatal(i)
+ ) u_prim_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_req_i ( alerts[0] ),
+ .alert_ack_o ( ),
+ .alert_rx_i ( alert_rx_i[i] ),
+ .alert_tx_o ( alert_tx_o[i] )
+ );
+ end
+
+ /////////////////////////
+ // HMAC Error Handling //
+ /////////////////////////
+ logic msg_push_sha_disabled, hash_start_sha_disabled, update_seckey_inprocess;
+ logic hash_start_active; // `reg_hash_start` set when hash already in active
+ logic msg_push_not_allowed; // Message is received when `hash_start` isn't set
+ assign msg_push_sha_disabled = msg_write & ~sha_en;
+ assign hash_start_sha_disabled = reg_hash_start & ~sha_en;
+ assign hash_start_active = reg_hash_start & cfg_block;
+ assign msg_push_not_allowed = msg_fifo_req & ~msg_allowed;
+
+ always_comb begin
+ update_seckey_inprocess = 1'b0;
+ if (cfg_block) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ if (reg2hw.key[i].qe) begin
+ update_seckey_inprocess = update_seckey_inprocess | 1'b1;
+ end
+ end
+ end else begin
+ update_seckey_inprocess = 1'b0;
+ end
+ end
+
+ // Update ERR_CODE register and interrupt only when no pending interrupt.
+ // This ensures only the first event of the series of events can be seen to sw.
+ // It is recommended that the software reads ERR_CODE register when interrupt
+ // is pending to avoid any race conditions.
+ assign err_valid = ~reg2hw.intr_state.hmac_err.q &
+ ( msg_push_sha_disabled | hash_start_sha_disabled
+ | update_seckey_inprocess | hash_start_active
+ | msg_push_not_allowed );
+
+ always_comb begin
+ err_code = NoError;
+ unique case (1'b1)
+ msg_push_sha_disabled: begin
+ err_code = SwPushMsgWhenShaDisabled;
+ end
+ hash_start_sha_disabled: begin
+ err_code = SwHashStartWhenShaDisabled;
+ end
+
+ update_seckey_inprocess: begin
+ err_code = SwUpdateSecretKeyInProcess;
+ end
+
+ hash_start_active: begin
+ err_code = SwHashStartWhenActive;
+ end
+
+ msg_push_not_allowed: begin
+ err_code = SwPushMsgWhenDisallowed;
+ end
+
+ default: begin
+ err_code = NoError;
+ end
+ endcase
+ end
+
+ /////////////////////
+ // Unused Signals //
+ /////////////////////
+ logic unused_wmask;
+ assign unused_wmask = ^reg_fifo_wmask;
+
+ /////////////////////
+ // Idle output //
+ /////////////////////
+ // TBD this should be connected later
+ // Idle: AND condition of:
+ // - packer empty: Currently no way to guarantee the packer is empty.
+ // temporary, the logic uses packer output (reg_fifo_wvalid)
+ // - MSG_FIFO --> fifo_rvalid
+ // - HMAC_CORE --> hmac_core_idle
+ // - SHA2_CORE --> sha_core_idle
+ // - Clean interrupt status
+ logic idle;
+ assign idle = !reg_fifo_wvalid && !fifo_rvalid
+ && hmac_core_idle && sha_core_idle;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ idle_o <= 1'b1;
+ end else begin
+ idle_o <= idle;
+ end
+ end
+
+
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_core.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_core.sv
new file mode 100644
index 00000000..823d318d
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_core.sv
@@ -0,0 +1,315 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// HMAC Core implementation
+
+module hmac_core import hmac_pkg::*; (
+ input clk_i,
+ input rst_ni,
+
+ input [255:0] secret_key, // {word0, word1, ..., word7}
+
+ input wipe_secret,
+ input [31:0] wipe_v,
+
+ input hmac_en,
+
+ input reg_hash_start,
+ input reg_hash_process,
+ output logic hash_done,
+ output logic sha_hash_start,
+ output logic sha_hash_process,
+ input sha_hash_done,
+
+ // fifo
+ output logic sha_rvalid,
+ output sha_fifo_t sha_rdata,
+ input sha_rready,
+
+ input fifo_rvalid,
+ input sha_fifo_t fifo_rdata,
+ output logic fifo_rready,
+
+ // fifo control (select and fifo write data)
+ output logic fifo_wsel, // 0: from reg, 1: from digest
+ output logic fifo_wvalid,
+ output logic [2:0] fifo_wdata_sel, // 0: digest[0] .. 7: digest[7]
+ input fifo_wready,
+
+ input [63:0] message_length,
+ output [63:0] sha_message_length,
+
+ output logic idle
+);
+
+ localparam int unsigned BlockSize = 512;
+ localparam int unsigned BlockSizeBits = $clog2(BlockSize);
+ localparam int unsigned HashWordBits = $clog2($bits(sha_word_t));
+
+ localparam bit [63:0] BlockSize64 = 64'(BlockSize);
+ localparam bit [BlockSizeBits:0] BlockSizeBSB = BlockSize[BlockSizeBits:0];
+
+ logic hash_start; // generated from internal state machine
+ logic hash_process; // generated from internal state machine to trigger hash
+ logic hmac_hash_done;
+
+ logic [BlockSize-1:0] i_pad ;
+ logic [BlockSize-1:0] o_pad ;
+
+ logic [63:0] txcount;
+ logic [BlockSizeBits-HashWordBits-1:0] pad_index;
+ logic clr_txcount, inc_txcount;
+
+ logic hmac_sha_rvalid;
+
+ typedef enum logic [1:0] {
+ SelIPad,
+ SelOPad,
+ SelFifo
+ } sel_rdata_t;
+
+ sel_rdata_t sel_rdata;
+
+ typedef enum logic {
+ SelIPadMsg,
+ SelOPadMsg
+ } sel_msglen_t;
+
+ sel_msglen_t sel_msglen;
+
+ typedef enum logic {
+ Inner, // Update when state goes to StIPad
+ Outer // Update when state enters StOPad
+ } round_t ;
+
+ logic update_round ;
+ round_t round_q, round_d;
+
+ typedef enum logic [2:0] {
+ StIdle,
+ StIPad,
+ StMsg, // Actual Msg, and Digest both
+ StPushToMsgFifo, // Digest --> Msg Fifo
+ StWaitResp, // Hash done( by checking processed_length? or hash_done)
+ StOPad,
+ StDone // hmac_done
+ } st_e ;
+
+ st_e st_q, st_d;
+
+ logic clr_fifo_wdata_sel;
+ logic txcnt_eq_blksz ;
+
+ logic reg_hash_process_flag;
+
+ assign sha_hash_start = (hmac_en) ? hash_start : reg_hash_start ;
+ assign sha_hash_process = (hmac_en) ? reg_hash_process | hash_process : reg_hash_process ;
+ assign hash_done = (hmac_en) ? hmac_hash_done : sha_hash_done ;
+
+ assign pad_index = txcount[BlockSizeBits-1:HashWordBits];
+
+ assign i_pad = {secret_key, {(BlockSize-256){1'b0}}} ^ {(BlockSize/8){8'h36}};
+ assign o_pad = {secret_key, {(BlockSize-256){1'b0}}} ^ {(BlockSize/8){8'h5c}};
+
+
+ assign fifo_rready = (hmac_en) ? (st_q == StMsg) & sha_rready : sha_rready ;
+ // sha_rvalid is controlled by State Machine below.
+ assign sha_rvalid = (!hmac_en) ? fifo_rvalid : hmac_sha_rvalid ;
+ assign sha_rdata =
+ (!hmac_en) ? fifo_rdata :
+ (sel_rdata == SelIPad) ? '{data: i_pad[(BlockSize-1)-32*pad_index-:32], mask: '1} :
+ (sel_rdata == SelOPad) ? '{data: o_pad[(BlockSize-1)-32*pad_index-:32], mask: '1} :
+ (sel_rdata == SelFifo) ? fifo_rdata :
+ '{default: '0};
+
+ assign sha_message_length = (!hmac_en) ? message_length :
+ (sel_msglen == SelIPadMsg) ? message_length + BlockSize64 :
+ (sel_msglen == SelOPadMsg) ? BlockSize64 + 64'd256 :
+ '0 ;
+
+ assign txcnt_eq_blksz = (txcount[BlockSizeBits:0] == BlockSizeBSB);
+
+ assign inc_txcount = sha_rready && sha_rvalid;
+
+ // txcount
+ // Looks like txcount can be removed entirely here in hmac_core
+ // In the first round (InnerPaddedKey), it can just watch process and hash_done
+ // In the second round, it only needs count 256 bits for hash digest to trigger
+ // hash_process to SHA2
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ txcount <= '0;
+ end else if (clr_txcount) begin
+ txcount <= '0;
+ end else if (inc_txcount) begin
+ txcount[63:5] <= txcount[63:5] + 1'b1;
+ end
+ end
+
+ // reg_hash_process trigger logic
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ reg_hash_process_flag <= 1'b0;
+ end else if (reg_hash_process) begin
+ reg_hash_process_flag <= 1'b1;
+ end else if (hmac_hash_done || reg_hash_start) begin
+ reg_hash_process_flag <= 1'b0;
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ round_q <= Inner;
+ end else if (update_round) begin
+ round_q <= round_d;
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_wdata_sel <= 3'h0;
+ end else if (clr_fifo_wdata_sel) begin
+ fifo_wdata_sel <= 3'h0;
+ end else if (fifo_wsel && fifo_wvalid) begin
+ fifo_wdata_sel <= fifo_wdata_sel + 1'b1;
+ end
+ end
+
+ assign sel_msglen = (round_q == Inner) ? SelIPadMsg : SelOPadMsg ;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : state_ff
+ if (!rst_ni) st_q <= StIdle;
+ else st_q <= st_d;
+ end
+
+ always_comb begin : next_state
+ hmac_hash_done = 1'b0;
+ hmac_sha_rvalid = 1'b0;
+
+ clr_txcount = 1'b0;
+
+ update_round = 1'b0;
+ round_d = Inner;
+
+ fifo_wsel = 1'b0; // from register
+ fifo_wvalid = 1'b0;
+
+ clr_fifo_wdata_sel = 1'b1;
+
+ sel_rdata = SelFifo;
+
+ hash_start = 1'b0;
+ hash_process = 1'b0;
+
+ unique case (st_q)
+ StIdle: begin
+ if (hmac_en && reg_hash_start) begin
+ st_d = StIPad;
+
+ clr_txcount = 1'b1;
+ update_round = 1'b1;
+ round_d = Inner;
+ hash_start = 1'b1;
+ end else begin
+ st_d = StIdle;
+ end
+ end
+
+ StIPad: begin
+ sel_rdata = SelIPad;
+
+ if (txcnt_eq_blksz) begin
+ st_d = StMsg;
+
+ hmac_sha_rvalid = 1'b0; // block new read request
+ end else begin
+ st_d = StIPad;
+
+ hmac_sha_rvalid = 1'b1;
+ end
+ end
+
+ StMsg: begin
+ sel_rdata = SelFifo;
+ fifo_wsel = (round_q == Outer);
+
+ if ( (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
+ && (txcount >= sha_message_length)) begin
+ st_d = StWaitResp;
+
+ hmac_sha_rvalid = 1'b0; // block
+ hash_process = (round_q == Outer);
+ end else begin
+ st_d = StMsg;
+
+ hmac_sha_rvalid = fifo_rvalid;
+ end
+ end
+
+ StWaitResp: begin
+ hmac_sha_rvalid = 1'b0;
+
+ if (sha_hash_done) begin
+ if (round_q == Outer) begin
+ st_d = StDone;
+ end else begin // round_q == Inner
+ st_d = StPushToMsgFifo;
+ end
+ end else begin
+ st_d = StWaitResp;
+ end
+ end
+
+ StPushToMsgFifo: begin
+ hmac_sha_rvalid = 1'b0;
+ fifo_wsel = 1'b1;
+ fifo_wvalid = 1'b1;
+ clr_fifo_wdata_sel = 1'b0;
+
+ if (fifo_wready && fifo_wdata_sel == 3'h7) begin
+ st_d = StOPad;
+
+ clr_txcount = 1'b1;
+ update_round = 1'b1;
+ round_d = Outer;
+ hash_start = 1'b1;
+ end else begin
+ st_d = StPushToMsgFifo;
+
+ end
+ end
+
+ StOPad: begin
+ sel_rdata = SelOPad;
+ fifo_wsel = 1'b1; // Remained HMAC select to indicate HMAC is in second stage
+
+ if (txcnt_eq_blksz) begin
+ st_d = StMsg;
+
+ hmac_sha_rvalid = 1'b0; // block new read request
+ end else begin
+ st_d = StOPad;
+
+ hmac_sha_rvalid = 1'b1;
+ end
+ end
+
+ StDone: begin
+ // raise interrupt (hash_done)
+ st_d = StIdle;
+
+ hmac_hash_done = 1'b1;
+ end
+
+ default: begin
+ st_d = StIdle;
+ end
+
+ endcase
+ end
+
+ // Idle: Idle in HMAC_CORE only represents the idle status when hmac mode is
+ // set. If hmac_en is 0, this logic sends the idle signal always.
+ assign idle = (st_q == StIdle) && !reg_hash_start;
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_pkg.sv
new file mode 100644
index 00000000..4a55eaaf
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_pkg.sv
@@ -0,0 +1,98 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package hmac_pkg;
+
+ localparam int MsgFifoDepth = 16;
+
+ localparam int NumRound = 64; // SHA-224, SHA-256
+
+ typedef logic [31:0] sha_word_t;
+ localparam int WordByte = $bits(sha_word_t)/8;
+
+ typedef struct packed {
+ sha_word_t data;
+ logic [WordByte-1:0] mask;
+ } sha_fifo_t;
+
+
+ localparam sha_word_t InitHash [8]= '{
+ 32'h6a09_e667, 32'hbb67_ae85, 32'h3c6e_f372, 32'ha54f_f53a,
+ 32'h510e_527f, 32'h9b05_688c, 32'h1f83_d9ab, 32'h5be0_cd19
+ };
+
+ localparam sha_word_t CubicRootPrime [64] = '{
+ 32'h428a_2f98, 32'h7137_4491, 32'hb5c0_fbcf, 32'he9b5_dba5,
+ 32'h3956_c25b, 32'h59f1_11f1, 32'h923f_82a4, 32'hab1c_5ed5,
+ 32'hd807_aa98, 32'h1283_5b01, 32'h2431_85be, 32'h550c_7dc3,
+ 32'h72be_5d74, 32'h80de_b1fe, 32'h9bdc_06a7, 32'hc19b_f174,
+ 32'he49b_69c1, 32'hefbe_4786, 32'h0fc1_9dc6, 32'h240c_a1cc,
+ 32'h2de9_2c6f, 32'h4a74_84aa, 32'h5cb0_a9dc, 32'h76f9_88da,
+ 32'h983e_5152, 32'ha831_c66d, 32'hb003_27c8, 32'hbf59_7fc7,
+ 32'hc6e0_0bf3, 32'hd5a7_9147, 32'h06ca_6351, 32'h1429_2967,
+ 32'h27b7_0a85, 32'h2e1b_2138, 32'h4d2c_6dfc, 32'h5338_0d13,
+ 32'h650a_7354, 32'h766a_0abb, 32'h81c2_c92e, 32'h9272_2c85,
+ 32'ha2bf_e8a1, 32'ha81a_664b, 32'hc24b_8b70, 32'hc76c_51a3,
+ 32'hd192_e819, 32'hd699_0624, 32'hf40e_3585, 32'h106a_a070,
+ 32'h19a4_c116, 32'h1e37_6c08, 32'h2748_774c, 32'h34b0_bcb5,
+ 32'h391c_0cb3, 32'h4ed8_aa4a, 32'h5b9c_ca4f, 32'h682e_6ff3,
+ 32'h748f_82ee, 32'h78a5_636f, 32'h84c8_7814, 32'h8cc7_0208,
+ 32'h90be_fffa, 32'ha450_6ceb, 32'hbef9_a3f7, 32'hc671_78f2
+ };
+
+ function automatic sha_word_t conv_endian( input sha_word_t v, input logic swap);
+ sha_word_t conv_data = {<<8{v}};
+ conv_endian = (swap) ? conv_data : v ;
+ endfunction : conv_endian
+
+ function automatic sha_word_t rotr( input sha_word_t v , input int amt );
+ rotr = (v >> amt) | (v << (32-amt));
+ endfunction : rotr
+
+ function automatic sha_word_t shiftr( input sha_word_t v, input int amt );
+ shiftr = (v >> amt);
+ endfunction : shiftr
+
+ function automatic sha_word_t [7:0] compress( input sha_word_t w, input sha_word_t k,
+ input sha_word_t [7:0] h_i);
+ automatic sha_word_t sigma_0, sigma_1, ch, maj, temp1, temp2;
+
+ sigma_1 = rotr(h_i[4], 6) ^ rotr(h_i[4], 11) ^ rotr(h_i[4], 25);
+ ch = (h_i[4] & h_i[5]) ^ (~h_i[4] & h_i[6]);
+ temp1 = (h_i[7] + sigma_1 + ch + k + w);
+ sigma_0 = rotr(h_i[0], 2) ^ rotr(h_i[0], 13) ^ rotr(h_i[0], 22);
+ maj = (h_i[0] & h_i[1]) ^ (h_i[0] & h_i[2]) ^ (h_i[1] & h_i[2]);
+ temp2 = (sigma_0 + maj);
+
+ compress[7] = h_i[6]; // h = g
+ compress[6] = h_i[5]; // g = f
+ compress[5] = h_i[4]; // f = e
+ compress[4] = h_i[3] + temp1; // e = (d + temp1)
+ compress[3] = h_i[2]; // d = c
+ compress[2] = h_i[1]; // c = b
+ compress[1] = h_i[0]; // b = a
+ compress[0] = (temp1 + temp2); // a = (temp1 + temp2)
+ endfunction : compress
+
+ function automatic sha_word_t calc_w(input sha_word_t w_0,
+ input sha_word_t w_1,
+ input sha_word_t w_9,
+ input sha_word_t w_14);
+ automatic sha_word_t sum0, sum1;
+ sum0 = rotr(w_1, 7) ^ rotr(w_1, 18) ^ shiftr(w_1, 3);
+ sum1 = rotr(w_14, 17) ^ rotr(w_14, 19) ^ shiftr(w_14, 10);
+ calc_w = w_0 + sum0 + w_9 + sum1;
+ endfunction : calc_w
+
+ typedef enum logic [31:0] {
+ NoError = 32'h0000_0000,
+ SwPushMsgWhenShaDisabled = 32'h0000_0001,
+ SwHashStartWhenShaDisabled = 32'h0000_0002,
+ SwUpdateSecretKeyInProcess = 32'h0000_0003,
+ SwHashStartWhenActive = 32'h0000_0004,
+ SwPushMsgWhenDisallowed = 32'h0000_0005
+ } err_code_e;
+
+endpackage : hmac_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_reg_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_reg_pkg.sv
new file mode 100644
index 00000000..16af8747
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_reg_pkg.sv
@@ -0,0 +1,320 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package hmac_reg_pkg;
+
+ // Param list
+ parameter int NumWords = 8;
+ parameter int NumAlerts = 1;
+
+ // Address widths within the block
+ parameter int BlockAw = 12;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } hmac_done;
+ struct packed {
+ logic q;
+ } fifo_empty;
+ struct packed {
+ logic q;
+ } hmac_err;
+ } hmac_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } hmac_done;
+ struct packed {
+ logic q;
+ } fifo_empty;
+ struct packed {
+ logic q;
+ } hmac_err;
+ } hmac_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } hmac_done;
+ struct packed {
+ logic q;
+ logic qe;
+ } fifo_empty;
+ struct packed {
+ logic q;
+ logic qe;
+ } hmac_err;
+ } hmac_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } hmac_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } hmac_en;
+ struct packed {
+ logic q;
+ logic qe;
+ } sha_en;
+ struct packed {
+ logic q;
+ logic qe;
+ } endian_swap;
+ struct packed {
+ logic q;
+ logic qe;
+ } digest_swap;
+ } hmac_reg2hw_cfg_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } hash_start;
+ struct packed {
+ logic q;
+ logic qe;
+ } hash_process;
+ } hmac_reg2hw_cmd_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ logic qe;
+ } hmac_reg2hw_wipe_secret_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ logic qe;
+ } hmac_reg2hw_key_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } hmac_done;
+ struct packed {
+ logic d;
+ logic de;
+ } fifo_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } hmac_err;
+ } hmac_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ } hmac_en;
+ struct packed {
+ logic d;
+ } sha_en;
+ struct packed {
+ logic d;
+ } endian_swap;
+ struct packed {
+ logic d;
+ } digest_swap;
+ } hmac_hw2reg_cfg_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ } fifo_empty;
+ struct packed {
+ logic d;
+ } fifo_full;
+ struct packed {
+ logic [4:0] d;
+ } fifo_depth;
+ } hmac_hw2reg_status_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ logic de;
+ } hmac_hw2reg_err_code_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } hmac_hw2reg_key_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } hmac_hw2reg_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ logic de;
+ } hmac_hw2reg_msg_length_lower_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ logic de;
+ } hmac_hw2reg_msg_length_upper_reg_t;
+
+ // Register -> HW type
+ typedef struct packed {
+ hmac_reg2hw_intr_state_reg_t intr_state; // [322:320]
+ hmac_reg2hw_intr_enable_reg_t intr_enable; // [319:317]
+ hmac_reg2hw_intr_test_reg_t intr_test; // [316:311]
+ hmac_reg2hw_alert_test_reg_t alert_test; // [310:309]
+ hmac_reg2hw_cfg_reg_t cfg; // [308:301]
+ hmac_reg2hw_cmd_reg_t cmd; // [300:297]
+ hmac_reg2hw_wipe_secret_reg_t wipe_secret; // [296:264]
+ hmac_reg2hw_key_mreg_t [7:0] key; // [263:0]
+ } hmac_reg2hw_t;
+
+ // HW -> register type
+ typedef struct packed {
+ hmac_hw2reg_intr_state_reg_t intr_state; // [627:622]
+ hmac_hw2reg_cfg_reg_t cfg; // [621:618]
+ hmac_hw2reg_status_reg_t status; // [617:611]
+ hmac_hw2reg_err_code_reg_t err_code; // [610:578]
+ hmac_hw2reg_key_mreg_t [7:0] key; // [577:322]
+ hmac_hw2reg_digest_mreg_t [7:0] digest; // [321:66]
+ hmac_hw2reg_msg_length_lower_reg_t msg_length_lower; // [65:33]
+ hmac_hw2reg_msg_length_upper_reg_t msg_length_upper; // [32:0]
+ } hmac_hw2reg_t;
+
+ // Register offsets
+ parameter logic [BlockAw-1:0] HMAC_INTR_STATE_OFFSET = 12'h0;
+ parameter logic [BlockAw-1:0] HMAC_INTR_ENABLE_OFFSET = 12'h4;
+ parameter logic [BlockAw-1:0] HMAC_INTR_TEST_OFFSET = 12'h8;
+ parameter logic [BlockAw-1:0] HMAC_ALERT_TEST_OFFSET = 12'hc;
+ parameter logic [BlockAw-1:0] HMAC_CFG_OFFSET = 12'h10;
+ parameter logic [BlockAw-1:0] HMAC_CMD_OFFSET = 12'h14;
+ parameter logic [BlockAw-1:0] HMAC_STATUS_OFFSET = 12'h18;
+ parameter logic [BlockAw-1:0] HMAC_ERR_CODE_OFFSET = 12'h1c;
+ parameter logic [BlockAw-1:0] HMAC_WIPE_SECRET_OFFSET = 12'h20;
+ parameter logic [BlockAw-1:0] HMAC_KEY_0_OFFSET = 12'h24;
+ parameter logic [BlockAw-1:0] HMAC_KEY_1_OFFSET = 12'h28;
+ parameter logic [BlockAw-1:0] HMAC_KEY_2_OFFSET = 12'h2c;
+ parameter logic [BlockAw-1:0] HMAC_KEY_3_OFFSET = 12'h30;
+ parameter logic [BlockAw-1:0] HMAC_KEY_4_OFFSET = 12'h34;
+ parameter logic [BlockAw-1:0] HMAC_KEY_5_OFFSET = 12'h38;
+ parameter logic [BlockAw-1:0] HMAC_KEY_6_OFFSET = 12'h3c;
+ parameter logic [BlockAw-1:0] HMAC_KEY_7_OFFSET = 12'h40;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_0_OFFSET = 12'h44;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_1_OFFSET = 12'h48;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_2_OFFSET = 12'h4c;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_3_OFFSET = 12'h50;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_4_OFFSET = 12'h54;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_5_OFFSET = 12'h58;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_6_OFFSET = 12'h5c;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_7_OFFSET = 12'h60;
+ parameter logic [BlockAw-1:0] HMAC_MSG_LENGTH_LOWER_OFFSET = 12'h64;
+ parameter logic [BlockAw-1:0] HMAC_MSG_LENGTH_UPPER_OFFSET = 12'h68;
+
+ // Reset values for hwext registers and their fields
+ parameter logic [2:0] HMAC_INTR_TEST_RESVAL = 3'h0;
+ parameter logic [0:0] HMAC_INTR_TEST_HMAC_DONE_RESVAL = 1'h0;
+ parameter logic [0:0] HMAC_INTR_TEST_FIFO_EMPTY_RESVAL = 1'h0;
+ parameter logic [0:0] HMAC_INTR_TEST_HMAC_ERR_RESVAL = 1'h0;
+ parameter logic [0:0] HMAC_ALERT_TEST_RESVAL = 1'h0;
+ parameter logic [0:0] HMAC_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h0;
+ parameter logic [3:0] HMAC_CFG_RESVAL = 4'h4;
+ parameter logic [0:0] HMAC_CFG_ENDIAN_SWAP_RESVAL = 1'h1;
+ parameter logic [0:0] HMAC_CFG_DIGEST_SWAP_RESVAL = 1'h0;
+ parameter logic [1:0] HMAC_CMD_RESVAL = 2'h0;
+ parameter logic [8:0] HMAC_STATUS_RESVAL = 9'h1;
+ parameter logic [0:0] HMAC_STATUS_FIFO_EMPTY_RESVAL = 1'h1;
+ parameter logic [31:0] HMAC_WIPE_SECRET_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_0_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_1_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_2_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_3_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_4_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_5_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_6_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_7_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_2_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_3_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_4_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_5_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_6_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_7_RESVAL = 32'h0;
+
+ // Window parameters
+ parameter logic [BlockAw-1:0] HMAC_MSG_FIFO_OFFSET = 12'h800;
+ parameter int unsigned HMAC_MSG_FIFO_SIZE = 'h800;
+
+ // Register index
+ typedef enum int {
+ HMAC_INTR_STATE,
+ HMAC_INTR_ENABLE,
+ HMAC_INTR_TEST,
+ HMAC_ALERT_TEST,
+ HMAC_CFG,
+ HMAC_CMD,
+ HMAC_STATUS,
+ HMAC_ERR_CODE,
+ HMAC_WIPE_SECRET,
+ HMAC_KEY_0,
+ HMAC_KEY_1,
+ HMAC_KEY_2,
+ HMAC_KEY_3,
+ HMAC_KEY_4,
+ HMAC_KEY_5,
+ HMAC_KEY_6,
+ HMAC_KEY_7,
+ HMAC_DIGEST_0,
+ HMAC_DIGEST_1,
+ HMAC_DIGEST_2,
+ HMAC_DIGEST_3,
+ HMAC_DIGEST_4,
+ HMAC_DIGEST_5,
+ HMAC_DIGEST_6,
+ HMAC_DIGEST_7,
+ HMAC_MSG_LENGTH_LOWER,
+ HMAC_MSG_LENGTH_UPPER
+ } hmac_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] HMAC_PERMIT [27] = '{
+ 4'b0001, // index[ 0] HMAC_INTR_STATE
+ 4'b0001, // index[ 1] HMAC_INTR_ENABLE
+ 4'b0001, // index[ 2] HMAC_INTR_TEST
+ 4'b0001, // index[ 3] HMAC_ALERT_TEST
+ 4'b0001, // index[ 4] HMAC_CFG
+ 4'b0001, // index[ 5] HMAC_CMD
+ 4'b0011, // index[ 6] HMAC_STATUS
+ 4'b1111, // index[ 7] HMAC_ERR_CODE
+ 4'b1111, // index[ 8] HMAC_WIPE_SECRET
+ 4'b1111, // index[ 9] HMAC_KEY_0
+ 4'b1111, // index[10] HMAC_KEY_1
+ 4'b1111, // index[11] HMAC_KEY_2
+ 4'b1111, // index[12] HMAC_KEY_3
+ 4'b1111, // index[13] HMAC_KEY_4
+ 4'b1111, // index[14] HMAC_KEY_5
+ 4'b1111, // index[15] HMAC_KEY_6
+ 4'b1111, // index[16] HMAC_KEY_7
+ 4'b1111, // index[17] HMAC_DIGEST_0
+ 4'b1111, // index[18] HMAC_DIGEST_1
+ 4'b1111, // index[19] HMAC_DIGEST_2
+ 4'b1111, // index[20] HMAC_DIGEST_3
+ 4'b1111, // index[21] HMAC_DIGEST_4
+ 4'b1111, // index[22] HMAC_DIGEST_5
+ 4'b1111, // index[23] HMAC_DIGEST_6
+ 4'b1111, // index[24] HMAC_DIGEST_7
+ 4'b1111, // index[25] HMAC_MSG_LENGTH_LOWER
+ 4'b1111 // index[26] HMAC_MSG_LENGTH_UPPER
+ };
+
+endpackage
+
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_reg_top.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_reg_top.sv
new file mode 100644
index 00000000..d1c2bfda
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/hmac_reg_top.sv
@@ -0,0 +1,1230 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+
+module hmac_reg_top (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // Output port for window
+ output tlul_pkg::tl_h2d_t tl_win_o,
+ input tlul_pkg::tl_d2h_t tl_win_i,
+
+ // To HW
+ output hmac_reg_pkg::hmac_reg2hw_t reg2hw, // Write
+ input hmac_reg_pkg::hmac_hw2reg_t hw2reg, // Read
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import hmac_reg_pkg::* ;
+
+ localparam int AW = 12;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+ logic reg_busy;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ logic intg_err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_q <= '0;
+ end else if (intg_err) begin
+ intg_err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = intg_err_q | intg_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ tlul_pkg::tl_h2d_t tl_socket_h2d [2];
+ tlul_pkg::tl_d2h_t tl_socket_d2h [2];
+
+ logic [0:0] reg_steer;
+
+ // socket_1n connection
+ assign tl_reg_h2d = tl_socket_h2d[1];
+ assign tl_socket_d2h[1] = tl_reg_d2h;
+
+ assign tl_win_o = tl_socket_h2d[0];
+ assign tl_socket_d2h[0] = tl_win_i;
+
+ // Create Socket_1n
+ tlul_socket_1n #(
+ .N (2),
+ .HReqPass (1'b1),
+ .HRspPass (1'b1),
+ .DReqPass ({2{1'b1}}),
+ .DRspPass ({2{1'b1}}),
+ .HReqDepth (4'h0),
+ .HRspDepth (4'h0),
+ .DReqDepth ({2{4'h0}}),
+ .DRspDepth ({2{4'h0}})
+ ) u_socket (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .tl_h_i (tl_i),
+ .tl_h_o (tl_o_pre),
+ .tl_d_o (tl_socket_h2d),
+ .tl_d_i (tl_socket_d2h),
+ .dev_select_i (reg_steer)
+ );
+
+ // Create steering logic
+ always_comb begin
+ unique case (tl_i.a_address[AW-1:0]) inside
+ [2048:4095]: begin
+ reg_steer = 0;
+ end
+ default: begin
+ // Default set to register
+ reg_steer = 1;
+ end
+ endcase
+
+ // Override this in case of an integrity error
+ if (intg_err) begin
+ reg_steer = 1;
+ end
+ end
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW),
+ .EnableDataIntgGen(0)
+ ) u_reg_if (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ // cdc oversampling signals
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+
+ // Define SW related signals
+ // Format: __{wd|we|qs}
+ // or _{wd|we|qs} if field == 1 or 0
+ logic intr_state_we;
+ logic intr_state_hmac_done_qs;
+ logic intr_state_hmac_done_wd;
+ logic intr_state_fifo_empty_qs;
+ logic intr_state_fifo_empty_wd;
+ logic intr_state_hmac_err_qs;
+ logic intr_state_hmac_err_wd;
+ logic intr_enable_we;
+ logic intr_enable_hmac_done_qs;
+ logic intr_enable_hmac_done_wd;
+ logic intr_enable_fifo_empty_qs;
+ logic intr_enable_fifo_empty_wd;
+ logic intr_enable_hmac_err_qs;
+ logic intr_enable_hmac_err_wd;
+ logic intr_test_we;
+ logic intr_test_hmac_done_wd;
+ logic intr_test_fifo_empty_wd;
+ logic intr_test_hmac_err_wd;
+ logic alert_test_we;
+ logic alert_test_wd;
+ logic cfg_re;
+ logic cfg_we;
+ logic cfg_hmac_en_qs;
+ logic cfg_hmac_en_wd;
+ logic cfg_sha_en_qs;
+ logic cfg_sha_en_wd;
+ logic cfg_endian_swap_qs;
+ logic cfg_endian_swap_wd;
+ logic cfg_digest_swap_qs;
+ logic cfg_digest_swap_wd;
+ logic cmd_we;
+ logic cmd_hash_start_wd;
+ logic cmd_hash_process_wd;
+ logic status_re;
+ logic status_fifo_empty_qs;
+ logic status_fifo_full_qs;
+ logic [4:0] status_fifo_depth_qs;
+ logic [31:0] err_code_qs;
+ logic wipe_secret_we;
+ logic [31:0] wipe_secret_wd;
+ logic key_0_we;
+ logic [31:0] key_0_wd;
+ logic key_1_we;
+ logic [31:0] key_1_wd;
+ logic key_2_we;
+ logic [31:0] key_2_wd;
+ logic key_3_we;
+ logic [31:0] key_3_wd;
+ logic key_4_we;
+ logic [31:0] key_4_wd;
+ logic key_5_we;
+ logic [31:0] key_5_wd;
+ logic key_6_we;
+ logic [31:0] key_6_wd;
+ logic key_7_we;
+ logic [31:0] key_7_wd;
+ logic digest_0_re;
+ logic [31:0] digest_0_qs;
+ logic digest_1_re;
+ logic [31:0] digest_1_qs;
+ logic digest_2_re;
+ logic [31:0] digest_2_qs;
+ logic digest_3_re;
+ logic [31:0] digest_3_qs;
+ logic digest_4_re;
+ logic [31:0] digest_4_qs;
+ logic digest_5_re;
+ logic [31:0] digest_5_qs;
+ logic digest_6_re;
+ logic [31:0] digest_6_qs;
+ logic digest_7_re;
+ logic [31:0] digest_7_qs;
+ logic [31:0] msg_length_lower_qs;
+ logic [31:0] msg_length_upper_qs;
+
+ // Register instances
+ // R[intr_state]: V(False)
+ // F[hmac_done]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_hmac_done (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_hmac_done_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.hmac_done.de),
+ .d (hw2reg.intr_state.hmac_done.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.hmac_done.q),
+
+ // to register interface (read)
+ .qs (intr_state_hmac_done_qs)
+ );
+
+ // F[fifo_empty]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_fifo_empty (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_fifo_empty_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.fifo_empty.de),
+ .d (hw2reg.intr_state.fifo_empty.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.fifo_empty.q),
+
+ // to register interface (read)
+ .qs (intr_state_fifo_empty_qs)
+ );
+
+ // F[hmac_err]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_hmac_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_hmac_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.hmac_err.de),
+ .d (hw2reg.intr_state.hmac_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.hmac_err.q),
+
+ // to register interface (read)
+ .qs (intr_state_hmac_err_qs)
+ );
+
+
+ // R[intr_enable]: V(False)
+ // F[hmac_done]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_hmac_done (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_hmac_done_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.hmac_done.q),
+
+ // to register interface (read)
+ .qs (intr_enable_hmac_done_qs)
+ );
+
+ // F[fifo_empty]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_fifo_empty (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_fifo_empty_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.fifo_empty.q),
+
+ // to register interface (read)
+ .qs (intr_enable_fifo_empty_qs)
+ );
+
+ // F[hmac_err]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_hmac_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_hmac_err_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.hmac_err.q),
+
+ // to register interface (read)
+ .qs (intr_enable_hmac_err_qs)
+ );
+
+
+ // R[intr_test]: V(True)
+ // F[hmac_done]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_hmac_done (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_hmac_done_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.hmac_done.qe),
+ .q (reg2hw.intr_test.hmac_done.q),
+ .qs ()
+ );
+
+ // F[fifo_empty]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_fifo_empty (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_fifo_empty_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.fifo_empty.qe),
+ .q (reg2hw.intr_test.fifo_empty.q),
+ .qs ()
+ );
+
+ // F[hmac_err]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_hmac_err (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_hmac_err_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.hmac_err.qe),
+ .q (reg2hw.intr_test.hmac_err.q),
+ .qs ()
+ );
+
+
+ // R[alert_test]: V(True)
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.alert_test.qe),
+ .q (reg2hw.alert_test.q),
+ .qs ()
+ );
+
+
+ // R[cfg]: V(True)
+ // F[hmac_en]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cfg_hmac_en (
+ .re (cfg_re),
+ .we (cfg_we),
+ .wd (cfg_hmac_en_wd),
+ .d (hw2reg.cfg.hmac_en.d),
+ .qre (),
+ .qe (reg2hw.cfg.hmac_en.qe),
+ .q (reg2hw.cfg.hmac_en.q),
+ .qs (cfg_hmac_en_qs)
+ );
+
+ // F[sha_en]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cfg_sha_en (
+ .re (cfg_re),
+ .we (cfg_we),
+ .wd (cfg_sha_en_wd),
+ .d (hw2reg.cfg.sha_en.d),
+ .qre (),
+ .qe (reg2hw.cfg.sha_en.qe),
+ .q (reg2hw.cfg.sha_en.q),
+ .qs (cfg_sha_en_qs)
+ );
+
+ // F[endian_swap]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cfg_endian_swap (
+ .re (cfg_re),
+ .we (cfg_we),
+ .wd (cfg_endian_swap_wd),
+ .d (hw2reg.cfg.endian_swap.d),
+ .qre (),
+ .qe (reg2hw.cfg.endian_swap.qe),
+ .q (reg2hw.cfg.endian_swap.q),
+ .qs (cfg_endian_swap_qs)
+ );
+
+ // F[digest_swap]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cfg_digest_swap (
+ .re (cfg_re),
+ .we (cfg_we),
+ .wd (cfg_digest_swap_wd),
+ .d (hw2reg.cfg.digest_swap.d),
+ .qre (),
+ .qe (reg2hw.cfg.digest_swap.qe),
+ .q (reg2hw.cfg.digest_swap.q),
+ .qs (cfg_digest_swap_qs)
+ );
+
+
+ // R[cmd]: V(True)
+ // F[hash_start]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cmd_hash_start (
+ .re (1'b0),
+ .we (cmd_we),
+ .wd (cmd_hash_start_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.cmd.hash_start.qe),
+ .q (reg2hw.cmd.hash_start.q),
+ .qs ()
+ );
+
+ // F[hash_process]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cmd_hash_process (
+ .re (1'b0),
+ .we (cmd_we),
+ .wd (cmd_hash_process_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.cmd.hash_process.qe),
+ .q (reg2hw.cmd.hash_process.q),
+ .qs ()
+ );
+
+
+ // R[status]: V(True)
+ // F[fifo_empty]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_fifo_empty (
+ .re (status_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.fifo_empty.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (status_fifo_empty_qs)
+ );
+
+ // F[fifo_full]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_fifo_full (
+ .re (status_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.fifo_full.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (status_fifo_full_qs)
+ );
+
+ // F[fifo_depth]: 8:4
+ prim_subreg_ext #(
+ .DW (5)
+ ) u_status_fifo_depth (
+ .re (status_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.fifo_depth.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (status_fifo_depth_qs)
+ );
+
+
+ // R[err_code]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (32'h0)
+ ) u_err_code (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.err_code.de),
+ .d (hw2reg.err_code.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (err_code_qs)
+ );
+
+
+ // R[wipe_secret]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_wipe_secret (
+ .re (1'b0),
+ .we (wipe_secret_we),
+ .wd (wipe_secret_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.wipe_secret.qe),
+ .q (reg2hw.wipe_secret.q),
+ .qs ()
+ );
+
+
+ // Subregister 0 of Multireg key
+ // R[key_0]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_0 (
+ .re (1'b0),
+ .we (key_0_we),
+ .wd (key_0_wd),
+ .d (hw2reg.key[0].d),
+ .qre (),
+ .qe (reg2hw.key[0].qe),
+ .q (reg2hw.key[0].q),
+ .qs ()
+ );
+
+
+ // Subregister 1 of Multireg key
+ // R[key_1]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_1 (
+ .re (1'b0),
+ .we (key_1_we),
+ .wd (key_1_wd),
+ .d (hw2reg.key[1].d),
+ .qre (),
+ .qe (reg2hw.key[1].qe),
+ .q (reg2hw.key[1].q),
+ .qs ()
+ );
+
+
+ // Subregister 2 of Multireg key
+ // R[key_2]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_2 (
+ .re (1'b0),
+ .we (key_2_we),
+ .wd (key_2_wd),
+ .d (hw2reg.key[2].d),
+ .qre (),
+ .qe (reg2hw.key[2].qe),
+ .q (reg2hw.key[2].q),
+ .qs ()
+ );
+
+
+ // Subregister 3 of Multireg key
+ // R[key_3]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_3 (
+ .re (1'b0),
+ .we (key_3_we),
+ .wd (key_3_wd),
+ .d (hw2reg.key[3].d),
+ .qre (),
+ .qe (reg2hw.key[3].qe),
+ .q (reg2hw.key[3].q),
+ .qs ()
+ );
+
+
+ // Subregister 4 of Multireg key
+ // R[key_4]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_4 (
+ .re (1'b0),
+ .we (key_4_we),
+ .wd (key_4_wd),
+ .d (hw2reg.key[4].d),
+ .qre (),
+ .qe (reg2hw.key[4].qe),
+ .q (reg2hw.key[4].q),
+ .qs ()
+ );
+
+
+ // Subregister 5 of Multireg key
+ // R[key_5]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_5 (
+ .re (1'b0),
+ .we (key_5_we),
+ .wd (key_5_wd),
+ .d (hw2reg.key[5].d),
+ .qre (),
+ .qe (reg2hw.key[5].qe),
+ .q (reg2hw.key[5].q),
+ .qs ()
+ );
+
+
+ // Subregister 6 of Multireg key
+ // R[key_6]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_6 (
+ .re (1'b0),
+ .we (key_6_we),
+ .wd (key_6_wd),
+ .d (hw2reg.key[6].d),
+ .qre (),
+ .qe (reg2hw.key[6].qe),
+ .q (reg2hw.key[6].q),
+ .qs ()
+ );
+
+
+ // Subregister 7 of Multireg key
+ // R[key_7]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_7 (
+ .re (1'b0),
+ .we (key_7_we),
+ .wd (key_7_wd),
+ .d (hw2reg.key[7].d),
+ .qre (),
+ .qe (reg2hw.key[7].qe),
+ .q (reg2hw.key[7].q),
+ .qs ()
+ );
+
+
+ // Subregister 0 of Multireg digest
+ // R[digest_0]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_0 (
+ .re (digest_0_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[0].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg digest
+ // R[digest_1]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_1 (
+ .re (digest_1_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[1].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg digest
+ // R[digest_2]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_2 (
+ .re (digest_2_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[2].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg digest
+ // R[digest_3]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_3 (
+ .re (digest_3_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[3].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg digest
+ // R[digest_4]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_4 (
+ .re (digest_4_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[4].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg digest
+ // R[digest_5]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_5 (
+ .re (digest_5_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[5].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg digest
+ // R[digest_6]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_6 (
+ .re (digest_6_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[6].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg digest
+ // R[digest_7]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_7 (
+ .re (digest_7_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[7].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_7_qs)
+ );
+
+
+ // R[msg_length_lower]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (32'h0)
+ ) u_msg_length_lower (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.msg_length_lower.de),
+ .d (hw2reg.msg_length_lower.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (msg_length_lower_qs)
+ );
+
+
+ // R[msg_length_upper]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (32'h0)
+ ) u_msg_length_upper (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.msg_length_upper.de),
+ .d (hw2reg.msg_length_upper.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (msg_length_upper_qs)
+ );
+
+
+
+ logic [26:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == HMAC_INTR_STATE_OFFSET);
+ addr_hit[ 1] = (reg_addr == HMAC_INTR_ENABLE_OFFSET);
+ addr_hit[ 2] = (reg_addr == HMAC_INTR_TEST_OFFSET);
+ addr_hit[ 3] = (reg_addr == HMAC_ALERT_TEST_OFFSET);
+ addr_hit[ 4] = (reg_addr == HMAC_CFG_OFFSET);
+ addr_hit[ 5] = (reg_addr == HMAC_CMD_OFFSET);
+ addr_hit[ 6] = (reg_addr == HMAC_STATUS_OFFSET);
+ addr_hit[ 7] = (reg_addr == HMAC_ERR_CODE_OFFSET);
+ addr_hit[ 8] = (reg_addr == HMAC_WIPE_SECRET_OFFSET);
+ addr_hit[ 9] = (reg_addr == HMAC_KEY_0_OFFSET);
+ addr_hit[10] = (reg_addr == HMAC_KEY_1_OFFSET);
+ addr_hit[11] = (reg_addr == HMAC_KEY_2_OFFSET);
+ addr_hit[12] = (reg_addr == HMAC_KEY_3_OFFSET);
+ addr_hit[13] = (reg_addr == HMAC_KEY_4_OFFSET);
+ addr_hit[14] = (reg_addr == HMAC_KEY_5_OFFSET);
+ addr_hit[15] = (reg_addr == HMAC_KEY_6_OFFSET);
+ addr_hit[16] = (reg_addr == HMAC_KEY_7_OFFSET);
+ addr_hit[17] = (reg_addr == HMAC_DIGEST_0_OFFSET);
+ addr_hit[18] = (reg_addr == HMAC_DIGEST_1_OFFSET);
+ addr_hit[19] = (reg_addr == HMAC_DIGEST_2_OFFSET);
+ addr_hit[20] = (reg_addr == HMAC_DIGEST_3_OFFSET);
+ addr_hit[21] = (reg_addr == HMAC_DIGEST_4_OFFSET);
+ addr_hit[22] = (reg_addr == HMAC_DIGEST_5_OFFSET);
+ addr_hit[23] = (reg_addr == HMAC_DIGEST_6_OFFSET);
+ addr_hit[24] = (reg_addr == HMAC_DIGEST_7_OFFSET);
+ addr_hit[25] = (reg_addr == HMAC_MSG_LENGTH_LOWER_OFFSET);
+ addr_hit[26] = (reg_addr == HMAC_MSG_LENGTH_UPPER_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = (reg_we &
+ ((addr_hit[ 0] & (|(HMAC_PERMIT[ 0] & ~reg_be))) |
+ (addr_hit[ 1] & (|(HMAC_PERMIT[ 1] & ~reg_be))) |
+ (addr_hit[ 2] & (|(HMAC_PERMIT[ 2] & ~reg_be))) |
+ (addr_hit[ 3] & (|(HMAC_PERMIT[ 3] & ~reg_be))) |
+ (addr_hit[ 4] & (|(HMAC_PERMIT[ 4] & ~reg_be))) |
+ (addr_hit[ 5] & (|(HMAC_PERMIT[ 5] & ~reg_be))) |
+ (addr_hit[ 6] & (|(HMAC_PERMIT[ 6] & ~reg_be))) |
+ (addr_hit[ 7] & (|(HMAC_PERMIT[ 7] & ~reg_be))) |
+ (addr_hit[ 8] & (|(HMAC_PERMIT[ 8] & ~reg_be))) |
+ (addr_hit[ 9] & (|(HMAC_PERMIT[ 9] & ~reg_be))) |
+ (addr_hit[10] & (|(HMAC_PERMIT[10] & ~reg_be))) |
+ (addr_hit[11] & (|(HMAC_PERMIT[11] & ~reg_be))) |
+ (addr_hit[12] & (|(HMAC_PERMIT[12] & ~reg_be))) |
+ (addr_hit[13] & (|(HMAC_PERMIT[13] & ~reg_be))) |
+ (addr_hit[14] & (|(HMAC_PERMIT[14] & ~reg_be))) |
+ (addr_hit[15] & (|(HMAC_PERMIT[15] & ~reg_be))) |
+ (addr_hit[16] & (|(HMAC_PERMIT[16] & ~reg_be))) |
+ (addr_hit[17] & (|(HMAC_PERMIT[17] & ~reg_be))) |
+ (addr_hit[18] & (|(HMAC_PERMIT[18] & ~reg_be))) |
+ (addr_hit[19] & (|(HMAC_PERMIT[19] & ~reg_be))) |
+ (addr_hit[20] & (|(HMAC_PERMIT[20] & ~reg_be))) |
+ (addr_hit[21] & (|(HMAC_PERMIT[21] & ~reg_be))) |
+ (addr_hit[22] & (|(HMAC_PERMIT[22] & ~reg_be))) |
+ (addr_hit[23] & (|(HMAC_PERMIT[23] & ~reg_be))) |
+ (addr_hit[24] & (|(HMAC_PERMIT[24] & ~reg_be))) |
+ (addr_hit[25] & (|(HMAC_PERMIT[25] & ~reg_be))) |
+ (addr_hit[26] & (|(HMAC_PERMIT[26] & ~reg_be)))));
+ end
+ assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
+
+ assign intr_state_hmac_done_wd = reg_wdata[0];
+
+ assign intr_state_fifo_empty_wd = reg_wdata[1];
+
+ assign intr_state_hmac_err_wd = reg_wdata[2];
+ assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
+
+ assign intr_enable_hmac_done_wd = reg_wdata[0];
+
+ assign intr_enable_fifo_empty_wd = reg_wdata[1];
+
+ assign intr_enable_hmac_err_wd = reg_wdata[2];
+ assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
+
+ assign intr_test_hmac_done_wd = reg_wdata[0];
+
+ assign intr_test_fifo_empty_wd = reg_wdata[1];
+
+ assign intr_test_hmac_err_wd = reg_wdata[2];
+ assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
+
+ assign alert_test_wd = reg_wdata[0];
+ assign cfg_re = addr_hit[4] & reg_re & !reg_error;
+ assign cfg_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign cfg_hmac_en_wd = reg_wdata[0];
+
+ assign cfg_sha_en_wd = reg_wdata[1];
+
+ assign cfg_endian_swap_wd = reg_wdata[2];
+
+ assign cfg_digest_swap_wd = reg_wdata[3];
+ assign cmd_we = addr_hit[5] & reg_we & !reg_error;
+
+ assign cmd_hash_start_wd = reg_wdata[0];
+
+ assign cmd_hash_process_wd = reg_wdata[1];
+ assign status_re = addr_hit[6] & reg_re & !reg_error;
+ assign wipe_secret_we = addr_hit[8] & reg_we & !reg_error;
+
+ assign wipe_secret_wd = reg_wdata[31:0];
+ assign key_0_we = addr_hit[9] & reg_we & !reg_error;
+
+ assign key_0_wd = reg_wdata[31:0];
+ assign key_1_we = addr_hit[10] & reg_we & !reg_error;
+
+ assign key_1_wd = reg_wdata[31:0];
+ assign key_2_we = addr_hit[11] & reg_we & !reg_error;
+
+ assign key_2_wd = reg_wdata[31:0];
+ assign key_3_we = addr_hit[12] & reg_we & !reg_error;
+
+ assign key_3_wd = reg_wdata[31:0];
+ assign key_4_we = addr_hit[13] & reg_we & !reg_error;
+
+ assign key_4_wd = reg_wdata[31:0];
+ assign key_5_we = addr_hit[14] & reg_we & !reg_error;
+
+ assign key_5_wd = reg_wdata[31:0];
+ assign key_6_we = addr_hit[15] & reg_we & !reg_error;
+
+ assign key_6_wd = reg_wdata[31:0];
+ assign key_7_we = addr_hit[16] & reg_we & !reg_error;
+
+ assign key_7_wd = reg_wdata[31:0];
+ assign digest_0_re = addr_hit[17] & reg_re & !reg_error;
+ assign digest_1_re = addr_hit[18] & reg_re & !reg_error;
+ assign digest_2_re = addr_hit[19] & reg_re & !reg_error;
+ assign digest_3_re = addr_hit[20] & reg_re & !reg_error;
+ assign digest_4_re = addr_hit[21] & reg_re & !reg_error;
+ assign digest_5_re = addr_hit[22] & reg_re & !reg_error;
+ assign digest_6_re = addr_hit[23] & reg_re & !reg_error;
+ assign digest_7_re = addr_hit[24] & reg_re & !reg_error;
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = intr_state_hmac_done_qs;
+ reg_rdata_next[1] = intr_state_fifo_empty_qs;
+ reg_rdata_next[2] = intr_state_hmac_err_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[0] = intr_enable_hmac_done_qs;
+ reg_rdata_next[1] = intr_enable_fifo_empty_qs;
+ reg_rdata_next[2] = intr_enable_hmac_err_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ reg_rdata_next[2] = '0;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[0] = '0;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[0] = cfg_hmac_en_qs;
+ reg_rdata_next[1] = cfg_sha_en_qs;
+ reg_rdata_next[2] = cfg_endian_swap_qs;
+ reg_rdata_next[3] = cfg_digest_swap_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[0] = status_fifo_empty_qs;
+ reg_rdata_next[1] = status_fifo_full_qs;
+ reg_rdata_next[8:4] = status_fifo_depth_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[31:0] = err_code_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[31:0] = digest_0_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[31:0] = digest_1_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[31:0] = digest_2_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[31:0] = digest_3_qs;
+ end
+
+ addr_hit[21]: begin
+ reg_rdata_next[31:0] = digest_4_qs;
+ end
+
+ addr_hit[22]: begin
+ reg_rdata_next[31:0] = digest_5_qs;
+ end
+
+ addr_hit[23]: begin
+ reg_rdata_next[31:0] = digest_6_qs;
+ end
+
+ addr_hit[24]: begin
+ reg_rdata_next[31:0] = digest_7_qs;
+ end
+
+ addr_hit[25]: begin
+ reg_rdata_next[31:0] = msg_length_lower_qs;
+ end
+
+ addr_hit[26]: begin
+ reg_rdata_next[31:0] = msg_length_upper_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // shadow busy
+ logic shadow_busy;
+ assign shadow_busy = 1'b0;
+
+ // register busy
+ logic reg_busy_sel;
+ assign reg_busy = reg_busy_sel | shadow_busy;
+ always_comb begin
+ reg_busy_sel = '0;
+ unique case (1'b1)
+ default: begin
+ reg_busy_sel = '0;
+ end
+ endcase
+ end
+
+
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/jtag_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/jtag_pkg.sv
new file mode 100644
index 00000000..2a67ee07
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/jtag_pkg.sv
@@ -0,0 +1,24 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package jtag_pkg;
+
+ typedef struct packed {
+ logic tck;
+ logic tms;
+ logic trst_n;
+ logic tdi;
+ } jtag_req_t;
+
+ parameter jtag_req_t JTAG_REQ_DEFAULT = '0;
+
+ typedef struct packed {
+ logic tdo;
+ logic tdo_oe;
+ } jtag_rsp_t;
+
+ parameter jtag_rsp_t JTAG_RSP_DEFAULT = '0;
+
+endpackage : jtag_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/lc_ctrl_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/lc_ctrl_pkg.sv
new file mode 100644
index 00000000..b7c19189
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/lc_ctrl_pkg.sv
@@ -0,0 +1,345 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package lc_ctrl_pkg;
+
+ import prim_util_pkg::vbits;
+
+ // TODO: need to generate these randomly, based on ECC
+ // polynomial used inside the OTP macro.
+ // The A/B values are used for the encoded LC state.
+ parameter logic [15:0] A0 = 16'h0000;
+ parameter logic [15:0] A1 = 16'h0000;
+ parameter logic [15:0] A2 = 16'h0000;
+ parameter logic [15:0] A3 = 16'h0000;
+ parameter logic [15:0] A4 = 16'h0000;
+ parameter logic [15:0] A5 = 16'h0000;
+ parameter logic [15:0] A6 = 16'h0000;
+ parameter logic [15:0] A7 = 16'h0000;
+ parameter logic [15:0] A8 = 16'h0000;
+ parameter logic [15:0] A9 = 16'h0000;
+ parameter logic [15:0] A10 = 16'h0000;
+ parameter logic [15:0] A11 = 16'h0000;
+
+ parameter logic [15:0] B0 = 16'hFFFF;
+ parameter logic [15:0] B1 = 16'hFFFF;
+ parameter logic [15:0] B2 = 16'hFFFF;
+ parameter logic [15:0] B3 = 16'hFFFF;
+ parameter logic [15:0] B4 = 16'hFFFF;
+ parameter logic [15:0] B5 = 16'hFFFF;
+ parameter logic [15:0] B6 = 16'hFFFF;
+ parameter logic [15:0] B7 = 16'hFFFF;
+ parameter logic [15:0] B8 = 16'hFFFF;
+ parameter logic [15:0] B9 = 16'hFFFF;
+ parameter logic [15:0] B10 = 16'hFFFF;
+ parameter logic [15:0] B11 = 16'hFFFF;
+
+ // The C/D values are used for the encoded LC transition counter.
+ parameter logic [15:0] C0 = 16'h0000;
+ parameter logic [15:0] C1 = 16'h0000;
+ parameter logic [15:0] C2 = 16'h0000;
+ parameter logic [15:0] C3 = 16'h0000;
+ parameter logic [15:0] C4 = 16'h0000;
+ parameter logic [15:0] C5 = 16'h0000;
+ parameter logic [15:0] C6 = 16'h0000;
+ parameter logic [15:0] C7 = 16'h0000;
+ parameter logic [15:0] C8 = 16'h0000;
+ parameter logic [15:0] C9 = 16'h0000;
+ parameter logic [15:0] C10 = 16'h0000;
+ parameter logic [15:0] C11 = 16'h0000;
+ parameter logic [15:0] C12 = 16'h0000;
+ parameter logic [15:0] C13 = 16'h0000;
+ parameter logic [15:0] C14 = 16'h0000;
+ parameter logic [15:0] C15 = 16'h0000;
+
+ parameter logic [15:0] D0 = 16'hFFFF;
+ parameter logic [15:0] D1 = 16'hFFFF;
+ parameter logic [15:0] D2 = 16'hFFFF;
+ parameter logic [15:0] D3 = 16'hFFFF;
+ parameter logic [15:0] D4 = 16'hFFFF;
+ parameter logic [15:0] D5 = 16'hFFFF;
+ parameter logic [15:0] D6 = 16'hFFFF;
+ parameter logic [15:0] D7 = 16'hFFFF;
+ parameter logic [15:0] D8 = 16'hFFFF;
+ parameter logic [15:0] D9 = 16'hFFFF;
+ parameter logic [15:0] D10 = 16'hFFFF;
+ parameter logic [15:0] D11 = 16'hFFFF;
+ parameter logic [15:0] D12 = 16'hFFFF;
+ parameter logic [15:0] D13 = 16'hFFFF;
+ parameter logic [15:0] D14 = 16'hFFFF;
+ parameter logic [15:0] D15 = 16'hFFFF;
+
+ // The E/F values are used for the encoded ID state.
+ parameter logic [15:0] E0 = 16'h0000;
+ parameter logic [15:0] F0 = 16'hFFFF;
+
+ /////////////////////////////////
+ // General Typedefs and Params //
+ /////////////////////////////////
+
+ parameter int LcValueWidth = 16;
+ parameter int LcTokenWidth = 128;
+ parameter int NumLcStateValues = 12;
+ parameter int LcStateWidth = NumLcStateValues * LcValueWidth;
+ parameter int NumLcCountValues = 16;
+ parameter int LcCountWidth = NumLcCountValues * LcValueWidth;
+ parameter int NumLcStates = 13;
+ parameter int DecLcStateWidth = vbits(NumLcStates);
+ parameter int DecLcCountWidth = vbits(NumLcCountValues+1);
+ parameter int LcIdStateWidth = LcValueWidth;
+ parameter int DecLcIdStateWidth = 2;
+
+ typedef logic [LcTokenWidth-1:0] lc_token_t;
+
+ // TODO: make this secret and generate randomly, given a specific ECC polynomial.
+ typedef enum logic [LcStateWidth-1:0] {
+ // Halfword idx : 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ LcStRaw = '0,
+ LcStTestUnlocked0 = {A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, B0},
+ LcStTestLocked0 = {A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, B1, B0},
+ LcStTestUnlocked1 = {A11, A10, A9, A8, A7, A6, A5, A4, A3, B2, B1, B0},
+ LcStTestLocked1 = {A11, A10, A9, A8, A7, A6, A5, A4, B3, B2, B1, B0},
+ LcStTestUnlocked2 = {A11, A10, A9, A8, A7, A6, A5, B4, B3, B2, B1, B0},
+ LcStTestLocked2 = {A11, A10, A9, A8, A7, A6, B5, B4, B3, B2, B1, B0},
+ LcStTestUnlocked3 = {A11, A10, A9, A8, A7, B6, B5, B4, B3, B2, B1, B0},
+ LcStDev = {A11, A10, A9, A8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStProd = {A11, A10, A9, B8, A7, B6, B5, B4, B3, B2, B1, B0},
+ LcStProdEnd = {A11, A10, B9, A8, A7, B6, B5, B4, B3, B2, B1, B0},
+ LcStRma = {B11, B10, A9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStScrap = {B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}
+ } lc_state_e;
+
+ // Decoded life cycle state, used to interface with CSRs and TAP.
+ typedef enum logic [DecLcStateWidth-1:0] {
+ DecLcStRaw = 4'h0,
+ DecLcStTestUnlocked0 = 4'h1,
+ DecLcStTestLocked0 = 4'h2,
+ DecLcStTestUnlocked1 = 4'h3,
+ DecLcStTestLocked1 = 4'h4,
+ DecLcStTestUnlocked2 = 4'h5,
+ DecLcStTestLocked2 = 4'h6,
+ DecLcStTestUnlocked3 = 4'h7,
+ DecLcStDev = 4'h8,
+ DecLcStProd = 4'h9,
+ DecLcStProdEnd = 4'hA,
+ DecLcStRma = 4'hB,
+ DecLcStScrap = 4'hC,
+ DecLcStPostTrans = 4'hD,
+ DecLcStEscalate = 4'hE,
+ DecLcStInvalid = 4'hF
+ } dec_lc_state_e;
+
+ typedef enum logic [LcIdStateWidth-1:0] {
+ LcIdBlank = E0,
+ LcIdPersonalized = F0
+ } lc_id_state_e;
+
+ typedef enum logic [DecLcIdStateWidth-1:0] {
+ DecLcIdBlank = 2'd0,
+ DecLcIdPersonalized = 2'd1,
+ DecLcIdInvalid = 2'd2
+ } dec_lc_id_state_e;
+
+ typedef enum logic [LcCountWidth-1:0] {
+ LcCntRaw = '0,
+ LcCnt1 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, D0},
+ LcCnt2 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, D1, D0},
+ LcCnt3 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, D2, D1, D0},
+ LcCnt4 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, D3, D2, D1, D0},
+ LcCnt5 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, D4, D3, D2, D1, D0},
+ LcCnt6 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, D5, D4, D3, D2, D1, D0},
+ LcCnt7 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt8 = {C15, C14, C13, C12, C11, C10, C9, C8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt9 = {C15, C14, C13, C12, C11, C10, C9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt10 = {C15, C14, C13, C12, C11, C10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt11 = {C15, C14, C13, C12, C11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt12 = {C15, C14, C13, C12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt13 = {C15, C14, C13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt14 = {C15, C14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt15 = {C15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt16 = {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}
+ } lc_cnt_e;
+
+ typedef logic [DecLcCountWidth-1:0] dec_lc_cnt_t;
+
+
+ ///////////////////////////////////////
+ // Netlist Constants (Hashed Tokens) //
+ ///////////////////////////////////////
+
+ parameter int NumTokens = 6;
+ parameter int TokenIdxWidth = vbits(NumTokens);
+ typedef enum logic [TokenIdxWidth-1:0] {
+ // This is the index for the hashed all-zero constant.
+ // All unconditional transitions use this token.
+ ZeroTokenIdx = 3'h0,
+ RawUnlockTokenIdx = 3'h1,
+ TestUnlockTokenIdx = 3'h2,
+ TestExitTokenIdx = 3'h3,
+ RmaTokenIdx = 3'h4,
+ // This is the index for an all-zero value (i.e., hashed value = '0).
+ // This is used as an additional blocker for some invalid state transition edges.
+ InvalidTokenIdx = 3'h5
+ } token_idx_e;
+
+ ////////////////////////////////
+ // Typedefs for LC Interfaces //
+ ////////////////////////////////
+
+ parameter int TxWidth = 4;
+ typedef enum logic [TxWidth-1:0] {
+ On = 4'b1010,
+ Off = 4'b0101
+ } lc_tx_e;
+
+ typedef lc_tx_e lc_tx_t;
+
+ parameter lc_tx_t LC_TX_DEFAULT = Off;
+
+ parameter int RmaSeedWidth = 32;
+ typedef logic [RmaSeedWidth-1:0] lc_flash_rma_seed_t;
+
+ parameter int LcKeymgrDivWidth = 64;
+ typedef logic [LcKeymgrDivWidth-1:0] lc_keymgr_div_t;
+
+ ////////////////////
+ // Main FSM State //
+ ////////////////////
+
+ // Encoding generated with:
+ // $ ./sparse-fsm-encode.py -d 5 -m 14 -n 16 \
+ // -s 2934212379 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: |||||| (6.59%)
+ // 6: |||||||||| (10.99%)
+ // 7: |||||||||||||||| (17.58%)
+ // 8: |||||||||||||||||||| (20.88%)
+ // 9: |||||||||||||||| (17.58%)
+ // 10: |||||||||||||| (15.38%)
+ // 11: |||||| (6.59%)
+ // 12: ||| (3.30%)
+ // 13: | (1.10%)
+ // 14: --
+ // 15: --
+ // 16: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 13
+ //
+ localparam int FsmStateWidth = 16;
+ typedef enum logic [FsmStateWidth-1:0] {
+ ResetSt = 16'b1100000001111011,
+ IdleSt = 16'b1111011010111100,
+ ClkMuxSt = 16'b0000011110101101,
+ CntIncrSt = 16'b1100111011001001,
+ CntProgSt = 16'b0011001111000111,
+ TransCheckSt = 16'b0000110001010100,
+ TokenHashSt = 16'b1110100010001111,
+ FlashRmaSt = 16'b0110111010110000,
+ TokenCheck0St = 16'b0010000011000000,
+ TokenCheck1St = 16'b1101010101101111,
+ TransProgSt = 16'b1000000110101011,
+ PostTransSt = 16'b0110110100101100,
+ EscalateSt = 16'b1010100001010001,
+ InvalidSt = 16'b1011110110011011
+ } fsm_state_e;
+
+ ///////////////////////////////////////////
+ // Manufacturing State Transition Matrix //
+ ///////////////////////////////////////////
+
+ // The token index matrix below encodes 1) which transition edges are valid and 2) which token
+ // to use for a given transition edge. Note that unconditional but otherwise valid transitions
+ // are assigned the ZeroTokenIdx, whereas invalid transitions are assigned an InvalidTokenIdx.
+ parameter token_idx_e [NumLcStates-1:0][NumLcStates-1:0] TransTokenIdxMatrix = {
+ // SCRAP
+ {13{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END, RMA, SCRAP
+ // RMA
+ ZeroTokenIdx, // -> SCRAP
+ {12{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END, RMA
+ // PROD_END
+ ZeroTokenIdx, // -> SCRAP
+ {12{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END, RMA
+ // PROD
+ ZeroTokenIdx, // -> SCRAP
+ RmaTokenIdx, // -> RMA
+ {11{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END
+ // DEV
+ ZeroTokenIdx, // -> SCRAP
+ RmaTokenIdx, // -> RMA
+ {11{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END
+ // TEST_UNLOCKED3
+ {2{ZeroTokenIdx}}, // -> SCRAP, RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ {8{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, RAW
+ // TEST_LOCKED2
+ ZeroTokenIdx, // -> SCRAP
+ InvalidTokenIdx, // -> RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED3
+ {7{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-2, RAW
+ // TEST_UNLOCKED2
+ {2{ZeroTokenIdx}}, // -> SCRAP, RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ InvalidTokenIdx, // -> TEST_UNLOCKED3
+ ZeroTokenIdx, // -> TEST_LOCKED2
+ {6{InvalidTokenIdx}}, // -> TEST_LOCKED0-1, TEST_UNLOCKED0-2, RAW
+ // TEST_LOCKED1
+ ZeroTokenIdx, // -> SCRAP
+ InvalidTokenIdx, // -> RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED3
+ InvalidTokenIdx , // -> TEST_LOCKED2
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED2
+ {5{InvalidTokenIdx}}, // -> TEST_LOCKED0-1, TEST_UNLOCKED0-1, RAW
+ // TEST_UNLOCKED1
+ {2{ZeroTokenIdx}}, // -> SCRAP, RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ InvalidTokenIdx, // -> TEST_UNLOCKED3
+ ZeroTokenIdx, // -> TEST_LOCKED2
+ InvalidTokenIdx, // -> TEST_UNLOCKED2
+ ZeroTokenIdx, // -> TEST_LOCKED1
+ {4{InvalidTokenIdx}}, // -> TEST_LOCKED0, TEST_UNLOCKED0-1, RAW
+ // TEST_LOCKED0
+ ZeroTokenIdx, // -> SCRAP
+ InvalidTokenIdx, // -> RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED3
+ InvalidTokenIdx, // -> TEST_LOCKED2
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED2
+ InvalidTokenIdx, // -> TEST_LOCKED1
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED1
+ {3{InvalidTokenIdx}}, // -> TEST_LOCKED0, TEST_UNLOCKED0, RAW
+ // TEST_UNLOCKED0
+ {2{ZeroTokenIdx}}, // -> SCRAP, RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ InvalidTokenIdx, // -> TEST_UNLOCKED3
+ ZeroTokenIdx, // -> TEST_LOCKED2
+ InvalidTokenIdx, // -> TEST_UNLOCKED2
+ ZeroTokenIdx, // -> TEST_LOCKED1
+ InvalidTokenIdx, // -> TEST_UNLOCKED1
+ ZeroTokenIdx, // -> TEST_LOCKED0
+ {2{InvalidTokenIdx}}, // -> TEST_UNLOCKED0, RAW
+ // RAW
+ ZeroTokenIdx, // -> SCRAP
+ {4{InvalidTokenIdx}}, // -> RMA, PROD, PROD_END, DEV
+ RawUnlockTokenIdx, // -> TEST_UNLOCKED3
+ InvalidTokenIdx, // -> TEST_LOCKED2
+ RawUnlockTokenIdx, // -> TEST_UNLOCKED2
+ InvalidTokenIdx, // -> TEST_LOCKED1
+ RawUnlockTokenIdx, // -> TEST_UNLOCKED1
+ InvalidTokenIdx, // -> TEST_LOCKED0
+ RawUnlockTokenIdx, // -> TEST_UNLOCKED0
+ InvalidTokenIdx // -> RAW
+ };
+
+endpackage : lc_ctrl_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/otp_ctrl_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/otp_ctrl_pkg.sv
new file mode 100644
index 00000000..ba03e2ec
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/otp_ctrl_pkg.sv
@@ -0,0 +1,337 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package otp_ctrl_pkg;
+
+ import prim_util_pkg::vbits;
+ import otp_ctrl_reg_pkg::*;
+
+ ////////////////////////
+ // General Parameters //
+ ////////////////////////
+
+ // Width of entropy input
+ parameter int EdnDataWidth = 64;
+
+ parameter int NumPartWidth = vbits(NumPart);
+
+ parameter int SwWindowAddrWidth = vbits(NumSwCfgWindowWords);
+
+ // Redundantly encoded and complementary values are used to for signalling to the partition
+ // controller FSMs and the DAI whether a partition is locked or not. Any other value than
+ // "Unlocked" is interpreted as "Locked" in those FSMs.
+ typedef enum logic [7:0] {
+ Unlocked = 8'h5A,
+ Locked = 8'hA5
+ } access_e;
+
+ // Partition access type
+ typedef struct packed {
+ access_e read_lock;
+ access_e write_lock;
+ } part_access_t;
+
+ parameter int DaiCmdWidth = 3;
+ typedef enum logic [DaiCmdWidth-1:0] {
+ DaiRead = 3'b001,
+ DaiWrite = 3'b010,
+ DaiDigest = 3'b100
+ } dai_cmd_e;
+
+ //////////////////////////////////////
+ // Typedefs for OTP Macro Interface //
+ //////////////////////////////////////
+
+ // OTP-macro specific
+ parameter int OtpWidth = 16;
+ parameter int OtpAddrWidth = OtpByteAddrWidth - $clog2(OtpWidth/8);
+ parameter int OtpDepth = 2**OtpAddrWidth;
+ parameter int OtpSizeWidth = 2; // Allows to transfer up to 4 native OTP words at once.
+ parameter int OtpErrWidth = 3;
+ parameter int OtpPwrSeqWidth = 2;
+ parameter int OtpIfWidth = 2**OtpSizeWidth*OtpWidth;
+ // Number of Byte address bits to cut off in order to get the native OTP word address.
+ parameter int OtpAddrShift = OtpByteAddrWidth - OtpAddrWidth;
+
+ typedef enum logic [OtpErrWidth-1:0] {
+ NoError = 3'h0,
+ MacroError = 3'h1,
+ MacroEccCorrError = 3'h2,
+ MacroEccUncorrError = 3'h3,
+ MacroWriteBlankError = 3'h4,
+ AccessError = 3'h5,
+ CheckFailError = 3'h6,
+ FsmStateError = 3'h7
+ } otp_err_e;
+
+ /////////////////////////////////
+ // Typedefs for OTP Scrambling //
+ /////////////////////////////////
+
+ parameter int ScrmblKeyWidth = 128;
+ parameter int ScrmblBlockWidth = 64;
+
+ parameter int NumPresentRounds = 31;
+ parameter int ScrmblBlockHalfWords = ScrmblBlockWidth / OtpWidth;
+
+ typedef enum logic [2:0] {
+ Decrypt,
+ Encrypt,
+ LoadShadow,
+ Digest,
+ DigestInit,
+ DigestFinalize
+ } otp_scrmbl_cmd_e;
+
+ parameter int NumScrmblKeys = 3;
+ parameter int NumDigestSets = 5;
+ parameter int ConstSelWidth = (NumScrmblKeys > NumDigestSets) ?
+ vbits(NumScrmblKeys) :
+ vbits(NumDigestSets);
+
+ typedef enum logic [ConstSelWidth-1:0] {
+ Secret0Key,
+ Secret1Key,
+ Secret2Key
+ } key_sel_e;
+
+ typedef enum logic [ConstSelWidth-1:0] {
+ CnstyDigest,
+ LcRawDigest,
+ FlashDataKey,
+ FlashAddrKey,
+ SramDataKey
+ } digest_sel_e;
+
+ typedef enum logic [ConstSelWidth-1:0] {
+ StandardMode,
+ ChainedMode
+ } digest_mode_e;
+
+ /////////////////////////////////////
+ // Typedefs for Partition Metadata //
+ /////////////////////////////////////
+
+ typedef enum logic [1:0] {
+ Unbuffered,
+ Buffered,
+ LifeCycle
+ } part_variant_e;
+
+ typedef struct packed {
+ part_variant_e variant;
+ // Offset and size within the OTP array, in Bytes.
+ logic [OtpByteAddrWidth-1:0] offset;
+ logic [OtpByteAddrWidth-1:0] size;
+ // Key index to use for scrambling.
+ key_sel_e key_sel;
+ // Attributes
+ logic secret; // Whether the partition is secret (and hence scrambled)
+ logic hw_digest; // Whether the partition has a hardware digest
+ logic write_lock; // Whether the partition is write lockable (via digest)
+ logic read_lock; // Whether the partition is read lockable (via digest)
+ } part_info_t;
+
+ ///////////////////////////////
+ // Typedefs for LC Interface //
+ ///////////////////////////////
+
+ typedef struct packed {
+ logic valid;
+ logic state;
+ // lc_ctrl_pkg::lc_cnt_e
+ logic count;
+ // These are all hash post-images
+ lc_ctrl_pkg::lc_token_t all_zero_token;
+ lc_ctrl_pkg::lc_token_t raw_unlock_token;
+ lc_ctrl_pkg::lc_token_t test_unlock_token;
+ lc_ctrl_pkg::lc_token_t test_exit_token;
+ lc_ctrl_pkg::lc_token_t rma_token;
+ // lc_ctrl_pkg::lc_id_state_e
+ logic id_state;
+ } otp_lc_data_t;
+
+ // Default for dangling connection
+ parameter otp_lc_data_t OTP_LC_DATA_DEFAULT = '{
+ valid: 1'b1,
+ state : 1'b0,
+ count: 1'b0,
+ all_zero_token:1'b0,
+ raw_unlock_token: 1'b0,
+ test_unlock_token: 1'b0,
+ test_exit_token: 1'b0,
+ rma_token: 1'b0,
+ id_state: 1'b0
+ };
+
+
+ typedef struct packed {
+ logic req;
+ // lc_ctrl_pkg::lc_state_e state;
+ // lc_ctrl_pkg::lc_cnt_e count;
+ } lc_otp_program_req_t;
+
+ typedef struct packed {
+ logic err;
+ logic ack;
+ } lc_otp_program_rsp_t;
+
+ // RAW unlock token hashing request.
+ typedef struct packed {
+ logic req;
+ lc_ctrl_pkg::lc_token_t token_input;
+ } lc_otp_token_req_t;
+
+ typedef struct packed {
+ logic ack;
+ lc_ctrl_pkg::lc_token_t hashed_token;
+ } lc_otp_token_rsp_t;
+
+ ////////////////////////////////
+ // Typedefs for Key Broadcast //
+ ////////////////////////////////
+
+ parameter int FlashKeySeedWidth = 256;
+ parameter int SramKeySeedWidth = 128;
+ parameter int KeyMgrKeyWidth = 256;
+ parameter int FlashKeyWidth = 128;
+ parameter int SramKeyWidth = 128;
+ parameter int SramNonceWidth = 64;
+ parameter int OtbnKeyWidth = 128;
+ parameter int OtbnNonceWidth = 256;
+
+ typedef logic [SramKeyWidth-1:0] sram_key_t;
+ typedef logic [SramNonceWidth-1:0] sram_nonce_t;
+ typedef logic [OtbnKeyWidth-1:0] otbn_key_t;
+ typedef logic [OtbnNonceWidth-1:0] otbn_nonce_t;
+
+ typedef struct packed {
+ logic valid;
+ logic [KeyMgrKeyWidth-1:0] key_share0;
+ logic [KeyMgrKeyWidth-1:0] key_share1;
+ } otp_keymgr_key_t;
+
+ parameter otp_keymgr_key_t OTP_KEYMGR_KEY_DEFAULT = '{
+ valid: 1'b1,
+ key_share0: 256'hefb7ea7ee90093cf4affd9aaa2d6c0ec446cfdf5f2d5a0bfd7e2d93edc63a102,
+ key_share1: 256'h56d24a00181de99e0f690b447a8dde2a1ffb8bc306707107aa6e2410f15cfc37
+ };
+
+ typedef struct packed {
+ logic data_req; // Requests static key for data scrambling.
+ logic addr_req; // Requests static key for address scrambling.
+ } flash_otp_key_req_t;
+
+ typedef struct packed {
+ logic req; // Requests ephemeral scrambling key and nonce.
+ } sram_otp_key_req_t;
+
+ typedef struct packed {
+ logic req; // Requests ephemeral scrambling key and nonce.
+ } otbn_otp_key_req_t;
+
+ typedef struct packed {
+ logic data_ack; // Ack for data key.
+ logic addr_ack; // Ack for address key.
+ logic [FlashKeyWidth-1:0] key; // 128bit static scrambling key.
+ logic seed_valid; // Set to 1 if the key seed has been provisioned and is valid.
+ } flash_otp_key_rsp_t;
+
+ // Default for dangling connection
+ parameter flash_otp_key_rsp_t FLASH_OTP_KEY_RSP_DEFAULT = '{
+ data_ack: 1'b1,
+ addr_ack: 1'b1,
+ key: '0,
+ seed_valid: 1'b1
+ };
+
+ typedef struct packed {
+ logic ack; // Ack for key.
+ sram_key_t key; // 128bit ephemeral scrambling key.
+ sram_nonce_t nonce; // 64bit nonce.
+ logic seed_valid; // Set to 1 if the key seed has been provisioned and is valid.
+ } sram_otp_key_rsp_t;
+
+ typedef struct packed {
+ logic ack; // Ack for key.
+ otbn_key_t key; // 128bit ephemeral scrambling key.
+ otbn_nonce_t nonce; // 256bit nonce.
+ logic seed_valid; // Set to 1 if the key seed has been provisioned and is valid.
+ } otbn_otp_key_rsp_t;
+
+ ////////////////////////////////
+ // Power/Reset Ctrl Interface //
+ ////////////////////////////////
+
+ typedef struct packed {
+ logic init;
+ } pwr_otp_init_req_t;
+
+ typedef struct packed {
+ logic done;
+ } pwr_otp_init_rsp_t;
+
+ typedef struct packed {
+ logic idle;
+ } otp_pwr_state_t;
+
+
+ ///////////////////
+ // AST Interface //
+ ///////////////////
+
+ typedef struct packed {
+ logic [OtpPwrSeqWidth-1:0] pwr_seq;
+ } otp_ast_req_t;
+
+ typedef struct packed {
+ logic [OtpPwrSeqWidth-1:0] pwr_seq_h;
+ } otp_ast_rsp_t;
+
+ ///////////////////////////////////////////
+ // Defaults for random netlist constants //
+ ///////////////////////////////////////////
+
+ // These LFSR parameters have been generated with
+ // $ hw/ip/prim/util/gen-lfsr-seed.py --width 40 --seed 4247488366
+ localparam int LfsrWidth = 40;
+ typedef logic [LfsrWidth-1:0] lfsr_seed_t;
+ typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
+ localparam lfsr_seed_t RndCnstLfsrSeedDefault = 40'h453d28ea98;
+ localparam lfsr_perm_t RndCnstLfsrPermDefault =
+ 240'h4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5;
+
+
+ typedef logic [NumScrmblKeys-1:0][ScrmblKeyWidth-1:0] key_array_t;
+ parameter key_array_t RndCnstKeyDefault = {
+ 128'h047288e1a65c839dae610bbbdf8c4525,
+ 128'h38fe59a71a91a65636573a6513784e3b,
+ 128'h4f48dcc45ace0770e9135bda73e56344
+ };
+
+ // Note: digest set 0 is used for computing the partition digests. Constants at
+ // higher indices are used to compute the scrambling keys.
+ typedef logic [NumDigestSets-1:0][ScrmblKeyWidth-1:0] digest_const_array_t;
+ parameter digest_const_array_t RndCnstDigestConstDefault = {
+ 128'h9d40106e2dc2346ec96d61f0cc5295c7,
+ 128'hafed2aa5c3284c01d71103edab1d8953,
+ 128'h8a14fe0c08f8a3a190dd32c05f208474,
+ 128'h9e6fac4ba15a3bce29d05a3e9e2d0846,
+ 128'h3a0c6051392e00ef24073627319555b8
+ };
+
+ typedef logic [NumDigestSets-1:0][ScrmblBlockWidth-1:0] digest_iv_array_t;
+ parameter digest_iv_array_t RndCnstDigestIVDefault = {
+ 64'ha5af72c1b813aec4,
+ 64'h5d7aacd1db316407,
+ 64'hd0ec83b7fe6ae2ae,
+ 64'hc2993a0ea64e312d,
+ 64'h899aac2ab7d91479
+ };
+
+ parameter lc_ctrl_pkg::lc_token_t RndCnstRawUnlockTokenDefault =
+ 128'hcbbd013ff15eba2f3065461eeb88463e;
+
+endpackage : otp_ctrl_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/otp_ctrl_reg_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/otp_ctrl_reg_pkg.sv
new file mode 100644
index 00000000..49c86563
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/otp_ctrl_reg_pkg.sv
@@ -0,0 +1,571 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package otp_ctrl_reg_pkg;
+
+ // Param list
+ parameter int NumSramKeyReqSlots = 2;
+ parameter int OtpByteAddrWidth = 11;
+ parameter int NumErrorEntries = 10;
+ parameter int NumDaiWords = 2;
+ parameter int NumDigestWords = 2;
+ parameter int NumSwCfgWindowWords = 512;
+ parameter int NumDebugWindowWords = 16;
+ parameter int NumPart = 8;
+ parameter int VendorTestOffset = 0;
+ parameter int VendorTestSize = 64;
+ parameter int ScratchOffset = 0;
+ parameter int ScratchSize = 56;
+ parameter int VendorTestDigestOffset = 56;
+ parameter int VendorTestDigestSize = 8;
+ parameter int CreatorSwCfgOffset = 64;
+ parameter int CreatorSwCfgSize = 800;
+ parameter int CreatorSwCfgAstCfgOffset = 64;
+ parameter int CreatorSwCfgAstCfgSize = 128;
+ parameter int CreatorSwCfgAstInitEnOffset = 192;
+ parameter int CreatorSwCfgAstInitEnSize = 4;
+ parameter int CreatorSwCfgRomExtSkuOffset = 196;
+ parameter int CreatorSwCfgRomExtSkuSize = 4;
+ parameter int CreatorSwCfgUseSwRsaVerifyOffset = 200;
+ parameter int CreatorSwCfgUseSwRsaVerifySize = 4;
+ parameter int CreatorSwCfgKeyIsValidOffset = 204;
+ parameter int CreatorSwCfgKeyIsValidSize = 8;
+ parameter int CreatorSwCfgFlashDataDefaultCfgOffset = 212;
+ parameter int CreatorSwCfgFlashDataDefaultCfgSize = 4;
+ parameter int CreatorSwCfgFlashInfoBootDataCfgOffset = 216;
+ parameter int CreatorSwCfgFlashInfoBootDataCfgSize = 4;
+ parameter int CreatorSwCfgRngEnOffset = 220;
+ parameter int CreatorSwCfgRngEnSize = 4;
+ parameter int CreatorSwCfgDigestOffset = 856;
+ parameter int CreatorSwCfgDigestSize = 8;
+ parameter int OwnerSwCfgOffset = 864;
+ parameter int OwnerSwCfgSize = 800;
+ parameter int RomErrorReportingOffset = 864;
+ parameter int RomErrorReportingSize = 4;
+ parameter int RomBootstrapEnOffset = 868;
+ parameter int RomBootstrapEnSize = 4;
+ parameter int RomFaultResponseOffset = 872;
+ parameter int RomFaultResponseSize = 4;
+ parameter int RomAlertClassEnOffset = 876;
+ parameter int RomAlertClassEnSize = 4;
+ parameter int RomAlertEscalationOffset = 880;
+ parameter int RomAlertEscalationSize = 4;
+ parameter int RomAlertClassificationOffset = 884;
+ parameter int RomAlertClassificationSize = 320;
+ parameter int RomLocalAlertClassificationOffset = 1204;
+ parameter int RomLocalAlertClassificationSize = 64;
+ parameter int RomAlertAccumThreshOffset = 1268;
+ parameter int RomAlertAccumThreshSize = 16;
+ parameter int RomAlertTimeoutCyclesOffset = 1284;
+ parameter int RomAlertTimeoutCyclesSize = 16;
+ parameter int RomAlertPhaseCyclesOffset = 1300;
+ parameter int RomAlertPhaseCyclesSize = 64;
+ parameter int OwnerSwCfgDigestOffset = 1656;
+ parameter int OwnerSwCfgDigestSize = 8;
+ parameter int HwCfgOffset = 1664;
+ parameter int HwCfgSize = 80;
+ parameter int DeviceIdOffset = 1664;
+ parameter int DeviceIdSize = 32;
+ parameter int ManufStateOffset = 1696;
+ parameter int ManufStateSize = 32;
+ parameter int EnSramIfetchOffset = 1728;
+ parameter int EnSramIfetchSize = 1;
+ parameter int EnCsrngSwAppReadOffset = 1729;
+ parameter int EnCsrngSwAppReadSize = 1;
+ parameter int EnEntropySrcFwReadOffset = 1730;
+ parameter int EnEntropySrcFwReadSize = 1;
+ parameter int EnEntropySrcFwOverOffset = 1731;
+ parameter int EnEntropySrcFwOverSize = 1;
+ parameter int HwCfgDigestOffset = 1736;
+ parameter int HwCfgDigestSize = 8;
+ parameter int Secret0Offset = 1744;
+ parameter int Secret0Size = 40;
+ parameter int TestUnlockTokenOffset = 1744;
+ parameter int TestUnlockTokenSize = 16;
+ parameter int TestExitTokenOffset = 1760;
+ parameter int TestExitTokenSize = 16;
+ parameter int Secret0DigestOffset = 1776;
+ parameter int Secret0DigestSize = 8;
+ parameter int Secret1Offset = 1784;
+ parameter int Secret1Size = 88;
+ parameter int FlashAddrKeySeedOffset = 1784;
+ parameter int FlashAddrKeySeedSize = 32;
+ parameter int FlashDataKeySeedOffset = 1816;
+ parameter int FlashDataKeySeedSize = 32;
+ parameter int SramDataKeySeedOffset = 1848;
+ parameter int SramDataKeySeedSize = 16;
+ parameter int Secret1DigestOffset = 1864;
+ parameter int Secret1DigestSize = 8;
+ parameter int Secret2Offset = 1872;
+ parameter int Secret2Size = 88;
+ parameter int RmaTokenOffset = 1872;
+ parameter int RmaTokenSize = 16;
+ parameter int CreatorRootKeyShare0Offset = 1888;
+ parameter int CreatorRootKeyShare0Size = 32;
+ parameter int CreatorRootKeyShare1Offset = 1920;
+ parameter int CreatorRootKeyShare1Size = 32;
+ parameter int Secret2DigestOffset = 1952;
+ parameter int Secret2DigestSize = 8;
+ parameter int LifeCycleOffset = 1960;
+ parameter int LifeCycleSize = 88;
+ parameter int LcTransitionCntOffset = 1960;
+ parameter int LcTransitionCntSize = 48;
+ parameter int LcStateOffset = 2008;
+ parameter int LcStateSize = 40;
+ parameter int NumAlerts = 3;
+
+ // Address widths within the block
+ parameter int CoreAw = 13;
+ parameter int PrimAw = 1;
+
+ ///////////////////////////////////////////////
+ // Typedefs for registers for core interface //
+ ///////////////////////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } otp_operation_done;
+ struct packed {
+ logic q;
+ } otp_error;
+ } otp_ctrl_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } otp_operation_done;
+ struct packed {
+ logic q;
+ } otp_error;
+ } otp_ctrl_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } otp_operation_done;
+ struct packed {
+ logic q;
+ logic qe;
+ } otp_error;
+ } otp_ctrl_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_macro_error;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_check_error;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_bus_integ_error;
+ } otp_ctrl_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } rd;
+ struct packed {
+ logic q;
+ logic qe;
+ } wr;
+ struct packed {
+ logic q;
+ logic qe;
+ } digest;
+ } otp_ctrl_reg2hw_direct_access_cmd_reg_t;
+
+ typedef struct packed {
+ logic [10:0] q;
+ } otp_ctrl_reg2hw_direct_access_address_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } otp_ctrl_reg2hw_direct_access_wdata_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } integrity;
+ struct packed {
+ logic q;
+ logic qe;
+ } consistency;
+ } otp_ctrl_reg2hw_check_trigger_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } otp_ctrl_reg2hw_check_timeout_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } otp_ctrl_reg2hw_integrity_check_period_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } otp_ctrl_reg2hw_consistency_check_period_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } otp_ctrl_reg2hw_vendor_test_read_lock_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } otp_ctrl_reg2hw_creator_sw_cfg_read_lock_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } otp_ctrl_reg2hw_owner_sw_cfg_read_lock_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } otp_operation_done;
+ struct packed {
+ logic d;
+ logic de;
+ } otp_error;
+ } otp_ctrl_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ } vendor_test_error;
+ struct packed {
+ logic d;
+ } creator_sw_cfg_error;
+ struct packed {
+ logic d;
+ } owner_sw_cfg_error;
+ struct packed {
+ logic d;
+ } hw_cfg_error;
+ struct packed {
+ logic d;
+ } secret0_error;
+ struct packed {
+ logic d;
+ } secret1_error;
+ struct packed {
+ logic d;
+ } secret2_error;
+ struct packed {
+ logic d;
+ } life_cycle_error;
+ struct packed {
+ logic d;
+ } dai_error;
+ struct packed {
+ logic d;
+ } lci_error;
+ struct packed {
+ logic d;
+ } timeout_error;
+ struct packed {
+ logic d;
+ } lfsr_fsm_error;
+ struct packed {
+ logic d;
+ } scrambling_fsm_error;
+ struct packed {
+ logic d;
+ } key_deriv_fsm_error;
+ struct packed {
+ logic d;
+ } bus_integ_error;
+ struct packed {
+ logic d;
+ } dai_idle;
+ struct packed {
+ logic d;
+ } check_pending;
+ } otp_ctrl_hw2reg_status_reg_t;
+
+ typedef struct packed {
+ logic [2:0] d;
+ } otp_ctrl_hw2reg_err_code_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ } otp_ctrl_hw2reg_direct_access_regwen_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_direct_access_rdata_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_vendor_test_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_creator_sw_cfg_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_owner_sw_cfg_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_hw_cfg_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_secret0_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_secret1_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_secret2_digest_mreg_t;
+
+ // Register -> HW type for core interface
+ typedef struct packed {
+ otp_ctrl_reg2hw_intr_state_reg_t intr_state; // [197:196]
+ otp_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [195:194]
+ otp_ctrl_reg2hw_intr_test_reg_t intr_test; // [193:190]
+ otp_ctrl_reg2hw_alert_test_reg_t alert_test; // [189:184]
+ otp_ctrl_reg2hw_direct_access_cmd_reg_t direct_access_cmd; // [183:178]
+ otp_ctrl_reg2hw_direct_access_address_reg_t direct_access_address; // [177:167]
+ otp_ctrl_reg2hw_direct_access_wdata_mreg_t [1:0] direct_access_wdata; // [166:103]
+ otp_ctrl_reg2hw_check_trigger_reg_t check_trigger; // [102:99]
+ otp_ctrl_reg2hw_check_timeout_reg_t check_timeout; // [98:67]
+ otp_ctrl_reg2hw_integrity_check_period_reg_t integrity_check_period; // [66:35]
+ otp_ctrl_reg2hw_consistency_check_period_reg_t consistency_check_period; // [34:3]
+ otp_ctrl_reg2hw_vendor_test_read_lock_reg_t vendor_test_read_lock; // [2:2]
+ otp_ctrl_reg2hw_creator_sw_cfg_read_lock_reg_t creator_sw_cfg_read_lock; // [1:1]
+ otp_ctrl_reg2hw_owner_sw_cfg_read_lock_reg_t owner_sw_cfg_read_lock; // [0:0]
+ } otp_ctrl_core_reg2hw_t;
+
+ // HW -> register type for core interface
+ typedef struct packed {
+ otp_ctrl_hw2reg_intr_state_reg_t intr_state; // [563:560]
+ otp_ctrl_hw2reg_status_reg_t status; // [559:543]
+ otp_ctrl_hw2reg_err_code_mreg_t [9:0] err_code; // [542:513]
+ otp_ctrl_hw2reg_direct_access_regwen_reg_t direct_access_regwen; // [512:512]
+ otp_ctrl_hw2reg_direct_access_rdata_mreg_t [1:0] direct_access_rdata; // [511:448]
+ otp_ctrl_hw2reg_vendor_test_digest_mreg_t [1:0] vendor_test_digest; // [447:384]
+ otp_ctrl_hw2reg_creator_sw_cfg_digest_mreg_t [1:0] creator_sw_cfg_digest; // [383:320]
+ otp_ctrl_hw2reg_owner_sw_cfg_digest_mreg_t [1:0] owner_sw_cfg_digest; // [319:256]
+ otp_ctrl_hw2reg_hw_cfg_digest_mreg_t [1:0] hw_cfg_digest; // [255:192]
+ otp_ctrl_hw2reg_secret0_digest_mreg_t [1:0] secret0_digest; // [191:128]
+ otp_ctrl_hw2reg_secret1_digest_mreg_t [1:0] secret1_digest; // [127:64]
+ otp_ctrl_hw2reg_secret2_digest_mreg_t [1:0] secret2_digest; // [63:0]
+ } otp_ctrl_core_hw2reg_t;
+
+ // Register offsets for core interface
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTR_STATE_OFFSET = 13'h0;
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTR_ENABLE_OFFSET = 13'h4;
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTR_TEST_OFFSET = 13'h8;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ALERT_TEST_OFFSET = 13'hc;
+ parameter logic [CoreAw-1:0] OTP_CTRL_STATUS_OFFSET = 13'h10;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_OFFSET = 13'h14;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET = 13'h18;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET = 13'h1c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET = 13'h20;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET = 13'h24;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET = 13'h28;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET = 13'h2c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET = 13'h30;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET = 13'h34;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_OFFSET = 13'h38;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_REGWEN_OFFSET = 13'h3c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TIMEOUT_OFFSET = 13'h40;
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET = 13'h44;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET = 13'h48;
+ parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET = 13'h4c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET = 13'h50;
+ parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET = 13'h54;
+ parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET = 13'h58;
+ parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET = 13'h5c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET = 13'h60;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET = 13'h64;
+ parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET = 13'h68;
+ parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET = 13'h6c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG_DIGEST_0_OFFSET = 13'h70;
+ parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG_DIGEST_1_OFFSET = 13'h74;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_0_OFFSET = 13'h78;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_1_OFFSET = 13'h7c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_0_OFFSET = 13'h80;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_1_OFFSET = 13'h84;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_0_OFFSET = 13'h88;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_1_OFFSET = 13'h8c;
+
+ // Reset values for hwext registers and their fields for core interface
+ parameter logic [1:0] OTP_CTRL_INTR_TEST_RESVAL = 2'h0;
+ parameter logic [0:0] OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL = 1'h0;
+ parameter logic [2:0] OTP_CTRL_ALERT_TEST_RESVAL = 3'h0;
+ parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL = 1'h0;
+ parameter logic [16:0] OTP_CTRL_STATUS_RESVAL = 17'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_DAI_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_LCI_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_DAI_IDLE_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_CHECK_PENDING_RESVAL = 1'h0;
+ parameter logic [29:0] OTP_CTRL_ERR_CODE_RESVAL = 30'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL = 3'h0;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL = 1'h1;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL = 1'h1;
+ parameter logic [2:0] OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL = 3'h0;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL = 1'h0;
+ parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL = 32'h0;
+ parameter logic [1:0] OTP_CTRL_CHECK_TRIGGER_RESVAL = 2'h0;
+ parameter logic [0:0] OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL = 1'h0;
+ parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_HW_CFG_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_HW_CFG_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL = 32'h0;
+
+ // Window parameters for core interface
+ parameter logic [CoreAw-1:0] OTP_CTRL_SW_CFG_WINDOW_OFFSET = 13'h1000;
+ parameter int unsigned OTP_CTRL_SW_CFG_WINDOW_SIZE = 'h800;
+
+ // Register index for core interface
+ typedef enum int {
+ OTP_CTRL_INTR_STATE,
+ OTP_CTRL_INTR_ENABLE,
+ OTP_CTRL_INTR_TEST,
+ OTP_CTRL_ALERT_TEST,
+ OTP_CTRL_STATUS,
+ OTP_CTRL_ERR_CODE,
+ OTP_CTRL_DIRECT_ACCESS_REGWEN,
+ OTP_CTRL_DIRECT_ACCESS_CMD,
+ OTP_CTRL_DIRECT_ACCESS_ADDRESS,
+ OTP_CTRL_DIRECT_ACCESS_WDATA_0,
+ OTP_CTRL_DIRECT_ACCESS_WDATA_1,
+ OTP_CTRL_DIRECT_ACCESS_RDATA_0,
+ OTP_CTRL_DIRECT_ACCESS_RDATA_1,
+ OTP_CTRL_CHECK_TRIGGER_REGWEN,
+ OTP_CTRL_CHECK_TRIGGER,
+ OTP_CTRL_CHECK_REGWEN,
+ OTP_CTRL_CHECK_TIMEOUT,
+ OTP_CTRL_INTEGRITY_CHECK_PERIOD,
+ OTP_CTRL_CONSISTENCY_CHECK_PERIOD,
+ OTP_CTRL_VENDOR_TEST_READ_LOCK,
+ OTP_CTRL_CREATOR_SW_CFG_READ_LOCK,
+ OTP_CTRL_OWNER_SW_CFG_READ_LOCK,
+ OTP_CTRL_VENDOR_TEST_DIGEST_0,
+ OTP_CTRL_VENDOR_TEST_DIGEST_1,
+ OTP_CTRL_CREATOR_SW_CFG_DIGEST_0,
+ OTP_CTRL_CREATOR_SW_CFG_DIGEST_1,
+ OTP_CTRL_OWNER_SW_CFG_DIGEST_0,
+ OTP_CTRL_OWNER_SW_CFG_DIGEST_1,
+ OTP_CTRL_HW_CFG_DIGEST_0,
+ OTP_CTRL_HW_CFG_DIGEST_1,
+ OTP_CTRL_SECRET0_DIGEST_0,
+ OTP_CTRL_SECRET0_DIGEST_1,
+ OTP_CTRL_SECRET1_DIGEST_0,
+ OTP_CTRL_SECRET1_DIGEST_1,
+ OTP_CTRL_SECRET2_DIGEST_0,
+ OTP_CTRL_SECRET2_DIGEST_1
+ } otp_ctrl_core_id_e;
+
+ // Register width information to check illegal writes for core interface
+ parameter logic [3:0] OTP_CTRL_CORE_PERMIT [36] = '{
+ 4'b0001, // index[ 0] OTP_CTRL_INTR_STATE
+ 4'b0001, // index[ 1] OTP_CTRL_INTR_ENABLE
+ 4'b0001, // index[ 2] OTP_CTRL_INTR_TEST
+ 4'b0001, // index[ 3] OTP_CTRL_ALERT_TEST
+ 4'b0111, // index[ 4] OTP_CTRL_STATUS
+ 4'b1111, // index[ 5] OTP_CTRL_ERR_CODE
+ 4'b0001, // index[ 6] OTP_CTRL_DIRECT_ACCESS_REGWEN
+ 4'b0001, // index[ 7] OTP_CTRL_DIRECT_ACCESS_CMD
+ 4'b0011, // index[ 8] OTP_CTRL_DIRECT_ACCESS_ADDRESS
+ 4'b1111, // index[ 9] OTP_CTRL_DIRECT_ACCESS_WDATA_0
+ 4'b1111, // index[10] OTP_CTRL_DIRECT_ACCESS_WDATA_1
+ 4'b1111, // index[11] OTP_CTRL_DIRECT_ACCESS_RDATA_0
+ 4'b1111, // index[12] OTP_CTRL_DIRECT_ACCESS_RDATA_1
+ 4'b0001, // index[13] OTP_CTRL_CHECK_TRIGGER_REGWEN
+ 4'b0001, // index[14] OTP_CTRL_CHECK_TRIGGER
+ 4'b0001, // index[15] OTP_CTRL_CHECK_REGWEN
+ 4'b1111, // index[16] OTP_CTRL_CHECK_TIMEOUT
+ 4'b1111, // index[17] OTP_CTRL_INTEGRITY_CHECK_PERIOD
+ 4'b1111, // index[18] OTP_CTRL_CONSISTENCY_CHECK_PERIOD
+ 4'b0001, // index[19] OTP_CTRL_VENDOR_TEST_READ_LOCK
+ 4'b0001, // index[20] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK
+ 4'b0001, // index[21] OTP_CTRL_OWNER_SW_CFG_READ_LOCK
+ 4'b1111, // index[22] OTP_CTRL_VENDOR_TEST_DIGEST_0
+ 4'b1111, // index[23] OTP_CTRL_VENDOR_TEST_DIGEST_1
+ 4'b1111, // index[24] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0
+ 4'b1111, // index[25] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1
+ 4'b1111, // index[26] OTP_CTRL_OWNER_SW_CFG_DIGEST_0
+ 4'b1111, // index[27] OTP_CTRL_OWNER_SW_CFG_DIGEST_1
+ 4'b1111, // index[28] OTP_CTRL_HW_CFG_DIGEST_0
+ 4'b1111, // index[29] OTP_CTRL_HW_CFG_DIGEST_1
+ 4'b1111, // index[30] OTP_CTRL_SECRET0_DIGEST_0
+ 4'b1111, // index[31] OTP_CTRL_SECRET0_DIGEST_1
+ 4'b1111, // index[32] OTP_CTRL_SECRET1_DIGEST_0
+ 4'b1111, // index[33] OTP_CTRL_SECRET1_DIGEST_1
+ 4'b1111, // index[34] OTP_CTRL_SECRET2_DIGEST_0
+ 4'b1111 // index[35] OTP_CTRL_SECRET2_DIGEST_1
+ };
+
+endpackage
+
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_alert_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_alert_pkg.sv
new file mode 100644
index 00000000..a3594b61
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_alert_pkg.sv
@@ -0,0 +1,27 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package prim_alert_pkg;
+
+ typedef struct packed {
+ logic alert_p;
+ logic alert_n;
+ } alert_tx_t;
+
+ typedef struct packed {
+ logic ping_p;
+ logic ping_n;
+ logic ack_p;
+ logic ack_n;
+ } alert_rx_t;
+
+ parameter alert_tx_t ALERT_TX_DEFAULT = '{alert_p: 1'b0,
+ alert_n: 1'b1};
+
+ parameter alert_rx_t ALERT_RX_DEFAULT = '{ping_p: 1'b0,
+ ping_n: 1'b1,
+ ack_p: 1'b0,
+ ack_n: 1'b1};
+
+endpackage : prim_alert_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_alert_sender.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_alert_sender.sv
new file mode 100644
index 00000000..b9793596
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_alert_sender.sv
@@ -0,0 +1,239 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// The alert sender primitive module differentially encodes and transmits an
+// alert signal to the prim_alert_receiver module. An alert will be signalled
+// by a full handshake on alert_p/n and ack_p/n. The alert_req_i signal may
+// be continuously asserted, in which case the alert signalling handshake
+// will be repeatedly initiated.
+//
+// The alert_req_i signal may also be used as part of req/ack. The parent module
+// can keep alert_req_i asserted until it has been ack'd (transferred to the alert
+// receiver). The parent module is not required to use this.
+//
+// Further, this module supports in-band ping testing, which means that a level
+// change on the ping_p/n diff pair will result in a full-handshake response
+// on alert_p/n and ack_p/n.
+//
+// The protocol works in both asynchronous and synchronous cases. In the
+// asynchronous case, the parameter AsyncOn must be set to 1'b1 in order to
+// instantiate additional synchronization logic. Further, it must be ensured
+// that the timing skew between all diff pairs is smaller than the shortest
+// clock period of the involved clocks.
+//
+// Incorrectly encoded diff inputs can be detected and will be signalled
+// to the receiver by placing an inconsistent diff value on the differential
+// output (and continuously toggling it).
+//
+// See also: prim_alert_receiver, prim_diff_decode, alert_handler
+
+
+module prim_alert_sender
+ import prim_alert_pkg::*;
+#(parameter IsFatal = 1'b1,
+ // enables additional synchronization logic
+ parameter bit AsyncOn = 1'b1
+) (
+ input clk_i,
+ input rst_ni,
+ // native alert from the peripheral
+ input alert_req_i,
+ output logic alert_ack_o,
+ // ping input diff pair and ack diff pair
+ input alert_rx_t alert_rx_i,
+ // alert output diff pair
+ output alert_tx_t alert_tx_o
+);
+
+
+ /////////////////////////////////
+ // decode differential signals //
+ /////////////////////////////////
+ logic ping_sigint, ping_event;
+
+ prim_diff_decode #(
+ .AsyncOn(AsyncOn)
+ ) i_decode_ping (
+ .clk_i,
+ .rst_ni,
+ .diff_pi ( alert_rx_i.ping_p ),
+ .diff_ni ( alert_rx_i.ping_n ),
+ .level_o ( ),
+ .rise_o ( ),
+ .fall_o ( ),
+ .event_o ( ping_event ),
+ .sigint_o ( ping_sigint )
+ );
+
+ logic ack_sigint, ack_level;
+
+ prim_diff_decode #(
+ .AsyncOn(AsyncOn)
+ ) i_decode_ack (
+ .clk_i,
+ .rst_ni,
+ .diff_pi ( alert_rx_i.ack_p ),
+ .diff_ni ( alert_rx_i.ack_n ),
+ .level_o ( ack_level ),
+ .rise_o ( ),
+ .fall_o ( ),
+ .event_o ( ),
+ .sigint_o ( ack_sigint )
+ );
+
+
+ ///////////////////////////////////////////////////
+ // main protocol FSM that drives the diff output //
+ ///////////////////////////////////////////////////
+ typedef enum logic [2:0] {
+ Idle,
+ AlertHsPhase1,
+ AlertHsPhase2,
+ PingHsPhase1,
+ PingHsPhase2,
+ SigInt,
+ Pause0,
+ Pause1
+ } state_e;
+ state_e state_d, state_q;
+ logic alert_p, alert_n, alert_pq, alert_nq, alert_pd, alert_nd;
+ logic sigint_detected;
+
+ assign sigint_detected = ack_sigint | ping_sigint;
+
+
+ // diff pair output
+ assign alert_tx_o.alert_p = alert_pq;
+ assign alert_tx_o.alert_n = alert_nq;
+
+ // alert and ping set regs
+ logic alert_set_d, alert_set_q, alert_clr;
+ logic ping_set_d, ping_set_q, ping_clr;
+
+ // if handshake is ongoing, capture additional alert requests
+ assign alert_set_d = (alert_clr) ? 1'b0 : (alert_set_q | alert_req_i);
+ assign ping_set_d = (ping_clr) ? 1'b0 : (ping_set_q | ping_event);
+
+ // alert event acknowledge
+ assign alert_ack_o = alert_clr;
+
+ // this FSM performs a full four phase handshake upon a ping or alert trigger.
+ // note that the latency of the alert_p/n diff pair is at least one cycle
+ // until it enters the receiver FSM. the same holds for the ack_* diff pair
+ // input. in case a signal integrity issue is detected, the FSM bails out,
+ // sets the alert_p/n diff pair to the same value and toggles it in order to
+ // signal that condition over to the receiver.
+ always_comb begin : p_fsm
+ // default
+ state_d = state_q;
+ alert_p = 1'b0;
+ alert_n = 1'b1;
+ ping_clr = 1'b0;
+ alert_clr = 1'b0;
+
+ unique case (state_q)
+ Idle: begin
+ // alert always takes precedence
+ if (alert_req_i || alert_set_q || ping_event || ping_set_q) begin
+ state_d = (alert_req_i || alert_set_q) ? AlertHsPhase1 : PingHsPhase1;
+ alert_p = 1'b1;
+ alert_n = 1'b0;
+ end
+ end
+ // waiting for ack from receiver
+ AlertHsPhase1: begin
+ if (ack_level) begin
+ state_d = AlertHsPhase2;
+ end else begin
+ alert_p = 1'b1;
+ alert_n = 1'b0;
+ end
+ end
+ // wait for deassertion of ack
+ AlertHsPhase2: begin
+ if (!ack_level) begin
+ state_d = Pause0;
+ alert_clr = 1'b1;
+ end
+ end
+ // waiting for ack from receiver
+ PingHsPhase1: begin
+ if (ack_level) begin
+ state_d = PingHsPhase2;
+ end else begin
+ alert_p = 1'b1;
+ alert_n = 1'b0;
+ end
+ end
+ // wait for deassertion of ack
+ PingHsPhase2: begin
+ if (!ack_level) begin
+ ping_clr = 1'b1;
+ state_d = Pause0;
+ end
+ end
+ // pause cycles between back-to-back handshakes
+ Pause0: begin
+ state_d = Pause1;
+ end
+
+ // clear and ack alert request if it was set
+ Pause1: begin
+ state_d = Idle;
+ end
+
+ // we have a signal integrity issue at one of
+ // the incoming diff pairs. this condition is
+ // signalled by setting the output diffpair
+ // to the same value and continuously toggling
+ // them.
+ SigInt: begin
+ state_d = Idle;
+ if (sigint_detected) begin
+ state_d = SigInt;
+ alert_p = ~alert_pq;
+ alert_n = ~alert_pq;
+ end
+ end
+ // catch parasitic states
+ default : state_d = Idle;
+ endcase
+ // bail out if a signal integrity issue has been detected
+ if (sigint_detected && (state_q != SigInt)) begin
+ state_d = SigInt;
+ alert_p = 1'b0;
+ alert_n = 1'b0;
+ ping_clr = 1'b0;
+ alert_clr = 1'b0;
+ end
+ end
+
+ // This prevents further tool optimizations of the differential signal.
+ prim_buf u_prim_buf_p (
+ .in_i(alert_p),
+ .out_o(alert_pd)
+ );
+ prim_buf u_prim_buf_n (
+ .in_i(alert_n),
+ .out_o(alert_nd)
+ );
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg
+ if (!rst_ni) begin
+ state_q <= Idle;
+ alert_pq <= 1'b0;
+ alert_nq <= 1'b1;
+ alert_set_q <= 1'b0;
+ ping_set_q <= 1'b0;
+ end else begin
+ state_q <= state_d;
+ alert_pq <= alert_pd;
+ alert_nq <= alert_nd;
+ alert_set_q <= alert_set_d;
+ ping_set_q <= ping_set_d;
+ end
+ end
+
+
+endmodule : prim_alert_sender
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_buf.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_buf.sv
new file mode 100644
index 00000000..60773881
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_buf.sv
@@ -0,0 +1,37 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is auto-generated.
+
+
+
+
+
+// This is to prevent AscentLint warnings in the generated
+// abstract prim wrapper. These warnings occur due to the .*
+// use. TODO: we may want to move these inline waivers
+// into a separate, generated waiver file for consistency.
+//ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
+module prim_buf
+
+#(
+parameter Width = 1
+) (
+ input in_i,
+ output logic out_o
+);
+ parameter prim_pkg::impl_e Impl = prim_pkg::ImplGeneric;
+
+if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx
+ prim_xilinx_buf u_impl_xilinx (
+ .*
+ );
+end else begin : gen_generic
+ prim_generic_buf u_impl_generic (
+ .*
+ );
+end
+
+endmodule
+//ri lint_check_on OUTPUT_NOT_DRIVEN INPUT_NOT_READ
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_cipher_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_cipher_pkg.sv
new file mode 100644
index 00000000..372baa02
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_cipher_pkg.sv
@@ -0,0 +1,397 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This package holds common constants and functions for PRESENT- and
+// PRINCE-based scrambling devices.
+//
+// See also: prim_present, prim_prince
+//
+// References: - https://en.wikipedia.org/wiki/PRESENT
+// - https://en.wikipedia.org/wiki/Prince_(cipher)
+// - http://www.lightweightcrypto.org/present/present_ches2007.pdf
+// - https://eprint.iacr.org/2012/529.pdf
+// - https://eprint.iacr.org/2015/372.pdf
+// - https://eprint.iacr.org/2014/656.pdf
+
+package prim_cipher_pkg;
+
+ ///////////////////
+ // PRINCE Cipher //
+ ///////////////////
+
+ parameter logic [15:0][3:0] PRINCE_SBOX4 = {4'h4, 4'hD, 4'h5, 4'hE,
+ 4'h0, 4'h8, 4'h7, 4'h6,
+ 4'h1, 4'h9, 4'hC, 4'hA,
+ 4'h2, 4'h3, 4'hF, 4'hB};
+
+ parameter logic [15:0][3:0] PRINCE_SBOX4_INV = {4'h1, 4'hC, 4'hE, 4'h5,
+ 4'h0, 4'h4, 4'h6, 4'hA,
+ 4'h9, 4'h8, 4'hD, 4'hF,
+ 4'h2, 4'h3, 4'h7, 4'hB};
+ // nibble permutations
+ parameter logic [15:0][3:0] PRINCE_SHIFT_ROWS64 = '{4'hF, 4'hA, 4'h5, 4'h0,
+ 4'hB, 4'h6, 4'h1, 4'hC,
+ 4'h7, 4'h2, 4'hD, 4'h8,
+ 4'h3, 4'hE, 4'h9, 4'h4};
+
+ parameter logic [15:0][3:0] PRINCE_SHIFT_ROWS64_INV = '{4'hF, 4'h2, 4'h5, 4'h8,
+ 4'hB, 4'hE, 4'h1, 4'h4,
+ 4'h7, 4'hA, 4'hD, 4'h0,
+ 4'h3, 4'h6, 4'h9, 4'hC};
+
+ // these are the round constants
+ parameter logic [11:0][63:0] PRINCE_ROUND_CONST = {64'hC0AC29B7C97C50DD,
+ 64'hD3B5A399CA0C2399,
+ 64'h64A51195E0E3610D,
+ 64'hC882D32F25323C54,
+ 64'h85840851F1AC43AA,
+ 64'h7EF84F78FD955CB1,
+ 64'hBE5466CF34E90C6C,
+ 64'h452821E638D01377,
+ 64'h082EFA98EC4E6C89,
+ 64'hA4093822299F31D0,
+ 64'h13198A2E03707344,
+ 64'h0000000000000000};
+
+ // tweak constant for key modification between enc/dec modes
+ parameter logic [63:0] PRINCE_ALPHA_CONST = 64'hC0AC29B7C97C50DD;
+
+ // masking constants for shift rows function below
+ parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST0 = 16'h7BDE;
+ parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST1 = 16'hBDE7;
+ parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST2 = 16'hDE7B;
+ parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST3 = 16'hE7BD;
+
+ // nibble shifts
+ function automatic logic [31:0] prince_shiftrows_32bit(logic [31:0] state_in,
+ logic [15:0][3:0] shifts );
+ logic [31:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 32/2; k++) begin
+ // operate on pairs of 2bit instead of nibbles
+ state_out[k*2 +: 2] = state_in[shifts[k]*2 +: 2];
+ end
+ return state_out;
+ endfunction : prince_shiftrows_32bit
+
+ function automatic logic [63:0] prince_shiftrows_64bit(logic [63:0] state_in,
+ logic [15:0][3:0] shifts );
+ logic [63:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 64/4; k++) begin
+ state_out[k*4 +: 4] = state_in[shifts[k]*4 +: 4];
+ end
+ return state_out;
+ endfunction : prince_shiftrows_64bit
+
+ // XOR reduction of four nibbles in a 16bit subvector
+ function automatic logic [3:0] prince_nibble_red16(logic [15:0] vect);
+ return vect[0 +: 4] ^ vect[4 +: 4] ^ vect[8 +: 4] ^ vect[12 +: 4];
+ endfunction : prince_nibble_red16
+
+ // M prime multiplication
+ function automatic logic [31:0] prince_mult_prime_32bit(logic [31:0] state_in);
+ logic [31:0] state_out;
+ // M0
+ state_out[0 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[4 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[8 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ state_out[12 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ // M1
+ state_out[16 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ state_out[20 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[24 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[28 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ return state_out;
+ endfunction : prince_mult_prime_32bit
+
+ // M prime multiplication
+ function automatic logic [63:0] prince_mult_prime_64bit(logic [63:0] state_in);
+ logic [63:0] state_out;
+ // M0
+ state_out[0 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[4 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[8 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ state_out[12 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ // M1
+ state_out[16 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ state_out[20 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[24 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[28 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ // M1
+ state_out[32 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ state_out[36 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[40 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[44 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ // M0
+ state_out[48 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[52 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[56 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ state_out[60 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ return state_out;
+ endfunction : prince_mult_prime_64bit
+
+
+ ////////////////////
+ // PRESENT Cipher //
+ ////////////////////
+
+ // this is the sbox from the present cipher
+ parameter logic [15:0][3:0] PRESENT_SBOX4 = {4'h2, 4'h1, 4'h7, 4'h4,
+ 4'h8, 4'hF, 4'hE, 4'h3,
+ 4'hD, 4'hA, 4'h0, 4'h9,
+ 4'hB, 4'h6, 4'h5, 4'hC};
+
+ parameter logic [15:0][3:0] PRESENT_SBOX4_INV = {4'hA, 4'h9, 4'h7, 4'h0,
+ 4'h3, 4'h6, 4'h4, 4'hB,
+ 4'hD, 4'h2, 4'h1, 4'hC,
+ 4'h8, 4'hF, 4'hE, 4'h5};
+
+ // these are modified permutation indices for a 32bit version that
+ // follow the same pattern as for the 64bit version
+ parameter logic [31:0][4:0] PRESENT_PERM32 = {5'd31, 5'd23, 5'd15, 5'd07,
+ 5'd30, 5'd22, 5'd14, 5'd06,
+ 5'd29, 5'd21, 5'd13, 5'd05,
+ 5'd28, 5'd20, 5'd12, 5'd04,
+ 5'd27, 5'd19, 5'd11, 5'd03,
+ 5'd26, 5'd18, 5'd10, 5'd02,
+ 5'd25, 5'd17, 5'd09, 5'd01,
+ 5'd24, 5'd16, 5'd08, 5'd00};
+
+ parameter logic [31:0][4:0] PRESENT_PERM32_INV = {5'd31, 5'd27, 5'd23, 5'd19,
+ 5'd15, 5'd11, 5'd07, 5'd03,
+ 5'd30, 5'd26, 5'd22, 5'd18,
+ 5'd14, 5'd10, 5'd06, 5'd02,
+ 5'd29, 5'd25, 5'd21, 5'd17,
+ 5'd13, 5'd09, 5'd05, 5'd01,
+ 5'd28, 5'd24, 5'd20, 5'd16,
+ 5'd12, 5'd08, 5'd04, 5'd00};
+
+ // these are the permutation indices of the present cipher
+ parameter logic [63:0][5:0] PRESENT_PERM64 = {6'd63, 6'd47, 6'd31, 6'd15,
+ 6'd62, 6'd46, 6'd30, 6'd14,
+ 6'd61, 6'd45, 6'd29, 6'd13,
+ 6'd60, 6'd44, 6'd28, 6'd12,
+ 6'd59, 6'd43, 6'd27, 6'd11,
+ 6'd58, 6'd42, 6'd26, 6'd10,
+ 6'd57, 6'd41, 6'd25, 6'd09,
+ 6'd56, 6'd40, 6'd24, 6'd08,
+ 6'd55, 6'd39, 6'd23, 6'd07,
+ 6'd54, 6'd38, 6'd22, 6'd06,
+ 6'd53, 6'd37, 6'd21, 6'd05,
+ 6'd52, 6'd36, 6'd20, 6'd04,
+ 6'd51, 6'd35, 6'd19, 6'd03,
+ 6'd50, 6'd34, 6'd18, 6'd02,
+ 6'd49, 6'd33, 6'd17, 6'd01,
+ 6'd48, 6'd32, 6'd16, 6'd00};
+
+ parameter logic [63:0][5:0] PRESENT_PERM64_INV = {6'd63, 6'd59, 6'd55, 6'd51,
+ 6'd47, 6'd43, 6'd39, 6'd35,
+ 6'd31, 6'd27, 6'd23, 6'd19,
+ 6'd15, 6'd11, 6'd07, 6'd03,
+ 6'd62, 6'd58, 6'd54, 6'd50,
+ 6'd46, 6'd42, 6'd38, 6'd34,
+ 6'd30, 6'd26, 6'd22, 6'd18,
+ 6'd14, 6'd10, 6'd06, 6'd02,
+ 6'd61, 6'd57, 6'd53, 6'd49,
+ 6'd45, 6'd41, 6'd37, 6'd33,
+ 6'd29, 6'd25, 6'd21, 6'd17,
+ 6'd13, 6'd09, 6'd05, 6'd01,
+ 6'd60, 6'd56, 6'd52, 6'd48,
+ 6'd44, 6'd40, 6'd36, 6'd32,
+ 6'd28, 6'd24, 6'd20, 6'd16,
+ 6'd12, 6'd08, 6'd04, 6'd00};
+
+ // forward key schedule
+ function automatic logic [63:0] present_update_key64(logic [63:0] key_in,
+ logic [4:0] round_idx);
+ logic [63:0] key_out;
+ // rotate by 61 to the left
+ key_out = {key_in[63-61:0], key_in[63:64-61]};
+ // sbox on uppermost 4 bits
+ key_out[63 -: 4] = PRESENT_SBOX4[key_out[63 -: 4]];
+ // xor in round counter on bits 19 to 15
+ key_out[19:15] ^= round_idx;
+ return key_out;
+ endfunction : present_update_key64
+
+ function automatic logic [79:0] present_update_key80(logic [79:0] key_in,
+ logic [4:0] round_idx);
+ logic [79:0] key_out;
+ // rotate by 61 to the left
+ key_out = {key_in[79-61:0], key_in[79:80-61]};
+ // sbox on uppermost 4 bits
+ key_out[79 -: 4] = PRESENT_SBOX4[key_out[79 -: 4]];
+ // xor in round counter on bits 19 to 15
+ key_out[19:15] ^= round_idx;
+ return key_out;
+ endfunction : present_update_key80
+
+ function automatic logic [127:0] present_update_key128(logic [127:0] key_in,
+ logic [4:0] round_idx);
+ logic [127:0] key_out;
+ // rotate by 61 to the left
+ key_out = {key_in[127-61:0], key_in[127:128-61]};
+ // sbox on uppermost 4 bits
+ key_out[127 -: 4] = PRESENT_SBOX4[key_out[127 -: 4]];
+ // sbox on second nibble from top
+ key_out[123 -: 4] = PRESENT_SBOX4[key_out[123 -: 4]];
+ // xor in round counter on bits 66 to 62
+ key_out[66:62] ^= round_idx;
+ return key_out;
+ endfunction : present_update_key128
+
+
+ // inverse key schedule
+ function automatic logic [63:0] present_inv_update_key64(logic [63:0] key_in,
+ logic [4:0] round_idx);
+ logic [63:0] key_out = key_in;
+ // xor in round counter on bits 19 to 15
+ key_out[19:15] ^= round_idx;
+ // sbox on uppermost 4 bits
+ key_out[63 -: 4] = PRESENT_SBOX4_INV[key_out[63 -: 4]];
+ // rotate by 61 to the right
+ key_out = {key_out[60:0], key_out[63:61]};
+ return key_out;
+ endfunction : present_inv_update_key64
+
+ function automatic logic [79:0] present_inv_update_key80(logic [79:0] key_in,
+ logic [4:0] round_idx);
+ logic [79:0] key_out = key_in;
+ // xor in round counter on bits 19 to 15
+ key_out[19:15] ^= round_idx;
+ // sbox on uppermost 4 bits
+ key_out[79 -: 4] = PRESENT_SBOX4_INV[key_out[79 -: 4]];
+ // rotate by 61 to the right
+ key_out = {key_out[60:0], key_out[79:61]};
+ return key_out;
+ endfunction : present_inv_update_key80
+
+ function automatic logic [127:0] present_inv_update_key128(logic [127:0] key_in,
+ logic [4:0] round_idx);
+ logic [127:0] key_out = key_in;
+ // xor in round counter on bits 66 to 62
+ key_out[66:62] ^= round_idx;
+ // sbox on second highest nibble
+ key_out[123 -: 4] = PRESENT_SBOX4_INV[key_out[123 -: 4]];
+ // sbox on uppermost 4 bits
+ key_out[127 -: 4] = PRESENT_SBOX4_INV[key_out[127 -: 4]];
+ // rotate by 61 to the right
+ key_out = {key_out[60:0], key_out[127:61]};
+ return key_out;
+ endfunction : present_inv_update_key128
+
+
+ // these functions can be used to derive the DEC key from the ENC key by
+ // stepping the key by the correct number of rounds using the keyschedule functions above.
+ function automatic logic [63:0] present_get_dec_key64(logic [63:0] key_in,
+ // total number of rounds employed
+ logic [4:0] round_cnt);
+ logic [63:0] key_out;
+ key_out = key_in;
+ for (int unsigned k = 0; k < round_cnt; k++) begin
+ key_out = present_update_key64(key_out, 5'(k + 1));
+ end
+ return key_out;
+ endfunction : present_get_dec_key64
+
+ function automatic logic [79:0] present_get_dec_key80(logic [79:0] key_in,
+ // total number of rounds employed
+ logic [4:0] round_cnt);
+ logic [79:0] key_out;
+ key_out = key_in;
+ for (int unsigned k = 0; k < round_cnt; k++) begin
+ key_out = present_update_key80(key_out, 5'(k + 1));
+ end
+ return key_out;
+ endfunction : present_get_dec_key80
+
+ function automatic logic [127:0] present_get_dec_key128(logic [127:0] key_in,
+ // total number of rounds employed
+ logic [4:0] round_cnt);
+ logic [127:0] key_out;
+ key_out = key_in;
+ for (int unsigned k = 0; k < round_cnt; k++) begin
+ key_out = present_update_key128(key_out, 5'(k + 1));
+ end
+ return key_out;
+ endfunction : present_get_dec_key128
+
+ /////////////////////////
+ // Common Subfunctions //
+ /////////////////////////
+
+ function automatic logic [7:0] sbox4_8bit(logic [7:0] state_in, logic [15:0][3:0] sbox4);
+ logic [7:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 8/4; k++) begin
+ state_out[k*4 +: 4] = sbox4[state_in[k*4 +: 4]];
+ end
+ return state_out;
+ endfunction : sbox4_8bit
+
+ function automatic logic [15:0] sbox4_16bit(logic [15:0] state_in, logic [15:0][3:0] sbox4);
+ logic [15:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 2; k++) begin
+ state_out[k*8 +: 8] = sbox4_8bit(state_in[k*8 +: 8], sbox4);
+ end
+ return state_out;
+ endfunction : sbox4_16bit
+
+ function automatic logic [31:0] sbox4_32bit(logic [31:0] state_in, logic [15:0][3:0] sbox4);
+ logic [31:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 4; k++) begin
+ state_out[k*8 +: 8] = sbox4_8bit(state_in[k*8 +: 8], sbox4);
+ end
+ return state_out;
+ endfunction : sbox4_32bit
+
+ function automatic logic [63:0] sbox4_64bit(logic [63:0] state_in, logic [15:0][3:0] sbox4);
+ logic [63:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 8; k++) begin
+ state_out[k*8 +: 8] = sbox4_8bit(state_in[k*8 +: 8], sbox4);
+ end
+ return state_out;
+ endfunction : sbox4_64bit
+
+ function automatic logic [7:0] perm_8bit(logic [7:0] state_in, logic [7:0][2:0] perm);
+ logic [7:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 8; k++) begin
+ state_out[perm[k]] = state_in[k];
+ end
+ return state_out;
+ endfunction : perm_8bit
+
+ function automatic logic [15:0] perm_16bit(logic [15:0] state_in, logic [15:0][3:0] perm);
+ logic [15:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 16; k++) begin
+ state_out[perm[k]] = state_in[k];
+ end
+ return state_out;
+ endfunction : perm_16bit
+
+ function automatic logic [31:0] perm_32bit(logic [31:0] state_in, logic [31:0][4:0] perm);
+ logic [31:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 32; k++) begin
+ state_out[perm[k]] = state_in[k];
+ end
+ return state_out;
+ endfunction : perm_32bit
+
+ function automatic logic [63:0] perm_64bit(logic [63:0] state_in, logic [63:0][5:0] perm);
+ logic [63:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 64; k++) begin
+ state_out[perm[k]] = state_in[k];
+ end
+ return state_out;
+ endfunction : perm_64bit
+
+endpackage : prim_cipher_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_count_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_count_pkg.sv
new file mode 100644
index 00000000..f49a270c
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_count_pkg.sv
@@ -0,0 +1,22 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Package for primitive hardened counter module
+//
+
+package prim_count_pkg;
+
+ // Enumeration for hardened count style
+ typedef enum logic {
+ CrossCnt, // up count and down count
+ DupCnt // duplicate counters
+ } prim_count_style_e;
+
+ // Enumeration for differential valid
+ typedef enum logic [1:0] {
+ CmpInvalid = 2'b01,
+ CmpValid = 2'b10
+ } cmp_valid_e;
+
+endpackage //
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_diff_decode.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_diff_decode.sv
new file mode 100644
index 00000000..780cb0bc
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_diff_decode.sv
@@ -0,0 +1,207 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This module decodes a differentially encoded signal and detects
+// incorrectly encoded differential states.
+//
+// In case the differential pair crosses an asynchronous boundary, it has
+// to be re-synchronized to the local clock. This can be achieved by
+// setting the AsyncOn parameter to 1'b1. In that case, two additional
+// input registers are added (to counteract metastability), and
+// a pattern detector is instantiated that detects skewed level changes on
+// the differential pair (i.e., when level changes on the diff pair are
+// sampled one cycle apart due to a timing skew between the two wires).
+//
+// See also: prim_alert_sender, prim_alert_receiver, alert_handler
+
+
+module prim_diff_decode #(
+ // enables additional synchronization logic
+ parameter bit AsyncOn = 1'b0
+) (
+ input clk_i,
+ input rst_ni,
+ // input diff pair
+ input diff_pi,
+ input diff_ni,
+ // logical level and
+ // detected edges
+ output logic level_o,
+ output logic rise_o,
+ output logic fall_o,
+ // either rise or fall
+ output logic event_o,
+ //signal integrity issue detected
+ output logic sigint_o
+);
+
+ logic level_d, level_q;
+
+ ///////////////////////////////////////////////////////////////
+ // synchronization regs for incoming diff pair (if required) //
+ ///////////////////////////////////////////////////////////////
+ if (AsyncOn) begin : gen_async
+
+ typedef enum logic [1:0] {IsStd, IsSkewed, SigInt} state_e;
+ state_e state_d, state_q;
+ logic diff_p_edge, diff_n_edge, diff_check_ok, level;
+
+ // 2 sync regs, one reg for edge detection
+ logic diff_pq, diff_nq, diff_pd, diff_nd;
+
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue(0)
+ ) i_sync_p (
+ .clk_i,
+ .rst_ni,
+ .d_i(diff_pi),
+ .q_o(diff_pd)
+ );
+
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue(1)
+ ) i_sync_n (
+ .clk_i,
+ .rst_ni,
+ .d_i(diff_ni),
+ .q_o(diff_nd)
+ );
+
+ // detect level transitions
+ assign diff_p_edge = diff_pq ^ diff_pd;
+ assign diff_n_edge = diff_nq ^ diff_nd;
+
+ // detect sigint issue
+ assign diff_check_ok = diff_pd ^ diff_nd;
+
+ // this is the current logical level
+ assign level = diff_pd;
+
+ // outputs
+ assign level_o = level_d;
+ assign event_o = rise_o | fall_o;
+
+ // sigint detection is a bit more involved in async case since
+ // we might have skew on the diff pair, which can result in a
+ // one cycle sampling delay between the two wires
+ // so we need a simple pattern matcher
+ // the following waves are legal
+ // clk | | | | | | | |
+ // _______ _______
+ // p _______/ ... \________
+ // _______ ________
+ // n \_______ ... _______/
+ // ____ ___
+ // p __________/ ... \________
+ // _______ ________
+ // n \_______ ... _______/
+ //
+ // i.e., level changes may be off by one cycle - which is permissible
+ // as long as this condition is only one cycle long.
+
+
+ always_comb begin : p_diff_fsm
+ // default
+ state_d = state_q;
+ level_d = level_q;
+ rise_o = 1'b0;
+ fall_o = 1'b0;
+ sigint_o = 1'b0;
+
+ unique case (state_q)
+ // we remain here as long as
+ // the diff pair is correctly encoded
+ IsStd: begin
+ if (diff_check_ok) begin
+ level_d = level;
+ if (diff_p_edge && diff_n_edge) begin
+ if (level) begin
+ rise_o = 1'b1;
+ end else begin
+ fall_o = 1'b1;
+ end
+ end
+ end else begin
+ if (diff_p_edge || diff_n_edge) begin
+ state_d = IsSkewed;
+ end else begin
+ state_d = SigInt;
+ sigint_o = 1'b1;
+ end
+ end
+ end
+ // diff pair must be correctly encoded, otherwise we got a sigint
+ IsSkewed: begin
+ if (diff_check_ok) begin
+ state_d = IsStd;
+ level_d = level;
+ if (level) rise_o = 1'b1;
+ else fall_o = 1'b1;
+ end else begin
+ state_d = SigInt;
+ sigint_o = 1'b1;
+ end
+ end
+ // Signal integrity issue detected, remain here
+ // until resolved
+ SigInt: begin
+ sigint_o = 1'b1;
+ if (diff_check_ok) begin
+ state_d = IsStd;
+ sigint_o = 1'b0;
+ end
+ end
+ default : ;
+ endcase
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_sync_reg
+ if (!rst_ni) begin
+ state_q <= IsStd;
+ diff_pq <= 1'b0;
+ diff_nq <= 1'b1;
+ level_q <= 1'b0;
+ end else begin
+ state_q <= state_d;
+ diff_pq <= diff_pd;
+ diff_nq <= diff_nd;
+ level_q <= level_d;
+ end
+ end
+
+ //////////////////////////////////////////////////////////
+ // fully synchronous case, no skew present in this case //
+ //////////////////////////////////////////////////////////
+ end else begin : gen_no_async
+ logic diff_pq, diff_pd;
+
+ // one reg for edge detection
+ assign diff_pd = diff_pi;
+
+ // incorrect encoding -> signal integrity issue
+ assign sigint_o = ~(diff_pi ^ diff_ni);
+
+ assign level_o = (sigint_o) ? level_q : diff_pi;
+ assign level_d = level_o;
+
+ // detect level transitions
+ assign rise_o = (~diff_pq & diff_pi) & ~sigint_o;
+ assign fall_o = ( diff_pq & ~diff_pi) & ~sigint_o;
+ assign event_o = rise_o | fall_o;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_edge_reg
+ if (!rst_ni) begin
+ diff_pq <= 1'b0;
+ level_q <= 1'b0;
+ end else begin
+ diff_pq <= diff_pd;
+ level_q <= level_d;
+ end
+ end
+ end
+
+
+endmodule : prim_diff_decode
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_fifo_sync.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_fifo_sync.sv
new file mode 100644
index 00000000..9bc0bff3
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_fifo_sync.sv
@@ -0,0 +1,148 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Generic synchronous fifo for use in a variety of devices.
+module prim_fifo_sync #(
+ parameter int unsigned Width = 16,
+ parameter bit Pass = 1'b1, // if == 1 allow requests to pass through empty FIFO
+ parameter int unsigned Depth = 4,
+ parameter bit OutputZeroIfEmpty = 1'b1, // if == 1 always output 0 when FIFO is empty
+ // derived parameter
+ localparam int unsigned DepthWNorm = $clog2(Depth+1),
+ localparam int unsigned DepthW = (DepthWNorm == 0) ? 1 : DepthWNorm
+) (
+ input clk_i,
+ input rst_ni,
+ // synchronous clear / flush port
+ input clr_i,
+ // write port
+ input wvalid,
+ output wready,
+ input [Width-1:0] wdata,
+ // read port
+ output rvalid,
+ input rready,
+ output [Width-1:0] rdata,
+ // occupancy
+ output [DepthW-1:0] depth
+);
+
+ // FIFO is in complete passthrough mode
+ if (Depth == 0) begin : gen_passthru_fifo
+
+ assign depth = 1'b0; //output is meaningless
+
+ // devie facing
+ assign rvalid = wvalid;
+ assign rdata = wdata;
+
+ // host facing
+ assign wready = rready;
+
+ // this avoids lint warnings
+ logic unused_clr;
+ assign unused_clr = clr_i;
+
+ // Normal FIFO construction
+ end else begin : gen_normal_fifo
+
+ // consider Depth == 1 case when $clog2(1) == 0
+ localparam int unsigned PTRV_W = $clog2(Depth) + ~|$clog2(Depth);
+ localparam int unsigned PTR_WIDTH = PTRV_W+1;
+
+ logic [PTR_WIDTH-1:0] fifo_wptr, fifo_rptr;
+ logic fifo_incr_wptr, fifo_incr_rptr, fifo_empty;
+
+ // create the write and read pointers
+ logic full, empty;
+ logic wptr_msb;
+ logic rptr_msb;
+ logic [PTRV_W-1:0] wptr_value;
+ logic [PTRV_W-1:0] rptr_value;
+
+ assign wptr_msb = fifo_wptr[PTR_WIDTH-1];
+ assign rptr_msb = fifo_rptr[PTR_WIDTH-1];
+ assign wptr_value = fifo_wptr[0+:PTRV_W];
+ assign rptr_value = fifo_rptr[0+:PTRV_W];
+ assign depth = (full) ? DepthW'(Depth) :
+ (wptr_msb == rptr_msb) ? DepthW'(wptr_value) - DepthW'(rptr_value) :
+ (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_value)) ;
+
+ assign fifo_incr_wptr = wvalid & wready;
+ assign fifo_incr_rptr = rvalid & rready;
+
+ assign wready = ~full;
+ assign rvalid = ~empty;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_wptr <= {(PTR_WIDTH){1'b0}};
+ end else if (clr_i) begin
+ fifo_wptr <= {(PTR_WIDTH){1'b0}};
+ end else if (fifo_incr_wptr) begin
+ if (fifo_wptr[PTR_WIDTH-2:0] == (Depth-1)) begin
+ fifo_wptr <= {~fifo_wptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}};
+ end else begin
+ fifo_wptr <= fifo_wptr + {{(PTR_WIDTH-1){1'b0}},1'b1};
+ end
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_rptr <= {(PTR_WIDTH){1'b0}};
+ end else if (clr_i) begin
+ fifo_rptr <= {(PTR_WIDTH){1'b0}};
+ end else if (fifo_incr_rptr) begin
+ if (fifo_rptr[PTR_WIDTH-2:0] == (Depth-1)) begin
+ fifo_rptr <= {~fifo_rptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}};
+ end else begin
+ fifo_rptr <= fifo_rptr + {{(PTR_WIDTH-1){1'b0}},1'b1};
+ end
+ end
+ end
+
+ assign full = (fifo_wptr == (fifo_rptr ^ {1'b1,{(PTR_WIDTH-1){1'b0}}}));
+ assign fifo_empty = (fifo_wptr == fifo_rptr);
+
+
+ // the generate blocks below are needed to avoid lint errors due to array indexing
+ // in the where the fifo only has one storage element
+ logic [Depth-1:0][Width-1:0] storage;
+ logic [Width-1:0] storage_rdata;
+ if (Depth == 1) begin : gen_depth_eq1
+ assign storage_rdata = storage[0];
+
+ always_ff @(posedge clk_i)
+ if (fifo_incr_wptr) begin
+ storage[0] <= wdata;
+ end
+ // fifo with more than one storage element
+ end else begin : gen_depth_gt1
+ assign storage_rdata = storage[fifo_rptr[PTR_WIDTH-2:0]];
+
+ always_ff @(posedge clk_i)
+ if (fifo_incr_wptr) begin
+ storage[fifo_wptr[PTR_WIDTH-2:0]] <= wdata;
+ end
+ end
+
+ logic [Width-1:0] rdata_int;
+ if (Pass == 1'b1) begin : gen_pass
+ assign rdata_int = (fifo_empty && wvalid) ? wdata : storage_rdata;
+ assign empty = fifo_empty & ~wvalid;
+ end else begin : gen_nopass
+ assign rdata_int = storage_rdata;
+ assign empty = fifo_empty;
+ end
+
+ if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
+ assign rdata = empty ? 'b0 : rdata_int;
+ end else begin : gen_no_output_zero
+ assign rdata = rdata_int;
+ end
+ end // block: gen_normal_fifo
+
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_flop_2sync.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_flop_2sync.sv
new file mode 100644
index 00000000..3665c804
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_flop_2sync.sv
@@ -0,0 +1,39 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is auto-generated.
+
+
+// This is to prevent AscentLint warnings in the generated
+// abstract prim wrapper. These warnings occur due to the .*
+// use. TODO: we may want to move these inline waivers
+// into a separate, generated waiver file for consistency.
+//ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
+module prim_flop_2sync
+
+#(
+
+ parameter int Width = 16,
+ localparam int WidthSubOne = Width-1, // temp work around #2679
+ parameter logic [WidthSubOne:0] ResetValue = '0
+
+) (
+ input clk_i, // receive clock
+ input rst_ni,
+ input [Width-1:0] d_i,
+ output logic [Width-1:0] q_o
+);
+
+ if (1) begin : gen_generic
+ prim_generic_flop_2sync #(
+ .ResetValue(ResetValue),
+ .Width(Width)
+ ) u_impl_generic (
+ .*
+ );
+
+ end
+
+endmodule
+//ri lint_check_on OUTPUT_NOT_DRIVEN INPUT_NOT_READ
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_generic_buf.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_generic_buf.sv
new file mode 100644
index 00000000..b2b4cb54
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_generic_buf.sv
@@ -0,0 +1,13 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+module prim_generic_buf (
+ input in_i,
+ output logic out_o
+);
+
+ assign out_o = in_i;
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_generic_flop.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_generic_flop.sv
new file mode 100644
index 00000000..8eacf015
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_generic_flop.sv
@@ -0,0 +1,26 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// `include "prim_assert.sv"
+
+module prim_generic_flop # (
+ parameter int Width = 1,
+ localparam int WidthSubOne = Width-1,
+ parameter logic [WidthSubOne:0] ResetValue = 0
+) (
+ input clk_i,
+ input rst_ni,
+ input [Width-1:0] d_i,
+ output logic [Width-1:0] q_o
+);
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ q_o <= ResetValue;
+ end else begin
+ q_o <= d_i;
+ end
+ end
+
+endmodule // prim_generic_flop
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_generic_flop_2sync.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_generic_flop_2sync.sv
new file mode 100644
index 00000000..fdd1358d
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_generic_flop_2sync.sv
@@ -0,0 +1,43 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Generic double-synchronizer flop
+// This may need to be moved to prim_generic if libraries have a specific cell
+// for synchronization
+
+module prim_generic_flop_2sync #(
+ parameter int Width = 16,
+ localparam int WidthSubOne = Width-1, // temp work around #2679
+ parameter logic [WidthSubOne:0] ResetValue = '0
+) (
+ input clk_i, // receive clock
+ input rst_ni,
+ input [Width-1:0] d_i,
+ output logic [Width-1:0] q_o
+);
+
+ logic [Width-1:0] intq;
+
+ prim_generic_flop #(
+ .Width(Width),
+ .ResetValue(ResetValue)
+ ) u_sync_1 (
+ .clk_i,
+ .rst_ni,
+ .d_i,
+ .q_o(intq)
+ );
+
+ prim_generic_flop #(
+ .Width(Width),
+ .ResetValue(ResetValue)
+ ) u_sync_2 (
+ .clk_i,
+ .rst_ni,
+ .d_i(intq),
+ .q_o
+ );
+
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_intr_hw.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_intr_hw.sv
new file mode 100644
index 00000000..be09a7c8
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_intr_hw.sv
@@ -0,0 +1,58 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Primitive interrupt handler. This assumes the existence of three
+// controller registers: INTR_ENABLE, INTR_STATE, INTR_TEST.
+// This module can be instantiated once per interrupt field, or
+// "bussified" with all fields of the interrupt vector.
+
+module prim_intr_hw # (
+ parameter int unsigned Width = 1,
+ parameter bit FlopOutput = 1
+) (
+ // event
+ input clk_i,
+ input rst_ni,
+ input [Width-1:0] event_intr_i,
+
+ // register interface
+ input [Width-1:0] reg2hw_intr_enable_q_i,
+ input [Width-1:0] reg2hw_intr_test_q_i,
+ input reg2hw_intr_test_qe_i,
+ input [Width-1:0] reg2hw_intr_state_q_i,
+ output hw2reg_intr_state_de_o,
+ output [Width-1:0] hw2reg_intr_state_d_o,
+
+ // outgoing interrupt
+ output logic [Width-1:0] intr_o
+);
+
+ logic [Width-1:0] new_event;
+ assign new_event =
+ (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
+ assign hw2reg_intr_state_de_o = |new_event;
+ // for scalar interrupts, this resolves to '1' with new event
+ // for vector interrupts, new events are OR'd in to existing interrupt state
+ assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i;
+
+ if (FlopOutput == 1) begin : gen_flop_intr_output
+ // flop the interrupt output
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intr_o <= '0;
+ end else begin
+ intr_o <= reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i;
+ end
+ end
+
+ end else begin : gen_intr_passthrough_output
+ logic unused_clk;
+ logic unused_rst_n;
+ assign unused_clk = clk_i;
+ assign unused_rst_n = rst_ni;
+ assign intr_o = reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i;
+ end
+
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_mubi_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_mubi_pkg.sv
new file mode 100644
index 00000000..e74dddc4
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_mubi_pkg.sv
@@ -0,0 +1,531 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/design/gen-mubi.py
+//
+// This package defines common multibit signal types, active high and active low values and
+// the corresponding functions to test whether the values are set or not.
+
+package prim_mubi_pkg;
+
+ //////////////////////////////////////////////
+ // 4 Bit Multibit Type and Functions //
+ //////////////////////////////////////////////
+
+ parameter int MuBi4Width = 4;
+ typedef enum logic [MuBi4Width-1:0] {
+ MuBi4True = 4'hA, // enabled
+ MuBi4False = 4'h5 // disabled
+ } mubi4_t;
+
+ // Test whether the value is supplied is one of the valid enumerations
+ function automatic logic mubi4_test_invalid(mubi4_t val);
+ return ~(val inside {MuBi4True, MuBi4False});
+ endfunction : mubi4_test_invalid
+
+ // Convert a 1 input value to a mubi output
+ function automatic mubi4_t mubi4_bool_to_mubi(logic val);
+ return (val ? MuBi4True : MuBi4False);
+ endfunction : mubi4_bool_to_mubi
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal True.
+ function automatic logic mubi4_test_true_strict(mubi4_t val);
+ return MuBi4True == val;
+ endfunction : mubi4_test_true_strict
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal False.
+ function automatic logic mubi4_test_false_strict(mubi4_t val);
+ return MuBi4False == val;
+ endfunction : mubi4_test_false_strict
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The loose version of this function interprets all
+ // values other than False as "enabled".
+ function automatic logic mubi4_test_true_loose(mubi4_t val);
+ return MuBi4False != val;
+ endfunction : mubi4_test_true_loose
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The loose version of this function interprets all
+ // values other than True as "disabled".
+ function automatic logic mubi4_test_false_loose(mubi4_t val);
+ return MuBi4True != val;
+ endfunction : mubi4_test_false_loose
+
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | act
+ // !act | act | act
+ // act | act | act
+ //
+ function automatic mubi4_t mubi4_or(mubi4_t a, mubi4_t b, mubi4_t act);
+ logic [MuBi4Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi4Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] || b_in[k];
+ end else begin
+ out[k] = a_in[k] && b_in[k];
+ end
+ end
+ return mubi4_t'(out);
+ endfunction : mubi4_or
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | !act
+ // !act | act | !act
+ // act | act | act
+ //
+ function automatic mubi4_t mubi4_and(mubi4_t a, mubi4_t b, mubi4_t act);
+ logic [MuBi4Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi4Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] && b_in[k];
+ end else begin
+ out[k] = a_in[k] || b_in[k];
+ end
+ end
+ return mubi4_t'(out);
+ endfunction : mubi4_and
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi4_t mubi4_or_hi(mubi4_t a, mubi4_t b);
+ return mubi4_or(a, b, MuBi4True);
+ endfunction : mubi4_or_hi
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi4_t mubi4_and_hi(mubi4_t a, mubi4_t b);
+ return mubi4_and(a, b, MuBi4True);
+ endfunction : mubi4_and_hi
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi4_t mubi4_or_lo(mubi4_t a, mubi4_t b);
+ return mubi4_or(a, b, MuBi4False);
+ endfunction : mubi4_or_lo
+
+ // Performs a logical AND operation between two multibit values.
+ // Tlos treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi4_t mubi4_and_lo(mubi4_t a, mubi4_t b);
+ return mubi4_and(a, b, MuBi4False);
+ endfunction : mubi4_and_lo
+
+ //////////////////////////////////////////////
+ // 8 Bit Multibit Type and Functions //
+ //////////////////////////////////////////////
+
+ parameter int MuBi8Width = 8;
+ typedef enum logic [MuBi8Width-1:0] {
+ MuBi8True = 8'h5A, // enabled
+ MuBi8False = 8'hA5 // disabled
+ } mubi8_t;
+
+ // Test whether the value is supplied is one of the valid enumerations
+ function automatic logic mubi8_test_invalid(mubi8_t val);
+ return ~(val inside {MuBi8True, MuBi8False});
+ endfunction : mubi8_test_invalid
+
+ // Convert a 1 input value to a mubi output
+ function automatic mubi8_t mubi8_bool_to_mubi(logic val);
+ return (val ? MuBi8True : MuBi8False);
+ endfunction : mubi8_bool_to_mubi
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal True.
+ function automatic logic mubi8_test_true_strict(mubi8_t val);
+ return MuBi8True == val;
+ endfunction : mubi8_test_true_strict
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal False.
+ function automatic logic mubi8_test_false_strict(mubi8_t val);
+ return MuBi8False == val;
+ endfunction : mubi8_test_false_strict
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The loose version of this function interprets all
+ // values other than False as "enabled".
+ function automatic logic mubi8_test_true_loose(mubi8_t val);
+ return MuBi8False != val;
+ endfunction : mubi8_test_true_loose
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The loose version of this function interprets all
+ // values other than True as "disabled".
+ function automatic logic mubi8_test_false_loose(mubi8_t val);
+ return MuBi8True != val;
+ endfunction : mubi8_test_false_loose
+
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | act
+ // !act | act | act
+ // act | act | act
+ //
+ function automatic mubi8_t mubi8_or(mubi8_t a, mubi8_t b, mubi8_t act);
+ logic [MuBi8Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi8Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] || b_in[k];
+ end else begin
+ out[k] = a_in[k] && b_in[k];
+ end
+ end
+ return mubi8_t'(out);
+ endfunction : mubi8_or
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | !act
+ // !act | act | !act
+ // act | act | act
+ //
+ function automatic mubi8_t mubi8_and(mubi8_t a, mubi8_t b, mubi8_t act);
+ logic [MuBi8Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi8Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] && b_in[k];
+ end else begin
+ out[k] = a_in[k] || b_in[k];
+ end
+ end
+ return mubi8_t'(out);
+ endfunction : mubi8_and
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi8_t mubi8_or_hi(mubi8_t a, mubi8_t b);
+ return mubi8_or(a, b, MuBi8True);
+ endfunction : mubi8_or_hi
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi8_t mubi8_and_hi(mubi8_t a, mubi8_t b);
+ return mubi8_and(a, b, MuBi8True);
+ endfunction : mubi8_and_hi
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi8_t mubi8_or_lo(mubi8_t a, mubi8_t b);
+ return mubi8_or(a, b, MuBi8False);
+ endfunction : mubi8_or_lo
+
+ // Performs a logical AND operation between two multibit values.
+ // Tlos treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi8_t mubi8_and_lo(mubi8_t a, mubi8_t b);
+ return mubi8_and(a, b, MuBi8False);
+ endfunction : mubi8_and_lo
+
+ //////////////////////////////////////////////
+ // 12 Bit Multibit Type and Functions //
+ //////////////////////////////////////////////
+
+ parameter int MuBi12Width = 12;
+ typedef enum logic [MuBi12Width-1:0] {
+ MuBi12True = 12'hA5A, // enabled
+ MuBi12False = 12'h5A5 // disabled
+ } mubi12_t;
+
+ // Test whether the value is supplied is one of the valid enumerations
+ function automatic logic mubi12_test_invalid(mubi12_t val);
+ return ~(val inside {MuBi12True, MuBi12False});
+ endfunction : mubi12_test_invalid
+
+ // Convert a 1 input value to a mubi output
+ function automatic mubi12_t mubi12_bool_to_mubi(logic val);
+ return (val ? MuBi12True : MuBi12False);
+ endfunction : mubi12_bool_to_mubi
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal True.
+ function automatic logic mubi12_test_true_strict(mubi12_t val);
+ return MuBi12True == val;
+ endfunction : mubi12_test_true_strict
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal False.
+ function automatic logic mubi12_test_false_strict(mubi12_t val);
+ return MuBi12False == val;
+ endfunction : mubi12_test_false_strict
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The loose version of this function interprets all
+ // values other than False as "enabled".
+ function automatic logic mubi12_test_true_loose(mubi12_t val);
+ return MuBi12False != val;
+ endfunction : mubi12_test_true_loose
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The loose version of this function interprets all
+ // values other than True as "disabled".
+ function automatic logic mubi12_test_false_loose(mubi12_t val);
+ return MuBi12True != val;
+ endfunction : mubi12_test_false_loose
+
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | act
+ // !act | act | act
+ // act | act | act
+ //
+ function automatic mubi12_t mubi12_or(mubi12_t a, mubi12_t b, mubi12_t act);
+ logic [MuBi12Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi12Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] || b_in[k];
+ end else begin
+ out[k] = a_in[k] && b_in[k];
+ end
+ end
+ return mubi12_t'(out);
+ endfunction : mubi12_or
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | !act
+ // !act | act | !act
+ // act | act | act
+ //
+ function automatic mubi12_t mubi12_and(mubi12_t a, mubi12_t b, mubi12_t act);
+ logic [MuBi12Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi12Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] && b_in[k];
+ end else begin
+ out[k] = a_in[k] || b_in[k];
+ end
+ end
+ return mubi12_t'(out);
+ endfunction : mubi12_and
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi12_t mubi12_or_hi(mubi12_t a, mubi12_t b);
+ return mubi12_or(a, b, MuBi12True);
+ endfunction : mubi12_or_hi
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi12_t mubi12_and_hi(mubi12_t a, mubi12_t b);
+ return mubi12_and(a, b, MuBi12True);
+ endfunction : mubi12_and_hi
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi12_t mubi12_or_lo(mubi12_t a, mubi12_t b);
+ return mubi12_or(a, b, MuBi12False);
+ endfunction : mubi12_or_lo
+
+ // Performs a logical AND operation between two multibit values.
+ // Tlos treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi12_t mubi12_and_lo(mubi12_t a, mubi12_t b);
+ return mubi12_and(a, b, MuBi12False);
+ endfunction : mubi12_and_lo
+
+ //////////////////////////////////////////////
+ // 16 Bit Multibit Type and Functions //
+ //////////////////////////////////////////////
+
+ parameter int MuBi16Width = 16;
+ typedef enum logic [MuBi16Width-1:0] {
+ MuBi16True = 16'h5A5A, // enabled
+ MuBi16False = 16'hA5A5 // disabled
+ } mubi16_t;
+
+ // Test whether the value is supplied is one of the valid enumerations
+ function automatic logic mubi16_test_invalid(mubi16_t val);
+ return ~(val inside {MuBi16True, MuBi16False});
+ endfunction : mubi16_test_invalid
+
+ // Convert a 1 input value to a mubi output
+ function automatic mubi16_t mubi16_bool_to_mubi(logic val);
+ return (val ? MuBi16True : MuBi16False);
+ endfunction : mubi16_bool_to_mubi
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal True.
+ function automatic logic mubi16_test_true_strict(mubi16_t val);
+ return MuBi16True == val;
+ endfunction : mubi16_test_true_strict
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal False.
+ function automatic logic mubi16_test_false_strict(mubi16_t val);
+ return MuBi16False == val;
+ endfunction : mubi16_test_false_strict
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The loose version of this function interprets all
+ // values other than False as "enabled".
+ function automatic logic mubi16_test_true_loose(mubi16_t val);
+ return MuBi16False != val;
+ endfunction : mubi16_test_true_loose
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The loose version of this function interprets all
+ // values other than True as "disabled".
+ function automatic logic mubi16_test_false_loose(mubi16_t val);
+ return MuBi16True != val;
+ endfunction : mubi16_test_false_loose
+
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | act
+ // !act | act | act
+ // act | act | act
+ //
+ function automatic mubi16_t mubi16_or(mubi16_t a, mubi16_t b, mubi16_t act);
+ logic [MuBi16Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi16Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] || b_in[k];
+ end else begin
+ out[k] = a_in[k] && b_in[k];
+ end
+ end
+ return mubi16_t'(out);
+ endfunction : mubi16_or
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | !act
+ // !act | act | !act
+ // act | act | act
+ //
+ function automatic mubi16_t mubi16_and(mubi16_t a, mubi16_t b, mubi16_t act);
+ logic [MuBi16Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi16Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] && b_in[k];
+ end else begin
+ out[k] = a_in[k] || b_in[k];
+ end
+ end
+ return mubi16_t'(out);
+ endfunction : mubi16_and
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi16_t mubi16_or_hi(mubi16_t a, mubi16_t b);
+ return mubi16_or(a, b, MuBi16True);
+ endfunction : mubi16_or_hi
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi16_t mubi16_and_hi(mubi16_t a, mubi16_t b);
+ return mubi16_and(a, b, MuBi16True);
+ endfunction : mubi16_and_hi
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi16_t mubi16_or_lo(mubi16_t a, mubi16_t b);
+ return mubi16_or(a, b, MuBi16False);
+ endfunction : mubi16_or_lo
+
+ // Performs a logical AND operation between two multibit values.
+ // Tlos treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi16_t mubi16_and_lo(mubi16_t a, mubi16_t b);
+ return mubi16_and(a, b, MuBi16False);
+ endfunction : mubi16_and_lo
+
+endpackage : prim_mubi_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_packer.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_packer.sv
new file mode 100644
index 00000000..5c940227
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_packer.sv
@@ -0,0 +1,228 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Combine InW data and write to OutW data if packed to full word or stop signal
+
+
+module prim_packer #(
+ parameter int InW = 32,
+ parameter int OutW = 32,
+ parameter int HintByteData = 0 // If 1, The input/output are byte granularity
+) (
+ input clk_i ,
+ input rst_ni,
+
+ input valid_i,
+ input [InW-1:0] data_i,
+ input [InW-1:0] mask_i,
+ output ready_o,
+
+ output logic valid_o,
+ output logic [OutW-1:0] data_o,
+ output logic [OutW-1:0] mask_o,
+ input ready_i,
+
+ input flush_i, // If 1, send out remnant and clear state
+ output logic flush_done_o
+);
+
+ localparam int Width = InW + OutW; // storage width
+ localparam int ConcatW = Width + InW; // Input concatenated width
+ localparam int PtrW = $clog2(ConcatW+1);
+ localparam int IdxW = $clog2(InW) + ~|$clog2(InW);
+
+ logic valid_next, ready_next;
+ logic [Width-1:0] stored_data, stored_mask;
+ logic [ConcatW-1:0] concat_data, concat_mask;
+ logic [ConcatW-1:0] shiftl_data, shiftl_mask;
+
+ logic [PtrW-1:0] pos, pos_next; // Current write position
+ logic [IdxW-1:0] lod_idx; // result of Leading One Detector
+ logic [$clog2(InW+1)-1:0] inmask_ones; // Counting Ones for mask_i
+
+ logic ack_in, ack_out;
+
+ logic flush_valid; // flush data out request
+ logic flush_done;
+
+ // Computing next position ==================================================
+ always_comb begin
+ // counting mask_i ones
+ inmask_ones = '0;
+ for (int i = 0 ; i < InW ; i++) begin
+ inmask_ones = inmask_ones + mask_i[i];
+ end
+ end
+
+ logic [PtrW-1:0] pos_with_input;
+
+ always_comb begin
+ pos_next = pos;
+ pos_with_input = pos + PtrW'(inmask_ones);
+
+ unique case ({ack_in, ack_out})
+ 2'b00: pos_next = pos;
+ 2'b01: pos_next = (pos <= OutW) ? '0 : pos - OutW;
+ 2'b10: pos_next = pos_with_input;
+ 2'b11: pos_next = (pos_with_input <= OutW) ? '0 : pos_with_input - OutW;
+ default: pos_next = pos;
+ endcase
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ pos <= '0;
+ end else if (flush_done) begin
+ pos <= '0;
+ end else begin
+ pos <= pos_next;
+ end
+ end
+ //---------------------------------------------------------------------------
+
+ // Leading one detector for mask_i
+ always_comb begin
+ lod_idx = 0;
+ for (int i = InW-1; i >= 0 ; i--) begin
+ if (mask_i[i] == 1'b1) begin
+ lod_idx = $unsigned(i);
+ end
+ end
+ end
+
+ assign ack_in = valid_i & ready_o;
+ assign ack_out = valid_o & ready_i;
+
+ // Data process =============================================================
+ // shiftl : Input data shifted into the current stored position
+ assign shiftl_data = (valid_i) ? Width'(data_i >> lod_idx) << pos : '0;
+ assign shiftl_mask = (valid_i) ? Width'(mask_i >> lod_idx) << pos : '0;
+
+ // concat : Merging stored and shiftl
+ assign concat_data = {{(InW){1'b0}}, stored_data & stored_mask} |
+ (shiftl_data & shiftl_mask);
+ assign concat_mask = {{(InW){1'b0}}, stored_mask} | shiftl_mask;
+
+ logic [Width-1:0] stored_data_next, stored_mask_next;
+
+ always_comb begin
+ unique case ({ack_in, ack_out})
+ 2'b00: begin
+ stored_data_next = stored_data;
+ stored_mask_next = stored_mask;
+ end
+ 2'b01: begin
+ // ack_out : shift the amount of OutW
+ stored_data_next = {{OutW{1'b0}}, stored_data[Width-1:OutW]};
+ stored_mask_next = {{OutW{1'b0}}, stored_mask[Width-1:OutW]};
+ end
+ 2'b10: begin
+ // ack_in : Store concat data
+ stored_data_next = concat_data[0+:Width];
+ stored_mask_next = concat_mask[0+:Width];
+ end
+ 2'b11: begin
+ // both : shift the concat_data
+ stored_data_next = concat_data[ConcatW-1:OutW];
+ stored_mask_next = concat_mask[ConcatW-1:OutW];
+ end
+ default: begin
+ stored_data_next = stored_data;
+ stored_mask_next = stored_mask;
+ end
+ endcase
+ end
+
+ // Store the data temporary if it doesn't exceed OutW
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ stored_data <= '0;
+ stored_mask <= '0;
+ end else if (flush_done) begin
+ stored_data <= '0;
+ stored_mask <= '0;
+ end else begin
+ stored_data <= stored_data_next;
+ stored_mask <= stored_mask_next;
+ end
+ end
+ //---------------------------------------------------------------------------
+
+ // flush handling
+ typedef enum logic {
+ FlushIdle,
+ FlushSend
+ } flush_st_e;
+ flush_st_e flush_st, flush_st_next;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ flush_st <= FlushIdle;
+ end else begin
+ flush_st <= flush_st_next;
+ end
+ end
+
+ always_comb begin
+ flush_st_next = FlushIdle;
+
+ flush_valid = 1'b0;
+ flush_done = 1'b0;
+
+ unique case (flush_st)
+ FlushIdle: begin
+ if (flush_i) begin
+ flush_st_next = FlushSend;
+ end else begin
+ flush_st_next = FlushIdle;
+ end
+ end
+
+ FlushSend: begin
+ if (pos == '0) begin
+ flush_st_next = FlushIdle;
+
+ flush_valid = 1'b0;
+ flush_done = 1'b1;
+ end else begin
+ flush_st_next = FlushSend;
+
+ flush_valid = 1'b1;
+ flush_done = 1'b0;
+ end
+ end
+ default: begin
+ flush_st_next = FlushIdle;
+
+ flush_valid = 1'b0;
+ flush_done = 1'b0;
+ end
+ endcase
+ end
+
+ assign flush_done_o = flush_done;
+
+
+ // Output signals ===========================================================
+ assign valid_next = (pos >= OutW) ? 1'b1 : flush_valid;
+
+ // storage space is InW + OutW. So technically, ready_o can be asserted even
+ // if `pos` is greater than OutW. But in order to do that, the logic should
+ // use `inmask_ones` value whether pos+inmask_ones is less than (InW+OutW)
+ // with `valid_i`. It creates a path from `valid_i` --> `ready_o`.
+ // It may create a timing loop in some modules that use `ready_o` to
+ // `valid_i` (which is not a good practice though)
+ assign ready_next = pos <= OutW;
+
+ // Output request
+ assign valid_o = valid_next;
+ assign data_o = stored_data[OutW-1:0];
+ assign mask_o = stored_mask[OutW-1:0];
+
+ // ready_o
+ assign ready_o = ready_next;
+ //---------------------------------------------------------------------------
+
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_pkg.sv
new file mode 100644
index 00000000..ebe38d11
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_pkg.sv
@@ -0,0 +1,18 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Constants for use in primitives
+//
+// This file is a stop-gap until the DV file list is generated by FuseSoC.
+// Its contents are taken from the file which would be generated by FuseSoC.
+// https://github.com/lowRISC/ibex/issues/893
+
+package prim_pkg;
+
+ // Implementation target specialization
+ typedef enum integer {
+ ImplGeneric,
+ ImplXilinx
+ } impl_e;
+endpackage : prim_pkg
\ No newline at end of file
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_ram_1p_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_ram_1p_pkg.sv
new file mode 100644
index 00000000..d4796292
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_ram_1p_pkg.sv
@@ -0,0 +1,20 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package prim_ram_1p_pkg;
+
+ typedef struct packed {
+ logic cfg_en;
+ logic [3:0] cfg;
+ } cfg_t;
+
+ typedef struct packed {
+ cfg_t ram_cfg; // configuration for ram
+ cfg_t rf_cfg; // configuration for regfile
+ } ram_1p_cfg_t;
+
+ parameter ram_1p_cfg_t RAM_1P_CFG_DEFAULT = '0;
+
+endpackage // prim_ram_1p_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_dec.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_dec.sv
new file mode 100644
index 00000000..a40a86cd
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_dec.sv
@@ -0,0 +1,62 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED decoder generated by util/design/secded_gen.py
+
+module prim_secded_inv_39_32_dec (
+ input [38:0] data_i,
+ output logic [31:0] data_o,
+ output logic [6:0] syndrome_o,
+ output logic [1:0] err_o
+);
+
+ always_comb begin : p_encode
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 39'h2A00000000) & 39'h012606BD25);
+ syndrome_o[1] = ^((data_i ^ 39'h2A00000000) & 39'h02DEBA8050);
+ syndrome_o[2] = ^((data_i ^ 39'h2A00000000) & 39'h04413D89AA);
+ syndrome_o[3] = ^((data_i ^ 39'h2A00000000) & 39'h0831234ED1);
+ syndrome_o[4] = ^((data_i ^ 39'h2A00000000) & 39'h10C2C1323B);
+ syndrome_o[5] = ^((data_i ^ 39'h2A00000000) & 39'h202DCC624C);
+ syndrome_o[6] = ^((data_i ^ 39'h2A00000000) & 39'h4098505586);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h19) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h54) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h61) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h34) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h1a) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h2a) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h38) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h49) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'hd) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h51) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h31) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h68) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h7) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'hb) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h25) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h26) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h46) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h70) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h32) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h2c) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h13) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h23) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h29) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h16) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h52) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+ end
+endmodule : prim_secded_inv_39_32_dec
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_enc.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_enc.sv
new file mode 100644
index 00000000..e59d4879
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_enc.sv
@@ -0,0 +1,23 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED encoder generated by util/design/secded_gen.py
+
+module prim_secded_inv_39_32_enc (
+ input [31:0] data_i,
+ output logic [38:0] data_o
+);
+
+ always_comb begin : p_encode
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h002606BD25);
+ data_o[33] = 1'b1 ^ ^(data_o & 39'h00DEBA8050);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00413D89AA);
+ data_o[35] = 1'b1 ^ ^(data_o & 39'h0031234ED1);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h00C2C1323B);
+ data_o[37] = 1'b1 ^ ^(data_o & 39'h002DCC624C);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h0098505586);
+ end
+
+endmodule : prim_secded_inv_39_32_enc
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_dec.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_dec.sv
new file mode 100644
index 00000000..6e34b502
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_dec.sv
@@ -0,0 +1,87 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED decoder generated by util/design/secded_gen.py
+
+module prim_secded_inv_64_57_dec (
+ input [63:0] data_i,
+ output logic [56:0] data_o,
+ output logic [6:0] syndrome_o,
+ output logic [1:0] err_o
+);
+
+ always_comb begin : p_encode
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 64'h5400000000000000) & 64'h0303FFF800007FFF);
+ syndrome_o[1] = ^((data_i ^ 64'h5400000000000000) & 64'h057C1FF801FF801F);
+ syndrome_o[2] = ^((data_i ^ 64'h5400000000000000) & 64'h09BDE1F87E0781E1);
+ syndrome_o[3] = ^((data_i ^ 64'h5400000000000000) & 64'h11DEEE3B8E388E22);
+ syndrome_o[4] = ^((data_i ^ 64'h5400000000000000) & 64'h21EF76CDB2C93244);
+ syndrome_o[5] = ^((data_i ^ 64'h5400000000000000) & 64'h41F7BB56D5525488);
+ syndrome_o[6] = ^((data_i ^ 64'h5400000000000000) & 64'h81FBDDA769A46910);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'hd) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h15) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h25) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h19) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h29) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h49) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h31) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h51) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h61) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'he) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h16) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h26) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h46) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h1a) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h2a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h4a) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h32) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h52) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h62) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h1c) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h2c) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h4c) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h34) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h54) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h64) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h38) ^ data_i[31];
+ data_o[32] = (syndrome_o == 7'h58) ^ data_i[32];
+ data_o[33] = (syndrome_o == 7'h68) ^ data_i[33];
+ data_o[34] = (syndrome_o == 7'h70) ^ data_i[34];
+ data_o[35] = (syndrome_o == 7'h1f) ^ data_i[35];
+ data_o[36] = (syndrome_o == 7'h2f) ^ data_i[36];
+ data_o[37] = (syndrome_o == 7'h4f) ^ data_i[37];
+ data_o[38] = (syndrome_o == 7'h37) ^ data_i[38];
+ data_o[39] = (syndrome_o == 7'h57) ^ data_i[39];
+ data_o[40] = (syndrome_o == 7'h67) ^ data_i[40];
+ data_o[41] = (syndrome_o == 7'h3b) ^ data_i[41];
+ data_o[42] = (syndrome_o == 7'h5b) ^ data_i[42];
+ data_o[43] = (syndrome_o == 7'h6b) ^ data_i[43];
+ data_o[44] = (syndrome_o == 7'h73) ^ data_i[44];
+ data_o[45] = (syndrome_o == 7'h3d) ^ data_i[45];
+ data_o[46] = (syndrome_o == 7'h5d) ^ data_i[46];
+ data_o[47] = (syndrome_o == 7'h6d) ^ data_i[47];
+ data_o[48] = (syndrome_o == 7'h75) ^ data_i[48];
+ data_o[49] = (syndrome_o == 7'h79) ^ data_i[49];
+ data_o[50] = (syndrome_o == 7'h3e) ^ data_i[50];
+ data_o[51] = (syndrome_o == 7'h5e) ^ data_i[51];
+ data_o[52] = (syndrome_o == 7'h6e) ^ data_i[52];
+ data_o[53] = (syndrome_o == 7'h76) ^ data_i[53];
+ data_o[54] = (syndrome_o == 7'h7a) ^ data_i[54];
+ data_o[55] = (syndrome_o == 7'h7c) ^ data_i[55];
+ data_o[56] = (syndrome_o == 7'h7f) ^ data_i[56];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+ end
+endmodule : prim_secded_inv_64_57_dec
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_enc.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_enc.sv
new file mode 100644
index 00000000..21caaa6b
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_enc.sv
@@ -0,0 +1,23 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED encoder generated by util/design/secded_gen.py
+
+module prim_secded_inv_64_57_enc (
+ input [56:0] data_i,
+ output logic [63:0] data_o
+);
+
+ always_comb begin : p_encode
+ data_o = 64'(data_i);
+ data_o[57] = 1'b0 ^ ^(data_o & 64'h0103FFF800007FFF);
+ data_o[58] = 1'b1 ^ ^(data_o & 64'h017C1FF801FF801F);
+ data_o[59] = 1'b0 ^ ^(data_o & 64'h01BDE1F87E0781E1);
+ data_o[60] = 1'b1 ^ ^(data_o & 64'h01DEEE3B8E388E22);
+ data_o[61] = 1'b0 ^ ^(data_o & 64'h01EF76CDB2C93244);
+ data_o[62] = 1'b1 ^ ^(data_o & 64'h01F7BB56D5525488);
+ data_o[63] = 1'b0 ^ ^(data_o & 64'h01FBDDA769A46910);
+ end
+
+endmodule : prim_secded_inv_64_57_enc
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_pkg.sv
new file mode 100644
index 00000000..5f227e6e
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_secded_pkg.sv
@@ -0,0 +1,1778 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED package generated by
+// util/design/secded_gen.py from util/design/data/secded_cfg.hjson
+
+package prim_secded_pkg;
+
+ typedef enum int {
+ SecdedNone,
+ Secded_22_16,
+ Secded_28_22,
+ Secded_39_32,
+ Secded_64_57,
+ Secded_72_64,
+ SecdedHamming_22_16,
+ SecdedHamming_39_32,
+ SecdedHamming_72_64,
+ SecdedHamming_76_68,
+ SecdedInv_22_16,
+ SecdedInv_28_22,
+ SecdedInv_39_32,
+ SecdedInv_64_57,
+ SecdedInv_72_64,
+ SecdedInvHamming_22_16,
+ SecdedInvHamming_39_32,
+ SecdedInvHamming_72_64,
+ SecdedInvHamming_76_68
+ } prim_secded_e;
+
+ function automatic int get_ecc_data_width(prim_secded_e ecc_type);
+ case (ecc_type)
+ Secded_22_16: return 16;
+ Secded_28_22: return 22;
+ Secded_39_32: return 32;
+ Secded_64_57: return 57;
+ Secded_72_64: return 64;
+ SecdedHamming_22_16: return 16;
+ SecdedHamming_39_32: return 32;
+ SecdedHamming_72_64: return 64;
+ SecdedHamming_76_68: return 68;
+ SecdedInv_22_16: return 16;
+ SecdedInv_28_22: return 22;
+ SecdedInv_39_32: return 32;
+ SecdedInv_64_57: return 57;
+ SecdedInv_72_64: return 64;
+ SecdedInvHamming_22_16: return 16;
+ SecdedInvHamming_39_32: return 32;
+ SecdedInvHamming_72_64: return 64;
+ SecdedInvHamming_76_68: return 68;
+ // Return a non-zero width to avoid VCS compile issues
+ default: return 32;
+ endcase
+ endfunction
+
+ function automatic int get_ecc_parity_width(prim_secded_e ecc_type);
+ case (ecc_type)
+ Secded_22_16: return 6;
+ Secded_28_22: return 6;
+ Secded_39_32: return 7;
+ Secded_64_57: return 7;
+ Secded_72_64: return 8;
+ SecdedHamming_22_16: return 6;
+ SecdedHamming_39_32: return 7;
+ SecdedHamming_72_64: return 8;
+ SecdedHamming_76_68: return 8;
+ SecdedInv_22_16: return 6;
+ SecdedInv_28_22: return 6;
+ SecdedInv_39_32: return 7;
+ SecdedInv_64_57: return 7;
+ SecdedInv_72_64: return 8;
+ SecdedInvHamming_22_16: return 6;
+ SecdedInvHamming_39_32: return 7;
+ SecdedInvHamming_72_64: return 8;
+ SecdedInvHamming_76_68: return 8;
+ default: return 0;
+ endcase
+ endfunction
+
+ parameter logic [5:0] Secded2216ZeroEcc = 6'h0;
+ parameter logic [21:0] Secded2216ZeroWord = 22'h0;
+
+ typedef struct packed {
+ logic [15:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_22_16_t;
+
+ parameter logic [5:0] Secded2822ZeroEcc = 6'h0;
+ parameter logic [27:0] Secded2822ZeroWord = 28'h0;
+
+ typedef struct packed {
+ logic [21:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_28_22_t;
+
+ parameter logic [6:0] Secded3932ZeroEcc = 7'h0;
+ parameter logic [38:0] Secded3932ZeroWord = 39'h0;
+
+ typedef struct packed {
+ logic [31:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_39_32_t;
+
+ parameter logic [6:0] Secded6457ZeroEcc = 7'h0;
+ parameter logic [63:0] Secded6457ZeroWord = 64'h0;
+
+ typedef struct packed {
+ logic [56:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_64_57_t;
+
+ parameter logic [7:0] Secded7264ZeroEcc = 8'h0;
+ parameter logic [71:0] Secded7264ZeroWord = 72'h0;
+
+ typedef struct packed {
+ logic [63:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_72_64_t;
+
+ parameter logic [5:0] SecdedHamming2216ZeroEcc = 6'h0;
+ parameter logic [21:0] SecdedHamming2216ZeroWord = 22'h0;
+
+ typedef struct packed {
+ logic [15:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_hamming_22_16_t;
+
+ parameter logic [6:0] SecdedHamming3932ZeroEcc = 7'h0;
+ parameter logic [38:0] SecdedHamming3932ZeroWord = 39'h0;
+
+ typedef struct packed {
+ logic [31:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_hamming_39_32_t;
+
+ parameter logic [7:0] SecdedHamming7264ZeroEcc = 8'h0;
+ parameter logic [71:0] SecdedHamming7264ZeroWord = 72'h0;
+
+ typedef struct packed {
+ logic [63:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_hamming_72_64_t;
+
+ parameter logic [7:0] SecdedHamming7668ZeroEcc = 8'h0;
+ parameter logic [75:0] SecdedHamming7668ZeroWord = 76'h0;
+
+ typedef struct packed {
+ logic [67:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_hamming_76_68_t;
+
+ parameter logic [5:0] SecdedInv2216ZeroEcc = 6'h2A;
+ parameter logic [21:0] SecdedInv2216ZeroWord = 22'h2A0000;
+
+ typedef struct packed {
+ logic [15:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_22_16_t;
+
+ parameter logic [5:0] SecdedInv2822ZeroEcc = 6'h2A;
+ parameter logic [27:0] SecdedInv2822ZeroWord = 28'hA800000;
+
+ typedef struct packed {
+ logic [21:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_28_22_t;
+
+ parameter logic [6:0] SecdedInv3932ZeroEcc = 7'h2A;
+ parameter logic [38:0] SecdedInv3932ZeroWord = 39'h2A00000000;
+
+ typedef struct packed {
+ logic [31:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_39_32_t;
+
+ parameter logic [6:0] SecdedInv6457ZeroEcc = 7'h2A;
+ parameter logic [63:0] SecdedInv6457ZeroWord = 64'h5400000000000000;
+
+ typedef struct packed {
+ logic [56:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_64_57_t;
+
+ parameter logic [7:0] SecdedInv7264ZeroEcc = 8'hAA;
+ parameter logic [71:0] SecdedInv7264ZeroWord = 72'hAA0000000000000000;
+
+ typedef struct packed {
+ logic [63:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_72_64_t;
+
+ parameter logic [5:0] SecdedInvHamming2216ZeroEcc = 6'h2A;
+ parameter logic [21:0] SecdedInvHamming2216ZeroWord = 22'h2A0000;
+
+ typedef struct packed {
+ logic [15:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_hamming_22_16_t;
+
+ parameter logic [6:0] SecdedInvHamming3932ZeroEcc = 7'h2A;
+ parameter logic [38:0] SecdedInvHamming3932ZeroWord = 39'h2A00000000;
+
+ typedef struct packed {
+ logic [31:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_hamming_39_32_t;
+
+ parameter logic [7:0] SecdedInvHamming7264ZeroEcc = 8'hAA;
+ parameter logic [71:0] SecdedInvHamming7264ZeroWord = 72'hAA0000000000000000;
+
+ typedef struct packed {
+ logic [63:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_hamming_72_64_t;
+
+ parameter logic [7:0] SecdedInvHamming7668ZeroEcc = 8'hAA;
+ parameter logic [75:0] SecdedInvHamming7668ZeroWord = 76'hAA00000000000000000;
+
+ typedef struct packed {
+ logic [67:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_hamming_76_68_t;
+
+ function automatic logic [21:0]
+ prim_secded_22_16_enc (logic [15:0] data_i);
+ logic [21:0] data_o;
+ data_o = 22'(data_i);
+ data_o[16] = 1'b0 ^ ^(data_o & 22'h00496E);
+ data_o[17] = 1'b0 ^ ^(data_o & 22'h00F20B);
+ data_o[18] = 1'b0 ^ ^(data_o & 22'h008ED8);
+ data_o[19] = 1'b0 ^ ^(data_o & 22'h007714);
+ data_o[20] = 1'b0 ^ ^(data_o & 22'h00ACA5);
+ data_o[21] = 1'b0 ^ ^(data_o & 22'h0011F3);
+ return data_o;
+ endfunction
+
+ function automatic secded_22_16_t
+ prim_secded_22_16_dec (logic [21:0] data_i);
+ logic [15:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_22_16_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 22'h01496E);
+ syndrome_o[1] = ^(data_i & 22'h02F20B);
+ syndrome_o[2] = ^(data_i & 22'h048ED8);
+ syndrome_o[3] = ^(data_i & 22'h087714);
+ syndrome_o[4] = ^(data_i & 22'h10ACA5);
+ syndrome_o[5] = ^(data_i & 22'h2011F3);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h32) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'h23) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h19) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h7) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'h2c) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h31) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h25) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h34) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h29) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'he) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'h1c) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h15) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h2a) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h1a) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'hb) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h16) ^ data_i[15];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [27:0]
+ prim_secded_28_22_enc (logic [21:0] data_i);
+ logic [27:0] data_o;
+ data_o = 28'(data_i);
+ data_o[22] = 1'b0 ^ ^(data_o & 28'h03003FF);
+ data_o[23] = 1'b0 ^ ^(data_o & 28'h010FC0F);
+ data_o[24] = 1'b0 ^ ^(data_o & 28'h0271C71);
+ data_o[25] = 1'b0 ^ ^(data_o & 28'h03B6592);
+ data_o[26] = 1'b0 ^ ^(data_o & 28'h03DAAA4);
+ data_o[27] = 1'b0 ^ ^(data_o & 28'h03ED348);
+ return data_o;
+ endfunction
+
+ function automatic secded_28_22_t
+ prim_secded_28_22_dec (logic [27:0] data_i);
+ logic [21:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_28_22_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 28'h07003FF);
+ syndrome_o[1] = ^(data_i & 28'h090FC0F);
+ syndrome_o[2] = ^(data_i & 28'h1271C71);
+ syndrome_o[3] = ^(data_i & 28'h23B6592);
+ syndrome_o[4] = ^(data_i & 28'h43DAAA4);
+ syndrome_o[5] = ^(data_i & 28'h83ED348);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'hd) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h25) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h19) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h29) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'h31) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'he) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h16) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h26) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h1a) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'h2a) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h32) ^ data_i[15];
+ data_o[16] = (syndrome_o == 6'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 6'h2c) ^ data_i[17];
+ data_o[18] = (syndrome_o == 6'h34) ^ data_i[18];
+ data_o[19] = (syndrome_o == 6'h38) ^ data_i[19];
+ data_o[20] = (syndrome_o == 6'h3b) ^ data_i[20];
+ data_o[21] = (syndrome_o == 6'h3d) ^ data_i[21];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [38:0]
+ prim_secded_39_32_enc (logic [31:0] data_i);
+ logic [38:0] data_o;
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h002606BD25);
+ data_o[33] = 1'b0 ^ ^(data_o & 39'h00DEBA8050);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00413D89AA);
+ data_o[35] = 1'b0 ^ ^(data_o & 39'h0031234ED1);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h00C2C1323B);
+ data_o[37] = 1'b0 ^ ^(data_o & 39'h002DCC624C);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h0098505586);
+ return data_o;
+ endfunction
+
+ function automatic secded_39_32_t
+ prim_secded_39_32_dec (logic [38:0] data_i);
+ logic [31:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_39_32_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 39'h012606BD25);
+ syndrome_o[1] = ^(data_i & 39'h02DEBA8050);
+ syndrome_o[2] = ^(data_i & 39'h04413D89AA);
+ syndrome_o[3] = ^(data_i & 39'h0831234ED1);
+ syndrome_o[4] = ^(data_i & 39'h10C2C1323B);
+ syndrome_o[5] = ^(data_i & 39'h202DCC624C);
+ syndrome_o[6] = ^(data_i & 39'h4098505586);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h19) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h54) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h61) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h34) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h1a) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h2a) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h38) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h49) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'hd) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h51) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h31) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h68) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h7) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'hb) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h25) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h26) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h46) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h70) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h32) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h2c) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h13) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h23) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h29) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h16) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h52) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [63:0]
+ prim_secded_64_57_enc (logic [56:0] data_i);
+ logic [63:0] data_o;
+ data_o = 64'(data_i);
+ data_o[57] = 1'b0 ^ ^(data_o & 64'h0103FFF800007FFF);
+ data_o[58] = 1'b0 ^ ^(data_o & 64'h017C1FF801FF801F);
+ data_o[59] = 1'b0 ^ ^(data_o & 64'h01BDE1F87E0781E1);
+ data_o[60] = 1'b0 ^ ^(data_o & 64'h01DEEE3B8E388E22);
+ data_o[61] = 1'b0 ^ ^(data_o & 64'h01EF76CDB2C93244);
+ data_o[62] = 1'b0 ^ ^(data_o & 64'h01F7BB56D5525488);
+ data_o[63] = 1'b0 ^ ^(data_o & 64'h01FBDDA769A46910);
+ return data_o;
+ endfunction
+
+ function automatic secded_64_57_t
+ prim_secded_64_57_dec (logic [63:0] data_i);
+ logic [56:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_64_57_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 64'h0303FFF800007FFF);
+ syndrome_o[1] = ^(data_i & 64'h057C1FF801FF801F);
+ syndrome_o[2] = ^(data_i & 64'h09BDE1F87E0781E1);
+ syndrome_o[3] = ^(data_i & 64'h11DEEE3B8E388E22);
+ syndrome_o[4] = ^(data_i & 64'h21EF76CDB2C93244);
+ syndrome_o[5] = ^(data_i & 64'h41F7BB56D5525488);
+ syndrome_o[6] = ^(data_i & 64'h81FBDDA769A46910);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'hd) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h15) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h25) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h19) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h29) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h49) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h31) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h51) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h61) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'he) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h16) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h26) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h46) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h1a) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h2a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h4a) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h32) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h52) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h62) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h1c) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h2c) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h4c) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h34) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h54) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h64) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h38) ^ data_i[31];
+ data_o[32] = (syndrome_o == 7'h58) ^ data_i[32];
+ data_o[33] = (syndrome_o == 7'h68) ^ data_i[33];
+ data_o[34] = (syndrome_o == 7'h70) ^ data_i[34];
+ data_o[35] = (syndrome_o == 7'h1f) ^ data_i[35];
+ data_o[36] = (syndrome_o == 7'h2f) ^ data_i[36];
+ data_o[37] = (syndrome_o == 7'h4f) ^ data_i[37];
+ data_o[38] = (syndrome_o == 7'h37) ^ data_i[38];
+ data_o[39] = (syndrome_o == 7'h57) ^ data_i[39];
+ data_o[40] = (syndrome_o == 7'h67) ^ data_i[40];
+ data_o[41] = (syndrome_o == 7'h3b) ^ data_i[41];
+ data_o[42] = (syndrome_o == 7'h5b) ^ data_i[42];
+ data_o[43] = (syndrome_o == 7'h6b) ^ data_i[43];
+ data_o[44] = (syndrome_o == 7'h73) ^ data_i[44];
+ data_o[45] = (syndrome_o == 7'h3d) ^ data_i[45];
+ data_o[46] = (syndrome_o == 7'h5d) ^ data_i[46];
+ data_o[47] = (syndrome_o == 7'h6d) ^ data_i[47];
+ data_o[48] = (syndrome_o == 7'h75) ^ data_i[48];
+ data_o[49] = (syndrome_o == 7'h79) ^ data_i[49];
+ data_o[50] = (syndrome_o == 7'h3e) ^ data_i[50];
+ data_o[51] = (syndrome_o == 7'h5e) ^ data_i[51];
+ data_o[52] = (syndrome_o == 7'h6e) ^ data_i[52];
+ data_o[53] = (syndrome_o == 7'h76) ^ data_i[53];
+ data_o[54] = (syndrome_o == 7'h7a) ^ data_i[54];
+ data_o[55] = (syndrome_o == 7'h7c) ^ data_i[55];
+ data_o[56] = (syndrome_o == 7'h7f) ^ data_i[56];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [71:0]
+ prim_secded_72_64_enc (logic [63:0] data_i);
+ logic [71:0] data_o;
+ data_o = 72'(data_i);
+ data_o[64] = 1'b0 ^ ^(data_o & 72'h00B9000000001FFFFF);
+ data_o[65] = 1'b0 ^ ^(data_o & 72'h005E00000FFFE0003F);
+ data_o[66] = 1'b0 ^ ^(data_o & 72'h0067003FF003E007C1);
+ data_o[67] = 1'b0 ^ ^(data_o & 72'h00CD0FC0F03C207842);
+ data_o[68] = 1'b0 ^ ^(data_o & 72'h00B671C711C4438884);
+ data_o[69] = 1'b0 ^ ^(data_o & 72'h00B5B65926488C9108);
+ data_o[70] = 1'b0 ^ ^(data_o & 72'h00CBDAAA4A91152210);
+ data_o[71] = 1'b0 ^ ^(data_o & 72'h007AED348D221A4420);
+ return data_o;
+ endfunction
+
+ function automatic secded_72_64_t
+ prim_secded_72_64_dec (logic [71:0] data_i);
+ logic [63:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_72_64_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 72'h01B9000000001FFFFF);
+ syndrome_o[1] = ^(data_i & 72'h025E00000FFFE0003F);
+ syndrome_o[2] = ^(data_i & 72'h0467003FF003E007C1);
+ syndrome_o[3] = ^(data_i & 72'h08CD0FC0F03C207842);
+ syndrome_o[4] = ^(data_i & 72'h10B671C711C4438884);
+ syndrome_o[5] = ^(data_i & 72'h20B5B65926488C9108);
+ syndrome_o[6] = ^(data_i & 72'h40CBDAAA4A91152210);
+ syndrome_o[7] = ^(data_i & 72'h807AED348D221A4420);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h83) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'hd) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h15) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h25) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h45) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h85) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h19) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h29) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h49) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h89) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h31) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h51) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h91) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h61) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'ha1) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'hc1) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h16) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h26) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h46) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h86) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'h1a) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'h2a) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'h8a) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'h32) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'h52) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'h92) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'h62) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha2) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'hc2) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'h1c) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'h2c) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'h4c) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'h8c) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'h34) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'h54) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'h94) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'h64) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'ha4) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hc4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'h38) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'h58) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'h98) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'h68) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'ha8) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hc8) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'h70) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hb0) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hd0) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'he0) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'h6d) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hd6) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'h3e) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hcb) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hb3) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hb5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hce) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'h79) ^ data_i[63];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [21:0]
+ prim_secded_hamming_22_16_enc (logic [15:0] data_i);
+ logic [21:0] data_o;
+ data_o = 22'(data_i);
+ data_o[16] = 1'b0 ^ ^(data_o & 22'h00AD5B);
+ data_o[17] = 1'b0 ^ ^(data_o & 22'h00366D);
+ data_o[18] = 1'b0 ^ ^(data_o & 22'h00C78E);
+ data_o[19] = 1'b0 ^ ^(data_o & 22'h0007F0);
+ data_o[20] = 1'b0 ^ ^(data_o & 22'h00F800);
+ data_o[21] = 1'b0 ^ ^(data_o & 22'h1FFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_hamming_22_16_t
+ prim_secded_hamming_22_16_dec (logic [21:0] data_i);
+ logic [15:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_hamming_22_16_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 22'h01AD5B);
+ syndrome_o[1] = ^(data_i & 22'h02366D);
+ syndrome_o[2] = ^(data_i & 22'h04C78E);
+ syndrome_o[3] = ^(data_i & 22'h0807F0);
+ syndrome_o[4] = ^(data_i & 22'h10F800);
+ syndrome_o[5] = ^(data_i & 22'h3FFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h23) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'h25) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h26) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h27) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'h29) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h2a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h2b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h2c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h2d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'h2e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'h2f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h31) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h32) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h33) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'h34) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h35) ^ data_i[15];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[5];
+ err_o[1] = |syndrome_o[4:0] & ~syndrome_o[5];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [38:0]
+ prim_secded_hamming_39_32_enc (logic [31:0] data_i);
+ logic [38:0] data_o;
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h0056AAAD5B);
+ data_o[33] = 1'b0 ^ ^(data_o & 39'h009B33366D);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00E3C3C78E);
+ data_o[35] = 1'b0 ^ ^(data_o & 39'h0003FC07F0);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h0003FFF800);
+ data_o[37] = 1'b0 ^ ^(data_o & 39'h00FC000000);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h3FFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_hamming_39_32_t
+ prim_secded_hamming_39_32_dec (logic [38:0] data_i);
+ logic [31:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_hamming_39_32_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 39'h0156AAAD5B);
+ syndrome_o[1] = ^(data_i & 39'h029B33366D);
+ syndrome_o[2] = ^(data_i & 39'h04E3C3C78E);
+ syndrome_o[3] = ^(data_i & 39'h0803FC07F0);
+ syndrome_o[4] = ^(data_i & 39'h1003FFF800);
+ syndrome_o[5] = ^(data_i & 39'h20FC000000);
+ syndrome_o[6] = ^(data_i & 39'h7FFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h43) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h45) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h46) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h47) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h49) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h4a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h4b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h4d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h4e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h4f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h51) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h52) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h53) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h54) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h55) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h56) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h57) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h58) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h59) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h5a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h5b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h5c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h5d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h5e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h5f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h61) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h63) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h64) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h65) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h66) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[6];
+ err_o[1] = |syndrome_o[5:0] & ~syndrome_o[6];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [71:0]
+ prim_secded_hamming_72_64_enc (logic [63:0] data_i);
+ logic [71:0] data_o;
+ data_o = 72'(data_i);
+ data_o[64] = 1'b0 ^ ^(data_o & 72'h00AB55555556AAAD5B);
+ data_o[65] = 1'b0 ^ ^(data_o & 72'h00CD9999999B33366D);
+ data_o[66] = 1'b0 ^ ^(data_o & 72'h00F1E1E1E1E3C3C78E);
+ data_o[67] = 1'b0 ^ ^(data_o & 72'h0001FE01FE03FC07F0);
+ data_o[68] = 1'b0 ^ ^(data_o & 72'h0001FFFE0003FFF800);
+ data_o[69] = 1'b0 ^ ^(data_o & 72'h0001FFFFFFFC000000);
+ data_o[70] = 1'b0 ^ ^(data_o & 72'h00FE00000000000000);
+ data_o[71] = 1'b0 ^ ^(data_o & 72'h7FFFFFFFFFFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_hamming_72_64_t
+ prim_secded_hamming_72_64_dec (logic [71:0] data_i);
+ logic [63:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_hamming_72_64_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 72'h01AB55555556AAAD5B);
+ syndrome_o[1] = ^(data_i & 72'h02CD9999999B33366D);
+ syndrome_o[2] = ^(data_i & 72'h04F1E1E1E1E3C3C78E);
+ syndrome_o[3] = ^(data_i & 72'h0801FE01FE03FC07F0);
+ syndrome_o[4] = ^(data_i & 72'h1001FFFE0003FFF800);
+ syndrome_o[5] = ^(data_i & 72'h2001FFFFFFFC000000);
+ syndrome_o[6] = ^(data_i & 72'h40FE00000000000000);
+ syndrome_o[7] = ^(data_i & 72'hFFFFFFFFFFFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h83) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'h85) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h86) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h87) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h89) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h8a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'h8b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h8c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h8d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h8e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h8f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h91) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h92) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h93) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h94) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h95) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h96) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h97) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h98) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'h99) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'h9a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'h9b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h9c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h9d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h9e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h9f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'ha1) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'ha2) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'ha3) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'ha4) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'ha5) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'ha6) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'ha7) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'ha8) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha9) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'haa) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'hab) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'hac) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'had) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'hae) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'haf) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'hb0) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'hb1) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'hb2) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'hb3) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hb4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'hb5) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'hb6) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'hb7) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'hb8) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'hb9) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hba) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'hbb) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hbc) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hbd) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'hbe) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'hbf) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hc1) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'hc2) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hc3) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hc4) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hc5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hc6) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'hc7) ^ data_i[63];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[7];
+ err_o[1] = |syndrome_o[6:0] & ~syndrome_o[7];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [75:0]
+ prim_secded_hamming_76_68_enc (logic [67:0] data_i);
+ logic [75:0] data_o;
+ data_o = 76'(data_i);
+ data_o[68] = 1'b0 ^ ^(data_o & 76'h00AAB55555556AAAD5B);
+ data_o[69] = 1'b0 ^ ^(data_o & 76'h00CCD9999999B33366D);
+ data_o[70] = 1'b0 ^ ^(data_o & 76'h000F1E1E1E1E3C3C78E);
+ data_o[71] = 1'b0 ^ ^(data_o & 76'h00F01FE01FE03FC07F0);
+ data_o[72] = 1'b0 ^ ^(data_o & 76'h00001FFFE0003FFF800);
+ data_o[73] = 1'b0 ^ ^(data_o & 76'h00001FFFFFFFC000000);
+ data_o[74] = 1'b0 ^ ^(data_o & 76'h00FFE00000000000000);
+ data_o[75] = 1'b0 ^ ^(data_o & 76'h7FFFFFFFFFFFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_hamming_76_68_t
+ prim_secded_hamming_76_68_dec (logic [75:0] data_i);
+ logic [67:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_hamming_76_68_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 76'h01AAB55555556AAAD5B);
+ syndrome_o[1] = ^(data_i & 76'h02CCD9999999B33366D);
+ syndrome_o[2] = ^(data_i & 76'h040F1E1E1E1E3C3C78E);
+ syndrome_o[3] = ^(data_i & 76'h08F01FE01FE03FC07F0);
+ syndrome_o[4] = ^(data_i & 76'h10001FFFE0003FFF800);
+ syndrome_o[5] = ^(data_i & 76'h20001FFFFFFFC000000);
+ syndrome_o[6] = ^(data_i & 76'h40FFE00000000000000);
+ syndrome_o[7] = ^(data_i & 76'hFFFFFFFFFFFFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h83) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'h85) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h86) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h87) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h89) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h8a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'h8b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h8c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h8d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h8e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h8f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h91) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h92) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h93) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h94) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h95) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h96) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h97) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h98) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'h99) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'h9a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'h9b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h9c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h9d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h9e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h9f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'ha1) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'ha2) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'ha3) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'ha4) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'ha5) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'ha6) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'ha7) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'ha8) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha9) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'haa) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'hab) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'hac) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'had) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'hae) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'haf) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'hb0) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'hb1) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'hb2) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'hb3) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hb4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'hb5) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'hb6) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'hb7) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'hb8) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'hb9) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hba) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'hbb) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hbc) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hbd) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'hbe) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'hbf) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hc1) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'hc2) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hc3) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hc4) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hc5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hc6) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'hc7) ^ data_i[63];
+ data_o[64] = (syndrome_o == 8'hc8) ^ data_i[64];
+ data_o[65] = (syndrome_o == 8'hc9) ^ data_i[65];
+ data_o[66] = (syndrome_o == 8'hca) ^ data_i[66];
+ data_o[67] = (syndrome_o == 8'hcb) ^ data_i[67];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[7];
+ err_o[1] = |syndrome_o[6:0] & ~syndrome_o[7];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [21:0]
+ prim_secded_inv_22_16_enc (logic [15:0] data_i);
+ logic [21:0] data_o;
+ data_o = 22'(data_i);
+ data_o[16] = 1'b0 ^ ^(data_o & 22'h00496E);
+ data_o[17] = 1'b1 ^ ^(data_o & 22'h00F20B);
+ data_o[18] = 1'b0 ^ ^(data_o & 22'h008ED8);
+ data_o[19] = 1'b1 ^ ^(data_o & 22'h007714);
+ data_o[20] = 1'b0 ^ ^(data_o & 22'h00ACA5);
+ data_o[21] = 1'b1 ^ ^(data_o & 22'h0011F3);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_22_16_t
+ prim_secded_inv_22_16_dec (logic [21:0] data_i);
+ logic [15:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_22_16_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 22'h2A0000) & 22'h01496E);
+ syndrome_o[1] = ^((data_i ^ 22'h2A0000) & 22'h02F20B);
+ syndrome_o[2] = ^((data_i ^ 22'h2A0000) & 22'h048ED8);
+ syndrome_o[3] = ^((data_i ^ 22'h2A0000) & 22'h087714);
+ syndrome_o[4] = ^((data_i ^ 22'h2A0000) & 22'h10ACA5);
+ syndrome_o[5] = ^((data_i ^ 22'h2A0000) & 22'h2011F3);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h32) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'h23) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h19) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h7) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'h2c) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h31) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h25) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h34) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h29) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'he) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'h1c) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h15) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h2a) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h1a) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'hb) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h16) ^ data_i[15];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [27:0]
+ prim_secded_inv_28_22_enc (logic [21:0] data_i);
+ logic [27:0] data_o;
+ data_o = 28'(data_i);
+ data_o[22] = 1'b0 ^ ^(data_o & 28'h03003FF);
+ data_o[23] = 1'b1 ^ ^(data_o & 28'h010FC0F);
+ data_o[24] = 1'b0 ^ ^(data_o & 28'h0271C71);
+ data_o[25] = 1'b1 ^ ^(data_o & 28'h03B6592);
+ data_o[26] = 1'b0 ^ ^(data_o & 28'h03DAAA4);
+ data_o[27] = 1'b1 ^ ^(data_o & 28'h03ED348);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_28_22_t
+ prim_secded_inv_28_22_dec (logic [27:0] data_i);
+ logic [21:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_28_22_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 28'hA800000) & 28'h07003FF);
+ syndrome_o[1] = ^((data_i ^ 28'hA800000) & 28'h090FC0F);
+ syndrome_o[2] = ^((data_i ^ 28'hA800000) & 28'h1271C71);
+ syndrome_o[3] = ^((data_i ^ 28'hA800000) & 28'h23B6592);
+ syndrome_o[4] = ^((data_i ^ 28'hA800000) & 28'h43DAAA4);
+ syndrome_o[5] = ^((data_i ^ 28'hA800000) & 28'h83ED348);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'hd) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h25) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h19) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h29) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'h31) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'he) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h16) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h26) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h1a) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'h2a) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h32) ^ data_i[15];
+ data_o[16] = (syndrome_o == 6'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 6'h2c) ^ data_i[17];
+ data_o[18] = (syndrome_o == 6'h34) ^ data_i[18];
+ data_o[19] = (syndrome_o == 6'h38) ^ data_i[19];
+ data_o[20] = (syndrome_o == 6'h3b) ^ data_i[20];
+ data_o[21] = (syndrome_o == 6'h3d) ^ data_i[21];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [38:0]
+ prim_secded_inv_39_32_enc (logic [31:0] data_i);
+ logic [38:0] data_o;
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h002606BD25);
+ data_o[33] = 1'b1 ^ ^(data_o & 39'h00DEBA8050);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00413D89AA);
+ data_o[35] = 1'b1 ^ ^(data_o & 39'h0031234ED1);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h00C2C1323B);
+ data_o[37] = 1'b1 ^ ^(data_o & 39'h002DCC624C);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h0098505586);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_39_32_t
+ prim_secded_inv_39_32_dec (logic [38:0] data_i);
+ logic [31:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_39_32_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 39'h2A00000000) & 39'h012606BD25);
+ syndrome_o[1] = ^((data_i ^ 39'h2A00000000) & 39'h02DEBA8050);
+ syndrome_o[2] = ^((data_i ^ 39'h2A00000000) & 39'h04413D89AA);
+ syndrome_o[3] = ^((data_i ^ 39'h2A00000000) & 39'h0831234ED1);
+ syndrome_o[4] = ^((data_i ^ 39'h2A00000000) & 39'h10C2C1323B);
+ syndrome_o[5] = ^((data_i ^ 39'h2A00000000) & 39'h202DCC624C);
+ syndrome_o[6] = ^((data_i ^ 39'h2A00000000) & 39'h4098505586);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h19) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h54) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h61) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h34) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h1a) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h2a) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h38) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h49) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'hd) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h51) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h31) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h68) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h7) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'hb) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h25) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h26) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h46) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h70) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h32) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h2c) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h13) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h23) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h29) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h16) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h52) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [63:0]
+ prim_secded_inv_64_57_enc (logic [56:0] data_i);
+ logic [63:0] data_o;
+ data_o = 64'(data_i);
+ data_o[57] = 1'b0 ^ ^(data_o & 64'h0103FFF800007FFF);
+ data_o[58] = 1'b1 ^ ^(data_o & 64'h017C1FF801FF801F);
+ data_o[59] = 1'b0 ^ ^(data_o & 64'h01BDE1F87E0781E1);
+ data_o[60] = 1'b1 ^ ^(data_o & 64'h01DEEE3B8E388E22);
+ data_o[61] = 1'b0 ^ ^(data_o & 64'h01EF76CDB2C93244);
+ data_o[62] = 1'b1 ^ ^(data_o & 64'h01F7BB56D5525488);
+ data_o[63] = 1'b0 ^ ^(data_o & 64'h01FBDDA769A46910);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_64_57_t
+ prim_secded_inv_64_57_dec (logic [63:0] data_i);
+ logic [56:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_64_57_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 64'h5400000000000000) & 64'h0303FFF800007FFF);
+ syndrome_o[1] = ^((data_i ^ 64'h5400000000000000) & 64'h057C1FF801FF801F);
+ syndrome_o[2] = ^((data_i ^ 64'h5400000000000000) & 64'h09BDE1F87E0781E1);
+ syndrome_o[3] = ^((data_i ^ 64'h5400000000000000) & 64'h11DEEE3B8E388E22);
+ syndrome_o[4] = ^((data_i ^ 64'h5400000000000000) & 64'h21EF76CDB2C93244);
+ syndrome_o[5] = ^((data_i ^ 64'h5400000000000000) & 64'h41F7BB56D5525488);
+ syndrome_o[6] = ^((data_i ^ 64'h5400000000000000) & 64'h81FBDDA769A46910);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'hd) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h15) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h25) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h19) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h29) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h49) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h31) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h51) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h61) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'he) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h16) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h26) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h46) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h1a) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h2a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h4a) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h32) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h52) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h62) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h1c) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h2c) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h4c) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h34) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h54) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h64) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h38) ^ data_i[31];
+ data_o[32] = (syndrome_o == 7'h58) ^ data_i[32];
+ data_o[33] = (syndrome_o == 7'h68) ^ data_i[33];
+ data_o[34] = (syndrome_o == 7'h70) ^ data_i[34];
+ data_o[35] = (syndrome_o == 7'h1f) ^ data_i[35];
+ data_o[36] = (syndrome_o == 7'h2f) ^ data_i[36];
+ data_o[37] = (syndrome_o == 7'h4f) ^ data_i[37];
+ data_o[38] = (syndrome_o == 7'h37) ^ data_i[38];
+ data_o[39] = (syndrome_o == 7'h57) ^ data_i[39];
+ data_o[40] = (syndrome_o == 7'h67) ^ data_i[40];
+ data_o[41] = (syndrome_o == 7'h3b) ^ data_i[41];
+ data_o[42] = (syndrome_o == 7'h5b) ^ data_i[42];
+ data_o[43] = (syndrome_o == 7'h6b) ^ data_i[43];
+ data_o[44] = (syndrome_o == 7'h73) ^ data_i[44];
+ data_o[45] = (syndrome_o == 7'h3d) ^ data_i[45];
+ data_o[46] = (syndrome_o == 7'h5d) ^ data_i[46];
+ data_o[47] = (syndrome_o == 7'h6d) ^ data_i[47];
+ data_o[48] = (syndrome_o == 7'h75) ^ data_i[48];
+ data_o[49] = (syndrome_o == 7'h79) ^ data_i[49];
+ data_o[50] = (syndrome_o == 7'h3e) ^ data_i[50];
+ data_o[51] = (syndrome_o == 7'h5e) ^ data_i[51];
+ data_o[52] = (syndrome_o == 7'h6e) ^ data_i[52];
+ data_o[53] = (syndrome_o == 7'h76) ^ data_i[53];
+ data_o[54] = (syndrome_o == 7'h7a) ^ data_i[54];
+ data_o[55] = (syndrome_o == 7'h7c) ^ data_i[55];
+ data_o[56] = (syndrome_o == 7'h7f) ^ data_i[56];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [71:0]
+ prim_secded_inv_72_64_enc (logic [63:0] data_i);
+ logic [71:0] data_o;
+ data_o = 72'(data_i);
+ data_o[64] = 1'b0 ^ ^(data_o & 72'h00B9000000001FFFFF);
+ data_o[65] = 1'b1 ^ ^(data_o & 72'h005E00000FFFE0003F);
+ data_o[66] = 1'b0 ^ ^(data_o & 72'h0067003FF003E007C1);
+ data_o[67] = 1'b1 ^ ^(data_o & 72'h00CD0FC0F03C207842);
+ data_o[68] = 1'b0 ^ ^(data_o & 72'h00B671C711C4438884);
+ data_o[69] = 1'b1 ^ ^(data_o & 72'h00B5B65926488C9108);
+ data_o[70] = 1'b0 ^ ^(data_o & 72'h00CBDAAA4A91152210);
+ data_o[71] = 1'b1 ^ ^(data_o & 72'h007AED348D221A4420);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_72_64_t
+ prim_secded_inv_72_64_dec (logic [71:0] data_i);
+ logic [63:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_72_64_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 72'hAA0000000000000000) & 72'h01B9000000001FFFFF);
+ syndrome_o[1] = ^((data_i ^ 72'hAA0000000000000000) & 72'h025E00000FFFE0003F);
+ syndrome_o[2] = ^((data_i ^ 72'hAA0000000000000000) & 72'h0467003FF003E007C1);
+ syndrome_o[3] = ^((data_i ^ 72'hAA0000000000000000) & 72'h08CD0FC0F03C207842);
+ syndrome_o[4] = ^((data_i ^ 72'hAA0000000000000000) & 72'h10B671C711C4438884);
+ syndrome_o[5] = ^((data_i ^ 72'hAA0000000000000000) & 72'h20B5B65926488C9108);
+ syndrome_o[6] = ^((data_i ^ 72'hAA0000000000000000) & 72'h40CBDAAA4A91152210);
+ syndrome_o[7] = ^((data_i ^ 72'hAA0000000000000000) & 72'h807AED348D221A4420);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h83) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'hd) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h15) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h25) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h45) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h85) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h19) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h29) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h49) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h89) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h31) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h51) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h91) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h61) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'ha1) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'hc1) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h16) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h26) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h46) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h86) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'h1a) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'h2a) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'h8a) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'h32) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'h52) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'h92) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'h62) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha2) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'hc2) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'h1c) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'h2c) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'h4c) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'h8c) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'h34) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'h54) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'h94) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'h64) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'ha4) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hc4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'h38) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'h58) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'h98) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'h68) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'ha8) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hc8) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'h70) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hb0) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hd0) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'he0) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'h6d) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hd6) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'h3e) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hcb) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hb3) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hb5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hce) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'h79) ^ data_i[63];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [21:0]
+ prim_secded_inv_hamming_22_16_enc (logic [15:0] data_i);
+ logic [21:0] data_o;
+ data_o = 22'(data_i);
+ data_o[16] = 1'b0 ^ ^(data_o & 22'h00AD5B);
+ data_o[17] = 1'b1 ^ ^(data_o & 22'h00366D);
+ data_o[18] = 1'b0 ^ ^(data_o & 22'h00C78E);
+ data_o[19] = 1'b1 ^ ^(data_o & 22'h0007F0);
+ data_o[20] = 1'b0 ^ ^(data_o & 22'h00F800);
+ data_o[21] = 1'b1 ^ ^(data_o & 22'h1FFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_hamming_22_16_t
+ prim_secded_inv_hamming_22_16_dec (logic [21:0] data_i);
+ logic [15:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_hamming_22_16_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 22'h2A0000) & 22'h01AD5B);
+ syndrome_o[1] = ^((data_i ^ 22'h2A0000) & 22'h02366D);
+ syndrome_o[2] = ^((data_i ^ 22'h2A0000) & 22'h04C78E);
+ syndrome_o[3] = ^((data_i ^ 22'h2A0000) & 22'h0807F0);
+ syndrome_o[4] = ^((data_i ^ 22'h2A0000) & 22'h10F800);
+ syndrome_o[5] = ^((data_i ^ 22'h2A0000) & 22'h3FFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h23) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'h25) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h26) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h27) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'h29) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h2a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h2b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h2c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h2d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'h2e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'h2f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h31) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h32) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h33) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'h34) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h35) ^ data_i[15];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[5];
+ err_o[1] = |syndrome_o[4:0] & ~syndrome_o[5];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [38:0]
+ prim_secded_inv_hamming_39_32_enc (logic [31:0] data_i);
+ logic [38:0] data_o;
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h0056AAAD5B);
+ data_o[33] = 1'b1 ^ ^(data_o & 39'h009B33366D);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00E3C3C78E);
+ data_o[35] = 1'b1 ^ ^(data_o & 39'h0003FC07F0);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h0003FFF800);
+ data_o[37] = 1'b1 ^ ^(data_o & 39'h00FC000000);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h3FFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_hamming_39_32_t
+ prim_secded_inv_hamming_39_32_dec (logic [38:0] data_i);
+ logic [31:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_hamming_39_32_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 39'h2A00000000) & 39'h0156AAAD5B);
+ syndrome_o[1] = ^((data_i ^ 39'h2A00000000) & 39'h029B33366D);
+ syndrome_o[2] = ^((data_i ^ 39'h2A00000000) & 39'h04E3C3C78E);
+ syndrome_o[3] = ^((data_i ^ 39'h2A00000000) & 39'h0803FC07F0);
+ syndrome_o[4] = ^((data_i ^ 39'h2A00000000) & 39'h1003FFF800);
+ syndrome_o[5] = ^((data_i ^ 39'h2A00000000) & 39'h20FC000000);
+ syndrome_o[6] = ^((data_i ^ 39'h2A00000000) & 39'h7FFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h43) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h45) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h46) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h47) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h49) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h4a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h4b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h4d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h4e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h4f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h51) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h52) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h53) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h54) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h55) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h56) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h57) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h58) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h59) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h5a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h5b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h5c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h5d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h5e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h5f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h61) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h63) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h64) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h65) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h66) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[6];
+ err_o[1] = |syndrome_o[5:0] & ~syndrome_o[6];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [71:0]
+ prim_secded_inv_hamming_72_64_enc (logic [63:0] data_i);
+ logic [71:0] data_o;
+ data_o = 72'(data_i);
+ data_o[64] = 1'b0 ^ ^(data_o & 72'h00AB55555556AAAD5B);
+ data_o[65] = 1'b1 ^ ^(data_o & 72'h00CD9999999B33366D);
+ data_o[66] = 1'b0 ^ ^(data_o & 72'h00F1E1E1E1E3C3C78E);
+ data_o[67] = 1'b1 ^ ^(data_o & 72'h0001FE01FE03FC07F0);
+ data_o[68] = 1'b0 ^ ^(data_o & 72'h0001FFFE0003FFF800);
+ data_o[69] = 1'b1 ^ ^(data_o & 72'h0001FFFFFFFC000000);
+ data_o[70] = 1'b0 ^ ^(data_o & 72'h00FE00000000000000);
+ data_o[71] = 1'b1 ^ ^(data_o & 72'h7FFFFFFFFFFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_hamming_72_64_t
+ prim_secded_inv_hamming_72_64_dec (logic [71:0] data_i);
+ logic [63:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_hamming_72_64_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 72'hAA0000000000000000) & 72'h01AB55555556AAAD5B);
+ syndrome_o[1] = ^((data_i ^ 72'hAA0000000000000000) & 72'h02CD9999999B33366D);
+ syndrome_o[2] = ^((data_i ^ 72'hAA0000000000000000) & 72'h04F1E1E1E1E3C3C78E);
+ syndrome_o[3] = ^((data_i ^ 72'hAA0000000000000000) & 72'h0801FE01FE03FC07F0);
+ syndrome_o[4] = ^((data_i ^ 72'hAA0000000000000000) & 72'h1001FFFE0003FFF800);
+ syndrome_o[5] = ^((data_i ^ 72'hAA0000000000000000) & 72'h2001FFFFFFFC000000);
+ syndrome_o[6] = ^((data_i ^ 72'hAA0000000000000000) & 72'h40FE00000000000000);
+ syndrome_o[7] = ^((data_i ^ 72'hAA0000000000000000) & 72'hFFFFFFFFFFFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h83) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'h85) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h86) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h87) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h89) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h8a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'h8b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h8c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h8d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h8e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h8f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h91) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h92) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h93) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h94) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h95) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h96) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h97) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h98) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'h99) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'h9a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'h9b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h9c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h9d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h9e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h9f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'ha1) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'ha2) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'ha3) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'ha4) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'ha5) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'ha6) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'ha7) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'ha8) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha9) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'haa) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'hab) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'hac) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'had) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'hae) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'haf) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'hb0) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'hb1) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'hb2) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'hb3) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hb4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'hb5) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'hb6) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'hb7) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'hb8) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'hb9) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hba) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'hbb) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hbc) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hbd) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'hbe) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'hbf) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hc1) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'hc2) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hc3) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hc4) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hc5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hc6) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'hc7) ^ data_i[63];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[7];
+ err_o[1] = |syndrome_o[6:0] & ~syndrome_o[7];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [75:0]
+ prim_secded_inv_hamming_76_68_enc (logic [67:0] data_i);
+ logic [75:0] data_o;
+ data_o = 76'(data_i);
+ data_o[68] = 1'b0 ^ ^(data_o & 76'h00AAB55555556AAAD5B);
+ data_o[69] = 1'b1 ^ ^(data_o & 76'h00CCD9999999B33366D);
+ data_o[70] = 1'b0 ^ ^(data_o & 76'h000F1E1E1E1E3C3C78E);
+ data_o[71] = 1'b1 ^ ^(data_o & 76'h00F01FE01FE03FC07F0);
+ data_o[72] = 1'b0 ^ ^(data_o & 76'h00001FFFE0003FFF800);
+ data_o[73] = 1'b1 ^ ^(data_o & 76'h00001FFFFFFFC000000);
+ data_o[74] = 1'b0 ^ ^(data_o & 76'h00FFE00000000000000);
+ data_o[75] = 1'b1 ^ ^(data_o & 76'h7FFFFFFFFFFFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_hamming_76_68_t
+ prim_secded_inv_hamming_76_68_dec (logic [75:0] data_i);
+ logic [67:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_hamming_76_68_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 76'hAA00000000000000000) & 76'h01AAB55555556AAAD5B);
+ syndrome_o[1] = ^((data_i ^ 76'hAA00000000000000000) & 76'h02CCD9999999B33366D);
+ syndrome_o[2] = ^((data_i ^ 76'hAA00000000000000000) & 76'h040F1E1E1E1E3C3C78E);
+ syndrome_o[3] = ^((data_i ^ 76'hAA00000000000000000) & 76'h08F01FE01FE03FC07F0);
+ syndrome_o[4] = ^((data_i ^ 76'hAA00000000000000000) & 76'h10001FFFE0003FFF800);
+ syndrome_o[5] = ^((data_i ^ 76'hAA00000000000000000) & 76'h20001FFFFFFFC000000);
+ syndrome_o[6] = ^((data_i ^ 76'hAA00000000000000000) & 76'h40FFE00000000000000);
+ syndrome_o[7] = ^((data_i ^ 76'hAA00000000000000000) & 76'hFFFFFFFFFFFFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h83) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'h85) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h86) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h87) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h89) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h8a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'h8b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h8c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h8d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h8e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h8f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h91) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h92) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h93) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h94) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h95) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h96) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h97) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h98) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'h99) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'h9a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'h9b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h9c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h9d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h9e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h9f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'ha1) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'ha2) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'ha3) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'ha4) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'ha5) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'ha6) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'ha7) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'ha8) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha9) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'haa) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'hab) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'hac) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'had) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'hae) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'haf) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'hb0) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'hb1) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'hb2) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'hb3) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hb4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'hb5) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'hb6) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'hb7) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'hb8) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'hb9) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hba) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'hbb) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hbc) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hbd) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'hbe) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'hbf) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hc1) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'hc2) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hc3) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hc4) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hc5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hc6) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'hc7) ^ data_i[63];
+ data_o[64] = (syndrome_o == 8'hc8) ^ data_i[64];
+ data_o[65] = (syndrome_o == 8'hc9) ^ data_i[65];
+ data_o[66] = (syndrome_o == 8'hca) ^ data_i[66];
+ data_o[67] = (syndrome_o == 8'hcb) ^ data_i[67];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[7];
+ err_o[1] = |syndrome_o[6:0] & ~syndrome_o[7];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+
+endpackage
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_subreg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_subreg.sv
new file mode 100644
index 00000000..a004090e
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_subreg.sv
@@ -0,0 +1,76 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register slice conforming to Comportibility guide.
+
+module prim_subreg #(
+ parameter int DW = 32 ,
+ parameter SwAccess = "RW", // {RW, RO, WO, W1C, W1S, W0C, RC}
+ parameter logic [DW-1:0] RESVAL = '0 // Reset value
+) (
+ input clk_i,
+ input rst_ni,
+
+ // From SW: valid for RW, WO, W1C, W1S, W0C, RC
+ // In case of RC, Top connects Read Pulse to we
+ input we,
+ input [DW-1:0] wd,
+
+ // From HW: valid for HRW, HWO
+ input de,
+ input [DW-1:0] d,
+
+ // output to HW and Reg Read
+ output logic qe,
+ output logic [DW-1:0] q,
+ output logic [DW-1:0] qs
+);
+
+ logic wr_en ;
+ logic [DW-1:0] wr_data;
+
+ if ((SwAccess == "RW") || (SwAccess == "WO")) begin : gen_w
+ assign wr_en = we | de ;
+ assign wr_data = (we == 1'b1) ? wd : d ; // SW higher priority
+ end else if (SwAccess == "RO") begin : gen_ro
+ // Unused we, wd
+ assign wr_en = de ;
+ assign wr_data = d ;
+ end else if (SwAccess == "W1S") begin : gen_w1s
+ // If SWACCESS is W1S, then assume hw tries to clear.
+ // So, give a chance HW to clear when SW tries to set.
+ // If both try to set/clr at the same bit pos, SW wins.
+ assign wr_en = we | de ;
+ assign wr_data = (de ? d : q) | (we ? wd : '0);
+ end else if (SwAccess == "W1C") begin : gen_w1c
+ // If SWACCESS is W1C, then assume hw tries to set.
+ // So, give a chance HW to set when SW tries to clear.
+ // If both try to set/clr at the same bit pos, SW wins.
+ assign wr_en = we | de ;
+ assign wr_data = (de ? d : q) & (we ? ~wd : '1);
+ end else if (SwAccess == "W0C") begin : gen_w0c
+ assign wr_en = we | de ;
+ assign wr_data = (de ? d : q) & (we ? wd : '1);
+ end else if (SwAccess == "RC") begin : gen_rc
+ // This swtype is not recommended but exists for compatibility.
+ // WARN: we signal is actually read signal not write enable.
+ assign wr_en = we | de ;
+ assign wr_data = (de ? d : q) & (we ? '0 : '1);
+ end else begin : gen_hw
+ assign wr_en = de ;
+ assign wr_data = d ;
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) qe <= 1'b0;
+ else qe <= we ;
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) q <= RESVAL ;
+ else if (wr_en) q <= wr_data;
+ end
+ assign qs = q;
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_subreg_ext.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_subreg_ext.sv
new file mode 100644
index 00000000..6db975d8
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_subreg_ext.sv
@@ -0,0 +1,28 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register slice conforming to Comportibility guide.
+
+module prim_subreg_ext #(
+ parameter int unsigned DW = 32
+) (
+ input re,
+ input we,
+ input [DW-1:0] wd,
+
+ input [DW-1:0] d,
+
+ // output to HW and Reg Read
+ output logic qe,
+ output logic qre,
+ output logic [DW-1:0] q,
+ output logic [DW-1:0] qs
+);
+
+ assign qs = d;
+ assign q = wd;
+ assign qe = we;
+ assign qre = re;
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_subreg_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_subreg_pkg.sv
new file mode 100644
index 00000000..b0988e45
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_subreg_pkg.sv
@@ -0,0 +1,17 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package prim_subreg_pkg;
+
+ // Register access specifier
+ typedef enum logic [2:0] {
+ SwAccessRW = 3'd0, // Read-write
+ SwAccessRO = 3'd1, // Read-only
+ SwAccessWO = 3'd2, // Write-only
+ SwAccessW1C = 3'd3, // Write 1 to clear
+ SwAccessW1S = 3'd4, // Write 1 to set
+ SwAccessW0C = 3'd5, // Write 0 to clear
+ SwAccessRC = 3'd6 // Read to clear. Do not use, only exists for compatibility.
+ } sw_access_e;
+endpackage
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_util_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_util_pkg.sv
new file mode 100644
index 00000000..536fa294
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/prim_util_pkg.sv
@@ -0,0 +1,89 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Utility functions
+ */
+package prim_util_pkg;
+ /**
+ * Math function: $clog2 as specified in Verilog-2005
+ *
+ * Do not use this function if $clog2() is available.
+ *
+ * clog2 = 0 for value == 0
+ * ceil(log2(value)) for value >= 1
+ *
+ * This implementation is a synthesizable variant of the $clog2 function as
+ * specified in the Verilog-2005 standard (IEEE 1364-2005).
+ *
+ * To quote the standard:
+ * The system function $clog2 shall return the ceiling of the log
+ * base 2 of the argument (the log rounded up to an integer
+ * value). The argument can be an integer or an arbitrary sized
+ * vector value. The argument shall be treated as an unsigned
+ * value, and an argument value of 0 shall produce a result of 0.
+ */
+ function automatic integer _clog2(integer value);
+ integer result;
+ // Use an intermediate value to avoid assigning to an input port, which produces a warning in
+ // Synopsys DC.
+ integer v = value;
+ v = v - 1;
+ for (result = 0; v > 0; result++) begin
+ v = v >> 1;
+ end
+ return result;
+ endfunction
+
+
+ /**
+ * Math function: Number of bits needed to address |value| items.
+ *
+ * 0 for value == 0
+ * vbits = 1 for value == 1
+ * ceil(log2(value)) for value > 1
+ *
+ *
+ * The primary use case for this function is the definition of registers/arrays
+ * which are wide enough to contain |value| items.
+ *
+ * This function identical to $clog2() for all input values except the value 1;
+ * it could be considered an "enhanced" $clog2() function.
+ *
+ *
+ * Example 1:
+ * parameter Items = 1;
+ * localparam ItemsWidth = vbits(Items); // 1
+ * logic [ItemsWidth-1:0] item_register; // items_register is now [0:0]
+ *
+ * Example 2:
+ * parameter Items = 64;
+ * localparam ItemsWidth = vbits(Items); // 6
+ * logic [ItemsWidth-1:0] item_register; // items_register is now [5:0]
+ *
+ * Note: If you want to store the number "value" inside a register, you need
+ * a register with size vbits(value + 1), since you also need to store
+ * the number 0.
+ *
+ * Example 3:
+ * logic [vbits(64)-1:0] store_64_logic_values; // width is [5:0]
+ * logic [vbits(64 + 1)-1:0] store_number_64; // width is [6:0]
+ */
+ function automatic integer vbits(integer value);
+
+
+
+
+
+
+
+
+
+
+ return (value == 1) ? 1 : $clog2(value);
+
+ endfunction
+
+endpackage
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/pwrmgr_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/pwrmgr_pkg.sv
new file mode 100644
index 00000000..002f6d7f
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/pwrmgr_pkg.sv
@@ -0,0 +1,274 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Power Manager Package
+//
+
+package pwrmgr_pkg;
+
+ // global constant
+ parameter int ALWAYS_ON_DOMAIN = 0;
+
+ // variables referenced by other modules / packages
+ parameter int PowerDomains = 2; // this needs to be a topgen populated number, or from topcfg?
+
+ // variables referenced only by pwrmgr
+ localparam int TotalWakeWidth = pwrmgr_reg_pkg::NumWkups + 2; // Abort and fall through are added
+
+ typedef enum logic [1:0] {
+ IntReqMainPwr,
+ IntReqEsc,
+ IntReqLastIdx
+ } pwr_int_rst_req_e;
+
+ parameter int NumSwRstReq = 1;
+
+ // position of escalation request
+ parameter int HwResetWidth = pwrmgr_reg_pkg::NumRstReqs + int'(IntReqLastIdx);
+ parameter int TotalResetWidth = HwResetWidth + NumSwRstReq;
+ parameter int ResetMainPwrIdx = pwrmgr_reg_pkg::NumRstReqs + int'(IntReqMainPwr);
+ parameter int ResetEscIdx = pwrmgr_reg_pkg::NumRstReqs + int'(IntReqEsc);
+ parameter int ResetSwReqIdx = TotalResetWidth - 1;
+
+ // pwrmgr to ast
+ typedef struct packed {
+ logic main_pd_n;
+ logic pwr_clamp_env;
+ logic pwr_clamp;
+ logic slow_clk_en;
+ logic core_clk_en;
+ logic io_clk_en;
+ logic usb_clk_en;
+ } pwr_ast_req_t;
+
+ typedef struct packed {
+ logic slow_clk_val;
+ logic core_clk_val;
+ logic io_clk_val;
+ logic usb_clk_val;
+ logic main_pok;
+ } pwr_ast_rsp_t;
+
+ // default value of pwr_ast_rsp (for dangling ports)
+ parameter pwr_ast_rsp_t PWR_AST_RSP_DEFAULT = '{
+ slow_clk_val: 1'b1,
+ core_clk_val: 1'b1,
+ io_clk_val: 1'b1,
+ usb_clk_val: 1'b1,
+ main_pok: 1'b1
+ };
+
+ parameter pwr_ast_rsp_t PWR_AST_RSP_SYNC_DEFAULT = '{
+ slow_clk_val: 1'b0,
+ core_clk_val: 1'b0,
+ io_clk_val: 1'b0,
+ usb_clk_val: 1'b0,
+ main_pok: 1'b0
+ };
+
+ // reasons for pwrmgr reset
+ typedef enum logic [1:0] {
+ ResetNone = 0, // there is no reset
+ LowPwrEntry = 1, // reset is caused by low power entry
+ HwReq = 2, // reset is caused by peripheral reset requests
+ ResetUndefined = 3 // this should never happen outside of POR
+ } reset_cause_e;
+
+ // pwrmgr to rstmgr
+ typedef struct packed {
+ logic [PowerDomains-1:0] rst_lc_req;
+ logic [PowerDomains-1:0] rst_sys_req;
+ logic [HwResetWidth-1:0] rstreqs;
+ reset_cause_e reset_cause;
+ } pwr_rst_req_t;
+
+ // rstmgr to pwrmgr
+ typedef struct packed {
+ logic [PowerDomains-1:0] rst_lc_src_n;
+ logic [PowerDomains-1:0] rst_sys_src_n;
+ } pwr_rst_rsp_t;
+
+ // default value (for dangling ports)
+ parameter pwr_rst_rsp_t PWR_RST_RSP_DEFAULT = '{
+ rst_lc_src_n: {PowerDomains{1'b1}},
+ rst_sys_src_n: {PowerDomains{1'b1}}
+ };
+
+ // pwrmgr to clkmgr
+ typedef struct packed {
+ logic main_ip_clk_en;
+ logic io_ip_clk_en;
+ logic usb_ip_clk_en;
+ } pwr_clk_req_t;
+
+ // clkmgr to pwrmgr
+ typedef struct packed {
+ logic main_status;
+ logic io_status;
+ logic usb_status;
+ } pwr_clk_rsp_t;
+
+ // pwrmgr to otp
+ typedef struct packed {
+ logic otp_init;
+ } pwr_otp_req_t;
+
+ // otp to pwrmgr
+ typedef struct packed {
+ logic otp_done;
+ logic otp_idle;
+ } pwr_otp_rsp_t;
+
+ // default value (for dangling ports)
+ parameter pwr_otp_rsp_t PWR_OTP_RSP_DEFAULT = '{
+ otp_done: 1'b1,
+ otp_idle: 1'b1
+ };
+
+ // pwrmgr to lifecycle
+ typedef struct packed {
+ logic lc_init;
+ } pwr_lc_req_t;
+
+ // lifecycle to pwrmgr
+ typedef struct packed {
+ logic lc_done;
+ logic lc_idle;
+ } pwr_lc_rsp_t;
+
+ // default value (for dangling ports)
+ parameter pwr_lc_rsp_t PWR_LC_RSP_DEFAULT = '{
+ lc_done: 1'b1,
+ lc_idle: 1'b1
+ };
+
+ typedef struct packed {
+ logic flash_idle;
+ } pwr_flash_t;
+
+ parameter pwr_flash_t PWR_FLASH_DEFAULT = '{
+ flash_idle: 1'b1
+ };
+
+ // processor to pwrmgr
+ typedef struct packed {
+ logic core_sleeping;
+ } pwr_cpu_t;
+
+ // default value (for dangling ports)
+ parameter pwr_cpu_t PWR_CPU_DEFAULT = '{
+ core_sleeping: 1'b0
+ };
+
+ // default value (for dangling ports)
+ parameter int WAKEUPS_DEFAULT = '0;
+ parameter int RSTREQS_DEFAULT = '0;
+
+ // peripherals to pwrmgr
+ typedef struct packed {
+ logic [pwrmgr_reg_pkg::NumWkups-1:0] wakeups;
+ // reset requests include external requests + escalation reset
+ logic [TotalResetWidth-1:0] rstreqs;
+ } pwr_peri_t;
+
+ // power-up causes
+ typedef enum logic [1:0] {
+ Por = 2'h0,
+ Wake = 2'h1,
+ Reset = 2'h2
+ } pwrup_cause_e;
+
+ // low power hints
+ typedef enum logic {
+ None = 1'b0,
+ LowPower = 1'b1
+ } low_power_hint_e;
+
+ // fast fsm state enum
+ // Encoding generated with:
+ // $ ./util/design/sparse-fsm-encode.py -d 5 -m 17 -n 12 \
+ // -s 4233784300 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: ||||||||||||||||| (30.15%)
+ // 6: |||||||||||||||||||| (35.29%)
+ // 7: |||||||||| (19.12%)
+ // 8: ||||| (9.56%)
+ // 9: | (2.21%)
+ // 10: | (2.21%)
+ // 11: (1.47%)
+ // 12: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 11
+ // Minimum Hamming weight: 3
+ // Maximum Hamming weight: 9
+ //
+ localparam int FastPwrStateWidth = 12;
+ typedef enum logic [FastPwrStateWidth-1:0] {
+ FastPwrStateLowPower = 12'b111010101011,
+ FastPwrStateEnableClocks = 12'b000011000010,
+ FastPwrStateReleaseLcRst = 12'b111011010110,
+ FastPwrStateOtpInit = 12'b100101011010,
+ FastPwrStateLcInit = 12'b010001111100,
+ FastPwrStateStrap = 12'b010110111010,
+ FastPwrStateAckPwrUp = 12'b010100100101,
+ FastPwrStateRomCheck = 12'b101100000011,
+ FastPwrStateActive = 12'b100001010101,
+ FastPwrStateDisClks = 12'b010000010011,
+ FastPwrStateFallThrough = 12'b111111011001,
+ FastPwrStateNvmIdleChk = 12'b001111110011,
+ FastPwrStateLowPowerPrep = 12'b011101001111,
+ FastPwrStateNvmShutDown = 12'b001010011111,
+ FastPwrStateResetPrep = 12'b101000110000,
+ FastPwrStateReqPwrDn = 12'b101101101100,
+ FastPwrStateInvalid = 12'b100010001100
+ } fast_pwr_state_e;
+
+ // Encoding generated with:
+ // $ ./util/design/sparse-fsm-encode.py -d 5 -m 12 -n 10 \
+ // -s 1726685338 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: |||||||||||||||||||| (54.55%)
+ // 6: |||||||||||||||| (45.45%)
+ // 7: --
+ // 8: --
+ // 9: --
+ // 10: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 6
+ // Minimum Hamming weight: 2
+ // Maximum Hamming weight: 8
+ //
+ localparam int SlowPwrStateWidth = 10;
+ typedef enum logic [SlowPwrStateWidth-1:0] {
+ SlowPwrStateReset = 10'b0000100010,
+ SlowPwrStateLowPower = 10'b1011000111,
+ SlowPwrStateMainPowerOn = 10'b0110101111,
+ SlowPwrStatePwrClampOff = 10'b0110010001,
+ SlowPwrStateClocksOn = 10'b1010111100,
+ SlowPwrStateReqPwrUp = 10'b0011011010,
+ SlowPwrStateIdle = 10'b1111100000,
+ SlowPwrStateAckPwrDn = 10'b0001110101,
+ SlowPwrStateClocksOff = 10'b1101111011,
+ SlowPwrStatePwrClampOn = 10'b0101001100,
+ SlowPwrStateMainPowerOff = 10'b1000001001,
+ SlowPwrStateInvalid = 10'b1100010110
+ } slow_pwr_state_e;
+
+endpackage // pwrmgr_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/pwrmgr_reg_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/pwrmgr_reg_pkg.sv
new file mode 100644
index 00000000..ef381aa9
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/pwrmgr_reg_pkg.sv
@@ -0,0 +1,217 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package pwrmgr_reg_pkg;
+
+ // Param list
+ parameter int NumWkups = 1;
+ parameter int NumRstReqs = 1;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } pwrmgr_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } low_power_hint;
+ struct packed {
+ logic q;
+ } core_clk_en;
+ struct packed {
+ logic q;
+ } io_clk_en;
+ struct packed {
+ logic q;
+ } usb_clk_en_lp;
+ struct packed {
+ logic q;
+ } usb_clk_en_active;
+ struct packed {
+ logic q;
+ } main_pd_n;
+ } pwrmgr_reg2hw_control_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } pwrmgr_reg2hw_cfg_cdc_sync_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_wakeup_en_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_reset_en_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_wake_info_capture_dis_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } reasons;
+ struct packed {
+ logic q;
+ logic qe;
+ } fall_through;
+ struct packed {
+ logic q;
+ logic qe;
+ } abort;
+ } pwrmgr_reg2hw_wake_info_reg_t;
+
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ logic d;
+ } pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } low_power_hint;
+ } pwrmgr_hw2reg_control_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_cfg_cdc_sync_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_wake_status_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_reset_status_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_escalate_reset_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ } reasons;
+ struct packed {
+ logic d;
+ } fall_through;
+ struct packed {
+ logic d;
+ } abort;
+ } pwrmgr_hw2reg_wake_info_reg_t;
+
+
+ ///////////////////////////////////////
+ // Register to internal design logic //
+ ///////////////////////////////////////
+ typedef struct packed {
+ pwrmgr_reg2hw_intr_state_reg_t intr_state; // [20:20]
+ pwrmgr_reg2hw_intr_enable_reg_t intr_enable; // [19:19]
+ pwrmgr_reg2hw_intr_test_reg_t intr_test; // [18:17]
+ pwrmgr_reg2hw_control_reg_t control; // [16:11]
+ pwrmgr_reg2hw_cfg_cdc_sync_reg_t cfg_cdc_sync; // [10:9]
+ pwrmgr_reg2hw_wakeup_en_mreg_t [0:0] wakeup_en; // [8:8]
+ pwrmgr_reg2hw_reset_en_mreg_t [0:0] reset_en; // [7:7]
+ pwrmgr_reg2hw_wake_info_capture_dis_reg_t wake_info_capture_dis; // [6:6]
+ pwrmgr_reg2hw_wake_info_reg_t wake_info; // [5:0]
+ } pwrmgr_reg2hw_t;
+
+ ///////////////////////////////////////
+ // Internal design logic to register //
+ ///////////////////////////////////////
+ typedef struct packed {
+ pwrmgr_hw2reg_intr_state_reg_t intr_state; // [15:14]
+ pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t ctrl_cfg_regwen; // [13:13]
+ pwrmgr_hw2reg_control_reg_t control; // [12:11]
+ pwrmgr_hw2reg_cfg_cdc_sync_reg_t cfg_cdc_sync; // [10:9]
+ pwrmgr_hw2reg_wake_status_mreg_t [0:0] wake_status; // [8:7]
+ pwrmgr_hw2reg_reset_status_mreg_t [0:0] reset_status; // [6:5]
+ pwrmgr_hw2reg_escalate_reset_status_reg_t escalate_reset_status; // [4:3]
+ pwrmgr_hw2reg_wake_info_reg_t wake_info; // [2:0]
+ } pwrmgr_hw2reg_t;
+
+ // Register Address
+ parameter logic [5:0] PWRMGR_INTR_STATE_OFFSET = 6'h0;
+ parameter logic [5:0] PWRMGR_INTR_ENABLE_OFFSET = 6'h4;
+ parameter logic [5:0] PWRMGR_INTR_TEST_OFFSET = 6'h8;
+ parameter logic [5:0] PWRMGR_CTRL_CFG_REGWEN_OFFSET = 6'hc;
+ parameter logic [5:0] PWRMGR_CONTROL_OFFSET = 6'h10;
+ parameter logic [5:0] PWRMGR_CFG_CDC_SYNC_OFFSET = 6'h14;
+ parameter logic [5:0] PWRMGR_WAKEUP_EN_REGWEN_OFFSET = 6'h18;
+ parameter logic [5:0] PWRMGR_WAKEUP_EN_OFFSET = 6'h1c;
+ parameter logic [5:0] PWRMGR_WAKE_STATUS_OFFSET = 6'h20;
+ parameter logic [5:0] PWRMGR_RESET_EN_REGWEN_OFFSET = 6'h24;
+ parameter logic [5:0] PWRMGR_RESET_EN_OFFSET = 6'h28;
+ parameter logic [5:0] PWRMGR_RESET_STATUS_OFFSET = 6'h2c;
+ parameter logic [5:0] PWRMGR_ESCALATE_RESET_STATUS_OFFSET = 6'h30;
+ parameter logic [5:0] PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET = 6'h34;
+ parameter logic [5:0] PWRMGR_WAKE_INFO_OFFSET = 6'h38;
+
+
+ // Register Index
+ typedef enum int {
+ PWRMGR_INTR_STATE,
+ PWRMGR_INTR_ENABLE,
+ PWRMGR_INTR_TEST,
+ PWRMGR_CTRL_CFG_REGWEN,
+ PWRMGR_CONTROL,
+ PWRMGR_CFG_CDC_SYNC,
+ PWRMGR_WAKEUP_EN_REGWEN,
+ PWRMGR_WAKEUP_EN,
+ PWRMGR_WAKE_STATUS,
+ PWRMGR_RESET_EN_REGWEN,
+ PWRMGR_RESET_EN,
+ PWRMGR_RESET_STATUS,
+ PWRMGR_ESCALATE_RESET_STATUS,
+ PWRMGR_WAKE_INFO_CAPTURE_DIS,
+ PWRMGR_WAKE_INFO
+ } pwrmgr_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] PWRMGR_PERMIT [15] = '{
+ 4'b0001, // index[ 0] PWRMGR_INTR_STATE
+ 4'b0001, // index[ 1] PWRMGR_INTR_ENABLE
+ 4'b0001, // index[ 2] PWRMGR_INTR_TEST
+ 4'b0001, // index[ 3] PWRMGR_CTRL_CFG_REGWEN
+ 4'b0011, // index[ 4] PWRMGR_CONTROL
+ 4'b0001, // index[ 5] PWRMGR_CFG_CDC_SYNC
+ 4'b0001, // index[ 6] PWRMGR_WAKEUP_EN_REGWEN
+ 4'b0001, // index[ 7] PWRMGR_WAKEUP_EN
+ 4'b0001, // index[ 8] PWRMGR_WAKE_STATUS
+ 4'b0001, // index[ 9] PWRMGR_RESET_EN_REGWEN
+ 4'b0001, // index[10] PWRMGR_RESET_EN
+ 4'b0001, // index[11] PWRMGR_RESET_STATUS
+ 4'b0001, // index[12] PWRMGR_ESCALATE_RESET_STATUS
+ 4'b0001, // index[13] PWRMGR_WAKE_INFO_CAPTURE_DIS
+ 4'b0001 // index[14] PWRMGR_WAKE_INFO
+ };
+endpackage
+
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/sha2.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/sha2.sv
new file mode 100644
index 00000000..0779c22d
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/sha2.sv
@@ -0,0 +1,323 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SHA-256 algorithm
+//
+
+module sha2 import hmac_pkg::*; (
+ input clk_i,
+ input rst_ni,
+
+ input wipe_secret,
+ input sha_word_t wipe_v,
+
+ // FIFO read signal
+ input fifo_rvalid,
+ input sha_fifo_t fifo_rdata,
+ output logic fifo_rready,
+
+ // Control signals
+ input sha_en, // If disabled, it clears internal content.
+ input hash_start,
+ input hash_process,
+ output logic hash_done,
+
+ input [63:0] message_length, // bits but byte based
+ output sha_word_t [7:0] digest,
+
+ output logic idle
+);
+
+ localparam int unsigned RoundWidth = $clog2(NumRound);
+
+ logic msg_feed_complete;
+
+ logic shaf_rready;
+ sha_word_t shaf_rdata;
+ logic shaf_rvalid;
+
+ logic [RoundWidth-1:0] round;
+
+ logic [3:0] w_index;
+ sha_word_t [15:0] w;
+
+ localparam sha_word_t ZeroWord = '0;
+
+ // w, hash, digest update logic control signals
+ logic update_w_from_fifo, calculate_next_w;
+ logic init_hash, run_hash, complete_one_chunk;
+ logic update_digest, clear_digest;
+
+ logic hash_done_next; // to meet the phase with digest value.
+
+ sha_word_t [7:0] hash; // a,b,c,d,e,f,g,h
+
+ // Fill up w
+ always_ff @(posedge clk_i or negedge rst_ni) begin : fill_w
+ if (!rst_ni) begin
+ w <= '0;
+ end else if (wipe_secret) begin
+ w <= w ^ {16{wipe_v}};
+ end else if (!sha_en) begin
+ w <= '0;
+ end else if (!run_hash && update_w_from_fifo) begin
+ // this logic runs at the first stage of SHA.
+ w <= {shaf_rdata, w[15:1]};
+ end else if (calculate_next_w) begin
+ w <= {calc_w(w[0], w[1], w[9], w[14]), w[15:1]};
+ //end else if (run_hash && update_w_from_fifo) begin
+ // // This code runs when round is in [48, 63]. At this time, it reads from the fifo
+ // // to fill the register if available. If FIFO goes to empty, w_index doesn't increase
+ // // and it cannot reach 15. Then the sha engine doesn't start, which introduces latency.
+ // //
+ // // But in this case, still w should be shifted to feed SHA compress engine. Then
+ // // fifo_rdata should be inserted in the middle of w index.
+ // // w[64-round + w_index] <= fifo_rdata;
+ // for (int i = 0 ; i < 16 ; i++) begin
+ // if (i == (64 - round + w_index)) begin
+ // w[i] <= shaf_rdata;
+ // end else if (i == 15) begin
+ // w[i] <= '0;
+ // end else begin
+ // w[i] <= w[i+1];
+ // end
+ // end
+ end else if (run_hash) begin
+ // Just shift-out. There's no incoming data
+ w <= {ZeroWord, w[15:1]};
+ end
+ end : fill_w
+
+ // Update engine
+ always_ff @(posedge clk_i or negedge rst_ni) begin : compress_round
+ if (!rst_ni) begin
+ hash <= '{default:'0};
+ end else if (wipe_secret) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ hash[i] <= hash[i] ^ wipe_v;
+ end
+ end else if (init_hash) begin
+ hash <= digest;
+ end else if (run_hash) begin
+ hash <= compress( w[0], CubicRootPrime[round], hash);
+ end
+ end : compress_round
+
+ // Digest
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ digest <= '{default: '0};
+ end else if (wipe_secret) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ digest[i] <= digest[i] ^ wipe_v;
+ end
+ end else if (hash_start) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ digest[i] <= InitHash[i];
+ end
+ end else if (!sha_en || clear_digest) begin
+ digest <= '0;
+ end else if (update_digest) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ digest[i] <= digest[i] + hash[i];
+ end
+ end
+ end
+
+ // round
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ round <= '0;
+ end else if (!sha_en) begin
+ round <= '0;
+ end else if (run_hash) begin
+ if (round == RoundWidth'(unsigned'(NumRound-1))) begin
+ round <= '0;
+ end else begin
+ round <= round + 1;
+ end
+ end
+ end
+
+ // w_index
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ w_index <= '0;
+ end else if (!sha_en) begin
+ w_index <= '0;
+ end else if (update_w_from_fifo) begin
+ w_index <= w_index + 1;
+ end
+ end
+
+ assign shaf_rready = update_w_from_fifo;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) hash_done <= 1'b0;
+ else hash_done <= hash_done_next;
+ end
+
+ typedef enum logic [1:0] {
+ FifoIdle,
+ FifoLoadFromFifo,
+ FifoWait
+ } fifoctl_state_e;
+
+ fifoctl_state_e fifo_st_q, fifo_st_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_st_q <= FifoIdle;
+ end else begin
+ fifo_st_q <= fifo_st_d;
+ end
+ end
+
+ always_comb begin
+ fifo_st_d = FifoIdle;
+ update_w_from_fifo = 1'b0;
+ hash_done_next = 1'b0;
+
+ unique case (fifo_st_q)
+ FifoIdle: begin
+ if (hash_start) begin
+ fifo_st_d = FifoLoadFromFifo;
+ end else begin
+ fifo_st_d = FifoIdle;
+ end
+ end
+
+ FifoLoadFromFifo: begin
+ if (!sha_en) begin
+ fifo_st_d = FifoIdle;
+ update_w_from_fifo = 1'b0;
+ end else if (!shaf_rvalid) begin
+ // Wait until it is filled
+ fifo_st_d = FifoLoadFromFifo;
+ update_w_from_fifo = 1'b0;
+ end else if (w_index == 4'd15) begin
+ fifo_st_d = FifoWait;
+ update_w_from_fifo = 1'b1;
+ end else begin
+ fifo_st_d = FifoLoadFromFifo;
+ update_w_from_fifo = 1'b1;
+ end
+ end
+
+ FifoWait: begin
+ // Wait until next fetch begins (begin at round == 48)a
+ if (msg_feed_complete && complete_one_chunk) begin
+ fifo_st_d = FifoIdle;
+
+ hash_done_next = 1'b1;
+ end else if (complete_one_chunk) begin
+ fifo_st_d = FifoLoadFromFifo;
+ end else begin
+ fifo_st_d = FifoWait;
+ end
+ end
+
+ default: begin
+ fifo_st_d = FifoIdle;
+ end
+ endcase
+ end
+
+ // SHA control
+ typedef enum logic [1:0] {
+ ShaIdle,
+ ShaCompress,
+ ShaUpdateDigest
+ } sha_st_t;
+
+ sha_st_t sha_st_q, sha_st_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ sha_st_q <= ShaIdle;
+ end else begin
+ sha_st_q <= sha_st_d;
+ end
+ end
+
+ assign clear_digest = hash_start;
+
+ always_comb begin
+ update_digest = 1'b0;
+ calculate_next_w = 1'b0;
+
+ init_hash = 1'b0;
+ run_hash = 1'b0;
+
+ unique case (sha_st_q)
+ ShaIdle: begin
+ if (fifo_st_q == FifoWait) begin
+ init_hash = 1'b1;
+ sha_st_d = ShaCompress;
+ end else begin
+ sha_st_d = ShaIdle;
+ end
+ end
+
+ ShaCompress: begin
+ run_hash = 1'b1;
+
+ if (round < 48) begin
+ calculate_next_w = 1'b1;
+ end
+
+ if (complete_one_chunk) begin
+ sha_st_d = ShaUpdateDigest;
+ end else begin
+ sha_st_d = ShaCompress;
+ end
+ end
+
+ ShaUpdateDigest: begin
+ update_digest = 1'b1;
+ if (fifo_st_q == FifoWait) begin
+ init_hash = 1'b1;
+ sha_st_d = ShaCompress;
+ end else begin
+ sha_st_d = ShaIdle;
+ end
+ end
+
+ default: begin
+ sha_st_d = ShaIdle;
+ end
+ endcase
+ end
+
+ // complete_one_chunk
+ assign complete_one_chunk = (round == 6'd63);
+
+ sha2_pad u_pad (
+ .clk_i,
+ .rst_ni,
+
+ .wipe_secret,
+ .wipe_v,
+
+ .fifo_rvalid,
+ .fifo_rdata,
+ .fifo_rready,
+
+ .shaf_rvalid,
+ .shaf_rdata,
+ .shaf_rready,
+
+ .sha_en,
+ .hash_start,
+ .hash_process,
+ .hash_done,
+
+ .message_length,
+ .msg_feed_complete
+ );
+
+ // Idle
+ assign idle = (fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && !hash_start;
+
+endmodule : sha2
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/sha2_pad.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/sha2_pad.sv
new file mode 100644
index 00000000..6b249fc0
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/sha2_pad.sv
@@ -0,0 +1,311 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SHA-256 Padding logic
+//
+
+
+module sha2_pad import hmac_pkg::*; (
+ input clk_i,
+ input rst_ni,
+
+ input wipe_secret,
+ input sha_word_t wipe_v,
+
+ // To actual FIFO
+ input fifo_rvalid,
+ input sha_fifo_t fifo_rdata,
+ output logic fifo_rready,
+
+ // from SHA2 compress engine
+ output logic shaf_rvalid,
+ output sha_word_t shaf_rdata,
+ input shaf_rready,
+
+ input sha_en,
+ input hash_start,
+ input hash_process,
+ input hash_done,
+
+ input [63:0] message_length, // # of bytes in bits (8 bits granularity)
+ output logic msg_feed_complete // Indicates, all message is feeded
+);
+
+ //logic [8:0] length_added;
+
+ logic [63:0] tx_count; // fin received data count.
+
+ logic inc_txcount;
+ logic fifo_partial;
+ logic txcnt_eq_1a0;
+ logic hash_process_flag; // Set by hash_process, clear by hash_done
+
+ assign fifo_partial = ~&fifo_rdata.mask;
+
+ // tx_count[8:0] == 'h1c0 --> should send LenHi
+ assign txcnt_eq_1a0 = (tx_count[8:0] == 9'h1a0);
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ hash_process_flag <= 1'b0;
+ end else if (hash_process) begin
+ hash_process_flag <= 1'b1;
+ end else if (hash_done || hash_start) begin
+ hash_process_flag <= 1'b0;
+ end
+ end
+
+ // Data path: fout_wdata
+ typedef enum logic [2:0] {
+ FifoIn, // fin_wdata, fin_wstrb
+ Pad80, // {8'h80, 8'h00} , strb (calc based on len[4:3])
+ Pad00, // 32'h0, full strb
+ LenHi, // len[63:32], full strb
+ LenLo // len[31:0], full strb
+ } sel_data_e;
+ sel_data_e sel_data;
+
+ always_comb begin
+ unique case (sel_data)
+ FifoIn: begin
+ shaf_rdata = fifo_rdata.data;
+ end
+
+ Pad80: begin
+ // {a[7:0], b[7:0], c[7:0], d[7:0]}
+ // msglen[4:3] == 00 |-> {'h80, 'h00, 'h00, 'h00}
+ // msglen[4:3] == 01 |-> {msg, 'h80, 'h00, 'h00}
+ // msglen[4:3] == 10 |-> {msg[15:0], 'h80, 'h00}
+ // msglen[4:3] == 11 |-> {msg[23:0], 'h80}
+ unique case (message_length[4:3])
+ 2'b00: shaf_rdata = 32'h8000_0000;
+ 2'b01: shaf_rdata = {fifo_rdata.data[31:24], 24'h8000_00};
+ 2'b10: shaf_rdata = {fifo_rdata.data[31:16], 16'h8000};
+ 2'b11: shaf_rdata = {fifo_rdata.data[31: 8], 8'h80};
+ default: shaf_rdata = 32'h0;
+ endcase
+ end
+
+ Pad00: begin
+ shaf_rdata = '0;
+ end
+
+ LenHi: begin
+ shaf_rdata = message_length[63:32];
+ end
+
+ LenLo: begin
+ shaf_rdata = message_length[31:0];
+ end
+
+ default: begin
+ shaf_rdata = '0;
+ end
+ endcase
+ end
+
+ // Padded length
+ // $ceil(message_length + 8 + 64, 512) -> message_length [8:0] + 440 and ignore carry
+ //assign length_added = (message_length[8:0] + 9'h1b8) ;
+
+ // fifo control
+ // add 8'h 80 , N 8'h00, 64'h message_length
+
+ // Steps
+ // 1. `hash_start` from CPU (or DMA?)
+ // 2. calculate `padded_length` from `message_length`
+ // 3. Check if tx_count == message_length, then go to 5
+ // 4. Receiving FIFO input (hand over to fifo output)
+ // 5. Padding bit 1 (8'h80) followed by 8'h00 if needed
+ // 6. Padding with length (high -> low)
+
+ // State Machine
+ typedef enum logic [2:0] {
+ StIdle, // fin_full to prevent unwanted FIFO write
+ StFifoReceive, // Check tx_count == message_length
+ StPad80, // 8'h 80 + 8'h 00 X N
+ StPad00,
+ StLenHi,
+ StLenLo
+ } pad_st_e;
+
+ pad_st_e st_q, st_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ st_q <= StIdle;
+ end else begin
+ st_q <= st_d;
+ end
+ end
+
+ // Next state
+ always_comb begin
+ shaf_rvalid = 1'b0;
+ inc_txcount = 1'b0;
+ sel_data = FifoIn;
+ fifo_rready = 1'b0;
+
+ st_d = StIdle;
+
+ unique case (st_q)
+ StIdle: begin
+ sel_data = FifoIn;
+ shaf_rvalid = 1'b0;
+
+ if (sha_en && hash_start) begin
+ inc_txcount = 1'b0;
+
+ st_d = StFifoReceive;
+ end else begin
+ st_d = StIdle;
+ end
+ end
+
+ StFifoReceive: begin
+ sel_data = FifoIn;
+
+ if (fifo_partial && fifo_rvalid) begin
+ // End of the message, assume hash_process_flag is set
+ shaf_rvalid = 1'b0; // Update entry at StPad80
+ inc_txcount = 1'b0;
+ fifo_rready = 1'b0;
+
+ st_d = StPad80;
+ end else if (!hash_process_flag) begin
+ fifo_rready = shaf_rready;
+ shaf_rvalid = fifo_rvalid;
+ inc_txcount = shaf_rready;
+
+ st_d = StFifoReceive;
+ end else if (tx_count == message_length) begin
+ // already received all msg and was waiting process flag
+ shaf_rvalid = 1'b0;
+ inc_txcount = 1'b0;
+ fifo_rready = 1'b0;
+
+ st_d = StPad80;
+ end else begin
+ shaf_rvalid = fifo_rvalid;
+ fifo_rready = shaf_rready; // 0 always
+ inc_txcount = shaf_rready; // 0 always
+
+ st_d = StFifoReceive;
+ end
+ end
+
+ StPad80: begin
+ sel_data = Pad80;
+
+ shaf_rvalid = 1'b1;
+ fifo_rready = shaf_rready && |message_length[4:3]; // Only when partial
+
+ // exactly 96 bits left, do not need to pad00's
+ if (shaf_rready && txcnt_eq_1a0) begin
+ st_d = StLenHi;
+ inc_txcount = 1'b1;
+ // it does not matter if value is < or > than 416 bits. If it's the former, 00 pad until
+ // length field. If >, then the next chunk will contain the length field with appropriate
+ // 0 padding.
+ end else if (shaf_rready && !txcnt_eq_1a0) begin
+ st_d = StPad00;
+ inc_txcount = 1'b1;
+ end else begin
+ st_d = StPad80;
+ inc_txcount = 1'b0;
+ end
+
+ // # Below part is temporal code to speed up the SHA by 16 clocks per chunk
+ // # (80 clk --> 64 clk)
+ // # leaving this as a reference but needs to verify it.
+ //if (shaf_rready && !txcnt_eq_1a0) begin
+ // st_d = StPad00;
+ //
+ // inc_txcount = 1'b1;
+ // shaf_rvalid = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
+ // fifo_rready = (msg_word_aligned) ? 1'b0 : 1'b1;
+ //end else if (!shaf_rready && !txcnt_eq_1a0) begin
+ // st_d = StPad80;
+ //
+ // inc_txcount = 1'b0;
+ // shaf_rvalid = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
+ //
+ //end else if (shaf_rready && txcnt_eq_1a0) begin
+ // st_d = StLenHi;
+ // inc_txcount = 1'b1;
+ //end else begin
+ // // !shaf_rready && txcnt_eq_1a0 , just wait until fifo_rready asserted
+ // st_d = StPad80;
+ // inc_txcount = 1'b0;
+ //end
+ end
+
+ StPad00: begin
+ sel_data = Pad00;
+ shaf_rvalid = 1'b1;
+
+ if (shaf_rready) begin
+ inc_txcount = 1'b1;
+
+ if (txcnt_eq_1a0) begin
+ st_d = StLenHi;
+ end else begin
+ st_d = StPad00;
+ end
+ end else begin
+ st_d = StPad00;
+ end
+ end
+
+ StLenHi: begin
+ sel_data = LenHi;
+ shaf_rvalid = 1'b1;
+
+ if (shaf_rready) begin
+ st_d = StLenLo;
+
+ inc_txcount = 1'b1;
+ end else begin
+ st_d = StLenHi;
+
+ inc_txcount = 1'b0;
+ end
+ end
+
+ StLenLo: begin
+ sel_data = LenLo;
+ shaf_rvalid = 1'b1;
+
+ if (shaf_rready) begin
+ st_d = StIdle;
+
+ inc_txcount = 1'b1;
+ end else begin
+ st_d = StLenLo;
+
+ inc_txcount = 1'b0;
+ end
+ end
+
+ default: begin
+ st_d = StIdle;
+ end
+ endcase
+ end
+
+ // tx_count
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ tx_count <= '0;
+ end else if (hash_start) begin
+ tx_count <= '0;
+ end else if (inc_txcount) begin
+ tx_count[63:5] <= tx_count[63:5] + 1'b1;
+ end
+ end
+
+ // State machine is in Idle only when it meets tx_count == message length
+ assign msg_feed_complete = hash_process_flag && (st_q == StIdle);
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_adapter_reg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_adapter_reg.sv
new file mode 100644
index 00000000..5fcf48bf
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_adapter_reg.sv
@@ -0,0 +1,138 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Tile-Link UL adapter for Register interface
+ */
+
+module tlul_adapter_reg import tlul_pkg::*; #(
+ parameter int RegAw = 8,
+ parameter int EnableDataIntgGen = 0,
+ parameter int RegDw = 32, // Shall be matched with TL_DW
+ localparam int RegBw = RegDw/8
+) (
+ input clk_i,
+ input rst_ni,
+
+ // TL-UL interface
+ input tl_h2d_t tl_i,
+ output tl_d2h_t tl_o,
+
+ // Register interface
+ output logic re_o,
+ output logic we_o,
+ output logic [RegAw-1:0] addr_o,
+ output logic [RegDw-1:0] wdata_o,
+ output logic [RegBw-1:0] be_o,
+ input [RegDw-1:0] rdata_i,
+ input error_i
+);
+
+ localparam int IW = $bits(tl_i.a_source);
+ localparam int SZW = $bits(tl_i.a_size);
+
+ logic outstanding; // Indicates current request is pending
+ logic a_ack, d_ack;
+
+ logic [RegDw-1:0] rdata;
+ logic error, err_internal;
+
+ logic addr_align_err; // Size and alignment
+ logic malformed_meta_err; // User signal format error or unsupported
+ logic tl_err; // Common TL-UL error checker
+
+ logic [IW-1:0] reqid;
+ logic [SZW-1:0] reqsz;
+ tl_d_op_e rspop;
+
+ logic rd_req, wr_req;
+
+ assign a_ack = tl_i.a_valid & tl_o.a_ready;
+ assign d_ack = tl_o.d_valid & tl_i.d_ready;
+ // Request signal
+ assign wr_req = a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData));
+ assign rd_req = a_ack & (tl_i.a_opcode == Get);
+
+ assign we_o = wr_req & ~err_internal;
+ assign re_o = rd_req & ~err_internal;
+ assign addr_o = {tl_i.a_address[RegAw-1:2], 2'b00}; // generate always word-align
+ assign wdata_o = tl_i.a_data;
+ assign be_o = tl_i.a_mask;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) outstanding <= 1'b0;
+ else if (a_ack) outstanding <= 1'b1;
+ else if (d_ack) outstanding <= 1'b0;
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ reqid <= '0;
+ reqsz <= '0;
+ rspop <= AccessAck;
+ end else if (a_ack) begin
+ reqid <= tl_i.a_source;
+ reqsz <= tl_i.a_size;
+ // Return AccessAckData regardless of error
+ rspop <= (rd_req) ? AccessAckData : AccessAck ;
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ rdata <= '0;
+ error <= 1'b0;
+ end else if (a_ack) begin
+ rdata <= (err_internal) ? '1 : rdata_i;
+ error <= error_i | err_internal;
+ end
+ end
+
+ assign tl_o = '{
+ a_ready: ~outstanding,
+ d_valid: outstanding,
+ d_opcode: rspop,
+ d_param: '0,
+ d_size: reqsz,
+ d_source: reqid,
+ d_sink: '0,
+ d_data: rdata,
+ d_user: '0,
+ d_error: error
+ };
+
+ ////////////////////
+ // Error Handling //
+ ////////////////////
+ assign err_internal = addr_align_err | malformed_meta_err | tl_err ;
+
+ // malformed_meta_err
+ // Raised if not supported feature is turned on or user signal has malformed
+ //assign malformed_meta_err = (tl_i.a_user.parity_en == 1'b1);
+ assign malformed_meta_err = 1'b0;
+
+ // addr_align_err
+ // Raised if addr isn't aligned with the size
+ // Read size error is checked in tlul_assert.sv
+ // Here is it added due to the limitation of register interface.
+ always_comb begin
+ if (wr_req) begin
+ // Only word-align is accepted based on comportability spec
+ addr_align_err = |tl_i.a_address[1:0];
+ end else begin
+ // No request
+ addr_align_err = 1'b0;
+ end
+ end
+
+ // tl_err : separate checker
+ tlul_err u_err (
+ .clk_i,
+ .rst_ni,
+ .tl_i,
+ .err_o (tl_err)
+ );
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_adapter_sram.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_adapter_sram.sv
new file mode 100644
index 00000000..c4c338cc
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_adapter_sram.sv
@@ -0,0 +1,351 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Tile-Link UL adapter for SRAM-like devices
+ *
+ * - Intentionally omitted BaseAddr in case of multiple memory maps are used in a SoC,
+ * it means that aliasing can happen if target device size in TL-UL crossbar is bigger
+ * than SRAM size
+ */
+module tlul_adapter_sram #(
+ parameter int SramAw = 12,
+ parameter int SramDw = 32, // Must be multiple of the TL width
+ parameter int Outstanding = 1, // Only one request is accepted
+ parameter bit ByteAccess = 1, // 1: true, 0: false
+ parameter bit ErrOnWrite = 0, // 1: Writes not allowed, automatically error
+ parameter bit ErrOnRead = 0, // 1: Reads not allowed, automatically error
+ parameter int CmdIntgCheck =1,
+ parameter int EnableRspIntgGen = 1,
+ parameter int EnableDataIntgGen =1
+
+) (
+ input clk_i,
+ input rst_ni,
+
+ // TL-UL interface
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // SRAM interface
+ output logic req_o,
+ input gnt_i,
+ output logic we_o,
+ output logic [SramAw-1:0] addr_o,
+ output logic [SramDw-1:0] wdata_o,
+ output logic [SramDw-1:0] wmask_o,
+ input [SramDw-1:0] rdata_i,
+ input rvalid_i,
+ input [1:0] rerror_i // 2 bit error [1]: Uncorrectable, [0]: Correctable
+);
+
+ import tlul_pkg::*;
+
+ localparam int SramByte = SramDw/8;
+ localparam int DataBitWidth = prim_util_pkg::vbits(SramByte);
+ localparam int WidthMult = SramDw / top_pkg::TL_DW;
+ localparam int WoffsetWidth = (SramByte == top_pkg::TL_DBW) ? 1 :
+ DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW);
+
+ typedef struct packed {
+ logic [top_pkg::TL_DBW-1:0] mask ; // Byte mask within the TL-UL word
+ logic [WoffsetWidth-1:0] woffset ; // Offset of the TL-UL word within the SRAM word
+ } sram_req_t ;
+
+ typedef enum logic [1:0] {
+ OpWrite,
+ OpRead,
+ OpUnknown
+ } req_op_e ;
+
+ typedef struct packed {
+ req_op_e op ;
+ logic error ;
+ logic [top_pkg::TL_SZW-1:0] size ;
+ logic [top_pkg::TL_AIW-1:0] source ;
+ } req_t ;
+
+ typedef struct packed {
+ logic [SramDw-1:0] data ;
+ logic error ;
+ } rsp_t ;
+
+ localparam int SramReqFifoWidth = $bits(sram_req_t) ;
+ localparam int ReqFifoWidth = $bits(req_t) ;
+ localparam int RspFifoWidth = $bits(rsp_t) ;
+
+ // FIFO signal in case OutStand is greater than 1
+ // If request is latched, {write, source} is pushed to req fifo.
+ // Req fifo is popped when D channel is acknowledged (v & r)
+ // D channel valid is asserted if it is write request or rsp fifo not empty if read.
+ logic reqfifo_wvalid, reqfifo_wready;
+ logic reqfifo_rvalid, reqfifo_rready;
+ req_t reqfifo_wdata, reqfifo_rdata;
+
+ logic sramreqfifo_wvalid, sramreqfifo_wready;
+ logic sramreqfifo_rready;
+ sram_req_t sramreqfifo_wdata, sramreqfifo_rdata;
+
+ logic rspfifo_wvalid, rspfifo_wready;
+ logic rspfifo_rvalid, rspfifo_rready;
+ rsp_t rspfifo_wdata, rspfifo_rdata;
+
+ logic error_internal; // Internal protocol error checker
+ logic wr_attr_error;
+ logic wr_vld_error;
+ logic rd_vld_error;
+ logic tlul_error; // Error from `tlul_err` module
+
+ logic a_ack, d_ack, sram_ack;
+ assign a_ack = tl_i.a_valid & tl_o.a_ready ;
+ assign d_ack = tl_o.d_valid & tl_i.d_ready ;
+ assign sram_ack = req_o & gnt_i ;
+
+ // Valid handling
+ logic d_valid, d_error;
+ always_comb begin
+ d_valid = 1'b0;
+
+ if (reqfifo_rvalid) begin
+ if (reqfifo_rdata.error) begin
+ // Return error response. Assume no request went out to SRAM
+ d_valid = 1'b1;
+ end else if (reqfifo_rdata.op == OpRead) begin
+ d_valid = rspfifo_rvalid;
+ end else begin
+ // Write without error
+ d_valid = 1'b1;
+ end
+ end else begin
+ d_valid = 1'b0;
+ end
+ end
+
+ always_comb begin
+ d_error = 1'b0;
+
+ if (reqfifo_rvalid) begin
+ if (reqfifo_rdata.op == OpRead) begin
+ d_error = rspfifo_rdata.error | reqfifo_rdata.error;
+ end else begin
+ d_error = reqfifo_rdata.error;
+ end
+ end else begin
+ d_error = 1'b0;
+ end
+ end
+
+ assign tl_o = '{
+ d_valid : d_valid ,
+ d_opcode : (d_valid && reqfifo_rdata.op != OpRead) ? AccessAck : AccessAckData,
+ d_param : '0,
+ d_size : (d_valid) ? reqfifo_rdata.size : '0,
+ d_source : (d_valid) ? reqfifo_rdata.source : '0,
+ d_sink : 1'b0,
+ d_data : (d_valid && rspfifo_rvalid && reqfifo_rdata.op == OpRead)
+ ? rspfifo_rdata.data : '0,
+ d_user : '0,
+ d_error : d_valid && d_error,
+
+ a_ready : (gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready
+ };
+
+ // a_ready depends on the FIFO full condition and grant from SRAM (or SRAM arbiter)
+ // assemble response, including read response, write response, and error for unsupported stuff
+
+ // Output to SRAM:
+ // Generate request only when no internal error occurs. If error occurs, the request should be
+ // dropped and returned error response to the host. So, error to be pushed to reqfifo.
+ // In this case, it is assumed the request is granted (may cause ordering issue later?)
+ assign req_o = tl_i.a_valid & reqfifo_wready & ~error_internal;
+ assign we_o = tl_i.a_valid & logic'(tl_i.a_opcode inside {PutFullData, PutPartialData});
+ assign addr_o = (tl_i.a_valid) ? tl_i.a_address[DataBitWidth+:SramAw] : '0;
+
+ // Support SRAMs wider than the TL-UL word width by mapping the parts of the
+ // TL-UL address which are more fine-granular than the SRAM width to the
+ // SRAM write mask.
+ logic [WoffsetWidth-1:0] woffset;
+ if (top_pkg::TL_DW != SramDw) begin : gen_wordwidthadapt
+ assign woffset = tl_i.a_address[DataBitWidth-1:prim_util_pkg::vbits(top_pkg::TL_DBW)];
+ end else begin : gen_no_wordwidthadapt
+ assign woffset = '0;
+ end
+
+ // Convert byte mask to SRAM bit mask for writes, and only forward valid data
+ logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wmask_int;
+ logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wdata_int;
+
+ always_comb begin
+ wmask_int = '0;
+ wdata_int = '0;
+
+ if (tl_i.a_valid) begin
+ for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
+ wmask_int[woffset][8*i +: 8] = {8{tl_i.a_mask[i]}};
+ wdata_int[woffset][8*i +: 8] = (tl_i.a_mask[i] && we_o) ? tl_i.a_data[8*i+:8] : '0;
+ end
+ end
+ end
+
+ assign wmask_o = wmask_int;
+ assign wdata_o = wdata_int;
+
+ // Begin: Request Error Detection
+
+ // wr_attr_error: Check if the request size,mask are permitted.
+ // Basic check of size, mask, addr align is done in tlul_err module.
+ // Here it checks any partial write if ByteAccess isn't allowed.
+ assign wr_attr_error = (tl_i.a_opcode == PutFullData || tl_i.a_opcode == PutPartialData) ?
+ (ByteAccess == 0) ? (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0 :
+ 1'b0;
+
+ if (ErrOnWrite == 1) begin : gen_no_writes
+ assign wr_vld_error = tl_i.a_opcode != Get;
+ end else begin : gen_writes_allowed
+ assign wr_vld_error = 1'b0;
+ end
+
+ if (ErrOnRead == 1) begin: gen_no_reads
+ assign rd_vld_error = tl_i.a_opcode == Get;
+ end else begin : gen_reads_allowed
+ assign rd_vld_error = 1'b0;
+ end
+
+ tlul_err u_err (
+ .clk_i,
+ .rst_ni,
+ .tl_i,
+ .err_o (tlul_error)
+ );
+
+ assign error_internal = wr_attr_error | wr_vld_error | rd_vld_error | tlul_error;
+ // End: Request Error Detection
+
+ assign reqfifo_wvalid = a_ack ; // Push to FIFO only when granted
+ assign reqfifo_wdata = '{
+ op: (tl_i.a_opcode != Get) ? OpWrite : OpRead, // To return AccessAck for opcode error
+ error: error_internal,
+ size: tl_i.a_size,
+ source: tl_i.a_source
+ }; // Store the request only. Doesn't have to store data
+ assign reqfifo_rready = d_ack ;
+
+ // push together with ReqFIFO, pop upon returning read
+ assign sramreqfifo_wdata = '{
+ mask : tl_i.a_mask,
+ woffset : woffset
+ };
+ assign sramreqfifo_wvalid = sram_ack & ~we_o;
+ assign sramreqfifo_rready = rspfifo_wvalid;
+
+ assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid;
+
+ // Make sure only requested bytes are forwarded
+ logic [WidthMult-1:0][top_pkg::TL_DW-1:0] rdata;
+ logic [WidthMult-1:0][top_pkg::TL_DW-1:0] rmask;
+ //logic [SramDw-1:0] rmask;
+ logic [top_pkg::TL_DW-1:0] rdata_tlword;
+
+ always_comb begin
+ rmask = '0;
+ for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
+ rmask[sramreqfifo_rdata.woffset][8*i +: 8] = {8{sramreqfifo_rdata.mask[i]}};
+ end
+ end
+
+ assign rdata = rdata_i & rmask;
+ assign rdata_tlword = rdata[sramreqfifo_rdata.woffset];
+
+ assign rspfifo_wdata = '{
+ data : rdata_tlword,
+ error: rerror_i[1] // Only care for Uncorrectable error
+ };
+ assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error)
+ ? reqfifo_rready : 1'b0 ;
+
+ // This module only cares about uncorrectable errors.
+ logic unused_rerror;
+ assign unused_rerror = rerror_i[0];
+
+ // FIFO instance: REQ, RSP
+
+ // ReqFIFO is to store the Access type to match to the Response data.
+ // For instance, SRAM accepts the write request but doesn't return the
+ // acknowledge. In this case, it may be hard to determine when the D
+ // response for the write data should send out if reads/writes are
+ // interleaved. So, to make it in-order (even TL-UL allows out-of-order
+ // responses), storing the request is necessary. And if the read entry
+ // is write op, it is safe to return the response right away. If it is
+ // read reqeust, then D response is waiting until read data arrives.
+
+ // Notes:
+ // The oustanding+1 allows the reqfifo to absorb back to back transactions
+ // without any wait states. Alternatively, the depth can be kept as
+ // oustanding as long as the outgoing ready is qualified with the acceptance
+ // of the response in the same cycle. Doing so however creates a path from
+ // ready_i to ready_o, which may not be desireable.
+ prim_fifo_sync #(
+ .Width (ReqFifoWidth),
+ .Pass (1'b0),
+ .Depth (Outstanding)
+ ) u_reqfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0),
+ .wvalid(reqfifo_wvalid),
+ .wready(reqfifo_wready),
+ .wdata (reqfifo_wdata),
+ .depth (),
+ .rvalid(reqfifo_rvalid),
+ .rready(reqfifo_rready),
+ .rdata (reqfifo_rdata)
+ );
+
+ // sramreqfifo:
+ // While the ReqFIFO holds the request until it is sent back via TL-UL, the
+ // sramreqfifo only needs to hold the mask and word offset until the read
+ // data returns from memory.
+ prim_fifo_sync #(
+ .Width (SramReqFifoWidth),
+ .Pass (1'b0),
+ .Depth (Outstanding)
+ ) u_sramreqfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0),
+ .wvalid(sramreqfifo_wvalid),
+ .wready(sramreqfifo_wready),
+ .wdata (sramreqfifo_wdata),
+ .depth (),
+ .rvalid(),
+ .rready(sramreqfifo_rready),
+ .rdata (sramreqfifo_rdata)
+ );
+
+ // Rationale having #Outstanding depth in response FIFO.
+ // In normal case, if the host or the crossbar accepts the response data,
+ // response FIFO isn't needed. But if in any case it has a chance to be
+ // back pressured, the response FIFO should store the returned data not to
+ // lose the data from the SRAM interface. Remember, SRAM interface doesn't
+ // have back-pressure signal such as read_ready.
+ prim_fifo_sync #(
+ .Width (RspFifoWidth),
+ .Pass (1'b1),
+ .Depth (Outstanding)
+ ) u_rspfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0),
+ .wvalid(rspfifo_wvalid),
+ .wready(rspfifo_wready),
+ .wdata (rspfifo_wdata),
+ .depth (),
+ .rvalid(rspfifo_rvalid),
+ .rready(rspfifo_rready),
+ .rdata (rspfifo_rdata)
+ );
+
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_cmd_intg_chk.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_cmd_intg_chk.sv
new file mode 100644
index 00000000..a903e254
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_cmd_intg_chk.sv
@@ -0,0 +1,40 @@
+
+
+module tlul_cmd_intg_chk import tlul_pkg::*; (
+ // TL-UL interface
+ input tl_h2d_t tl_i,
+
+ // error output
+ output logic err_o
+);
+
+ logic [1:0] err;
+ logic data_err;
+ tl_h2d_cmd_intg_t cmd;
+ assign cmd = extract_h2d_cmd_intg(tl_i);
+
+ prim_secded_inv_64_57_dec u_chk (
+ .data_i({tl_i.a_user.cmd_intg, H2DCmdMaxWidth'(cmd)}),
+ .data_o(),
+ .syndrome_o(),
+ .err_o(err)
+ );
+
+ tlul_data_integ_dec u_tlul_data_integ_dec (
+ .data_intg_i({tl_i.a_user.data_intg, DataMaxWidth'(tl_i.a_data)}),
+ .data_err_o(data_err)
+ );
+
+ // error output is transactional, it is up to the instantiating module
+ // to determine if a permanent latch is feasible
+ logic wr_txn;
+ assign wr_txn = tl_i.a_valid &
+ (tl_i.a_opcode == PutFullData | tl_i.a_opcode == PutPartialData);
+
+ assign err_o = tl_i.a_valid & (|err | (|data_err));
+
+
+ logic unused_tl;
+ assign unused_tl = |tl_i;
+
+endmodule // tlul_payload_chk
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_data_integ_dec.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_data_integ_dec.sv
new file mode 100644
index 00000000..3db4312b
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_data_integ_dec.sv
@@ -0,0 +1,26 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Data integrity decoder for bus integrity scheme
+ */
+
+module tlul_data_integ_dec import tlul_pkg::*; (
+ // TL-UL interface
+ input [DataMaxWidth+DataIntgWidth-1:0] data_intg_i,
+ output logic data_err_o
+);
+
+ logic [1:0] data_err;
+ prim_secded_inv_39_32_dec u_data_chk (
+ .data_i(data_intg_i),
+ .data_o(),
+ .syndrome_o(),
+ .err_o(data_err)
+ );
+
+ assign data_err_o = |data_err;
+
+endmodule : tlul_data_integ_dec
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_data_integ_enc.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_data_integ_enc.sv
new file mode 100644
index 00000000..1ae5b521
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_data_integ_enc.sv
@@ -0,0 +1,21 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Data integrity encoder for bus integrity scheme
+ */
+
+module tlul_data_integ_enc import tlul_pkg::*; (
+ // TL-UL interface
+ input [DataMaxWidth-1:0] data_i,
+ output logic [DataMaxWidth+DataIntgWidth-1:0] data_intg_o
+);
+
+ prim_secded_inv_39_32_enc u_data_gen (
+ .data_i,
+ .data_o(data_intg_o)
+ );
+
+endmodule : tlul_data_integ_enc
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_err.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_err.sv
new file mode 100644
index 00000000..67fd8307
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_err.sv
@@ -0,0 +1,92 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+
+module tlul_err import tlul_pkg::*; (
+ input clk_i,
+ input rst_ni,
+
+ input tl_h2d_t tl_i,
+
+ output logic err_o
+);
+
+ localparam int IW = $bits(tl_i.a_source);
+ localparam int SZW = $bits(tl_i.a_size);
+ localparam int DW = $bits(tl_i.a_data);
+ localparam int MW = $bits(tl_i.a_mask);
+ localparam int SubAW = $clog2(DW/8);
+
+ logic opcode_allowed, a_config_allowed;
+
+ logic op_full, op_partial, op_get;
+ assign op_full = (tl_i.a_opcode == PutFullData);
+ assign op_partial = (tl_i.a_opcode == PutPartialData);
+ assign op_get = (tl_i.a_opcode == Get);
+
+ // Anything that doesn't fall into the permitted category, it raises an error
+ assign err_o = ~(opcode_allowed & a_config_allowed);
+
+ // opcode check
+ assign opcode_allowed = (tl_i.a_opcode == PutFullData)
+ | (tl_i.a_opcode == PutPartialData)
+ | (tl_i.a_opcode == Get);
+
+ // a channel configuration check
+ logic addr_sz_chk; // address and size alignment check
+ logic mask_chk; // inactive lane a_mask check
+ logic fulldata_chk; // PutFullData should have size match to mask
+
+ logic [MW-1:0] mask;
+
+ assign mask = (1 << tl_i.a_address[SubAW-1:0]);
+
+ always_comb begin
+ addr_sz_chk = 1'b0;
+ mask_chk = 1'b0;
+ fulldata_chk = 1'b0; // Only valid when opcode is PutFullData
+
+ if (tl_i.a_valid) begin
+ unique case (tl_i.a_size)
+ 'h0: begin // 1 Byte
+ addr_sz_chk = 1'b1;
+ mask_chk = ~|(tl_i.a_mask & ~mask);
+ fulldata_chk = |(tl_i.a_mask & mask);
+ end
+
+ 'h1: begin // 2 Byte
+ addr_sz_chk = ~tl_i.a_address[0];
+ // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0]
+ mask_chk = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011)
+ : ~|(tl_i.a_mask & 4'b1100);
+ fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ;
+ end
+
+ 'h2: begin // 4 Byte
+ addr_sz_chk = ~|tl_i.a_address[SubAW-1:0];
+ mask_chk = 1'b1;
+ fulldata_chk = &tl_i.a_mask[3:0];
+ end
+
+ default: begin // else
+ addr_sz_chk = 1'b0;
+ mask_chk = 1'b0;
+ fulldata_chk = 1'b0;
+ end
+ endcase
+ end else begin
+ addr_sz_chk = 1'b0;
+ mask_chk = 1'b0;
+ fulldata_chk = 1'b0;
+ end
+ end
+
+ assign a_config_allowed = addr_sz_chk
+ & mask_chk
+ & (op_get | op_partial | fulldata_chk) ;
+
+
+endmodule
+
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_err_resp.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_err_resp.sv
new file mode 100644
index 00000000..d05e70ae
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_err_resp.sv
@@ -0,0 +1,59 @@
+
+// TL-UL error responder module, used by tlul_socket_1n to help response
+// to requests to no correct address space. Responses are always one cycle
+// after request with no stalling unless response is stuck on the way out.
+//`include "/home/sajjad/Shaheen-sv/src/buraq_core_top/ibex_core/tlul_pkg.sv"
+module tlul_err_resp (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_h_i,
+ output tlul_pkg::tl_d2h_t tl_h_o
+);
+ import tlul_pkg::*;
+ localparam int TL_AIW=8; // a_source, d_source
+
+ //tlul_pkg::tl_a_m_op get;
+ logic [$bits(tl_h_i.a_source)-1:0] err_source;
+ logic [$bits(tl_h_i.a_size)-1:0] err_size;
+ logic err_req_pending, err_rsp_pending;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_req_pending <= 1'b0;
+ //err_source <= {tlul_pkg::TL_AIW{1'b0}};
+ //err_opcode <= tlul_pkg::Get;
+ err_size <= '0;
+ end else if (tl_h_i.a_valid && tl_h_o.a_ready) begin
+ err_req_pending <= 1'b1;
+ err_source <= tl_h_i.a_source;
+ //err_opcode <= tl_h_i.a_opcode;
+ err_size <= tl_h_i.a_size;
+ end else if (!err_rsp_pending) begin
+ err_req_pending <= 1'b0;
+ end
+ end
+
+ assign tl_h_o.a_ready = ~err_rsp_pending & ~(err_req_pending & ~tl_h_i.d_ready);
+ assign tl_h_o.d_valid = err_req_pending | err_rsp_pending;
+ assign tl_h_o.d_data = '1; // Return all F
+ assign tl_h_o.d_source = err_source;
+ assign tl_h_o.d_sink = '0;
+ assign tl_h_o.d_param = '0;
+ assign tl_h_o.d_user.rsp_intg = '0;
+ assign tl_h_o.d_user.data_intg = '0;
+ assign tl_h_o.d_size = err_size;
+ //assign tl_h_o.d_opcode = (err_opcode == tlul_pkg::Get) ? AccessAckData : AccessAck;
+ assign tl_h_o.d_opcode = AccessAck;
+ assign tl_h_o.d_error = 1'b1;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_rsp_pending <= 1'b0;
+ end else if ((err_req_pending || err_rsp_pending) && !tl_h_i.d_ready) begin
+ err_rsp_pending <= 1'b1;
+ end else begin
+ err_rsp_pending <= 1'b0;
+ end
+ end
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_fifo_sync.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_fifo_sync.sv
new file mode 100644
index 00000000..0cc3d8ec
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_fifo_sync.sv
@@ -0,0 +1,91 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// TL-UL fifo, used to add elasticity or an asynchronous clock crossing
+// to an TL-UL bus. This instantiates two FIFOs, one for the request side,
+// and one for the response side.
+
+module tlul_fifo_sync #(
+ parameter bit ReqPass = 1'b1,
+ parameter bit RspPass = 1'b1,
+ parameter int unsigned ReqDepth = 2,
+ parameter int unsigned RspDepth = 2,
+ parameter int unsigned SpareReqW = 1,
+ parameter int unsigned SpareRspW = 1
+) (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_h_i,
+ output tlul_pkg::tl_d2h_t tl_h_o,
+ output tlul_pkg::tl_h2d_t tl_d_o,
+ input tlul_pkg::tl_d2h_t tl_d_i,
+ input [SpareReqW-1:0] spare_req_i,
+ output [SpareReqW-1:0] spare_req_o,
+ input [SpareRspW-1:0] spare_rsp_i,
+ output [SpareRspW-1:0] spare_rsp_o
+);
+
+ // Put everything on the request side into one FIFO
+ localparam int unsigned REQFIFO_WIDTH = $bits(tlul_pkg::tl_h2d_t) -2 + SpareReqW;
+
+ prim_fifo_sync #(.Width(REQFIFO_WIDTH), .Pass(ReqPass), .Depth(ReqDepth)) reqfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0 ),
+ .wvalid (tl_h_i.a_valid),
+ .wready (tl_h_o.a_ready),
+ .wdata ({tl_h_i.a_opcode ,
+ tl_h_i.a_param ,
+ tl_h_i.a_size ,
+ tl_h_i.a_source ,
+ tl_h_i.a_address,
+ tl_h_i.a_mask ,
+ tl_h_i.a_data ,
+ tl_h_i.a_user ,
+ spare_req_i}),
+ .rvalid (tl_d_o.a_valid),
+ .rready (tl_d_i.a_ready),
+ .rdata ({tl_d_o.a_opcode ,
+ tl_d_o.a_param ,
+ tl_d_o.a_size ,
+ tl_d_o.a_source ,
+ tl_d_o.a_address,
+ tl_d_o.a_mask ,
+ tl_d_o.a_data ,
+ tl_d_o.a_user ,
+ spare_req_o}));
+
+ // Put everything on the response side into the other FIFO
+
+ localparam int unsigned RSPFIFO_WIDTH = $bits(tlul_pkg::tl_d2h_t) -2 + SpareRspW;
+
+ prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0 ),
+ .wvalid (tl_d_i.d_valid),
+ .wready (tl_d_o.d_ready),
+ .wdata ({tl_d_i.d_opcode,
+ tl_d_i.d_param ,
+ tl_d_i.d_size ,
+ tl_d_i.d_source,
+ tl_d_i.d_sink ,
+ (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
+ {top_pkg::TL_DW{1'b0}} ,
+ tl_d_i.d_user ,
+ tl_d_i.d_error ,
+ spare_rsp_i}),
+ .rvalid (tl_h_o.d_valid),
+ .rready (tl_h_i.d_ready),
+ .rdata ({tl_h_o.d_opcode,
+ tl_h_o.d_param ,
+ tl_h_o.d_size ,
+ tl_h_o.d_source,
+ tl_h_o.d_sink ,
+ tl_h_o.d_data ,
+ tl_h_o.d_user ,
+ tl_h_o.d_error ,
+ spare_rsp_o}));
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_pkg.sv
new file mode 100644
index 00000000..81feee0c
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_pkg.sv
@@ -0,0 +1,174 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package tlul_pkg;
+
+ // this can be either PPC or BINTREE
+ // there is no functional difference, but timing and area behavior is different
+ // between the two instances. PPC can result in smaller implementations when timing
+ // is not critical, whereas BINTREE is favorable when timing pressure is high (but this
+ // may also result in a larger implementation). on FPGA targets, BINTREE is favorable
+ // both in terms of area and timing.
+ parameter ArbiterImpl = "PPC";
+
+ typedef enum logic [2:0] {
+ PutFullData = 3'h0,
+ PutPartialData = 3'h1,
+ Get = 3'h4
+ } tl_a_op_e;
+
+ typedef enum logic [2:0] {
+ AccessAck = 3'h0,
+ AccessAckData = 3'h1
+ } tl_d_op_e;
+
+ parameter int H2DCmdMaxWidth = 57;
+ parameter int H2DCmdIntgWidth = 7;
+ parameter int H2DCmdFullWidth = H2DCmdMaxWidth + H2DCmdIntgWidth;
+ parameter int D2HRspMaxWidth = 57;
+ parameter int D2HRspIntgWidth = 7;
+ parameter int D2HRspFullWidth = D2HRspMaxWidth + D2HRspIntgWidth;
+ parameter int DataMaxWidth = 32;
+ parameter int DataIntgWidth = 7;
+ parameter int DataFullWidth = DataMaxWidth + DataIntgWidth;
+
+ typedef struct packed {
+ logic [4:0] rsvd;
+ prim_mubi_pkg::mubi4_t instr_type;
+ logic [H2DCmdIntgWidth-1:0] cmd_intg;
+ logic [DataIntgWidth-1:0] data_intg;
+ } tl_a_user_t;
+
+ parameter tl_a_user_t TL_A_USER_DEFAULT = '{
+ rsvd: '0,
+ instr_type: prim_mubi_pkg::MuBi4False,
+ cmd_intg: {H2DCmdIntgWidth{1'b1}},
+ data_intg: {DataIntgWidth{1'b1}}
+ };
+
+ typedef struct packed {
+ prim_mubi_pkg::mubi4_t instr_type;
+ logic [top_pkg::TL_AW-1:0] addr;
+ tl_a_op_e opcode;
+ logic [top_pkg::TL_DBW-1:0] mask;
+ } tl_h2d_cmd_intg_t;
+
+ typedef struct packed {
+ logic a_valid;
+ tl_a_op_e a_opcode;
+ logic [2:0] a_param;
+ logic [top_pkg::TL_SZW-1:0] a_size;
+ logic [top_pkg::TL_AIW-1:0] a_source;
+ logic [top_pkg::TL_AW-1:0] a_address;
+ logic [top_pkg::TL_DBW-1:0] a_mask;
+ logic [top_pkg::TL_DW-1:0] a_data;
+ tl_a_user_t a_user;
+
+ logic d_ready;
+ } tl_h2d_t;
+
+ localparam tl_h2d_t TL_H2D_DEFAULT = '{
+ d_ready: 1'b1,
+ a_opcode: tl_a_op_e'('0),
+ a_user: TL_A_USER_DEFAULT,
+ default: '0
+ };
+
+ typedef struct packed {
+ logic [D2HRspIntgWidth-1:0] rsp_intg;
+ logic [DataIntgWidth-1:0] data_intg;
+ } tl_d_user_t;
+
+ parameter tl_d_user_t TL_D_USER_DEFAULT = '{
+ rsp_intg: {D2HRspIntgWidth{1'b1}},
+ data_intg: {DataIntgWidth{1'b1}}
+ };
+
+ typedef struct packed {
+ logic d_valid;
+ tl_d_op_e d_opcode;
+ logic [2:0] d_param;
+ logic [top_pkg::TL_SZW-1:0] d_size; // Bouncing back a_size
+ logic [top_pkg::TL_AIW-1:0] d_source;
+ logic [top_pkg::TL_DIW-1:0] d_sink;
+ logic [top_pkg::TL_DW-1:0] d_data;
+ tl_d_user_t d_user;
+ logic d_error;
+
+ logic a_ready;
+
+ } tl_d2h_t;
+
+ typedef struct packed {
+ tl_d_op_e opcode;
+ logic [top_pkg::TL_SZW-1:0] size;
+ // Temporarily removed because source changes throughout the fabric
+ // and thus cannot be used for end-to-end checking.
+ // A different PR will propose a work-around (a hoaky one) to see if
+ // it gets the job done.
+ //logic [top_pkg::TL_AIW-1:0] source;
+ logic error;
+ } tl_d2h_rsp_intg_t;
+
+ localparam tl_d2h_t TL_D2H_DEFAULT = '{
+ a_ready: 1'b1,
+ d_opcode: tl_d_op_e'('0),
+ d_user: TL_D_USER_DEFAULT,
+ default: '0
+ };
+
+ // Check user for unsupported values
+ function automatic logic tl_a_user_chk(tl_a_user_t user);
+ logic malformed_err;
+ logic unused_user;
+ unused_user = |user;
+ malformed_err = prim_mubi_pkg::mubi4_test_invalid(user.instr_type);
+ return malformed_err;
+ endfunction // tl_a_user_chk
+
+ // extract variables used for command checking
+ function automatic tl_h2d_cmd_intg_t extract_h2d_cmd_intg(tl_h2d_t tl);
+ tl_h2d_cmd_intg_t payload;
+ logic unused_tlul;
+ unused_tlul = ^tl;
+ payload.addr = tl.a_address;
+ payload.opcode = tl.a_opcode;
+ payload.mask = tl.a_mask;
+ payload.instr_type = tl.a_user.instr_type;
+ return payload;
+ endfunction // extract_h2d_payload
+
+ // extract variables used for response checking
+ function automatic tl_d2h_rsp_intg_t extract_d2h_rsp_intg(tl_d2h_t tl);
+ tl_d2h_rsp_intg_t payload;
+ logic unused_tlul;
+ unused_tlul = ^tl;
+ payload.opcode = tl.d_opcode;
+ payload.size = tl.d_size;
+ //payload.source = tl.d_source;
+ payload.error = tl.d_error;
+ return payload;
+ endfunction // extract_d2h_rsp_intg
+
+ // calculate ecc for command checking
+ function automatic logic [H2DCmdIntgWidth-1:0] get_cmd_intg(tl_h2d_t tl);
+ logic [H2DCmdIntgWidth-1:0] cmd_intg;
+ logic [H2DCmdMaxWidth-1:0] unused_cmd_payload;
+ tl_h2d_cmd_intg_t cmd;
+ cmd = extract_h2d_cmd_intg(tl);
+ {cmd_intg, unused_cmd_payload} =
+ prim_secded_pkg::prim_secded_inv_64_57_enc(H2DCmdMaxWidth'(cmd));
+ return cmd_intg;
+ endfunction // get_cmd_intg
+
+ // calculate ecc for data checking
+ function automatic logic [DataIntgWidth-1:0] get_data_intg(logic [top_pkg::TL_DW-1:0] data);
+ logic [DataIntgWidth-1:0] data_intg;
+ logic [top_pkg::TL_DW-1:0] unused_data;
+ {data_intg, unused_data} = prim_secded_pkg::prim_secded_inv_39_32_enc(data);
+ return data_intg;
+ endfunction // get_data_intg
+
+endpackage
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_rsp_intg_gen.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_rsp_intg_gen.sv
new file mode 100644
index 00000000..fbcedebb
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_rsp_intg_gen.sv
@@ -0,0 +1,54 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+/**
+ * Tile-Link UL response integrity generator
+ */
+
+module tlul_rsp_intg_gen import tlul_pkg::*; #(
+ parameter bit EnableRspIntgGen = 1'b1,
+ parameter bit EnableDataIntgGen = 1'b1
+) (
+ // TL-UL interface
+ input tl_d2h_t tl_i,
+ output tl_d2h_t tl_o
+);
+
+ logic [D2HRspIntgWidth-1:0] rsp_intg;
+ if (EnableRspIntgGen) begin : gen_rsp_intg
+ tl_d2h_rsp_intg_t rsp;
+ logic [D2HRspMaxWidth-1:0] unused_payload;
+
+ assign rsp = extract_d2h_rsp_intg(tl_i);
+
+ prim_secded_inv_64_57_enc u_rsp_gen (
+ .data_i(D2HRspMaxWidth'(rsp)),
+ .data_o({rsp_intg, unused_payload})
+ );
+ end else begin : gen_passthrough_rsp_intg
+ assign rsp_intg = tl_i.d_user.rsp_intg;
+ end
+
+ logic [DataIntgWidth-1:0] data_intg;
+ if (EnableDataIntgGen) begin : gen_data_intg
+ logic [DataMaxWidth-1:0] unused_data;
+ tlul_data_integ_enc u_tlul_data_integ_enc (
+ .data_i(DataMaxWidth'(tl_i.d_data)),
+ .data_intg_o({data_intg, unused_data})
+ );
+ end else begin : gen_passthrough_data_intg
+ assign data_intg = tl_i.d_user.data_intg;
+ end
+
+ always_comb begin
+ tl_o = tl_i;
+ tl_o.d_user.rsp_intg = rsp_intg;
+ tl_o.d_user.data_intg = data_intg;
+ end
+
+ logic unused_tl;
+ assign unused_tl = ^tl_i;
+
+
+endmodule // tlul_rsp_intg_gen
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_socket_1n.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_socket_1n.sv
new file mode 100644
index 00000000..fd96a64e
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/tlul_socket_1n.sv
@@ -0,0 +1,213 @@
+
+// TL-UL socket 1:N module
+//
+// configuration settings
+// device_count: 4
+//
+// Verilog parameters
+// HReqPass: if 1 then host requests can pass through on empty fifo,
+// default 1
+// HRspPass: if 1 then host responses can pass through on empty fifo,
+// default 1
+// DReqPass: (one per device_count) if 1 then device i requests can
+// pass through on empty fifo, default 1
+// DRspPass: (one per device_count) if 1 then device i responses can
+// pass through on empty fifo, default 1
+// HReqDepth: Depth of host request FIFO, default 2
+// HRspDepth: Depth of host response FIFO, default 2
+// DReqDepth: (one per device_count) Depth of device i request FIFO,
+// default 2
+// DRspDepth: (one per device_count) Depth of device i response FIFO,
+// default 2
+//
+// Requests must stall to one device until all responses from other devices
+// have returned. Need to keep a counter of all outstanding requests and
+// wait until that counter is zero before switching devices.
+//
+// This module will return a request error if the input value of 'dev_select_i'
+// is not within the range 0..N-1. Thus the instantiator of the socket
+// can indicate error by any illegal value of dev_select_i. 4'b1111 is
+// recommended for visibility
+//
+// The maximum value of N is 15
+
+
+module tlul_socket_1n #(
+ parameter int unsigned N = 4,
+ parameter bit HReqPass = 1'b1,
+ parameter bit HRspPass = 1'b1,
+ parameter bit [N-1:0] DReqPass = {N{1'b1}},
+ parameter bit [N-1:0] DRspPass = {N{1'b1}},
+ parameter bit [3:0] HReqDepth = 4'h2,
+ parameter bit [3:0] HRspDepth = 4'h2,
+ parameter bit [N*4-1:0] DReqDepth = {N{4'h2}},
+ parameter bit [N*4-1:0] DRspDepth = {N{4'h2}},
+ localparam int unsigned NWD = $clog2(N+1) // derived parameter
+) (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_h_i,
+ output tlul_pkg::tl_d2h_t tl_h_o,
+ output tlul_pkg::tl_h2d_t tl_d_o [N],
+ input tlul_pkg::tl_d2h_t tl_d_i [N],
+ input [NWD-1:0] dev_select_i
+);
+
+ // Since our steering is done after potential FIFOing, we need to
+ // shove our device select bits into spare bits of reqfifo
+
+ // instantiate the host fifo, create intermediate bus 't'
+
+ // FIFO'd version of device select
+ logic [NWD-1:0] dev_select_t;
+
+ tlul_pkg::tl_h2d_t tl_t_o;
+ tlul_pkg::tl_d2h_t tl_t_i;
+
+ tlul_fifo_sync #(
+ .ReqPass(HReqPass),
+ .RspPass(HRspPass),
+ .ReqDepth(HReqDepth),
+ .RspDepth(HRspDepth),
+ .SpareReqW(NWD)
+ ) fifo_h (
+ .clk_i,
+ .rst_ni,
+ .tl_h_i,
+ .tl_h_o,
+ .tl_d_o (tl_t_o),
+ .tl_d_i (tl_t_i),
+ .spare_req_i (dev_select_i),
+ .spare_req_o (dev_select_t),
+ .spare_rsp_i (1'b0),
+ .spare_rsp_o ());
+
+
+ // We need to keep track of how many requests are outstanding,
+ // and to which device. New requests are compared to this and
+ // stall until that number is zero.
+ // Up to 256 ounstanding
+ localparam int MaxOutstanding = 256;
+ localparam int OutstandingW = $clog2(MaxOutstanding+1);
+ logic [OutstandingW-1:0] num_req_outstanding;
+ logic [NWD-1:0] dev_select_outstanding;
+ logic hold_all_requests;
+ logic accept_t_req, accept_t_rsp;
+
+ assign accept_t_req = tl_t_o.a_valid & tl_t_i.a_ready;
+ assign accept_t_rsp = tl_t_i.d_valid & tl_t_o.d_ready;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ num_req_outstanding <= '0;
+ dev_select_outstanding <= '0;
+ end else if (accept_t_req) begin
+ if (!accept_t_rsp) begin
+ num_req_outstanding <= num_req_outstanding + 1'b1;
+ end
+ dev_select_outstanding <= dev_select_t;
+ end else if (accept_t_rsp) begin
+ num_req_outstanding <= num_req_outstanding - 1'b1;
+ end
+ end
+
+ assign hold_all_requests =
+ (num_req_outstanding != '0) &
+ (dev_select_t != dev_select_outstanding);
+
+ // Make N copies of 't' request side with modified reqvalid, call
+ // them 'u[0]' .. 'u[n-1]'.
+
+ tlul_pkg::tl_h2d_t tl_u_o [N+1];
+ tlul_pkg::tl_d2h_t tl_u_i [N+1];
+
+ for (genvar i = 0 ; i < N ; i++) begin : gen_u_o
+ assign tl_u_o[i].a_valid = tl_t_o.a_valid &
+ (dev_select_t == NWD'(i)) &
+ ~hold_all_requests;
+ assign tl_u_o[i].a_opcode = tl_t_o.a_opcode;
+ assign tl_u_o[i].a_param = tl_t_o.a_param;
+ assign tl_u_o[i].a_size = tl_t_o.a_size;
+ assign tl_u_o[i].a_source = tl_t_o.a_source;
+ assign tl_u_o[i].a_address = tl_t_o.a_address;
+ assign tl_u_o[i].a_mask = tl_t_o.a_mask;
+ assign tl_u_o[i].a_data = tl_t_o.a_data;
+ assign tl_u_o[i].a_user = tl_t_o.a_user;
+ end
+
+ tlul_pkg::tl_d2h_t tl_t_p ;
+
+ // for the returning reqready, only look at the device we're addressing
+ logic hfifo_reqready;
+ always_comb begin
+ hfifo_reqready = tl_u_i[N].a_ready; // default to error
+ for (int idx = 0 ; idx < N ; idx++) begin
+ //if (dev_select_outstanding == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready;
+ if (dev_select_t == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready;
+ end
+ if (hold_all_requests) hfifo_reqready = 1'b0;
+ end
+ // Adding a_valid as a qualifier. This prevents the a_ready from having unknown value
+ // when the address is unknown and the Host TL-UL FIFO is bypass mode.
+ assign tl_t_i.a_ready = tl_t_o.a_valid & hfifo_reqready;
+
+ always_comb begin
+ tl_t_p = tl_u_i[N];
+ for (int idx = 0 ; idx < N ; idx++) begin
+ if (dev_select_outstanding == NWD'(idx)) tl_t_p = tl_u_i[idx];
+ end
+ end
+ assign tl_t_i.d_valid = tl_t_p.d_valid ;
+ assign tl_t_i.d_opcode = tl_t_p.d_opcode;
+ assign tl_t_i.d_param = tl_t_p.d_param ;
+ assign tl_t_i.d_size = tl_t_p.d_size ;
+ assign tl_t_i.d_source = tl_t_p.d_source;
+ assign tl_t_i.d_sink = tl_t_p.d_sink ;
+ assign tl_t_i.d_data = tl_t_p.d_data ;
+ assign tl_t_i.d_error = tl_t_p.d_error ;
+ assign tl_t_i.d_user = '0;
+
+
+ // accept responses from devices when selected if upstream is accepting
+ for (genvar i = 0 ; i < N+1 ; i++) begin : gen_u_o_d_ready
+ assign tl_u_o[i].d_ready = tl_t_o.d_ready;
+ end
+
+ // finally instantiate all device FIFOs and the error responder
+ for (genvar i = 0 ; i < N ; i++) begin : gen_dfifo
+ tlul_fifo_sync #(
+ .ReqPass(DReqPass[i]),
+ .RspPass(DRspPass[i]),
+ .ReqDepth(DReqDepth[i*4+:4]),
+ .RspDepth(DRspDepth[i*4+:4])
+ ) fifo_d (
+ .clk_i,
+ .rst_ni,
+ .tl_h_i (tl_u_o[i]),
+ .tl_h_o (tl_u_i[i]),
+ .tl_d_o (tl_d_o[i]),
+ .tl_d_i (tl_d_i[i]),
+ .spare_req_i (1'b0),
+ .spare_req_o (),
+ .spare_rsp_i (1'b0),
+ .spare_rsp_o ());
+ end
+
+ assign tl_u_o[N].a_valid = tl_t_o.a_valid &
+ (dev_select_t == NWD'(N)) &
+ ~hold_all_requests;
+ assign tl_u_o[N].a_opcode = tl_t_o.a_opcode;
+ assign tl_u_o[N].a_param = tl_t_o.a_param;
+ assign tl_u_o[N].a_size = tl_t_o.a_size;
+ assign tl_u_o[N].a_source = tl_t_o.a_source;
+ assign tl_u_o[N].a_address = tl_t_o.a_address;
+ assign tl_u_o[N].a_mask = tl_t_o.a_mask;
+ assign tl_u_o[N].a_data = tl_t_o.a_data;
+ assign tl_u_o[N].a_user = tl_t_o.a_user;
+ tlul_err_resp err_resp (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .tl_h_i (tl_u_o[N]),
+ .tl_h_o (tl_u_i[N]));
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/top_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/top_pkg.sv
new file mode 100644
index 00000000..3d62c73d
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/lib/work/rtl/top_pkg.sv
@@ -0,0 +1,17 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package top_pkg;
+
+localparam int TL_AW=32;
+localparam int TL_DW=32; // = TL_DBW * 8; TL_DBW must be a power-of-two
+localparam int TL_AIW=8; // a_source, d_source
+localparam int TL_DIW=1; // d_sink
+localparam int TL_AUW=21; // a_user
+localparam int TL_DUW=14; // d_user
+localparam int TL_DBW=(TL_DW>>3);
+localparam int TL_SZW=$clog2($clog2(TL_DBW)+1);
+
+endpackage
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/surelog.log b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/surelog.log
new file mode 100644
index 00000000..2afe7c3a
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/surelog.log
@@ -0,0 +1,157 @@
+********************************************
+* SURELOG SystemVerilog Compiler/Linter *
+********************************************
+
+Copyright (c) 2017-2023 Alain Dargelas,
+http://www.apache.org/licenses/LICENSE-2.0
+
+VERSION: 1.84
+BUILT : Oct 1 2024
+DATE : 2024-10-02.01:40:38
+COMMAND: -synth -top hmac -y ../../../../.././rtl/ -I../../../../.././rtl/ -I../../../../.. -I/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl +libext+.v+.sv -sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_util_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/pwrmgr_reg_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/pwrmgr_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_ram_1p_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_mubi_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_cipher_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_alert_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_count_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/jtag_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/entropy_src_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/edn_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/top_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_ctrl_reg_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_ctrl_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_phy_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_reg_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/lc_ctrl_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/otp_ctrl_reg_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/otp_ctrl_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/ast_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_core.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_reg_top.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_alert_sender.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_buf.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_diff_decode.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_fifo_sync.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_flop_2sync.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_buf.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_flop.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_flop_2sync.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_intr_hw.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_packer.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_39_32_dec.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_39_32_enc.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_64_57_dec.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_64_57_enc.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg_ext.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/sha2.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/sha2_pad.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_adapter_reg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_adapter_sram.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_cmd_intg_chk.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_data_integ_dec.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_data_integ_enc.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_err.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_err_resp.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_fifo_sync.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_rsp_intg_gen.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_socket_1n.sv -DYOSYS=1 -DSYNTHESIS=1
+
+[INF:CM0023] Creating log file "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/surelog.log".
+[INF:CP0300] Compilation...
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_pkg.sv:8:1: Compile package "prim_secded_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg_pkg.sv:5:1: Compile package "prim_subreg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_util_pkg.sv:9:1: Compile package "prim_util_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/pwrmgr_reg_pkg.sv:7:1: Compile package "pwrmgr_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/pwrmgr_pkg.sv:8:1: Compile package "pwrmgr_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_ram_1p_pkg.sv:6:1: Compile package "prim_ram_1p_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:13:1: Compile package "prim_mubi_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_pkg.sv:11:1: Compile package "prim_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:17:1: Compile package "prim_cipher_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_pkg.sv:5:1: Compile package "prim_alert_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_count_pkg.sv:8:1: Compile package "prim_count_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/jtag_pkg.sv:6:1: Compile package "jtag_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/entropy_src_pkg.sv:7:1: Compile package "entropy_src_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/edn_pkg.sv:7:1: Compile package "edn_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/top_pkg.sv:6:1: Compile package "top_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_ctrl_reg_pkg.sv:7:1: Compile package "flash_ctrl_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_ctrl_pkg.sv:8:1: Compile package "flash_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_phy_pkg.sv:8:1: Compile package "flash_phy_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_pkg.sv:7:1: Compile package "hmac_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:6:1: Compile package "hmac_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/lc_ctrl_pkg.sv:6:1: Compile package "lc_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/otp_ctrl_reg_pkg.sv:7:1: Compile package "otp_ctrl_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/otp_ctrl_pkg.sv:6:1: Compile package "otp_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:6:1: Compile package "tlul_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/ast_pkg.sv:12:1: Compile package "ast_pkg".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:9:1: Compile module "work@hmac".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:7:1: Compile module "work@hmac_core".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:8:1: Compile module "work@hmac_reg_top".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:32:1: Compile module "work@prim_alert_sender".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:16:1: Compile module "work@prim_buf".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:19:1: Compile module "work@prim_diff_decode".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:6:1: Compile module "work@prim_fifo_sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:13:1: Compile module "work@prim_flop_2sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_buf.sv:6:1: Compile module "work@prim_generic_buf".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:7:1: Compile module "work@prim_generic_flop".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop_2sync.sv:9:1: Compile module "work@prim_generic_flop_2sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:10:1: Compile module "work@prim_intr_hw".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:8:1: Compile module "work@prim_packer".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:7:1: Compile module "work@prim_secded_inv_39_32_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_enc.sv:7:1: Compile module "work@prim_secded_inv_39_32_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:7:1: Compile module "work@prim_secded_inv_64_57_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_enc.sv:7:1: Compile module "work@prim_secded_inv_64_57_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:7:1: Compile module "work@prim_subreg".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg_ext.sv:7:1: Compile module "work@prim_subreg_ext".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:8:1: Compile module "work@sha2".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:9:1: Compile module "work@sha2_pad".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:10:1: Compile module "work@tlul_adapter_reg".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:13:1: Compile module "work@tlul_adapter_sram".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:3:1: Compile module "work@tlul_cmd_intg_chk".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_data_integ_dec.sv:10:1: Compile module "work@tlul_data_integ_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_data_integ_enc.sv:10:1: Compile module "work@tlul_data_integ_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:7:1: Compile module "work@tlul_err".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:6:1: Compile module "work@tlul_err_resp".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:9:1: Compile module "work@tlul_fifo_sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:9:1: Compile module "work@tlul_rsp_intg_gen".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:35:1: Compile module "work@tlul_socket_1n".
+[INF:CP0302] Compile class "work@mailbox".
+[INF:CP0302] Compile class "work@process".
+[INF:CP0302] Compile class "work@semaphore".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:41:17: Implicit port type (wire) for "sha_message_length".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:21:27: Implicit port type (wire) for "wready",
+there are 3 more instances of this message.
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:24:23: Implicit port type (wire) for "hw2reg_intr_state_de_o",
+there are 1 more instances of this message.
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:19:27: Implicit port type (wire) for "ready_o".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:24:29: Implicit port type (wire) for "spare_req_o",
+there are 1 more instances of this message.
+[INF:EL0526] Design Elaboration...
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[2]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[3]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[4]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[5]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[6]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[7]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_hmac_done.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_fifo_empty.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_hmac_err.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:122:14: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_depth_gt1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:132:23: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_pass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:172:12: Compile generate block "work@hmac.u_tlul_adapter.gen_no_wordwidthadapt".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:206:12: Compile generate block "work@hmac.u_tlul_adapter.gen_writes_allowed".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:210:23: Compile generate block "work@hmac.u_tlul_adapter.gen_no_reads".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:135:14: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_nopass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:135:14: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_nopass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:132:23: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_pass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:19:25: Compile generate block "work@hmac.u_reg.u_rsp_intg_gen.gen_rsp_intg".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:34:26: Compile generate block "work@hmac.u_reg.u_rsp_intg_gen.gen_data_intg".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:124:36: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:124:36: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[2]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:177:36: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:177:36: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_hmac_done.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_fifo_empty.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_hmac_err.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_hmac_done.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_fifo_empty.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_hmac_err.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_err_code.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_msg_length_lower.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_msg_length_upper.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:460:42: Compile generate block "work@hmac.gen_alert_tx[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:44:16: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_n.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:44:16: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_n.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:30:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:30:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_n.gen_generic".
+[NTE:EL0503] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:9:1: Top level module "work@hmac".
+[NTE:EL0508] Nb Top level modules: 1.
+[NTE:EL0509] Max instance depth: 9.
+[NTE:EL0510] Nb instances: 98.
+[NTE:EL0511] Nb leaf instances: 32.
+[INF:UH0706] Creating UHDM Model...
+[INF:UH0707] Elaborating UHDM...
+[ FATAL] : 0
+[ SYNTAX] : 0
+[ ERROR] : 0
+[WARNING] : 0
+[ NOTE] : 10
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/hmac.ys b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/hmac.ys
new file mode 100644
index 00000000..15335df3
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/hmac.ys
@@ -0,0 +1,81 @@
+
+# Yosys/Surelog synthesis script for hmac
+# Read source files
+plugin -i systemverilog
+read_systemverilog -synth -top hmac -y ../../../../.././rtl/ -I../../../../.././rtl/ -I../../../../.. -I/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl +libext+.v+.sv -sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_util_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/pwrmgr_reg_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/pwrmgr_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_ram_1p_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_mubi_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_cipher_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_alert_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_count_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/jtag_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/entropy_src_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/edn_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/top_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_ctrl_reg_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_ctrl_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_phy_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_reg_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/lc_ctrl_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/otp_ctrl_reg_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/otp_ctrl_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/ast_pkg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_core.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_reg_top.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_alert_sender.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_buf.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_diff_decode.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_fifo_sync.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_flop_2sync.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_buf.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_flop.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_flop_2sync.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_intr_hw.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_packer.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_39_32_dec.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_39_32_enc.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_64_57_dec.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_64_57_enc.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg_ext.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/sha2.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/sha2_pad.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_adapter_reg.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_adapter_sram.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_cmd_intg_chk.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_data_integ_dec.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_data_integ_enc.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_err.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_err_resp.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_fifo_sync.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_rsp_intg_gen.sv \
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_socket_1n.sv \
+/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v
+
+# Technology mapping
+hierarchy -top hmac
+
+setattr -set keep 1 w:\clk_i
+
+
+plugin -i synth-rs
+
+synth_rs -post_cleanup 1 -legalize_ram_clk_ports -new_iobuf_map 3 -iofab_map 1 -tech genesis3 -de -goal delay -effort high -carry auto -keep_tribuf -new_dsp19x2 -new_tdp36k -max_lut 17472 -max_reg 34944 -max_device_dsp 56 -max_device_bram 56 -max_device_carry_length 336 -max_dsp 56 -max_bram 56 -max_carry_length 336 -fsm_encoding onehot -de_max_threads -1
+
+write_verilog -noexpr -nodec -norename -v hmac_post_synth.v
+write_blif -param hmac_post_synth.eblif
+
+plugin -i design-edit
+design_edit -tech genesis3 -sdc pin_location_hmac.sdc -json config.json -w wrapper_hmac_post_synth.v wrapper_hmac_post_synth.eblif -pr post_pnr_wrapper_hmac_post_synth.v post_pnr_wrapper_hmac_post_synth.eblif
+write_verilog -noexpr -nodec -norename -v fabric_hmac_post_synth.v
+write_blif -param fabric_hmac_post_synth.eblif
+
+
\ No newline at end of file
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/hmac_synth.log b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/hmac_synth.log
new file mode 100644
index 00000000..90aaa537
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/hmac_synth.log
@@ -0,0 +1,4379 @@
+
+ /----------------------------------------------------------------------------\
+ | yosys -- Yosys Open SYnthesis Suite |
+ | Copyright (C) 2012 - 2024 Claire Xenia Wolf |
+ | Distributed under an ISC-like license, type "license" to see terms |
+ \----------------------------------------------------------------------------/
+
+ Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3)
+
+-- Executing script file `hmac.ys' --
+Warning: Using synlig as yosys plugin is deprecated. It is recommended to build synlig as standalone binary.
+
+1. Executing SystemVerilog frontend.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_util_pkg.sv:34: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:80: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:106: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:209: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:235: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:338: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:364: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:467: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:493: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:71: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:82: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:293: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:304: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:315: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:328: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:337: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:346: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:355: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:364: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:373: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:382: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:391: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_ctrl_pkg.sv:553: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:128: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:322: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:488: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:185: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:253: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:53: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:87: Post-decrementation operations are handled as pre-decrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:97: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:112: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:116: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:122: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:144: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:156: Post-incrementation operations are handled as pre-incrementation.
+Generating RTLIL representation for module `$paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000'.
+Generating RTLIL representation for module `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg'.
+Generating RTLIL representation for module `$paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101'.
+Generating RTLIL representation for module `$paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001'.
+Generating RTLIL representation for module `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp'.
+Generating RTLIL representation for module `$paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_diff_decode\AsyncOn=1'1'.
+Generating RTLIL representation for module `$paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf'.
+Generating RTLIL representation for module `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg'.
+Generating RTLIL representation for module `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender'.
+Generating RTLIL representation for module `\sha2'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1'.
+Generating RTLIL representation for module `\hmac'.
+Generating RTLIL representation for module `$paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1'.
+Generating RTLIL representation for module `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg'.
+Generating RTLIL representation for module `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0'.
+Generating RTLIL representation for module `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk'.
+Generating RTLIL representation for module `$paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0'.
+Generating RTLIL representation for module `$paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1'.
+Generating RTLIL representation for module `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err'.
+Generating RTLIL representation for module `\hmac_core'.
+Warning: reg '\sel_msglen' is assigned in a continuous assignment at /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:179.10-179.67.
+Generating RTLIL representation for module `$paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1'.
+Generating RTLIL representation for module `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top'.
+Generating RTLIL representation for module `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen'.
+Generating RTLIL representation for module `\sha2_pad'.
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:83: Warning: Range select [127:124] out of bounds on signal `\fifo_rdata': Setting all 4 result bits to undef.
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:84: Warning: Range select [127:124] out of bounds on signal `\fifo_rdata': Setting all 4 result bits to undef.
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:85: Warning: Range select [127:124] out of bounds on signal `\fifo_rdata': Setting all 4 result bits to undef.
+Generating RTLIL representation for module `\prim_secded_inv_64_57_dec'.
+Generating RTLIL representation for module `$paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec'.
+Generating RTLIL representation for module `\prim_secded_inv_39_32_dec'.
+Generating RTLIL representation for module `\prim_generic_buf'.
+Generating RTLIL representation for module `\prim_secded_inv_64_57_enc'.
+Generating RTLIL representation for module `$paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc'.
+Generating RTLIL representation for module `\prim_secded_inv_39_32_enc'.
+Generating RTLIL representation for module `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n'.
+
+2. Executing HIERARCHY pass (managing design hierarchy).
+
+2.1. Analyzing design hierarchy..
+Top module: \hmac
+Used module: $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top
+Used module: $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001
+Used module: $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg
+Used module: $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg
+Used module: $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err
+Used module: $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp
+Used module: $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync
+Used module: $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync
+Used module: $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync
+Used module: $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync
+Used module: $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync
+Used module: $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync
+Used module: $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc
+Used module: \prim_secded_inv_39_32_enc
+Used module: \prim_secded_inv_64_57_enc
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec
+Used module: \prim_secded_inv_39_32_dec
+Used module: \prim_secded_inv_64_57_dec
+Used module: \sha2
+Used module: \sha2_pad
+Used module: \hmac_core
+Used module: $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer
+Used module: $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram
+Used module: $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync
+Used module: $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync
+Used module: $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync
+Used module: $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync
+Used module: $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1
+Used module: $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender
+Used module: $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf
+Used module: \prim_generic_buf
+Used module: $paramod\prim_diff_decode\AsyncOn=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+
+2.2. Analyzing design hierarchy..
+Top module: \hmac
+Used module: $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top
+Used module: $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001
+Used module: $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg
+Used module: $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg
+Used module: $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err
+Used module: $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp
+Used module: $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync
+Used module: $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync
+Used module: $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync
+Used module: $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync
+Used module: $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync
+Used module: $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync
+Used module: $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc
+Used module: \prim_secded_inv_39_32_enc
+Used module: \prim_secded_inv_64_57_enc
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec
+Used module: \prim_secded_inv_39_32_dec
+Used module: \prim_secded_inv_64_57_dec
+Used module: \sha2
+Used module: \sha2_pad
+Used module: \hmac_core
+Used module: $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer
+Used module: $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram
+Used module: $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync
+Used module: $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync
+Used module: $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync
+Used module: $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync
+Used module: $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1
+Used module: $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender
+Used module: $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf
+Used module: \prim_generic_buf
+Used module: $paramod\prim_diff_decode\AsyncOn=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Removed 0 unused modules.
+Warning: Resizing cell port $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.gen_rsp_intg.u_rsp_gen.data_i from 6 bits to 57 bits.
+Warning: Resizing cell port $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.u_socket.dev_select_i from 1 bits to 2 bits.
+Warning: Resizing cell port $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.u_chk.data_i from 50 bits to 64 bits.
+Warning: Resizing cell port hmac.u_sha2.digest from 256 bits to 32 bits.
+
+3. Executing synth_rs pass: v0.4.218
+
+3.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v' to AST representation.
+Generating RTLIL representation for module `\inv'.
+Generating RTLIL representation for module `\buff'.
+Generating RTLIL representation for module `\logic_0'.
+Generating RTLIL representation for module `\logic_1'.
+Generating RTLIL representation for module `\gclkbuff'.
+Successfully finished Verilog frontend.
+
+3.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v' to AST representation.
+Generating RTLIL representation for module `\CARRY'.
+Successfully finished Verilog frontend.
+
+3.3. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v' to AST representation.
+Generating RTLIL representation for module `\LATCH'.
+Generating RTLIL representation for module `\LATCHN'.
+Generating RTLIL representation for module `\LATCHR'.
+Generating RTLIL representation for module `\LATCHS'.
+Generating RTLIL representation for module `\LATCHNR'.
+Generating RTLIL representation for module `\LATCHNS'.
+Generating RTLIL representation for module `\LATCHSRE'.
+Generating RTLIL representation for module `\LATCHNSRE'.
+Successfully finished Verilog frontend.
+
+3.4. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v' to AST representation.
+Generating RTLIL representation for module `\DFFRE'.
+Successfully finished Verilog frontend.
+
+3.5. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v' to AST representation.
+Generating RTLIL representation for module `\DFFNRE'.
+Successfully finished Verilog frontend.
+
+3.6. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v' to AST representation.
+Generating RTLIL representation for module `\LUT1'.
+Successfully finished Verilog frontend.
+
+3.7. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v' to AST representation.
+Generating RTLIL representation for module `\LUT2'.
+Successfully finished Verilog frontend.
+
+3.8. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v' to AST representation.
+Generating RTLIL representation for module `\LUT3'.
+Successfully finished Verilog frontend.
+
+3.9. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v' to AST representation.
+Generating RTLIL representation for module `\LUT4'.
+Successfully finished Verilog frontend.
+
+3.10. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v' to AST representation.
+Generating RTLIL representation for module `\LUT5'.
+Successfully finished Verilog frontend.
+
+3.11. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v' to AST representation.
+Generating RTLIL representation for module `\LUT6'.
+Successfully finished Verilog frontend.
+
+3.12. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v' to AST representation.
+Generating RTLIL representation for module `\CLK_BUF'.
+Successfully finished Verilog frontend.
+
+3.13. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v' to AST representation.
+Generating RTLIL representation for module `\O_BUF'.
+Successfully finished Verilog frontend.
+
+3.14. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v' to AST representation.
+Generating RTLIL representation for module `\DSP38'.
+Successfully finished Verilog frontend.
+
+3.15. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v' to AST representation.
+Generating RTLIL representation for module `\TDP_RAM36K'.
+Generating RTLIL representation for module `\TDP_RAM18KX2'.
+Generating RTLIL representation for module `\RS_DSP3'.
+Generating RTLIL representation for module `\DSP19X2'.
+Successfully finished Verilog frontend.
+
+3.16. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v' to AST representation.
+Generating RTLIL representation for module `\TDP_BRAM18'.
+Generating RTLIL representation for module `\BRAM2x18_TDP'.
+Generating RTLIL representation for module `\BRAM2x18_SDP'.
+Generating RTLIL representation for module `\_$_mem_v2_asymmetric'.
+Successfully finished Verilog frontend.
+
+3.17. Executing HIERARCHY pass (managing design hierarchy).
+
+3.17.1. Analyzing design hierarchy..
+Top module: \hmac
+Used module: $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top
+Used module: $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001
+Used module: $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg
+Used module: $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg
+Used module: $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err
+Used module: $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp
+Used module: $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync
+Used module: $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync
+Used module: $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync
+Used module: $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync
+Used module: $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync
+Used module: $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync
+Used module: $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc
+Used module: \prim_secded_inv_39_32_enc
+Used module: \prim_secded_inv_64_57_enc
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec
+Used module: \prim_secded_inv_39_32_dec
+Used module: \prim_secded_inv_64_57_dec
+Used module: \sha2
+Used module: \sha2_pad
+Used module: \hmac_core
+Used module: $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer
+Used module: $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram
+Used module: $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync
+Used module: $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync
+Used module: $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync
+Used module: $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync
+Used module: $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1
+Used module: $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender
+Used module: $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf
+Used module: \prim_generic_buf
+Used module: $paramod\prim_diff_decode\AsyncOn=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+
+3.17.2. Analyzing design hierarchy..
+Top module: \hmac
+Used module: $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top
+Used module: $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001
+Used module: $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg
+Used module: $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg
+Used module: $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err
+Used module: $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp
+Used module: $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync
+Used module: $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync
+Used module: $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync
+Used module: $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync
+Used module: $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync
+Used module: $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync
+Used module: $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc
+Used module: \prim_secded_inv_39_32_enc
+Used module: \prim_secded_inv_64_57_enc
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec
+Used module: \prim_secded_inv_39_32_dec
+Used module: \prim_secded_inv_64_57_dec
+Used module: \sha2
+Used module: \sha2_pad
+Used module: \hmac_core
+Used module: $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer
+Used module: $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram
+Used module: $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync
+Used module: $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync
+Used module: $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync
+Used module: $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync
+Used module: $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1
+Used module: $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender
+Used module: $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf
+Used module: \prim_generic_buf
+Used module: $paramod\prim_diff_decode\AsyncOn=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Removed 0 unused modules.
+
+3.18. Executing PROC pass (convert processes to netlists).
+
+3.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Found and cleaned up 1 empty switch in `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1211$1509'.
+Cleaned up 1 empty switch.
+
+3.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:100$1960 in module $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:154$1946 in module $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:142$1942 in module $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:49$1656 in module sha2_pad.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:298$1648 in module sha2_pad.
+Marked 11 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638 in module sha2_pad.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:135$1636 in module sha2_pad.
+Removed 1 dead cases from process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:69$1635 in module sha2_pad.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:69$1635 in module sha2_pad.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$1616 in module $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$1611 in module $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:61$1596 in module $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1075$1508 in module $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:117$1343 in module $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$1259 in module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:140$1254 in module hmac_core.
+Marked 8 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197 in module hmac_core.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:181$1195 in module hmac_core.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:169$1191 in module hmac_core.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:161$1189 in module hmac_core.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:151$1186 in module hmac_core.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:46$1165 in module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:108$1148 in module $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958 in module $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:126$955 in module $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:125$924 in module $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$916 in module $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$911 in module $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:41$890 in module $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.
+Removed 1 dead cases from process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:159$819 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:138$817 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Removed 1 dead cases from process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:109$816 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:109$816 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 32 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:85$782 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:73$780 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Removed 1 dead cases from process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:60$772 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:60$772 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$770 in module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$759 in module $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$754 in module $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:64$739 in module $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:120$722 in module $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:83$718 in module $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715 in module $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:121$598 in module hmac.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:555$549 in module hmac.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:507$548 in module hmac.
+Marked 9 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:485$537 in module hmac.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:328$532 in module hmac.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:200$495 in module hmac.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:187$493 in module hmac.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:178$489 in module hmac.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:168$487 in module hmac.
+Marked 5 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324 in module sha2.
+Marked 5 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314 in module sha2.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:236$312 in module sha2.
+Marked 7 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:177$307 in module sha2.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:169$305 in module sha2.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:156$303 in module sha2.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:144$299 in module sha2.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:129$294 in module sha2.
+Marked 5 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261 in module sha2.
+Marked 4 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98 in module sha2.
+Removed 1 dead cases from process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72 in module $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.
+Marked 8 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72 in module $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65 in module $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$57 in module $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$52 in module $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$37 in module $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$35 in module $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33 in module $paramod\prim_diff_decode\AsyncOn=1'1.
+Marked 8 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30 in module $paramod\prim_diff_decode\AsyncOn=1'1.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20 in module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:49$9 in module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$7 in module $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$5 in module $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$3 in module $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$1 in module $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.
+Removed a total of 5 dead cases.
+
+3.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
+Removed 26 redundant assignments.
+Promoted 421 assignments to connections.
+
+3.18.4. Executing PROC_INIT pass (extract init attributes).
+
+3.18.5. Executing PROC_ARST pass (detect async resets in processes).
+Found async reset \rst_ni in `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:100$1960'.
+Found async reset \rst_ni in `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:49$1656'.
+Found async reset \rst_ni in `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:298$1648'.
+Found async reset \rst_ni in `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:135$1636'.
+Found async reset \rst_ni in `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$1616'.
+Found async reset \rst_ni in `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$1611'.
+Found async reset \rst_ni in `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:61$1596'.
+Found async reset \rst_ni in `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$1259'.
+Found async reset \rst_ni in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:140$1254'.
+Found async reset \rst_ni in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:181$1195'.
+Found async reset \rst_ni in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:169$1191'.
+Found async reset \rst_ni in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:161$1189'.
+Found async reset \rst_ni in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:151$1186'.
+Found async reset \rst_ni in `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$916'.
+Found async reset \rst_ni in `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$911'.
+Found async reset \rst_ni in `$paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:41$890'.
+Found async reset \rst_ni in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:159$819'.
+Found async reset \rst_ni in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:138$817'.
+Found async reset \rst_ni in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:73$780'.
+Found async reset \rst_ni in `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$770'.
+Found async reset \rst_ni in `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$759'.
+Found async reset \rst_ni in `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$754'.
+Found async reset \rst_ni in `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:64$739'.
+Found async reset \rst_ni in `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:83$718'.
+Found async reset \rst_ni in `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715'.
+Found async reset \rst_ni in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:121$598'.
+Found async reset \rst_ni in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:555$549'.
+Found async reset \rst_ni in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:328$532'.
+Found async reset \rst_ni in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:200$495'.
+Found async reset \rst_ni in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:187$493'.
+Found async reset \rst_ni in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:178$489'.
+Found async reset \rst_ni in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:168$487'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:236$312'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:169$305'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:156$303'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:144$299'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:129$294'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+Found async reset \rst_ni in `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+Found async reset \rst_ni in `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$57'.
+Found async reset \rst_ni in `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$52'.
+Found async reset \rst_ni in `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$37'.
+Found async reset \rst_ni in `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$35'.
+Found async reset \rst_ni in `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33'.
+Found async reset \rst_ni in `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20'.
+Found async reset \rst_ni in `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:49$9'.
+Found async reset \rst_ni in `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$7'.
+Found async reset \rst_ni in `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$5'.
+Found async reset \rst_ni in `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$3'.
+Found async reset \rst_ni in `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$1'.
+
+3.18.6. Executing PROC_ROM pass (convert switches to ROMs).
+Converted 1 switch.
+
+
+3.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
+Creating decoders for process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:100$1960'.
+ 1/2: $0\dev_select_outstanding[1:0]
+ 2/2: $0\num_req_outstanding[8:0]
+Creating decoders for process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:154$1946'.
+ 1/2: $2\tl_t_p[65:0]
+ 2/2: $1\tl_t_p[65:0]
+Creating decoders for process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:142$1942'.
+ 1/3: $3\hfifo_reqready[0:0]
+ 2/3: $2\hfifo_reqready[0:0]
+ 3/3: $1\hfifo_reqready[0:0]
+Creating decoders for process `\prim_secded_inv_39_32_enc.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_enc.sv:12$1912'.
+Creating decoders for process `\prim_secded_inv_64_57_enc.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_enc.sv:12$1890'.
+Creating decoders for process `\prim_secded_inv_39_32_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:14$1800'.
+Creating decoders for process `\prim_secded_inv_64_57_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:14$1659'.
+Creating decoders for process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:49$1656'.
+ 1/1: $0\hash_process_flag[0:0]
+Creating decoders for process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:298$1648'.
+ 1/2: $0\tx_count[63:0] [63:5]
+ 2/2: $0\tx_count[63:0] [4:0]
+Creating decoders for process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+ 1/30: $10\inc_txcount[0:0]
+ 2/30: $11\st_d[2:0]
+ 3/30: $9\inc_txcount[0:0]
+ 4/30: $10\st_d[2:0]
+ 5/30: $9\st_d[2:0]
+ 6/30: $8\st_d[2:0]
+ 7/30: $8\inc_txcount[0:0]
+ 8/30: $7\inc_txcount[0:0]
+ 9/30: $7\st_d[2:0]
+ 10/30: $6\inc_txcount[0:0]
+ 11/30: $6\st_d[2:0]
+ 12/30: $5\st_d[2:0]
+ 13/30: $4\fifo_rready[0:0]
+ 14/30: $5\inc_txcount[0:0]
+ 15/30: $4\shaf_rvalid[0:0]
+ 16/30: $4\st_d[2:0]
+ 17/30: $4\inc_txcount[0:0]
+ 18/30: $3\shaf_rvalid[0:0]
+ 19/30: $3\fifo_rready[0:0]
+ 20/30: $3\st_d[2:0]
+ 21/30: $2\fifo_rready[0:0]
+ 22/30: $3\inc_txcount[0:0]
+ 23/30: $2\shaf_rvalid[0:0]
+ 24/30: $2\st_d[2:0]
+ 25/30: $2\inc_txcount[0:0]
+ 26/30: $1\st_d[2:0]
+ 27/30: $1\inc_txcount[0:0]
+ 28/30: $1\shaf_rvalid[0:0]
+ 29/30: $1\sel_data[2:0]
+ 30/30: $1\fifo_rready[0:0]
+Creating decoders for process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:135$1636'.
+ 1/1: $0\st_q[2:0]
+Creating decoders for process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:69$1635'.
+ 1/2: $2\shaf_rdata[31:0]
+ 2/2: $1\shaf_rdata[31:0]
+Creating decoders for process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$1628'.
+Creating decoders for process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:44$1627'.
+Creating decoders for process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$1621'.
+ 1/1: $0\gen_normal_fifo.storage[12:0]
+Creating decoders for process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$1616'.
+ 1/1: $0\gen_normal_fifo.fifo_rptr[1:0]
+Creating decoders for process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$1611'.
+ 1/1: $0\gen_normal_fifo.fifo_wptr[1:0]
+Creating decoders for process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:61$1596'.
+ 1/1: $0\intg_err_q[0:0]
+Creating decoders for process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1211$1509'.
+Creating decoders for process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1075$1508'.
+ 1/6: $1\reg_rdata_next[31:0] [31:9]
+ 2/6: $1\reg_rdata_next[31:0] [3]
+ 3/6: $1\reg_rdata_next[31:0] [2]
+ 4/6: $1\reg_rdata_next[31:0] [0]
+ 5/6: $1\reg_rdata_next[31:0] [8:4]
+ 6/6: $1\reg_rdata_next[31:0] [1]
+Creating decoders for process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:968$1372'.
+Creating decoders for process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:934$1344'.
+Creating decoders for process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:117$1343'.
+ 1/2: $2\reg_steer[0:0]
+ 2/2: $1\reg_steer[0:0]
+Creating decoders for process `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$1259'.
+ 1/1: $0\q_o[0:0]
+Creating decoders for process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:140$1254'.
+ 1/2: $0\txcount[63:0] [63:5]
+ 2/2: $0\txcount[63:0] [4:0]
+Creating decoders for process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+ 1/31: $4\hmac_sha_rvalid[0:0]
+ 2/31: $8\st_d[2:0]
+ 3/31: $3\hash_start[0:0]
+ 4/31: $3\round_d[0:0]
+ 5/31: $3\update_round[0:0]
+ 6/31: $3\clr_txcount[0:0]
+ 7/31: $7\st_d[2:0]
+ 8/31: $6\st_d[2:0]
+ 9/31: $5\st_d[2:0]
+ 10/31: $2\hash_process[0:0]
+ 11/31: $3\hmac_sha_rvalid[0:0]
+ 12/31: $4\st_d[2:0]
+ 13/31: $2\hmac_sha_rvalid[0:0]
+ 14/31: $3\st_d[2:0]
+ 15/31: $2\hash_start[0:0]
+ 16/31: $2\round_d[0:0]
+ 17/31: $2\update_round[0:0]
+ 18/31: $2\clr_txcount[0:0]
+ 19/31: $2\st_d[2:0]
+ 20/31: $1\st_d[2:0]
+ 21/31: $1\round_d[0:0]
+ 22/31: $1\update_round[0:0]
+ 23/31: $1\clr_txcount[0:0]
+ 24/31: $1\hash_start[0:0]
+ 25/31: $1\clr_fifo_wdata_sel[0:0]
+ 26/31: $1\sel_rdata[1:0]
+ 27/31: $1\hmac_sha_rvalid[0:0]
+ 28/31: $1\hmac_hash_done[0:0]
+ 29/31: $1\fifo_wsel[0:0]
+ 30/31: $1\fifo_wvalid[0:0]
+ 31/31: $1\hash_process[0:0]
+Creating decoders for process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:181$1195'.
+ 1/1: $0\st_q[2:0]
+Creating decoders for process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:169$1191'.
+ 1/1: $0\fifo_wdata_sel[2:0]
+Creating decoders for process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:161$1189'.
+ 1/1: $0\round_q[0:0]
+Creating decoders for process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:151$1186'.
+ 1/1: $0\reg_hash_process_flag[0:0]
+Creating decoders for process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:46$1165'.
+ 1/6: $2\fulldata_chk[0:0]
+ 2/6: $2\mask_chk[0:0]
+ 3/6: $2\addr_sz_chk[0:0]
+ 4/6: $1\fulldata_chk[0:0]
+ 5/6: $1\mask_chk[0:0]
+ 6/6: $1\addr_sz_chk[0:0]
+Creating decoders for process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:108$1148'.
+ 1/3: $3\d_valid[0:0]
+ 2/3: $2\d_valid[0:0]
+ 3/3: $1\d_valid[0:0]
+Creating decoders for process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+Creating decoders for process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+ 1/11: $1$fordecl_block29.i[31:0]$968
+ 2/11: $1\wdata_int[31:0]
+ 3/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$949[31:0]$976
+ 4/11: $1\wmask_int[31:0]
+ 5/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$948[31:0]$975
+ 6/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$947[31:0]$974
+ 7/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$946[31:0]$973
+ 8/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$945[31:0]$972
+ 9/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$944[31:0]$971
+ 10/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$943[31:0]$970
+ 11/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$942[31:0]$969
+Creating decoders for process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:126$955'.
+ 1/2: $2\d_error[0:0]
+ 2/2: $1\d_error[0:0]
+Creating decoders for process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:125$924'.
+ 1/2: $1$lookahead\gen_normal_fifo.storage$923[575:0]$928
+ 2/2: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:127$897[31:0]$927
+Creating decoders for process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$916'.
+ 1/1: $0\gen_normal_fifo.fifo_rptr[4:0]
+Creating decoders for process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$911'.
+ 1/1: $0\gen_normal_fifo.fifo_wptr[4:0]
+Creating decoders for process `$paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:41$890'.
+ 1/1: $0\intr_o[0:0]
+Creating decoders for process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$883'.
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:50$838'.
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821'.
+ 1/7: $2\flush_done[0:0]
+ 2/7: $2\flush_valid[0:0]
+ 3/7: $3\flush_st_next[0:0]
+ 4/7: $2\flush_st_next[0:0]
+ 5/7: $1\flush_st_next[0:0]
+ 6/7: $1\flush_done[0:0]
+ 7/7: $1\flush_valid[0:0]
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:159$819'.
+ 1/1: $0\flush_st[0:0]
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:138$817'.
+ 1/2: $0\stored_mask[63:0]
+ 2/2: $0\stored_data[63:0]
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:109$816'.
+ 1/2: $1\stored_mask_next[63:0]
+ 2/2: $1\stored_data_next[63:0]
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:85$782'.
+ 1/32: $32\lod_idx[4:0]
+ 2/32: $31\lod_idx[4:0]
+ 3/32: $30\lod_idx[4:0]
+ 4/32: $29\lod_idx[4:0]
+ 5/32: $28\lod_idx[4:0]
+ 6/32: $27\lod_idx[4:0]
+ 7/32: $26\lod_idx[4:0]
+ 8/32: $25\lod_idx[4:0]
+ 9/32: $24\lod_idx[4:0]
+ 10/32: $23\lod_idx[4:0]
+ 11/32: $22\lod_idx[4:0]
+ 12/32: $21\lod_idx[4:0]
+ 13/32: $20\lod_idx[4:0]
+ 14/32: $19\lod_idx[4:0]
+ 15/32: $18\lod_idx[4:0]
+ 16/32: $17\lod_idx[4:0]
+ 17/32: $16\lod_idx[4:0]
+ 18/32: $15\lod_idx[4:0]
+ 19/32: $14\lod_idx[4:0]
+ 20/32: $13\lod_idx[4:0]
+ 21/32: $12\lod_idx[4:0]
+ 22/32: $11\lod_idx[4:0]
+ 23/32: $10\lod_idx[4:0]
+ 24/32: $9\lod_idx[4:0]
+ 25/32: $8\lod_idx[4:0]
+ 26/32: $7\lod_idx[4:0]
+ 27/32: $6\lod_idx[4:0]
+ 28/32: $5\lod_idx[4:0]
+ 29/32: $4\lod_idx[4:0]
+ 30/32: $3\lod_idx[4:0]
+ 31/32: $2\lod_idx[4:0]
+ 32/32: $1\lod_idx[4:0]
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:73$780'.
+ 1/1: $0\pos[6:0]
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:60$772'.
+ 1/1: $1\pos_next[6:0]
+Creating decoders for process `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$770'.
+ 1/1: $0\q_o[0:0]
+Creating decoders for process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$764'.
+ 1/1: $0\gen_normal_fifo.storage[32:0]
+Creating decoders for process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$759'.
+ 1/1: $0\gen_normal_fifo.fifo_rptr[1:0]
+Creating decoders for process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$754'.
+ 1/1: $0\gen_normal_fifo.fifo_wptr[1:0]
+Creating decoders for process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:64$739'.
+ 1/1: $0\outstanding[0:0]
+Creating decoders for process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:120$722'.
+ 1/1: $1\addr_align_err[0:0]
+Creating decoders for process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:83$718'.
+ 1/2: $0\error[0:0]
+ 2/2: $0\rdata[31:0]
+Creating decoders for process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715'.
+ 1/3: $0\rspop[2:0]
+ 2/3: $0\reqsz[1:0]
+ 3/3: $0\reqid[7:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:121$598'.
+ 1/11: $0\secret_key[255:0] [255:224]
+ 2/11: $0\secret_key[255:0] [223:192]
+ 3/11: $0\secret_key[255:0] [191:160]
+ 4/11: $0\secret_key[255:0] [159:128]
+ 5/11: $0\secret_key[255:0] [127:96]
+ 6/11: $0\secret_key[255:0] [95:64]
+ 7/11: $0\secret_key[255:0] [63:32]
+ 8/11: $0\secret_key[255:0] [31:0]
+ 9/11: $2$fordecl_block26.i[31:0]$602
+ 10/11: $1$fordecl_block26.i[31:0]$601
+ 11/11: $3$fordecl_block26.i[31:0]$604
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:555$549'.
+ 1/1: $0\idle_o[0:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:507$548'.
+ 1/1: $1\err_code[31:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:485$537'.
+ 1/10: $9\update_seckey_inprocess[0:0]
+ 2/10: $8\update_seckey_inprocess[0:0]
+ 3/10: $7\update_seckey_inprocess[0:0]
+ 4/10: $6\update_seckey_inprocess[0:0]
+ 5/10: $5\update_seckey_inprocess[0:0]
+ 6/10: $4\update_seckey_inprocess[0:0]
+ 7/10: $3\update_seckey_inprocess[0:0]
+ 8/10: $2\update_seckey_inprocess[0:0]
+ 9/10: $1$fordecl_block28.i[31:0]$539
+ 10/10: $1\update_seckey_inprocess[0:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:328$532'.
+ 1/1: $0\message_length[63:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:320$498'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:200$495'.
+ 1/1: $0\fifo_empty_q[0:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:187$493'.
+ 1/1: $0\msg_allowed[0:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:178$489'.
+ 1/1: $0\cfg_reg[7:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:168$487'.
+ 1/1: $0\cfg_block[0:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ 1/96: $5\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$result[31:0]$425
+ 2/96: $5\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum1[31:0]$431
+ 3/96: $5\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.$result[31:0]$442
+ 4/96: $5\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.v[31:0]$443
+ 5/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.$result[31:0]$440
+ 6/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.v[31:0]$441
+ 7/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.$result[31:0]$438
+ 8/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.v[31:0]$439
+ 9/96: $5\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum0[31:0]$430
+ 10/96: $5\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.$result[31:0]$436
+ 11/96: $5\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.v[31:0]$437
+ 12/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.$result[31:0]$434
+ 13/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.v[31:0]$435
+ 14/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.$result[31:0]$432
+ 15/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.v[31:0]$433
+ 16/96: $5\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_14[31:0]$429
+ 17/96: $5\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_9[31:0]$428
+ 18/96: $5\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_1[31:0]$427
+ 19/96: $5\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_0[31:0]$426
+ 20/96: $4\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.v[31:0]$424
+ 21/96: $4\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.$result[31:0]$423
+ 22/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.v[31:0]$422
+ 23/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.$result[31:0]$421
+ 24/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.v[31:0]$420
+ 25/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.$result[31:0]$419
+ 26/96: $4\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.v[31:0]$418
+ 27/96: $4\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.$result[31:0]$417
+ 28/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.v[31:0]$416
+ 29/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.$result[31:0]$415
+ 30/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.v[31:0]$414
+ 31/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.$result[31:0]$413
+ 32/96: $4\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum1[31:0]$412
+ 33/96: $4\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum0[31:0]$411
+ 34/96: $4\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_14[31:0]$410
+ 35/96: $4\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_9[31:0]$409
+ 36/96: $4\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_1[31:0]$408
+ 37/96: $4\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_0[31:0]$407
+ 38/96: $4\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$result[31:0]$406
+ 39/96: $3\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.v[31:0]$403
+ 40/96: $3\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.$result[31:0]$402
+ 41/96: $3\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.v[31:0]$401
+ 42/96: $3\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.$result[31:0]$400
+ 43/96: $3\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.v[31:0]$399
+ 44/96: $3\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.$result[31:0]$398
+ 45/96: $3\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.v[31:0]$397
+ 46/96: $3\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.$result[31:0]$396
+ 47/96: $3\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.v[31:0]$395
+ 48/96: $3\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.$result[31:0]$394
+ 49/96: $3\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.v[31:0]$393
+ 50/96: $3\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.$result[31:0]$392
+ 51/96: $3\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum1[31:0]$391
+ 52/96: $3\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum0[31:0]$390
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+ 59/96: $2\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.$result[31:0]$381
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+ 66/96: $2\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.v[31:0]$374
+ 67/96: $2\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.$result[31:0]$373
+ 68/96: $2\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.v[31:0]$372
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+ 70/96: $2\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum1[31:0]$370
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+ 73/96: $2\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_9[31:0]$367
+ 74/96: $2\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_1[31:0]$366
+ 75/96: $2\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_0[31:0]$365
+ 76/96: $2\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$result[31:0]$364
+ 77/96: $1\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.v[31:0]$363
+ 78/96: $1\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.$result[31:0]$362
+ 79/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.v[31:0]$361
+ 80/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.$result[31:0]$360
+ 81/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.v[31:0]$359
+ 82/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.$result[31:0]$358
+ 83/96: $1\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.v[31:0]$357
+ 84/96: $1\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.$result[31:0]$356
+ 85/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.v[31:0]$355
+ 86/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.$result[31:0]$354
+ 87/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.v[31:0]$353
+ 88/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.$result[31:0]$352
+ 89/96: $1\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum1[31:0]$351
+ 90/96: $1\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum0[31:0]$350
+ 91/96: $1\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_14[31:0]$349
+ 92/96: $1\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_9[31:0]$348
+ 93/96: $1\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_1[31:0]$347
+ 94/96: $1\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_0[31:0]$346
+ 95/96: $1\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$result[31:0]$345
+ 96/96: $0\w[511:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+ 1/11: $4\sha_st_d[1:0]
+ 2/11: $3\init_hash[0:0]
+ 3/11: $3\sha_st_d[1:0]
+ 4/11: $2\calculate_next_w[0:0]
+ 5/11: $2\sha_st_d[1:0]
+ 6/11: $2\init_hash[0:0]
+ 7/11: $1\sha_st_d[1:0]
+ 8/11: $1\init_hash[0:0]
+ 9/11: $1\update_digest[0:0]
+ 10/11: $1\run_hash[0:0]
+ 11/11: $1\calculate_next_w[0:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:236$312'.
+ 1/1: $0\sha_st_q[1:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:177$307'.
+ 1/13: $7\fifo_st_d[1:0]
+ 2/13: $2\hash_done_next[0:0]
+ 3/13: $6\fifo_st_d[1:0]
+ 4/13: $4\update_w_from_fifo[0:0]
+ 5/13: $5\fifo_st_d[1:0]
+ 6/13: $3\update_w_from_fifo[0:0]
+ 7/13: $4\fifo_st_d[1:0]
+ 8/13: $2\update_w_from_fifo[0:0]
+ 9/13: $3\fifo_st_d[1:0]
+ 10/13: $2\fifo_st_d[1:0]
+ 11/13: $1\fifo_st_d[1:0]
+ 12/13: $1\hash_done_next[0:0]
+ 13/13: $1\update_w_from_fifo[0:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:169$305'.
+ 1/1: $0\fifo_st_q[1:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:156$303'.
+ 1/1: $0\hash_done[0:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:144$299'.
+ 1/1: $0\w_index[3:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:129$294'.
+ 1/1: $0\round[5:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+ 1/19: $5$fordecl_block40.i[31:0]$285
+ 2/19: $0\digest[31:0] [31:8]
+ 3/19: $3$fordecl_block39.i[31:0]$280
+ 4/19: $3$fordecl_block40.i[31:0]$281
+ 5/19: $2$fordecl_block38.i[31:0]$269
+ 6/19: $0\digest[31:0] [7]
+ 7/19: $0\digest[31:0] [6]
+ 8/19: $0\digest[31:0] [5]
+ 9/19: $0\digest[31:0] [4]
+ 10/19: $0\digest[31:0] [3]
+ 11/19: $0\digest[31:0] [2]
+ 12/19: $0\digest[31:0] [1]
+ 13/19: $0\digest[31:0] [0]
+ 14/19: $4$fordecl_block40.i[31:0]$284
+ 15/19: $2$fordecl_block39.i[31:0]$270
+ 16/19: $1$fordecl_block40.i[31:0]$268
+ 17/19: $1$fordecl_block39.i[31:0]$267
+ 18/19: $1$fordecl_block38.i[31:0]$266
+ 19/19: $2$fordecl_block40.i[31:0]$271
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ 1/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [7]
+ 2/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [0]
+ 3/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [1]
+ 4/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [2]
+ 5/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [3]
+ 6/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [4]
+ 7/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [5]
+ 8/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [6]
+ 9/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.temp2[31:0]$208
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+ 11/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.sigma_0[31:0]$203
+ 12/105: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$90.$result[31:0]$219
+ 13/105: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$90.v[31:0]$220
+ 14/105: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$89.$result[31:0]$217
+ 15/105: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$89.v[31:0]$218
+ 16/105: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$88.$result[31:0]$215
+ 17/105: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$88.v[31:0]$216
+ 18/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.temp1[31:0]$207
+ 19/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.ch[31:0]$205
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+Creating decoders for process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
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+ 25/26: $1\ping_clr[0:0]
+ 26/26: $1\alert_clr[0:0]
+Creating decoders for process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+ 1/5: $0\ping_set_q[0:0]
+ 2/5: $0\alert_set_q[0:0]
+ 3/5: $0\alert_nq[0:0]
+ 4/5: $0\alert_pq[0:0]
+ 5/5: $0\state_q[2:0]
+Creating decoders for process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$62'.
+ 1/1: $0\gen_normal_fifo.storage[4:0]
+Creating decoders for process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$57'.
+ 1/1: $0\gen_normal_fifo.fifo_rptr[1:0]
+Creating decoders for process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$52'.
+ 1/1: $0\gen_normal_fifo.fifo_wptr[1:0]
+Creating decoders for process `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$37'.
+ 1/1: $0\qe[0:0]
+Creating decoders for process `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$35'.
+ 1/1: $0\q[0:0]
+Creating decoders for process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33'.
+ 1/4: $0\level_q[0:0]
+ 2/4: $0\gen_async.diff_nq[0:0]
+ 3/4: $0\gen_async.diff_pq[0:0]
+ 4/4: $0\gen_async.state_q[1:0]
+Creating decoders for process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+ 1/25: $5\sigint_o[0:0]
+ 2/25: $5\gen_async.state_d[1:0]
+ 3/25: $6\rise_o[0:0]
+ 4/25: $6\fall_o[0:0]
+ 5/25: $5\fall_o[0:0]
+ 6/25: $5\rise_o[0:0]
+ 7/25: $3\level_d[0:0]
+ 8/25: $4\gen_async.state_d[1:0]
+ 9/25: $4\sigint_o[0:0]
+ 10/25: $3\gen_async.state_d[1:0]
+ 11/25: $3\sigint_o[0:0]
+ 12/25: $4\rise_o[0:0]
+ 13/25: $4\fall_o[0:0]
+ 14/25: $3\fall_o[0:0]
+ 15/25: $3\rise_o[0:0]
+ 16/25: $2\fall_o[0:0]
+ 17/25: $2\rise_o[0:0]
+ 18/25: $2\level_d[0:0]
+ 19/25: $2\gen_async.state_d[1:0]
+ 20/25: $2\sigint_o[0:0]
+ 21/25: $1\gen_async.state_d[1:0]
+ 22/25: $1\sigint_o[0:0]
+ 23/25: $1\fall_o[0:0]
+ 24/25: $1\rise_o[0:0]
+ 25/25: $1\level_d[0:0]
+Creating decoders for process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20'.
+ 1/3: $0\err_req_pending[0:0]
+ 2/3: $0\err_size[1:0]
+ 3/3: $0\err_source[7:0]
+Creating decoders for process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:49$9'.
+ 1/1: $0\err_rsp_pending[0:0]
+Creating decoders for process `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$7'.
+ 1/1: $0\qe[0:0]
+Creating decoders for process `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$5'.
+ 1/1: $0\q[0:0]
+Creating decoders for process `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$3'.
+ 1/1: $0\qe[0:0]
+Creating decoders for process `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$1'.
+ 1/1: $0\q[31:0]
+
+3.18.8. Executing PROC_DLATCH pass (convert process syncs to latches).
+No latch inferred for signal `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.\tl_t_p' from process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:154$1946'.
+No latch inferred for signal `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$fordecl_block44.idx' from process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:154$1946'.
+No latch inferred for signal `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.\hfifo_reqready' from process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:142$1942'.
+No latch inferred for signal `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$fordecl_block43.idx' from process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:142$1942'.
+No latch inferred for signal `\prim_secded_inv_39_32_enc.\data_o' from process `\prim_secded_inv_39_32_enc.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_enc.sv:12$1912'.
+No latch inferred for signal `\prim_secded_inv_64_57_enc.\data_o' from process `\prim_secded_inv_64_57_enc.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_enc.sv:12$1890'.
+No latch inferred for signal `\prim_secded_inv_39_32_dec.\data_o' from process `\prim_secded_inv_39_32_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:14$1800'.
+No latch inferred for signal `\prim_secded_inv_39_32_dec.\err_o' from process `\prim_secded_inv_39_32_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:14$1800'.
+No latch inferred for signal `\prim_secded_inv_39_32_dec.\syndrome_o' from process `\prim_secded_inv_39_32_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:14$1800'.
+No latch inferred for signal `\prim_secded_inv_64_57_dec.\data_o' from process `\prim_secded_inv_64_57_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:14$1659'.
+No latch inferred for signal `\prim_secded_inv_64_57_dec.\err_o' from process `\prim_secded_inv_64_57_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:14$1659'.
+No latch inferred for signal `\prim_secded_inv_64_57_dec.\syndrome_o' from process `\prim_secded_inv_64_57_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:14$1659'.
+No latch inferred for signal `\sha2_pad.\shaf_rvalid' from process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+No latch inferred for signal `\sha2_pad.\fifo_rready' from process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+No latch inferred for signal `\sha2_pad.\inc_txcount' from process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+No latch inferred for signal `\sha2_pad.\st_d' from process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+No latch inferred for signal `\sha2_pad.\sel_data' from process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+No latch inferred for signal `\sha2_pad.\shaf_rdata' from process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:69$1635'.
+No latch inferred for signal `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.\tlul_pkg::extract_d2h_rsp_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:23$1624.$result' from process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$1628'.
+No latch inferred for signal `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.\tlul_pkg::extract_d2h_rsp_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:23$1625.$result' from process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$1628'.
+No latch inferred for signal `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.\tlul_pkg::extract_d2h_rsp_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:23$1625.tl' from process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$1628'.
+No latch inferred for signal `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.\tlul_pkg::extract_d2h_rsp_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:23$1625.$unnamed_block$72.payload' from process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$1628'.
+No latch inferred for signal `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.\tlul_pkg::extract_d2h_rsp_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:23$1625.$unnamed_block$72.unused_tlul' from process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$1628'.
+No latch inferred for signal `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.\tl_o' from process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:44$1627'.
+No latch inferred for signal `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.\reg_busy_sel' from process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1211$1509'.
+No latch inferred for signal `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.\reg_rdata_next' from process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1075$1508'.
+No latch inferred for signal `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.\wr_err' from process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:968$1372'.
+No latch inferred for signal `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.\addr_hit' from process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:934$1344'.
+No latch inferred for signal `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.\reg_steer' from process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:117$1343'.
+No latch inferred for signal `\hmac_core.\hash_start' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\hash_process' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\fifo_wvalid' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\fifo_wsel' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\hmac_hash_done' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\clr_txcount' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\hmac_sha_rvalid' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\sel_rdata' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\update_round' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\round_d' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\st_d' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\clr_fifo_wdata_sel' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.\addr_sz_chk' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:46$1165'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.\mask_chk' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:46$1165'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.\fulldata_chk' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:46$1165'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.\d_valid' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:108$1148'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.\rmask' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$fordecl_block30.i' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:254$950' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:254$951' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:254$952' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:254$953' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.\wmask_int' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.\wdata_int' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$fordecl_block29.i' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$942' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$943' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$944' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$945' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$946' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$947' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$948' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$949' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.\d_error' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:126$955'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.\tlul_pkg::extract_h2d_cmd_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:14$872.$result' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$883'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.\tlul_pkg::extract_h2d_cmd_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:14$873.$result' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$883'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.\tlul_pkg::extract_h2d_cmd_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:14$873.tl' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$883'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.\tlul_pkg::extract_h2d_cmd_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:14$873.$unnamed_block$71.payload' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$883'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.\tlul_pkg::extract_h2d_cmd_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:14$873.$unnamed_block$71.unused_tlul' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$883'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\inmask_ones' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:50$838'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$fordecl_block31.i' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:50$838'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\flush_valid' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\flush_done' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\flush_st_next' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\stored_data_next' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:109$816'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\stored_mask_next' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:109$816'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\lod_idx' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:85$782'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$fordecl_block32.i' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:85$782'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\pos_next' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:60$772'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\pos_with_input' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:60$772'.
+No latch inferred for signal `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.\addr_align_err' from process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:120$722'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$475.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$486.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$486.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$486.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$486.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$486.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$486.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$486.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$474.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$485.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$485.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$485.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$485.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$485.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$485.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$485.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:261$473.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:261$484.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:261$484.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:261$484.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:261$484.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:261$484.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:261$484.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$472.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$483.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$483.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$483.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$483.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$483.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$483.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$483.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$471.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$482.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$482.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$482.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$482.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$482.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$482.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$482.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$470.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$481.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$481.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$481.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$481.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$481.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$481.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$481.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$469.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$480.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$480.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$480.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$480.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$480.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$480.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$480.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$468.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$479.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$479.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$479.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$479.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$479.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$479.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$479.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$467.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$478.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$478.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$478.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$478.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$478.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$478.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$478.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$466.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$477.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$477.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$477.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$477.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$477.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$477.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$477.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$465.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$476.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$476.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$476.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$476.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$476.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$476.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$476.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\err_code' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:507$548'.
+No latch inferred for signal `\hmac.\update_seckey_inprocess' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:485$537'.
+No latch inferred for signal `\hmac.$fordecl_block28.i' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:485$537'.
+No latch inferred for signal `\hmac.\wmask_ones' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:320$498'.
+No latch inferred for signal `\hmac.$fordecl_block27.i' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:320$498'.
+No latch inferred for signal `\sha2.\calculate_next_w' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+No latch inferred for signal `\sha2.\init_hash' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+No latch inferred for signal `\sha2.\run_hash' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+No latch inferred for signal `\sha2.\update_digest' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+No latch inferred for signal `\sha2.\sha_st_d' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+No latch inferred for signal `\sha2.\update_w_from_fifo' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:177$307'.
+No latch inferred for signal `\sha2.\hash_done_next' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:177$307'.
+No latch inferred for signal `\sha2.\fifo_st_d' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:177$307'.
+No latch inferred for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\state_d' from process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+No latch inferred for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\alert_p' from process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+No latch inferred for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\alert_n' from process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+No latch inferred for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\alert_clr' from process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+No latch inferred for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\ping_clr' from process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+No latch inferred for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\level_d' from process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+No latch inferred for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\rise_o' from process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+No latch inferred for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\fall_o' from process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+No latch inferred for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\sigint_o' from process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+No latch inferred for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\gen_async.state_d' from process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+
+3.18.9. Executing PROC_DFF pass (convert process syncs to FFs).
+Creating register for signal `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.\num_req_outstanding' using process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:100$1960'.
+ created $adff cell `$procdff$5309' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.\dev_select_outstanding' using process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:100$1960'.
+ created $adff cell `$procdff$5310' with positive edge clock and negative level reset.
+Creating register for signal `\sha2_pad.\hash_process_flag' using process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:49$1656'.
+ created $adff cell `$procdff$5311' with positive edge clock and negative level reset.
+Creating register for signal `\sha2_pad.\tx_count' using process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:298$1648'.
+ created $adff cell `$procdff$5312' with positive edge clock and negative level reset.
+Creating register for signal `\sha2_pad.\st_q' using process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:135$1636'.
+ created $adff cell `$procdff$5313' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.\gen_normal_fifo.storage' using process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$1621'.
+ created $dff cell `$procdff$5314' with positive edge clock.
+Creating register for signal `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.\gen_normal_fifo.fifo_rptr' using process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$1616'.
+ created $adff cell `$procdff$5315' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.\gen_normal_fifo.fifo_wptr' using process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$1611'.
+ created $adff cell `$procdff$5316' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.\intg_err_q' using process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:61$1596'.
+ created $adff cell `$procdff$5317' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.\q_o' using process `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$1259'.
+ created $adff cell `$procdff$5318' with positive edge clock and negative level reset.
+Creating register for signal `\hmac_core.\txcount' using process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:140$1254'.
+ created $adff cell `$procdff$5319' with positive edge clock and negative level reset.
+Creating register for signal `\hmac_core.\st_q' using process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:181$1195'.
+ created $adff cell `$procdff$5320' with positive edge clock and negative level reset.
+Creating register for signal `\hmac_core.\fifo_wdata_sel' using process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:169$1191'.
+ created $adff cell `$procdff$5321' with positive edge clock and negative level reset.
+Creating register for signal `\hmac_core.\round_q' using process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:161$1189'.
+ created $adff cell `$procdff$5322' with positive edge clock and negative level reset.
+Creating register for signal `\hmac_core.\reg_hash_process_flag' using process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:151$1186'.
+ created $adff cell `$procdff$5323' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.\gen_normal_fifo.storage' using process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:125$924'.
+ created $dff cell `$procdff$5324' with positive edge clock.
+Creating register for signal `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:127$897' using process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:125$924'.
+ created $dff cell `$procdff$5325' with positive edge clock.
+Creating register for signal `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$lookahead\gen_normal_fifo.storage$923' using process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:125$924'.
+ created $dff cell `$procdff$5326' with positive edge clock.
+Creating register for signal `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.\gen_normal_fifo.fifo_rptr' using process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$916'.
+ created $adff cell `$procdff$5327' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.\gen_normal_fifo.fifo_wptr' using process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$911'.
+ created $adff cell `$procdff$5328' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.\intr_o' using process `$paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:41$890'.
+ created $adff cell `$procdff$5329' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\flush_st' using process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:159$819'.
+ created $adff cell `$procdff$5330' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\stored_data' using process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:138$817'.
+ created $adff cell `$procdff$5331' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\stored_mask' using process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:138$817'.
+ created $adff cell `$procdff$5332' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\pos' using process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:73$780'.
+ created $adff cell `$procdff$5333' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.\q_o' using process `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$770'.
+ created $adff cell `$procdff$5334' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.\gen_normal_fifo.storage' using process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$764'.
+ created $dff cell `$procdff$5335' with positive edge clock.
+Creating register for signal `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.\gen_normal_fifo.fifo_rptr' using process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$759'.
+ created $adff cell `$procdff$5336' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.\gen_normal_fifo.fifo_wptr' using process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$754'.
+ created $adff cell `$procdff$5337' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.\outstanding' using process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:64$739'.
+ created $adff cell `$procdff$5338' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.\rdata' using process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:83$718'.
+ created $adff cell `$procdff$5339' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.\error' using process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:83$718'.
+ created $adff cell `$procdff$5340' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.\reqid' using process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715'.
+ created $adff cell `$procdff$5341' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.\reqsz' using process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715'.
+ created $adff cell `$procdff$5342' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.\rspop' using process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715'.
+ created $adff cell `$procdff$5343' with positive edge clock and negative level reset.
+Creating register for signal `\hmac.\secret_key' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:121$598'.
+ created $adff cell `$procdff$5344' with positive edge clock and negative level reset.
+Creating register for signal `\hmac.$fordecl_block26.i' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:121$598'.
+ created $dff cell `$procdff$5347' with positive edge clock.
+Creating register for signal `\hmac.\idle_o' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:555$549'.
+ created $adff cell `$procdff$5348' with positive edge clock and negative level reset.
+Creating register for signal `\hmac.\message_length' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:328$532'.
+ created $adff cell `$procdff$5349' with positive edge clock and negative level reset.
+Creating register for signal `\hmac.\fifo_empty_q' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:200$495'.
+ created $adff cell `$procdff$5350' with positive edge clock and negative level reset.
+Creating register for signal `\hmac.\msg_allowed' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:187$493'.
+ created $adff cell `$procdff$5351' with positive edge clock and negative level reset.
+Creating register for signal `\hmac.\cfg_reg' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:178$489'.
+ created $adff cell `$procdff$5352' with positive edge clock and negative level reset.
+Creating register for signal `\hmac.\cfg_block' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:168$487'.
+ created $adff cell `$procdff$5353' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\w' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5354' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5355' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_0' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5356' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_1' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5357' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_9' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5358' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_14' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5359' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum0' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $dff cell `$procdff$5362' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum1' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $dff cell `$procdff$5365' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5366' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5367' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5368' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5369' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5370' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5371' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5372' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5373' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5374' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5375' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5376' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5377' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\sha_st_q' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:236$312'.
+ created $adff cell `$procdff$5378' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\fifo_st_q' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:169$305'.
+ created $adff cell `$procdff$5379' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hash_done' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:156$303'.
+ created $adff cell `$procdff$5380' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\w_index' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:144$299'.
+ created $adff cell `$procdff$5381' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\round' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:129$294'.
+ created $adff cell `$procdff$5382' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\digest' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+ created $adff cell `$procdff$5383' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.$fordecl_block38.i' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+ created $dff cell `$procdff$5386' with positive edge clock.
+Creating register for signal `\sha2.$fordecl_block39.i' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+ created $dff cell `$procdff$5389' with positive edge clock.
+Creating register for signal `\sha2.$fordecl_block40.i' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+ created $dff cell `$procdff$5392' with positive edge clock.
+Creating register for signal `\sha2.\hash' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5393' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\compress_round.$fordecl_block37.i' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $dff cell `$procdff$5396' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5397' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.w' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5398' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.k' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5399' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.h_i' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5400' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.sigma_0' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $dff cell `$procdff$5403' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.sigma_1' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $dff cell `$procdff$5406' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.ch' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $dff cell `$procdff$5409' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.maj' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $dff cell `$procdff$5412' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.temp1' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $dff cell `$procdff$5415' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.temp2' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $dff cell `$procdff$5418' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$85.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5419' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$85.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5420' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$86.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5421' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$86.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5422' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$87.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5423' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$87.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5424' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$88.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5425' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$88.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5426' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$89.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5427' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$89.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5428' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$90.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5429' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$90.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5430' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\state_q' using process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+ created $adff cell `$procdff$5431' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\alert_pq' using process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+ created $adff cell `$procdff$5432' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\alert_nq' using process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+ created $adff cell `$procdff$5433' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\alert_set_q' using process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+ created $adff cell `$procdff$5434' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\ping_set_q' using process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+ created $adff cell `$procdff$5435' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.\gen_normal_fifo.storage' using process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$62'.
+ created $dff cell `$procdff$5436' with positive edge clock.
+Creating register for signal `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.\gen_normal_fifo.fifo_rptr' using process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$57'.
+ created $adff cell `$procdff$5437' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.\gen_normal_fifo.fifo_wptr' using process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$52'.
+ created $adff cell `$procdff$5438' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.\qe' using process `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$37'.
+ created $adff cell `$procdff$5439' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.\q' using process `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$35'.
+ created $adff cell `$procdff$5440' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\level_q' using process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33'.
+ created $adff cell `$procdff$5441' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\gen_async.state_q' using process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33'.
+ created $adff cell `$procdff$5442' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\gen_async.diff_pq' using process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33'.
+ created $adff cell `$procdff$5443' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\gen_async.diff_nq' using process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33'.
+ created $adff cell `$procdff$5444' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.\err_source' using process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20'.
+ created $dff cell `$procdff$5447' with positive edge clock.
+Creating register for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.\err_size' using process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20'.
+ created $adff cell `$procdff$5448' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.\err_req_pending' using process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20'.
+ created $adff cell `$procdff$5449' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.\err_rsp_pending' using process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:49$9'.
+ created $adff cell `$procdff$5450' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.\qe' using process `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$7'.
+ created $adff cell `$procdff$5451' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.\q' using process `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$5'.
+ created $adff cell `$procdff$5452' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.\qe' using process `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$3'.
+ created $adff cell `$procdff$5453' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.\q' using process `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$1'.
+ created $adff cell `$procdff$5454' with positive edge clock and negative level reset.
+
+3.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
+
+3.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Found and cleaned up 3 empty switches in `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:100$1960'.
+Removing empty process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:100$1960'.
+Found and cleaned up 2 empty switches in `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:154$1946'.
+Removing empty process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:154$1946'.
+Found and cleaned up 3 empty switches in `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:142$1942'.
+Removing empty process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:142$1942'.
+Removing empty process `prim_secded_inv_39_32_enc.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_enc.sv:12$1912'.
+Removing empty process `prim_secded_inv_64_57_enc.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_enc.sv:12$1890'.
+Removing empty process `prim_secded_inv_39_32_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:14$1800'.
+Removing empty process `prim_secded_inv_64_57_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:14$1659'.
+Found and cleaned up 2 empty switches in `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:49$1656'.
+Removing empty process `sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:49$1656'.
+Found and cleaned up 2 empty switches in `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:298$1648'.
+Removing empty process `sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:298$1648'.
+Found and cleaned up 11 empty switches in `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+Removing empty process `sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+Removing empty process `sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:135$1636'.
+Found and cleaned up 2 empty switches in `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:69$1635'.
+Removing empty process `sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:69$1635'.
+Removing empty process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$1628'.
+Removing empty process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:44$1627'.
+Found and cleaned up 1 empty switch in `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$1621'.
+Removing empty process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$1621'.
+Found and cleaned up 3 empty switches in `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$1616'.
+Removing empty process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$1616'.
+Found and cleaned up 3 empty switches in `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$1611'.
+Removing empty process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$1611'.
+Found and cleaned up 1 empty switch in `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:61$1596'.
+Removing empty process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:61$1596'.
+Removing empty process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1211$1509'.
+Found and cleaned up 1 empty switch in `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1075$1508'.
+Removing empty process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1075$1508'.
+Removing empty process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:968$1372'.
+Removing empty process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:934$1344'.
+Found and cleaned up 2 empty switches in `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:117$1343'.
+Removing empty process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:117$1343'.
+Removing empty process `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$1259'.
+Found and cleaned up 2 empty switches in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:140$1254'.
+Removing empty process `hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:140$1254'.
+Found and cleaned up 8 empty switches in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+Removing empty process `hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+Removing empty process `hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:181$1195'.
+Found and cleaned up 2 empty switches in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:169$1191'.
+Removing empty process `hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:169$1191'.
+Found and cleaned up 1 empty switch in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:161$1189'.
+Removing empty process `hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:161$1189'.
+Found and cleaned up 2 empty switches in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:151$1186'.
+Removing empty process `hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:151$1186'.
+Found and cleaned up 2 empty switches in `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:46$1165'.
+Removing empty process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:46$1165'.
+Found and cleaned up 3 empty switches in `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:108$1148'.
+Removing empty process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:108$1148'.
+Removing empty process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+Found and cleaned up 1 empty switch in `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+Removing empty process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+Found and cleaned up 2 empty switches in `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:126$955'.
+Removing empty process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:126$955'.
+Found and cleaned up 1 empty switch in `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:125$924'.
+Removing empty process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:125$924'.
+Found and cleaned up 3 empty switches in `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$916'.
+Removing empty process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$916'.
+Found and cleaned up 3 empty switches in `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$911'.
+Removing empty process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$911'.
+Removing empty process `$paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:41$890'.
+Removing empty process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$883'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:50$838'.
+Found and cleaned up 3 empty switches in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:159$819'.
+Found and cleaned up 1 empty switch in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:138$817'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:138$817'.
+Found and cleaned up 1 empty switch in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:109$816'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:109$816'.
+Found and cleaned up 32 empty switches in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:85$782'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:85$782'.
+Found and cleaned up 1 empty switch in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:73$780'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:73$780'.
+Found and cleaned up 1 empty switch in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:60$772'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:60$772'.
+Removing empty process `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$770'.
+Found and cleaned up 1 empty switch in `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$764'.
+Removing empty process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$764'.
+Found and cleaned up 3 empty switches in `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$759'.
+Removing empty process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$759'.
+Found and cleaned up 3 empty switches in `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$754'.
+Removing empty process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$754'.
+Found and cleaned up 2 empty switches in `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:64$739'.
+Removing empty process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:64$739'.
+Found and cleaned up 1 empty switch in `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:120$722'.
+Removing empty process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:120$722'.
+Found and cleaned up 1 empty switch in `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:83$718'.
+Removing empty process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:83$718'.
+Found and cleaned up 1 empty switch in `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715'.
+Removing empty process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+Found and cleaned up 10 empty switches in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:121$598'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:121$598'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:555$549'.
+Found and cleaned up 1 empty switch in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:507$548'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:507$548'.
+Found and cleaned up 9 empty switches in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:485$537'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:485$537'.
+Found and cleaned up 2 empty switches in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:328$532'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:328$532'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:320$498'.
+Found and cleaned up 1 empty switch in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:200$495'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:200$495'.
+Found and cleaned up 2 empty switches in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:187$493'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:187$493'.
+Found and cleaned up 1 empty switch in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:178$489'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:178$489'.
+Found and cleaned up 2 empty switches in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:168$487'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:168$487'.
+Found and cleaned up 5 empty switches in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+Found and cleaned up 5 empty switches in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:236$312'.
+Found and cleaned up 7 empty switches in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:177$307'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:177$307'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:169$305'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:156$303'.
+Found and cleaned up 2 empty switches in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:144$299'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:144$299'.
+Found and cleaned up 3 empty switches in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:129$294'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:129$294'.
+Found and cleaned up 4 empty switches in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+Found and cleaned up 3 empty switches in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+Found and cleaned up 8 empty switches in `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+Removing empty process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+Removing empty process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+Found and cleaned up 1 empty switch in `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$62'.
+Removing empty process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$62'.
+Found and cleaned up 3 empty switches in `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$57'.
+Removing empty process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$57'.
+Found and cleaned up 3 empty switches in `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$52'.
+Removing empty process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$52'.
+Removing empty process `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$37'.
+Found and cleaned up 1 empty switch in `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$35'.
+Removing empty process `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$35'.
+Removing empty process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33'.
+Found and cleaned up 8 empty switches in `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+Removing empty process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+Found and cleaned up 2 empty switches in `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20'.
+Removing empty process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20'.
+Found and cleaned up 1 empty switch in `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:49$9'.
+Removing empty process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:49$9'.
+Removing empty process `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$7'.
+Found and cleaned up 1 empty switch in `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$5'.
+Removing empty process `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$5'.
+Removing empty process `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$3'.
+Found and cleaned up 1 empty switch in `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$1'.
+Removing empty process `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$1'.
+Cleaned up 203 empty switches.
+
+3.18.12. Executing OPT_EXPR pass (perform const folding).
+Optimizing module $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.
+
+Optimizing module prim_secded_inv_39_32_enc.
+
+Optimizing module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc.
+Optimizing module $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync.
+Optimizing module prim_secded_inv_64_57_enc.
+
+Optimizing module prim_generic_buf.
+Optimizing module prim_secded_inv_39_32_dec.
+
+Optimizing module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec.
+Optimizing module $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync.
+Optimizing module prim_secded_inv_64_57_dec.
+
+Optimizing module sha2_pad.
+
+Optimizing module $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.
+Optimizing module $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.
+
+Optimizing module $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.
+
+Optimizing module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Optimizing module $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync.
+Optimizing module hmac_core.
+
+Optimizing module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.
+
+Optimizing module $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.
+
+Optimizing module $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.
+
+Optimizing module $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.
+
+Optimizing module $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync.
+Optimizing module $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Optimizing module $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Optimizing module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.
+
+Optimizing module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+
+Optimizing module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Optimizing module $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.
+
+Optimizing module $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.
+
+Optimizing module $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Optimizing module hmac.
+
+Optimizing module $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Optimizing module sha2.
+
+Optimizing module $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.
+
+Optimizing module $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.
+
+Optimizing module $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.
+Optimizing module $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf.
+Optimizing module $paramod\prim_diff_decode\AsyncOn=1'1.
+
+Optimizing module $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync.
+Optimizing module $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync.
+Optimizing module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.
+
+Optimizing module $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.
+Optimizing module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001.
+Optimizing module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101.
+Optimizing module $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.
+Optimizing module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000.
+
+3.19. Executing FLATTEN pass (flatten design).
+Deleting now unused module $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.
+Deleting now unused module prim_secded_inv_39_32_enc.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc.
+Deleting now unused module $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync.
+Deleting now unused module prim_secded_inv_64_57_enc.
+Deleting now unused module prim_generic_buf.
+Deleting now unused module prim_secded_inv_39_32_dec.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec.
+Deleting now unused module $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync.
+Deleting now unused module prim_secded_inv_64_57_dec.
+Deleting now unused module sha2_pad.
+Deleting now unused module $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.
+Deleting now unused module $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.
+Deleting now unused module $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.
+Deleting now unused module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Deleting now unused module $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync.
+Deleting now unused module hmac_core.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.
+Deleting now unused module $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.
+Deleting now unused module $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.
+Deleting now unused module $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.
+Deleting now unused module $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync.
+Deleting now unused module $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Deleting now unused module $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.
+Deleting now unused module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Deleting now unused module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Deleting now unused module $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.
+Deleting now unused module $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.
+Deleting now unused module $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Deleting now unused module $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Deleting now unused module sha2.
+Deleting now unused module $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.
+Deleting now unused module $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.
+Deleting now unused module $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.
+Deleting now unused module $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf.
+Deleting now unused module $paramod\prim_diff_decode\AsyncOn=1'1.
+Deleting now unused module $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync.
+Deleting now unused module $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.
+Deleting now unused module $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.
+Deleting now unused module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001.
+Deleting now unused module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101.
+Deleting now unused module $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.
+Deleting now unused module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000.
+
+
+# --------------------
+# Design entry stats
+# --------------------
+
+3.20. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 6096
+ Number of wire bits: 85823
+ Number of public wires: 1354
+ Number of public wire bits: 23810
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 1
+ Number of memory bits: 4096
+ Number of processes: 0
+ Number of cells: 2866
+ $add 109
+ $adff 122
+ $and 173
+ $dff 20
+ $eq 376
+ $ge 2
+ $le 3
+ $logic_and 39
+ $logic_not 221
+ $logic_or 14
+ $lt 1
+ $meminit 1
+ $memrd_v2 1
+ $mul 11
+ $mux 1159
+ $ne 4
+ $neg 10
+ $not 125
+ $or 84
+ $pmux 45
+ $pos 6
+ $reduce_and 7
+ $reduce_bool 1
+ $reduce_or 39
+ $reduce_xor 36
+ $scopeinfo 97
+ $shift 10
+ $shiftx 6
+ $shl 4
+ $shr 2
+ $sub 15
+ $xor 123
+
+3.21. Executing SPLITNETS pass (splitting up multi-bit signals).
+
+3.22. Executing DEMUXMAP pass.
+
+3.23. Executing FLATTEN pass (flatten design).
+Deleting now unused module $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.
+Deleting now unused module $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.
+Deleting now unused module $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync.
+Deleting now unused module $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.
+Deleting now unused module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Deleting now unused module $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.
+Deleting now unused module $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.
+Deleting now unused module $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.
+Deleting now unused module $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync.
+Deleting now unused module $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync.
+Deleting now unused module $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.
+Deleting now unused module $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync.
+Deleting now unused module $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync.
+Deleting now unused module $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.
+Deleting now unused module $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf.
+Deleting now unused module $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.
+Deleting now unused module $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.
+Deleting now unused module $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.
+Deleting now unused module $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync.
+Deleting now unused module $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.
+Deleting now unused module $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.
+Deleting now unused module $paramod\prim_diff_decode\AsyncOn=1'1.
+Deleting now unused module $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Deleting now unused module $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Deleting now unused module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Deleting now unused module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Deleting now unused module $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Deleting now unused module $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Deleting now unused module $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.
+Deleting now unused module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001.
+Deleting now unused module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101.
+Deleting now unused module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000.
+Deleting now unused module hmac_core.
+Deleting now unused module prim_generic_buf.
+Deleting now unused module prim_secded_inv_39_32_dec.
+Deleting now unused module prim_secded_inv_39_32_enc.
+Deleting now unused module prim_secded_inv_64_57_dec.
+Deleting now unused module prim_secded_inv_64_57_enc.
+Deleting now unused module sha2.
+Deleting now unused module sha2_pad.
+
+
+3.24. Executing DEMUXMAP pass.
+
+3.25. Executing TRIBUF pass.
+Warning: Ignored -no_iobuf because -keep_tribuf is used.
+
+3.26. Executing DEMINOUT pass (demote inout ports to input or output).
+
+3.27. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+
+3.28. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 851 unused cells and 3473 unused wires.
+
+
+3.29. Executing CHECK pass (checking for obvious problems).
+Checking module hmac...
+Found and reported 0 problems.
+
+3.30. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 2623
+ Number of wire bits: 37350
+ Number of public wires: 1135
+ Number of public wire bits: 19171
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 1
+ Number of memory bits: 4096
+ Number of processes: 0
+ Number of cells: 1964
+ $add 102
+ $adff 79
+ $and 143
+ $dff 5
+ $eq 274
+ $ge 2
+ $le 3
+ $logic_and 38
+ $logic_not 105
+ $logic_or 13
+ $lt 1
+ $meminit 1
+ $memrd_v2 1
+ $mul 2
+ $mux 720
+ $ne 4
+ $neg 9
+ $not 101
+ $or 82
+ $pmux 42
+ $reduce_and 7
+ $reduce_bool 1
+ $reduce_or 38
+ $reduce_xor 30
+ $scopeinfo 97
+ $shift 9
+ $shiftx 6
+ $shl 4
+ $shr 2
+ $sub 9
+ $xor 34
+
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procdff$5431 ($adff): \gen_alert_tx[0].u_prim_alert_sender.state_q = 3'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procdff$5432 ($adff): \gen_alert_tx[0].u_prim_alert_sender.alert_pq = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procdff$5433 ($adff): \gen_alert_tx[0].u_prim_alert_sender.alert_nq = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procdff$5434 ($adff): \gen_alert_tx[0].u_prim_alert_sender.alert_set_q = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procdff$5435 ($adff): \gen_alert_tx[0].u_prim_alert_sender.ping_set_q = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procdff$5441 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.level_q = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procdff$5442 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.state_q = 2'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procdff$5443 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.diff_pq = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procdff$5444 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.diff_nq = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.\gen_async.i_sync_n.\gen_generic.u_impl_generic.\u_sync_1.$procdff$5318 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_n.gen_generic.u_impl_generic.u_sync_1.q_o = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.\gen_async.i_sync_n.\gen_generic.u_impl_generic.\u_sync_2.$procdff$5318 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_n.gen_generic.u_impl_generic.u_sync_2.q_o = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.\gen_async.i_sync_p.\gen_generic.u_impl_generic.\u_sync_1.$procdff$5334 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_p.gen_generic.u_impl_generic.u_sync_1.q_o = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.\gen_async.i_sync_p.\gen_generic.u_impl_generic.\u_sync_2.$procdff$5334 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_p.gen_generic.u_impl_generic.u_sync_2.q_o = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procdff$5442 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.state_q = 2'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procdff$5443 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.diff_pq = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procdff$5444 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.diff_nq = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.\gen_async.i_sync_n.\gen_generic.u_impl_generic.\u_sync_1.$procdff$5318 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_n.gen_generic.u_impl_generic.u_sync_1.q_o = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.\gen_async.i_sync_n.\gen_generic.u_impl_generic.\u_sync_2.$procdff$5318 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_n.gen_generic.u_impl_generic.u_sync_2.q_o = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.\gen_async.i_sync_p.\gen_generic.u_impl_generic.\u_sync_1.$procdff$5334 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic.u_sync_1.q_o = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.\gen_async.i_sync_p.\gen_generic.u_impl_generic.\u_sync_2.$procdff$5334 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic.u_sync_2.q_o = 1'x
+FF init value for cell $flatten\intr_hw_fifo_empty.$procdff$5329 ($adff): \intr_hw_fifo_empty.intr_o = 1'x
+FF init value for cell $flatten\intr_hw_hmac_done.$procdff$5329 ($adff): \intr_hw_hmac_done.intr_o = 1'x
+FF init value for cell $flatten\intr_hw_hmac_err.$procdff$5329 ($adff): \intr_hw_hmac_err.intr_o = 1'x
+FF init value for cell $flatten\u_hmac.$procdff$5319 ($adff): \u_hmac.txcount = 64'x
+FF init value for cell $flatten\u_hmac.$procdff$5320 ($adff): \u_hmac.st_q = 3'x
+FF init value for cell $flatten\u_hmac.$procdff$5321 ($adff): \u_hmac.fifo_wdata_sel = 3'x
+FF init value for cell $flatten\u_hmac.$procdff$5322 ($adff): \u_hmac.round_q = 1'x
+FF init value for cell $flatten\u_hmac.$procdff$5323 ($adff): \u_hmac.reg_hash_process_flag = 1'x
+FF init value for cell $flatten\u_msg_fifo.$procdff$5324 ($dff): \u_msg_fifo.gen_normal_fifo.storage = 576'x
+FF init value for cell $flatten\u_msg_fifo.$procdff$5327 ($adff): \u_msg_fifo.gen_normal_fifo.fifo_rptr = 5'x
+FF init value for cell $flatten\u_msg_fifo.$procdff$5328 ($adff): \u_msg_fifo.gen_normal_fifo.fifo_wptr = 5'x
+FF init value for cell $flatten\u_packer.$procdff$5330 ($adff): \u_packer.flush_st = 1'x
+FF init value for cell $flatten\u_packer.$procdff$5331 ($adff): \u_packer.stored_data = 64'x
+FF init value for cell $flatten\u_packer.$procdff$5332 ($adff): \u_packer.stored_mask = 64'x
+FF init value for cell $flatten\u_packer.$procdff$5333 ($adff): \u_packer.pos = 7'x
+FF init value for cell $flatten\u_reg.$procdff$5317 ($adff): \u_reg.intg_err_q = 1'x
+FF init value for cell $flatten\u_reg.\u_err_code.$procdff$5454 ($adff): \u_reg.u_err_code.q = 32'x
+FF init value for cell $flatten\u_reg.\u_intr_enable_fifo_empty.$procdff$5440 ($adff): \u_reg.u_intr_enable_fifo_empty.q = 1'x
+FF init value for cell $flatten\u_reg.\u_intr_enable_hmac_done.$procdff$5440 ($adff): \u_reg.u_intr_enable_hmac_done.q = 1'x
+FF init value for cell $flatten\u_reg.\u_intr_enable_hmac_err.$procdff$5440 ($adff): \u_reg.u_intr_enable_hmac_err.q = 1'x
+FF init value for cell $flatten\u_reg.\u_intr_state_fifo_empty.$procdff$5452 ($adff): \u_reg.u_intr_state_fifo_empty.q = 1'x
+FF init value for cell $flatten\u_reg.\u_intr_state_hmac_done.$procdff$5452 ($adff): \u_reg.u_intr_state_hmac_done.q = 1'x
+FF init value for cell $flatten\u_reg.\u_intr_state_hmac_err.$procdff$5452 ($adff): \u_reg.u_intr_state_hmac_err.q = 1'x
+FF init value for cell $flatten\u_reg.\u_msg_length_lower.$procdff$5454 ($adff): \u_reg.u_msg_length_lower.q = 32'x
+FF init value for cell $flatten\u_reg.\u_msg_length_upper.$procdff$5454 ($adff): \u_reg.u_msg_length_upper.q = 32'x
+FF init value for cell $flatten\u_reg.\u_reg_if.$procdff$5338 ($adff): \u_reg.u_reg_if.outstanding = 1'x
+FF init value for cell $flatten\u_reg.\u_reg_if.$procdff$5339 ($adff): \u_reg.u_reg_if.rdata = 32'x
+FF init value for cell $flatten\u_reg.\u_reg_if.$procdff$5340 ($adff): \u_reg.u_reg_if.error = 1'x
+FF init value for cell $flatten\u_reg.\u_reg_if.$procdff$5341 ($adff): \u_reg.u_reg_if.reqid = 8'x
+FF init value for cell $flatten\u_reg.\u_reg_if.$procdff$5342 ($adff): \u_reg.u_reg_if.reqsz = 2'x
+FF init value for cell $flatten\u_reg.\u_reg_if.$procdff$5343 ($adff): \u_reg.u_reg_if.rspop = 3'x
+FF init value for cell $flatten\u_reg.\u_socket.$procdff$5309 ($adff): \u_reg.u_socket.num_req_outstanding = 9'x
+FF init value for cell $flatten\u_reg.\u_socket.$procdff$5310 ($adff): \u_reg.u_socket.dev_select_outstanding = 2'x
+FF init value for cell $flatten\u_reg.\u_socket.\err_resp.$procdff$5447 ($dff): \u_reg.u_socket.err_resp.err_source = 8'x
+FF init value for cell $flatten\u_reg.\u_socket.\err_resp.$procdff$5448 ($adff): \u_reg.u_socket.err_resp.err_size = 2'x
+FF init value for cell $flatten\u_reg.\u_socket.\err_resp.$procdff$5449 ($adff): \u_reg.u_socket.err_resp.err_req_pending = 1'x
+FF init value for cell $flatten\u_reg.\u_socket.\err_resp.$procdff$5450 ($adff): \u_reg.u_socket.err_resp.err_rsp_pending = 1'x
+FF init value for cell $flatten\u_sha2.$procdff$5354 ($adff): \u_sha2.w = 512'x
+FF init value for cell $flatten\u_sha2.$procdff$5378 ($adff): \u_sha2.sha_st_q = 2'x
+FF init value for cell $flatten\u_sha2.$procdff$5379 ($adff): \u_sha2.fifo_st_q = 2'x
+FF init value for cell $flatten\u_sha2.$procdff$5380 ($adff): \u_sha2.hash_done = 1'x
+FF init value for cell $flatten\u_sha2.$procdff$5381 ($adff): \u_sha2.w_index = 4'x
+FF init value for cell $flatten\u_sha2.$procdff$5382 ($adff): \u_sha2.round = 6'x
+FF init value for cell $flatten\u_sha2.$procdff$5383 ($adff): \u_sha2.digest = 32'x
+FF init value for cell $flatten\u_sha2.$procdff$5393 ($adff): \u_sha2.hash = 256'x
+FF init value for cell $flatten\u_sha2.\u_pad.$procdff$5311 ($adff): \u_sha2.u_pad.hash_process_flag = 1'x
+FF init value for cell $flatten\u_sha2.\u_pad.$procdff$5312 ($adff): \u_sha2.u_pad.tx_count = 64'x
+FF init value for cell $flatten\u_sha2.\u_pad.$procdff$5313 ($adff): \u_sha2.u_pad.st_q = 3'x
+FF init value for cell $flatten\u_tlul_adapter.\u_reqfifo.$procdff$5314 ($dff): \u_tlul_adapter.u_reqfifo.gen_normal_fifo.storage = 13'x
+FF init value for cell $flatten\u_tlul_adapter.\u_reqfifo.$procdff$5315 ($adff): \u_tlul_adapter.u_reqfifo.gen_normal_fifo.fifo_rptr = 2'x
+FF init value for cell $flatten\u_tlul_adapter.\u_reqfifo.$procdff$5316 ($adff): \u_tlul_adapter.u_reqfifo.gen_normal_fifo.fifo_wptr = 2'x
+FF init value for cell $flatten\u_tlul_adapter.\u_rspfifo.$procdff$5335 ($dff): \u_tlul_adapter.u_rspfifo.gen_normal_fifo.storage = 33'x
+FF init value for cell $flatten\u_tlul_adapter.\u_rspfifo.$procdff$5336 ($adff): \u_tlul_adapter.u_rspfifo.gen_normal_fifo.fifo_rptr = 2'x
+FF init value for cell $flatten\u_tlul_adapter.\u_rspfifo.$procdff$5337 ($adff): \u_tlul_adapter.u_rspfifo.gen_normal_fifo.fifo_wptr = 2'x
+FF init value for cell $flatten\u_tlul_adapter.\u_sramreqfifo.$procdff$5436 ($dff): \u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.storage = 5'x
+FF init value for cell $flatten\u_tlul_adapter.\u_sramreqfifo.$procdff$5437 ($adff): \u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.fifo_rptr = 2'x
+FF init value for cell $flatten\u_tlul_adapter.\u_sramreqfifo.$procdff$5438 ($adff): \u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.fifo_wptr = 2'x
+FF init value for cell $procdff$5344 ($adff): \secret_key = 256'x
+FF init value for cell $procdff$5348 ($adff): \idle_o = 1'x
+FF init value for cell $procdff$5349 ($adff): \message_length = 64'x
+FF init value for cell $procdff$5350 ($adff): \fifo_empty_q = 1'x
+FF init value for cell $procdff$5351 ($adff): \msg_allowed = 1'x
+FF init value for cell $procdff$5352 ($adff): \cfg_reg = 8'x
+FF init value for cell $procdff$5353 ($adff): \cfg_block = 1'x
+
+3.31. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+
+3.32. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+
+Removed a total of 343 cells.
+
+3.33. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2699.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2706.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4951.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2714.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2722.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2730.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2738.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4962.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2746.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2756.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2758.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2767.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2777.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4973.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2787.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2797.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2808.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2819.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4984.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2831.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2842.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2854.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4996.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2866.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2878.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5008.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5020.
+ dead port 2/2 on $mux $flatten\u_hmac.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:128$1244.
+ dead port 2/2 on $mux $flatten\u_packer.$procmux$3080.
+ dead port 2/2 on $mux $flatten\u_packer.$procmux$3085.
+ dead port 2/2 on $mux $flatten\u_packer.$procmux$3090.
+ dead port 1/2 on $mux $flatten\u_packer.$procmux$3096.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5091.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5097.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5138.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5145.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5152.
+ dead port 1/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5161.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5163.
+ dead port 1/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5172.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5174.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5248.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5256.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5264.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4878.
+ dead port 2/2 on $mux $flatten\u_reg.\u_reg_if.\u_err.$procmux$2968.
+ dead port 2/2 on $mux $flatten\u_reg.\u_reg_if.\u_err.$procmux$2976.
+ dead port 2/2 on $mux $flatten\u_reg.\u_reg_if.\u_err.$procmux$2984.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5091.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4008.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4014.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4021.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4028.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4036.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5097.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4044.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5105.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5107.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5115.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5117.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4883.
+ dead port 1/2 on $mux $flatten\u_sha2.$procmux$4071.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4073.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4079.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5124.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4085.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4092.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4095.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4097.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4105.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4108.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4110.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4118.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4120.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5131.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4128.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4130.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4137.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4144.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5145.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4152.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4888.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5152.
+ dead port 1/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5161.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2011.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2017.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5163.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2024.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2031.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2040.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2042.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2050.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2058.
+ dead port 1/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5172.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2068.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2070.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2080.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2082.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5174.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2091.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2100.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2111.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2114.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2116.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2127.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2130.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2132.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5184.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2143.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2146.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2148.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5186.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2159.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2162.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2164.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5188.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2175.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2177.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4896.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2188.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2190.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2201.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2203.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5198.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2214.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2216.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5200.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2226.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5202.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2236.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2246.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2256.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5211.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2267.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5213.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2277.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5222.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5224.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4904.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5232.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5240.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5256.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4913.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5264.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4922.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4931.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2324.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4941.
+ dead port 1/2 on $mux $flatten\u_tlul_adapter.$procmux$3000.
+ dead port 1/2 on $mux $flatten\u_tlul_adapter.$procmux$3002.
+ dead port 1/2 on $mux $flatten\u_tlul_adapter.$procmux$3008.
+ dead port 1/2 on $mux $flatten\u_tlul_adapter.$procmux$3050.
+ dead port 2/2 on $mux $flatten\u_tlul_adapter.\u_err.$procmux$2968.
+ dead port 2/2 on $mux $flatten\u_tlul_adapter.\u_err.$procmux$2976.
+ dead port 2/2 on $mux $flatten\u_tlul_adapter.\u_err.$procmux$2984.
+ dead port 2/2 on $mux $procmux$3351.
+ dead port 2/2 on $mux $procmux$3357.
+ dead port 2/2 on $mux $procmux$3363.
+ dead port 2/2 on $mux $procmux$3369.
+ dead port 2/2 on $mux $procmux$3375.
+ dead port 2/2 on $mux $procmux$3381.
+ dead port 2/2 on $mux $procmux$3387.
+ dead port 2/2 on $mux $procmux$3393.
+Removed 163 multiplexer ports.
+
+
+3.34. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+ New input vector for $reduce_or cell $flatten\u_reg.\u_reg_if.\u_err.$reduce_or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:63$1177: \tl_i [59:58]
+ New input vector for $reduce_or cell $flatten\u_reg.\u_reg_if.\u_err.$reduce_or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:62$1174: \tl_i [57:56]
+ New input vector for $reduce_or cell $flatten\u_reg.$reduce_or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:990$1474: $flatten\u_reg.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:970$1374_Y [1:0]
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5049: { $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4897_CMP $auto_5680 }
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5058: { $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4942_CMP $auto_5682 }
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5022: { $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4997_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4963_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4914_CMP $auto_5684 $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4879_CMP }
+ New ctrl vector for $pmux cell $flatten\u_hmac.$procmux$2892: $flatten\u_hmac.$procmux$2715_CMP
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5031: { $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4997_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4963_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4914_CMP $auto_5686 $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4879_CMP }
+ New ctrl vector for $pmux cell $flatten\u_hmac.$procmux$2934: { $flatten\u_hmac.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:116$1216_Y $auto_5688 }
+ New ctrl vector for $pmux cell $flatten\u_sha2.\u_pad.$procmux$2288: { $flatten\u_sha2.\u_pad.$procmux$2117_CMP $flatten\u_sha2.\u_pad.$procmux$2071_CMP $flatten\u_sha2.\u_pad.$procmux$2043_CMP $flatten\u_sha2.\u_pad.$procmux$2025_CMP $flatten\u_sha2.\u_pad.$procmux$2012_CMP }
+ New ctrl vector for $pmux cell $flatten\u_sha2.\u_pad.$procmux$2296: { $flatten\u_sha2.\u_pad.$procmux$2117_CMP $auto_5690 }
+ Optimizing cells in module \hmac.
+Performed a total of 11 changes.
+
+3.35. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+
+Removed a total of 32 cells.
+
+3.36. Executing OPT_SHARE pass.
+ Found cells that share an operand and can be merged by moving the $mux $flatten\u_msg_fifo.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:69$902 in front of them:
+ $flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:69$899
+ $flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:70$901
+
+3.37. Executing OPT_DFF pass (perform DFF optimizations).
+Handling D = Q on $flatten\u_reg.\u_intr_enable_hmac_err.$procdff$5440 ($adff) from module hmac (removing D path).
+Handling D = Q on $flatten\u_reg.\u_intr_enable_hmac_done.$procdff$5440 ($adff) from module hmac (removing D path).
+Handling D = Q on $flatten\u_reg.\u_intr_enable_fifo_empty.$procdff$5440 ($adff) from module hmac (removing D path).
+Setting constant 0-bit at position 0 on $flatten\u_reg.\u_intr_enable_fifo_empty.$procdff$5440 ($dlatch) from module hmac.
+Setting constant 0-bit at position 0 on $flatten\u_reg.\u_intr_enable_hmac_done.$procdff$5440 ($dlatch) from module hmac.
+Setting constant 0-bit at position 0 on $flatten\u_reg.\u_intr_enable_hmac_err.$procdff$5440 ($dlatch) from module hmac.
+[#visit=84, #solve=0, #remove=3, time=0.63 sec.]
+
+3.38. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 0 unused cells and 551 unused wires.
+
+
+3.39. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+
+3.40. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.41. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5022: { $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4997_CMP $auto_5697 $auto_5684 $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4879_CMP }
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5031: { $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4997_CMP $auto_5699 $auto_5684 $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4879_CMP }
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5040: { $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4997_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4963_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4914_CMP $auto_5701 $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5025_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5024_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4879_CMP }
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5272: { $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5164_CMP $auto_5703 }
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5288: $auto_5705
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5272: { $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5164_CMP $auto_5707 }
+ New ctrl vector for $pmux cell $flatten\u_hmac.$procmux$2925: { $flatten\u_hmac.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:116$1216_Y $auto_5709 }
+ New ctrl vector for $pmux cell $flatten\u_sha2.$procmux$4047: { $flatten\u_sha2.$procmux$4022_CMP $auto_5711 }
+ New ctrl vector for $pmux cell $flatten\u_sha2.$procmux$4052: $auto_5713
+ New ctrl vector for $pmux cell $flatten\u_sha2.\u_pad.$procmux$2288: { $flatten\u_sha2.\u_pad.$procmux$2117_CMP $flatten\u_sha2.\u_pad.$procmux$2071_CMP $auto_5715 }
+ Optimizing cells in module \hmac.
+Performed a total of 10 changes.
+
+3.42. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+
+Removed a total of 4 cells.
+
+3.43. Executing OPT_SHARE pass.
+
+3.44. Executing OPT_DFF pass (perform DFF optimizations).
+Handling D = Q on $flatten\u_reg.\u_socket.\err_resp.$procdff$5448 ($adff) from module hmac (removing D path).
+Handling D = Q on $flatten\u_reg.\u_socket.\err_resp.$procdff$5447 ($dff) from module hmac (removing D path).
+Setting constant 0-bit at position 0 on $flatten\intr_hw_fifo_empty.$procdff$5329 ($adff) from module hmac.
+Setting constant 0-bit at position 0 on $flatten\u_reg.\u_socket.\err_resp.$procdff$5448 ($dlatch) from module hmac.
+Setting constant 0-bit at position 1 on $flatten\u_reg.\u_socket.\err_resp.$procdff$5448 ($dlatch) from module hmac.
+[#visit=78, #solve=0, #remove=3, time=0.55 sec.]
+
+3.45. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 0 unused cells and 6 unused wires.
+
+
+3.46. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.47. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.48. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.49. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.50. Executing OPT_SHARE pass.
+
+3.51. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=76, #solve=0, #remove=0, time=0.75 sec.]
+
+3.52. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.53. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+RUN-OPT ITERATIONS DONE : 3
+
+3.54. Executing FSM pass (extract and optimize FSM).
+
+3.54.1. Executing FSM_DETECT pass (finding FSMs in design).
+Not marking hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.state_q as FSM state register:
+ Register has an initialization value.
+Not marking hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.state_q as FSM state register:
+ Register has an initialization value.
+Not marking hmac.gen_alert_tx[0].u_prim_alert_sender.state_q as FSM state register:
+ Register has an initialization value.
+Not marking hmac.u_hmac.st_q as FSM state register:
+ Register has an initialization value.
+ Circuit seems to be self-resetting.
+Not marking hmac.u_reg.u_err_code.q as FSM state register:
+ Users of register don't seem to benefit from recoding.
+ Register has an initialization value.
+Not marking hmac.u_reg.u_reg_if.rspop as FSM state register:
+ Users of register don't seem to benefit from recoding.
+ Register has an initialization value.
+Not marking hmac.u_sha2.fifo_st_q as FSM state register:
+ Register has an initialization value.
+ Circuit seems to be self-resetting.
+Not marking hmac.u_sha2.sha_st_q as FSM state register:
+ Register has an initialization value.
+ Circuit seems to be self-resetting.
+Not marking hmac.u_sha2.u_pad.st_q as FSM state register:
+ Register has an initialization value.
+ Circuit seems to be self-resetting.
+
+3.54.2. Executing FSM_EXTRACT pass (extracting FSM from design).
+
+3.54.3. Executing FSM_OPT pass (simple optimizations of FSMs).
+
+3.54.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.54.5. Executing FSM_OPT pass (simple optimizations of FSMs).
+
+3.54.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
+
+3.54.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
+
+3.54.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
+
+3.55. Executing WREDUCE pass (reducing word size of cells).
+Removed top 20 address bits (of 32) from memory init port hmac.$flatten\u_reg.$auto_1968 ($flatten\u_reg.$auto_1966).
+Removed top 23 bits (of 32) from port B of cell hmac.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_pkg.sv:0$568 ($shiftx).
+Removed top 29 bits (of 32) from mux cell hmac.$procmux$3337 ($mux).
+Removed top 28 bits (of 32) from mux cell hmac.$flatten\u_tlul_adapter.\u_sramreqfifo.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:141$64 ($mux).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.\u_sramreqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$56 ($add).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.\u_sramreqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$61 ($add).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.\u_rspfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$758 ($add).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.\u_rspfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$763 ($add).
+Removed top 19 bits (of 32) from mux cell hmac.$flatten\u_tlul_adapter.\u_reqfifo.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:141$1623 ($mux).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.\u_reqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$1615 ($add).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.\u_reqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$1620 ($add).
+Removed top 1 bits (of 2) from mux cell hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:228$1137 ($mux).
+Removed top 24 bits (of 32) from mux cell hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$994 ($mux).
+Removed top 24 bits (of 32) from mux cell hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$1057 ($mux).
+Removed top 24 bits (of 32) from mux cell hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$1036 ($mux).
+Removed top 24 bits (of 32) from mux cell hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$1015 ($mux).
+Removed top 2 bits (of 3) from mux cell hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:142$1120 ($mux).
+Removed top 25 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1143 ($shiftx).
+Removed top 8 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1060 ($or).
+Removed top 8 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1048 ($or).
+Removed top 8 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1039 ($or).
+Removed top 8 bits (of 32) from port Y of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1039 ($or).
+Removed top 8 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1027 ($or).
+Removed top 8 bits (of 32) from port Y of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1027 ($or).
+Removed top 24 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1018 ($or).
+Removed top 16 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1018 ($or).
+Removed top 16 bits (of 32) from port Y of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1018 ($or).
+Removed top 24 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1006 ($or).
+Removed top 16 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1006 ($or).
+Removed top 16 bits (of 32) from port Y of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1006 ($or).
+Converting cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1096 ($neg) from signed to unsigned.
+Converting cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1087 ($neg) from signed to unsigned.
+Converting cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1078 ($neg) from signed to unsigned.
+Removed top 26 bits (of 33) from port A of cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1073 ($neg).
+Converting cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1073 ($neg) from signed to unsigned.
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.$ne$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:142$1118 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:115$1149 ($eq).
+Removed top 26 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1095 ($add).
+Removed top 27 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1095 ($add).
+Removed top 25 bits (of 32) from port Y of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1095 ($add).
+Removed top 26 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1086 ($add).
+Removed top 27 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1086 ($add).
+Removed top 25 bits (of 32) from port Y of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1086 ($add).
+Removed top 26 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1077 ($add).
+Removed top 28 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1077 ($add).
+Removed top 25 bits (of 32) from port Y of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1077 ($add).
+Removed top 1 bits (of 3) from port B of cell hmac.$flatten\u_sha2.\u_pad.$procmux$2329_CMP0 ($eq).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\u_sha2.\u_pad.$procmux$2325_CMP0 ($eq).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_sha2.\u_pad.$procmux$2322_CMP0 ($eq).
+Removed top 2 bits (of 3) from mux cell hmac.$flatten\u_sha2.\u_pad.$procmux$2265 ($mux).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\u_sha2.\u_pad.$procmux$2117_CMP0 ($eq).
+Removed top 1 bits (of 3) from mux cell hmac.$flatten\u_sha2.\u_pad.$procmux$2108 ($mux).
+Removed top 2 bits (of 3) from mux cell hmac.$flatten\u_sha2.\u_pad.$procmux$2077 ($mux).
+Removed top 1 bits (of 3) from port B of cell hmac.$flatten\u_sha2.\u_pad.$procmux$2071_CMP0 ($eq).
+Removed top 1 bits (of 3) from port B of cell hmac.$flatten\u_sha2.\u_pad.$procmux$2043_CMP0 ($eq).
+Removed top 2 bits (of 3) from mux cell hmac.$flatten\u_sha2.\u_pad.$procmux$2029 ($mux).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$279 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$278 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$277 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$276 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$275 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$274 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$273 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$272 ($xor).
+Removed top 10 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$461 ($xor).
+Removed top 3 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$452 ($xor).
+Removed top 15 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$222 ($shiftx).
+Removed top 992 bits (of 1024) from port Y of cell hmac.$flatten\u_sha2.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$222 ($shiftx).
+Removed top 1 bits (of 2) from mux cell hmac.$flatten\u_sha2.$procmux$4150 ($mux).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_sha2.$procmux$4098_CMP0 ($eq).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_sha2.$procmux$4022_CMP0 ($eq).
+Removed top 1 bits (of 2) from mux cell hmac.$flatten\u_sha2.$procmux$4006 ($mux).
+Removed top 19 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$458 ($or).
+Removed top 17 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$455 ($or).
+Removed top 18 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$449 ($or).
+Removed top 7 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$446 ($or).
+Removed top 22 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$250 ($or).
+Removed top 13 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$247 ($or).
+Removed top 2 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$244 ($or).
+Removed top 25 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$231 ($or).
+Removed top 11 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$228 ($or).
+Removed top 6 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$225 ($or).
+Removed top 26 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$lt$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:266$316 ($lt).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:150$302 ($add).
+Removed top 28 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:150$302 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:138$298 ($add).
+Removed top 26 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:138$298 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$293 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$292 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$291 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$290 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$289 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$288 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$287 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$286 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:72$259 ($add).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\u_reg.\u_socket.\gen_dfifo[1].fifo_d.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:74$1257 ($eq).
+Removed top 2 bits (of 3) from port A of cell hmac.$flatten\u_reg.\u_socket.\gen_dfifo[0].fifo_d.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:74$1257 ($eq).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\u_reg.\u_socket.\gen_dfifo[0].fifo_d.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:74$1257 ($eq).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\u_reg.\u_socket.\fifo_h.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:74$24 ($eq).
+Removed top 1 bits (of 2) from port A of cell hmac.$flatten\u_reg.\u_socket.$ne$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:116$1953 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_reg.\u_socket.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:157$1949 ($eq).
+Removed top 30 bits (of 32) from port A of cell hmac.$flatten\u_reg.\u_reg_if.\u_err.$shl$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:44$1160 ($shl).
+Removed top 28 bits (of 32) from port Y of cell hmac.$flatten\u_reg.\u_reg_if.\u_err.$shl$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:44$1160 ($shl).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_reg.\u_reg_if.\u_err.$procmux$2966_CMP0 ($eq).
+Removed top 2 bits (of 3) from mux cell hmac.$flatten\u_reg.\u_reg_if.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:79$717 ($mux).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\u_reg.\u_reg_if.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:55$727 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:962$1371 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:961$1370 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:960$1369 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:959$1368 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:958$1367 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:957$1366 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:956$1365 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:955$1364 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:954$1363 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:953$1362 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:952$1361 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:951$1360 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:950$1359 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:949$1358 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:948$1357 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:947$1356 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:946$1355 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:945$1354 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:944$1353 ($eq).
+Removed top 7 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:943$1352 ($eq).
+Removed top 7 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:942$1351 ($eq).
+Removed top 7 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:941$1350 ($eq).
+Removed top 7 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:940$1349 ($eq).
+Removed top 8 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:939$1348 ($eq).
+Removed top 8 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:938$1347 ($eq).
+Removed top 9 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:937$1346 ($eq).
+Removed top 25 bits (of 32) from mux cell hmac.$flatten\u_packer.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$779 ($mux).
+Removed top 25 bits (of 32) from mux cell hmac.$flatten\u_packer.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$776 ($mux).
+Removed top 26 bits (of 32) from port B of cell hmac.$flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$778 ($sub).
+Removed top 25 bits (of 32) from port Y of cell hmac.$flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$778 ($sub).
+Removed top 26 bits (of 32) from port B of cell hmac.$flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$775 ($sub).
+Removed top 25 bits (of 32) from port Y of cell hmac.$flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$775 ($sub).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_packer.$procmux$3116_CMP0 ($eq).
+Removed top 32 bits (of 96) from port A of cell hmac.$flatten\u_packer.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:105$834 ($or).
+Removed top 32 bits (of 96) from port A of cell hmac.$flatten\u_packer.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:103$833 ($or).
+Removed top 26 bits (of 32) from port B of cell hmac.$flatten\u_packer.$le$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$777 ($le).
+Removed top 26 bits (of 32) from port B of cell hmac.$flatten\u_packer.$le$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:216$837 ($le).
+Removed top 26 bits (of 32) from port B of cell hmac.$flatten\u_packer.$ge$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:208$835 ($ge).
+Removed top 5 bits (of 6) from port A of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$841 ($add).
+Removed top 4 bits (of 6) from port Y of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$841 ($add).
+Removed top 27 bits (of 32) from mux cell hmac.$flatten\u_msg_fifo.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:68$903 ($mux).
+Removed top 27 bits (of 32) from port A of cell hmac.$flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:70$900 ($sub).
+Removed top 26 bits (of 32) from port Y of cell hmac.$flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:70$900 ($sub).
+Removed top 27 bits (of 32) from port Y of cell hmac.$flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:69$899 ($sub).
+Converting cell hmac.$flatten\u_msg_fifo.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$930 ($neg) from signed to unsigned.
+Removed top 26 bits (of 30) from port B of cell hmac.$flatten\u_msg_fifo.$mul$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$929 ($mul).
+Removed top 22 bits (of 30) from port Y of cell hmac.$flatten\u_msg_fifo.$mul$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$929 ($mul).
+Removed top 26 bits (of 30) from port B of cell hmac.$flatten\u_msg_fifo.$mul$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$921 ($mul).
+Removed top 22 bits (of 30) from port Y of cell hmac.$flatten\u_msg_fifo.$mul$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$921 ($mul).
+Removed top 4 bits (of 5) from port B of cell hmac.$flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$915 ($add).
+Removed top 4 bits (of 5) from port B of cell hmac.$flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$920 ($add).
+Removed top 26 bits (of 32) from port B of cell hmac.$flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1226 ($sub).
+Removed top 23 bits (of 32) from port A of cell hmac.$flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1224 ($sub).
+Removed top 23 bits (of 32) from port B of cell hmac.$flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1224 ($sub).
+Removed top 22 bits (of 32) from port Y of cell hmac.$flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1224 ($sub).
+Removed top 2 bits (of 3) from mux cell hmac.$flatten\u_hmac.$procmux$2876 ($mux).
+Removed top 1 bits (of 3) from mux cell hmac.$flatten\u_hmac.$procmux$2817 ($mux).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\u_hmac.$procmux$2809_CMP0 ($eq).
+Removed top 1 bits (of 3) from port B of cell hmac.$flatten\u_hmac.$procmux$2715_CMP0 ($eq).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_hmac.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:122$1228 ($eq).
+Removed top 1 bits (of 3) from port B of cell hmac.$flatten\u_hmac.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:116$1216 ($eq).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1225 ($add).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5108_CMP0 ($eq).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5139_CMP0 ($eq).
+Removed top 1 bits (of 3) from mux cell hmac.$flatten\gen_alert_tx[0].u_prim_alert_sender.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:139$77 ($mux).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4963_CMP0 ($eq).
+Removed top 1 bits (of 3) from port B of cell hmac.$flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4942_CMP0 ($eq).
+Removed top 1 bits (of 3) from port B of cell hmac.$flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4914_CMP0 ($eq).
+Removed top 5 bits (of 6) from port A of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$501 ($add).
+Removed top 4 bits (of 6) from port Y of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$501 ($add).
+Removed top 29 bits (of 32) from mux cell hmac.$procmux$3339 ($mux).
+Removed top 16 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1039 ($or).
+Removed top 16 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1027 ($or).
+Removed top 26 bits (of 33) from port A of cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1096 ($neg).
+Removed top 26 bits (of 33) from port A of cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1087 ($neg).
+Removed top 26 bits (of 33) from port A of cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1078 ($neg).
+Removed top 1 bits (of 7) from port A of cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1073 ($neg).
+Removed top 1 bits (of 3) from mux cell hmac.$flatten\u_sha2.\u_pad.$procmux$2172 ($mux).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$279 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$278 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$277 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$276 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$275 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$274 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$273 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$272 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$293 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$292 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$291 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$290 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$289 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$288 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$287 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$286 ($add).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260 ($add).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:72$259 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:72$259 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:67$258 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241 ($add).
+Removed top 4 bits (of 6) from port A of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$842 ($add).
+Removed top 3 bits (of 6) from port Y of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$842 ($add).
+Removed top 27 bits (of 32) from port B of cell hmac.$flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:69$899 ($sub).
+Removed top 21 bits (of 32) from port B of cell hmac.$flatten\u_msg_fifo.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$922 ($shiftx).
+Removed top 23 bits (of 33) from port A of cell hmac.$flatten\u_msg_fifo.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$930 ($neg).
+Removed top 27 bits (of 32) from mux cell hmac.$auto_5694 ($mux).
+Removed top 27 bits (of 32) from port Y of cell hmac.$auto_5691 ($neg).
+Removed top 4 bits (of 6) from port A of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$502 ($add).
+Removed top 3 bits (of 6) from port Y of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$502 ($add).
+Removed top 29 bits (of 32) from mux cell hmac.$procmux$3341 ($mux).
+Removed top 1 bits (of 3) from mux cell hmac.$flatten\u_sha2.\u_pad.$procmux$2224 ($mux).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:67$258 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:67$258 ($add).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$240 ($add).
+Removed top 3 bits (of 6) from port A of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$843 ($add).
+Removed top 2 bits (of 6) from port Y of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$843 ($add).
+Removed top 27 bits (of 32) from port A of cell hmac.$auto_5691 ($neg).
+Removed top 3 bits (of 6) from port A of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$503 ($add).
+Removed top 2 bits (of 6) from port Y of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$503 ($add).
+Removed top 29 bits (of 32) from mux cell hmac.$procmux$3343 ($mux).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$257 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$252 ($xor).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$240 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$240 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$239 ($add).
+Removed top 2 bits (of 6) from port A of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$844 ($add).
+Removed top 1 bits (of 6) from port Y of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$844 ($add).
+Removed top 1 bits (of 6) from port Y of cell hmac.$flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:70$900 ($sub).
+Removed top 2 bits (of 6) from port A of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$504 ($add).
+Removed top 1 bits (of 6) from port Y of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$504 ($add).
+Removed top 29 bits (of 32) from mux cell hmac.$procmux$3345 ($mux).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$257 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$257 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$255 ($xor).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$252 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$252 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$251 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$222 ($shiftx).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$250 ($or).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$256 ($and).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$239 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$239 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$238 ($add).
+Removed top 1 bits (of 6) from port A of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$845 ($add).
+Removed top 1 bits (of 6) from port A of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$505 ($add).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$255 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$255 ($xor).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$251 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$251 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$237 ($xor).
+Removed top 9 bits (of 10) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$250 ($or).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$250 ($or).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$247 ($or).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$244 ($or).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$256 ($and).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$256 ($and).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$254 ($and).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$253 ($and).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$238 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$238 ($add).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$237 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$237 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$233 ($xor).
+Removed top 18 bits (of 19) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$247 ($or).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$247 ($or).
+Removed top 29 bits (of 30) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$244 ($or).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$244 ($or).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$254 ($and).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$254 ($and).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$253 ($and).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$253 ($and).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$236 ($and).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$234 ($and).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$233 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$233 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$232 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$231 ($or).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$236 ($and).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$236 ($and).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$234 ($and).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$234 ($and).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$232 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$232 ($xor).
+Removed top 6 bits (of 7) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$231 ($or).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$231 ($or).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$228 ($or).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$225 ($or).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$not$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$235 ($not).
+Removed top 20 bits (of 21) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$228 ($or).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$228 ($or).
+Removed top 25 bits (of 26) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$225 ($or).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$225 ($or).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$not$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$235 ($not).
+Removed top 4 bits (of 6) from wire hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$501_Y.
+Removed top 3 bits (of 6) from wire hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$502_Y.
+Removed top 2 bits (of 6) from wire hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$503_Y.
+Removed top 1 bits (of 6) from wire hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$504_Y.
+Removed top 27 bits (of 32) from wire hmac.$auto_5692.
+Removed top 27 bits (of 32) from wire hmac.$auto_5693.
+Removed top 27 bits (of 32) from wire hmac.$auto_5695.
+Removed top 1 bits (of 3) from wire hmac.$flatten\gen_alert_tx[0].u_prim_alert_sender.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:139$77_Y.
+Removed top 2 bits (of 3) from wire hmac.$flatten\u_hmac.$2\st_d[2:0].
+Removed top 1 bits (of 3) from wire hmac.$flatten\u_hmac.$3\st_d[2:0].
+Removed top 22 bits (of 32) from wire hmac.$flatten\u_msg_fifo.$mul$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$921_Y.
+Removed top 22 bits (of 32) from wire hmac.$flatten\u_msg_fifo.$mul$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$929_Y.
+Removed top 27 bits (of 32) from wire hmac.$flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:70$900_Y.
+Removed top 4 bits (of 6) from wire hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$841_Y.
+Removed top 3 bits (of 6) from wire hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$842_Y.
+Removed top 2 bits (of 6) from wire hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$843_Y.
+Removed top 1 bits (of 6) from wire hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$844_Y.
+Removed top 25 bits (of 32) from wire hmac.$flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$775_Y.
+Removed top 25 bits (of 32) from wire hmac.$flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$778_Y.
+Removed top 25 bits (of 32) from wire hmac.$flatten\u_packer.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$776_Y.
+Removed top 25 bits (of 32) from wire hmac.$flatten\u_packer.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$779_Y.
+Removed top 5 bits (of 39) from wire hmac.$flatten\u_reg.\u_chk.\u_tlul_data_integ_dec.\u_data_chk.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:17$1805_Y.
+Removed top 3 bits (of 39) from wire hmac.$flatten\u_reg.\u_chk.\u_tlul_data_integ_dec.\u_data_chk.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:19$1811_Y.
+Removed top 1 bits (of 39) from wire hmac.$flatten\u_reg.\u_chk.\u_tlul_data_integ_dec.\u_data_chk.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:21$1817_Y.
+Removed top 2 bits (of 3) from wire hmac.$flatten\u_reg.\u_reg_if.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:79$717_Y.
+Removed top 1 bits (of 2) from wire hmac.$flatten\u_sha2.$2\fifo_st_d[1:0].
+Removed top 1 bits (of 2) from wire hmac.$flatten\u_sha2.$2\sha_st_d[1:0].
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$238_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$239_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$240_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:67$258_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:72$259_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$286_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$287_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$288_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$289_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$290_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$291_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$292_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$293_Y.
+Removed top 26 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:138$298_Y.
+Removed top 28 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:150$302_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$234_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$236_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$253_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$254_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$256_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$not$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$235_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$225_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$228_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$231_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$244_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$247_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$250_Y.
+Removed top 1023 bits (of 1024) from wire hmac.$flatten\u_sha2.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$222_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$232_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$233_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$237_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$251_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$252_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$255_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$257_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$272_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$273_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$274_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$275_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$276_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$277_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$278_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$279_Y.
+Removed top 2 bits (of 3) from wire hmac.$flatten\u_sha2.\u_pad.$10\st_d[2:0].
+Removed top 2 bits (of 3) from wire hmac.$flatten\u_sha2.\u_pad.$2\st_d[2:0].
+Removed top 1 bits (of 3) from wire hmac.$flatten\u_sha2.\u_pad.$3\st_d[2:0].
+Removed top 1 bits (of 3) from wire hmac.$flatten\u_sha2.\u_pad.$4\st_d[2:0].
+Removed top 1 bits (of 3) from wire hmac.$flatten\u_sha2.\u_pad.$5\st_d[2:0].
+Removed top 2 bits (of 3) from wire hmac.$flatten\u_sha2.\u_pad.$7\st_d[2:0].
+Removed top 25 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$0$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:254$951[31:0]$1064.
+Removed top 25 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$0$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:254$952[31:0]$1065.
+Removed top 25 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$0$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:254$953[31:0]$1066.
+Removed top 24 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1012_Y.
+Removed top 16 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1024_Y.
+Removed top 16 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1033_Y.
+Removed top 8 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1045_Y.
+Removed top 8 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1054_Y.
+Removed top 16 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$shift$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1017_Y.
+Removed top 8 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$shift$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1038_Y.
+Removed top 24 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$1015_Y.
+Removed top 24 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$1036_Y.
+Removed top 24 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$1057_Y.
+Removed top 28 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.\u_sramreqfifo.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:141$64_Y.
+Removed top 29 bits (of 32) from wire hmac.$procmux$3337_Y.
+Removed top 29 bits (of 32) from wire hmac.$procmux$3339_Y.
+Removed top 29 bits (of 32) from wire hmac.$procmux$3341_Y.
+Removed top 29 bits (of 32) from wire hmac.$procmux$3343_Y.
+
+3.56. Executing PEEPOPT pass (run peephole optimizers).
+right shiftmul pattern in hmac: shift=$flatten\u_msg_fifo.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$922, mul=$flatten\u_msg_fifo.$mul$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$921
+
+3.57. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 1 unused cells and 109 unused wires.
+
+
+3.58. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+
+3.59. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.60. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.61. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.62. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+
+Removed a total of 4 cells.
+
+3.63. Executing OPT_SHARE pass.
+
+3.64. Executing OPT_DFF pass (perform DFF optimizations).
+Adding EN signal on $procdff$5353 ($adff) from module hmac (D = $0\cfg_block[0:0], Q = \cfg_block).
+Adding EN signal on $procdff$5352 ($adff) from module hmac (D = { \tl_i [24] \u_reg.cfg_we \tl_i [25] \u_reg.cfg_we \tl_i [26] \u_reg.cfg_we \tl_i [27] \u_reg.cfg_we }, Q = \cfg_reg).
+Adding EN signal on $procdff$5351 ($adff) from module hmac (D = $0\msg_allowed[0:0], Q = \msg_allowed).
+Adding EN signal on $procdff$5350 ($adff) from module hmac (D = \fifo_empty, Q = \fifo_empty_q).
+Adding EN signal on $procdff$5349 ($adff) from module hmac (D = $0\message_length[63:0], Q = \message_length).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [31:0], Q = \secret_key [31:0]).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [63:32], Q = \secret_key [63:32]).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [95:64], Q = \secret_key [95:64]).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [127:96], Q = \secret_key [127:96]).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [159:128], Q = \secret_key [159:128]).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [191:160], Q = \secret_key [191:160]).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [223:192], Q = \secret_key [223:192]).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [255:224], Q = \secret_key [255:224]).
+Adding EN signal on $flatten\u_tlul_adapter.\u_sramreqfifo.$procdff$5438 ($adff) from module hmac (D = $flatten\u_tlul_adapter.\u_sramreqfifo.$procmux$5078_Y, Q = \u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.fifo_wptr).
+Adding EN signal on $flatten\u_tlul_adapter.\u_sramreqfifo.$procdff$5437 ($adff) from module hmac (D = $flatten\u_tlul_adapter.\u_sramreqfifo.$procmux$5070_Y, Q = \u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.fifo_rptr).
+Adding EN signal on $flatten\u_tlul_adapter.\u_sramreqfifo.$procdff$5436 ($dff) from module hmac (D = { \tl_i [59:56] 1'0 }, Q = \u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.storage).
+Adding EN signal on $flatten\u_tlul_adapter.\u_rspfifo.$procdff$5337 ($adff) from module hmac (D = $flatten\u_tlul_adapter.\u_rspfifo.$procmux$3238_Y, Q = \u_tlul_adapter.u_rspfifo.gen_normal_fifo.fifo_wptr).
+Adding EN signal on $flatten\u_tlul_adapter.\u_rspfifo.$procdff$5336 ($adff) from module hmac (D = $flatten\u_tlul_adapter.\u_rspfifo.$procmux$3230_Y, Q = \u_tlul_adapter.u_rspfifo.gen_normal_fifo.fifo_rptr).
+Adding EN signal on $flatten\u_tlul_adapter.\u_rspfifo.$procdff$5335 ($dff) from module hmac (D = { \u_tlul_adapter.rdata_tlword 1'1 }, Q = \u_tlul_adapter.u_rspfifo.gen_normal_fifo.storage).
+Adding EN signal on $flatten\u_tlul_adapter.\u_reqfifo.$procdff$5316 ($adff) from module hmac (D = $flatten\u_tlul_adapter.\u_reqfifo.$procmux$2343_Y, Q = \u_tlul_adapter.u_reqfifo.gen_normal_fifo.fifo_wptr).
+Adding EN signal on $flatten\u_tlul_adapter.\u_reqfifo.$procdff$5315 ($adff) from module hmac (D = $flatten\u_tlul_adapter.\u_reqfifo.$procmux$2335_Y, Q = \u_tlul_adapter.u_reqfifo.gen_normal_fifo.fifo_rptr).
+Adding EN signal on $flatten\u_tlul_adapter.\u_reqfifo.$procdff$5314 ($dff) from module hmac (D = { 1'0 \u_tlul_adapter.u_reqfifo.wdata [11] \u_tlul_adapter.error_internal \tl_i [101:92] }, Q = \u_tlul_adapter.u_reqfifo.gen_normal_fifo.storage).
+Adding EN signal on $flatten\u_sha2.\u_pad.$procdff$5312 ($adff) from module hmac (D = 5'00000, Q = \u_sha2.u_pad.tx_count [4:0]).
+Adding EN signal on $flatten\u_sha2.\u_pad.$procdff$5312 ($adff) from module hmac (D = $flatten\u_sha2.\u_pad.$0\tx_count[63:0] [63:5], Q = \u_sha2.u_pad.tx_count [63:5]).
+Adding EN signal on $flatten\u_sha2.\u_pad.$procdff$5311 ($adff) from module hmac (D = $flatten\u_sha2.\u_pad.$0\hash_process_flag[0:0], Q = \u_sha2.u_pad.hash_process_flag).
+Adding EN signal on $flatten\u_sha2.$procdff$5393 ($adff) from module hmac (D = $flatten\u_sha2.$0\hash[255:0], Q = \u_sha2.hash).
+Adding EN signal on $flatten\u_sha2.$procdff$5383 ($adff) from module hmac (D = 24'000000000000000000000000, Q = \u_sha2.digest [31:8]).
+Adding EN signal on $flatten\u_sha2.$procdff$5383 ($adff) from module hmac (D = $flatten\u_sha2.$0\digest[31:0] [7:0], Q = \u_sha2.digest [7:0]).
+Adding EN signal on $flatten\u_sha2.$procdff$5382 ($adff) from module hmac (D = $flatten\u_sha2.$0\round[5:0], Q = \u_sha2.round).
+Adding EN signal on $flatten\u_sha2.$procdff$5381 ($adff) from module hmac (D = $flatten\u_sha2.$0\w_index[3:0], Q = \u_sha2.w_index).
+Adding EN signal on $flatten\u_sha2.$procdff$5354 ($adff) from module hmac (D = $flatten\u_sha2.$0\w[511:0], Q = \u_sha2.w).
+Adding EN signal on $flatten\u_reg.\u_socket.\err_resp.$procdff$5449 ($adff) from module hmac (D = 1'0, Q = \u_reg.u_socket.err_resp.err_req_pending).
+Adding EN signal on $flatten\u_reg.\u_socket.$procdff$5310 ($adff) from module hmac (D = { 1'0 \u_reg.reg_steer }, Q = \u_reg.u_socket.dev_select_outstanding).
+Adding EN signal on $flatten\u_reg.\u_socket.$procdff$5309 ($adff) from module hmac (D = $flatten\u_reg.\u_socket.$0\num_req_outstanding[8:0], Q = \u_reg.u_socket.num_req_outstanding).
+Adding EN signal on $flatten\u_reg.\u_reg_if.$procdff$5343 ($adff) from module hmac (D = { 2'00 $auto_5740 [0] }, Q = \u_reg.u_reg_if.rspop).
+Adding EN signal on $flatten\u_reg.\u_reg_if.$procdff$5342 ($adff) from module hmac (D = \tl_i [101:100], Q = \u_reg.u_reg_if.reqsz).
+Adding EN signal on $flatten\u_reg.\u_reg_if.$procdff$5341 ($adff) from module hmac (D = \tl_i [99:92], Q = \u_reg.u_reg_if.reqid).
+Adding EN signal on $flatten\u_reg.\u_reg_if.$procdff$5340 ($adff) from module hmac (D = $flatten\u_reg.\u_reg_if.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:89$721_Y, Q = \u_reg.u_reg_if.error).
+Adding EN signal on $flatten\u_reg.\u_reg_if.$procdff$5339 ($adff) from module hmac (D = $flatten\u_reg.\u_reg_if.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:88$720_Y, Q = \u_reg.u_reg_if.rdata).
+Adding EN signal on $flatten\u_reg.\u_reg_if.$procdff$5338 ($adff) from module hmac (D = $flatten\u_reg.\u_reg_if.$0\outstanding[0:0], Q = \u_reg.u_reg_if.outstanding).
+Adding EN signal on $flatten\u_reg.\u_intr_state_hmac_err.$procdff$5452 ($adff) from module hmac (D = \u_reg.u_intr_state_hmac_err.d, Q = \u_reg.u_intr_state_hmac_err.q).
+Adding EN signal on $flatten\u_reg.\u_intr_state_hmac_done.$procdff$5452 ($adff) from module hmac (D = \u_reg.u_intr_state_hmac_done.d, Q = \u_reg.u_intr_state_hmac_done.q).
+Adding EN signal on $flatten\u_reg.\u_intr_state_fifo_empty.$procdff$5452 ($adff) from module hmac (D = \u_reg.u_intr_state_fifo_empty.d, Q = \u_reg.u_intr_state_fifo_empty.q).
+Adding EN signal on $flatten\u_reg.\u_err_code.$procdff$5454 ($adff) from module hmac (D = { 29'00000000000000000000000000000 \u_reg.u_err_code.d [2:0] }, Q = \u_reg.u_err_code.q).
+Adding EN signal on $flatten\u_reg.$procdff$5317 ($adff) from module hmac (D = 1'1, Q = \u_reg.intg_err_q).
+Adding EN signal on $flatten\u_packer.$procdff$5333 ($adff) from module hmac (D = $flatten\u_packer.$0\pos[6:0], Q = \u_packer.pos).
+Adding EN signal on $flatten\u_packer.$procdff$5332 ($adff) from module hmac (D = $flatten\u_packer.$0\stored_mask[63:0], Q = \u_packer.stored_mask).
+Adding EN signal on $flatten\u_packer.$procdff$5331 ($adff) from module hmac (D = $flatten\u_packer.$0\stored_data[63:0], Q = \u_packer.stored_data).
+Adding EN signal on $flatten\u_msg_fifo.$procdff$5328 ($adff) from module hmac (D = $flatten\u_msg_fifo.$procmux$3070_Y, Q = \u_msg_fifo.gen_normal_fifo.fifo_wptr).
+Adding EN signal on $flatten\u_msg_fifo.$procdff$5327 ($adff) from module hmac (D = $flatten\u_msg_fifo.$procmux$3062_Y, Q = \u_msg_fifo.gen_normal_fifo.fifo_rptr).
+Adding EN signal on $flatten\u_msg_fifo.$procdff$5324 ($dff) from module hmac (D = $flatten\u_msg_fifo.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$936_Y, Q = \u_msg_fifo.gen_normal_fifo.storage).
+Adding EN signal on $flatten\u_hmac.$procdff$5323 ($adff) from module hmac (D = $flatten\u_hmac.$0\reg_hash_process_flag[0:0], Q = \u_hmac.reg_hash_process_flag).
+Adding EN signal on $flatten\u_hmac.$procdff$5322 ($adff) from module hmac (D = \u_hmac.round_d, Q = \u_hmac.round_q).
+Adding EN signal on $flatten\u_hmac.$procdff$5321 ($adff) from module hmac (D = $flatten\u_hmac.$0\fifo_wdata_sel[2:0], Q = \u_hmac.fifo_wdata_sel).
+Adding EN signal on $flatten\u_hmac.$procdff$5319 ($adff) from module hmac (D = 5'00000, Q = \u_hmac.txcount [4:0]).
+Adding EN signal on $flatten\u_hmac.$procdff$5319 ($adff) from module hmac (D = $flatten\u_hmac.$0\txcount[63:0] [63:5], Q = \u_hmac.txcount [63:5]).
+Adding EN signal on $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procdff$5442 ($adff) from module hmac (D = \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.state_d, Q = \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.state_q).
+Adding EN signal on $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procdff$5442 ($adff) from module hmac (D = \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.state_d, Q = \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.state_q).
+Adding EN signal on $flatten\gen_alert_tx[0].u_prim_alert_sender.$procdff$5431 ($adff) from module hmac (D = \gen_alert_tx[0].u_prim_alert_sender.state_d, Q = \gen_alert_tx[0].u_prim_alert_sender.state_q).
+Setting constant 0-bit at position 0 on $auto_5958 ($adffe) from module hmac.
+Setting constant 0-bit at position 1 on $auto_5958 ($adffe) from module hmac.
+Setting constant 0-bit at position 2 on $auto_5958 ($adffe) from module hmac.
+Setting constant 0-bit at position 3 on $auto_5958 ($adffe) from module hmac.
+Setting constant 0-bit at position 4 on $auto_5958 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 1 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 2 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 3 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 4 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 5 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 6 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 7 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 8 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 9 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 10 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 11 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 12 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 13 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 14 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 15 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 16 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 17 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 18 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 19 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 20 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 21 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 22 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 23 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5888 ($adffe) from module hmac.
+Setting constant 0-bit at position 1 on $auto_5888 ($adffe) from module hmac.
+Setting constant 0-bit at position 2 on $auto_5888 ($adffe) from module hmac.
+Setting constant 0-bit at position 3 on $auto_5888 ($adffe) from module hmac.
+Setting constant 0-bit at position 4 on $auto_5888 ($adffe) from module hmac.
+Setting constant 0-bit at position 3 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 4 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 5 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 6 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 7 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 8 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 9 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 10 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 11 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 12 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 13 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 14 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 15 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 16 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 17 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 18 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 19 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 20 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 21 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 22 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 23 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 24 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 25 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 26 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 27 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 28 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 29 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 30 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 31 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 1 on $auto_5926 ($adffe) from module hmac.
+Setting constant 0-bit at position 2 on $auto_5926 ($adffe) from module hmac.
+Setting constant 0-bit at position 1 on $auto_5918 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on hmac:u_reg.u_socket.err_resp.err_req_pending_5917 ($adffe) from module hmac.
+Setting constant 0-bit at position 12 on $auto_5887 ($dffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5881 ($dffe) from module hmac.
+[#visit=86, #solve=0, #remove=69, time=0.41 sec.]
+
+3.65. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 35 unused cells and 43 unused wires.
+
+
+3.66. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+
+3.67. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.68. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+ New ctrl vector for $pmux cell $flatten\u_packer.$procmux$3113: { $flatten\u_packer.$procmux$3116_CMP $flatten\u_packer.$procmux$3115_CMP $flatten\u_packer.$procmux$3114_CMP }
+ New ctrl vector for $pmux cell $flatten\u_packer.$procmux$3118: { $flatten\u_packer.$procmux$3116_CMP $flatten\u_packer.$procmux$3115_CMP $flatten\u_packer.$procmux$3114_CMP }
+ New ctrl vector for $pmux cell $flatten\u_packer.$procmux$3222: { $flatten\u_packer.$procmux$3116_CMP $flatten\u_packer.$procmux$3115_CMP $flatten\u_packer.$procmux$3114_CMP }
+ Optimizing cells in module \hmac.
+Performed a total of 3 changes.
+
+3.69. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+
+Removed a total of 21 cells.
+
+3.70. Executing OPT_SHARE pass.
+
+3.71. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=82, #solve=0, #remove=0, time=0.46 sec.]
+
+3.72. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 1 unused cells and 28 unused wires.
+
+
+3.73. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.74. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.75. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.76. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.77. Executing OPT_SHARE pass.
+
+3.78. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=82, #solve=0, #remove=0, time=0.51 sec.]
+
+3.79. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.80. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+RUN-OPT ITERATIONS DONE : 3
+
+3.81. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.82. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.83. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.84. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.85. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.86. Executing OPT_SHARE pass.
+
+3.87. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=82, #solve=0, #remove=0, time=0.68 sec.]
+
+3.88. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.89. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+RUN-OPT ITERATIONS DONE : 1
+
+3.90. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.91. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.92. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.93. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.94. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.95. Executing OPT_SHARE pass.
+
+3.96. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=82, #solve=0, #remove=0, time=0.60 sec.]
+
+3.97. Executing OPT_DFF pass (perform DFF optimizations).
+Setting constant 0-bit at position 0 on $auto_5879 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5880 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5882 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5883 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5885 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5886 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $flatten\u_reg.\u_socket.\err_resp.$procdff$5450 ($adff) from module hmac.
+[#visit=82, #solve=2145, #remove=7, time=456.95 sec.]
+
+3.98. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 3 unused cells and 3 unused wires.
+
+
+3.99. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+
+RUN-OPT ITERATIONS DONE : 1
+
+3.100. Executing WREDUCE pass (reducing word size of cells).
+Removed cell hmac.$flatten\u_tlul_adapter.\u_sramreqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$56 ($add).
+Removed cell hmac.$flatten\u_tlul_adapter.\u_sramreqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$61 ($add).
+Removed cell hmac.$flatten\u_tlul_adapter.\u_rspfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$758 ($add).
+Removed cell hmac.$flatten\u_tlul_adapter.\u_rspfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$763 ($add).
+Removed top 1 bits (of 13) from mux cell hmac.$flatten\u_tlul_adapter.\u_reqfifo.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:141$1623 ($mux).
+Removed cell hmac.$flatten\u_tlul_adapter.\u_reqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$1615 ($add).
+Removed cell hmac.$flatten\u_tlul_adapter.\u_reqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$1620 ($add).
+Removed top 1 bits (of 2) from port A of cell hmac.$flatten\u_tlul_adapter.$ne$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:142$1118 ($ne).
+Removed top 1 bits (of 2) from port A of cell hmac.$flatten\u_tlul_adapter.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:115$1149 ($eq).
+Removed top 1 bits (of 4) from FF cell hmac.$auto_5995 ($dffe).
+Removed top 2 bits (of 3) from port B of cell hmac.$auto_5988 ($ne).
+Removed top 1 bits (of 3) from port B of cell hmac.$auto_5984 ($ne).
+Removed top 1 bits (of 3) from port B of cell hmac.$auto_5982 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$auto_5975 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$auto_5966 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$auto_5957 ($ne).
+Removed top 4 bits (of 5) from port B of cell hmac.$auto_5916 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$auto_5913 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$auto_5910 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$auto_5827 ($ne).
+Removed top 1 bits (of 3) from wire hmac.$auto_5723.
+Removed top 2 bits (of 3) from wire hmac.$auto_5724.
+Removed top 1 bits (of 3) from wire hmac.$auto_5725.
+Removed top 22 bits (of 32) from wire hmac.$auto_5727.
+Removed top 27 bits (of 32) from wire hmac.$auto_5728.
+Removed top 4 bits (of 6) from wire hmac.$auto_5729.
+Removed top 3 bits (of 6) from wire hmac.$auto_5730.
+Removed top 2 bits (of 6) from wire hmac.$auto_5731.
+Removed top 1 bits (of 6) from wire hmac.$auto_5732.
+Removed top 25 bits (of 32) from wire hmac.$auto_5733.
+Removed top 25 bits (of 32) from wire hmac.$auto_5734.
+Removed top 25 bits (of 32) from wire hmac.$auto_5735.
+Removed top 25 bits (of 32) from wire hmac.$auto_5736.
+Removed top 5 bits (of 39) from wire hmac.$auto_5737.
+Removed top 3 bits (of 39) from wire hmac.$auto_5738.
+Removed top 1 bits (of 39) from wire hmac.$auto_5739.
+Removed top 2 bits (of 3) from wire hmac.$auto_5740.
+Removed top 1 bits (of 2) from wire hmac.$auto_5741.
+Removed top 1 bits (of 2) from wire hmac.$auto_5742.
+Removed top 31 bits (of 32) from wire hmac.$auto_5743.
+Removed top 31 bits (of 32) from wire hmac.$auto_5744.
+Removed top 31 bits (of 32) from wire hmac.$auto_5745.
+Removed top 31 bits (of 32) from wire hmac.$auto_5746.
+Removed top 31 bits (of 32) from wire hmac.$auto_5747.
+Removed top 31 bits (of 32) from wire hmac.$auto_5748.
+Removed top 31 bits (of 32) from wire hmac.$auto_5749.
+Removed top 31 bits (of 32) from wire hmac.$auto_5750.
+Removed top 31 bits (of 32) from wire hmac.$auto_5751.
+Removed top 31 bits (of 32) from wire hmac.$auto_5752.
+Removed top 31 bits (of 32) from wire hmac.$auto_5753.
+Removed top 31 bits (of 32) from wire hmac.$auto_5754.
+Removed top 31 bits (of 32) from wire hmac.$auto_5755.
+Removed top 31 bits (of 32) from wire hmac.$auto_5756.
+Removed top 31 bits (of 32) from wire hmac.$auto_5757.
+Removed top 26 bits (of 32) from wire hmac.$auto_5758.
+Removed top 28 bits (of 32) from wire hmac.$auto_5759.
+Removed top 31 bits (of 32) from wire hmac.$auto_5760.
+Removed top 31 bits (of 32) from wire hmac.$auto_5761.
+Removed top 31 bits (of 32) from wire hmac.$auto_5762.
+Removed top 31 bits (of 32) from wire hmac.$auto_5763.
+Removed top 31 bits (of 32) from wire hmac.$auto_5764.
+Removed top 31 bits (of 32) from wire hmac.$auto_5765.
+Removed top 1023 bits (of 1024) from wire hmac.$auto_5772.
+Removed top 31 bits (of 32) from wire hmac.$auto_5773.
+Removed top 31 bits (of 32) from wire hmac.$auto_5774.
+Removed top 31 bits (of 32) from wire hmac.$auto_5775.
+Removed top 31 bits (of 32) from wire hmac.$auto_5776.
+Removed top 31 bits (of 32) from wire hmac.$auto_5777.
+Removed top 31 bits (of 32) from wire hmac.$auto_5778.
+Removed top 31 bits (of 32) from wire hmac.$auto_5779.
+Removed top 31 bits (of 32) from wire hmac.$auto_5780.
+Removed top 31 bits (of 32) from wire hmac.$auto_5781.
+Removed top 31 bits (of 32) from wire hmac.$auto_5782.
+Removed top 31 bits (of 32) from wire hmac.$auto_5783.
+Removed top 31 bits (of 32) from wire hmac.$auto_5784.
+Removed top 31 bits (of 32) from wire hmac.$auto_5785.
+Removed top 31 bits (of 32) from wire hmac.$auto_5786.
+Removed top 31 bits (of 32) from wire hmac.$auto_5787.
+Removed top 2 bits (of 3) from wire hmac.$auto_5788.
+Removed top 2 bits (of 3) from wire hmac.$auto_5789.
+Removed top 1 bits (of 3) from wire hmac.$auto_5790.
+Removed top 1 bits (of 3) from wire hmac.$auto_5791.
+Removed top 1 bits (of 3) from wire hmac.$auto_5792.
+Removed top 2 bits (of 3) from wire hmac.$auto_5793.
+Removed top 25 bits (of 32) from wire hmac.$auto_5794.
+Removed top 25 bits (of 32) from wire hmac.$auto_5795.
+Removed top 25 bits (of 32) from wire hmac.$auto_5796.
+Removed top 24 bits (of 32) from wire hmac.$auto_5797.
+Removed top 16 bits (of 32) from wire hmac.$auto_5798.
+Removed top 16 bits (of 32) from wire hmac.$auto_5799.
+Removed top 8 bits (of 32) from wire hmac.$auto_5800.
+Removed top 8 bits (of 32) from wire hmac.$auto_5801.
+Removed top 16 bits (of 32) from wire hmac.$auto_5802.
+Removed top 8 bits (of 32) from wire hmac.$auto_5803.
+Removed top 24 bits (of 32) from wire hmac.$auto_5806.
+Removed top 29 bits (of 32) from wire hmac.$auto_5808.
+Removed top 29 bits (of 32) from wire hmac.$auto_5809.
+Removed top 29 bits (of 32) from wire hmac.$auto_5810.
+Removed top 29 bits (of 32) from wire hmac.$auto_5811.
+Removed top 24 bits (of 32) from wire hmac.$flatten\u_sha2.$0\digest[31:0].
+
+3.101. Executing PEEPOPT pass (run peephole optimizers).
+
+3.102. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 0 unused cells and 92 unused wires.
+
+
+3.103. Executing DEMUXMAP pass.
+
+3.104. Executing SPLITNETS pass (splitting up multi-bit signals).
+
+3.105. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 2046
+ Number of wire bits: 31698
+ Number of public wires: 1135
+ Number of public wire bits: 19171
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 1
+ Number of memory bits: 4096
+ Number of processes: 0
+ Number of cells: 1392
+ $add 94
+ $adff 26
+ $adffe 51
+ $and 134
+ $dffe 4
+ $eq 86
+ $ge 2
+ $le 2
+ $logic_and 36
+ $logic_not 31
+ $logic_or 11
+ $lt 1
+ $meminit 1
+ $memrd_v2 1
+ $mul 1
+ $mux 475
+ $ne 19
+ $neg 6
+ $not 54
+ $or 71
+ $pmux 34
+ $reduce_and 16
+ $reduce_bool 22
+ $reduce_or 26
+ $reduce_xor 30
+ $scopeinfo 97
+ $shift 9
+ $shiftx 6
+ $shl 3
+ $shr 2
+ $sub 7
+ $xor 34
+
+3.106. Executing RS_DSP_MULTADD pass.
+
+3.107. Executing WREDUCE pass (reducing word size of cells).
+
+3.108. Executing RS_DSP_MACC pass.
+
+3.109. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.110. Executing TECHMAP pass (map to technology primitives).
+
+3.110.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation.
+Generating RTLIL representation for module `\_80_mul'.
+Generating RTLIL representation for module `\_90_soft_mul'.
+Successfully finished Verilog frontend.
+
+3.110.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.111. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 2052
+ Number of wire bits: 32757
+ Number of public wires: 1135
+ Number of public wire bits: 19171
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 1
+ Number of memory bits: 4096
+ Number of processes: 0
+ Number of cells: 1392
+ $__RS_MUL10X9 1
+ $add 94
+ $adff 26
+ $adffe 51
+ $and 134
+ $dffe 4
+ $eq 86
+ $ge 2
+ $le 2
+ $logic_and 36
+ $logic_not 31
+ $logic_or 11
+ $lt 1
+ $meminit 1
+ $memrd_v2 1
+ $mux 475
+ $ne 19
+ $neg 6
+ $not 54
+ $or 71
+ $pmux 34
+ $reduce_and 16
+ $reduce_bool 22
+ $reduce_or 26
+ $reduce_xor 30
+ $scopeinfo 97
+ $shift 9
+ $shiftx 6
+ $shl 3
+ $shr 2
+ $sub 7
+ $xor 34
+
+3.112. Executing TECHMAP pass (map to technology primitives).
+
+3.112.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation.
+Generating RTLIL representation for module `\_80_mul'.
+Generating RTLIL representation for module `\_90_soft_mul'.
+Successfully finished Verilog frontend.
+
+3.112.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.113. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 2052
+ Number of wire bits: 32757
+ Number of public wires: 1135
+ Number of public wire bits: 19171
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 1
+ Number of memory bits: 4096
+ Number of processes: 0
+ Number of cells: 1392
+ $__RS_MUL10X9 1
+ $add 94
+ $adff 26
+ $adffe 51
+ $and 134
+ $dffe 4
+ $eq 86
+ $ge 2
+ $le 2
+ $logic_and 36
+ $logic_not 31
+ $logic_or 11
+ $lt 1
+ $meminit 1
+ $memrd_v2 1
+ $mux 475
+ $ne 19
+ $neg 6
+ $not 54
+ $or 71
+ $pmux 34
+ $reduce_and 16
+ $reduce_bool 22
+ $reduce_or 26
+ $reduce_xor 30
+ $scopeinfo 97
+ $shift 9
+ $shiftx 6
+ $shl 3
+ $shr 2
+ $sub 7
+ $xor 34
+
+3.114. Executing TECHMAP pass (map to technology primitives).
+
+3.114.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp.v' to AST representation.
+Generating RTLIL representation for module `\_80_mul'.
+Generating RTLIL representation for module `\_90_soft_mul'.
+Successfully finished Verilog frontend.
+
+3.114.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.115. Executing TECHMAP pass (map to technology primitives).
+
+3.115.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp.v' to AST representation.
+Generating RTLIL representation for module `\_80_mul'.
+Generating RTLIL representation for module `\_90_soft_mul'.
+Successfully finished Verilog frontend.
+
+3.115.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.116. Executing TECHMAP pass (map to technology primitives).
+
+3.116.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v' to AST representation.
+Generating RTLIL representation for module `\$__RS_MUL20X18'.
+Generating RTLIL representation for module `\$__RS_MUL10X9'.
+Successfully finished Verilog frontend.
+
+3.116.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.117. Executing RS_DSP_SIMD pass.
+
+3.118. Executing TECHMAP pass (map to technology primitives).
+
+3.118.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v' to AST representation.
+Generating RTLIL representation for module `\dsp_t1_20x18x64_cfg_ports'.
+Generating RTLIL representation for module `\dsp_t1_10x9x32_cfg_params'.
+Successfully finished Verilog frontend.
+
+3.118.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.119. Executing TECHMAP pass (map to technology primitives).
+
+3.119.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSP3'.
+Successfully finished Verilog frontend.
+
+3.119.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.120. Executing rs_pack_dsp_regs pass.
+
+
+3.121. Executing RS_DSP_IO_REGS pass.
+
+3.122. Executing TECHMAP pass (map to technology primitives).
+
+3.122.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v' to AST representation.
+Generating RTLIL representation for module `\RS_DSP_MULTACC'.
+Generating RTLIL representation for module `\RS_DSP_MULT'.
+Generating RTLIL representation for module `\RS_DSP_MULT_REGIN'.
+Generating RTLIL representation for module `\RS_DSP_MULT_REGOUT'.
+Generating RTLIL representation for module `\RS_DSP_MULT_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSP_MULTADD'.
+Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN'.
+Generating RTLIL representation for module `\RS_DSP_MULTADD_REGOUT'.
+Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN'.
+Generating RTLIL representation for module `\RS_DSP_MULTACC_REGOUT'.
+Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN_REGOUT'.
+Successfully finished Verilog frontend.
+
+3.122.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.123. Executing TECHMAP pass (map to technology primitives).
+
+3.123.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSP3'.
+Successfully finished Verilog frontend.
+
+3.123.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.124. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 2096
+ Number of wire bits: 33154
+ Number of public wires: 1135
+ Number of public wire bits: 19171
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 1
+ Number of memory bits: 4096
+ Number of processes: 0
+ Number of cells: 1392
+ $add 94
+ $adff 26
+ $adffe 51
+ $and 134
+ $dffe 4
+ $eq 86
+ $ge 2
+ $le 2
+ $logic_and 36
+ $logic_not 31
+ $logic_or 11
+ $lt 1
+ $meminit 1
+ $memrd_v2 1
+ $mux 475
+ $ne 19
+ $neg 6
+ $not 54
+ $or 71
+ $pmux 34
+ $reduce_and 16
+ $reduce_bool 22
+ $reduce_or 26
+ $reduce_xor 30
+ $scopeinfo 97
+ $shift 9
+ $shiftx 6
+ $shl 3
+ $shr 2
+ $sub 7
+ $xor 34
+ DSP19X2 1
+
+3.125. Executing ALUMACC pass (create $alu and $macc cells).
+Extracting $alu and $macc cells in module hmac:
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$502 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$503 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$504 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$505 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$506 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$507 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$508 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$509 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$510 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$511 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$512 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$513 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$514 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$515 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$516 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$517 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$518 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$519 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$520 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$521 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$522 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$523 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$524 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$525 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$526 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$527 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$528 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$529 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$530 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:334$536 ($add).
+ creating $macc model for $auto_5691 ($neg).
+ creating $macc model for $flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1225 ($add).
+ creating $macc model for $flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:146$1256 ($add).
+ creating $macc model for $flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:175$1194 ($add).
+ creating $macc model for $flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1224 ($sub).
+ creating $macc model for $flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1226 ($sub).
+ creating $macc model for $flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$920 ($add).
+ creating $macc model for $flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$915 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$501 ($add).
+ creating $macc model for $flatten\u_msg_fifo.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$930 ($neg).
+ creating $macc model for $flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:69$899 ($sub).
+ creating $macc model for $flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:70$900 ($sub).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$841 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$842 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$843 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$844 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$845 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$846 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$847 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$848 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$849 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$850 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$851 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$852 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$853 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$854 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$855 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$856 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$857 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$858 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$859 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$860 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$861 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$862 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$863 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$864 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$865 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$866 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$867 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$868 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$869 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$870 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:62$773 ($add).
+ creating $macc model for $flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$775 ($sub).
+ creating $macc model for $flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$778 ($sub).
+ creating $macc model for $flatten\u_reg.\u_socket.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:106$1963 ($add).
+ creating $macc model for $flatten\u_reg.\u_socket.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:110$1964 ($sub).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$238 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$239 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$240 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:67$258 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:72$259 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$462 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$463 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$464 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$286 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$287 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$288 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$289 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$290 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$291 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$292 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$293 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:138$298 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:150$302 ($add).
+ creating $macc model for $flatten\u_sha2.\u_pad.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:304$1650 ($add).
+ creating $macc model for $flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1077 ($add).
+ creating $macc model for $flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1086 ($add).
+ creating $macc model for $flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1095 ($add).
+ creating $macc model for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1073 ($neg).
+ creating $macc model for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1078 ($neg).
+ creating $macc model for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1087 ($neg).
+ creating $macc model for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1096 ($neg).
+ merging $macc model for $flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1095 into $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1096.
+ merging $macc model for $flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1086 into $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1087.
+ merging $macc model for $flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1077 into $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1078.
+ merging $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$463 into $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$464.
+ merging $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$462 into $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$464.
+ merging $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:67$258 into $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260.
+ merging $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$240 into $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241.
+ merging $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$239 into $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241.
+ merging $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$238 into $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$870 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$869 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$868 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$867 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$866 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$865 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$864 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$863 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$862 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$861 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$860 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$859 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$858 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$857 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$856 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$855 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$854 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$853 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$852 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$851 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$850 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$849 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$848 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$847 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$846 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$845 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$844 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$843 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$842 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$841 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1225 into $flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1226.
+ merging $macc model for $flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:70$900 into $auto_5691.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$530 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$529 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$528 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$527 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$526 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$525 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$524 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$523 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$522 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$521 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$520 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$519 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$518 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$517 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$516 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$515 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$514 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$513 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$512 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$511 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$510 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$509 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$508 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$507 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$506 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$505 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$504 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$503 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$502 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$501 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:334$536.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:62$773.
+ creating $alu model for $macc $flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:146$1256.
+ creating $alu model for $macc $flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$775.
+ creating $alu model for $macc $auto_5691.
+ creating $alu model for $macc $flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:175$1194.
+ creating $alu model for $macc $flatten\u_reg.\u_socket.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:106$1963.
+ creating $alu model for $macc $flatten\u_reg.\u_socket.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:110$1964.
+ creating $alu model for $macc $flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1224.
+ creating $alu model for $macc $flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$778.
+ creating $alu model for $macc $flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:69$899.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:72$259.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260.
+ creating $alu model for $macc $flatten\u_msg_fifo.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$930.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$286.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$287.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$288.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$289.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$290.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$291.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$292.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$293.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:138$298.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:150$302.
+ creating $alu model for $macc $flatten\u_sha2.\u_pad.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:304$1650.
+ creating $alu model for $macc $flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$915.
+ creating $alu model for $macc $flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$920.
+ creating $alu model for $macc $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1073.
+ creating $macc cell for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:62$773: $auto_6087
+ creating $macc cell for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:334$536: $auto_6088
+ creating $macc cell for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1096: $auto_6089
+ creating $macc cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241: $auto_6090
+ creating $macc cell for $flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1226: $auto_6091
+ creating $macc cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$464: $auto_6092
+ creating $macc cell for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1078: $auto_6093
+ creating $macc cell for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1087: $auto_6094
+ creating $alu model for $flatten\u_hmac.$ge$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:238$1204 ($ge): new $alu
+ creating $alu model for $flatten\u_packer.$ge$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:208$835 ($ge): new $alu
+ creating $alu model for $flatten\u_packer.$le$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:216$837 ($le): merged with $flatten\u_packer.$ge$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:208$835.
+ creating $alu model for $flatten\u_packer.$le$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$777 ($le): new $alu
+ creating $alu model for $flatten\u_sha2.$lt$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:266$316 ($lt): new $alu
+ creating $alu cell for $flatten\u_sha2.$lt$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:266$316: $auto_6099
+ creating $alu cell for $flatten\u_packer.$le$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$777: $auto_6104
+ creating $alu cell for $flatten\u_packer.$ge$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:208$835, $flatten\u_packer.$le$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:216$837: $auto_6117
+ creating $alu cell for $flatten\u_hmac.$ge$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:238$1204: $auto_6132
+ creating $alu cell for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1073: $auto_6145
+ creating $alu cell for $flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$920: $auto_6148
+ creating $alu cell for $flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$915: $auto_6151
+ creating $alu cell for $flatten\u_sha2.\u_pad.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:304$1650: $auto_6154
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:150$302: $auto_6157
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:138$298: $auto_6160
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$293: $auto_6163
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$292: $auto_6166
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$291: $auto_6169
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$290: $auto_6172
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$289: $auto_6175
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$288: $auto_6178
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$287: $auto_6181
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$286: $auto_6184
+ creating $alu cell for $flatten\u_msg_fifo.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$930: $auto_6187
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260: $auto_6190
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:72$259: $auto_6193
+ creating $alu cell for $flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:69$899: $auto_6196
+ creating $alu cell for $flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$778: $auto_6199
+ creating $alu cell for $flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1224: $auto_6202
+ creating $alu cell for $flatten\u_reg.\u_socket.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:110$1964: $auto_6205
+ creating $alu cell for $flatten\u_reg.\u_socket.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:106$1963: $auto_6208
+ creating $alu cell for $flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:175$1194: $auto_6211
+ creating $alu cell for $auto_5691: $auto_6214
+ creating $alu cell for $flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$775: $auto_6217
+ creating $alu cell for $flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:146$1256: $auto_6220
+ created 30 $alu and 8 $macc cells.
+
+3.126. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+
+3.127. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.128. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.129. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.130. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.131. Executing OPT_SHARE pass.
+
+3.132. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=81, #solve=0, #remove=0, time=0.48 sec.]
+
+3.133. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 74 unused cells and 128 unused wires.
+
+
+3.134. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.135. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.136. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.137. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.138. Executing OPT_SHARE pass.
+
+3.139. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=81, #solve=0, #remove=0, time=0.50 sec.]
+
+3.140. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.141. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+RUN-OPT ITERATIONS DONE : 2
+
+3.142. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 2049
+ Number of wire bits: 32075
+ Number of public wires: 1133
+ Number of public wire bits: 19159
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 1
+ Number of memory bits: 4096
+ Number of processes: 0
+ Number of cells: 1333
+ $adff 26
+ $adffe 51
+ $alu 30
+ $and 134
+ $dffe 4
+ $eq 85
+ $logic_and 36
+ $logic_not 31
+ $logic_or 11
+ $macc 8
+ $meminit 1
+ $memrd_v2 1
+ $mux 475
+ $ne 18
+ $not 61
+ $or 74
+ $pmux 34
+ $reduce_and 19
+ $reduce_bool 22
+ $reduce_or 30
+ $reduce_xor 30
+ $scopeinfo 97
+ $shift 9
+ $shiftx 6
+ $shl 3
+ $shr 2
+ $xor 34
+ DSP19X2 1
+
+3.143. Executing MEMORY pass.
+
+3.143.1. Executing OPT_MEM pass (optimize memories).
+Performed a total of 0 transformations.
+
+3.143.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
+Performed a total of 0 transformations.
+
+3.143.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
+
+3.143.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
+
+3.143.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
+Checking read port `$flatten\u_reg.$auto_1966'[0] in module `\hmac': no output FF found.
+Checking read port address `$flatten\u_reg.$auto_1966'[0] in module `\hmac': no address FF found.
+
+3.143.6. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.143.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
+
+3.143.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
+Performed a total of 0 transformations.
+
+3.143.9. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.143.10. Executing MEMORY_COLLECT pass (generating $mem cells).
+
+3.144. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 2049
+ Number of wire bits: 32075
+ Number of public wires: 1133
+ Number of public wire bits: 19159
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 1332
+ $adff 26
+ $adffe 51
+ $alu 30
+ $and 134
+ $dffe 4
+ $eq 85
+ $logic_and 36
+ $logic_not 31
+ $logic_or 11
+ $macc 8
+ $mem_v2 1
+ $mux 475
+ $ne 18
+ $not 61
+ $or 74
+ $pmux 34
+ $reduce_and 19
+ $reduce_bool 22
+ $reduce_or 30
+ $reduce_xor 30
+ $scopeinfo 97
+ $shift 9
+ $shiftx 6
+ $shl 3
+ $shr 2
+ $xor 34
+ DSP19X2 1
+
+3.145. Executing MUXPACK pass ($mux cell cascades to $pmux).
+Converting hmac.$flatten\u_hmac.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:123$1235 ... hmac.$flatten\u_hmac.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1237 to a pmux with 3 cases.
+Converting hmac.$flatten\u_reg.$procmux$2353 ... hmac.$flatten\u_reg.$procmux$2403 to a pmux with 26 cases.
+Converting hmac.$flatten\u_reg.$procmux$2408 ... hmac.$flatten\u_reg.$procmux$2458 to a pmux with 26 cases.
+Converting hmac.$flatten\u_reg.$procmux$2463 ... hmac.$flatten\u_reg.$procmux$2513 to a pmux with 26 cases.
+Converting hmac.$flatten\u_reg.$procmux$2518 ... hmac.$flatten\u_reg.$procmux$2568 to a pmux with 26 cases.
+Converting hmac.$flatten\u_reg.$procmux$2573 ... hmac.$flatten\u_reg.$procmux$2611 to a pmux with 20 cases.
+Converting hmac.$flatten\u_reg.$procmux$2613 ... hmac.$flatten\u_reg.$procmux$2623 to a pmux with 6 cases.
+Converting hmac.$flatten\u_reg.$procmux$2628 ... hmac.$flatten\u_reg.$procmux$2678 to a pmux with 26 cases.
+Converted 159 (p)mux cells into 8 pmux cells.
+
+
+3.146. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 0 unused cells and 151 unused wires.
+
+
+3.147. Executing MEMORY_LIBMAP pass (mapping memories to cells).
+
+3.148. Executing MEMORY_LIBMAP pass (mapping memories to cells).
+Warning: Asyncronous read in BRAM is not supported, memory will be mapped to soft logic.
+found attribute 'ram_block = logic' on memory hmac.$flatten\u_reg.$auto_1966, forced mapping to FF
+using FF mapping for memory hmac.$flatten\u_reg.$auto_1966
+
+3.149. Executing Rs_BRAM_Split pass.
+
+3.150. Executing TECHMAP pass (map to technology primitives).
+
+3.150.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v' to AST representation.
+Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_TDP'.
+Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_TDP'.
+Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_SDP'.
+Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_SDP'.
+Successfully finished Verilog frontend.
+
+3.150.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.151. Executing TECHMAP pass (map to technology primitives).
+
+3.151.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v' to AST representation.
+Generating RTLIL representation for module `\BRAM2x18_TDP'.
+Generating RTLIL representation for module `\BRAM2x18_SDP'.
+Successfully finished Verilog frontend.
+
+3.151.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.152. Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs).
+
+3.153. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.154. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.155. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.156. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+ New ctrl vector for $pmux cell $flatten\u_reg.$procmux$2353: { \u_reg.addr_hit [17] $auto_6242 \u_reg.addr_hit [25] \u_reg.addr_hit [26] }
+ New ctrl vector for $pmux cell $flatten\u_reg.$procmux$2408: { \u_reg.addr_hit [4] \u_reg.addr_hit [17] $auto_6244 \u_reg.addr_hit [25] \u_reg.addr_hit [26] }
+ New ctrl vector for $pmux cell $flatten\u_reg.$procmux$2463: { \u_reg.addr_hit [4] \u_reg.addr_hit [7] \u_reg.addr_hit [17] $auto_6246 \u_reg.addr_hit [25] \u_reg.addr_hit [26] }
+ New ctrl vector for $pmux cell $flatten\u_reg.$procmux$2518: { \u_reg.addr_hit [4] \u_reg.addr_hit [6] \u_reg.addr_hit [7] \u_reg.addr_hit [17] $auto_6248 \u_reg.addr_hit [25] \u_reg.addr_hit [26] }
+ New ctrl vector for $pmux cell $flatten\u_reg.$procmux$2573: { \u_reg.addr_hit [17] $auto_6250 \u_reg.addr_hit [25] \u_reg.addr_hit [26] }
+ New ctrl vector for $pmux cell $flatten\u_reg.$procmux$2613: { $auto_6252 \u_reg.addr_hit [6] }
+ New ctrl vector for $pmux cell $flatten\u_reg.$procmux$2628: { \u_reg.addr_hit [4] \u_reg.addr_hit [6] \u_reg.addr_hit [7] \u_reg.addr_hit [17] $auto_6254 \u_reg.addr_hit [25] \u_reg.addr_hit [26] }
+ Optimizing cells in module \hmac.
+Performed a total of 7 changes.
+
+3.157. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+
+Removed a total of 1 cells.
+
+3.158. Executing OPT_SHARE pass.
+ Found cells that share an operand and can be merged by moving the $pmux $flatten\u_hmac.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:123$1235 in front of them:
+ $flatten\u_hmac.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:0$1233
+ $flatten\u_hmac.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:0$1227
+
+3.159. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=81, #solve=0, #remove=0, time=0.44 sec.]
+
+3.160. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 0 unused cells and 3 unused wires.
+
+
+3.161. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.162. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.163. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+ New ctrl vector for $pmux cell $flatten\u_hmac.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:123$1235: { $auto_6259 $flatten\u_hmac.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:123$1234_Y }
+ Optimizing cells in module \hmac.
+Performed a total of 1 changes.
+
+3.164. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.165. Executing OPT_SHARE pass.
+
+3.166. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=81, #solve=0, #remove=0, time=0.42 sec.]
+
+3.167. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.168. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.169. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.170. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.171. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.172. Executing OPT_SHARE pass.
+
+3.173. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=81, #solve=0, #remove=0, time=0.41 sec.]
+
+3.174. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.175. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+RUN-OPT ITERATIONS DONE : 3
+
+3.176. Executing PMUXTREE pass.
+
+3.177. Executing MUXPACK pass ($mux cell cascades to $pmux).
+Converting hmac.$auto_6650 ... hmac.$auto_6652 to a pmux with 2 cases.
+Converting hmac.$auto_6638 ... hmac.$auto_6640 to a pmux with 2 cases.
+Converting hmac.$auto_6628 ... hmac.$auto_6630 to a pmux with 2 cases.
+Converting hmac.$auto_6576 ... hmac.$auto_6578 to a pmux with 2 cases.
+Converting hmac.$auto_6496 ... hmac.$auto_6498 to a pmux with 2 cases.
+Converting hmac.$auto_6450 ... hmac.$auto_6452 to a pmux with 2 cases.
+Converting hmac.$auto_6438 ... hmac.$auto_6440 to a pmux with 2 cases.
+Converting hmac.$auto_6434 ... hmac.$auto_6436 to a pmux with 2 cases.
+Converting hmac.$auto_6422 ... hmac.$auto_6424 to a pmux with 2 cases.
+Converting hmac.$auto_6408 ... hmac.$auto_6410 to a pmux with 2 cases.
+Converting hmac.$auto_6404 ... hmac.$auto_6406 to a pmux with 2 cases.
+Converting hmac.$auto_6386 ... hmac.$auto_6388 to a pmux with 2 cases.
+Converting hmac.$auto_6370 ... hmac.$auto_6372 to a pmux with 2 cases.
+Converted 26 (p)mux cells into 13 pmux cells.
+
+
+3.178. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
+Mapping memory $flatten\u_reg.$auto_1966 in module \hmac:
+ created 4096 $dff cells and 0 static cells of width 1.
+ read interface: 0 $dff and 4095 $mux cells.
+ write interface: 0 write mux blocks.
+Memory $flatten\u_reg.$auto_1966 type : dissolved
+
+3.179. Executing TECHMAP pass (map to technology primitives).
+
+3.179.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/techmap.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/techmap.v' to AST representation.
+Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
+Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
+Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
+Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
+Generating RTLIL representation for module `\_90_simplemap_various'.
+Generating RTLIL representation for module `\_90_simplemap_registers'.
+Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
+Generating RTLIL representation for module `\_90_shift_shiftx'.
+Generating RTLIL representation for module `\_90_fa'.
+Generating RTLIL representation for module `\_90_lcu_brent_kung'.
+Generating RTLIL representation for module `\_90_alu'.
+Generating RTLIL representation for module `\_90_macc'.
+Generating RTLIL representation for module `\_90_alumacc'.
+Generating RTLIL representation for module `\$__div_mod_u'.
+Generating RTLIL representation for module `\$__div_mod_trunc'.
+Generating RTLIL representation for module `\_90_div'.
+Generating RTLIL representation for module `\_90_mod'.
+Generating RTLIL representation for module `\$__div_mod_floor'.
+Generating RTLIL representation for module `\_90_divfloor'.
+Generating RTLIL representation for module `\_90_modfloor'.
+Generating RTLIL representation for module `\_90_pow'.
+Generating RTLIL representation for module `\_90_pmux'.
+Generating RTLIL representation for module `\_90_demux'.
+Generating RTLIL representation for module `\_90_lut'.
+Successfully finished Verilog frontend.
+
+3.179.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v' to AST representation.
+Generating RTLIL representation for module `\_80_rs_alu'.
+Successfully finished Verilog frontend.
+
+3.179.3. Continuing TECHMAP pass.
+Using extmapper simplemap for cells of type $adffe.
+Using extmapper simplemap for cells of type $mux.
+Using extmapper simplemap for cells of type $adff.
+Using extmapper simplemap for cells of type $or.
+Using extmapper simplemap for cells of type $not.
+Using extmapper simplemap for cells of type $logic_not.
+Using extmapper simplemap for cells of type $logic_and.
+Using extmapper simplemap for cells of type $eq.
+Using extmapper simplemap for cells of type $and.
+Analyzing pattern of constant bits for this cell:
+ Constant input on bit 0 of port A: 1'1
+ Constant input on bit 1 of port A: 1'1
+ Constant input on bit 2 of port A: 1'1
+ Constant input on bit 3 of port A: 1'1
+ Constant input on bit 4 of port A: 1'1
+ Constant input on bit 5 of port A: 1'1
+ Constant input on bit 6 of port A: 1'1
+ Constant input on bit 7 of port A: 1'1
+Creating constmapped module `$paramod$constmap:5804069588edb7ff25baa001bebacc87928895c1$paramod$f510a8f4abd4276a0075f18cd429675e9cfe270f\_90_shift_shiftx'.
+
+3.179.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module $paramod$constmap:5804069588edb7ff25baa001bebacc87928895c1$paramod$f510a8f4abd4276a0075f18cd429675e9cfe270f\_90_shift_shiftx..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+ dead port 2/2 on $mux $procmux$20529.
+ dead port 2/2 on $mux $procmux$20523.
+ dead port 2/2 on $mux $procmux$20517.
+ dead port 2/2 on $mux $procmux$20511.
+ dead port 2/2 on $mux $procmux$20505.
+ dead port 2/2 on $mux $procmux$20499.
+Removed 6 multiplexer ports.
+
+
+3.179.20. Executing OPT_EXPR pass (perform const folding).
+Optimizing module $paramod$constmap:5804069588edb7ff25baa001bebacc87928895c1$paramod$f510a8f4abd4276a0075f18cd429675e9cfe270f\_90_shift_shiftx.
+
+Removed 0 unused cells and 10 unused wires.
+Using extmapper simplemap for cells of type $ne.
+Using extmapper simplemap for cells of type $logic_or.
+Using extmapper simplemap for cells of type $reduce_or.
+Using extmapper simplemap for cells of type $reduce_and.
+Using extmapper simplemap for cells of type $xor.
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/pin_location_hmac.sdc b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/pin_location_hmac.sdc
new file mode 100644
index 00000000..e69de29b
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/file.lst b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/file.lst
new file mode 100644
index 00000000..7e19f8ad
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/file.lst
@@ -0,0 +1,57 @@
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_subreg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_util_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/pwrmgr_reg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/pwrmgr_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_ram_1p_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_mubi_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_cipher_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_alert_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_count_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/jtag_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/entropy_src_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/edn_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/top_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_ctrl_reg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_ctrl_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_phy_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_reg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/lc_ctrl_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/otp_ctrl_reg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/otp_ctrl_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/ast_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_core.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_reg_top.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_alert_sender.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_buf.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_diff_decode.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_fifo_sync.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_flop_2sync.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_generic_buf.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_generic_flop.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_generic_flop_2sync.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_intr_hw.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_packer.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_dec.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_enc.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_dec.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_enc.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_subreg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_subreg_ext.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/sha2.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/sha2_pad.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_adapter_reg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_adapter_sram.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_cmd_intg_chk.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_data_integ_dec.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_data_integ_enc.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_err.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_err_resp.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_fifo_sync.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_rsp_intg_gen.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_socket_1n.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/cell_sim_blackbox.v
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/file_elab.lst b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/file_elab.lst
new file mode 100644
index 00000000..64783fc2
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/file_elab.lst
@@ -0,0 +1,56 @@
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_subreg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_util_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/pwrmgr_reg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/pwrmgr_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_ram_1p_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_mubi_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_cipher_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_alert_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_count_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/jtag_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/entropy_src_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/edn_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/top_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_ctrl_reg_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_ctrl_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_phy_pkg.sv
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_reg_pkg.sv
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diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/file_map.lst b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/file_map.lst
new file mode 100644
index 00000000..a8981ef8
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/file_map.lst
@@ -0,0 +1,57 @@
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diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/cell_sim_blackbox.v b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/cell_sim_blackbox.v
new file mode 100644
index 00000000..242e89f9
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/cell_sim_blackbox.v
@@ -0,0 +1,1191 @@
+//
+// BOOT_CLOCK black box model
+// Internal BOOT_CLK connection
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module BOOT_CLOCK #(
+ parameter PERIOD = 25 // Clock period for simulation purposes (nS)
+ ) (
+ output reg O
+);
+endmodule
+`endcelldefine
+//
+// CARRY black box model
+// FLE carry logic
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module CARRY (
+ input logic P,
+ input logic G,
+ input logic CIN,
+ output logic O,
+ output logic COUT
+);
+endmodule
+`endcelldefine
+//
+// CLK_BUF black box model
+// Global clock buffer
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module CLK_BUF (
+ input logic I,
+ (* clkbuf_driver *)
+ output logic O
+);
+endmodule
+`endcelldefine
+//
+// DFFNRE black box model
+// Negedge D flipflop with async reset and enable
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module DFFNRE (
+ input logic D,
+ input logic R,
+ input logic E,
+ (* clkbuf_sink *)
+ input logic C,
+ output reg Q
+);
+endmodule
+`endcelldefine
+//
+// DFFRE black box model
+// Posedge D flipflop with async reset and enable
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module DFFRE (
+ input logic D,
+ input logic R,
+ input logic E,
+ (* clkbuf_sink *)
+ input logic C,
+ output reg Q
+);
+endmodule
+`endcelldefine
+//
+// DSP19X2 black box model
+// Paramatizable dual 10x9-bit multiplier accumulator
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module DSP19X2 #(
+ parameter DSP_MODE = "MULTIPLY_ACCUMULATE", // DSP arithmetic mode (MULTIPLY/MULTIPLY_ACCUMULATE)
+ parameter [9:0] COEFF1_0 = 10'h000, // Multiplier 1 10-bit A input coefficient 0
+ parameter [9:0] COEFF1_1 = 10'h000, // Multiplier 1 10-bit A input coefficient 1
+ parameter [9:0] COEFF1_2 = 10'h000, // Multiplier 1 10-bit A input coefficient 2
+ parameter [9:0] COEFF1_3 = 10'h000, // Multiplier 1 10-bit A input coefficient 3
+ parameter [9:0] COEFF2_0 = 10'h000, // Multiplier 2 10-bit A input coefficient 0
+ parameter [9:0] COEFF2_1 = 10'h000, // Multiplier 2 10-bit A input coefficient 1
+ parameter [9:0] COEFF2_2 = 10'h000, // Multiplier 2 10-bit A input coefficient 2
+ parameter [9:0] COEFF2_3 = 10'h000, // Multiplier 2 10-bit A input coefficient 3
+ parameter OUTPUT_REG_EN = "TRUE", // Enable output register (TRUE/FALSE)
+ parameter INPUT_REG_EN = "TRUE" // Enable input register (TRUE/FALSE)
+ ) (
+ input logic [9:0] A1,
+ input logic [8:0] B1,
+ output logic [18:0] Z1,
+ output logic [8:0] DLY_B1,
+ input logic [9:0] A2,
+ input logic [8:0] B2,
+ output logic [18:0] Z2,
+ output logic [8:0] DLY_B2,
+ (* clkbuf_sink *)
+ input logic CLK,
+ input logic RESET,
+ input logic [4:0] ACC_FIR,
+ input logic [2:0] FEEDBACK,
+ input logic LOAD_ACC,
+ input logic UNSIGNED_A,
+ input logic UNSIGNED_B,
+ input logic SATURATE,
+ input logic [4:0] SHIFT_RIGHT,
+ input logic ROUND,
+ input logic SUBTRACT
+);
+endmodule
+`endcelldefine
+//
+// DSP38 black box model
+// Paramatizable 20x18-bit multiplier accumulator
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module DSP38 #(
+ parameter DSP_MODE = "MULTIPLY_ACCUMULATE", // DSP arithmetic mode (MULTIPLY/MULTIPLY_ADD_SUB/MULTIPLY_ACCUMULATE)
+ parameter [19:0] COEFF_0 = 20'h00000, // 20-bit A input coefficient 0
+ parameter [19:0] COEFF_1 = 20'h00000, // 20-bit A input coefficient 1
+ parameter [19:0] COEFF_2 = 20'h00000, // 20-bit A input coefficient 2
+ parameter [19:0] COEFF_3 = 20'h00000, // 20-bit A input coefficient 3
+ parameter OUTPUT_REG_EN = "TRUE", // Enable output register (TRUE/FALSE)
+ parameter INPUT_REG_EN = "TRUE" // Enable input register (TRUE/FALSE)
+ ) (
+ input logic [19:0] A,
+ input logic [17:0] B,
+ input logic [5:0] ACC_FIR,
+ output logic [37:0] Z,
+ output reg [17:0] DLY_B,
+ (* clkbuf_sink *)
+ input logic CLK,
+ input logic RESET,
+ input logic [2:0] FEEDBACK,
+ input logic LOAD_ACC,
+ input logic SATURATE,
+ input logic [5:0] SHIFT_RIGHT,
+ input logic ROUND,
+ input logic SUBTRACT,
+ input logic UNSIGNED_A,
+ input logic UNSIGNED_B
+);
+endmodule
+`endcelldefine
+//
+// FCLK_BUF black box model
+// Clock buffer for routing logic signal to the global clock
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module FCLK_BUF (
+ input logic I,
+ output logic O
+);
+endmodule
+`endcelldefine
+//
+// FIFO18KX2 black box model
+// Dual 18Kb FIFO
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module FIFO18KX2 #(
+ parameter DATA_WRITE_WIDTH1 = 18, // FIFO data write width, FIFO 1 (9, 18)
+ parameter DATA_READ_WIDTH1 = 18, // FIFO data read width, FIFO 1 (9, 18)
+ parameter FIFO_TYPE1 = "SYNCHRONOUS", // Synchronous or Asynchronous data transfer, FIFO 1 (SYNCHRONOUS/ASYNCHRONOUS)
+ parameter [10:0] PROG_EMPTY_THRESH1 = 11'h004, // 11-bit Programmable empty depth, FIFO 1
+ parameter [10:0] PROG_FULL_THRESH1 = 11'h7fa, // 11-bit Programmable full depth, FIFO 1
+ parameter DATA_WRITE_WIDTH2 = 18, // FIFO data write width, FIFO 2 (9, 18)
+ parameter DATA_READ_WIDTH2 = 18, // FIFO data read width, FIFO 2 (9, 18)
+ parameter FIFO_TYPE2 = "SYNCHRONOUS", // Synchronous or Asynchronous data transfer, FIFO 2 (SYNCHRONOUS/ASYNCHRONOUS)
+ parameter [10:0] PROG_EMPTY_THRESH2 = 11'h004, // 11-bit Programmable empty depth, FIFO 2
+ parameter [10:0] PROG_FULL_THRESH2 = 11'h7fa // 11-bit Programmable full depth, FIFO 2
+ ) (
+ input logic RESET1,
+ (* clkbuf_sink *)
+ input logic WR_CLK1,
+ (* clkbuf_sink *)
+ input logic RD_CLK1,
+ input logic WR_EN1,
+ input logic RD_EN1,
+ input logic [DATA_WRITE_WIDTH1-1:0] WR_DATA1,
+ output logic [DATA_READ_WIDTH1-1:0] RD_DATA1,
+ output reg EMPTY1,
+ output reg FULL1,
+ output reg ALMOST_EMPTY1,
+ output reg ALMOST_FULL1,
+ output reg PROG_EMPTY1,
+ output reg PROG_FULL1,
+ output reg OVERFLOW1,
+ output reg UNDERFLOW1,
+ input logic RESET2,
+ (* clkbuf_sink *)
+ input logic WR_CLK2,
+ (* clkbuf_sink *)
+ input logic RD_CLK2,
+ input logic WR_EN2,
+ input logic RD_EN2,
+ input logic [DATA_WRITE_WIDTH2-1:0] WR_DATA2,
+ output logic [DATA_READ_WIDTH2-1:0] RD_DATA2,
+ output reg EMPTY2,
+ output reg FULL2,
+ output reg ALMOST_EMPTY2,
+ output reg ALMOST_FULL2,
+ output reg PROG_EMPTY2,
+ output reg PROG_FULL2,
+ output reg OVERFLOW2,
+ output reg UNDERFLOW2
+);
+endmodule
+`endcelldefine
+//
+// FIFO36K black box model
+// 36Kb FIFO
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module FIFO36K #(
+ parameter DATA_WRITE_WIDTH = 36, // FIFO data write width (9, 18, 36)
+ parameter DATA_READ_WIDTH = 36, // FIFO data read width (9, 18, 36)
+ parameter FIFO_TYPE = "SYNCHRONOUS", // Synchronous or Asynchronous data transfer (SYNCHRONOUS/ASYNCHRONOUS)
+ parameter [11:0] PROG_EMPTY_THRESH = 12'h004, // 12-bit Programmable empty depth
+ parameter [11:0] PROG_FULL_THRESH = 12'hffa // 12-bit Programmable full depth
+ ) (
+ input logic RESET,
+ (* clkbuf_sink *)
+ input logic WR_CLK,
+ (* clkbuf_sink *)
+ input logic RD_CLK,
+ input logic WR_EN,
+ input logic RD_EN,
+ input logic [DATA_WRITE_WIDTH-1:0] WR_DATA,
+ output logic [DATA_READ_WIDTH-1:0] RD_DATA,
+ output reg EMPTY,
+ output reg FULL,
+ output reg ALMOST_EMPTY,
+ output reg ALMOST_FULL,
+ output reg PROG_EMPTY,
+ output reg PROG_FULL,
+ output reg OVERFLOW,
+ output reg UNDERFLOW
+);
+endmodule
+`endcelldefine
+//
+// I_BUF_DS black box model
+// input differential buffer
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module I_BUF_DS #(
+ parameter WEAK_KEEPER = "NONE", // Specify Pull-up/Pull-down on input (NONE/PULLUP/PULLDOWN)
+ parameter IOSTANDARD = "DEFAULT", // IO Standard
+ parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
+ ) (
+ (* iopad_external_pin *)
+ input logic I_P,
+ (* iopad_external_pin *)
+ input logic I_N,
+ input logic EN,
+ output reg O
+);
+endmodule
+`endcelldefine
+//
+// I_BUF black box model
+// Input buffer
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module I_BUF #(
+ parameter WEAK_KEEPER = "NONE" // Specify Pull-up/Pull-down on input (NONE/PULLUP/PULLDOWN)
+, parameter IOSTANDARD = "DEFAULT" // IO Standard
+ ) (
+ (* iopad_external_pin *)
+ input logic I,
+ input logic EN,
+ output logic O
+);
+endmodule
+`endcelldefine
+//
+// I_DDR black box model
+// DDR input register
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module I_DDR (
+ input logic D,
+ input logic R,
+ input logic E,
+ (* clkbuf_sink *)
+ input logic C,
+ output reg [1:0] Q
+);
+endmodule
+`endcelldefine
+//
+// I_DELAY black box model
+// Input Delay
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module I_DELAY #(
+ parameter DELAY = 0 // TAP delay value (0-63)
+ ) (
+ input logic I,
+ input logic DLY_LOAD,
+ input logic DLY_ADJ,
+ input logic DLY_INCDEC,
+ output logic [5:0] DLY_TAP_VALUE,
+ (* clkbuf_sink *)
+ input logic CLK_IN,
+ output logic O
+);
+endmodule
+`endcelldefine
+//
+// I_FAB black box model
+// Marker Buffer for periphery to fabric transition
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module I_FAB (
+ input logic I,
+ output logic O
+);
+endmodule
+`endcelldefine
+//
+// I_SERDES black box model
+// Input Serial Deserializer
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module I_SERDES #(
+ parameter DATA_RATE = "SDR", // Single or double data rate (SDR/DDR)
+ parameter WIDTH = 4, // Width of Deserialization (3-10)
+ parameter DPA_MODE = "NONE" // Select Dynamic Phase Alignment or Clock Data Recovery (NONE/DPA/CDR)
+ ) (
+ input logic D,
+ input logic RST,
+ input logic BITSLIP_ADJ,
+ input logic EN,
+ (* clkbuf_sink *)
+ input logic CLK_IN,
+ output logic CLK_OUT,
+ output logic [WIDTH-1:0] Q,
+ output logic DATA_VALID,
+ output logic DPA_LOCK,
+ output logic DPA_ERROR,
+ input logic PLL_LOCK,
+ input logic PLL_CLK
+);
+endmodule
+`endcelldefine
+//
+// LATCHNR black box model
+// Negative level-sensitive latch with active-high asyncronous reset
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module LATCHNR (
+ input logic D,
+ input logic G,
+ input logic R,
+ output logic Q
+);
+endmodule
+`endcelldefine
+//
+// LATCHNS black box model
+// Negative level-sensitive latch with active-high asyncronous set
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module LATCHNS (
+ input logic D,
+ input logic G,
+ input logic R,
+ output logic Q
+);
+endmodule
+`endcelldefine
+//
+// LATCHN black box model
+// Negative level-sensitive latch
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module LATCHN (
+ input logic D,
+ input logic G,
+ output logic Q
+);
+endmodule
+`endcelldefine
+//
+// LATCHR black box model
+// Positive level-sensitive latch with active-high asyncronous reset
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module LATCHR (
+ input logic D,
+ input logic G,
+ input logic R,
+ output logic Q
+);
+endmodule
+`endcelldefine
+//
+// LATCHS black box model
+// Positive level-sensitive latch with active-high asyncronous set
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module LATCHS (
+ input logic D,
+ input logic G,
+ input logic R,
+ output logic Q
+);
+endmodule
+`endcelldefine
+//
+// LATCH black box model
+// Positive level-sensitive latch
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module LATCH (
+ input logic D,
+ input logic G,
+ output logic Q
+);
+endmodule
+`endcelldefine
+//
+// LUT1 black box model
+// 1-input lookup table (LUT)
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module LUT1 #(
+ parameter [1:0] INIT_VALUE = 2'h0 // 2-bit LUT logic value
+ ) (
+ input logic A,
+ output logic Y
+);
+endmodule
+`endcelldefine
+//
+// LUT2 black box model
+// 2-input lookup table (LUT)
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module LUT2 #(
+ parameter [3:0] INIT_VALUE = 4'h0 // 4-bit LUT logic value
+ ) (
+ input logic [1:0] A,
+ output logic Y
+);
+endmodule
+`endcelldefine
+//
+// LUT3 black box model
+// 3-input lookup table (LUT)
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module LUT3 #(
+ parameter [7:0] INIT_VALUE = 8'h00 // 8-bit LUT logic value
+ ) (
+ input logic [2:0] A,
+ output logic Y
+);
+endmodule
+`endcelldefine
+//
+// LUT4 black box model
+// 4-input lookup table (LUT)
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module LUT4 #(
+ parameter [15:0] INIT_VALUE = 16'h0000 // 16-bit LUT logic value
+ ) (
+ input logic [3:0] A,
+ output logic Y
+);
+endmodule
+`endcelldefine
+//
+// LUT5 black box model
+// 5-input lookup table (LUT)
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module LUT5 #(
+ parameter [31:0] INIT_VALUE = 32'h00000000 // LUT logic value
+ ) (
+ input logic [4:0] A,
+ output logic Y
+);
+endmodule
+`endcelldefine
+//
+// LUT6 black box model
+// 6-input lookup table (LUT)
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module LUT6 #(
+ parameter [63:0] INIT_VALUE = 64'h0000000000000000 // 64-bit LUT logic value
+ ) (
+ input logic [5:0] A,
+ output logic Y
+);
+endmodule
+`endcelldefine
+//
+// MIPI_RX black box model
+// MIPI Receiver
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module MIPI_RX #(
+ parameter WIDTH = 4, // Width of input data to serializer (3-10)
+ parameter EN_IDLY = "FALSE", // True or False
+ parameter DELAY = 0 // Fixed TAP delay value (0-63)
+ ) (
+ input logic RST,
+ input logic RX_CLK,
+ input logic PLL_LOCK,
+ (* clkbuf_sink *)
+ input logic CLK_IN,
+ input logic RX_DP,
+ input logic RX_DN,
+ input logic HS_EN,
+ input logic LP_EN,
+ input logic RX_TERM_EN,
+ input logic BITSLIP_ADJ,
+ input logic DLY_LOAD,
+ input logic DLY_ADJ,
+ input logic DLY_INCDEC,
+ output logic [5:0] DLY_TAP_VALUE,
+ output logic [WIDTH-1:0] HS_RX_DATA,
+ output logic HS_RXD_VALID,
+ output logic RX_OE,
+ output logic LP_RX_DP,
+ output logic LP_RX_DN
+);
+endmodule
+`endcelldefine
+//
+// MIPI_TX black box model
+// MIPI Transmitter
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module MIPI_TX #(
+ parameter WIDTH = 4, // Width of input data to serializer (3-10)
+ parameter EN_ODLY = "FALSE", // True or False
+ parameter LANE_MODE = "Master", // Master or Slave
+ parameter DELAY = 0 // Fixed TAP delay value (0-63)
+ ) (
+ input logic RST,
+ input logic RX_CLK,
+ input logic PLL_LOCK,
+ (* clkbuf_sink *)
+ input logic CLK_IN,
+ input logic [WIDTH-1:0] HS_TX_DATA,
+ input logic HS_TXD_VALID,
+ input logic HS_EN,
+ input logic TX_LP_DP,
+ input logic TX_LP_DN,
+ input logic LP_EN,
+ input logic TX_ODT_EN,
+ input logic DLY_LOAD,
+ input logic DLY_ADJ,
+ input logic DLY_INCDEC,
+ output logic TX_OE,
+ output logic TX_DP,
+ output logic TX_DN,
+ input logic CHANNEL_BOND_SYNC_IN,
+ output logic CHANNEL_BOND_SYNC_OUT
+);
+endmodule
+`endcelldefine
+//
+// O_BUF_DS black box model
+// Output differential buffer
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module O_BUF_DS
+ #(
+ parameter IOSTANDARD = "DEFAULT", // IO Standard
+ parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
+ )
+ (
+ input logic I,
+ (* iopad_external_pin *)
+ output logic O_P,
+ (* iopad_external_pin *)
+ output logic O_N
+);
+endmodule
+`endcelldefine
+//
+// O_BUFT_DS black box model
+// Output differential tri-state buffer
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module O_BUFT_DS #(
+ parameter WEAK_KEEPER = "NONE" // Enable pull-up/pull-down on output (NONE/PULLUP/PULLDOWN)
+, parameter IOSTANDARD = "DEFAULT", // IO Standard
+ parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination
+ ) (
+ input logic I,
+ input logic T,
+ (* iopad_external_pin *)
+ output logic O_P,
+ (* iopad_external_pin *)
+ output logic O_N
+);
+endmodule
+`endcelldefine
+//
+// O_BUFT black box model
+// Output tri-state buffer
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module O_BUFT #(
+ parameter WEAK_KEEPER = "NONE" // Enable pull-up/pull-down on output (NONE/PULLUP/PULLDOWN)
+, parameter IOSTANDARD = "DEFAULT", // IO Standard
+ parameter DRIVE_STRENGTH = 2, // Drive strength in mA for LVCMOS standards
+ parameter SLEW_RATE = "SLOW" // Transition rate for LVCMOS standards
+ ) (
+ input logic I,
+ input logic T,
+ (* iopad_external_pin *)
+ output logic O
+);
+endmodule
+`endcelldefine
+//
+// O_BUF black box model
+// Output buffer
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module O_BUF
+ #(
+ parameter IOSTANDARD = "DEFAULT", // IO Standard
+ parameter DRIVE_STRENGTH = 2, // Drive strength in mA for LVCMOS standards
+ parameter SLEW_RATE = "SLOW" // Transition rate for LVCMOS standards
+ )
+ (
+ input logic I,
+ (* iopad_external_pin *)
+ output logic O
+);
+endmodule
+`endcelldefine
+//
+// O_DDR black box model
+// DDR output register
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module O_DDR (
+ input logic [1:0] D,
+ input logic R,
+ input logic E,
+ (* clkbuf_sink *)
+ input logic C,
+ output reg Q
+);
+endmodule
+`endcelldefine
+//
+// O_DELAY black box model
+// Serdes output
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module O_DELAY #(
+ parameter DELAY = 0 // TAP delay value (0-63)
+ ) (
+ input logic I,
+ input logic DLY_LOAD,
+ input logic DLY_ADJ,
+ input logic DLY_INCDEC,
+ output logic [5:0] DLY_TAP_VALUE,
+ (* clkbuf_sink *)
+ input logic CLK_IN,
+ output logic O
+);
+endmodule
+`endcelldefine
+//
+// O_FAB black box model
+// Marker Buffer for fabric to periphery transition
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module O_FAB (
+ input logic I,
+ output logic O
+);
+endmodule
+`endcelldefine
+//
+// O_SERDES_CLK black box model
+// Output Serializer Clock
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module O_SERDES_CLK #(
+ parameter DATA_RATE = "SDR", // Single or double data rate (SDR/DDR)
+ parameter CLOCK_PHASE = 0 // Clock phase (0,90,180,270)
+ ) (
+ input logic CLK_EN,
+ output reg OUTPUT_CLK,
+ input logic PLL_LOCK,
+ input logic PLL_CLK
+);
+endmodule
+`endcelldefine
+//
+// O_SERDES black box model
+// Output Serializer
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module O_SERDES #(
+ parameter DATA_RATE = "SDR", // Single or double data rate (SDR/DDR)
+ parameter WIDTH = 4 // Width of input data to serializer (3-10)
+ ) (
+ input logic [WIDTH-1:0] D,
+ input logic RST,
+ input logic DATA_VALID,
+ (* clkbuf_sink *)
+ input logic CLK_IN,
+ input logic OE_IN,
+ output logic OE_OUT,
+ output logic Q,
+ input logic CHANNEL_BOND_SYNC_IN,
+ output logic CHANNEL_BOND_SYNC_OUT,
+ input logic PLL_LOCK,
+ input logic PLL_CLK
+);
+endmodule
+`endcelldefine
+//
+// PLL black box model
+// Phase locked loop
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module PLL #(
+ parameter DEV_FAMILY = "VIRGO", // Device Family
+ parameter DIVIDE_CLK_IN_BY_2 = "FALSE", // Enable input divider (TRUE/FALSE)
+ parameter PLL_MULT = 16, // VCO clock multiplier value (16-640)
+ parameter PLL_DIV = 1, // VCO clock divider value (1-63)
+ parameter PLL_MULT_FRAC = 0, // Fraction mode not supported
+ parameter PLL_POST_DIV = 17 // VCO clock post-divider value (17,18,19,20,21,22,23,34,35,36,37,38,39,51,52,53,54,55,68,69,70,71,85,86,87,102,103,119)
+ ) (
+ input logic PLL_EN,
+ (* clkbuf_sink *)
+ input logic CLK_IN,
+ output logic CLK_OUT,
+ output logic CLK_OUT_DIV2,
+ output logic CLK_OUT_DIV3,
+ output logic CLK_OUT_DIV4,
+ output logic FAST_CLK,
+ output logic LOCK
+);
+endmodule
+`endcelldefine
+//
+// SOC_FPGA_INTF_AHB_M black box model
+// SOC interface connection AHB Master
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module SOC_FPGA_INTF_AHB_M (
+ input logic HRESETN_I,
+ input logic [31:0] HADDR,
+ input logic [2:0] HBURST,
+ input logic [3:0] HPROT,
+ input logic [2:0] HSIZE,
+ input logic [2:0] HTRANS,
+ input logic [31:0] HWDATA,
+ input logic HWWRITE,
+ output logic [31:0] HRDATA,
+ output logic HREADY,
+ output logic HRESP,
+ input logic HCLK
+);
+endmodule
+`endcelldefine
+//
+// SOC_FPGA_INTF_AHB_S black box model
+// SOC interface connection AHB Slave
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module SOC_FPGA_INTF_AHB_S (
+ output logic HRESETN_I,
+ output logic [31:0] HADDR,
+ output logic [2:0] HBURST,
+ output logic HMASTLOCK,
+ input logic HREADY,
+ output logic [3:0] HPROT,
+ input logic [31:0] HRDATA,
+ input logic HRESP,
+ output logic HSEL,
+ output logic [2:0] HSIZE,
+ output logic [1:0] HTRANS,
+ output logic [3:0] HWBE,
+ output logic [31:0] HWDATA,
+ output logic HWRITE,
+ input logic HCLK
+);
+endmodule
+`endcelldefine
+//
+// SOC_FPGA_INTF_AXI_M0 black box model
+// SOC interface connection AXI Master 0
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module SOC_FPGA_INTF_AXI_M0 (
+ input logic [31:0] M0_ARADDR,
+ input logic [1:0] M0_ARBURST,
+ input logic [3:0] M0_ARCACHE,
+ input logic [3:0] M0_ARID,
+ input logic [2:0] M0_ARLEN,
+ input logic M0_ARLOCK,
+ input logic [2:0] M0_ARPROT,
+ output logic M0_ARREADY,
+ input logic [2:0] M0_ARSIZE,
+ input logic M0_ARVALID,
+ input logic [31:0] M0_AWADDR,
+ input logic [1:0] M0_AWBURST,
+ input logic [3:0] M0_AWCACHE,
+ input logic [3:0] M0_AWID,
+ input logic [2:0] M0_AWLEN,
+ input logic M0_AWLOCK,
+ input logic [2:0] M0_AWPROT,
+ output logic M0_AWREADY,
+ input logic [2:0] M0_AWSIZE,
+ input logic M0_AWVALID,
+ output logic [3:0] M0_BID,
+ input logic M0_BREADY,
+ output logic [1:0] M0_BRESP,
+ output logic M0_BVALID,
+ output logic [63:0] M0_RDATA,
+ output logic [3:0] M0_RID,
+ output logic M0_RLAST,
+ input logic M0_RREADY,
+ output logic [1:0] M0_RRESP,
+ output logic M0_RVALID,
+ input logic [63:0] M0_WDATA,
+ input logic M0_WLAST,
+ output logic M0_WREADY,
+ input logic [7:0] M0_WSTRB,
+ input logic M0_WVALID,
+ input logic M0_ACLK,
+ output logic M0_ARESETN_I
+);
+endmodule
+`endcelldefine
+//
+// SOC_FPGA_INTF_AXI_M1 black box model
+// SOC interface connection AXI Master 1
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module SOC_FPGA_INTF_AXI_M1 (
+ input logic [31:0] M1_ARADDR,
+ input logic [1:0] M1_ARBURST,
+ input logic [3:0] M1_ARCACHE,
+ input logic [3:0] M1_ARID,
+ input logic [2:0] M1_ARLEN,
+ input logic M1_ARLOCK,
+ input logic [2:0] M1_ARPROT,
+ output logic M1_ARREADY,
+ input logic [2:0] M1_ARSIZE,
+ input logic M1_ARVALID,
+ input logic [31:0] M1_AWADDR,
+ input logic [1:0] M1_AWBURST,
+ input logic [3:0] M1_AWCACHE,
+ input logic [3:0] M1_AWID,
+ input logic [2:0] M1_AWLEN,
+ input logic M1_AWLOCK,
+ input logic [2:0] M1_AWPROT,
+ output logic M1_AWREADY,
+ input logic [2:0] M1_AWSIZE,
+ input logic M1_AWVALID,
+ output logic [3:0] M1_BID,
+ input logic M1_BREADY,
+ output logic [1:0] M1_BRESP,
+ output logic M1_BVALID,
+ output logic [63:0] M1_RDATA,
+ output logic [3:0] M1_RID,
+ output logic M1_RLAST,
+ input logic M1_RREADY,
+ output logic [1:0] M1_RRESP,
+ output logic M1_RVALID,
+ input logic [63:0] M1_WDATA,
+ input logic M1_WLAST,
+ output logic M1_WREADY,
+ input logic [7:0] M1_WSTRB,
+ input logic M1_WVALID,
+ input logic M1_ACLK,
+ output logic M1_ARESETN_I
+);
+endmodule
+`endcelldefine
+//
+// SOC_FPGA_INTF_DMA black box model
+// SOC DMA interface
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module SOC_FPGA_INTF_DMA (
+ input logic [3:0] DMA_REQ,
+ output logic [3:0] DMA_ACK,
+ input logic DMA_CLK,
+ input logic DMA_RST_N
+);
+endmodule
+`endcelldefine
+//
+// SOC_FPGA_INTF_IRQ black box model
+// SOC Interupt connection
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module SOC_FPGA_INTF_IRQ (
+ input logic [15:0] IRQ_SRC,
+ output logic [15:0] IRQ_SET,
+ input logic IRQ_CLK,
+ input logic IRQ_RST_N
+);
+endmodule
+`endcelldefine
+//
+// SOC_FPGA_INTF_JTAG black box model
+// SOC JTAG connection
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module SOC_FPGA_INTF_JTAG (
+ input logic BOOT_JTAG_TCK,
+ output reg BOOT_JTAG_TDI,
+ input logic BOOT_JTAG_TDO,
+ output reg BOOT_JTAG_TMS,
+ output reg BOOT_JTAG_TRSTN,
+ input logic BOOT_JTAG_EN
+);
+endmodule
+`endcelldefine
+//
+// SOC_FPGA_TEMPERATURE black box model
+// SOC Temperature Interface
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module SOC_FPGA_TEMPERATURE #(
+ parameter INITIAL_TEMPERATURE = 25, // Specify initial temperature for simulation (0-125)
+ parameter TEMPERATURE_FILE = "" // Specify ASCII file containing temperature values over time
+ ) (
+ output reg [7:0] TEMPERATURE,
+ output reg VALID,
+ output reg ERROR
+);
+endmodule
+`endcelldefine
+//
+// TDP_RAM18KX2 black box model
+// Dual 18Kb True-dual-port RAM
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module TDP_RAM18KX2 #(
+ parameter [16383:0] INIT1 = {16384{1'b0}}, // Initial Contents of data memory, RAM 1
+ parameter [2047:0] INIT1_PARITY = {2048{1'b0}}, // Initial Contents of parity memory, RAM 1
+ parameter WRITE_WIDTH_A1 = 18, // Write data width on port A, RAM 1 (1, 2, 4, 9, 18)
+ parameter WRITE_WIDTH_B1 = 18, // Write data width on port B, RAM 1 (1, 2, 4, 9, 18)
+ parameter READ_WIDTH_A1 = 18, // Read data width on port A, RAM 1 (1, 2, 4, 9, 18)
+ parameter READ_WIDTH_B1 = 18, // Read data width on port B, RAM 1 (1, 2, 4, 9, 18)
+ parameter [16383:0] INIT2 = {16384{1'b0}}, // Initial Contents of memory, RAM 2
+ parameter [2047:0] INIT2_PARITY = {2048{1'b0}}, // Initial Contents of memory, RAM 2
+ parameter WRITE_WIDTH_A2 = 18, // Write data width on port A, RAM 2 (1, 2, 4, 9, 18)
+ parameter WRITE_WIDTH_B2 = 18, // Write data width on port B, RAM 2 (1, 2, 4, 9, 18)
+ parameter READ_WIDTH_A2 = 18, // Read data width on port A, RAM 2 (1, 2, 4, 9, 18)
+ parameter READ_WIDTH_B2 = 18 // Read data width on port B, RAM 2 (1, 2, 4, 9, 18)
+ ) (
+ input logic WEN_A1,
+ input logic WEN_B1,
+ input logic REN_A1,
+ input logic REN_B1,
+ (* clkbuf_sink *)
+ input logic CLK_A1,
+ (* clkbuf_sink *)
+ input logic CLK_B1,
+ input logic [1:0] BE_A1,
+ input logic [1:0] BE_B1,
+ input logic [13:0] ADDR_A1,
+ input logic [13:0] ADDR_B1,
+ input logic [15:0] WDATA_A1,
+ input logic [1:0] WPARITY_A1,
+ input logic [15:0] WDATA_B1,
+ input logic [1:0] WPARITY_B1,
+ output reg [15:0] RDATA_A1,
+ output reg [1:0] RPARITY_A1,
+ output reg [15:0] RDATA_B1,
+ output reg [1:0] RPARITY_B1,
+ input logic WEN_A2,
+ input logic WEN_B2,
+ input logic REN_A2,
+ input logic REN_B2,
+ (* clkbuf_sink *)
+ input logic CLK_A2,
+ (* clkbuf_sink *)
+ input logic CLK_B2,
+ input logic [1:0] BE_A2,
+ input logic [1:0] BE_B2,
+ input logic [13:0] ADDR_A2,
+ input logic [13:0] ADDR_B2,
+ input logic [15:0] WDATA_A2,
+ input logic [1:0] WPARITY_A2,
+ input logic [15:0] WDATA_B2,
+ input logic [1:0] WPARITY_B2,
+ output reg [15:0] RDATA_A2,
+ output reg [1:0] RPARITY_A2,
+ output reg [15:0] RDATA_B2,
+ output reg [1:0] RPARITY_B2
+);
+endmodule
+`endcelldefine
+//
+// TDP_RAM36K black box model
+// 36Kb True-dual-port RAM
+//
+// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
+//
+`celldefine
+(* blackbox *)
+module TDP_RAM36K #(
+ parameter [32767:0] INIT = {32768{1'b0}}, // Initial Contents of memory
+ parameter [4095:0] INIT_PARITY = {4096{1'b0}}, // Initial Contents of memory
+ parameter WRITE_WIDTH_A = 36, // Write data width on port A (1, 2, 4, 9, 18, 36)
+ parameter READ_WIDTH_A = WRITE_WIDTH_A, // Read data width on port A (1, 2, 4, 9, 18, 36)
+ parameter WRITE_WIDTH_B = WRITE_WIDTH_A, // Write data width on port B (1, 2, 4, 9, 18, 36)
+ parameter READ_WIDTH_B = READ_WIDTH_A // Read data width on port B (1, 2, 4, 9, 18, 36)
+ ) (
+ input logic WEN_A,
+ input logic WEN_B,
+ input logic REN_A,
+ input logic REN_B,
+ (* clkbuf_sink *)
+ input logic CLK_A,
+ (* clkbuf_sink *)
+ input logic CLK_B,
+ input logic [3:0] BE_A,
+ input logic [3:0] BE_B,
+ input logic [14:0] ADDR_A,
+ input logic [14:0] ADDR_B,
+ input logic [31:0] WDATA_A,
+ input logic [3:0] WPARITY_A,
+ input logic [31:0] WDATA_B,
+ input logic [3:0] WPARITY_B,
+ output reg [31:0] RDATA_A,
+ output reg [3:0] RPARITY_A,
+ output reg [31:0] RDATA_B,
+ output reg [3:0] RPARITY_B
+);
+endmodule
+`endcelldefine
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/ast_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/ast_pkg.sv
new file mode 100644
index 00000000..080a0f21
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/ast_pkg.sv
@@ -0,0 +1,165 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//############################################################################
+// *Name: ast_pkg
+// *Module Description: AST Package
+//############################################################################
+
+
+
+
+package ast_pkg;
+
+// Alerts
+parameter int unsigned NumAlerts = 13;
+parameter int unsigned NumIoRails = 2;
+parameter int unsigned AsSel = 0;
+parameter int unsigned CgSel = 1;
+parameter int unsigned GdSel = 2;
+parameter int unsigned TsHiSel = 3;
+parameter int unsigned TsLoSel = 4;
+parameter int unsigned FlaSel = 5;
+parameter int unsigned OtpSel = 6;
+parameter int unsigned Ot0Sel = 7;
+parameter int unsigned Ot1Sel = 8;
+parameter int unsigned Ot2Sel = 9;
+parameter int unsigned Ot3Sel = 10;
+parameter int unsigned Ot4Sel = 11;
+parameter int unsigned Ot5Sel = 12;
+//
+parameter int unsigned Lc2HcTrCyc = 104; // (100+4)x5 = 520 us
+parameter int unsigned Hc2LcTrCyc = 40; // (36+4)x5 = 200 us
+//
+parameter int unsigned EntropyStreams = 4;
+parameter int unsigned AdcChannels = 2;
+parameter int unsigned AdcDataWidth = 10;
+parameter int unsigned UsbCalibWidth = 20;
+parameter int unsigned Ast2PadOutWidth = 9;
+parameter int unsigned Pad2AstInWidth = 9;
+
+// These LFSR parameters have been generated with
+// $ ./util/design/gen-lfsr-seed.py --width 64 --seed 691876113 --prefix ""
+parameter int LfsrWidth = 64;
+typedef logic [LfsrWidth-1:0] lfsr_seed_t;
+typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
+parameter lfsr_seed_t RndCnstLfsrSeedDefault = 64'h22d326255bd24320;
+parameter lfsr_perm_t RndCnstLfsrPermDefault = {
+ 128'h16108c9f9008aa37e5118d1ec1df64a7,
+ 256'h24f3f1b73537f42d38383ee8f897286df81d49ab54b6bbbb666cbd1a16c41252
+};
+
+// Memories Read-Write Margin Interface
+typedef struct packed {
+ logic marg_en_a;
+ logic [4-1:0] marg_a;
+ logic marg_en_b;
+ logic [4-1:0] marg_b;
+} dpm_rm_t;
+
+typedef struct packed {
+ logic marg_en;
+ logic [4-1:0] marg;
+} spm_rm_t;
+
+// ADC Interface
+typedef struct packed {
+ logic [AdcChannels-1:0] channel_sel;
+ logic pd;
+} adc_ast_req_t;
+
+typedef struct packed {
+ logic [AdcDataWidth-1:0] data;
+ logic data_valid;
+} adc_ast_rsp_t;
+
+// Analog Signal
+
+
+
+typedef logic awire_t;
+
+
+// Clock & Resets Interface
+typedef struct packed {
+ logic clk_sys;
+ logic clk_io;
+ logic clk_usb;
+ logic clk_aon;
+} ast_clks_t;
+
+typedef struct packed {
+ logic aon_pok;
+} ast_rst_t;
+
+parameter ast_rst_t AST_RST_DEFAULT = '{
+ aon_pok: 1'b1
+};
+
+typedef struct packed {
+ logic [NumIoRails-1:0] io_pok;
+} ast_status_t;
+
+typedef struct packed {
+ logic aon_pok;
+ logic vcc_pok;
+ logic main_pok;
+ logic [NumIoRails-1:0] io_pok;
+} ast_pwst_t;
+
+// Alerts Interface
+typedef struct packed {
+ logic p;
+ logic n;
+} ast_dif_t;
+
+typedef struct packed {
+ ast_dif_t [NumAlerts-1:0] alerts;
+} ast_alert_req_t;
+
+typedef struct packed {
+ ast_dif_t [NumAlerts-1:0] alerts_ack;
+ ast_dif_t [NumAlerts-1:0] alerts_trig;
+} ast_alert_rsp_t;
+
+// Ack mode enumerations
+typedef enum logic {
+ ImmAck = 0,
+ SwAck = 1
+} ast_ack_mode_e;
+
+// Clocks Oschillator Bypass
+typedef struct packed {
+ logic usb;
+ logic sys;
+ logic io;
+ logic aon;
+} clks_osc_byp_t;
+
+typedef enum logic [4-1:0] {
+ ObsNon = 4'h0, // No module observed (disable)
+ ObsAst = 4'h1, // Observe AST
+ ObsFla = 4'h2, // Observe FLASH
+ ObsOtp = 4'h3, // Observe OTP
+ ObsOt0 = 4'h4, // Observe OT0
+ ObsOt1 = 4'h5, // Observe OT1
+ ObsOt2 = 4'h6, // Observe OT2
+ ObsOt3 = 4'h7, // Observe OT3
+ ObsRs0 = 4'h8, // RESERVED
+ ObsRs1 = 4'h9, // RESERVED
+ ObsRs2 = 4'hA, // RESERVED
+ ObsRs3 = 4'hB, // RESERVED
+ ObsRs4 = 4'hC, // RESERVED
+ ObsRs5 = 4'hD, // RESERVED
+ ObsRs6 = 4'hE, // RESERVED
+ ObsRs7 = 4'hF // RESERVED
+} ast_omdl_e;
+
+typedef struct packed {
+ logic [4-1:0] obgsl;
+ ast_omdl_e obmsl;
+ prim_mubi_pkg::mubi4_t obmen;
+} ast_obs_ctrl_t;
+
+endpackage // of ast_pkg
+
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/edn_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/edn_pkg.sv
new file mode 100644
index 00000000..b156b0a3
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/edn_pkg.sv
@@ -0,0 +1,35 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+//`include "entropy_src_pkg.sv"
+package edn_pkg;
+ ///////////////////////////
+ // Peripheral Interfaces //
+ ///////////////////////////
+
+ parameter int unsigned ENDPOINT_BUS_WIDTH = 32;
+ parameter int unsigned FIPS_ENDPOINT_BUS_WIDTH = entropy_src_pkg::FIPS_BUS_WIDTH +
+ ENDPOINT_BUS_WIDTH;
+
+ // EDN request interface
+ typedef struct packed {
+ logic edn_req;
+ } edn_req_t;
+ typedef struct packed {
+ logic edn_ack;
+ logic edn_fips;
+ logic [ENDPOINT_BUS_WIDTH-1:0] edn_bus;
+ } edn_rsp_t;
+
+ parameter edn_req_t EDN_REQ_DEFAULT = '0;
+ parameter edn_rsp_t EDN_RSP_DEFAULT = '0;
+
+ // Sparse four-value signal type
+ parameter int EDN_MODE_WIDTH = 4;
+ typedef enum logic [EDN_MODE_WIDTH-1:0] {
+ EDN_FIELD_ON = 4'b1010
+ } edn_enb_e;
+
+endpackage : edn_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/entropy_src_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/entropy_src_pkg.sv
new file mode 100644
index 00000000..69cc8425
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/entropy_src_pkg.sv
@@ -0,0 +1,66 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+
+package entropy_src_pkg;
+
+ //-------------------------
+ // Entropy Interface
+ //-------------------------
+
+ parameter int RNG_BUS_WIDTH = 4;
+ parameter int CSRNG_BUS_WIDTH = 384;
+ parameter int FIPS_BUS_WIDTH = 1;
+
+ // es entropy i/f
+ typedef struct packed {
+ logic es_ack;
+ logic [CSRNG_BUS_WIDTH-1:0] es_bits;
+ logic [FIPS_BUS_WIDTH-1:0] es_fips;
+ } entropy_src_hw_if_rsp_t;
+
+ typedef struct packed {
+ logic es_req;
+ } entropy_src_hw_if_req_t;
+
+ parameter entropy_src_hw_if_req_t ENTROPY_SRC_HW_IF_REQ_DEFAULT = '{default: '0};
+ parameter entropy_src_hw_if_rsp_t ENTROPY_SRC_HW_IF_RSP_DEFAULT = '{default: '0};
+
+
+ // ast rng i/f
+ typedef struct packed {
+ logic rng_enable;
+ } entropy_src_rng_req_t;
+
+ typedef struct packed {
+ logic rng_valid;
+ logic [RNG_BUS_WIDTH-1:0] rng_b;
+ } entropy_src_rng_rsp_t;
+
+ parameter entropy_src_rng_req_t ENTROPY_SRC_RNG_REQ_DEFAULT = '{default: '0};
+ parameter entropy_src_rng_rsp_t ENTROPY_SRC_RNG_RSP_DEFAULT = '{default: '0};
+
+ // external health test i/f
+ typedef struct packed {
+ logic [RNG_BUS_WIDTH-1:0] entropy_bit;
+ logic entropy_bit_valid;
+ logic clear;
+ logic active;
+ logic [15:0] thresh_hi;
+ logic [15:0] thresh_lo;
+ logic [15:0] window;
+ } entropy_src_xht_req_t;
+
+ typedef struct packed {
+ logic[15:0] test_cnt;
+ logic test_fail_hi_pulse;
+ logic test_fail_lo_pulse;
+ } entropy_src_xht_rsp_t;
+
+ parameter entropy_src_xht_req_t ENTROPY_SRC_XHT_REQ_DEFAULT = '{default: '0};
+ parameter entropy_src_xht_rsp_t ENTROPY_SRC_XHT_RSP_DEFAULT = '{default: '0};
+
+
+endpackage : entropy_src_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_ctrl_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_ctrl_pkg.sv
new file mode 100644
index 00000000..bd07ee4d
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_ctrl_pkg.sv
@@ -0,0 +1,597 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Flash Controller module.
+//
+
+package flash_ctrl_pkg;
+
+ // design parameters that can be altered through topgen
+ parameter int unsigned NumBanks = flash_ctrl_reg_pkg::RegNumBanks;
+ parameter int unsigned PagesPerBank = flash_ctrl_reg_pkg::RegPagesPerBank;
+ parameter int unsigned BusPgmResBytes = flash_ctrl_reg_pkg::RegBusPgmResBytes;
+
+ // fixed parameters of flash derived from topgen parameters
+ parameter int DataWidth = 64;
+ parameter int MetaDataWidth = 12;
+ parameter int InfoTypes = 3; // How many types of info per bank
+
+// The following hard-wired values are there to work-around verilator.
+// For some reason if the values are assigned through parameters verilator thinks
+// they are not constant
+ parameter int InfoTypeSize [InfoTypes] = '{
+ 10,
+ 1,
+ 2
+ };
+ parameter int InfosPerBank = max_info_pages('{
+ 10,
+ 1,
+ 2
+ });
+ parameter int WordsPerPage = 256; // Number of flash words per page
+ parameter int BusWidth = top_pkg::TL_DW;
+ parameter int MpRegions = 8; // flash controller protection regions
+ parameter int FifoDepth = 16; // rd / prog fifos
+ parameter int InfoTypesWidth = prim_util_pkg::vbits(InfoTypes);
+
+ // flash phy parameters
+ parameter int DataByteWidth = prim_util_pkg::vbits(DataWidth / 8);
+ parameter int BankW = prim_util_pkg::vbits(NumBanks);
+ parameter int InfoPageW = prim_util_pkg::vbits(InfosPerBank);
+ parameter int PageW = prim_util_pkg::vbits(PagesPerBank);
+ parameter int WordW = prim_util_pkg::vbits(WordsPerPage);
+ parameter int AddrW = BankW + PageW + WordW; // all flash range
+ parameter int BankAddrW = PageW + WordW; // 1 bank of flash range
+ parameter int AllPagesW = BankW + PageW;
+
+ // flash ctrl / bus parameters
+ // flash / bus width may be different from actual flash word width
+ parameter int BusBytes = BusWidth / 8;
+ parameter int BusByteWidth = prim_util_pkg::vbits(BusBytes);
+ parameter int WidthMultiple = DataWidth / BusWidth;
+ // Number of bus words that can be programmed at once
+ parameter int BusPgmRes = BusPgmResBytes / BusBytes;
+ parameter int BusPgmResWidth = prim_util_pkg::vbits(BusPgmRes);
+ parameter int BusWordsPerPage = WordsPerPage * WidthMultiple;
+ parameter int BusWordW = prim_util_pkg::vbits(BusWordsPerPage);
+ parameter int BusAddrW = BankW + PageW + BusWordW;
+ parameter int BusAddrByteW = BusAddrW + BusByteWidth;
+ parameter int BusBankAddrW = PageW + BusWordW;
+ parameter int PhyAddrStart = BusWordW - WordW;
+
+
+ // fifo parameters
+ parameter int FifoDepthW = prim_util_pkg::vbits(FifoDepth+1);
+
+ // The end address in bus words for each kind of partition in each bank
+ parameter logic [PageW-1:0] DataPartitionEndAddr = PageW'(PagesPerBank - 1);
+ //parameter logic [PageW-1:0] InfoPartitionEndAddr [InfoTypes] = '{
+ // 9,
+ // 0,
+ // 1
+ //};
+ parameter logic [PageW-1:0] InfoPartitionEndAddr [InfoTypes] = '{
+ PageW'(InfoTypeSize[0] - 1),
+ PageW'(InfoTypeSize[1] - 1),
+ PageW'(InfoTypeSize[2] - 1)
+ };
+
+ ////////////////////////////
+ // All memory protection, seed related parameters
+ // Those related for seed pages should be template candidates
+ ////////////////////////////
+
+ // parameters for connected components
+ parameter int SeedWidth = 256;
+ parameter int KeyWidth = 128;
+ parameter int EdnWidth = edn_pkg::ENDPOINT_BUS_WIDTH;
+ typedef logic [KeyWidth-1:0] flash_key_t;
+
+ // Default Lfsr configurations
+ // These LFSR parameters have been generated with
+ // $ util/design/gen-lfsr-seed.py --width 32 --seed 1274809145 --prefix ""
+ parameter int LfsrWidth = 32;
+ typedef logic [LfsrWidth-1:0] lfsr_seed_t;
+ typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
+ parameter lfsr_seed_t RndCnstLfsrSeedDefault = 32'ha8cee782;
+ parameter lfsr_perm_t RndCnstLfsrPermDefault = {
+ 160'hd60bc7d86445da9347e0ccdd05b281df95238bb5
+ };
+
+ // These LFSR parameters have been generated with
+ // $ util/design/gen-lfsr-seed.py --width 64 --seed 691876113 --prefix ""
+
+
+ // lcmgr phase enum
+ typedef enum logic [1:0] {
+ PhaseSeed,
+ PhaseRma,
+ PhaseNone,
+ PhaseInvalid
+ } flash_lcmgr_phase_e;
+
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t;
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_region_cfg_shadowed_mreg_t;
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_bank0_info0_page_cfg_shadowed_mreg_t;
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_default_region_shadowed_reg_t;
+
+ typedef flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t sw_bank_cfg_t;
+ typedef flash_ctrl_reg2hw_mp_region_cfg_shadowed_mreg_t sw_region_cfg_t;
+ typedef flash_ctrl_reg2hw_default_region_shadowed_reg_t sw_default_cfg_t;
+ typedef flash_ctrl_reg2hw_bank0_info0_page_cfg_shadowed_mreg_t sw_info_cfg_t;
+
+ // alias for super long reg_pkg typedef
+ typedef struct packed {
+ logic q;
+ } bank_cfg_t;
+
+ // This is identical to the reg structures but do not have err_updates / storage
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } rd_en;
+ struct packed {
+ logic q;
+ } prog_en;
+ struct packed {
+ logic q;
+ } erase_en;
+ struct packed {
+ logic q;
+ } scramble_en;
+ struct packed {
+ logic q;
+ } ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
+ } info_page_cfg_t;
+
+ // This is identical to the reg structures but do not have err_updates / storage
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } rd_en;
+ struct packed {
+ logic q;
+ } prog_en;
+ struct packed {
+ logic q;
+ } erase_en;
+ struct packed {
+ logic q;
+ } scramble_en;
+ struct packed {
+ logic q;
+ } ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
+ struct packed {
+ logic [8:0] q;
+ } base;
+ struct packed {
+ logic [9:0] q;
+ } size;
+ } mp_region_cfg_t;
+
+ // memory protection specific structs
+ typedef struct packed {
+ logic [InfoTypesWidth-1:0] sel;
+ logic [AllPagesW-1:0] addr;
+ } page_addr_t;
+
+ typedef struct packed {
+ page_addr_t page;
+ flash_lcmgr_phase_e phase;
+ info_page_cfg_t cfg;
+ } info_page_attr_t;
+
+ typedef struct packed {
+ flash_lcmgr_phase_e phase;
+ mp_region_cfg_t cfg;
+ } data_region_attr_t;
+
+ // flash life cycle / key manager management constants
+ // One page for creator seeds
+ // One page for owner seeds
+ // One page for isolated flash page
+ parameter int NumSeeds = 2;
+ parameter bit [BankW-1:0] SeedBank = 0;
+ parameter bit [InfoTypesWidth-1:0] SeedInfoSel = 0;
+ parameter bit [0:0] CreatorSeedIdx = 0;
+ parameter bit [0:0] OwnerSeedIdx = 1;
+ parameter bit [PageW-1:0] CreatorInfoPage = 1;
+ parameter bit [PageW-1:0] OwnerInfoPage = 2;
+ parameter bit [PageW-1:0] IsolatedInfoPage = 3;
+
+ // which page of which info type of which bank for seed selection
+ parameter page_addr_t SeedInfoPageSel [NumSeeds] = '{
+ '{
+ sel: SeedInfoSel,
+ addr: {SeedBank, CreatorInfoPage}
+ },
+
+ '{
+ sel: SeedInfoSel,
+ addr: {SeedBank, OwnerInfoPage}
+ }
+ };
+
+ // which page of which info type of which bank for isolated partition
+ parameter page_addr_t IsolatedPageSel = '{
+ sel: SeedInfoSel,
+ addr: {SeedBank, IsolatedInfoPage}
+ };
+
+ // hardware interface memory protection rules
+ parameter int HwInfoRules = 5;
+ parameter int HwDataRules = 1;
+
+ parameter info_page_cfg_t CfgAllowRead = '{
+ en: 1'b1,
+ rd_en: 1'b1,
+ prog_en: 1'b0,
+ erase_en: 1'b0,
+ scramble_en: 1'b0,
+ ecc_en: 1'b0, // TBD, update to 1 once tb supports ECC
+ he_en: 1'b1
+ };
+
+ parameter info_page_cfg_t CfgAllowReadProgErase = '{
+ en: 1'b1,
+ rd_en: 1'b1,
+ prog_en: 1'b1,
+ erase_en: 1'b1,
+ scramble_en: 1'b1,
+ ecc_en: 1'b1,
+ he_en: 1'b1 // HW assumes high endurance
+ };
+
+ parameter info_page_attr_t HwInfoPageAttr[HwInfoRules] = '{
+ '{
+ page: SeedInfoPageSel[CreatorSeedIdx],
+ phase: PhaseSeed,
+ cfg: CfgAllowRead
+ },
+
+ '{
+ page: SeedInfoPageSel[OwnerSeedIdx],
+ phase: PhaseSeed,
+ cfg: CfgAllowRead
+ },
+
+ '{
+ page: SeedInfoPageSel[CreatorSeedIdx],
+ phase: PhaseRma,
+ cfg: CfgAllowReadProgErase
+ },
+
+ '{
+ page: SeedInfoPageSel[OwnerSeedIdx],
+ phase: PhaseRma,
+ cfg: CfgAllowReadProgErase
+ },
+
+ '{
+ page: IsolatedPageSel,
+ phase: PhaseRma,
+ cfg: CfgAllowReadProgErase
+ }
+ };
+
+ parameter data_region_attr_t HwDataAttr[HwDataRules] = '{
+ '{
+ phase: PhaseRma,
+ cfg: '{
+ en: 1'b1,
+ rd_en: 1'b1,
+ prog_en: 1'b1,
+ erase_en: 1'b1,
+ scramble_en: 1'b1,
+ ecc_en: 1'b1,
+ he_en: 1'b1, // HW assumes high endurance
+ base: '0,
+ size: '1
+ }
+ }
+ };
+
+
+ ////////////////////////////
+ // Design time constants
+ ////////////////////////////
+ parameter flash_key_t RndCnstAddrKeyDefault =
+ 128'h5d707f8a2d01d400928fa691c6a6e0a4;
+ parameter flash_key_t RndCnstDataKeyDefault =
+ 128'h39953618f2ca6f674af39f64975ea1f5;
+
+ ////////////////////////////
+ // Flash operation related enums
+ ////////////////////////////
+
+ // Flash Operations Supported
+ typedef enum logic [1:0] {
+ FlashOpRead = 2'h0,
+ FlashOpProgram = 2'h1,
+ FlashOpErase = 2'h2,
+ FlashOpInvalid = 2'h3
+ } flash_op_e;
+
+ // Flash Program Operations Supported
+ typedef enum logic {
+ FlashProgNormal = 0,
+ FlashProgRepair = 1
+ } flash_prog_e;
+ parameter int ProgTypes = 2;
+
+ // Flash Erase Operations Supported
+ typedef enum logic {
+ FlashErasePage = 0,
+ FlashEraseBank = 1
+ } flash_erase_e;
+
+ // Flash function select
+ typedef enum logic [1:0] {
+ NoneSel,
+ SwSel,
+ HwSel
+ } flash_sel_e;
+
+ // Flash tlul to fifo direction
+ typedef enum logic {
+ WriteDir = 1'b0,
+ ReadDir = 1'b1
+ } flash_flfo_dir_e;
+
+ // Flash partition type
+ typedef enum logic {
+ FlashPartData = 1'b0,
+ FlashPartInfo = 1'b1
+ } flash_part_e;
+
+ // Flash controller to memory
+ typedef struct packed {
+ logic req;
+ logic scramble_en;
+ logic ecc_en;
+ logic he_en;
+ logic rd_buf_en;
+ logic rd;
+ logic prog;
+ logic pg_erase;
+ logic bk_erase;
+ logic erase_suspend;
+ flash_part_e part;
+ logic [InfoTypesWidth-1:0] info_sel;
+ logic [BusAddrW-1:0] addr;
+ logic [BusWidth-1:0] prog_data;
+ logic prog_last;
+ flash_prog_e prog_type;
+ mp_region_cfg_t [MpRegions:0] region_cfgs;
+ logic [KeyWidth-1:0] addr_key;
+ logic [KeyWidth-1:0] data_key;
+ logic [KeyWidth-1:0] rand_addr_key;
+ logic [KeyWidth-1:0] rand_data_key;
+ logic alert_trig;
+ logic alert_ack;
+ jtag_pkg::jtag_req_t jtag_req;
+ logic intg_err;
+ prim_mubi_pkg::mubi4_t flash_disable;
+ } flash_req_t;
+
+ // default value of flash_req_t (for dangling ports)
+ parameter flash_req_t FLASH_REQ_DEFAULT = '{
+ req: '0,
+ scramble_en: '0,
+ ecc_en: '0,
+ he_en: '0,
+ rd_buf_en: 1'b0,
+ rd: '0,
+ prog: '0,
+ pg_erase: '0,
+ bk_erase: '0,
+ erase_suspend: '0,
+ part: FlashPartData,
+ info_sel: '0,
+ addr: '0,
+ prog_data: '0,
+ prog_last: '0,
+ prog_type: FlashProgNormal,
+ region_cfgs: '0,
+ addr_key: RndCnstAddrKeyDefault,
+ data_key: RndCnstDataKeyDefault,
+ rand_addr_key: '0,
+ rand_data_key: '0,
+ alert_trig: 1'b0,
+ alert_ack: 1'b0,
+ jtag_req: '0,
+ intg_err: '0,
+ flash_disable: prim_mubi_pkg::MuBi4False
+ };
+
+ // memory to flash controller
+ typedef struct packed {
+ logic [ProgTypes-1:0] prog_type_avail;
+ logic rd_done;
+ logic prog_done;
+ logic erase_done;
+ logic rd_err;
+ logic [BusWidth-1:0] rd_data;
+ logic init_busy;
+ logic flash_err;
+ logic [NumBanks-1:0] ecc_single_err;
+ logic [NumBanks-1:0][BusAddrW-1:0] ecc_addr;
+ jtag_pkg::jtag_rsp_t jtag_rsp;
+ logic intg_err;
+ } flash_rsp_t;
+
+ // default value of flash_rsp_t (for dangling ports)
+ parameter flash_rsp_t FLASH_RSP_DEFAULT = '{
+ prog_type_avail: {ProgTypes{1'b1}},
+ rd_done: 1'b0,
+ prog_done: 1'b0,
+ erase_done: 1'b0,
+ rd_err: '0,
+ rd_data: '0,
+ init_busy: 1'b0,
+ flash_err: 1'b0,
+ ecc_single_err: '0,
+ ecc_addr: '0,
+ jtag_rsp: '0,
+ intg_err: '0
+ };
+
+ // RMA entries
+ typedef struct packed {
+ logic [BankW-1:0] bank;
+ flash_part_e part;
+ logic [InfoTypesWidth-1:0] info_sel;
+ logic [PageW:0] start_page;
+ logic [PageW:0] num_pages;
+ } rma_wipe_entry_t;
+
+ // entries to be wiped
+ parameter int WipeEntries = 5;
+ parameter rma_wipe_entry_t RmaWipeEntries[WipeEntries] = '{
+ '{
+ bank: SeedBank,
+ part: FlashPartInfo,
+ info_sel: SeedInfoSel,
+ start_page: {1'b0, CreatorInfoPage},
+ num_pages: 1
+ },
+
+ '{
+ bank: SeedBank,
+ part: FlashPartInfo,
+ info_sel: SeedInfoSel,
+ start_page: {1'b0, OwnerInfoPage},
+ num_pages: 1
+ },
+
+ '{
+ bank: SeedBank,
+ part: FlashPartInfo,
+ info_sel: SeedInfoSel,
+ start_page: {1'b0, IsolatedInfoPage},
+ num_pages: 1
+ },
+
+ '{
+ bank: 0,
+ part: FlashPartData,
+ info_sel: 0,
+ start_page: 0,
+ num_pages: (PageW + 1)'(PagesPerBank)
+ },
+
+ '{
+ bank: 1,
+ part: FlashPartData,
+ info_sel: 0,
+ start_page: 0,
+ num_pages: (PageW + 1)'(PagesPerBank)
+ }
+ };
+
+
+ // flash_ctrl to keymgr
+ typedef struct packed {
+ logic [NumSeeds-1:0][SeedWidth-1:0] seeds;
+ } keymgr_flash_t;
+
+ parameter keymgr_flash_t KEYMGR_FLASH_DEFAULT = '{
+ seeds: '{
+ 256'h9152e32c9380a4bcc3e0ab263581e6b0e8825186e1e445631646e8bef8c45d47,
+ 256'hfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78
+ }
+ };
+
+ // dft_en jtag selection
+ typedef enum logic [2:0] {
+ FlashLcTckSel,
+ FlashLcTdiSel,
+ FlashLcTmsSel,
+ FlashLcTdoSel,
+ FlashBistSel,
+ FlashLcDftLast
+ } flash_lc_jtag_e;
+
+ // Error bit positioning
+ typedef struct packed {
+ logic oob_err;
+ logic mp_err;
+ logic rd_err;
+ logic prog_win_err;
+ logic prog_type_err;
+ logic phy_err;
+ } flash_ctrl_err_t;
+
+ // interrupt bit positioning
+ typedef enum logic[2:0] {
+ ProgEmpty,
+ ProgLvl,
+ RdFull,
+ RdLvl,
+ OpDone,
+ CorrErr,
+ LastIntrIdx
+ } flash_ctrl_intr_e;
+
+ // find the max number pages among info types
+ function automatic integer max_info_pages(int infos[InfoTypes]);
+ int current_max = 0;
+ for (int i = 0; i < InfoTypes; i++) begin
+ if (infos[i] > current_max) begin
+ current_max = infos[i];
+ end
+ end
+ return current_max;
+ endfunction // max_info_banks
+
+ // RMA control FSM encoding
+ // Encoding generated with:
+ // $ ./util/design/sparse-fsm-encode.py -d 5 -m 7 -n 10 // -s 3319803877 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: |||||||||||||||||||| (47.62%)
+ // 6: |||||||||||||||| (38.10%)
+ // 7: |||| (9.52%)
+ // 8: || (4.76%)
+ // 9: --
+ // 10: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 8
+ // Minimum Hamming weight: 3
+ // Maximum Hamming weight: 6
+ //
+ localparam int RmaStateWidth = 10;
+ typedef enum logic [RmaStateWidth-1:0] {
+ StRmaIdle = 10'b1101000011,
+ StRmaPageSel = 10'b0010111001,
+ StRmaErase = 10'b1111010100,
+ StRmaEraseWait = 10'b0111010101,
+ StRmaWordSel = 10'b0001011111,
+ StRmaProgram = 10'b0110001110,
+ StRmaProgramWait = 10'b1000110110,
+ StRmaRdVerify = 10'b1011101010,
+ StRmaInvalid = 10'b1100101101
+ } rma_state_e;
+
+endpackage : flash_ctrl_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_ctrl_reg_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_ctrl_reg_pkg.sv
new file mode 100644
index 00000000..d2ac6ff9
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_ctrl_reg_pkg.sv
@@ -0,0 +1,1094 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package flash_ctrl_reg_pkg;
+
+ // Param list
+ parameter int RegNumBanks = 2;
+ parameter int RegPagesPerBank = 256;
+ parameter int RegBusPgmResBytes = 512;
+ parameter int RegPageWidth = 8;
+ parameter int RegBankWidth = 1;
+ parameter int NumRegions = 8;
+ parameter int NumInfos0 = 10;
+ parameter int NumInfos1 = 1;
+ parameter int NumInfos2 = 2;
+ parameter int WordsPerPage = 256;
+ parameter int BytesPerWord = 8;
+ parameter int BytesPerPage = 2048;
+ parameter int BytesPerBank = 524288;
+ parameter int ExecEn = 2724870391;
+ parameter int NumAlerts = 2;
+
+ // Address widths within the block
+ parameter int CoreAw = 9;
+ parameter int PrimAw = 1;
+ parameter int MemAw = 1;
+
+ ///////////////////////////////////////////////
+ // Typedefs for registers for core interface //
+ ///////////////////////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } prog_empty;
+ struct packed {
+ logic q;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ } rd_full;
+ struct packed {
+ logic q;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ } op_done;
+ struct packed {
+ logic q;
+ } corr_err;
+ } flash_ctrl_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } prog_empty;
+ struct packed {
+ logic q;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ } rd_full;
+ struct packed {
+ logic q;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ } op_done;
+ struct packed {
+ logic q;
+ } corr_err;
+ } flash_ctrl_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } prog_empty;
+ struct packed {
+ logic q;
+ logic qe;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ logic qe;
+ } rd_full;
+ struct packed {
+ logic q;
+ logic qe;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ logic qe;
+ } op_done;
+ struct packed {
+ logic q;
+ logic qe;
+ } corr_err;
+ } flash_ctrl_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } recov_err;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_err;
+ } flash_ctrl_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } flash_ctrl_reg2hw_dis_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } flash_ctrl_reg2hw_exec_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_init_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } start;
+ struct packed {
+ logic [1:0] q;
+ } op;
+ struct packed {
+ logic q;
+ } prog_sel;
+ struct packed {
+ logic q;
+ } erase_sel;
+ struct packed {
+ logic q;
+ } partition_sel;
+ struct packed {
+ logic [1:0] q;
+ } info_sel;
+ struct packed {
+ logic [11:0] q;
+ } num;
+ } flash_ctrl_reg2hw_control_reg_t;
+
+ typedef struct packed {
+ logic [19:0] q;
+ } flash_ctrl_reg2hw_addr_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } normal;
+ struct packed {
+ logic q;
+ } repair;
+ } flash_ctrl_reg2hw_prog_type_en_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_erase_suspend_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ struct packed {
+ logic [8:0] q;
+ logic err_update;
+ logic err_storage;
+ } base;
+ struct packed {
+ logic [9:0] q;
+ logic err_update;
+ logic err_storage;
+ } size;
+ } flash_ctrl_reg2hw_mp_region_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_default_region_shadowed_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank0_info0_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank0_info1_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank0_info2_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank1_info0_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank1_info1_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank1_info2_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } mp_err;
+ struct packed {
+ logic q;
+ } rd_err;
+ struct packed {
+ logic q;
+ } prog_win_err;
+ struct packed {
+ logic q;
+ } prog_type_err;
+ struct packed {
+ logic q;
+ } flash_phy_err;
+ struct packed {
+ logic q;
+ } reg_intg_err;
+ struct packed {
+ logic q;
+ } phy_intg_err;
+ struct packed {
+ logic q;
+ } lcmgr_err;
+ struct packed {
+ logic q;
+ } arb_fsm_err;
+ struct packed {
+ logic q;
+ } storage_err;
+ } flash_ctrl_reg2hw_fault_status_reg_t;
+
+ typedef struct packed {
+ logic [7:0] q;
+ } flash_ctrl_reg2hw_ecc_single_err_cnt_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } alert_ack;
+ struct packed {
+ logic q;
+ } alert_trig;
+ } flash_ctrl_reg2hw_phy_alert_cfg_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } flash_ctrl_reg2hw_scratch_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [4:0] q;
+ } prog;
+ struct packed {
+ logic [4:0] q;
+ } rd;
+ } flash_ctrl_reg2hw_fifo_lvl_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_fifo_rst_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } prog_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_lvl;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_full;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_lvl;
+ struct packed {
+ logic d;
+ logic de;
+ } op_done;
+ struct packed {
+ logic d;
+ logic de;
+ } corr_err;
+ } flash_ctrl_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ logic d;
+ } flash_ctrl_hw2reg_ctrl_regwen_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } start;
+ } flash_ctrl_hw2reg_control_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } flash_ctrl_hw2reg_erase_suspend_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } done;
+ struct packed {
+ logic d;
+ logic de;
+ } err;
+ } flash_ctrl_hw2reg_op_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } rd_full;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_full;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } init_wip;
+ } flash_ctrl_hw2reg_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } mp_err;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_win_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_type_err;
+ struct packed {
+ logic d;
+ logic de;
+ } flash_phy_err;
+ struct packed {
+ logic d;
+ logic de;
+ } update_err;
+ } flash_ctrl_hw2reg_err_code_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } mp_err;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_win_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_type_err;
+ struct packed {
+ logic d;
+ logic de;
+ } flash_phy_err;
+ struct packed {
+ logic d;
+ logic de;
+ } reg_intg_err;
+ struct packed {
+ logic d;
+ logic de;
+ } phy_intg_err;
+ struct packed {
+ logic d;
+ logic de;
+ } lcmgr_err;
+ struct packed {
+ logic d;
+ logic de;
+ } arb_fsm_err;
+ struct packed {
+ logic d;
+ logic de;
+ } storage_err;
+ } flash_ctrl_hw2reg_fault_status_reg_t;
+
+ typedef struct packed {
+ logic [19:0] d;
+ logic de;
+ } flash_ctrl_hw2reg_err_addr_reg_t;
+
+ typedef struct packed {
+ logic [7:0] d;
+ logic de;
+ } flash_ctrl_hw2reg_ecc_single_err_cnt_mreg_t;
+
+ typedef struct packed {
+ logic [19:0] d;
+ logic de;
+ } flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } init_wip;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_normal_avail;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_repair_avail;
+ } flash_ctrl_hw2reg_phy_status_reg_t;
+
+ // Register -> HW type for core interface
+ typedef struct packed {
+ flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [576:571]
+ flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [570:565]
+ flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [564:553]
+ flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [552:549]
+ flash_ctrl_reg2hw_dis_reg_t dis; // [548:545]
+ flash_ctrl_reg2hw_exec_reg_t exec; // [544:513]
+ flash_ctrl_reg2hw_init_reg_t init; // [512:512]
+ flash_ctrl_reg2hw_control_reg_t control; // [511:492]
+ flash_ctrl_reg2hw_addr_reg_t addr; // [491:472]
+ flash_ctrl_reg2hw_prog_type_en_reg_t prog_type_en; // [471:470]
+ flash_ctrl_reg2hw_erase_suspend_reg_t erase_suspend; // [469:469]
+ flash_ctrl_reg2hw_mp_region_cfg_shadowed_mreg_t [7:0] mp_region_cfg_shadowed; // [468:261]
+ flash_ctrl_reg2hw_default_region_shadowed_reg_t default_region_shadowed; // [260:255]
+ flash_ctrl_reg2hw_bank0_info0_page_cfg_shadowed_mreg_t [9:0]
+ bank0_info0_page_cfg_shadowed; // [254:185]
+ flash_ctrl_reg2hw_bank0_info1_page_cfg_shadowed_mreg_t [0:0]
+ bank0_info1_page_cfg_shadowed; // [184:178]
+ flash_ctrl_reg2hw_bank0_info2_page_cfg_shadowed_mreg_t [1:0]
+ bank0_info2_page_cfg_shadowed; // [177:164]
+ flash_ctrl_reg2hw_bank1_info0_page_cfg_shadowed_mreg_t [9:0]
+ bank1_info0_page_cfg_shadowed; // [163:94]
+ flash_ctrl_reg2hw_bank1_info1_page_cfg_shadowed_mreg_t [0:0]
+ bank1_info1_page_cfg_shadowed; // [93:87]
+ flash_ctrl_reg2hw_bank1_info2_page_cfg_shadowed_mreg_t [1:0]
+ bank1_info2_page_cfg_shadowed; // [86:73]
+ flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t [1:0] mp_bank_cfg_shadowed; // [72:71]
+ flash_ctrl_reg2hw_fault_status_reg_t fault_status; // [70:61]
+ flash_ctrl_reg2hw_ecc_single_err_cnt_mreg_t [1:0] ecc_single_err_cnt; // [60:45]
+ flash_ctrl_reg2hw_phy_alert_cfg_reg_t phy_alert_cfg; // [44:43]
+ flash_ctrl_reg2hw_scratch_reg_t scratch; // [42:11]
+ flash_ctrl_reg2hw_fifo_lvl_reg_t fifo_lvl; // [10:1]
+ flash_ctrl_reg2hw_fifo_rst_reg_t fifo_rst; // [0:0]
+ } flash_ctrl_core_reg2hw_t;
+
+ // HW -> register type for core interface
+ typedef struct packed {
+ flash_ctrl_hw2reg_intr_state_reg_t intr_state; // [149:138]
+ flash_ctrl_hw2reg_ctrl_regwen_reg_t ctrl_regwen; // [137:137]
+ flash_ctrl_hw2reg_control_reg_t control; // [136:135]
+ flash_ctrl_hw2reg_erase_suspend_reg_t erase_suspend; // [134:133]
+ flash_ctrl_hw2reg_op_status_reg_t op_status; // [132:129]
+ flash_ctrl_hw2reg_status_reg_t status; // [128:119]
+ flash_ctrl_hw2reg_err_code_reg_t err_code; // [118:107]
+ flash_ctrl_hw2reg_fault_status_reg_t fault_status; // [106:87]
+ flash_ctrl_hw2reg_err_addr_reg_t err_addr; // [86:66]
+ flash_ctrl_hw2reg_ecc_single_err_cnt_mreg_t [1:0] ecc_single_err_cnt; // [65:48]
+ flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t [1:0] ecc_single_err_addr; // [47:6]
+ flash_ctrl_hw2reg_phy_status_reg_t phy_status; // [5:0]
+ } flash_ctrl_core_hw2reg_t;
+
+ // Register offsets for core interface
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INTR_STATE_OFFSET = 9'h0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INTR_ENABLE_OFFSET = 9'h4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INTR_TEST_OFFSET = 9'h8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ALERT_TEST_OFFSET = 9'hc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_DIS_OFFSET = 9'h10;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_EXEC_OFFSET = 9'h14;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INIT_OFFSET = 9'h18;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_CTRL_REGWEN_OFFSET = 9'h1c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_CONTROL_OFFSET = 9'h20;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ADDR_OFFSET = 9'h24;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_TYPE_EN_OFFSET = 9'h28;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ERASE_SUSPEND_OFFSET = 9'h2c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET = 9'h30;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET = 9'h34;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET = 9'h38;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET = 9'h3c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET = 9'h40;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET = 9'h44;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET = 9'h48;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET = 9'h4c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET = 9'h50;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET = 9'h54;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET = 9'h58;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET = 9'h5c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET = 9'h60;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET = 9'h64;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET = 9'h68;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET = 9'h6c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET = 9'h70;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET = 9'h74;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET = 9'h78;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET = 9'h7c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET = 9'h80;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET = 9'h84;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET = 9'h88;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET = 9'h8c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET = 9'h90;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET = 9'h94;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET = 9'h98;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET = 9'h9c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET = 9'ha0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET = 9'ha4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET = 9'ha8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET = 9'hac;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET = 9'hb0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET = 9'hb4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET = 9'hb8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET = 9'hbc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET = 9'hc0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET = 9'hc4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET = 9'hc8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET = 9'hcc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET = 9'hd0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET = 9'hd4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET = 9'hd8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET = 9'hdc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET = 9'he0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET = 9'he4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET = 9'he8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET = 9'hec;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET = 9'hf0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET = 9'hf4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET = 9'hf8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET = 9'hfc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET = 9'h100;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET = 9'h104;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET = 9'h108;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET = 9'h10c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET = 9'h110;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET = 9'h114;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET = 9'h118;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET = 9'h11c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET = 9'h120;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET = 9'h124;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET = 9'h128;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET = 9'h12c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET = 9'h130;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET = 9'h134;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET = 9'h138;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET = 9'h13c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET = 9'h140;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 9'h144;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET = 9'h148;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_OP_STATUS_OFFSET = 9'h14c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_STATUS_OFFSET = 9'h150;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_CODE_OFFSET = 9'h154;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FAULT_STATUS_OFFSET = 9'h158;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_ADDR_OFFSET = 9'h15c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET = 9'h160;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET = 9'h164;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET = 9'h168;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ALERT_CFG_OFFSET = 9'h16c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h170;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h174;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h178;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h17c;
+
+ // Reset values for hwext registers and their fields for core interface
+ parameter logic [5:0] FLASH_CTRL_INTR_TEST_RESVAL = 6'h0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL = 1'h0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL = 1'h0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL = 1'h0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL = 1'h0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL = 1'h0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL = 1'h0;
+ parameter logic [1:0] FLASH_CTRL_ALERT_TEST_RESVAL = 2'h0;
+ parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL = 1'h0;
+ parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL = 1'h0;
+ parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_RESVAL = 1'h1;
+ parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_EN_RESVAL = 1'h1;
+
+ // Window parameters for core interface
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h180;
+ parameter int unsigned FLASH_CTRL_PROG_FIFO_SIZE = 'h4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h184;
+ parameter int unsigned FLASH_CTRL_RD_FIFO_SIZE = 'h4;
+
+ // Register index for core interface
+ typedef enum int {
+ FLASH_CTRL_INTR_STATE,
+ FLASH_CTRL_INTR_ENABLE,
+ FLASH_CTRL_INTR_TEST,
+ FLASH_CTRL_ALERT_TEST,
+ FLASH_CTRL_DIS,
+ FLASH_CTRL_EXEC,
+ FLASH_CTRL_INIT,
+ FLASH_CTRL_CTRL_REGWEN,
+ FLASH_CTRL_CONTROL,
+ FLASH_CTRL_ADDR,
+ FLASH_CTRL_PROG_TYPE_EN,
+ FLASH_CTRL_ERASE_SUSPEND,
+ FLASH_CTRL_REGION_CFG_REGWEN_0,
+ FLASH_CTRL_REGION_CFG_REGWEN_1,
+ FLASH_CTRL_REGION_CFG_REGWEN_2,
+ FLASH_CTRL_REGION_CFG_REGWEN_3,
+ FLASH_CTRL_REGION_CFG_REGWEN_4,
+ FLASH_CTRL_REGION_CFG_REGWEN_5,
+ FLASH_CTRL_REGION_CFG_REGWEN_6,
+ FLASH_CTRL_REGION_CFG_REGWEN_7,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_0,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_1,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_2,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_3,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_4,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_5,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_6,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_7,
+ FLASH_CTRL_DEFAULT_REGION_SHADOWED,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_0,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_1,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_2,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_3,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_4,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_5,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_6,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_7,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_8,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_9,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9,
+ FLASH_CTRL_BANK0_INFO1_REGWEN,
+ FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED,
+ FLASH_CTRL_BANK0_INFO2_REGWEN_0,
+ FLASH_CTRL_BANK0_INFO2_REGWEN_1,
+ FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0,
+ FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_0,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_1,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_2,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_3,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_4,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_5,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_6,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_7,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_8,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_9,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9,
+ FLASH_CTRL_BANK1_INFO1_REGWEN,
+ FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED,
+ FLASH_CTRL_BANK1_INFO2_REGWEN_0,
+ FLASH_CTRL_BANK1_INFO2_REGWEN_1,
+ FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0,
+ FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1,
+ FLASH_CTRL_BANK_CFG_REGWEN,
+ FLASH_CTRL_MP_BANK_CFG_SHADOWED,
+ FLASH_CTRL_OP_STATUS,
+ FLASH_CTRL_STATUS,
+ FLASH_CTRL_ERR_CODE,
+ FLASH_CTRL_FAULT_STATUS,
+ FLASH_CTRL_ERR_ADDR,
+ FLASH_CTRL_ECC_SINGLE_ERR_CNT,
+ FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0,
+ FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1,
+ FLASH_CTRL_PHY_ALERT_CFG,
+ FLASH_CTRL_PHY_STATUS,
+ FLASH_CTRL_SCRATCH,
+ FLASH_CTRL_FIFO_LVL,
+ FLASH_CTRL_FIFO_RST
+ } flash_ctrl_core_id_e;
+
+ // Register width information to check illegal writes for core interface
+ parameter logic [3:0] FLASH_CTRL_CORE_PERMIT [96] = '{
+ 4'b0001, // index[ 0] FLASH_CTRL_INTR_STATE
+ 4'b0001, // index[ 1] FLASH_CTRL_INTR_ENABLE
+ 4'b0001, // index[ 2] FLASH_CTRL_INTR_TEST
+ 4'b0001, // index[ 3] FLASH_CTRL_ALERT_TEST
+ 4'b0001, // index[ 4] FLASH_CTRL_DIS
+ 4'b1111, // index[ 5] FLASH_CTRL_EXEC
+ 4'b0001, // index[ 6] FLASH_CTRL_INIT
+ 4'b0001, // index[ 7] FLASH_CTRL_CTRL_REGWEN
+ 4'b1111, // index[ 8] FLASH_CTRL_CONTROL
+ 4'b0111, // index[ 9] FLASH_CTRL_ADDR
+ 4'b0001, // index[10] FLASH_CTRL_PROG_TYPE_EN
+ 4'b0001, // index[11] FLASH_CTRL_ERASE_SUSPEND
+ 4'b0001, // index[12] FLASH_CTRL_REGION_CFG_REGWEN_0
+ 4'b0001, // index[13] FLASH_CTRL_REGION_CFG_REGWEN_1
+ 4'b0001, // index[14] FLASH_CTRL_REGION_CFG_REGWEN_2
+ 4'b0001, // index[15] FLASH_CTRL_REGION_CFG_REGWEN_3
+ 4'b0001, // index[16] FLASH_CTRL_REGION_CFG_REGWEN_4
+ 4'b0001, // index[17] FLASH_CTRL_REGION_CFG_REGWEN_5
+ 4'b0001, // index[18] FLASH_CTRL_REGION_CFG_REGWEN_6
+ 4'b0001, // index[19] FLASH_CTRL_REGION_CFG_REGWEN_7
+ 4'b1111, // index[20] FLASH_CTRL_MP_REGION_CFG_SHADOWED_0
+ 4'b1111, // index[21] FLASH_CTRL_MP_REGION_CFG_SHADOWED_1
+ 4'b1111, // index[22] FLASH_CTRL_MP_REGION_CFG_SHADOWED_2
+ 4'b1111, // index[23] FLASH_CTRL_MP_REGION_CFG_SHADOWED_3
+ 4'b1111, // index[24] FLASH_CTRL_MP_REGION_CFG_SHADOWED_4
+ 4'b1111, // index[25] FLASH_CTRL_MP_REGION_CFG_SHADOWED_5
+ 4'b1111, // index[26] FLASH_CTRL_MP_REGION_CFG_SHADOWED_6
+ 4'b1111, // index[27] FLASH_CTRL_MP_REGION_CFG_SHADOWED_7
+ 4'b0001, // index[28] FLASH_CTRL_DEFAULT_REGION_SHADOWED
+ 4'b0001, // index[29] FLASH_CTRL_BANK0_INFO0_REGWEN_0
+ 4'b0001, // index[30] FLASH_CTRL_BANK0_INFO0_REGWEN_1
+ 4'b0001, // index[31] FLASH_CTRL_BANK0_INFO0_REGWEN_2
+ 4'b0001, // index[32] FLASH_CTRL_BANK0_INFO0_REGWEN_3
+ 4'b0001, // index[33] FLASH_CTRL_BANK0_INFO0_REGWEN_4
+ 4'b0001, // index[34] FLASH_CTRL_BANK0_INFO0_REGWEN_5
+ 4'b0001, // index[35] FLASH_CTRL_BANK0_INFO0_REGWEN_6
+ 4'b0001, // index[36] FLASH_CTRL_BANK0_INFO0_REGWEN_7
+ 4'b0001, // index[37] FLASH_CTRL_BANK0_INFO0_REGWEN_8
+ 4'b0001, // index[38] FLASH_CTRL_BANK0_INFO0_REGWEN_9
+ 4'b0001, // index[39] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0
+ 4'b0001, // index[40] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1
+ 4'b0001, // index[41] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2
+ 4'b0001, // index[42] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3
+ 4'b0001, // index[43] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4
+ 4'b0001, // index[44] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5
+ 4'b0001, // index[45] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6
+ 4'b0001, // index[46] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7
+ 4'b0001, // index[47] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8
+ 4'b0001, // index[48] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9
+ 4'b0001, // index[49] FLASH_CTRL_BANK0_INFO1_REGWEN
+ 4'b0001, // index[50] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED
+ 4'b0001, // index[51] FLASH_CTRL_BANK0_INFO2_REGWEN_0
+ 4'b0001, // index[52] FLASH_CTRL_BANK0_INFO2_REGWEN_1
+ 4'b0001, // index[53] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0
+ 4'b0001, // index[54] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1
+ 4'b0001, // index[55] FLASH_CTRL_BANK1_INFO0_REGWEN_0
+ 4'b0001, // index[56] FLASH_CTRL_BANK1_INFO0_REGWEN_1
+ 4'b0001, // index[57] FLASH_CTRL_BANK1_INFO0_REGWEN_2
+ 4'b0001, // index[58] FLASH_CTRL_BANK1_INFO0_REGWEN_3
+ 4'b0001, // index[59] FLASH_CTRL_BANK1_INFO0_REGWEN_4
+ 4'b0001, // index[60] FLASH_CTRL_BANK1_INFO0_REGWEN_5
+ 4'b0001, // index[61] FLASH_CTRL_BANK1_INFO0_REGWEN_6
+ 4'b0001, // index[62] FLASH_CTRL_BANK1_INFO0_REGWEN_7
+ 4'b0001, // index[63] FLASH_CTRL_BANK1_INFO0_REGWEN_8
+ 4'b0001, // index[64] FLASH_CTRL_BANK1_INFO0_REGWEN_9
+ 4'b0001, // index[65] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0
+ 4'b0001, // index[66] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1
+ 4'b0001, // index[67] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2
+ 4'b0001, // index[68] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3
+ 4'b0001, // index[69] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4
+ 4'b0001, // index[70] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5
+ 4'b0001, // index[71] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6
+ 4'b0001, // index[72] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7
+ 4'b0001, // index[73] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8
+ 4'b0001, // index[74] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9
+ 4'b0001, // index[75] FLASH_CTRL_BANK1_INFO1_REGWEN
+ 4'b0001, // index[76] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED
+ 4'b0001, // index[77] FLASH_CTRL_BANK1_INFO2_REGWEN_0
+ 4'b0001, // index[78] FLASH_CTRL_BANK1_INFO2_REGWEN_1
+ 4'b0001, // index[79] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0
+ 4'b0001, // index[80] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1
+ 4'b0001, // index[81] FLASH_CTRL_BANK_CFG_REGWEN
+ 4'b0001, // index[82] FLASH_CTRL_MP_BANK_CFG_SHADOWED
+ 4'b0001, // index[83] FLASH_CTRL_OP_STATUS
+ 4'b0001, // index[84] FLASH_CTRL_STATUS
+ 4'b0001, // index[85] FLASH_CTRL_ERR_CODE
+ 4'b0011, // index[86] FLASH_CTRL_FAULT_STATUS
+ 4'b0111, // index[87] FLASH_CTRL_ERR_ADDR
+ 4'b0011, // index[88] FLASH_CTRL_ECC_SINGLE_ERR_CNT
+ 4'b0111, // index[89] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0
+ 4'b0111, // index[90] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1
+ 4'b0001, // index[91] FLASH_CTRL_PHY_ALERT_CFG
+ 4'b0001, // index[92] FLASH_CTRL_PHY_STATUS
+ 4'b1111, // index[93] FLASH_CTRL_SCRATCH
+ 4'b0011, // index[94] FLASH_CTRL_FIFO_LVL
+ 4'b0001 // index[95] FLASH_CTRL_FIFO_RST
+ };
+
+endpackage
+
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_phy_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_phy_pkg.sv
new file mode 100644
index 00000000..5cdec0f7
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/flash_phy_pkg.sv
@@ -0,0 +1,125 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Flash phy module package
+//
+
+package flash_phy_pkg;
+
+ // flash phy parameters
+ parameter int NumBanks = flash_ctrl_pkg::NumBanks;
+ parameter int InfosPerBank = flash_ctrl_pkg::InfosPerBank;
+ parameter int PagesPerBank = flash_ctrl_pkg::PagesPerBank;
+ parameter int WordsPerPage = flash_ctrl_pkg::WordsPerPage;
+ parameter int BankW = flash_ctrl_pkg::BankW;
+ parameter int PageW = flash_ctrl_pkg::PageW;
+ parameter int WordW = flash_ctrl_pkg::WordW;
+ parameter int BankAddrW = flash_ctrl_pkg::BankAddrW;
+ parameter int DataWidth = flash_ctrl_pkg::DataWidth;
+ parameter int EccWidth = 8;
+ parameter int MetaDataWidth = flash_ctrl_pkg::MetaDataWidth;
+ parameter int WidthMultiple = flash_ctrl_pkg::WidthMultiple;
+ parameter int NumBuf = 4; // number of flash read buffers
+ parameter int RspOrderDepth = 2; // this should be DataWidth / BusWidth
+ // will switch to this after bus widening
+ parameter int ScrDataWidth = DataWidth + EccWidth;
+ parameter int FullDataWidth = DataWidth + MetaDataWidth;
+ parameter int InfoTypes = flash_ctrl_pkg::InfoTypes;
+ parameter int InfoTypesWidth = flash_ctrl_pkg::InfoTypesWidth;
+
+ // flash ctrl / bus parameters
+ parameter int BusWidth = flash_ctrl_pkg::BusWidth;
+ parameter int BusBankAddrW = flash_ctrl_pkg::BusBankAddrW;
+ parameter int BusWordW = flash_ctrl_pkg::BusWordW;
+ parameter int ProgTypes = flash_ctrl_pkg::ProgTypes;
+
+ // address bits remain must be 0
+ parameter int AddrBitsRemain = DataWidth % BusWidth;
+
+ // base index
+ // This is the lsb position of the prim flash address when looking at the bus address
+ parameter int LsbAddrBit = $clog2(WidthMultiple);
+ parameter int WordSelW = WidthMultiple == 1 ? 1 : LsbAddrBit;
+
+ // scramble / de-scramble parameters
+ // Number of cycles the gf_mult is given to complete
+ parameter int KeySize = 128;
+ parameter int GfMultCycles = 2;
+ // If this value is greater than 1, constraints must be updated for multicycle paths
+ parameter int CipherCycles = 2;
+
+ // Read buffer metadata
+ typedef enum logic [1:0] {
+ Invalid = 2'h0,
+ Wip = 2'h1,
+ Valid = 2'h2,
+ Undef = 2'h3
+ } rd_buf_attr_e;
+
+ typedef struct packed {
+ logic [DataWidth-1:0] data;
+ logic [BankAddrW-1:0] addr; // all address bits preserved to pick return portion
+ logic part;
+ logic [InfoTypesWidth-1:0] info_sel;
+ rd_buf_attr_e attr;
+ } rd_buf_t;
+
+ typedef struct packed {
+ logic [NumBuf-1:0] buf_sel;
+ logic [WordSelW-1:0] word_sel;
+ } rsp_fifo_entry_t;
+
+ parameter int RspOrderFifoWidth = $bits(rsp_fifo_entry_t);
+
+ typedef struct packed {
+ logic [BankAddrW-1:0] addr;
+ logic descramble;
+ logic ecc;
+ } rd_attr_t;
+
+ // Flash Operations Supported
+ typedef enum logic [2:0] {
+ PhyRead = 3'h0,
+ PhyProg = 3'h1,
+ PhyPgErase = 3'h2,
+ PhyBkErase = 3'h3,
+ PhyOps = 3'h4
+ } flash_phy_op_e;
+
+ // Flash Operations Selected
+ typedef enum logic [1:0] {
+ None = 2'h0,
+ Host = 2'h1,
+ Ctrl = 2'h2
+ } flash_phy_op_sel_e;
+
+ typedef enum logic {
+ ScrambleOp = 1'b0,
+ DeScrambleOp = 1'b1
+ } cipher_ops_e;
+
+ // Connections to prim_flash
+ typedef struct packed {
+ logic rd_req;
+ logic prog_req;
+ logic prog_last;
+ flash_ctrl_pkg::flash_prog_e prog_type;
+ logic pg_erase_req;
+ logic bk_erase_req;
+ logic erase_suspend_req;
+ logic he;
+ logic [BankAddrW-1:0] addr;
+ flash_ctrl_pkg::flash_part_e part;
+ logic [InfoTypesWidth-1:0] info_sel;
+ logic [FullDataWidth-1:0] prog_full_data;
+ } flash_phy_prim_flash_req_t;
+
+ typedef struct packed {
+ logic ack;
+ logic done;
+ logic [FullDataWidth-1:0] rdata;
+ logic erase_suspend_done;
+ } flash_phy_prim_flash_rsp_t;
+
+endpackage // flash_phy_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac.sv
new file mode 100644
index 00000000..6cca40d5
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac.sv
@@ -0,0 +1,565 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// HMAC-SHA256
+
+
+
+module hmac
+ import hmac_pkg::*;
+ import hmac_reg_pkg::*;
+#(
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}
+) (
+ input clk_i,
+ input rst_ni,
+
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+
+ output logic intr_hmac_done_o,
+ output logic intr_fifo_empty_o,
+ output logic intr_hmac_err_o,
+
+ output logic idle_o
+);
+
+
+ /////////////////////////
+ // Signal declarations //
+ /////////////////////////
+ hmac_reg2hw_t reg2hw;
+ hmac_hw2reg_t hw2reg;
+
+ tlul_pkg::tl_h2d_t tl_win_h2d;
+ tlul_pkg::tl_d2h_t tl_win_d2h;
+
+ logic [255:0] secret_key;
+
+ logic wipe_secret;
+ logic [31:0] wipe_v;
+
+ logic fifo_rvalid;
+ logic fifo_rready;
+ sha_fifo_t fifo_rdata;
+
+ logic fifo_wvalid, fifo_wready;
+ sha_fifo_t fifo_wdata;
+ logic fifo_full;
+ logic fifo_empty;
+ logic [4:0] fifo_depth;
+
+ logic msg_fifo_req;
+ logic msg_fifo_gnt;
+ logic msg_fifo_we;
+ logic [31:0] msg_fifo_wdata;
+ logic [31:0] msg_fifo_wmask;
+ logic [31:0] msg_fifo_rdata;
+ logic msg_fifo_rvalid;
+ logic [1:0] msg_fifo_rerror;
+ logic [31:0] msg_fifo_wdata_endian;
+ logic [31:0] msg_fifo_wmask_endian;
+
+ logic packer_ready;
+ logic packer_flush_done;
+
+ logic reg_fifo_wvalid;
+ sha_word_t reg_fifo_wdata;
+ sha_word_t reg_fifo_wmask;
+ logic hmac_fifo_wsel;
+ logic hmac_fifo_wvalid;
+ logic [2:0] hmac_fifo_wdata_sel;
+
+ logic shaf_rvalid;
+ sha_fifo_t shaf_rdata;
+ logic shaf_rready;
+
+ logic sha_en;
+ logic hmac_en;
+ logic endian_swap;
+ logic digest_swap;
+
+ logic reg_hash_start;
+ logic sha_hash_start;
+ logic hash_start; // Valid hash_start_signal
+ logic reg_hash_process;
+ logic sha_hash_process;
+
+ logic reg_hash_done;
+ logic sha_hash_done;
+
+ logic [63:0] message_length;
+ logic [63:0] sha_message_length;
+
+ err_code_e err_code;
+ logic err_valid;
+
+ sha_word_t [7:0] digest;
+
+ hmac_reg2hw_cfg_reg_t cfg_reg;
+ logic cfg_block; // Prevent changing config
+ logic msg_allowed; // MSG_FIFO from software is allowed
+
+ logic hmac_core_idle;
+ logic sha_core_idle;
+
+ ///////////////////////
+ // Connect registers //
+ ///////////////////////
+ assign hw2reg.status.fifo_full.d = fifo_full;
+ assign hw2reg.status.fifo_empty.d = fifo_empty;
+ assign hw2reg.status.fifo_depth.d = fifo_depth;
+
+ // secret key
+ assign wipe_secret = reg2hw.wipe_secret.qe;
+ assign wipe_v = reg2hw.wipe_secret.q;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ secret_key <= '0;
+ end else if (wipe_secret) begin
+ secret_key <= {8{wipe_v}};
+ end else if (!cfg_block) begin
+ // Allow updating secret key only when the engine is in Idle.
+ for (int i = 0; i < 8; i++) begin
+ if (reg2hw.key[7-i].qe) begin
+ secret_key[32*i+:32] <= reg2hw.key[7-i].q;
+ end
+ end
+ end
+ end
+
+ for (genvar i = 0; i < 8; i++) begin : gen_key_digest
+ assign hw2reg.key[7-i].d = '0;
+ // digest
+ assign hw2reg.digest[i].d = conv_endian(digest[i], digest_swap);
+ end
+
+ logic [3:0] unused_cfg_qe;
+
+ assign unused_cfg_qe = {cfg_reg.sha_en.qe, cfg_reg.hmac_en.qe,
+ cfg_reg.endian_swap.qe, cfg_reg.digest_swap.qe};
+
+ assign sha_en = cfg_reg.sha_en.q;
+ assign hmac_en = cfg_reg.hmac_en.q;
+ assign endian_swap = cfg_reg.endian_swap.q;
+ assign digest_swap = cfg_reg.digest_swap.q;
+ assign hw2reg.cfg.hmac_en.d = cfg_reg.hmac_en.q;
+ assign hw2reg.cfg.sha_en.d = cfg_reg.sha_en.q;
+ assign hw2reg.cfg.endian_swap.d = cfg_reg.endian_swap.q;
+ assign hw2reg.cfg.digest_swap.d = cfg_reg.digest_swap.q;
+
+ assign reg_hash_start = reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q;
+ assign reg_hash_process = reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q;
+
+ // Error code register
+ assign hw2reg.err_code.de = err_valid;
+ assign hw2reg.err_code.d = err_code;
+
+ /////////////////////
+ // Control signals //
+ /////////////////////
+ assign hash_start = reg_hash_start & sha_en & ~cfg_block;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ cfg_block <= '0;
+ end else if (hash_start) begin
+ cfg_block <= 1'b1;
+ end else if (reg_hash_done) begin
+ cfg_block <= 1'b0;
+ end
+ end
+ // Hold the configuration during the process
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ cfg_reg <= '{endian_swap: '{q: 1'b1, qe: 1'b0}, default:'0};
+ end else if (!cfg_block && reg2hw.cfg.hmac_en.qe) begin
+ cfg_reg <= reg2hw.cfg ;
+ end
+ end
+
+ // Open up the MSG_FIFO from the TL-UL port when it is ready
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ msg_allowed <= '0;
+ end else if (hash_start) begin
+ msg_allowed <= 1'b1;
+ end else if (packer_flush_done) begin
+ msg_allowed <= 1'b0;
+ end
+ end
+ ////////////////
+ // Interrupts //
+ ////////////////
+ logic fifo_empty_q, fifo_empty_event;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_empty_q <= '1; // By default, it is empty
+ end else if (!hmac_fifo_wsel) begin
+ fifo_empty_q <= fifo_empty;
+ end
+ end
+ assign fifo_empty_event = fifo_empty & ~fifo_empty_q;
+
+ logic [2:0] event_intr;
+ assign event_intr = {err_valid, fifo_empty_event, reg_hash_done};
+
+ // instantiate interrupt hardware primitive
+ prim_intr_hw #(.Width(1)) intr_hw_hmac_done (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (event_intr[0]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.hmac_done.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.hmac_done.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.hmac_done.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.hmac_done.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.hmac_done.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.hmac_done.d),
+ .intr_o (intr_hmac_done_o)
+ );
+ prim_intr_hw #(.Width(1)) intr_hw_fifo_empty (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (event_intr[1]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.fifo_empty.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.fifo_empty.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.fifo_empty.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.fifo_empty.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.fifo_empty.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.fifo_empty.d),
+ .intr_o (intr_fifo_empty_o)
+ );
+ prim_intr_hw #(.Width(1)) intr_hw_hmac_err (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (event_intr[2]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.hmac_err.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.hmac_err.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.hmac_err.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.hmac_err.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.hmac_err.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.hmac_err.d),
+ .intr_o (intr_hmac_err_o)
+ );
+
+ ///////////////
+ // Instances //
+ ///////////////
+
+ assign msg_fifo_rvalid = msg_fifo_req & ~msg_fifo_we;
+ assign msg_fifo_rdata = '1; // Return all F
+ assign msg_fifo_rerror = '1; // Return error for read access
+ assign msg_fifo_gnt = msg_fifo_req & ~hmac_fifo_wsel & packer_ready;
+
+ // FIFO control
+ sha_fifo_t reg_fifo_wentry;
+ assign reg_fifo_wentry.data = conv_endian(reg_fifo_wdata, 1'b1); // always convert
+ assign reg_fifo_wentry.mask = {reg_fifo_wmask[0], reg_fifo_wmask[8],
+ reg_fifo_wmask[16], reg_fifo_wmask[24]};
+ assign fifo_full = ~fifo_wready;
+ assign fifo_empty = ~fifo_rvalid;
+ assign fifo_wvalid = (hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid;
+ assign fifo_wdata = (hmac_fifo_wsel) ? '{data: digest[hmac_fifo_wdata_sel], mask: '1}
+ : reg_fifo_wentry;
+
+ prim_fifo_sync #(
+ .Width ($bits(sha_fifo_t)),
+ .Pass (1'b1),
+ .Depth (MsgFifoDepth)
+ ) u_msg_fifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0),
+
+ .wvalid(fifo_wvalid & sha_en),
+ .wready(fifo_wready),
+ .wdata (fifo_wdata),
+
+ .depth (fifo_depth),
+
+ .rvalid(fifo_rvalid),
+ .rready(fifo_rready),
+ .rdata(fifo_rdata)
+ );
+
+ // TL ADAPTER SRAM
+ tlul_adapter_sram #(
+ .SramAw (9),
+ .SramDw (32),
+ .Outstanding (1),
+ .ByteAccess (1),
+ .ErrOnRead (1)
+ ) u_tlul_adapter (
+ .clk_i,
+ .rst_ni,
+ .tl_i (tl_win_h2d),
+ .tl_o (tl_win_d2h),
+ .req_o (msg_fifo_req ),
+ .gnt_i (msg_fifo_gnt ),
+ .we_o (msg_fifo_we ),
+ .addr_o ( ), // Doesn't care the address other than sub-word
+ .wdata_o (msg_fifo_wdata ),
+ .wmask_o (msg_fifo_wmask ),
+ .rdata_i (msg_fifo_rdata ),
+ .rvalid_i (msg_fifo_rvalid),
+ .rerror_i (msg_fifo_rerror)
+ );
+
+ // TL-UL to MSG_FIFO byte write handling
+ logic msg_write;
+
+ assign msg_write = msg_fifo_req & msg_fifo_we & ~hmac_fifo_wsel & msg_allowed;
+
+ logic [$clog2(32+1)-1:0] wmask_ones;
+
+ always_comb begin
+ wmask_ones = '0;
+ for (int i = 0 ; i < 32 ; i++) begin
+ wmask_ones = wmask_ones + msg_fifo_wmask[i];
+ end
+ end
+
+ // Calculate written message
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ message_length <= '0;
+ end else if (hash_start) begin
+ message_length <= '0;
+ end else if (msg_write && sha_en && packer_ready) begin
+ message_length <= message_length + 64'(wmask_ones);
+ end
+ end
+
+ assign hw2reg.msg_length_upper.de = 1'b1;
+ assign hw2reg.msg_length_upper.d = message_length[63:32];
+ assign hw2reg.msg_length_lower.de = 1'b1;
+ assign hw2reg.msg_length_lower.d = message_length[31:0];
+
+
+ // Convert endian here
+ // prim_packer always packs to the right, but SHA engine assumes incoming
+ // to be big-endian, [31:24] comes first. So, the data is reverted after
+ // prim_packer before the message fifo. here to reverse if not big-endian
+ // before pushing to the packer.
+ assign msg_fifo_wdata_endian = conv_endian(msg_fifo_wdata, ~endian_swap);
+ assign msg_fifo_wmask_endian = conv_endian(msg_fifo_wmask, ~endian_swap);
+
+ prim_packer #(
+ .InW (32),
+ .OutW (32)
+ ) u_packer (
+ .clk_i,
+ .rst_ni,
+
+ .valid_i (msg_write & sha_en),
+ .data_i (msg_fifo_wdata_endian),
+ .mask_i (msg_fifo_wmask_endian),
+ .ready_o (packer_ready),
+
+ .valid_o (reg_fifo_wvalid),
+ .data_o (reg_fifo_wdata),
+ .mask_o (reg_fifo_wmask),
+ .ready_i (fifo_wready & ~hmac_fifo_wsel),
+
+ .flush_i (reg_hash_process),
+ .flush_done_o (packer_flush_done) // ignore at this moment
+ );
+
+
+ hmac_core u_hmac (
+ .clk_i,
+ .rst_ni,
+
+ .secret_key,
+
+ .wipe_secret,
+ .wipe_v,
+
+ .hmac_en,
+
+ .reg_hash_start (hash_start),
+ .reg_hash_process (packer_flush_done), // Trigger after all msg written
+ .hash_done (reg_hash_done),
+ .sha_hash_start,
+ .sha_hash_process,
+ .sha_hash_done,
+
+ .sha_rvalid (shaf_rvalid),
+ .sha_rdata (shaf_rdata),
+ .sha_rready (shaf_rready),
+
+ .fifo_rvalid,
+ .fifo_rdata,
+ .fifo_rready,
+
+ .fifo_wsel (hmac_fifo_wsel),
+ .fifo_wvalid (hmac_fifo_wvalid),
+ .fifo_wdata_sel (hmac_fifo_wdata_sel),
+ .fifo_wready,
+
+ .message_length,
+ .sha_message_length,
+
+ .idle (hmac_core_idle)
+ );
+
+ sha2 u_sha2 (
+ .clk_i,
+ .rst_ni,
+
+ .wipe_secret,
+ .wipe_v,
+
+ .fifo_rvalid (shaf_rvalid),
+ .fifo_rdata (shaf_rdata),
+ .fifo_rready (shaf_rready),
+
+ .sha_en,
+ .hash_start (sha_hash_start),
+ .hash_process (sha_hash_process),
+ .hash_done (sha_hash_done),
+
+ .message_length (sha_message_length),
+
+ .digest,
+
+ .idle (sha_core_idle)
+ );
+
+ // Register top
+ logic [NumAlerts-1:0] alert_test, alerts;
+ hmac_reg_top u_reg (
+ .clk_i,
+ .rst_ni,
+
+ .tl_i,
+ .tl_o,
+
+ .tl_win_o (tl_win_h2d),
+ .tl_win_i (tl_win_d2h),
+
+ .reg2hw,
+ .hw2reg,
+
+ // SEC_CM: BUS.INTEGRITY
+ .intg_err_o (alerts[0]),
+ .devmode_i (1'b1)
+ );
+
+ // Alerts
+ assign alert_test = {
+ reg2hw.alert_test.q &
+ reg2hw.alert_test.qe
+ };
+
+ for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[i]),
+ .IsFatal(i)
+ ) u_prim_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_req_i ( alerts[0] ),
+ .alert_ack_o ( ),
+ .alert_rx_i ( alert_rx_i[i] ),
+ .alert_tx_o ( alert_tx_o[i] )
+ );
+ end
+
+ /////////////////////////
+ // HMAC Error Handling //
+ /////////////////////////
+ logic msg_push_sha_disabled, hash_start_sha_disabled, update_seckey_inprocess;
+ logic hash_start_active; // `reg_hash_start` set when hash already in active
+ logic msg_push_not_allowed; // Message is received when `hash_start` isn't set
+ assign msg_push_sha_disabled = msg_write & ~sha_en;
+ assign hash_start_sha_disabled = reg_hash_start & ~sha_en;
+ assign hash_start_active = reg_hash_start & cfg_block;
+ assign msg_push_not_allowed = msg_fifo_req & ~msg_allowed;
+
+ always_comb begin
+ update_seckey_inprocess = 1'b0;
+ if (cfg_block) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ if (reg2hw.key[i].qe) begin
+ update_seckey_inprocess = update_seckey_inprocess | 1'b1;
+ end
+ end
+ end else begin
+ update_seckey_inprocess = 1'b0;
+ end
+ end
+
+ // Update ERR_CODE register and interrupt only when no pending interrupt.
+ // This ensures only the first event of the series of events can be seen to sw.
+ // It is recommended that the software reads ERR_CODE register when interrupt
+ // is pending to avoid any race conditions.
+ assign err_valid = ~reg2hw.intr_state.hmac_err.q &
+ ( msg_push_sha_disabled | hash_start_sha_disabled
+ | update_seckey_inprocess | hash_start_active
+ | msg_push_not_allowed );
+
+ always_comb begin
+ err_code = NoError;
+ unique case (1'b1)
+ msg_push_sha_disabled: begin
+ err_code = SwPushMsgWhenShaDisabled;
+ end
+ hash_start_sha_disabled: begin
+ err_code = SwHashStartWhenShaDisabled;
+ end
+
+ update_seckey_inprocess: begin
+ err_code = SwUpdateSecretKeyInProcess;
+ end
+
+ hash_start_active: begin
+ err_code = SwHashStartWhenActive;
+ end
+
+ msg_push_not_allowed: begin
+ err_code = SwPushMsgWhenDisallowed;
+ end
+
+ default: begin
+ err_code = NoError;
+ end
+ endcase
+ end
+
+ /////////////////////
+ // Unused Signals //
+ /////////////////////
+ logic unused_wmask;
+ assign unused_wmask = ^reg_fifo_wmask;
+
+ /////////////////////
+ // Idle output //
+ /////////////////////
+ // TBD this should be connected later
+ // Idle: AND condition of:
+ // - packer empty: Currently no way to guarantee the packer is empty.
+ // temporary, the logic uses packer output (reg_fifo_wvalid)
+ // - MSG_FIFO --> fifo_rvalid
+ // - HMAC_CORE --> hmac_core_idle
+ // - SHA2_CORE --> sha_core_idle
+ // - Clean interrupt status
+ logic idle;
+ assign idle = !reg_fifo_wvalid && !fifo_rvalid
+ && hmac_core_idle && sha_core_idle;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ idle_o <= 1'b1;
+ end else begin
+ idle_o <= idle;
+ end
+ end
+
+
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_core.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_core.sv
new file mode 100644
index 00000000..823d318d
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_core.sv
@@ -0,0 +1,315 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// HMAC Core implementation
+
+module hmac_core import hmac_pkg::*; (
+ input clk_i,
+ input rst_ni,
+
+ input [255:0] secret_key, // {word0, word1, ..., word7}
+
+ input wipe_secret,
+ input [31:0] wipe_v,
+
+ input hmac_en,
+
+ input reg_hash_start,
+ input reg_hash_process,
+ output logic hash_done,
+ output logic sha_hash_start,
+ output logic sha_hash_process,
+ input sha_hash_done,
+
+ // fifo
+ output logic sha_rvalid,
+ output sha_fifo_t sha_rdata,
+ input sha_rready,
+
+ input fifo_rvalid,
+ input sha_fifo_t fifo_rdata,
+ output logic fifo_rready,
+
+ // fifo control (select and fifo write data)
+ output logic fifo_wsel, // 0: from reg, 1: from digest
+ output logic fifo_wvalid,
+ output logic [2:0] fifo_wdata_sel, // 0: digest[0] .. 7: digest[7]
+ input fifo_wready,
+
+ input [63:0] message_length,
+ output [63:0] sha_message_length,
+
+ output logic idle
+);
+
+ localparam int unsigned BlockSize = 512;
+ localparam int unsigned BlockSizeBits = $clog2(BlockSize);
+ localparam int unsigned HashWordBits = $clog2($bits(sha_word_t));
+
+ localparam bit [63:0] BlockSize64 = 64'(BlockSize);
+ localparam bit [BlockSizeBits:0] BlockSizeBSB = BlockSize[BlockSizeBits:0];
+
+ logic hash_start; // generated from internal state machine
+ logic hash_process; // generated from internal state machine to trigger hash
+ logic hmac_hash_done;
+
+ logic [BlockSize-1:0] i_pad ;
+ logic [BlockSize-1:0] o_pad ;
+
+ logic [63:0] txcount;
+ logic [BlockSizeBits-HashWordBits-1:0] pad_index;
+ logic clr_txcount, inc_txcount;
+
+ logic hmac_sha_rvalid;
+
+ typedef enum logic [1:0] {
+ SelIPad,
+ SelOPad,
+ SelFifo
+ } sel_rdata_t;
+
+ sel_rdata_t sel_rdata;
+
+ typedef enum logic {
+ SelIPadMsg,
+ SelOPadMsg
+ } sel_msglen_t;
+
+ sel_msglen_t sel_msglen;
+
+ typedef enum logic {
+ Inner, // Update when state goes to StIPad
+ Outer // Update when state enters StOPad
+ } round_t ;
+
+ logic update_round ;
+ round_t round_q, round_d;
+
+ typedef enum logic [2:0] {
+ StIdle,
+ StIPad,
+ StMsg, // Actual Msg, and Digest both
+ StPushToMsgFifo, // Digest --> Msg Fifo
+ StWaitResp, // Hash done( by checking processed_length? or hash_done)
+ StOPad,
+ StDone // hmac_done
+ } st_e ;
+
+ st_e st_q, st_d;
+
+ logic clr_fifo_wdata_sel;
+ logic txcnt_eq_blksz ;
+
+ logic reg_hash_process_flag;
+
+ assign sha_hash_start = (hmac_en) ? hash_start : reg_hash_start ;
+ assign sha_hash_process = (hmac_en) ? reg_hash_process | hash_process : reg_hash_process ;
+ assign hash_done = (hmac_en) ? hmac_hash_done : sha_hash_done ;
+
+ assign pad_index = txcount[BlockSizeBits-1:HashWordBits];
+
+ assign i_pad = {secret_key, {(BlockSize-256){1'b0}}} ^ {(BlockSize/8){8'h36}};
+ assign o_pad = {secret_key, {(BlockSize-256){1'b0}}} ^ {(BlockSize/8){8'h5c}};
+
+
+ assign fifo_rready = (hmac_en) ? (st_q == StMsg) & sha_rready : sha_rready ;
+ // sha_rvalid is controlled by State Machine below.
+ assign sha_rvalid = (!hmac_en) ? fifo_rvalid : hmac_sha_rvalid ;
+ assign sha_rdata =
+ (!hmac_en) ? fifo_rdata :
+ (sel_rdata == SelIPad) ? '{data: i_pad[(BlockSize-1)-32*pad_index-:32], mask: '1} :
+ (sel_rdata == SelOPad) ? '{data: o_pad[(BlockSize-1)-32*pad_index-:32], mask: '1} :
+ (sel_rdata == SelFifo) ? fifo_rdata :
+ '{default: '0};
+
+ assign sha_message_length = (!hmac_en) ? message_length :
+ (sel_msglen == SelIPadMsg) ? message_length + BlockSize64 :
+ (sel_msglen == SelOPadMsg) ? BlockSize64 + 64'd256 :
+ '0 ;
+
+ assign txcnt_eq_blksz = (txcount[BlockSizeBits:0] == BlockSizeBSB);
+
+ assign inc_txcount = sha_rready && sha_rvalid;
+
+ // txcount
+ // Looks like txcount can be removed entirely here in hmac_core
+ // In the first round (InnerPaddedKey), it can just watch process and hash_done
+ // In the second round, it only needs count 256 bits for hash digest to trigger
+ // hash_process to SHA2
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ txcount <= '0;
+ end else if (clr_txcount) begin
+ txcount <= '0;
+ end else if (inc_txcount) begin
+ txcount[63:5] <= txcount[63:5] + 1'b1;
+ end
+ end
+
+ // reg_hash_process trigger logic
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ reg_hash_process_flag <= 1'b0;
+ end else if (reg_hash_process) begin
+ reg_hash_process_flag <= 1'b1;
+ end else if (hmac_hash_done || reg_hash_start) begin
+ reg_hash_process_flag <= 1'b0;
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ round_q <= Inner;
+ end else if (update_round) begin
+ round_q <= round_d;
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_wdata_sel <= 3'h0;
+ end else if (clr_fifo_wdata_sel) begin
+ fifo_wdata_sel <= 3'h0;
+ end else if (fifo_wsel && fifo_wvalid) begin
+ fifo_wdata_sel <= fifo_wdata_sel + 1'b1;
+ end
+ end
+
+ assign sel_msglen = (round_q == Inner) ? SelIPadMsg : SelOPadMsg ;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : state_ff
+ if (!rst_ni) st_q <= StIdle;
+ else st_q <= st_d;
+ end
+
+ always_comb begin : next_state
+ hmac_hash_done = 1'b0;
+ hmac_sha_rvalid = 1'b0;
+
+ clr_txcount = 1'b0;
+
+ update_round = 1'b0;
+ round_d = Inner;
+
+ fifo_wsel = 1'b0; // from register
+ fifo_wvalid = 1'b0;
+
+ clr_fifo_wdata_sel = 1'b1;
+
+ sel_rdata = SelFifo;
+
+ hash_start = 1'b0;
+ hash_process = 1'b0;
+
+ unique case (st_q)
+ StIdle: begin
+ if (hmac_en && reg_hash_start) begin
+ st_d = StIPad;
+
+ clr_txcount = 1'b1;
+ update_round = 1'b1;
+ round_d = Inner;
+ hash_start = 1'b1;
+ end else begin
+ st_d = StIdle;
+ end
+ end
+
+ StIPad: begin
+ sel_rdata = SelIPad;
+
+ if (txcnt_eq_blksz) begin
+ st_d = StMsg;
+
+ hmac_sha_rvalid = 1'b0; // block new read request
+ end else begin
+ st_d = StIPad;
+
+ hmac_sha_rvalid = 1'b1;
+ end
+ end
+
+ StMsg: begin
+ sel_rdata = SelFifo;
+ fifo_wsel = (round_q == Outer);
+
+ if ( (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
+ && (txcount >= sha_message_length)) begin
+ st_d = StWaitResp;
+
+ hmac_sha_rvalid = 1'b0; // block
+ hash_process = (round_q == Outer);
+ end else begin
+ st_d = StMsg;
+
+ hmac_sha_rvalid = fifo_rvalid;
+ end
+ end
+
+ StWaitResp: begin
+ hmac_sha_rvalid = 1'b0;
+
+ if (sha_hash_done) begin
+ if (round_q == Outer) begin
+ st_d = StDone;
+ end else begin // round_q == Inner
+ st_d = StPushToMsgFifo;
+ end
+ end else begin
+ st_d = StWaitResp;
+ end
+ end
+
+ StPushToMsgFifo: begin
+ hmac_sha_rvalid = 1'b0;
+ fifo_wsel = 1'b1;
+ fifo_wvalid = 1'b1;
+ clr_fifo_wdata_sel = 1'b0;
+
+ if (fifo_wready && fifo_wdata_sel == 3'h7) begin
+ st_d = StOPad;
+
+ clr_txcount = 1'b1;
+ update_round = 1'b1;
+ round_d = Outer;
+ hash_start = 1'b1;
+ end else begin
+ st_d = StPushToMsgFifo;
+
+ end
+ end
+
+ StOPad: begin
+ sel_rdata = SelOPad;
+ fifo_wsel = 1'b1; // Remained HMAC select to indicate HMAC is in second stage
+
+ if (txcnt_eq_blksz) begin
+ st_d = StMsg;
+
+ hmac_sha_rvalid = 1'b0; // block new read request
+ end else begin
+ st_d = StOPad;
+
+ hmac_sha_rvalid = 1'b1;
+ end
+ end
+
+ StDone: begin
+ // raise interrupt (hash_done)
+ st_d = StIdle;
+
+ hmac_hash_done = 1'b1;
+ end
+
+ default: begin
+ st_d = StIdle;
+ end
+
+ endcase
+ end
+
+ // Idle: Idle in HMAC_CORE only represents the idle status when hmac mode is
+ // set. If hmac_en is 0, this logic sends the idle signal always.
+ assign idle = (st_q == StIdle) && !reg_hash_start;
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_pkg.sv
new file mode 100644
index 00000000..4a55eaaf
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_pkg.sv
@@ -0,0 +1,98 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package hmac_pkg;
+
+ localparam int MsgFifoDepth = 16;
+
+ localparam int NumRound = 64; // SHA-224, SHA-256
+
+ typedef logic [31:0] sha_word_t;
+ localparam int WordByte = $bits(sha_word_t)/8;
+
+ typedef struct packed {
+ sha_word_t data;
+ logic [WordByte-1:0] mask;
+ } sha_fifo_t;
+
+
+ localparam sha_word_t InitHash [8]= '{
+ 32'h6a09_e667, 32'hbb67_ae85, 32'h3c6e_f372, 32'ha54f_f53a,
+ 32'h510e_527f, 32'h9b05_688c, 32'h1f83_d9ab, 32'h5be0_cd19
+ };
+
+ localparam sha_word_t CubicRootPrime [64] = '{
+ 32'h428a_2f98, 32'h7137_4491, 32'hb5c0_fbcf, 32'he9b5_dba5,
+ 32'h3956_c25b, 32'h59f1_11f1, 32'h923f_82a4, 32'hab1c_5ed5,
+ 32'hd807_aa98, 32'h1283_5b01, 32'h2431_85be, 32'h550c_7dc3,
+ 32'h72be_5d74, 32'h80de_b1fe, 32'h9bdc_06a7, 32'hc19b_f174,
+ 32'he49b_69c1, 32'hefbe_4786, 32'h0fc1_9dc6, 32'h240c_a1cc,
+ 32'h2de9_2c6f, 32'h4a74_84aa, 32'h5cb0_a9dc, 32'h76f9_88da,
+ 32'h983e_5152, 32'ha831_c66d, 32'hb003_27c8, 32'hbf59_7fc7,
+ 32'hc6e0_0bf3, 32'hd5a7_9147, 32'h06ca_6351, 32'h1429_2967,
+ 32'h27b7_0a85, 32'h2e1b_2138, 32'h4d2c_6dfc, 32'h5338_0d13,
+ 32'h650a_7354, 32'h766a_0abb, 32'h81c2_c92e, 32'h9272_2c85,
+ 32'ha2bf_e8a1, 32'ha81a_664b, 32'hc24b_8b70, 32'hc76c_51a3,
+ 32'hd192_e819, 32'hd699_0624, 32'hf40e_3585, 32'h106a_a070,
+ 32'h19a4_c116, 32'h1e37_6c08, 32'h2748_774c, 32'h34b0_bcb5,
+ 32'h391c_0cb3, 32'h4ed8_aa4a, 32'h5b9c_ca4f, 32'h682e_6ff3,
+ 32'h748f_82ee, 32'h78a5_636f, 32'h84c8_7814, 32'h8cc7_0208,
+ 32'h90be_fffa, 32'ha450_6ceb, 32'hbef9_a3f7, 32'hc671_78f2
+ };
+
+ function automatic sha_word_t conv_endian( input sha_word_t v, input logic swap);
+ sha_word_t conv_data = {<<8{v}};
+ conv_endian = (swap) ? conv_data : v ;
+ endfunction : conv_endian
+
+ function automatic sha_word_t rotr( input sha_word_t v , input int amt );
+ rotr = (v >> amt) | (v << (32-amt));
+ endfunction : rotr
+
+ function automatic sha_word_t shiftr( input sha_word_t v, input int amt );
+ shiftr = (v >> amt);
+ endfunction : shiftr
+
+ function automatic sha_word_t [7:0] compress( input sha_word_t w, input sha_word_t k,
+ input sha_word_t [7:0] h_i);
+ automatic sha_word_t sigma_0, sigma_1, ch, maj, temp1, temp2;
+
+ sigma_1 = rotr(h_i[4], 6) ^ rotr(h_i[4], 11) ^ rotr(h_i[4], 25);
+ ch = (h_i[4] & h_i[5]) ^ (~h_i[4] & h_i[6]);
+ temp1 = (h_i[7] + sigma_1 + ch + k + w);
+ sigma_0 = rotr(h_i[0], 2) ^ rotr(h_i[0], 13) ^ rotr(h_i[0], 22);
+ maj = (h_i[0] & h_i[1]) ^ (h_i[0] & h_i[2]) ^ (h_i[1] & h_i[2]);
+ temp2 = (sigma_0 + maj);
+
+ compress[7] = h_i[6]; // h = g
+ compress[6] = h_i[5]; // g = f
+ compress[5] = h_i[4]; // f = e
+ compress[4] = h_i[3] + temp1; // e = (d + temp1)
+ compress[3] = h_i[2]; // d = c
+ compress[2] = h_i[1]; // c = b
+ compress[1] = h_i[0]; // b = a
+ compress[0] = (temp1 + temp2); // a = (temp1 + temp2)
+ endfunction : compress
+
+ function automatic sha_word_t calc_w(input sha_word_t w_0,
+ input sha_word_t w_1,
+ input sha_word_t w_9,
+ input sha_word_t w_14);
+ automatic sha_word_t sum0, sum1;
+ sum0 = rotr(w_1, 7) ^ rotr(w_1, 18) ^ shiftr(w_1, 3);
+ sum1 = rotr(w_14, 17) ^ rotr(w_14, 19) ^ shiftr(w_14, 10);
+ calc_w = w_0 + sum0 + w_9 + sum1;
+ endfunction : calc_w
+
+ typedef enum logic [31:0] {
+ NoError = 32'h0000_0000,
+ SwPushMsgWhenShaDisabled = 32'h0000_0001,
+ SwHashStartWhenShaDisabled = 32'h0000_0002,
+ SwUpdateSecretKeyInProcess = 32'h0000_0003,
+ SwHashStartWhenActive = 32'h0000_0004,
+ SwPushMsgWhenDisallowed = 32'h0000_0005
+ } err_code_e;
+
+endpackage : hmac_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_reg_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_reg_pkg.sv
new file mode 100644
index 00000000..16af8747
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_reg_pkg.sv
@@ -0,0 +1,320 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package hmac_reg_pkg;
+
+ // Param list
+ parameter int NumWords = 8;
+ parameter int NumAlerts = 1;
+
+ // Address widths within the block
+ parameter int BlockAw = 12;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } hmac_done;
+ struct packed {
+ logic q;
+ } fifo_empty;
+ struct packed {
+ logic q;
+ } hmac_err;
+ } hmac_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } hmac_done;
+ struct packed {
+ logic q;
+ } fifo_empty;
+ struct packed {
+ logic q;
+ } hmac_err;
+ } hmac_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } hmac_done;
+ struct packed {
+ logic q;
+ logic qe;
+ } fifo_empty;
+ struct packed {
+ logic q;
+ logic qe;
+ } hmac_err;
+ } hmac_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } hmac_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } hmac_en;
+ struct packed {
+ logic q;
+ logic qe;
+ } sha_en;
+ struct packed {
+ logic q;
+ logic qe;
+ } endian_swap;
+ struct packed {
+ logic q;
+ logic qe;
+ } digest_swap;
+ } hmac_reg2hw_cfg_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } hash_start;
+ struct packed {
+ logic q;
+ logic qe;
+ } hash_process;
+ } hmac_reg2hw_cmd_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ logic qe;
+ } hmac_reg2hw_wipe_secret_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ logic qe;
+ } hmac_reg2hw_key_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } hmac_done;
+ struct packed {
+ logic d;
+ logic de;
+ } fifo_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } hmac_err;
+ } hmac_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ } hmac_en;
+ struct packed {
+ logic d;
+ } sha_en;
+ struct packed {
+ logic d;
+ } endian_swap;
+ struct packed {
+ logic d;
+ } digest_swap;
+ } hmac_hw2reg_cfg_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ } fifo_empty;
+ struct packed {
+ logic d;
+ } fifo_full;
+ struct packed {
+ logic [4:0] d;
+ } fifo_depth;
+ } hmac_hw2reg_status_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ logic de;
+ } hmac_hw2reg_err_code_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } hmac_hw2reg_key_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } hmac_hw2reg_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ logic de;
+ } hmac_hw2reg_msg_length_lower_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ logic de;
+ } hmac_hw2reg_msg_length_upper_reg_t;
+
+ // Register -> HW type
+ typedef struct packed {
+ hmac_reg2hw_intr_state_reg_t intr_state; // [322:320]
+ hmac_reg2hw_intr_enable_reg_t intr_enable; // [319:317]
+ hmac_reg2hw_intr_test_reg_t intr_test; // [316:311]
+ hmac_reg2hw_alert_test_reg_t alert_test; // [310:309]
+ hmac_reg2hw_cfg_reg_t cfg; // [308:301]
+ hmac_reg2hw_cmd_reg_t cmd; // [300:297]
+ hmac_reg2hw_wipe_secret_reg_t wipe_secret; // [296:264]
+ hmac_reg2hw_key_mreg_t [7:0] key; // [263:0]
+ } hmac_reg2hw_t;
+
+ // HW -> register type
+ typedef struct packed {
+ hmac_hw2reg_intr_state_reg_t intr_state; // [627:622]
+ hmac_hw2reg_cfg_reg_t cfg; // [621:618]
+ hmac_hw2reg_status_reg_t status; // [617:611]
+ hmac_hw2reg_err_code_reg_t err_code; // [610:578]
+ hmac_hw2reg_key_mreg_t [7:0] key; // [577:322]
+ hmac_hw2reg_digest_mreg_t [7:0] digest; // [321:66]
+ hmac_hw2reg_msg_length_lower_reg_t msg_length_lower; // [65:33]
+ hmac_hw2reg_msg_length_upper_reg_t msg_length_upper; // [32:0]
+ } hmac_hw2reg_t;
+
+ // Register offsets
+ parameter logic [BlockAw-1:0] HMAC_INTR_STATE_OFFSET = 12'h0;
+ parameter logic [BlockAw-1:0] HMAC_INTR_ENABLE_OFFSET = 12'h4;
+ parameter logic [BlockAw-1:0] HMAC_INTR_TEST_OFFSET = 12'h8;
+ parameter logic [BlockAw-1:0] HMAC_ALERT_TEST_OFFSET = 12'hc;
+ parameter logic [BlockAw-1:0] HMAC_CFG_OFFSET = 12'h10;
+ parameter logic [BlockAw-1:0] HMAC_CMD_OFFSET = 12'h14;
+ parameter logic [BlockAw-1:0] HMAC_STATUS_OFFSET = 12'h18;
+ parameter logic [BlockAw-1:0] HMAC_ERR_CODE_OFFSET = 12'h1c;
+ parameter logic [BlockAw-1:0] HMAC_WIPE_SECRET_OFFSET = 12'h20;
+ parameter logic [BlockAw-1:0] HMAC_KEY_0_OFFSET = 12'h24;
+ parameter logic [BlockAw-1:0] HMAC_KEY_1_OFFSET = 12'h28;
+ parameter logic [BlockAw-1:0] HMAC_KEY_2_OFFSET = 12'h2c;
+ parameter logic [BlockAw-1:0] HMAC_KEY_3_OFFSET = 12'h30;
+ parameter logic [BlockAw-1:0] HMAC_KEY_4_OFFSET = 12'h34;
+ parameter logic [BlockAw-1:0] HMAC_KEY_5_OFFSET = 12'h38;
+ parameter logic [BlockAw-1:0] HMAC_KEY_6_OFFSET = 12'h3c;
+ parameter logic [BlockAw-1:0] HMAC_KEY_7_OFFSET = 12'h40;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_0_OFFSET = 12'h44;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_1_OFFSET = 12'h48;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_2_OFFSET = 12'h4c;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_3_OFFSET = 12'h50;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_4_OFFSET = 12'h54;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_5_OFFSET = 12'h58;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_6_OFFSET = 12'h5c;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_7_OFFSET = 12'h60;
+ parameter logic [BlockAw-1:0] HMAC_MSG_LENGTH_LOWER_OFFSET = 12'h64;
+ parameter logic [BlockAw-1:0] HMAC_MSG_LENGTH_UPPER_OFFSET = 12'h68;
+
+ // Reset values for hwext registers and their fields
+ parameter logic [2:0] HMAC_INTR_TEST_RESVAL = 3'h0;
+ parameter logic [0:0] HMAC_INTR_TEST_HMAC_DONE_RESVAL = 1'h0;
+ parameter logic [0:0] HMAC_INTR_TEST_FIFO_EMPTY_RESVAL = 1'h0;
+ parameter logic [0:0] HMAC_INTR_TEST_HMAC_ERR_RESVAL = 1'h0;
+ parameter logic [0:0] HMAC_ALERT_TEST_RESVAL = 1'h0;
+ parameter logic [0:0] HMAC_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h0;
+ parameter logic [3:0] HMAC_CFG_RESVAL = 4'h4;
+ parameter logic [0:0] HMAC_CFG_ENDIAN_SWAP_RESVAL = 1'h1;
+ parameter logic [0:0] HMAC_CFG_DIGEST_SWAP_RESVAL = 1'h0;
+ parameter logic [1:0] HMAC_CMD_RESVAL = 2'h0;
+ parameter logic [8:0] HMAC_STATUS_RESVAL = 9'h1;
+ parameter logic [0:0] HMAC_STATUS_FIFO_EMPTY_RESVAL = 1'h1;
+ parameter logic [31:0] HMAC_WIPE_SECRET_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_0_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_1_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_2_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_3_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_4_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_5_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_6_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_KEY_7_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_2_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_3_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_4_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_5_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_6_RESVAL = 32'h0;
+ parameter logic [31:0] HMAC_DIGEST_7_RESVAL = 32'h0;
+
+ // Window parameters
+ parameter logic [BlockAw-1:0] HMAC_MSG_FIFO_OFFSET = 12'h800;
+ parameter int unsigned HMAC_MSG_FIFO_SIZE = 'h800;
+
+ // Register index
+ typedef enum int {
+ HMAC_INTR_STATE,
+ HMAC_INTR_ENABLE,
+ HMAC_INTR_TEST,
+ HMAC_ALERT_TEST,
+ HMAC_CFG,
+ HMAC_CMD,
+ HMAC_STATUS,
+ HMAC_ERR_CODE,
+ HMAC_WIPE_SECRET,
+ HMAC_KEY_0,
+ HMAC_KEY_1,
+ HMAC_KEY_2,
+ HMAC_KEY_3,
+ HMAC_KEY_4,
+ HMAC_KEY_5,
+ HMAC_KEY_6,
+ HMAC_KEY_7,
+ HMAC_DIGEST_0,
+ HMAC_DIGEST_1,
+ HMAC_DIGEST_2,
+ HMAC_DIGEST_3,
+ HMAC_DIGEST_4,
+ HMAC_DIGEST_5,
+ HMAC_DIGEST_6,
+ HMAC_DIGEST_7,
+ HMAC_MSG_LENGTH_LOWER,
+ HMAC_MSG_LENGTH_UPPER
+ } hmac_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] HMAC_PERMIT [27] = '{
+ 4'b0001, // index[ 0] HMAC_INTR_STATE
+ 4'b0001, // index[ 1] HMAC_INTR_ENABLE
+ 4'b0001, // index[ 2] HMAC_INTR_TEST
+ 4'b0001, // index[ 3] HMAC_ALERT_TEST
+ 4'b0001, // index[ 4] HMAC_CFG
+ 4'b0001, // index[ 5] HMAC_CMD
+ 4'b0011, // index[ 6] HMAC_STATUS
+ 4'b1111, // index[ 7] HMAC_ERR_CODE
+ 4'b1111, // index[ 8] HMAC_WIPE_SECRET
+ 4'b1111, // index[ 9] HMAC_KEY_0
+ 4'b1111, // index[10] HMAC_KEY_1
+ 4'b1111, // index[11] HMAC_KEY_2
+ 4'b1111, // index[12] HMAC_KEY_3
+ 4'b1111, // index[13] HMAC_KEY_4
+ 4'b1111, // index[14] HMAC_KEY_5
+ 4'b1111, // index[15] HMAC_KEY_6
+ 4'b1111, // index[16] HMAC_KEY_7
+ 4'b1111, // index[17] HMAC_DIGEST_0
+ 4'b1111, // index[18] HMAC_DIGEST_1
+ 4'b1111, // index[19] HMAC_DIGEST_2
+ 4'b1111, // index[20] HMAC_DIGEST_3
+ 4'b1111, // index[21] HMAC_DIGEST_4
+ 4'b1111, // index[22] HMAC_DIGEST_5
+ 4'b1111, // index[23] HMAC_DIGEST_6
+ 4'b1111, // index[24] HMAC_DIGEST_7
+ 4'b1111, // index[25] HMAC_MSG_LENGTH_LOWER
+ 4'b1111 // index[26] HMAC_MSG_LENGTH_UPPER
+ };
+
+endpackage
+
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_reg_top.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_reg_top.sv
new file mode 100644
index 00000000..d1c2bfda
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/hmac_reg_top.sv
@@ -0,0 +1,1230 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+
+module hmac_reg_top (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // Output port for window
+ output tlul_pkg::tl_h2d_t tl_win_o,
+ input tlul_pkg::tl_d2h_t tl_win_i,
+
+ // To HW
+ output hmac_reg_pkg::hmac_reg2hw_t reg2hw, // Write
+ input hmac_reg_pkg::hmac_hw2reg_t hw2reg, // Read
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import hmac_reg_pkg::* ;
+
+ localparam int AW = 12;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+ logic reg_busy;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ logic intg_err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_q <= '0;
+ end else if (intg_err) begin
+ intg_err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = intg_err_q | intg_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ tlul_pkg::tl_h2d_t tl_socket_h2d [2];
+ tlul_pkg::tl_d2h_t tl_socket_d2h [2];
+
+ logic [0:0] reg_steer;
+
+ // socket_1n connection
+ assign tl_reg_h2d = tl_socket_h2d[1];
+ assign tl_socket_d2h[1] = tl_reg_d2h;
+
+ assign tl_win_o = tl_socket_h2d[0];
+ assign tl_socket_d2h[0] = tl_win_i;
+
+ // Create Socket_1n
+ tlul_socket_1n #(
+ .N (2),
+ .HReqPass (1'b1),
+ .HRspPass (1'b1),
+ .DReqPass ({2{1'b1}}),
+ .DRspPass ({2{1'b1}}),
+ .HReqDepth (4'h0),
+ .HRspDepth (4'h0),
+ .DReqDepth ({2{4'h0}}),
+ .DRspDepth ({2{4'h0}})
+ ) u_socket (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .tl_h_i (tl_i),
+ .tl_h_o (tl_o_pre),
+ .tl_d_o (tl_socket_h2d),
+ .tl_d_i (tl_socket_d2h),
+ .dev_select_i (reg_steer)
+ );
+
+ // Create steering logic
+ always_comb begin
+ unique case (tl_i.a_address[AW-1:0]) inside
+ [2048:4095]: begin
+ reg_steer = 0;
+ end
+ default: begin
+ // Default set to register
+ reg_steer = 1;
+ end
+ endcase
+
+ // Override this in case of an integrity error
+ if (intg_err) begin
+ reg_steer = 1;
+ end
+ end
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW),
+ .EnableDataIntgGen(0)
+ ) u_reg_if (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ // cdc oversampling signals
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+
+ // Define SW related signals
+ // Format: __{wd|we|qs}
+ // or _{wd|we|qs} if field == 1 or 0
+ logic intr_state_we;
+ logic intr_state_hmac_done_qs;
+ logic intr_state_hmac_done_wd;
+ logic intr_state_fifo_empty_qs;
+ logic intr_state_fifo_empty_wd;
+ logic intr_state_hmac_err_qs;
+ logic intr_state_hmac_err_wd;
+ logic intr_enable_we;
+ logic intr_enable_hmac_done_qs;
+ logic intr_enable_hmac_done_wd;
+ logic intr_enable_fifo_empty_qs;
+ logic intr_enable_fifo_empty_wd;
+ logic intr_enable_hmac_err_qs;
+ logic intr_enable_hmac_err_wd;
+ logic intr_test_we;
+ logic intr_test_hmac_done_wd;
+ logic intr_test_fifo_empty_wd;
+ logic intr_test_hmac_err_wd;
+ logic alert_test_we;
+ logic alert_test_wd;
+ logic cfg_re;
+ logic cfg_we;
+ logic cfg_hmac_en_qs;
+ logic cfg_hmac_en_wd;
+ logic cfg_sha_en_qs;
+ logic cfg_sha_en_wd;
+ logic cfg_endian_swap_qs;
+ logic cfg_endian_swap_wd;
+ logic cfg_digest_swap_qs;
+ logic cfg_digest_swap_wd;
+ logic cmd_we;
+ logic cmd_hash_start_wd;
+ logic cmd_hash_process_wd;
+ logic status_re;
+ logic status_fifo_empty_qs;
+ logic status_fifo_full_qs;
+ logic [4:0] status_fifo_depth_qs;
+ logic [31:0] err_code_qs;
+ logic wipe_secret_we;
+ logic [31:0] wipe_secret_wd;
+ logic key_0_we;
+ logic [31:0] key_0_wd;
+ logic key_1_we;
+ logic [31:0] key_1_wd;
+ logic key_2_we;
+ logic [31:0] key_2_wd;
+ logic key_3_we;
+ logic [31:0] key_3_wd;
+ logic key_4_we;
+ logic [31:0] key_4_wd;
+ logic key_5_we;
+ logic [31:0] key_5_wd;
+ logic key_6_we;
+ logic [31:0] key_6_wd;
+ logic key_7_we;
+ logic [31:0] key_7_wd;
+ logic digest_0_re;
+ logic [31:0] digest_0_qs;
+ logic digest_1_re;
+ logic [31:0] digest_1_qs;
+ logic digest_2_re;
+ logic [31:0] digest_2_qs;
+ logic digest_3_re;
+ logic [31:0] digest_3_qs;
+ logic digest_4_re;
+ logic [31:0] digest_4_qs;
+ logic digest_5_re;
+ logic [31:0] digest_5_qs;
+ logic digest_6_re;
+ logic [31:0] digest_6_qs;
+ logic digest_7_re;
+ logic [31:0] digest_7_qs;
+ logic [31:0] msg_length_lower_qs;
+ logic [31:0] msg_length_upper_qs;
+
+ // Register instances
+ // R[intr_state]: V(False)
+ // F[hmac_done]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_hmac_done (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_hmac_done_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.hmac_done.de),
+ .d (hw2reg.intr_state.hmac_done.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.hmac_done.q),
+
+ // to register interface (read)
+ .qs (intr_state_hmac_done_qs)
+ );
+
+ // F[fifo_empty]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_fifo_empty (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_fifo_empty_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.fifo_empty.de),
+ .d (hw2reg.intr_state.fifo_empty.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.fifo_empty.q),
+
+ // to register interface (read)
+ .qs (intr_state_fifo_empty_qs)
+ );
+
+ // F[hmac_err]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_hmac_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_hmac_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.hmac_err.de),
+ .d (hw2reg.intr_state.hmac_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.hmac_err.q),
+
+ // to register interface (read)
+ .qs (intr_state_hmac_err_qs)
+ );
+
+
+ // R[intr_enable]: V(False)
+ // F[hmac_done]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_hmac_done (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_hmac_done_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.hmac_done.q),
+
+ // to register interface (read)
+ .qs (intr_enable_hmac_done_qs)
+ );
+
+ // F[fifo_empty]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_fifo_empty (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_fifo_empty_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.fifo_empty.q),
+
+ // to register interface (read)
+ .qs (intr_enable_fifo_empty_qs)
+ );
+
+ // F[hmac_err]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_hmac_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_hmac_err_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.hmac_err.q),
+
+ // to register interface (read)
+ .qs (intr_enable_hmac_err_qs)
+ );
+
+
+ // R[intr_test]: V(True)
+ // F[hmac_done]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_hmac_done (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_hmac_done_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.hmac_done.qe),
+ .q (reg2hw.intr_test.hmac_done.q),
+ .qs ()
+ );
+
+ // F[fifo_empty]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_fifo_empty (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_fifo_empty_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.fifo_empty.qe),
+ .q (reg2hw.intr_test.fifo_empty.q),
+ .qs ()
+ );
+
+ // F[hmac_err]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_hmac_err (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_hmac_err_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.hmac_err.qe),
+ .q (reg2hw.intr_test.hmac_err.q),
+ .qs ()
+ );
+
+
+ // R[alert_test]: V(True)
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.alert_test.qe),
+ .q (reg2hw.alert_test.q),
+ .qs ()
+ );
+
+
+ // R[cfg]: V(True)
+ // F[hmac_en]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cfg_hmac_en (
+ .re (cfg_re),
+ .we (cfg_we),
+ .wd (cfg_hmac_en_wd),
+ .d (hw2reg.cfg.hmac_en.d),
+ .qre (),
+ .qe (reg2hw.cfg.hmac_en.qe),
+ .q (reg2hw.cfg.hmac_en.q),
+ .qs (cfg_hmac_en_qs)
+ );
+
+ // F[sha_en]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cfg_sha_en (
+ .re (cfg_re),
+ .we (cfg_we),
+ .wd (cfg_sha_en_wd),
+ .d (hw2reg.cfg.sha_en.d),
+ .qre (),
+ .qe (reg2hw.cfg.sha_en.qe),
+ .q (reg2hw.cfg.sha_en.q),
+ .qs (cfg_sha_en_qs)
+ );
+
+ // F[endian_swap]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cfg_endian_swap (
+ .re (cfg_re),
+ .we (cfg_we),
+ .wd (cfg_endian_swap_wd),
+ .d (hw2reg.cfg.endian_swap.d),
+ .qre (),
+ .qe (reg2hw.cfg.endian_swap.qe),
+ .q (reg2hw.cfg.endian_swap.q),
+ .qs (cfg_endian_swap_qs)
+ );
+
+ // F[digest_swap]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cfg_digest_swap (
+ .re (cfg_re),
+ .we (cfg_we),
+ .wd (cfg_digest_swap_wd),
+ .d (hw2reg.cfg.digest_swap.d),
+ .qre (),
+ .qe (reg2hw.cfg.digest_swap.qe),
+ .q (reg2hw.cfg.digest_swap.q),
+ .qs (cfg_digest_swap_qs)
+ );
+
+
+ // R[cmd]: V(True)
+ // F[hash_start]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cmd_hash_start (
+ .re (1'b0),
+ .we (cmd_we),
+ .wd (cmd_hash_start_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.cmd.hash_start.qe),
+ .q (reg2hw.cmd.hash_start.q),
+ .qs ()
+ );
+
+ // F[hash_process]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cmd_hash_process (
+ .re (1'b0),
+ .we (cmd_we),
+ .wd (cmd_hash_process_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.cmd.hash_process.qe),
+ .q (reg2hw.cmd.hash_process.q),
+ .qs ()
+ );
+
+
+ // R[status]: V(True)
+ // F[fifo_empty]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_fifo_empty (
+ .re (status_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.fifo_empty.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (status_fifo_empty_qs)
+ );
+
+ // F[fifo_full]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_fifo_full (
+ .re (status_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.fifo_full.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (status_fifo_full_qs)
+ );
+
+ // F[fifo_depth]: 8:4
+ prim_subreg_ext #(
+ .DW (5)
+ ) u_status_fifo_depth (
+ .re (status_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.fifo_depth.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (status_fifo_depth_qs)
+ );
+
+
+ // R[err_code]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (32'h0)
+ ) u_err_code (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.err_code.de),
+ .d (hw2reg.err_code.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (err_code_qs)
+ );
+
+
+ // R[wipe_secret]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_wipe_secret (
+ .re (1'b0),
+ .we (wipe_secret_we),
+ .wd (wipe_secret_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.wipe_secret.qe),
+ .q (reg2hw.wipe_secret.q),
+ .qs ()
+ );
+
+
+ // Subregister 0 of Multireg key
+ // R[key_0]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_0 (
+ .re (1'b0),
+ .we (key_0_we),
+ .wd (key_0_wd),
+ .d (hw2reg.key[0].d),
+ .qre (),
+ .qe (reg2hw.key[0].qe),
+ .q (reg2hw.key[0].q),
+ .qs ()
+ );
+
+
+ // Subregister 1 of Multireg key
+ // R[key_1]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_1 (
+ .re (1'b0),
+ .we (key_1_we),
+ .wd (key_1_wd),
+ .d (hw2reg.key[1].d),
+ .qre (),
+ .qe (reg2hw.key[1].qe),
+ .q (reg2hw.key[1].q),
+ .qs ()
+ );
+
+
+ // Subregister 2 of Multireg key
+ // R[key_2]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_2 (
+ .re (1'b0),
+ .we (key_2_we),
+ .wd (key_2_wd),
+ .d (hw2reg.key[2].d),
+ .qre (),
+ .qe (reg2hw.key[2].qe),
+ .q (reg2hw.key[2].q),
+ .qs ()
+ );
+
+
+ // Subregister 3 of Multireg key
+ // R[key_3]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_3 (
+ .re (1'b0),
+ .we (key_3_we),
+ .wd (key_3_wd),
+ .d (hw2reg.key[3].d),
+ .qre (),
+ .qe (reg2hw.key[3].qe),
+ .q (reg2hw.key[3].q),
+ .qs ()
+ );
+
+
+ // Subregister 4 of Multireg key
+ // R[key_4]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_4 (
+ .re (1'b0),
+ .we (key_4_we),
+ .wd (key_4_wd),
+ .d (hw2reg.key[4].d),
+ .qre (),
+ .qe (reg2hw.key[4].qe),
+ .q (reg2hw.key[4].q),
+ .qs ()
+ );
+
+
+ // Subregister 5 of Multireg key
+ // R[key_5]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_5 (
+ .re (1'b0),
+ .we (key_5_we),
+ .wd (key_5_wd),
+ .d (hw2reg.key[5].d),
+ .qre (),
+ .qe (reg2hw.key[5].qe),
+ .q (reg2hw.key[5].q),
+ .qs ()
+ );
+
+
+ // Subregister 6 of Multireg key
+ // R[key_6]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_6 (
+ .re (1'b0),
+ .we (key_6_we),
+ .wd (key_6_wd),
+ .d (hw2reg.key[6].d),
+ .qre (),
+ .qe (reg2hw.key[6].qe),
+ .q (reg2hw.key[6].q),
+ .qs ()
+ );
+
+
+ // Subregister 7 of Multireg key
+ // R[key_7]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_7 (
+ .re (1'b0),
+ .we (key_7_we),
+ .wd (key_7_wd),
+ .d (hw2reg.key[7].d),
+ .qre (),
+ .qe (reg2hw.key[7].qe),
+ .q (reg2hw.key[7].q),
+ .qs ()
+ );
+
+
+ // Subregister 0 of Multireg digest
+ // R[digest_0]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_0 (
+ .re (digest_0_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[0].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg digest
+ // R[digest_1]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_1 (
+ .re (digest_1_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[1].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg digest
+ // R[digest_2]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_2 (
+ .re (digest_2_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[2].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg digest
+ // R[digest_3]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_3 (
+ .re (digest_3_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[3].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg digest
+ // R[digest_4]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_4 (
+ .re (digest_4_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[4].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg digest
+ // R[digest_5]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_5 (
+ .re (digest_5_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[5].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg digest
+ // R[digest_6]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_6 (
+ .re (digest_6_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[6].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg digest
+ // R[digest_7]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_7 (
+ .re (digest_7_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[7].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_7_qs)
+ );
+
+
+ // R[msg_length_lower]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (32'h0)
+ ) u_msg_length_lower (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.msg_length_lower.de),
+ .d (hw2reg.msg_length_lower.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (msg_length_lower_qs)
+ );
+
+
+ // R[msg_length_upper]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (32'h0)
+ ) u_msg_length_upper (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.msg_length_upper.de),
+ .d (hw2reg.msg_length_upper.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (msg_length_upper_qs)
+ );
+
+
+
+ logic [26:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == HMAC_INTR_STATE_OFFSET);
+ addr_hit[ 1] = (reg_addr == HMAC_INTR_ENABLE_OFFSET);
+ addr_hit[ 2] = (reg_addr == HMAC_INTR_TEST_OFFSET);
+ addr_hit[ 3] = (reg_addr == HMAC_ALERT_TEST_OFFSET);
+ addr_hit[ 4] = (reg_addr == HMAC_CFG_OFFSET);
+ addr_hit[ 5] = (reg_addr == HMAC_CMD_OFFSET);
+ addr_hit[ 6] = (reg_addr == HMAC_STATUS_OFFSET);
+ addr_hit[ 7] = (reg_addr == HMAC_ERR_CODE_OFFSET);
+ addr_hit[ 8] = (reg_addr == HMAC_WIPE_SECRET_OFFSET);
+ addr_hit[ 9] = (reg_addr == HMAC_KEY_0_OFFSET);
+ addr_hit[10] = (reg_addr == HMAC_KEY_1_OFFSET);
+ addr_hit[11] = (reg_addr == HMAC_KEY_2_OFFSET);
+ addr_hit[12] = (reg_addr == HMAC_KEY_3_OFFSET);
+ addr_hit[13] = (reg_addr == HMAC_KEY_4_OFFSET);
+ addr_hit[14] = (reg_addr == HMAC_KEY_5_OFFSET);
+ addr_hit[15] = (reg_addr == HMAC_KEY_6_OFFSET);
+ addr_hit[16] = (reg_addr == HMAC_KEY_7_OFFSET);
+ addr_hit[17] = (reg_addr == HMAC_DIGEST_0_OFFSET);
+ addr_hit[18] = (reg_addr == HMAC_DIGEST_1_OFFSET);
+ addr_hit[19] = (reg_addr == HMAC_DIGEST_2_OFFSET);
+ addr_hit[20] = (reg_addr == HMAC_DIGEST_3_OFFSET);
+ addr_hit[21] = (reg_addr == HMAC_DIGEST_4_OFFSET);
+ addr_hit[22] = (reg_addr == HMAC_DIGEST_5_OFFSET);
+ addr_hit[23] = (reg_addr == HMAC_DIGEST_6_OFFSET);
+ addr_hit[24] = (reg_addr == HMAC_DIGEST_7_OFFSET);
+ addr_hit[25] = (reg_addr == HMAC_MSG_LENGTH_LOWER_OFFSET);
+ addr_hit[26] = (reg_addr == HMAC_MSG_LENGTH_UPPER_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = (reg_we &
+ ((addr_hit[ 0] & (|(HMAC_PERMIT[ 0] & ~reg_be))) |
+ (addr_hit[ 1] & (|(HMAC_PERMIT[ 1] & ~reg_be))) |
+ (addr_hit[ 2] & (|(HMAC_PERMIT[ 2] & ~reg_be))) |
+ (addr_hit[ 3] & (|(HMAC_PERMIT[ 3] & ~reg_be))) |
+ (addr_hit[ 4] & (|(HMAC_PERMIT[ 4] & ~reg_be))) |
+ (addr_hit[ 5] & (|(HMAC_PERMIT[ 5] & ~reg_be))) |
+ (addr_hit[ 6] & (|(HMAC_PERMIT[ 6] & ~reg_be))) |
+ (addr_hit[ 7] & (|(HMAC_PERMIT[ 7] & ~reg_be))) |
+ (addr_hit[ 8] & (|(HMAC_PERMIT[ 8] & ~reg_be))) |
+ (addr_hit[ 9] & (|(HMAC_PERMIT[ 9] & ~reg_be))) |
+ (addr_hit[10] & (|(HMAC_PERMIT[10] & ~reg_be))) |
+ (addr_hit[11] & (|(HMAC_PERMIT[11] & ~reg_be))) |
+ (addr_hit[12] & (|(HMAC_PERMIT[12] & ~reg_be))) |
+ (addr_hit[13] & (|(HMAC_PERMIT[13] & ~reg_be))) |
+ (addr_hit[14] & (|(HMAC_PERMIT[14] & ~reg_be))) |
+ (addr_hit[15] & (|(HMAC_PERMIT[15] & ~reg_be))) |
+ (addr_hit[16] & (|(HMAC_PERMIT[16] & ~reg_be))) |
+ (addr_hit[17] & (|(HMAC_PERMIT[17] & ~reg_be))) |
+ (addr_hit[18] & (|(HMAC_PERMIT[18] & ~reg_be))) |
+ (addr_hit[19] & (|(HMAC_PERMIT[19] & ~reg_be))) |
+ (addr_hit[20] & (|(HMAC_PERMIT[20] & ~reg_be))) |
+ (addr_hit[21] & (|(HMAC_PERMIT[21] & ~reg_be))) |
+ (addr_hit[22] & (|(HMAC_PERMIT[22] & ~reg_be))) |
+ (addr_hit[23] & (|(HMAC_PERMIT[23] & ~reg_be))) |
+ (addr_hit[24] & (|(HMAC_PERMIT[24] & ~reg_be))) |
+ (addr_hit[25] & (|(HMAC_PERMIT[25] & ~reg_be))) |
+ (addr_hit[26] & (|(HMAC_PERMIT[26] & ~reg_be)))));
+ end
+ assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
+
+ assign intr_state_hmac_done_wd = reg_wdata[0];
+
+ assign intr_state_fifo_empty_wd = reg_wdata[1];
+
+ assign intr_state_hmac_err_wd = reg_wdata[2];
+ assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
+
+ assign intr_enable_hmac_done_wd = reg_wdata[0];
+
+ assign intr_enable_fifo_empty_wd = reg_wdata[1];
+
+ assign intr_enable_hmac_err_wd = reg_wdata[2];
+ assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
+
+ assign intr_test_hmac_done_wd = reg_wdata[0];
+
+ assign intr_test_fifo_empty_wd = reg_wdata[1];
+
+ assign intr_test_hmac_err_wd = reg_wdata[2];
+ assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
+
+ assign alert_test_wd = reg_wdata[0];
+ assign cfg_re = addr_hit[4] & reg_re & !reg_error;
+ assign cfg_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign cfg_hmac_en_wd = reg_wdata[0];
+
+ assign cfg_sha_en_wd = reg_wdata[1];
+
+ assign cfg_endian_swap_wd = reg_wdata[2];
+
+ assign cfg_digest_swap_wd = reg_wdata[3];
+ assign cmd_we = addr_hit[5] & reg_we & !reg_error;
+
+ assign cmd_hash_start_wd = reg_wdata[0];
+
+ assign cmd_hash_process_wd = reg_wdata[1];
+ assign status_re = addr_hit[6] & reg_re & !reg_error;
+ assign wipe_secret_we = addr_hit[8] & reg_we & !reg_error;
+
+ assign wipe_secret_wd = reg_wdata[31:0];
+ assign key_0_we = addr_hit[9] & reg_we & !reg_error;
+
+ assign key_0_wd = reg_wdata[31:0];
+ assign key_1_we = addr_hit[10] & reg_we & !reg_error;
+
+ assign key_1_wd = reg_wdata[31:0];
+ assign key_2_we = addr_hit[11] & reg_we & !reg_error;
+
+ assign key_2_wd = reg_wdata[31:0];
+ assign key_3_we = addr_hit[12] & reg_we & !reg_error;
+
+ assign key_3_wd = reg_wdata[31:0];
+ assign key_4_we = addr_hit[13] & reg_we & !reg_error;
+
+ assign key_4_wd = reg_wdata[31:0];
+ assign key_5_we = addr_hit[14] & reg_we & !reg_error;
+
+ assign key_5_wd = reg_wdata[31:0];
+ assign key_6_we = addr_hit[15] & reg_we & !reg_error;
+
+ assign key_6_wd = reg_wdata[31:0];
+ assign key_7_we = addr_hit[16] & reg_we & !reg_error;
+
+ assign key_7_wd = reg_wdata[31:0];
+ assign digest_0_re = addr_hit[17] & reg_re & !reg_error;
+ assign digest_1_re = addr_hit[18] & reg_re & !reg_error;
+ assign digest_2_re = addr_hit[19] & reg_re & !reg_error;
+ assign digest_3_re = addr_hit[20] & reg_re & !reg_error;
+ assign digest_4_re = addr_hit[21] & reg_re & !reg_error;
+ assign digest_5_re = addr_hit[22] & reg_re & !reg_error;
+ assign digest_6_re = addr_hit[23] & reg_re & !reg_error;
+ assign digest_7_re = addr_hit[24] & reg_re & !reg_error;
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = intr_state_hmac_done_qs;
+ reg_rdata_next[1] = intr_state_fifo_empty_qs;
+ reg_rdata_next[2] = intr_state_hmac_err_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[0] = intr_enable_hmac_done_qs;
+ reg_rdata_next[1] = intr_enable_fifo_empty_qs;
+ reg_rdata_next[2] = intr_enable_hmac_err_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ reg_rdata_next[2] = '0;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[0] = '0;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[0] = cfg_hmac_en_qs;
+ reg_rdata_next[1] = cfg_sha_en_qs;
+ reg_rdata_next[2] = cfg_endian_swap_qs;
+ reg_rdata_next[3] = cfg_digest_swap_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[0] = status_fifo_empty_qs;
+ reg_rdata_next[1] = status_fifo_full_qs;
+ reg_rdata_next[8:4] = status_fifo_depth_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[31:0] = err_code_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[31:0] = digest_0_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[31:0] = digest_1_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[31:0] = digest_2_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[31:0] = digest_3_qs;
+ end
+
+ addr_hit[21]: begin
+ reg_rdata_next[31:0] = digest_4_qs;
+ end
+
+ addr_hit[22]: begin
+ reg_rdata_next[31:0] = digest_5_qs;
+ end
+
+ addr_hit[23]: begin
+ reg_rdata_next[31:0] = digest_6_qs;
+ end
+
+ addr_hit[24]: begin
+ reg_rdata_next[31:0] = digest_7_qs;
+ end
+
+ addr_hit[25]: begin
+ reg_rdata_next[31:0] = msg_length_lower_qs;
+ end
+
+ addr_hit[26]: begin
+ reg_rdata_next[31:0] = msg_length_upper_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // shadow busy
+ logic shadow_busy;
+ assign shadow_busy = 1'b0;
+
+ // register busy
+ logic reg_busy_sel;
+ assign reg_busy = reg_busy_sel | shadow_busy;
+ always_comb begin
+ reg_busy_sel = '0;
+ unique case (1'b1)
+ default: begin
+ reg_busy_sel = '0;
+ end
+ endcase
+ end
+
+
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/jtag_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/jtag_pkg.sv
new file mode 100644
index 00000000..2a67ee07
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/jtag_pkg.sv
@@ -0,0 +1,24 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package jtag_pkg;
+
+ typedef struct packed {
+ logic tck;
+ logic tms;
+ logic trst_n;
+ logic tdi;
+ } jtag_req_t;
+
+ parameter jtag_req_t JTAG_REQ_DEFAULT = '0;
+
+ typedef struct packed {
+ logic tdo;
+ logic tdo_oe;
+ } jtag_rsp_t;
+
+ parameter jtag_rsp_t JTAG_RSP_DEFAULT = '0;
+
+endpackage : jtag_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/lc_ctrl_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/lc_ctrl_pkg.sv
new file mode 100644
index 00000000..b7c19189
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/lc_ctrl_pkg.sv
@@ -0,0 +1,345 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package lc_ctrl_pkg;
+
+ import prim_util_pkg::vbits;
+
+ // TODO: need to generate these randomly, based on ECC
+ // polynomial used inside the OTP macro.
+ // The A/B values are used for the encoded LC state.
+ parameter logic [15:0] A0 = 16'h0000;
+ parameter logic [15:0] A1 = 16'h0000;
+ parameter logic [15:0] A2 = 16'h0000;
+ parameter logic [15:0] A3 = 16'h0000;
+ parameter logic [15:0] A4 = 16'h0000;
+ parameter logic [15:0] A5 = 16'h0000;
+ parameter logic [15:0] A6 = 16'h0000;
+ parameter logic [15:0] A7 = 16'h0000;
+ parameter logic [15:0] A8 = 16'h0000;
+ parameter logic [15:0] A9 = 16'h0000;
+ parameter logic [15:0] A10 = 16'h0000;
+ parameter logic [15:0] A11 = 16'h0000;
+
+ parameter logic [15:0] B0 = 16'hFFFF;
+ parameter logic [15:0] B1 = 16'hFFFF;
+ parameter logic [15:0] B2 = 16'hFFFF;
+ parameter logic [15:0] B3 = 16'hFFFF;
+ parameter logic [15:0] B4 = 16'hFFFF;
+ parameter logic [15:0] B5 = 16'hFFFF;
+ parameter logic [15:0] B6 = 16'hFFFF;
+ parameter logic [15:0] B7 = 16'hFFFF;
+ parameter logic [15:0] B8 = 16'hFFFF;
+ parameter logic [15:0] B9 = 16'hFFFF;
+ parameter logic [15:0] B10 = 16'hFFFF;
+ parameter logic [15:0] B11 = 16'hFFFF;
+
+ // The C/D values are used for the encoded LC transition counter.
+ parameter logic [15:0] C0 = 16'h0000;
+ parameter logic [15:0] C1 = 16'h0000;
+ parameter logic [15:0] C2 = 16'h0000;
+ parameter logic [15:0] C3 = 16'h0000;
+ parameter logic [15:0] C4 = 16'h0000;
+ parameter logic [15:0] C5 = 16'h0000;
+ parameter logic [15:0] C6 = 16'h0000;
+ parameter logic [15:0] C7 = 16'h0000;
+ parameter logic [15:0] C8 = 16'h0000;
+ parameter logic [15:0] C9 = 16'h0000;
+ parameter logic [15:0] C10 = 16'h0000;
+ parameter logic [15:0] C11 = 16'h0000;
+ parameter logic [15:0] C12 = 16'h0000;
+ parameter logic [15:0] C13 = 16'h0000;
+ parameter logic [15:0] C14 = 16'h0000;
+ parameter logic [15:0] C15 = 16'h0000;
+
+ parameter logic [15:0] D0 = 16'hFFFF;
+ parameter logic [15:0] D1 = 16'hFFFF;
+ parameter logic [15:0] D2 = 16'hFFFF;
+ parameter logic [15:0] D3 = 16'hFFFF;
+ parameter logic [15:0] D4 = 16'hFFFF;
+ parameter logic [15:0] D5 = 16'hFFFF;
+ parameter logic [15:0] D6 = 16'hFFFF;
+ parameter logic [15:0] D7 = 16'hFFFF;
+ parameter logic [15:0] D8 = 16'hFFFF;
+ parameter logic [15:0] D9 = 16'hFFFF;
+ parameter logic [15:0] D10 = 16'hFFFF;
+ parameter logic [15:0] D11 = 16'hFFFF;
+ parameter logic [15:0] D12 = 16'hFFFF;
+ parameter logic [15:0] D13 = 16'hFFFF;
+ parameter logic [15:0] D14 = 16'hFFFF;
+ parameter logic [15:0] D15 = 16'hFFFF;
+
+ // The E/F values are used for the encoded ID state.
+ parameter logic [15:0] E0 = 16'h0000;
+ parameter logic [15:0] F0 = 16'hFFFF;
+
+ /////////////////////////////////
+ // General Typedefs and Params //
+ /////////////////////////////////
+
+ parameter int LcValueWidth = 16;
+ parameter int LcTokenWidth = 128;
+ parameter int NumLcStateValues = 12;
+ parameter int LcStateWidth = NumLcStateValues * LcValueWidth;
+ parameter int NumLcCountValues = 16;
+ parameter int LcCountWidth = NumLcCountValues * LcValueWidth;
+ parameter int NumLcStates = 13;
+ parameter int DecLcStateWidth = vbits(NumLcStates);
+ parameter int DecLcCountWidth = vbits(NumLcCountValues+1);
+ parameter int LcIdStateWidth = LcValueWidth;
+ parameter int DecLcIdStateWidth = 2;
+
+ typedef logic [LcTokenWidth-1:0] lc_token_t;
+
+ // TODO: make this secret and generate randomly, given a specific ECC polynomial.
+ typedef enum logic [LcStateWidth-1:0] {
+ // Halfword idx : 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ LcStRaw = '0,
+ LcStTestUnlocked0 = {A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, B0},
+ LcStTestLocked0 = {A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, B1, B0},
+ LcStTestUnlocked1 = {A11, A10, A9, A8, A7, A6, A5, A4, A3, B2, B1, B0},
+ LcStTestLocked1 = {A11, A10, A9, A8, A7, A6, A5, A4, B3, B2, B1, B0},
+ LcStTestUnlocked2 = {A11, A10, A9, A8, A7, A6, A5, B4, B3, B2, B1, B0},
+ LcStTestLocked2 = {A11, A10, A9, A8, A7, A6, B5, B4, B3, B2, B1, B0},
+ LcStTestUnlocked3 = {A11, A10, A9, A8, A7, B6, B5, B4, B3, B2, B1, B0},
+ LcStDev = {A11, A10, A9, A8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStProd = {A11, A10, A9, B8, A7, B6, B5, B4, B3, B2, B1, B0},
+ LcStProdEnd = {A11, A10, B9, A8, A7, B6, B5, B4, B3, B2, B1, B0},
+ LcStRma = {B11, B10, A9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStScrap = {B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}
+ } lc_state_e;
+
+ // Decoded life cycle state, used to interface with CSRs and TAP.
+ typedef enum logic [DecLcStateWidth-1:0] {
+ DecLcStRaw = 4'h0,
+ DecLcStTestUnlocked0 = 4'h1,
+ DecLcStTestLocked0 = 4'h2,
+ DecLcStTestUnlocked1 = 4'h3,
+ DecLcStTestLocked1 = 4'h4,
+ DecLcStTestUnlocked2 = 4'h5,
+ DecLcStTestLocked2 = 4'h6,
+ DecLcStTestUnlocked3 = 4'h7,
+ DecLcStDev = 4'h8,
+ DecLcStProd = 4'h9,
+ DecLcStProdEnd = 4'hA,
+ DecLcStRma = 4'hB,
+ DecLcStScrap = 4'hC,
+ DecLcStPostTrans = 4'hD,
+ DecLcStEscalate = 4'hE,
+ DecLcStInvalid = 4'hF
+ } dec_lc_state_e;
+
+ typedef enum logic [LcIdStateWidth-1:0] {
+ LcIdBlank = E0,
+ LcIdPersonalized = F0
+ } lc_id_state_e;
+
+ typedef enum logic [DecLcIdStateWidth-1:0] {
+ DecLcIdBlank = 2'd0,
+ DecLcIdPersonalized = 2'd1,
+ DecLcIdInvalid = 2'd2
+ } dec_lc_id_state_e;
+
+ typedef enum logic [LcCountWidth-1:0] {
+ LcCntRaw = '0,
+ LcCnt1 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, D0},
+ LcCnt2 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, D1, D0},
+ LcCnt3 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, D2, D1, D0},
+ LcCnt4 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, D3, D2, D1, D0},
+ LcCnt5 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, D4, D3, D2, D1, D0},
+ LcCnt6 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, D5, D4, D3, D2, D1, D0},
+ LcCnt7 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt8 = {C15, C14, C13, C12, C11, C10, C9, C8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt9 = {C15, C14, C13, C12, C11, C10, C9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt10 = {C15, C14, C13, C12, C11, C10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt11 = {C15, C14, C13, C12, C11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt12 = {C15, C14, C13, C12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt13 = {C15, C14, C13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt14 = {C15, C14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt15 = {C15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt16 = {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}
+ } lc_cnt_e;
+
+ typedef logic [DecLcCountWidth-1:0] dec_lc_cnt_t;
+
+
+ ///////////////////////////////////////
+ // Netlist Constants (Hashed Tokens) //
+ ///////////////////////////////////////
+
+ parameter int NumTokens = 6;
+ parameter int TokenIdxWidth = vbits(NumTokens);
+ typedef enum logic [TokenIdxWidth-1:0] {
+ // This is the index for the hashed all-zero constant.
+ // All unconditional transitions use this token.
+ ZeroTokenIdx = 3'h0,
+ RawUnlockTokenIdx = 3'h1,
+ TestUnlockTokenIdx = 3'h2,
+ TestExitTokenIdx = 3'h3,
+ RmaTokenIdx = 3'h4,
+ // This is the index for an all-zero value (i.e., hashed value = '0).
+ // This is used as an additional blocker for some invalid state transition edges.
+ InvalidTokenIdx = 3'h5
+ } token_idx_e;
+
+ ////////////////////////////////
+ // Typedefs for LC Interfaces //
+ ////////////////////////////////
+
+ parameter int TxWidth = 4;
+ typedef enum logic [TxWidth-1:0] {
+ On = 4'b1010,
+ Off = 4'b0101
+ } lc_tx_e;
+
+ typedef lc_tx_e lc_tx_t;
+
+ parameter lc_tx_t LC_TX_DEFAULT = Off;
+
+ parameter int RmaSeedWidth = 32;
+ typedef logic [RmaSeedWidth-1:0] lc_flash_rma_seed_t;
+
+ parameter int LcKeymgrDivWidth = 64;
+ typedef logic [LcKeymgrDivWidth-1:0] lc_keymgr_div_t;
+
+ ////////////////////
+ // Main FSM State //
+ ////////////////////
+
+ // Encoding generated with:
+ // $ ./sparse-fsm-encode.py -d 5 -m 14 -n 16 \
+ // -s 2934212379 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: |||||| (6.59%)
+ // 6: |||||||||| (10.99%)
+ // 7: |||||||||||||||| (17.58%)
+ // 8: |||||||||||||||||||| (20.88%)
+ // 9: |||||||||||||||| (17.58%)
+ // 10: |||||||||||||| (15.38%)
+ // 11: |||||| (6.59%)
+ // 12: ||| (3.30%)
+ // 13: | (1.10%)
+ // 14: --
+ // 15: --
+ // 16: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 13
+ //
+ localparam int FsmStateWidth = 16;
+ typedef enum logic [FsmStateWidth-1:0] {
+ ResetSt = 16'b1100000001111011,
+ IdleSt = 16'b1111011010111100,
+ ClkMuxSt = 16'b0000011110101101,
+ CntIncrSt = 16'b1100111011001001,
+ CntProgSt = 16'b0011001111000111,
+ TransCheckSt = 16'b0000110001010100,
+ TokenHashSt = 16'b1110100010001111,
+ FlashRmaSt = 16'b0110111010110000,
+ TokenCheck0St = 16'b0010000011000000,
+ TokenCheck1St = 16'b1101010101101111,
+ TransProgSt = 16'b1000000110101011,
+ PostTransSt = 16'b0110110100101100,
+ EscalateSt = 16'b1010100001010001,
+ InvalidSt = 16'b1011110110011011
+ } fsm_state_e;
+
+ ///////////////////////////////////////////
+ // Manufacturing State Transition Matrix //
+ ///////////////////////////////////////////
+
+ // The token index matrix below encodes 1) which transition edges are valid and 2) which token
+ // to use for a given transition edge. Note that unconditional but otherwise valid transitions
+ // are assigned the ZeroTokenIdx, whereas invalid transitions are assigned an InvalidTokenIdx.
+ parameter token_idx_e [NumLcStates-1:0][NumLcStates-1:0] TransTokenIdxMatrix = {
+ // SCRAP
+ {13{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END, RMA, SCRAP
+ // RMA
+ ZeroTokenIdx, // -> SCRAP
+ {12{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END, RMA
+ // PROD_END
+ ZeroTokenIdx, // -> SCRAP
+ {12{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END, RMA
+ // PROD
+ ZeroTokenIdx, // -> SCRAP
+ RmaTokenIdx, // -> RMA
+ {11{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END
+ // DEV
+ ZeroTokenIdx, // -> SCRAP
+ RmaTokenIdx, // -> RMA
+ {11{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END
+ // TEST_UNLOCKED3
+ {2{ZeroTokenIdx}}, // -> SCRAP, RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ {8{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, RAW
+ // TEST_LOCKED2
+ ZeroTokenIdx, // -> SCRAP
+ InvalidTokenIdx, // -> RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED3
+ {7{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-2, RAW
+ // TEST_UNLOCKED2
+ {2{ZeroTokenIdx}}, // -> SCRAP, RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ InvalidTokenIdx, // -> TEST_UNLOCKED3
+ ZeroTokenIdx, // -> TEST_LOCKED2
+ {6{InvalidTokenIdx}}, // -> TEST_LOCKED0-1, TEST_UNLOCKED0-2, RAW
+ // TEST_LOCKED1
+ ZeroTokenIdx, // -> SCRAP
+ InvalidTokenIdx, // -> RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED3
+ InvalidTokenIdx , // -> TEST_LOCKED2
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED2
+ {5{InvalidTokenIdx}}, // -> TEST_LOCKED0-1, TEST_UNLOCKED0-1, RAW
+ // TEST_UNLOCKED1
+ {2{ZeroTokenIdx}}, // -> SCRAP, RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ InvalidTokenIdx, // -> TEST_UNLOCKED3
+ ZeroTokenIdx, // -> TEST_LOCKED2
+ InvalidTokenIdx, // -> TEST_UNLOCKED2
+ ZeroTokenIdx, // -> TEST_LOCKED1
+ {4{InvalidTokenIdx}}, // -> TEST_LOCKED0, TEST_UNLOCKED0-1, RAW
+ // TEST_LOCKED0
+ ZeroTokenIdx, // -> SCRAP
+ InvalidTokenIdx, // -> RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED3
+ InvalidTokenIdx, // -> TEST_LOCKED2
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED2
+ InvalidTokenIdx, // -> TEST_LOCKED1
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED1
+ {3{InvalidTokenIdx}}, // -> TEST_LOCKED0, TEST_UNLOCKED0, RAW
+ // TEST_UNLOCKED0
+ {2{ZeroTokenIdx}}, // -> SCRAP, RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ InvalidTokenIdx, // -> TEST_UNLOCKED3
+ ZeroTokenIdx, // -> TEST_LOCKED2
+ InvalidTokenIdx, // -> TEST_UNLOCKED2
+ ZeroTokenIdx, // -> TEST_LOCKED1
+ InvalidTokenIdx, // -> TEST_UNLOCKED1
+ ZeroTokenIdx, // -> TEST_LOCKED0
+ {2{InvalidTokenIdx}}, // -> TEST_UNLOCKED0, RAW
+ // RAW
+ ZeroTokenIdx, // -> SCRAP
+ {4{InvalidTokenIdx}}, // -> RMA, PROD, PROD_END, DEV
+ RawUnlockTokenIdx, // -> TEST_UNLOCKED3
+ InvalidTokenIdx, // -> TEST_LOCKED2
+ RawUnlockTokenIdx, // -> TEST_UNLOCKED2
+ InvalidTokenIdx, // -> TEST_LOCKED1
+ RawUnlockTokenIdx, // -> TEST_UNLOCKED1
+ InvalidTokenIdx, // -> TEST_LOCKED0
+ RawUnlockTokenIdx, // -> TEST_UNLOCKED0
+ InvalidTokenIdx // -> RAW
+ };
+
+endpackage : lc_ctrl_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/otp_ctrl_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/otp_ctrl_pkg.sv
new file mode 100644
index 00000000..ba03e2ec
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/otp_ctrl_pkg.sv
@@ -0,0 +1,337 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package otp_ctrl_pkg;
+
+ import prim_util_pkg::vbits;
+ import otp_ctrl_reg_pkg::*;
+
+ ////////////////////////
+ // General Parameters //
+ ////////////////////////
+
+ // Width of entropy input
+ parameter int EdnDataWidth = 64;
+
+ parameter int NumPartWidth = vbits(NumPart);
+
+ parameter int SwWindowAddrWidth = vbits(NumSwCfgWindowWords);
+
+ // Redundantly encoded and complementary values are used to for signalling to the partition
+ // controller FSMs and the DAI whether a partition is locked or not. Any other value than
+ // "Unlocked" is interpreted as "Locked" in those FSMs.
+ typedef enum logic [7:0] {
+ Unlocked = 8'h5A,
+ Locked = 8'hA5
+ } access_e;
+
+ // Partition access type
+ typedef struct packed {
+ access_e read_lock;
+ access_e write_lock;
+ } part_access_t;
+
+ parameter int DaiCmdWidth = 3;
+ typedef enum logic [DaiCmdWidth-1:0] {
+ DaiRead = 3'b001,
+ DaiWrite = 3'b010,
+ DaiDigest = 3'b100
+ } dai_cmd_e;
+
+ //////////////////////////////////////
+ // Typedefs for OTP Macro Interface //
+ //////////////////////////////////////
+
+ // OTP-macro specific
+ parameter int OtpWidth = 16;
+ parameter int OtpAddrWidth = OtpByteAddrWidth - $clog2(OtpWidth/8);
+ parameter int OtpDepth = 2**OtpAddrWidth;
+ parameter int OtpSizeWidth = 2; // Allows to transfer up to 4 native OTP words at once.
+ parameter int OtpErrWidth = 3;
+ parameter int OtpPwrSeqWidth = 2;
+ parameter int OtpIfWidth = 2**OtpSizeWidth*OtpWidth;
+ // Number of Byte address bits to cut off in order to get the native OTP word address.
+ parameter int OtpAddrShift = OtpByteAddrWidth - OtpAddrWidth;
+
+ typedef enum logic [OtpErrWidth-1:0] {
+ NoError = 3'h0,
+ MacroError = 3'h1,
+ MacroEccCorrError = 3'h2,
+ MacroEccUncorrError = 3'h3,
+ MacroWriteBlankError = 3'h4,
+ AccessError = 3'h5,
+ CheckFailError = 3'h6,
+ FsmStateError = 3'h7
+ } otp_err_e;
+
+ /////////////////////////////////
+ // Typedefs for OTP Scrambling //
+ /////////////////////////////////
+
+ parameter int ScrmblKeyWidth = 128;
+ parameter int ScrmblBlockWidth = 64;
+
+ parameter int NumPresentRounds = 31;
+ parameter int ScrmblBlockHalfWords = ScrmblBlockWidth / OtpWidth;
+
+ typedef enum logic [2:0] {
+ Decrypt,
+ Encrypt,
+ LoadShadow,
+ Digest,
+ DigestInit,
+ DigestFinalize
+ } otp_scrmbl_cmd_e;
+
+ parameter int NumScrmblKeys = 3;
+ parameter int NumDigestSets = 5;
+ parameter int ConstSelWidth = (NumScrmblKeys > NumDigestSets) ?
+ vbits(NumScrmblKeys) :
+ vbits(NumDigestSets);
+
+ typedef enum logic [ConstSelWidth-1:0] {
+ Secret0Key,
+ Secret1Key,
+ Secret2Key
+ } key_sel_e;
+
+ typedef enum logic [ConstSelWidth-1:0] {
+ CnstyDigest,
+ LcRawDigest,
+ FlashDataKey,
+ FlashAddrKey,
+ SramDataKey
+ } digest_sel_e;
+
+ typedef enum logic [ConstSelWidth-1:0] {
+ StandardMode,
+ ChainedMode
+ } digest_mode_e;
+
+ /////////////////////////////////////
+ // Typedefs for Partition Metadata //
+ /////////////////////////////////////
+
+ typedef enum logic [1:0] {
+ Unbuffered,
+ Buffered,
+ LifeCycle
+ } part_variant_e;
+
+ typedef struct packed {
+ part_variant_e variant;
+ // Offset and size within the OTP array, in Bytes.
+ logic [OtpByteAddrWidth-1:0] offset;
+ logic [OtpByteAddrWidth-1:0] size;
+ // Key index to use for scrambling.
+ key_sel_e key_sel;
+ // Attributes
+ logic secret; // Whether the partition is secret (and hence scrambled)
+ logic hw_digest; // Whether the partition has a hardware digest
+ logic write_lock; // Whether the partition is write lockable (via digest)
+ logic read_lock; // Whether the partition is read lockable (via digest)
+ } part_info_t;
+
+ ///////////////////////////////
+ // Typedefs for LC Interface //
+ ///////////////////////////////
+
+ typedef struct packed {
+ logic valid;
+ logic state;
+ // lc_ctrl_pkg::lc_cnt_e
+ logic count;
+ // These are all hash post-images
+ lc_ctrl_pkg::lc_token_t all_zero_token;
+ lc_ctrl_pkg::lc_token_t raw_unlock_token;
+ lc_ctrl_pkg::lc_token_t test_unlock_token;
+ lc_ctrl_pkg::lc_token_t test_exit_token;
+ lc_ctrl_pkg::lc_token_t rma_token;
+ // lc_ctrl_pkg::lc_id_state_e
+ logic id_state;
+ } otp_lc_data_t;
+
+ // Default for dangling connection
+ parameter otp_lc_data_t OTP_LC_DATA_DEFAULT = '{
+ valid: 1'b1,
+ state : 1'b0,
+ count: 1'b0,
+ all_zero_token:1'b0,
+ raw_unlock_token: 1'b0,
+ test_unlock_token: 1'b0,
+ test_exit_token: 1'b0,
+ rma_token: 1'b0,
+ id_state: 1'b0
+ };
+
+
+ typedef struct packed {
+ logic req;
+ // lc_ctrl_pkg::lc_state_e state;
+ // lc_ctrl_pkg::lc_cnt_e count;
+ } lc_otp_program_req_t;
+
+ typedef struct packed {
+ logic err;
+ logic ack;
+ } lc_otp_program_rsp_t;
+
+ // RAW unlock token hashing request.
+ typedef struct packed {
+ logic req;
+ lc_ctrl_pkg::lc_token_t token_input;
+ } lc_otp_token_req_t;
+
+ typedef struct packed {
+ logic ack;
+ lc_ctrl_pkg::lc_token_t hashed_token;
+ } lc_otp_token_rsp_t;
+
+ ////////////////////////////////
+ // Typedefs for Key Broadcast //
+ ////////////////////////////////
+
+ parameter int FlashKeySeedWidth = 256;
+ parameter int SramKeySeedWidth = 128;
+ parameter int KeyMgrKeyWidth = 256;
+ parameter int FlashKeyWidth = 128;
+ parameter int SramKeyWidth = 128;
+ parameter int SramNonceWidth = 64;
+ parameter int OtbnKeyWidth = 128;
+ parameter int OtbnNonceWidth = 256;
+
+ typedef logic [SramKeyWidth-1:0] sram_key_t;
+ typedef logic [SramNonceWidth-1:0] sram_nonce_t;
+ typedef logic [OtbnKeyWidth-1:0] otbn_key_t;
+ typedef logic [OtbnNonceWidth-1:0] otbn_nonce_t;
+
+ typedef struct packed {
+ logic valid;
+ logic [KeyMgrKeyWidth-1:0] key_share0;
+ logic [KeyMgrKeyWidth-1:0] key_share1;
+ } otp_keymgr_key_t;
+
+ parameter otp_keymgr_key_t OTP_KEYMGR_KEY_DEFAULT = '{
+ valid: 1'b1,
+ key_share0: 256'hefb7ea7ee90093cf4affd9aaa2d6c0ec446cfdf5f2d5a0bfd7e2d93edc63a102,
+ key_share1: 256'h56d24a00181de99e0f690b447a8dde2a1ffb8bc306707107aa6e2410f15cfc37
+ };
+
+ typedef struct packed {
+ logic data_req; // Requests static key for data scrambling.
+ logic addr_req; // Requests static key for address scrambling.
+ } flash_otp_key_req_t;
+
+ typedef struct packed {
+ logic req; // Requests ephemeral scrambling key and nonce.
+ } sram_otp_key_req_t;
+
+ typedef struct packed {
+ logic req; // Requests ephemeral scrambling key and nonce.
+ } otbn_otp_key_req_t;
+
+ typedef struct packed {
+ logic data_ack; // Ack for data key.
+ logic addr_ack; // Ack for address key.
+ logic [FlashKeyWidth-1:0] key; // 128bit static scrambling key.
+ logic seed_valid; // Set to 1 if the key seed has been provisioned and is valid.
+ } flash_otp_key_rsp_t;
+
+ // Default for dangling connection
+ parameter flash_otp_key_rsp_t FLASH_OTP_KEY_RSP_DEFAULT = '{
+ data_ack: 1'b1,
+ addr_ack: 1'b1,
+ key: '0,
+ seed_valid: 1'b1
+ };
+
+ typedef struct packed {
+ logic ack; // Ack for key.
+ sram_key_t key; // 128bit ephemeral scrambling key.
+ sram_nonce_t nonce; // 64bit nonce.
+ logic seed_valid; // Set to 1 if the key seed has been provisioned and is valid.
+ } sram_otp_key_rsp_t;
+
+ typedef struct packed {
+ logic ack; // Ack for key.
+ otbn_key_t key; // 128bit ephemeral scrambling key.
+ otbn_nonce_t nonce; // 256bit nonce.
+ logic seed_valid; // Set to 1 if the key seed has been provisioned and is valid.
+ } otbn_otp_key_rsp_t;
+
+ ////////////////////////////////
+ // Power/Reset Ctrl Interface //
+ ////////////////////////////////
+
+ typedef struct packed {
+ logic init;
+ } pwr_otp_init_req_t;
+
+ typedef struct packed {
+ logic done;
+ } pwr_otp_init_rsp_t;
+
+ typedef struct packed {
+ logic idle;
+ } otp_pwr_state_t;
+
+
+ ///////////////////
+ // AST Interface //
+ ///////////////////
+
+ typedef struct packed {
+ logic [OtpPwrSeqWidth-1:0] pwr_seq;
+ } otp_ast_req_t;
+
+ typedef struct packed {
+ logic [OtpPwrSeqWidth-1:0] pwr_seq_h;
+ } otp_ast_rsp_t;
+
+ ///////////////////////////////////////////
+ // Defaults for random netlist constants //
+ ///////////////////////////////////////////
+
+ // These LFSR parameters have been generated with
+ // $ hw/ip/prim/util/gen-lfsr-seed.py --width 40 --seed 4247488366
+ localparam int LfsrWidth = 40;
+ typedef logic [LfsrWidth-1:0] lfsr_seed_t;
+ typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
+ localparam lfsr_seed_t RndCnstLfsrSeedDefault = 40'h453d28ea98;
+ localparam lfsr_perm_t RndCnstLfsrPermDefault =
+ 240'h4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5;
+
+
+ typedef logic [NumScrmblKeys-1:0][ScrmblKeyWidth-1:0] key_array_t;
+ parameter key_array_t RndCnstKeyDefault = {
+ 128'h047288e1a65c839dae610bbbdf8c4525,
+ 128'h38fe59a71a91a65636573a6513784e3b,
+ 128'h4f48dcc45ace0770e9135bda73e56344
+ };
+
+ // Note: digest set 0 is used for computing the partition digests. Constants at
+ // higher indices are used to compute the scrambling keys.
+ typedef logic [NumDigestSets-1:0][ScrmblKeyWidth-1:0] digest_const_array_t;
+ parameter digest_const_array_t RndCnstDigestConstDefault = {
+ 128'h9d40106e2dc2346ec96d61f0cc5295c7,
+ 128'hafed2aa5c3284c01d71103edab1d8953,
+ 128'h8a14fe0c08f8a3a190dd32c05f208474,
+ 128'h9e6fac4ba15a3bce29d05a3e9e2d0846,
+ 128'h3a0c6051392e00ef24073627319555b8
+ };
+
+ typedef logic [NumDigestSets-1:0][ScrmblBlockWidth-1:0] digest_iv_array_t;
+ parameter digest_iv_array_t RndCnstDigestIVDefault = {
+ 64'ha5af72c1b813aec4,
+ 64'h5d7aacd1db316407,
+ 64'hd0ec83b7fe6ae2ae,
+ 64'hc2993a0ea64e312d,
+ 64'h899aac2ab7d91479
+ };
+
+ parameter lc_ctrl_pkg::lc_token_t RndCnstRawUnlockTokenDefault =
+ 128'hcbbd013ff15eba2f3065461eeb88463e;
+
+endpackage : otp_ctrl_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/otp_ctrl_reg_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/otp_ctrl_reg_pkg.sv
new file mode 100644
index 00000000..49c86563
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/otp_ctrl_reg_pkg.sv
@@ -0,0 +1,571 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package otp_ctrl_reg_pkg;
+
+ // Param list
+ parameter int NumSramKeyReqSlots = 2;
+ parameter int OtpByteAddrWidth = 11;
+ parameter int NumErrorEntries = 10;
+ parameter int NumDaiWords = 2;
+ parameter int NumDigestWords = 2;
+ parameter int NumSwCfgWindowWords = 512;
+ parameter int NumDebugWindowWords = 16;
+ parameter int NumPart = 8;
+ parameter int VendorTestOffset = 0;
+ parameter int VendorTestSize = 64;
+ parameter int ScratchOffset = 0;
+ parameter int ScratchSize = 56;
+ parameter int VendorTestDigestOffset = 56;
+ parameter int VendorTestDigestSize = 8;
+ parameter int CreatorSwCfgOffset = 64;
+ parameter int CreatorSwCfgSize = 800;
+ parameter int CreatorSwCfgAstCfgOffset = 64;
+ parameter int CreatorSwCfgAstCfgSize = 128;
+ parameter int CreatorSwCfgAstInitEnOffset = 192;
+ parameter int CreatorSwCfgAstInitEnSize = 4;
+ parameter int CreatorSwCfgRomExtSkuOffset = 196;
+ parameter int CreatorSwCfgRomExtSkuSize = 4;
+ parameter int CreatorSwCfgUseSwRsaVerifyOffset = 200;
+ parameter int CreatorSwCfgUseSwRsaVerifySize = 4;
+ parameter int CreatorSwCfgKeyIsValidOffset = 204;
+ parameter int CreatorSwCfgKeyIsValidSize = 8;
+ parameter int CreatorSwCfgFlashDataDefaultCfgOffset = 212;
+ parameter int CreatorSwCfgFlashDataDefaultCfgSize = 4;
+ parameter int CreatorSwCfgFlashInfoBootDataCfgOffset = 216;
+ parameter int CreatorSwCfgFlashInfoBootDataCfgSize = 4;
+ parameter int CreatorSwCfgRngEnOffset = 220;
+ parameter int CreatorSwCfgRngEnSize = 4;
+ parameter int CreatorSwCfgDigestOffset = 856;
+ parameter int CreatorSwCfgDigestSize = 8;
+ parameter int OwnerSwCfgOffset = 864;
+ parameter int OwnerSwCfgSize = 800;
+ parameter int RomErrorReportingOffset = 864;
+ parameter int RomErrorReportingSize = 4;
+ parameter int RomBootstrapEnOffset = 868;
+ parameter int RomBootstrapEnSize = 4;
+ parameter int RomFaultResponseOffset = 872;
+ parameter int RomFaultResponseSize = 4;
+ parameter int RomAlertClassEnOffset = 876;
+ parameter int RomAlertClassEnSize = 4;
+ parameter int RomAlertEscalationOffset = 880;
+ parameter int RomAlertEscalationSize = 4;
+ parameter int RomAlertClassificationOffset = 884;
+ parameter int RomAlertClassificationSize = 320;
+ parameter int RomLocalAlertClassificationOffset = 1204;
+ parameter int RomLocalAlertClassificationSize = 64;
+ parameter int RomAlertAccumThreshOffset = 1268;
+ parameter int RomAlertAccumThreshSize = 16;
+ parameter int RomAlertTimeoutCyclesOffset = 1284;
+ parameter int RomAlertTimeoutCyclesSize = 16;
+ parameter int RomAlertPhaseCyclesOffset = 1300;
+ parameter int RomAlertPhaseCyclesSize = 64;
+ parameter int OwnerSwCfgDigestOffset = 1656;
+ parameter int OwnerSwCfgDigestSize = 8;
+ parameter int HwCfgOffset = 1664;
+ parameter int HwCfgSize = 80;
+ parameter int DeviceIdOffset = 1664;
+ parameter int DeviceIdSize = 32;
+ parameter int ManufStateOffset = 1696;
+ parameter int ManufStateSize = 32;
+ parameter int EnSramIfetchOffset = 1728;
+ parameter int EnSramIfetchSize = 1;
+ parameter int EnCsrngSwAppReadOffset = 1729;
+ parameter int EnCsrngSwAppReadSize = 1;
+ parameter int EnEntropySrcFwReadOffset = 1730;
+ parameter int EnEntropySrcFwReadSize = 1;
+ parameter int EnEntropySrcFwOverOffset = 1731;
+ parameter int EnEntropySrcFwOverSize = 1;
+ parameter int HwCfgDigestOffset = 1736;
+ parameter int HwCfgDigestSize = 8;
+ parameter int Secret0Offset = 1744;
+ parameter int Secret0Size = 40;
+ parameter int TestUnlockTokenOffset = 1744;
+ parameter int TestUnlockTokenSize = 16;
+ parameter int TestExitTokenOffset = 1760;
+ parameter int TestExitTokenSize = 16;
+ parameter int Secret0DigestOffset = 1776;
+ parameter int Secret0DigestSize = 8;
+ parameter int Secret1Offset = 1784;
+ parameter int Secret1Size = 88;
+ parameter int FlashAddrKeySeedOffset = 1784;
+ parameter int FlashAddrKeySeedSize = 32;
+ parameter int FlashDataKeySeedOffset = 1816;
+ parameter int FlashDataKeySeedSize = 32;
+ parameter int SramDataKeySeedOffset = 1848;
+ parameter int SramDataKeySeedSize = 16;
+ parameter int Secret1DigestOffset = 1864;
+ parameter int Secret1DigestSize = 8;
+ parameter int Secret2Offset = 1872;
+ parameter int Secret2Size = 88;
+ parameter int RmaTokenOffset = 1872;
+ parameter int RmaTokenSize = 16;
+ parameter int CreatorRootKeyShare0Offset = 1888;
+ parameter int CreatorRootKeyShare0Size = 32;
+ parameter int CreatorRootKeyShare1Offset = 1920;
+ parameter int CreatorRootKeyShare1Size = 32;
+ parameter int Secret2DigestOffset = 1952;
+ parameter int Secret2DigestSize = 8;
+ parameter int LifeCycleOffset = 1960;
+ parameter int LifeCycleSize = 88;
+ parameter int LcTransitionCntOffset = 1960;
+ parameter int LcTransitionCntSize = 48;
+ parameter int LcStateOffset = 2008;
+ parameter int LcStateSize = 40;
+ parameter int NumAlerts = 3;
+
+ // Address widths within the block
+ parameter int CoreAw = 13;
+ parameter int PrimAw = 1;
+
+ ///////////////////////////////////////////////
+ // Typedefs for registers for core interface //
+ ///////////////////////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } otp_operation_done;
+ struct packed {
+ logic q;
+ } otp_error;
+ } otp_ctrl_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } otp_operation_done;
+ struct packed {
+ logic q;
+ } otp_error;
+ } otp_ctrl_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } otp_operation_done;
+ struct packed {
+ logic q;
+ logic qe;
+ } otp_error;
+ } otp_ctrl_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_macro_error;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_check_error;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_bus_integ_error;
+ } otp_ctrl_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } rd;
+ struct packed {
+ logic q;
+ logic qe;
+ } wr;
+ struct packed {
+ logic q;
+ logic qe;
+ } digest;
+ } otp_ctrl_reg2hw_direct_access_cmd_reg_t;
+
+ typedef struct packed {
+ logic [10:0] q;
+ } otp_ctrl_reg2hw_direct_access_address_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } otp_ctrl_reg2hw_direct_access_wdata_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } integrity;
+ struct packed {
+ logic q;
+ logic qe;
+ } consistency;
+ } otp_ctrl_reg2hw_check_trigger_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } otp_ctrl_reg2hw_check_timeout_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } otp_ctrl_reg2hw_integrity_check_period_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } otp_ctrl_reg2hw_consistency_check_period_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } otp_ctrl_reg2hw_vendor_test_read_lock_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } otp_ctrl_reg2hw_creator_sw_cfg_read_lock_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } otp_ctrl_reg2hw_owner_sw_cfg_read_lock_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } otp_operation_done;
+ struct packed {
+ logic d;
+ logic de;
+ } otp_error;
+ } otp_ctrl_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ } vendor_test_error;
+ struct packed {
+ logic d;
+ } creator_sw_cfg_error;
+ struct packed {
+ logic d;
+ } owner_sw_cfg_error;
+ struct packed {
+ logic d;
+ } hw_cfg_error;
+ struct packed {
+ logic d;
+ } secret0_error;
+ struct packed {
+ logic d;
+ } secret1_error;
+ struct packed {
+ logic d;
+ } secret2_error;
+ struct packed {
+ logic d;
+ } life_cycle_error;
+ struct packed {
+ logic d;
+ } dai_error;
+ struct packed {
+ logic d;
+ } lci_error;
+ struct packed {
+ logic d;
+ } timeout_error;
+ struct packed {
+ logic d;
+ } lfsr_fsm_error;
+ struct packed {
+ logic d;
+ } scrambling_fsm_error;
+ struct packed {
+ logic d;
+ } key_deriv_fsm_error;
+ struct packed {
+ logic d;
+ } bus_integ_error;
+ struct packed {
+ logic d;
+ } dai_idle;
+ struct packed {
+ logic d;
+ } check_pending;
+ } otp_ctrl_hw2reg_status_reg_t;
+
+ typedef struct packed {
+ logic [2:0] d;
+ } otp_ctrl_hw2reg_err_code_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ } otp_ctrl_hw2reg_direct_access_regwen_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_direct_access_rdata_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_vendor_test_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_creator_sw_cfg_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_owner_sw_cfg_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_hw_cfg_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_secret0_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_secret1_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_secret2_digest_mreg_t;
+
+ // Register -> HW type for core interface
+ typedef struct packed {
+ otp_ctrl_reg2hw_intr_state_reg_t intr_state; // [197:196]
+ otp_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [195:194]
+ otp_ctrl_reg2hw_intr_test_reg_t intr_test; // [193:190]
+ otp_ctrl_reg2hw_alert_test_reg_t alert_test; // [189:184]
+ otp_ctrl_reg2hw_direct_access_cmd_reg_t direct_access_cmd; // [183:178]
+ otp_ctrl_reg2hw_direct_access_address_reg_t direct_access_address; // [177:167]
+ otp_ctrl_reg2hw_direct_access_wdata_mreg_t [1:0] direct_access_wdata; // [166:103]
+ otp_ctrl_reg2hw_check_trigger_reg_t check_trigger; // [102:99]
+ otp_ctrl_reg2hw_check_timeout_reg_t check_timeout; // [98:67]
+ otp_ctrl_reg2hw_integrity_check_period_reg_t integrity_check_period; // [66:35]
+ otp_ctrl_reg2hw_consistency_check_period_reg_t consistency_check_period; // [34:3]
+ otp_ctrl_reg2hw_vendor_test_read_lock_reg_t vendor_test_read_lock; // [2:2]
+ otp_ctrl_reg2hw_creator_sw_cfg_read_lock_reg_t creator_sw_cfg_read_lock; // [1:1]
+ otp_ctrl_reg2hw_owner_sw_cfg_read_lock_reg_t owner_sw_cfg_read_lock; // [0:0]
+ } otp_ctrl_core_reg2hw_t;
+
+ // HW -> register type for core interface
+ typedef struct packed {
+ otp_ctrl_hw2reg_intr_state_reg_t intr_state; // [563:560]
+ otp_ctrl_hw2reg_status_reg_t status; // [559:543]
+ otp_ctrl_hw2reg_err_code_mreg_t [9:0] err_code; // [542:513]
+ otp_ctrl_hw2reg_direct_access_regwen_reg_t direct_access_regwen; // [512:512]
+ otp_ctrl_hw2reg_direct_access_rdata_mreg_t [1:0] direct_access_rdata; // [511:448]
+ otp_ctrl_hw2reg_vendor_test_digest_mreg_t [1:0] vendor_test_digest; // [447:384]
+ otp_ctrl_hw2reg_creator_sw_cfg_digest_mreg_t [1:0] creator_sw_cfg_digest; // [383:320]
+ otp_ctrl_hw2reg_owner_sw_cfg_digest_mreg_t [1:0] owner_sw_cfg_digest; // [319:256]
+ otp_ctrl_hw2reg_hw_cfg_digest_mreg_t [1:0] hw_cfg_digest; // [255:192]
+ otp_ctrl_hw2reg_secret0_digest_mreg_t [1:0] secret0_digest; // [191:128]
+ otp_ctrl_hw2reg_secret1_digest_mreg_t [1:0] secret1_digest; // [127:64]
+ otp_ctrl_hw2reg_secret2_digest_mreg_t [1:0] secret2_digest; // [63:0]
+ } otp_ctrl_core_hw2reg_t;
+
+ // Register offsets for core interface
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTR_STATE_OFFSET = 13'h0;
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTR_ENABLE_OFFSET = 13'h4;
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTR_TEST_OFFSET = 13'h8;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ALERT_TEST_OFFSET = 13'hc;
+ parameter logic [CoreAw-1:0] OTP_CTRL_STATUS_OFFSET = 13'h10;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_OFFSET = 13'h14;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET = 13'h18;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET = 13'h1c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET = 13'h20;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET = 13'h24;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET = 13'h28;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET = 13'h2c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET = 13'h30;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET = 13'h34;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_OFFSET = 13'h38;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_REGWEN_OFFSET = 13'h3c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TIMEOUT_OFFSET = 13'h40;
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET = 13'h44;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET = 13'h48;
+ parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET = 13'h4c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET = 13'h50;
+ parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET = 13'h54;
+ parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET = 13'h58;
+ parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET = 13'h5c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET = 13'h60;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET = 13'h64;
+ parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET = 13'h68;
+ parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET = 13'h6c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG_DIGEST_0_OFFSET = 13'h70;
+ parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG_DIGEST_1_OFFSET = 13'h74;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_0_OFFSET = 13'h78;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_1_OFFSET = 13'h7c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_0_OFFSET = 13'h80;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_1_OFFSET = 13'h84;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_0_OFFSET = 13'h88;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_1_OFFSET = 13'h8c;
+
+ // Reset values for hwext registers and their fields for core interface
+ parameter logic [1:0] OTP_CTRL_INTR_TEST_RESVAL = 2'h0;
+ parameter logic [0:0] OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL = 1'h0;
+ parameter logic [2:0] OTP_CTRL_ALERT_TEST_RESVAL = 3'h0;
+ parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL = 1'h0;
+ parameter logic [16:0] OTP_CTRL_STATUS_RESVAL = 17'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_DAI_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_LCI_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_DAI_IDLE_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_STATUS_CHECK_PENDING_RESVAL = 1'h0;
+ parameter logic [29:0] OTP_CTRL_ERR_CODE_RESVAL = 30'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL = 3'h0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL = 3'h0;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL = 1'h1;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL = 1'h1;
+ parameter logic [2:0] OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL = 3'h0;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL = 1'h0;
+ parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL = 32'h0;
+ parameter logic [1:0] OTP_CTRL_CHECK_TRIGGER_RESVAL = 2'h0;
+ parameter logic [0:0] OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL = 1'h0;
+ parameter logic [0:0] OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL = 1'h0;
+ parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_HW_CFG_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_HW_CFG_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_1_RESVAL = 32'h0;
+ parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL = 32'h0;
+
+ // Window parameters for core interface
+ parameter logic [CoreAw-1:0] OTP_CTRL_SW_CFG_WINDOW_OFFSET = 13'h1000;
+ parameter int unsigned OTP_CTRL_SW_CFG_WINDOW_SIZE = 'h800;
+
+ // Register index for core interface
+ typedef enum int {
+ OTP_CTRL_INTR_STATE,
+ OTP_CTRL_INTR_ENABLE,
+ OTP_CTRL_INTR_TEST,
+ OTP_CTRL_ALERT_TEST,
+ OTP_CTRL_STATUS,
+ OTP_CTRL_ERR_CODE,
+ OTP_CTRL_DIRECT_ACCESS_REGWEN,
+ OTP_CTRL_DIRECT_ACCESS_CMD,
+ OTP_CTRL_DIRECT_ACCESS_ADDRESS,
+ OTP_CTRL_DIRECT_ACCESS_WDATA_0,
+ OTP_CTRL_DIRECT_ACCESS_WDATA_1,
+ OTP_CTRL_DIRECT_ACCESS_RDATA_0,
+ OTP_CTRL_DIRECT_ACCESS_RDATA_1,
+ OTP_CTRL_CHECK_TRIGGER_REGWEN,
+ OTP_CTRL_CHECK_TRIGGER,
+ OTP_CTRL_CHECK_REGWEN,
+ OTP_CTRL_CHECK_TIMEOUT,
+ OTP_CTRL_INTEGRITY_CHECK_PERIOD,
+ OTP_CTRL_CONSISTENCY_CHECK_PERIOD,
+ OTP_CTRL_VENDOR_TEST_READ_LOCK,
+ OTP_CTRL_CREATOR_SW_CFG_READ_LOCK,
+ OTP_CTRL_OWNER_SW_CFG_READ_LOCK,
+ OTP_CTRL_VENDOR_TEST_DIGEST_0,
+ OTP_CTRL_VENDOR_TEST_DIGEST_1,
+ OTP_CTRL_CREATOR_SW_CFG_DIGEST_0,
+ OTP_CTRL_CREATOR_SW_CFG_DIGEST_1,
+ OTP_CTRL_OWNER_SW_CFG_DIGEST_0,
+ OTP_CTRL_OWNER_SW_CFG_DIGEST_1,
+ OTP_CTRL_HW_CFG_DIGEST_0,
+ OTP_CTRL_HW_CFG_DIGEST_1,
+ OTP_CTRL_SECRET0_DIGEST_0,
+ OTP_CTRL_SECRET0_DIGEST_1,
+ OTP_CTRL_SECRET1_DIGEST_0,
+ OTP_CTRL_SECRET1_DIGEST_1,
+ OTP_CTRL_SECRET2_DIGEST_0,
+ OTP_CTRL_SECRET2_DIGEST_1
+ } otp_ctrl_core_id_e;
+
+ // Register width information to check illegal writes for core interface
+ parameter logic [3:0] OTP_CTRL_CORE_PERMIT [36] = '{
+ 4'b0001, // index[ 0] OTP_CTRL_INTR_STATE
+ 4'b0001, // index[ 1] OTP_CTRL_INTR_ENABLE
+ 4'b0001, // index[ 2] OTP_CTRL_INTR_TEST
+ 4'b0001, // index[ 3] OTP_CTRL_ALERT_TEST
+ 4'b0111, // index[ 4] OTP_CTRL_STATUS
+ 4'b1111, // index[ 5] OTP_CTRL_ERR_CODE
+ 4'b0001, // index[ 6] OTP_CTRL_DIRECT_ACCESS_REGWEN
+ 4'b0001, // index[ 7] OTP_CTRL_DIRECT_ACCESS_CMD
+ 4'b0011, // index[ 8] OTP_CTRL_DIRECT_ACCESS_ADDRESS
+ 4'b1111, // index[ 9] OTP_CTRL_DIRECT_ACCESS_WDATA_0
+ 4'b1111, // index[10] OTP_CTRL_DIRECT_ACCESS_WDATA_1
+ 4'b1111, // index[11] OTP_CTRL_DIRECT_ACCESS_RDATA_0
+ 4'b1111, // index[12] OTP_CTRL_DIRECT_ACCESS_RDATA_1
+ 4'b0001, // index[13] OTP_CTRL_CHECK_TRIGGER_REGWEN
+ 4'b0001, // index[14] OTP_CTRL_CHECK_TRIGGER
+ 4'b0001, // index[15] OTP_CTRL_CHECK_REGWEN
+ 4'b1111, // index[16] OTP_CTRL_CHECK_TIMEOUT
+ 4'b1111, // index[17] OTP_CTRL_INTEGRITY_CHECK_PERIOD
+ 4'b1111, // index[18] OTP_CTRL_CONSISTENCY_CHECK_PERIOD
+ 4'b0001, // index[19] OTP_CTRL_VENDOR_TEST_READ_LOCK
+ 4'b0001, // index[20] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK
+ 4'b0001, // index[21] OTP_CTRL_OWNER_SW_CFG_READ_LOCK
+ 4'b1111, // index[22] OTP_CTRL_VENDOR_TEST_DIGEST_0
+ 4'b1111, // index[23] OTP_CTRL_VENDOR_TEST_DIGEST_1
+ 4'b1111, // index[24] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0
+ 4'b1111, // index[25] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1
+ 4'b1111, // index[26] OTP_CTRL_OWNER_SW_CFG_DIGEST_0
+ 4'b1111, // index[27] OTP_CTRL_OWNER_SW_CFG_DIGEST_1
+ 4'b1111, // index[28] OTP_CTRL_HW_CFG_DIGEST_0
+ 4'b1111, // index[29] OTP_CTRL_HW_CFG_DIGEST_1
+ 4'b1111, // index[30] OTP_CTRL_SECRET0_DIGEST_0
+ 4'b1111, // index[31] OTP_CTRL_SECRET0_DIGEST_1
+ 4'b1111, // index[32] OTP_CTRL_SECRET1_DIGEST_0
+ 4'b1111, // index[33] OTP_CTRL_SECRET1_DIGEST_1
+ 4'b1111, // index[34] OTP_CTRL_SECRET2_DIGEST_0
+ 4'b1111 // index[35] OTP_CTRL_SECRET2_DIGEST_1
+ };
+
+endpackage
+
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_alert_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_alert_pkg.sv
new file mode 100644
index 00000000..a3594b61
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_alert_pkg.sv
@@ -0,0 +1,27 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package prim_alert_pkg;
+
+ typedef struct packed {
+ logic alert_p;
+ logic alert_n;
+ } alert_tx_t;
+
+ typedef struct packed {
+ logic ping_p;
+ logic ping_n;
+ logic ack_p;
+ logic ack_n;
+ } alert_rx_t;
+
+ parameter alert_tx_t ALERT_TX_DEFAULT = '{alert_p: 1'b0,
+ alert_n: 1'b1};
+
+ parameter alert_rx_t ALERT_RX_DEFAULT = '{ping_p: 1'b0,
+ ping_n: 1'b1,
+ ack_p: 1'b0,
+ ack_n: 1'b1};
+
+endpackage : prim_alert_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_alert_sender.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_alert_sender.sv
new file mode 100644
index 00000000..b9793596
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_alert_sender.sv
@@ -0,0 +1,239 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// The alert sender primitive module differentially encodes and transmits an
+// alert signal to the prim_alert_receiver module. An alert will be signalled
+// by a full handshake on alert_p/n and ack_p/n. The alert_req_i signal may
+// be continuously asserted, in which case the alert signalling handshake
+// will be repeatedly initiated.
+//
+// The alert_req_i signal may also be used as part of req/ack. The parent module
+// can keep alert_req_i asserted until it has been ack'd (transferred to the alert
+// receiver). The parent module is not required to use this.
+//
+// Further, this module supports in-band ping testing, which means that a level
+// change on the ping_p/n diff pair will result in a full-handshake response
+// on alert_p/n and ack_p/n.
+//
+// The protocol works in both asynchronous and synchronous cases. In the
+// asynchronous case, the parameter AsyncOn must be set to 1'b1 in order to
+// instantiate additional synchronization logic. Further, it must be ensured
+// that the timing skew between all diff pairs is smaller than the shortest
+// clock period of the involved clocks.
+//
+// Incorrectly encoded diff inputs can be detected and will be signalled
+// to the receiver by placing an inconsistent diff value on the differential
+// output (and continuously toggling it).
+//
+// See also: prim_alert_receiver, prim_diff_decode, alert_handler
+
+
+module prim_alert_sender
+ import prim_alert_pkg::*;
+#(parameter IsFatal = 1'b1,
+ // enables additional synchronization logic
+ parameter bit AsyncOn = 1'b1
+) (
+ input clk_i,
+ input rst_ni,
+ // native alert from the peripheral
+ input alert_req_i,
+ output logic alert_ack_o,
+ // ping input diff pair and ack diff pair
+ input alert_rx_t alert_rx_i,
+ // alert output diff pair
+ output alert_tx_t alert_tx_o
+);
+
+
+ /////////////////////////////////
+ // decode differential signals //
+ /////////////////////////////////
+ logic ping_sigint, ping_event;
+
+ prim_diff_decode #(
+ .AsyncOn(AsyncOn)
+ ) i_decode_ping (
+ .clk_i,
+ .rst_ni,
+ .diff_pi ( alert_rx_i.ping_p ),
+ .diff_ni ( alert_rx_i.ping_n ),
+ .level_o ( ),
+ .rise_o ( ),
+ .fall_o ( ),
+ .event_o ( ping_event ),
+ .sigint_o ( ping_sigint )
+ );
+
+ logic ack_sigint, ack_level;
+
+ prim_diff_decode #(
+ .AsyncOn(AsyncOn)
+ ) i_decode_ack (
+ .clk_i,
+ .rst_ni,
+ .diff_pi ( alert_rx_i.ack_p ),
+ .diff_ni ( alert_rx_i.ack_n ),
+ .level_o ( ack_level ),
+ .rise_o ( ),
+ .fall_o ( ),
+ .event_o ( ),
+ .sigint_o ( ack_sigint )
+ );
+
+
+ ///////////////////////////////////////////////////
+ // main protocol FSM that drives the diff output //
+ ///////////////////////////////////////////////////
+ typedef enum logic [2:0] {
+ Idle,
+ AlertHsPhase1,
+ AlertHsPhase2,
+ PingHsPhase1,
+ PingHsPhase2,
+ SigInt,
+ Pause0,
+ Pause1
+ } state_e;
+ state_e state_d, state_q;
+ logic alert_p, alert_n, alert_pq, alert_nq, alert_pd, alert_nd;
+ logic sigint_detected;
+
+ assign sigint_detected = ack_sigint | ping_sigint;
+
+
+ // diff pair output
+ assign alert_tx_o.alert_p = alert_pq;
+ assign alert_tx_o.alert_n = alert_nq;
+
+ // alert and ping set regs
+ logic alert_set_d, alert_set_q, alert_clr;
+ logic ping_set_d, ping_set_q, ping_clr;
+
+ // if handshake is ongoing, capture additional alert requests
+ assign alert_set_d = (alert_clr) ? 1'b0 : (alert_set_q | alert_req_i);
+ assign ping_set_d = (ping_clr) ? 1'b0 : (ping_set_q | ping_event);
+
+ // alert event acknowledge
+ assign alert_ack_o = alert_clr;
+
+ // this FSM performs a full four phase handshake upon a ping or alert trigger.
+ // note that the latency of the alert_p/n diff pair is at least one cycle
+ // until it enters the receiver FSM. the same holds for the ack_* diff pair
+ // input. in case a signal integrity issue is detected, the FSM bails out,
+ // sets the alert_p/n diff pair to the same value and toggles it in order to
+ // signal that condition over to the receiver.
+ always_comb begin : p_fsm
+ // default
+ state_d = state_q;
+ alert_p = 1'b0;
+ alert_n = 1'b1;
+ ping_clr = 1'b0;
+ alert_clr = 1'b0;
+
+ unique case (state_q)
+ Idle: begin
+ // alert always takes precedence
+ if (alert_req_i || alert_set_q || ping_event || ping_set_q) begin
+ state_d = (alert_req_i || alert_set_q) ? AlertHsPhase1 : PingHsPhase1;
+ alert_p = 1'b1;
+ alert_n = 1'b0;
+ end
+ end
+ // waiting for ack from receiver
+ AlertHsPhase1: begin
+ if (ack_level) begin
+ state_d = AlertHsPhase2;
+ end else begin
+ alert_p = 1'b1;
+ alert_n = 1'b0;
+ end
+ end
+ // wait for deassertion of ack
+ AlertHsPhase2: begin
+ if (!ack_level) begin
+ state_d = Pause0;
+ alert_clr = 1'b1;
+ end
+ end
+ // waiting for ack from receiver
+ PingHsPhase1: begin
+ if (ack_level) begin
+ state_d = PingHsPhase2;
+ end else begin
+ alert_p = 1'b1;
+ alert_n = 1'b0;
+ end
+ end
+ // wait for deassertion of ack
+ PingHsPhase2: begin
+ if (!ack_level) begin
+ ping_clr = 1'b1;
+ state_d = Pause0;
+ end
+ end
+ // pause cycles between back-to-back handshakes
+ Pause0: begin
+ state_d = Pause1;
+ end
+
+ // clear and ack alert request if it was set
+ Pause1: begin
+ state_d = Idle;
+ end
+
+ // we have a signal integrity issue at one of
+ // the incoming diff pairs. this condition is
+ // signalled by setting the output diffpair
+ // to the same value and continuously toggling
+ // them.
+ SigInt: begin
+ state_d = Idle;
+ if (sigint_detected) begin
+ state_d = SigInt;
+ alert_p = ~alert_pq;
+ alert_n = ~alert_pq;
+ end
+ end
+ // catch parasitic states
+ default : state_d = Idle;
+ endcase
+ // bail out if a signal integrity issue has been detected
+ if (sigint_detected && (state_q != SigInt)) begin
+ state_d = SigInt;
+ alert_p = 1'b0;
+ alert_n = 1'b0;
+ ping_clr = 1'b0;
+ alert_clr = 1'b0;
+ end
+ end
+
+ // This prevents further tool optimizations of the differential signal.
+ prim_buf u_prim_buf_p (
+ .in_i(alert_p),
+ .out_o(alert_pd)
+ );
+ prim_buf u_prim_buf_n (
+ .in_i(alert_n),
+ .out_o(alert_nd)
+ );
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg
+ if (!rst_ni) begin
+ state_q <= Idle;
+ alert_pq <= 1'b0;
+ alert_nq <= 1'b1;
+ alert_set_q <= 1'b0;
+ ping_set_q <= 1'b0;
+ end else begin
+ state_q <= state_d;
+ alert_pq <= alert_pd;
+ alert_nq <= alert_nd;
+ alert_set_q <= alert_set_d;
+ ping_set_q <= ping_set_d;
+ end
+ end
+
+
+endmodule : prim_alert_sender
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_buf.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_buf.sv
new file mode 100644
index 00000000..60773881
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_buf.sv
@@ -0,0 +1,37 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is auto-generated.
+
+
+
+
+
+// This is to prevent AscentLint warnings in the generated
+// abstract prim wrapper. These warnings occur due to the .*
+// use. TODO: we may want to move these inline waivers
+// into a separate, generated waiver file for consistency.
+//ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
+module prim_buf
+
+#(
+parameter Width = 1
+) (
+ input in_i,
+ output logic out_o
+);
+ parameter prim_pkg::impl_e Impl = prim_pkg::ImplGeneric;
+
+if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx
+ prim_xilinx_buf u_impl_xilinx (
+ .*
+ );
+end else begin : gen_generic
+ prim_generic_buf u_impl_generic (
+ .*
+ );
+end
+
+endmodule
+//ri lint_check_on OUTPUT_NOT_DRIVEN INPUT_NOT_READ
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_cipher_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_cipher_pkg.sv
new file mode 100644
index 00000000..372baa02
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_cipher_pkg.sv
@@ -0,0 +1,397 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This package holds common constants and functions for PRESENT- and
+// PRINCE-based scrambling devices.
+//
+// See also: prim_present, prim_prince
+//
+// References: - https://en.wikipedia.org/wiki/PRESENT
+// - https://en.wikipedia.org/wiki/Prince_(cipher)
+// - http://www.lightweightcrypto.org/present/present_ches2007.pdf
+// - https://eprint.iacr.org/2012/529.pdf
+// - https://eprint.iacr.org/2015/372.pdf
+// - https://eprint.iacr.org/2014/656.pdf
+
+package prim_cipher_pkg;
+
+ ///////////////////
+ // PRINCE Cipher //
+ ///////////////////
+
+ parameter logic [15:0][3:0] PRINCE_SBOX4 = {4'h4, 4'hD, 4'h5, 4'hE,
+ 4'h0, 4'h8, 4'h7, 4'h6,
+ 4'h1, 4'h9, 4'hC, 4'hA,
+ 4'h2, 4'h3, 4'hF, 4'hB};
+
+ parameter logic [15:0][3:0] PRINCE_SBOX4_INV = {4'h1, 4'hC, 4'hE, 4'h5,
+ 4'h0, 4'h4, 4'h6, 4'hA,
+ 4'h9, 4'h8, 4'hD, 4'hF,
+ 4'h2, 4'h3, 4'h7, 4'hB};
+ // nibble permutations
+ parameter logic [15:0][3:0] PRINCE_SHIFT_ROWS64 = '{4'hF, 4'hA, 4'h5, 4'h0,
+ 4'hB, 4'h6, 4'h1, 4'hC,
+ 4'h7, 4'h2, 4'hD, 4'h8,
+ 4'h3, 4'hE, 4'h9, 4'h4};
+
+ parameter logic [15:0][3:0] PRINCE_SHIFT_ROWS64_INV = '{4'hF, 4'h2, 4'h5, 4'h8,
+ 4'hB, 4'hE, 4'h1, 4'h4,
+ 4'h7, 4'hA, 4'hD, 4'h0,
+ 4'h3, 4'h6, 4'h9, 4'hC};
+
+ // these are the round constants
+ parameter logic [11:0][63:0] PRINCE_ROUND_CONST = {64'hC0AC29B7C97C50DD,
+ 64'hD3B5A399CA0C2399,
+ 64'h64A51195E0E3610D,
+ 64'hC882D32F25323C54,
+ 64'h85840851F1AC43AA,
+ 64'h7EF84F78FD955CB1,
+ 64'hBE5466CF34E90C6C,
+ 64'h452821E638D01377,
+ 64'h082EFA98EC4E6C89,
+ 64'hA4093822299F31D0,
+ 64'h13198A2E03707344,
+ 64'h0000000000000000};
+
+ // tweak constant for key modification between enc/dec modes
+ parameter logic [63:0] PRINCE_ALPHA_CONST = 64'hC0AC29B7C97C50DD;
+
+ // masking constants for shift rows function below
+ parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST0 = 16'h7BDE;
+ parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST1 = 16'hBDE7;
+ parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST2 = 16'hDE7B;
+ parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST3 = 16'hE7BD;
+
+ // nibble shifts
+ function automatic logic [31:0] prince_shiftrows_32bit(logic [31:0] state_in,
+ logic [15:0][3:0] shifts );
+ logic [31:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 32/2; k++) begin
+ // operate on pairs of 2bit instead of nibbles
+ state_out[k*2 +: 2] = state_in[shifts[k]*2 +: 2];
+ end
+ return state_out;
+ endfunction : prince_shiftrows_32bit
+
+ function automatic logic [63:0] prince_shiftrows_64bit(logic [63:0] state_in,
+ logic [15:0][3:0] shifts );
+ logic [63:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 64/4; k++) begin
+ state_out[k*4 +: 4] = state_in[shifts[k]*4 +: 4];
+ end
+ return state_out;
+ endfunction : prince_shiftrows_64bit
+
+ // XOR reduction of four nibbles in a 16bit subvector
+ function automatic logic [3:0] prince_nibble_red16(logic [15:0] vect);
+ return vect[0 +: 4] ^ vect[4 +: 4] ^ vect[8 +: 4] ^ vect[12 +: 4];
+ endfunction : prince_nibble_red16
+
+ // M prime multiplication
+ function automatic logic [31:0] prince_mult_prime_32bit(logic [31:0] state_in);
+ logic [31:0] state_out;
+ // M0
+ state_out[0 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[4 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[8 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ state_out[12 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ // M1
+ state_out[16 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ state_out[20 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[24 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[28 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ return state_out;
+ endfunction : prince_mult_prime_32bit
+
+ // M prime multiplication
+ function automatic logic [63:0] prince_mult_prime_64bit(logic [63:0] state_in);
+ logic [63:0] state_out;
+ // M0
+ state_out[0 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[4 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[8 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ state_out[12 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ // M1
+ state_out[16 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ state_out[20 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[24 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[28 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ // M1
+ state_out[32 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ state_out[36 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[40 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[44 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ // M0
+ state_out[48 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[52 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[56 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ state_out[60 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ return state_out;
+ endfunction : prince_mult_prime_64bit
+
+
+ ////////////////////
+ // PRESENT Cipher //
+ ////////////////////
+
+ // this is the sbox from the present cipher
+ parameter logic [15:0][3:0] PRESENT_SBOX4 = {4'h2, 4'h1, 4'h7, 4'h4,
+ 4'h8, 4'hF, 4'hE, 4'h3,
+ 4'hD, 4'hA, 4'h0, 4'h9,
+ 4'hB, 4'h6, 4'h5, 4'hC};
+
+ parameter logic [15:0][3:0] PRESENT_SBOX4_INV = {4'hA, 4'h9, 4'h7, 4'h0,
+ 4'h3, 4'h6, 4'h4, 4'hB,
+ 4'hD, 4'h2, 4'h1, 4'hC,
+ 4'h8, 4'hF, 4'hE, 4'h5};
+
+ // these are modified permutation indices for a 32bit version that
+ // follow the same pattern as for the 64bit version
+ parameter logic [31:0][4:0] PRESENT_PERM32 = {5'd31, 5'd23, 5'd15, 5'd07,
+ 5'd30, 5'd22, 5'd14, 5'd06,
+ 5'd29, 5'd21, 5'd13, 5'd05,
+ 5'd28, 5'd20, 5'd12, 5'd04,
+ 5'd27, 5'd19, 5'd11, 5'd03,
+ 5'd26, 5'd18, 5'd10, 5'd02,
+ 5'd25, 5'd17, 5'd09, 5'd01,
+ 5'd24, 5'd16, 5'd08, 5'd00};
+
+ parameter logic [31:0][4:0] PRESENT_PERM32_INV = {5'd31, 5'd27, 5'd23, 5'd19,
+ 5'd15, 5'd11, 5'd07, 5'd03,
+ 5'd30, 5'd26, 5'd22, 5'd18,
+ 5'd14, 5'd10, 5'd06, 5'd02,
+ 5'd29, 5'd25, 5'd21, 5'd17,
+ 5'd13, 5'd09, 5'd05, 5'd01,
+ 5'd28, 5'd24, 5'd20, 5'd16,
+ 5'd12, 5'd08, 5'd04, 5'd00};
+
+ // these are the permutation indices of the present cipher
+ parameter logic [63:0][5:0] PRESENT_PERM64 = {6'd63, 6'd47, 6'd31, 6'd15,
+ 6'd62, 6'd46, 6'd30, 6'd14,
+ 6'd61, 6'd45, 6'd29, 6'd13,
+ 6'd60, 6'd44, 6'd28, 6'd12,
+ 6'd59, 6'd43, 6'd27, 6'd11,
+ 6'd58, 6'd42, 6'd26, 6'd10,
+ 6'd57, 6'd41, 6'd25, 6'd09,
+ 6'd56, 6'd40, 6'd24, 6'd08,
+ 6'd55, 6'd39, 6'd23, 6'd07,
+ 6'd54, 6'd38, 6'd22, 6'd06,
+ 6'd53, 6'd37, 6'd21, 6'd05,
+ 6'd52, 6'd36, 6'd20, 6'd04,
+ 6'd51, 6'd35, 6'd19, 6'd03,
+ 6'd50, 6'd34, 6'd18, 6'd02,
+ 6'd49, 6'd33, 6'd17, 6'd01,
+ 6'd48, 6'd32, 6'd16, 6'd00};
+
+ parameter logic [63:0][5:0] PRESENT_PERM64_INV = {6'd63, 6'd59, 6'd55, 6'd51,
+ 6'd47, 6'd43, 6'd39, 6'd35,
+ 6'd31, 6'd27, 6'd23, 6'd19,
+ 6'd15, 6'd11, 6'd07, 6'd03,
+ 6'd62, 6'd58, 6'd54, 6'd50,
+ 6'd46, 6'd42, 6'd38, 6'd34,
+ 6'd30, 6'd26, 6'd22, 6'd18,
+ 6'd14, 6'd10, 6'd06, 6'd02,
+ 6'd61, 6'd57, 6'd53, 6'd49,
+ 6'd45, 6'd41, 6'd37, 6'd33,
+ 6'd29, 6'd25, 6'd21, 6'd17,
+ 6'd13, 6'd09, 6'd05, 6'd01,
+ 6'd60, 6'd56, 6'd52, 6'd48,
+ 6'd44, 6'd40, 6'd36, 6'd32,
+ 6'd28, 6'd24, 6'd20, 6'd16,
+ 6'd12, 6'd08, 6'd04, 6'd00};
+
+ // forward key schedule
+ function automatic logic [63:0] present_update_key64(logic [63:0] key_in,
+ logic [4:0] round_idx);
+ logic [63:0] key_out;
+ // rotate by 61 to the left
+ key_out = {key_in[63-61:0], key_in[63:64-61]};
+ // sbox on uppermost 4 bits
+ key_out[63 -: 4] = PRESENT_SBOX4[key_out[63 -: 4]];
+ // xor in round counter on bits 19 to 15
+ key_out[19:15] ^= round_idx;
+ return key_out;
+ endfunction : present_update_key64
+
+ function automatic logic [79:0] present_update_key80(logic [79:0] key_in,
+ logic [4:0] round_idx);
+ logic [79:0] key_out;
+ // rotate by 61 to the left
+ key_out = {key_in[79-61:0], key_in[79:80-61]};
+ // sbox on uppermost 4 bits
+ key_out[79 -: 4] = PRESENT_SBOX4[key_out[79 -: 4]];
+ // xor in round counter on bits 19 to 15
+ key_out[19:15] ^= round_idx;
+ return key_out;
+ endfunction : present_update_key80
+
+ function automatic logic [127:0] present_update_key128(logic [127:0] key_in,
+ logic [4:0] round_idx);
+ logic [127:0] key_out;
+ // rotate by 61 to the left
+ key_out = {key_in[127-61:0], key_in[127:128-61]};
+ // sbox on uppermost 4 bits
+ key_out[127 -: 4] = PRESENT_SBOX4[key_out[127 -: 4]];
+ // sbox on second nibble from top
+ key_out[123 -: 4] = PRESENT_SBOX4[key_out[123 -: 4]];
+ // xor in round counter on bits 66 to 62
+ key_out[66:62] ^= round_idx;
+ return key_out;
+ endfunction : present_update_key128
+
+
+ // inverse key schedule
+ function automatic logic [63:0] present_inv_update_key64(logic [63:0] key_in,
+ logic [4:0] round_idx);
+ logic [63:0] key_out = key_in;
+ // xor in round counter on bits 19 to 15
+ key_out[19:15] ^= round_idx;
+ // sbox on uppermost 4 bits
+ key_out[63 -: 4] = PRESENT_SBOX4_INV[key_out[63 -: 4]];
+ // rotate by 61 to the right
+ key_out = {key_out[60:0], key_out[63:61]};
+ return key_out;
+ endfunction : present_inv_update_key64
+
+ function automatic logic [79:0] present_inv_update_key80(logic [79:0] key_in,
+ logic [4:0] round_idx);
+ logic [79:0] key_out = key_in;
+ // xor in round counter on bits 19 to 15
+ key_out[19:15] ^= round_idx;
+ // sbox on uppermost 4 bits
+ key_out[79 -: 4] = PRESENT_SBOX4_INV[key_out[79 -: 4]];
+ // rotate by 61 to the right
+ key_out = {key_out[60:0], key_out[79:61]};
+ return key_out;
+ endfunction : present_inv_update_key80
+
+ function automatic logic [127:0] present_inv_update_key128(logic [127:0] key_in,
+ logic [4:0] round_idx);
+ logic [127:0] key_out = key_in;
+ // xor in round counter on bits 66 to 62
+ key_out[66:62] ^= round_idx;
+ // sbox on second highest nibble
+ key_out[123 -: 4] = PRESENT_SBOX4_INV[key_out[123 -: 4]];
+ // sbox on uppermost 4 bits
+ key_out[127 -: 4] = PRESENT_SBOX4_INV[key_out[127 -: 4]];
+ // rotate by 61 to the right
+ key_out = {key_out[60:0], key_out[127:61]};
+ return key_out;
+ endfunction : present_inv_update_key128
+
+
+ // these functions can be used to derive the DEC key from the ENC key by
+ // stepping the key by the correct number of rounds using the keyschedule functions above.
+ function automatic logic [63:0] present_get_dec_key64(logic [63:0] key_in,
+ // total number of rounds employed
+ logic [4:0] round_cnt);
+ logic [63:0] key_out;
+ key_out = key_in;
+ for (int unsigned k = 0; k < round_cnt; k++) begin
+ key_out = present_update_key64(key_out, 5'(k + 1));
+ end
+ return key_out;
+ endfunction : present_get_dec_key64
+
+ function automatic logic [79:0] present_get_dec_key80(logic [79:0] key_in,
+ // total number of rounds employed
+ logic [4:0] round_cnt);
+ logic [79:0] key_out;
+ key_out = key_in;
+ for (int unsigned k = 0; k < round_cnt; k++) begin
+ key_out = present_update_key80(key_out, 5'(k + 1));
+ end
+ return key_out;
+ endfunction : present_get_dec_key80
+
+ function automatic logic [127:0] present_get_dec_key128(logic [127:0] key_in,
+ // total number of rounds employed
+ logic [4:0] round_cnt);
+ logic [127:0] key_out;
+ key_out = key_in;
+ for (int unsigned k = 0; k < round_cnt; k++) begin
+ key_out = present_update_key128(key_out, 5'(k + 1));
+ end
+ return key_out;
+ endfunction : present_get_dec_key128
+
+ /////////////////////////
+ // Common Subfunctions //
+ /////////////////////////
+
+ function automatic logic [7:0] sbox4_8bit(logic [7:0] state_in, logic [15:0][3:0] sbox4);
+ logic [7:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 8/4; k++) begin
+ state_out[k*4 +: 4] = sbox4[state_in[k*4 +: 4]];
+ end
+ return state_out;
+ endfunction : sbox4_8bit
+
+ function automatic logic [15:0] sbox4_16bit(logic [15:0] state_in, logic [15:0][3:0] sbox4);
+ logic [15:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 2; k++) begin
+ state_out[k*8 +: 8] = sbox4_8bit(state_in[k*8 +: 8], sbox4);
+ end
+ return state_out;
+ endfunction : sbox4_16bit
+
+ function automatic logic [31:0] sbox4_32bit(logic [31:0] state_in, logic [15:0][3:0] sbox4);
+ logic [31:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 4; k++) begin
+ state_out[k*8 +: 8] = sbox4_8bit(state_in[k*8 +: 8], sbox4);
+ end
+ return state_out;
+ endfunction : sbox4_32bit
+
+ function automatic logic [63:0] sbox4_64bit(logic [63:0] state_in, logic [15:0][3:0] sbox4);
+ logic [63:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 8; k++) begin
+ state_out[k*8 +: 8] = sbox4_8bit(state_in[k*8 +: 8], sbox4);
+ end
+ return state_out;
+ endfunction : sbox4_64bit
+
+ function automatic logic [7:0] perm_8bit(logic [7:0] state_in, logic [7:0][2:0] perm);
+ logic [7:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 8; k++) begin
+ state_out[perm[k]] = state_in[k];
+ end
+ return state_out;
+ endfunction : perm_8bit
+
+ function automatic logic [15:0] perm_16bit(logic [15:0] state_in, logic [15:0][3:0] perm);
+ logic [15:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 16; k++) begin
+ state_out[perm[k]] = state_in[k];
+ end
+ return state_out;
+ endfunction : perm_16bit
+
+ function automatic logic [31:0] perm_32bit(logic [31:0] state_in, logic [31:0][4:0] perm);
+ logic [31:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 32; k++) begin
+ state_out[perm[k]] = state_in[k];
+ end
+ return state_out;
+ endfunction : perm_32bit
+
+ function automatic logic [63:0] perm_64bit(logic [63:0] state_in, logic [63:0][5:0] perm);
+ logic [63:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 64; k++) begin
+ state_out[perm[k]] = state_in[k];
+ end
+ return state_out;
+ endfunction : perm_64bit
+
+endpackage : prim_cipher_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_count_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_count_pkg.sv
new file mode 100644
index 00000000..f49a270c
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_count_pkg.sv
@@ -0,0 +1,22 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Package for primitive hardened counter module
+//
+
+package prim_count_pkg;
+
+ // Enumeration for hardened count style
+ typedef enum logic {
+ CrossCnt, // up count and down count
+ DupCnt // duplicate counters
+ } prim_count_style_e;
+
+ // Enumeration for differential valid
+ typedef enum logic [1:0] {
+ CmpInvalid = 2'b01,
+ CmpValid = 2'b10
+ } cmp_valid_e;
+
+endpackage //
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_diff_decode.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_diff_decode.sv
new file mode 100644
index 00000000..780cb0bc
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_diff_decode.sv
@@ -0,0 +1,207 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This module decodes a differentially encoded signal and detects
+// incorrectly encoded differential states.
+//
+// In case the differential pair crosses an asynchronous boundary, it has
+// to be re-synchronized to the local clock. This can be achieved by
+// setting the AsyncOn parameter to 1'b1. In that case, two additional
+// input registers are added (to counteract metastability), and
+// a pattern detector is instantiated that detects skewed level changes on
+// the differential pair (i.e., when level changes on the diff pair are
+// sampled one cycle apart due to a timing skew between the two wires).
+//
+// See also: prim_alert_sender, prim_alert_receiver, alert_handler
+
+
+module prim_diff_decode #(
+ // enables additional synchronization logic
+ parameter bit AsyncOn = 1'b0
+) (
+ input clk_i,
+ input rst_ni,
+ // input diff pair
+ input diff_pi,
+ input diff_ni,
+ // logical level and
+ // detected edges
+ output logic level_o,
+ output logic rise_o,
+ output logic fall_o,
+ // either rise or fall
+ output logic event_o,
+ //signal integrity issue detected
+ output logic sigint_o
+);
+
+ logic level_d, level_q;
+
+ ///////////////////////////////////////////////////////////////
+ // synchronization regs for incoming diff pair (if required) //
+ ///////////////////////////////////////////////////////////////
+ if (AsyncOn) begin : gen_async
+
+ typedef enum logic [1:0] {IsStd, IsSkewed, SigInt} state_e;
+ state_e state_d, state_q;
+ logic diff_p_edge, diff_n_edge, diff_check_ok, level;
+
+ // 2 sync regs, one reg for edge detection
+ logic diff_pq, diff_nq, diff_pd, diff_nd;
+
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue(0)
+ ) i_sync_p (
+ .clk_i,
+ .rst_ni,
+ .d_i(diff_pi),
+ .q_o(diff_pd)
+ );
+
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue(1)
+ ) i_sync_n (
+ .clk_i,
+ .rst_ni,
+ .d_i(diff_ni),
+ .q_o(diff_nd)
+ );
+
+ // detect level transitions
+ assign diff_p_edge = diff_pq ^ diff_pd;
+ assign diff_n_edge = diff_nq ^ diff_nd;
+
+ // detect sigint issue
+ assign diff_check_ok = diff_pd ^ diff_nd;
+
+ // this is the current logical level
+ assign level = diff_pd;
+
+ // outputs
+ assign level_o = level_d;
+ assign event_o = rise_o | fall_o;
+
+ // sigint detection is a bit more involved in async case since
+ // we might have skew on the diff pair, which can result in a
+ // one cycle sampling delay between the two wires
+ // so we need a simple pattern matcher
+ // the following waves are legal
+ // clk | | | | | | | |
+ // _______ _______
+ // p _______/ ... \________
+ // _______ ________
+ // n \_______ ... _______/
+ // ____ ___
+ // p __________/ ... \________
+ // _______ ________
+ // n \_______ ... _______/
+ //
+ // i.e., level changes may be off by one cycle - which is permissible
+ // as long as this condition is only one cycle long.
+
+
+ always_comb begin : p_diff_fsm
+ // default
+ state_d = state_q;
+ level_d = level_q;
+ rise_o = 1'b0;
+ fall_o = 1'b0;
+ sigint_o = 1'b0;
+
+ unique case (state_q)
+ // we remain here as long as
+ // the diff pair is correctly encoded
+ IsStd: begin
+ if (diff_check_ok) begin
+ level_d = level;
+ if (diff_p_edge && diff_n_edge) begin
+ if (level) begin
+ rise_o = 1'b1;
+ end else begin
+ fall_o = 1'b1;
+ end
+ end
+ end else begin
+ if (diff_p_edge || diff_n_edge) begin
+ state_d = IsSkewed;
+ end else begin
+ state_d = SigInt;
+ sigint_o = 1'b1;
+ end
+ end
+ end
+ // diff pair must be correctly encoded, otherwise we got a sigint
+ IsSkewed: begin
+ if (diff_check_ok) begin
+ state_d = IsStd;
+ level_d = level;
+ if (level) rise_o = 1'b1;
+ else fall_o = 1'b1;
+ end else begin
+ state_d = SigInt;
+ sigint_o = 1'b1;
+ end
+ end
+ // Signal integrity issue detected, remain here
+ // until resolved
+ SigInt: begin
+ sigint_o = 1'b1;
+ if (diff_check_ok) begin
+ state_d = IsStd;
+ sigint_o = 1'b0;
+ end
+ end
+ default : ;
+ endcase
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_sync_reg
+ if (!rst_ni) begin
+ state_q <= IsStd;
+ diff_pq <= 1'b0;
+ diff_nq <= 1'b1;
+ level_q <= 1'b0;
+ end else begin
+ state_q <= state_d;
+ diff_pq <= diff_pd;
+ diff_nq <= diff_nd;
+ level_q <= level_d;
+ end
+ end
+
+ //////////////////////////////////////////////////////////
+ // fully synchronous case, no skew present in this case //
+ //////////////////////////////////////////////////////////
+ end else begin : gen_no_async
+ logic diff_pq, diff_pd;
+
+ // one reg for edge detection
+ assign diff_pd = diff_pi;
+
+ // incorrect encoding -> signal integrity issue
+ assign sigint_o = ~(diff_pi ^ diff_ni);
+
+ assign level_o = (sigint_o) ? level_q : diff_pi;
+ assign level_d = level_o;
+
+ // detect level transitions
+ assign rise_o = (~diff_pq & diff_pi) & ~sigint_o;
+ assign fall_o = ( diff_pq & ~diff_pi) & ~sigint_o;
+ assign event_o = rise_o | fall_o;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_edge_reg
+ if (!rst_ni) begin
+ diff_pq <= 1'b0;
+ level_q <= 1'b0;
+ end else begin
+ diff_pq <= diff_pd;
+ level_q <= level_d;
+ end
+ end
+ end
+
+
+endmodule : prim_diff_decode
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_fifo_sync.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_fifo_sync.sv
new file mode 100644
index 00000000..9bc0bff3
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_fifo_sync.sv
@@ -0,0 +1,148 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Generic synchronous fifo for use in a variety of devices.
+module prim_fifo_sync #(
+ parameter int unsigned Width = 16,
+ parameter bit Pass = 1'b1, // if == 1 allow requests to pass through empty FIFO
+ parameter int unsigned Depth = 4,
+ parameter bit OutputZeroIfEmpty = 1'b1, // if == 1 always output 0 when FIFO is empty
+ // derived parameter
+ localparam int unsigned DepthWNorm = $clog2(Depth+1),
+ localparam int unsigned DepthW = (DepthWNorm == 0) ? 1 : DepthWNorm
+) (
+ input clk_i,
+ input rst_ni,
+ // synchronous clear / flush port
+ input clr_i,
+ // write port
+ input wvalid,
+ output wready,
+ input [Width-1:0] wdata,
+ // read port
+ output rvalid,
+ input rready,
+ output [Width-1:0] rdata,
+ // occupancy
+ output [DepthW-1:0] depth
+);
+
+ // FIFO is in complete passthrough mode
+ if (Depth == 0) begin : gen_passthru_fifo
+
+ assign depth = 1'b0; //output is meaningless
+
+ // devie facing
+ assign rvalid = wvalid;
+ assign rdata = wdata;
+
+ // host facing
+ assign wready = rready;
+
+ // this avoids lint warnings
+ logic unused_clr;
+ assign unused_clr = clr_i;
+
+ // Normal FIFO construction
+ end else begin : gen_normal_fifo
+
+ // consider Depth == 1 case when $clog2(1) == 0
+ localparam int unsigned PTRV_W = $clog2(Depth) + ~|$clog2(Depth);
+ localparam int unsigned PTR_WIDTH = PTRV_W+1;
+
+ logic [PTR_WIDTH-1:0] fifo_wptr, fifo_rptr;
+ logic fifo_incr_wptr, fifo_incr_rptr, fifo_empty;
+
+ // create the write and read pointers
+ logic full, empty;
+ logic wptr_msb;
+ logic rptr_msb;
+ logic [PTRV_W-1:0] wptr_value;
+ logic [PTRV_W-1:0] rptr_value;
+
+ assign wptr_msb = fifo_wptr[PTR_WIDTH-1];
+ assign rptr_msb = fifo_rptr[PTR_WIDTH-1];
+ assign wptr_value = fifo_wptr[0+:PTRV_W];
+ assign rptr_value = fifo_rptr[0+:PTRV_W];
+ assign depth = (full) ? DepthW'(Depth) :
+ (wptr_msb == rptr_msb) ? DepthW'(wptr_value) - DepthW'(rptr_value) :
+ (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_value)) ;
+
+ assign fifo_incr_wptr = wvalid & wready;
+ assign fifo_incr_rptr = rvalid & rready;
+
+ assign wready = ~full;
+ assign rvalid = ~empty;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_wptr <= {(PTR_WIDTH){1'b0}};
+ end else if (clr_i) begin
+ fifo_wptr <= {(PTR_WIDTH){1'b0}};
+ end else if (fifo_incr_wptr) begin
+ if (fifo_wptr[PTR_WIDTH-2:0] == (Depth-1)) begin
+ fifo_wptr <= {~fifo_wptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}};
+ end else begin
+ fifo_wptr <= fifo_wptr + {{(PTR_WIDTH-1){1'b0}},1'b1};
+ end
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_rptr <= {(PTR_WIDTH){1'b0}};
+ end else if (clr_i) begin
+ fifo_rptr <= {(PTR_WIDTH){1'b0}};
+ end else if (fifo_incr_rptr) begin
+ if (fifo_rptr[PTR_WIDTH-2:0] == (Depth-1)) begin
+ fifo_rptr <= {~fifo_rptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}};
+ end else begin
+ fifo_rptr <= fifo_rptr + {{(PTR_WIDTH-1){1'b0}},1'b1};
+ end
+ end
+ end
+
+ assign full = (fifo_wptr == (fifo_rptr ^ {1'b1,{(PTR_WIDTH-1){1'b0}}}));
+ assign fifo_empty = (fifo_wptr == fifo_rptr);
+
+
+ // the generate blocks below are needed to avoid lint errors due to array indexing
+ // in the where the fifo only has one storage element
+ logic [Depth-1:0][Width-1:0] storage;
+ logic [Width-1:0] storage_rdata;
+ if (Depth == 1) begin : gen_depth_eq1
+ assign storage_rdata = storage[0];
+
+ always_ff @(posedge clk_i)
+ if (fifo_incr_wptr) begin
+ storage[0] <= wdata;
+ end
+ // fifo with more than one storage element
+ end else begin : gen_depth_gt1
+ assign storage_rdata = storage[fifo_rptr[PTR_WIDTH-2:0]];
+
+ always_ff @(posedge clk_i)
+ if (fifo_incr_wptr) begin
+ storage[fifo_wptr[PTR_WIDTH-2:0]] <= wdata;
+ end
+ end
+
+ logic [Width-1:0] rdata_int;
+ if (Pass == 1'b1) begin : gen_pass
+ assign rdata_int = (fifo_empty && wvalid) ? wdata : storage_rdata;
+ assign empty = fifo_empty & ~wvalid;
+ end else begin : gen_nopass
+ assign rdata_int = storage_rdata;
+ assign empty = fifo_empty;
+ end
+
+ if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
+ assign rdata = empty ? 'b0 : rdata_int;
+ end else begin : gen_no_output_zero
+ assign rdata = rdata_int;
+ end
+ end // block: gen_normal_fifo
+
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_flop_2sync.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_flop_2sync.sv
new file mode 100644
index 00000000..3665c804
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_flop_2sync.sv
@@ -0,0 +1,39 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is auto-generated.
+
+
+// This is to prevent AscentLint warnings in the generated
+// abstract prim wrapper. These warnings occur due to the .*
+// use. TODO: we may want to move these inline waivers
+// into a separate, generated waiver file for consistency.
+//ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
+module prim_flop_2sync
+
+#(
+
+ parameter int Width = 16,
+ localparam int WidthSubOne = Width-1, // temp work around #2679
+ parameter logic [WidthSubOne:0] ResetValue = '0
+
+) (
+ input clk_i, // receive clock
+ input rst_ni,
+ input [Width-1:0] d_i,
+ output logic [Width-1:0] q_o
+);
+
+ if (1) begin : gen_generic
+ prim_generic_flop_2sync #(
+ .ResetValue(ResetValue),
+ .Width(Width)
+ ) u_impl_generic (
+ .*
+ );
+
+ end
+
+endmodule
+//ri lint_check_on OUTPUT_NOT_DRIVEN INPUT_NOT_READ
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_generic_buf.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_generic_buf.sv
new file mode 100644
index 00000000..b2b4cb54
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_generic_buf.sv
@@ -0,0 +1,13 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+module prim_generic_buf (
+ input in_i,
+ output logic out_o
+);
+
+ assign out_o = in_i;
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_generic_flop.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_generic_flop.sv
new file mode 100644
index 00000000..8eacf015
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_generic_flop.sv
@@ -0,0 +1,26 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// `include "prim_assert.sv"
+
+module prim_generic_flop # (
+ parameter int Width = 1,
+ localparam int WidthSubOne = Width-1,
+ parameter logic [WidthSubOne:0] ResetValue = 0
+) (
+ input clk_i,
+ input rst_ni,
+ input [Width-1:0] d_i,
+ output logic [Width-1:0] q_o
+);
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ q_o <= ResetValue;
+ end else begin
+ q_o <= d_i;
+ end
+ end
+
+endmodule // prim_generic_flop
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_generic_flop_2sync.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_generic_flop_2sync.sv
new file mode 100644
index 00000000..fdd1358d
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_generic_flop_2sync.sv
@@ -0,0 +1,43 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Generic double-synchronizer flop
+// This may need to be moved to prim_generic if libraries have a specific cell
+// for synchronization
+
+module prim_generic_flop_2sync #(
+ parameter int Width = 16,
+ localparam int WidthSubOne = Width-1, // temp work around #2679
+ parameter logic [WidthSubOne:0] ResetValue = '0
+) (
+ input clk_i, // receive clock
+ input rst_ni,
+ input [Width-1:0] d_i,
+ output logic [Width-1:0] q_o
+);
+
+ logic [Width-1:0] intq;
+
+ prim_generic_flop #(
+ .Width(Width),
+ .ResetValue(ResetValue)
+ ) u_sync_1 (
+ .clk_i,
+ .rst_ni,
+ .d_i,
+ .q_o(intq)
+ );
+
+ prim_generic_flop #(
+ .Width(Width),
+ .ResetValue(ResetValue)
+ ) u_sync_2 (
+ .clk_i,
+ .rst_ni,
+ .d_i(intq),
+ .q_o
+ );
+
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_intr_hw.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_intr_hw.sv
new file mode 100644
index 00000000..be09a7c8
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_intr_hw.sv
@@ -0,0 +1,58 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Primitive interrupt handler. This assumes the existence of three
+// controller registers: INTR_ENABLE, INTR_STATE, INTR_TEST.
+// This module can be instantiated once per interrupt field, or
+// "bussified" with all fields of the interrupt vector.
+
+module prim_intr_hw # (
+ parameter int unsigned Width = 1,
+ parameter bit FlopOutput = 1
+) (
+ // event
+ input clk_i,
+ input rst_ni,
+ input [Width-1:0] event_intr_i,
+
+ // register interface
+ input [Width-1:0] reg2hw_intr_enable_q_i,
+ input [Width-1:0] reg2hw_intr_test_q_i,
+ input reg2hw_intr_test_qe_i,
+ input [Width-1:0] reg2hw_intr_state_q_i,
+ output hw2reg_intr_state_de_o,
+ output [Width-1:0] hw2reg_intr_state_d_o,
+
+ // outgoing interrupt
+ output logic [Width-1:0] intr_o
+);
+
+ logic [Width-1:0] new_event;
+ assign new_event =
+ (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
+ assign hw2reg_intr_state_de_o = |new_event;
+ // for scalar interrupts, this resolves to '1' with new event
+ // for vector interrupts, new events are OR'd in to existing interrupt state
+ assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i;
+
+ if (FlopOutput == 1) begin : gen_flop_intr_output
+ // flop the interrupt output
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intr_o <= '0;
+ end else begin
+ intr_o <= reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i;
+ end
+ end
+
+ end else begin : gen_intr_passthrough_output
+ logic unused_clk;
+ logic unused_rst_n;
+ assign unused_clk = clk_i;
+ assign unused_rst_n = rst_ni;
+ assign intr_o = reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i;
+ end
+
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_mubi_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_mubi_pkg.sv
new file mode 100644
index 00000000..e74dddc4
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_mubi_pkg.sv
@@ -0,0 +1,531 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/design/gen-mubi.py
+//
+// This package defines common multibit signal types, active high and active low values and
+// the corresponding functions to test whether the values are set or not.
+
+package prim_mubi_pkg;
+
+ //////////////////////////////////////////////
+ // 4 Bit Multibit Type and Functions //
+ //////////////////////////////////////////////
+
+ parameter int MuBi4Width = 4;
+ typedef enum logic [MuBi4Width-1:0] {
+ MuBi4True = 4'hA, // enabled
+ MuBi4False = 4'h5 // disabled
+ } mubi4_t;
+
+ // Test whether the value is supplied is one of the valid enumerations
+ function automatic logic mubi4_test_invalid(mubi4_t val);
+ return ~(val inside {MuBi4True, MuBi4False});
+ endfunction : mubi4_test_invalid
+
+ // Convert a 1 input value to a mubi output
+ function automatic mubi4_t mubi4_bool_to_mubi(logic val);
+ return (val ? MuBi4True : MuBi4False);
+ endfunction : mubi4_bool_to_mubi
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal True.
+ function automatic logic mubi4_test_true_strict(mubi4_t val);
+ return MuBi4True == val;
+ endfunction : mubi4_test_true_strict
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal False.
+ function automatic logic mubi4_test_false_strict(mubi4_t val);
+ return MuBi4False == val;
+ endfunction : mubi4_test_false_strict
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The loose version of this function interprets all
+ // values other than False as "enabled".
+ function automatic logic mubi4_test_true_loose(mubi4_t val);
+ return MuBi4False != val;
+ endfunction : mubi4_test_true_loose
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The loose version of this function interprets all
+ // values other than True as "disabled".
+ function automatic logic mubi4_test_false_loose(mubi4_t val);
+ return MuBi4True != val;
+ endfunction : mubi4_test_false_loose
+
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | act
+ // !act | act | act
+ // act | act | act
+ //
+ function automatic mubi4_t mubi4_or(mubi4_t a, mubi4_t b, mubi4_t act);
+ logic [MuBi4Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi4Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] || b_in[k];
+ end else begin
+ out[k] = a_in[k] && b_in[k];
+ end
+ end
+ return mubi4_t'(out);
+ endfunction : mubi4_or
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | !act
+ // !act | act | !act
+ // act | act | act
+ //
+ function automatic mubi4_t mubi4_and(mubi4_t a, mubi4_t b, mubi4_t act);
+ logic [MuBi4Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi4Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] && b_in[k];
+ end else begin
+ out[k] = a_in[k] || b_in[k];
+ end
+ end
+ return mubi4_t'(out);
+ endfunction : mubi4_and
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi4_t mubi4_or_hi(mubi4_t a, mubi4_t b);
+ return mubi4_or(a, b, MuBi4True);
+ endfunction : mubi4_or_hi
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi4_t mubi4_and_hi(mubi4_t a, mubi4_t b);
+ return mubi4_and(a, b, MuBi4True);
+ endfunction : mubi4_and_hi
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi4_t mubi4_or_lo(mubi4_t a, mubi4_t b);
+ return mubi4_or(a, b, MuBi4False);
+ endfunction : mubi4_or_lo
+
+ // Performs a logical AND operation between two multibit values.
+ // Tlos treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi4_t mubi4_and_lo(mubi4_t a, mubi4_t b);
+ return mubi4_and(a, b, MuBi4False);
+ endfunction : mubi4_and_lo
+
+ //////////////////////////////////////////////
+ // 8 Bit Multibit Type and Functions //
+ //////////////////////////////////////////////
+
+ parameter int MuBi8Width = 8;
+ typedef enum logic [MuBi8Width-1:0] {
+ MuBi8True = 8'h5A, // enabled
+ MuBi8False = 8'hA5 // disabled
+ } mubi8_t;
+
+ // Test whether the value is supplied is one of the valid enumerations
+ function automatic logic mubi8_test_invalid(mubi8_t val);
+ return ~(val inside {MuBi8True, MuBi8False});
+ endfunction : mubi8_test_invalid
+
+ // Convert a 1 input value to a mubi output
+ function automatic mubi8_t mubi8_bool_to_mubi(logic val);
+ return (val ? MuBi8True : MuBi8False);
+ endfunction : mubi8_bool_to_mubi
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal True.
+ function automatic logic mubi8_test_true_strict(mubi8_t val);
+ return MuBi8True == val;
+ endfunction : mubi8_test_true_strict
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal False.
+ function automatic logic mubi8_test_false_strict(mubi8_t val);
+ return MuBi8False == val;
+ endfunction : mubi8_test_false_strict
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The loose version of this function interprets all
+ // values other than False as "enabled".
+ function automatic logic mubi8_test_true_loose(mubi8_t val);
+ return MuBi8False != val;
+ endfunction : mubi8_test_true_loose
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The loose version of this function interprets all
+ // values other than True as "disabled".
+ function automatic logic mubi8_test_false_loose(mubi8_t val);
+ return MuBi8True != val;
+ endfunction : mubi8_test_false_loose
+
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | act
+ // !act | act | act
+ // act | act | act
+ //
+ function automatic mubi8_t mubi8_or(mubi8_t a, mubi8_t b, mubi8_t act);
+ logic [MuBi8Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi8Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] || b_in[k];
+ end else begin
+ out[k] = a_in[k] && b_in[k];
+ end
+ end
+ return mubi8_t'(out);
+ endfunction : mubi8_or
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | !act
+ // !act | act | !act
+ // act | act | act
+ //
+ function automatic mubi8_t mubi8_and(mubi8_t a, mubi8_t b, mubi8_t act);
+ logic [MuBi8Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi8Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] && b_in[k];
+ end else begin
+ out[k] = a_in[k] || b_in[k];
+ end
+ end
+ return mubi8_t'(out);
+ endfunction : mubi8_and
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi8_t mubi8_or_hi(mubi8_t a, mubi8_t b);
+ return mubi8_or(a, b, MuBi8True);
+ endfunction : mubi8_or_hi
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi8_t mubi8_and_hi(mubi8_t a, mubi8_t b);
+ return mubi8_and(a, b, MuBi8True);
+ endfunction : mubi8_and_hi
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi8_t mubi8_or_lo(mubi8_t a, mubi8_t b);
+ return mubi8_or(a, b, MuBi8False);
+ endfunction : mubi8_or_lo
+
+ // Performs a logical AND operation between two multibit values.
+ // Tlos treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi8_t mubi8_and_lo(mubi8_t a, mubi8_t b);
+ return mubi8_and(a, b, MuBi8False);
+ endfunction : mubi8_and_lo
+
+ //////////////////////////////////////////////
+ // 12 Bit Multibit Type and Functions //
+ //////////////////////////////////////////////
+
+ parameter int MuBi12Width = 12;
+ typedef enum logic [MuBi12Width-1:0] {
+ MuBi12True = 12'hA5A, // enabled
+ MuBi12False = 12'h5A5 // disabled
+ } mubi12_t;
+
+ // Test whether the value is supplied is one of the valid enumerations
+ function automatic logic mubi12_test_invalid(mubi12_t val);
+ return ~(val inside {MuBi12True, MuBi12False});
+ endfunction : mubi12_test_invalid
+
+ // Convert a 1 input value to a mubi output
+ function automatic mubi12_t mubi12_bool_to_mubi(logic val);
+ return (val ? MuBi12True : MuBi12False);
+ endfunction : mubi12_bool_to_mubi
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal True.
+ function automatic logic mubi12_test_true_strict(mubi12_t val);
+ return MuBi12True == val;
+ endfunction : mubi12_test_true_strict
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal False.
+ function automatic logic mubi12_test_false_strict(mubi12_t val);
+ return MuBi12False == val;
+ endfunction : mubi12_test_false_strict
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The loose version of this function interprets all
+ // values other than False as "enabled".
+ function automatic logic mubi12_test_true_loose(mubi12_t val);
+ return MuBi12False != val;
+ endfunction : mubi12_test_true_loose
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The loose version of this function interprets all
+ // values other than True as "disabled".
+ function automatic logic mubi12_test_false_loose(mubi12_t val);
+ return MuBi12True != val;
+ endfunction : mubi12_test_false_loose
+
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | act
+ // !act | act | act
+ // act | act | act
+ //
+ function automatic mubi12_t mubi12_or(mubi12_t a, mubi12_t b, mubi12_t act);
+ logic [MuBi12Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi12Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] || b_in[k];
+ end else begin
+ out[k] = a_in[k] && b_in[k];
+ end
+ end
+ return mubi12_t'(out);
+ endfunction : mubi12_or
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | !act
+ // !act | act | !act
+ // act | act | act
+ //
+ function automatic mubi12_t mubi12_and(mubi12_t a, mubi12_t b, mubi12_t act);
+ logic [MuBi12Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi12Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] && b_in[k];
+ end else begin
+ out[k] = a_in[k] || b_in[k];
+ end
+ end
+ return mubi12_t'(out);
+ endfunction : mubi12_and
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi12_t mubi12_or_hi(mubi12_t a, mubi12_t b);
+ return mubi12_or(a, b, MuBi12True);
+ endfunction : mubi12_or_hi
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi12_t mubi12_and_hi(mubi12_t a, mubi12_t b);
+ return mubi12_and(a, b, MuBi12True);
+ endfunction : mubi12_and_hi
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi12_t mubi12_or_lo(mubi12_t a, mubi12_t b);
+ return mubi12_or(a, b, MuBi12False);
+ endfunction : mubi12_or_lo
+
+ // Performs a logical AND operation between two multibit values.
+ // Tlos treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi12_t mubi12_and_lo(mubi12_t a, mubi12_t b);
+ return mubi12_and(a, b, MuBi12False);
+ endfunction : mubi12_and_lo
+
+ //////////////////////////////////////////////
+ // 16 Bit Multibit Type and Functions //
+ //////////////////////////////////////////////
+
+ parameter int MuBi16Width = 16;
+ typedef enum logic [MuBi16Width-1:0] {
+ MuBi16True = 16'h5A5A, // enabled
+ MuBi16False = 16'hA5A5 // disabled
+ } mubi16_t;
+
+ // Test whether the value is supplied is one of the valid enumerations
+ function automatic logic mubi16_test_invalid(mubi16_t val);
+ return ~(val inside {MuBi16True, MuBi16False});
+ endfunction : mubi16_test_invalid
+
+ // Convert a 1 input value to a mubi output
+ function automatic mubi16_t mubi16_bool_to_mubi(logic val);
+ return (val ? MuBi16True : MuBi16False);
+ endfunction : mubi16_bool_to_mubi
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal True.
+ function automatic logic mubi16_test_true_strict(mubi16_t val);
+ return MuBi16True == val;
+ endfunction : mubi16_test_true_strict
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal False.
+ function automatic logic mubi16_test_false_strict(mubi16_t val);
+ return MuBi16False == val;
+ endfunction : mubi16_test_false_strict
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The loose version of this function interprets all
+ // values other than False as "enabled".
+ function automatic logic mubi16_test_true_loose(mubi16_t val);
+ return MuBi16False != val;
+ endfunction : mubi16_test_true_loose
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The loose version of this function interprets all
+ // values other than True as "disabled".
+ function automatic logic mubi16_test_false_loose(mubi16_t val);
+ return MuBi16True != val;
+ endfunction : mubi16_test_false_loose
+
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | act
+ // !act | act | act
+ // act | act | act
+ //
+ function automatic mubi16_t mubi16_or(mubi16_t a, mubi16_t b, mubi16_t act);
+ logic [MuBi16Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi16Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] || b_in[k];
+ end else begin
+ out[k] = a_in[k] && b_in[k];
+ end
+ end
+ return mubi16_t'(out);
+ endfunction : mubi16_or
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | !act
+ // !act | act | !act
+ // act | act | act
+ //
+ function automatic mubi16_t mubi16_and(mubi16_t a, mubi16_t b, mubi16_t act);
+ logic [MuBi16Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi16Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] && b_in[k];
+ end else begin
+ out[k] = a_in[k] || b_in[k];
+ end
+ end
+ return mubi16_t'(out);
+ endfunction : mubi16_and
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi16_t mubi16_or_hi(mubi16_t a, mubi16_t b);
+ return mubi16_or(a, b, MuBi16True);
+ endfunction : mubi16_or_hi
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi16_t mubi16_and_hi(mubi16_t a, mubi16_t b);
+ return mubi16_and(a, b, MuBi16True);
+ endfunction : mubi16_and_hi
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi16_t mubi16_or_lo(mubi16_t a, mubi16_t b);
+ return mubi16_or(a, b, MuBi16False);
+ endfunction : mubi16_or_lo
+
+ // Performs a logical AND operation between two multibit values.
+ // Tlos treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi16_t mubi16_and_lo(mubi16_t a, mubi16_t b);
+ return mubi16_and(a, b, MuBi16False);
+ endfunction : mubi16_and_lo
+
+endpackage : prim_mubi_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_packer.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_packer.sv
new file mode 100644
index 00000000..5c940227
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_packer.sv
@@ -0,0 +1,228 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Combine InW data and write to OutW data if packed to full word or stop signal
+
+
+module prim_packer #(
+ parameter int InW = 32,
+ parameter int OutW = 32,
+ parameter int HintByteData = 0 // If 1, The input/output are byte granularity
+) (
+ input clk_i ,
+ input rst_ni,
+
+ input valid_i,
+ input [InW-1:0] data_i,
+ input [InW-1:0] mask_i,
+ output ready_o,
+
+ output logic valid_o,
+ output logic [OutW-1:0] data_o,
+ output logic [OutW-1:0] mask_o,
+ input ready_i,
+
+ input flush_i, // If 1, send out remnant and clear state
+ output logic flush_done_o
+);
+
+ localparam int Width = InW + OutW; // storage width
+ localparam int ConcatW = Width + InW; // Input concatenated width
+ localparam int PtrW = $clog2(ConcatW+1);
+ localparam int IdxW = $clog2(InW) + ~|$clog2(InW);
+
+ logic valid_next, ready_next;
+ logic [Width-1:0] stored_data, stored_mask;
+ logic [ConcatW-1:0] concat_data, concat_mask;
+ logic [ConcatW-1:0] shiftl_data, shiftl_mask;
+
+ logic [PtrW-1:0] pos, pos_next; // Current write position
+ logic [IdxW-1:0] lod_idx; // result of Leading One Detector
+ logic [$clog2(InW+1)-1:0] inmask_ones; // Counting Ones for mask_i
+
+ logic ack_in, ack_out;
+
+ logic flush_valid; // flush data out request
+ logic flush_done;
+
+ // Computing next position ==================================================
+ always_comb begin
+ // counting mask_i ones
+ inmask_ones = '0;
+ for (int i = 0 ; i < InW ; i++) begin
+ inmask_ones = inmask_ones + mask_i[i];
+ end
+ end
+
+ logic [PtrW-1:0] pos_with_input;
+
+ always_comb begin
+ pos_next = pos;
+ pos_with_input = pos + PtrW'(inmask_ones);
+
+ unique case ({ack_in, ack_out})
+ 2'b00: pos_next = pos;
+ 2'b01: pos_next = (pos <= OutW) ? '0 : pos - OutW;
+ 2'b10: pos_next = pos_with_input;
+ 2'b11: pos_next = (pos_with_input <= OutW) ? '0 : pos_with_input - OutW;
+ default: pos_next = pos;
+ endcase
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ pos <= '0;
+ end else if (flush_done) begin
+ pos <= '0;
+ end else begin
+ pos <= pos_next;
+ end
+ end
+ //---------------------------------------------------------------------------
+
+ // Leading one detector for mask_i
+ always_comb begin
+ lod_idx = 0;
+ for (int i = InW-1; i >= 0 ; i--) begin
+ if (mask_i[i] == 1'b1) begin
+ lod_idx = $unsigned(i);
+ end
+ end
+ end
+
+ assign ack_in = valid_i & ready_o;
+ assign ack_out = valid_o & ready_i;
+
+ // Data process =============================================================
+ // shiftl : Input data shifted into the current stored position
+ assign shiftl_data = (valid_i) ? Width'(data_i >> lod_idx) << pos : '0;
+ assign shiftl_mask = (valid_i) ? Width'(mask_i >> lod_idx) << pos : '0;
+
+ // concat : Merging stored and shiftl
+ assign concat_data = {{(InW){1'b0}}, stored_data & stored_mask} |
+ (shiftl_data & shiftl_mask);
+ assign concat_mask = {{(InW){1'b0}}, stored_mask} | shiftl_mask;
+
+ logic [Width-1:0] stored_data_next, stored_mask_next;
+
+ always_comb begin
+ unique case ({ack_in, ack_out})
+ 2'b00: begin
+ stored_data_next = stored_data;
+ stored_mask_next = stored_mask;
+ end
+ 2'b01: begin
+ // ack_out : shift the amount of OutW
+ stored_data_next = {{OutW{1'b0}}, stored_data[Width-1:OutW]};
+ stored_mask_next = {{OutW{1'b0}}, stored_mask[Width-1:OutW]};
+ end
+ 2'b10: begin
+ // ack_in : Store concat data
+ stored_data_next = concat_data[0+:Width];
+ stored_mask_next = concat_mask[0+:Width];
+ end
+ 2'b11: begin
+ // both : shift the concat_data
+ stored_data_next = concat_data[ConcatW-1:OutW];
+ stored_mask_next = concat_mask[ConcatW-1:OutW];
+ end
+ default: begin
+ stored_data_next = stored_data;
+ stored_mask_next = stored_mask;
+ end
+ endcase
+ end
+
+ // Store the data temporary if it doesn't exceed OutW
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ stored_data <= '0;
+ stored_mask <= '0;
+ end else if (flush_done) begin
+ stored_data <= '0;
+ stored_mask <= '0;
+ end else begin
+ stored_data <= stored_data_next;
+ stored_mask <= stored_mask_next;
+ end
+ end
+ //---------------------------------------------------------------------------
+
+ // flush handling
+ typedef enum logic {
+ FlushIdle,
+ FlushSend
+ } flush_st_e;
+ flush_st_e flush_st, flush_st_next;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ flush_st <= FlushIdle;
+ end else begin
+ flush_st <= flush_st_next;
+ end
+ end
+
+ always_comb begin
+ flush_st_next = FlushIdle;
+
+ flush_valid = 1'b0;
+ flush_done = 1'b0;
+
+ unique case (flush_st)
+ FlushIdle: begin
+ if (flush_i) begin
+ flush_st_next = FlushSend;
+ end else begin
+ flush_st_next = FlushIdle;
+ end
+ end
+
+ FlushSend: begin
+ if (pos == '0) begin
+ flush_st_next = FlushIdle;
+
+ flush_valid = 1'b0;
+ flush_done = 1'b1;
+ end else begin
+ flush_st_next = FlushSend;
+
+ flush_valid = 1'b1;
+ flush_done = 1'b0;
+ end
+ end
+ default: begin
+ flush_st_next = FlushIdle;
+
+ flush_valid = 1'b0;
+ flush_done = 1'b0;
+ end
+ endcase
+ end
+
+ assign flush_done_o = flush_done;
+
+
+ // Output signals ===========================================================
+ assign valid_next = (pos >= OutW) ? 1'b1 : flush_valid;
+
+ // storage space is InW + OutW. So technically, ready_o can be asserted even
+ // if `pos` is greater than OutW. But in order to do that, the logic should
+ // use `inmask_ones` value whether pos+inmask_ones is less than (InW+OutW)
+ // with `valid_i`. It creates a path from `valid_i` --> `ready_o`.
+ // It may create a timing loop in some modules that use `ready_o` to
+ // `valid_i` (which is not a good practice though)
+ assign ready_next = pos <= OutW;
+
+ // Output request
+ assign valid_o = valid_next;
+ assign data_o = stored_data[OutW-1:0];
+ assign mask_o = stored_mask[OutW-1:0];
+
+ // ready_o
+ assign ready_o = ready_next;
+ //---------------------------------------------------------------------------
+
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_pkg.sv
new file mode 100644
index 00000000..ebe38d11
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_pkg.sv
@@ -0,0 +1,18 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Constants for use in primitives
+//
+// This file is a stop-gap until the DV file list is generated by FuseSoC.
+// Its contents are taken from the file which would be generated by FuseSoC.
+// https://github.com/lowRISC/ibex/issues/893
+
+package prim_pkg;
+
+ // Implementation target specialization
+ typedef enum integer {
+ ImplGeneric,
+ ImplXilinx
+ } impl_e;
+endpackage : prim_pkg
\ No newline at end of file
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_ram_1p_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_ram_1p_pkg.sv
new file mode 100644
index 00000000..d4796292
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_ram_1p_pkg.sv
@@ -0,0 +1,20 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package prim_ram_1p_pkg;
+
+ typedef struct packed {
+ logic cfg_en;
+ logic [3:0] cfg;
+ } cfg_t;
+
+ typedef struct packed {
+ cfg_t ram_cfg; // configuration for ram
+ cfg_t rf_cfg; // configuration for regfile
+ } ram_1p_cfg_t;
+
+ parameter ram_1p_cfg_t RAM_1P_CFG_DEFAULT = '0;
+
+endpackage // prim_ram_1p_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_dec.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_dec.sv
new file mode 100644
index 00000000..a40a86cd
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_dec.sv
@@ -0,0 +1,62 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED decoder generated by util/design/secded_gen.py
+
+module prim_secded_inv_39_32_dec (
+ input [38:0] data_i,
+ output logic [31:0] data_o,
+ output logic [6:0] syndrome_o,
+ output logic [1:0] err_o
+);
+
+ always_comb begin : p_encode
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 39'h2A00000000) & 39'h012606BD25);
+ syndrome_o[1] = ^((data_i ^ 39'h2A00000000) & 39'h02DEBA8050);
+ syndrome_o[2] = ^((data_i ^ 39'h2A00000000) & 39'h04413D89AA);
+ syndrome_o[3] = ^((data_i ^ 39'h2A00000000) & 39'h0831234ED1);
+ syndrome_o[4] = ^((data_i ^ 39'h2A00000000) & 39'h10C2C1323B);
+ syndrome_o[5] = ^((data_i ^ 39'h2A00000000) & 39'h202DCC624C);
+ syndrome_o[6] = ^((data_i ^ 39'h2A00000000) & 39'h4098505586);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h19) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h54) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h61) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h34) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h1a) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h2a) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h38) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h49) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'hd) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h51) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h31) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h68) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h7) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'hb) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h25) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h26) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h46) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h70) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h32) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h2c) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h13) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h23) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h29) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h16) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h52) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+ end
+endmodule : prim_secded_inv_39_32_dec
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_enc.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_enc.sv
new file mode 100644
index 00000000..e59d4879
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_39_32_enc.sv
@@ -0,0 +1,23 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED encoder generated by util/design/secded_gen.py
+
+module prim_secded_inv_39_32_enc (
+ input [31:0] data_i,
+ output logic [38:0] data_o
+);
+
+ always_comb begin : p_encode
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h002606BD25);
+ data_o[33] = 1'b1 ^ ^(data_o & 39'h00DEBA8050);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00413D89AA);
+ data_o[35] = 1'b1 ^ ^(data_o & 39'h0031234ED1);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h00C2C1323B);
+ data_o[37] = 1'b1 ^ ^(data_o & 39'h002DCC624C);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h0098505586);
+ end
+
+endmodule : prim_secded_inv_39_32_enc
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_dec.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_dec.sv
new file mode 100644
index 00000000..6e34b502
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_dec.sv
@@ -0,0 +1,87 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED decoder generated by util/design/secded_gen.py
+
+module prim_secded_inv_64_57_dec (
+ input [63:0] data_i,
+ output logic [56:0] data_o,
+ output logic [6:0] syndrome_o,
+ output logic [1:0] err_o
+);
+
+ always_comb begin : p_encode
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 64'h5400000000000000) & 64'h0303FFF800007FFF);
+ syndrome_o[1] = ^((data_i ^ 64'h5400000000000000) & 64'h057C1FF801FF801F);
+ syndrome_o[2] = ^((data_i ^ 64'h5400000000000000) & 64'h09BDE1F87E0781E1);
+ syndrome_o[3] = ^((data_i ^ 64'h5400000000000000) & 64'h11DEEE3B8E388E22);
+ syndrome_o[4] = ^((data_i ^ 64'h5400000000000000) & 64'h21EF76CDB2C93244);
+ syndrome_o[5] = ^((data_i ^ 64'h5400000000000000) & 64'h41F7BB56D5525488);
+ syndrome_o[6] = ^((data_i ^ 64'h5400000000000000) & 64'h81FBDDA769A46910);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'hd) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h15) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h25) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h19) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h29) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h49) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h31) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h51) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h61) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'he) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h16) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h26) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h46) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h1a) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h2a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h4a) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h32) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h52) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h62) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h1c) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h2c) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h4c) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h34) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h54) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h64) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h38) ^ data_i[31];
+ data_o[32] = (syndrome_o == 7'h58) ^ data_i[32];
+ data_o[33] = (syndrome_o == 7'h68) ^ data_i[33];
+ data_o[34] = (syndrome_o == 7'h70) ^ data_i[34];
+ data_o[35] = (syndrome_o == 7'h1f) ^ data_i[35];
+ data_o[36] = (syndrome_o == 7'h2f) ^ data_i[36];
+ data_o[37] = (syndrome_o == 7'h4f) ^ data_i[37];
+ data_o[38] = (syndrome_o == 7'h37) ^ data_i[38];
+ data_o[39] = (syndrome_o == 7'h57) ^ data_i[39];
+ data_o[40] = (syndrome_o == 7'h67) ^ data_i[40];
+ data_o[41] = (syndrome_o == 7'h3b) ^ data_i[41];
+ data_o[42] = (syndrome_o == 7'h5b) ^ data_i[42];
+ data_o[43] = (syndrome_o == 7'h6b) ^ data_i[43];
+ data_o[44] = (syndrome_o == 7'h73) ^ data_i[44];
+ data_o[45] = (syndrome_o == 7'h3d) ^ data_i[45];
+ data_o[46] = (syndrome_o == 7'h5d) ^ data_i[46];
+ data_o[47] = (syndrome_o == 7'h6d) ^ data_i[47];
+ data_o[48] = (syndrome_o == 7'h75) ^ data_i[48];
+ data_o[49] = (syndrome_o == 7'h79) ^ data_i[49];
+ data_o[50] = (syndrome_o == 7'h3e) ^ data_i[50];
+ data_o[51] = (syndrome_o == 7'h5e) ^ data_i[51];
+ data_o[52] = (syndrome_o == 7'h6e) ^ data_i[52];
+ data_o[53] = (syndrome_o == 7'h76) ^ data_i[53];
+ data_o[54] = (syndrome_o == 7'h7a) ^ data_i[54];
+ data_o[55] = (syndrome_o == 7'h7c) ^ data_i[55];
+ data_o[56] = (syndrome_o == 7'h7f) ^ data_i[56];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+ end
+endmodule : prim_secded_inv_64_57_dec
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_enc.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_enc.sv
new file mode 100644
index 00000000..21caaa6b
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_inv_64_57_enc.sv
@@ -0,0 +1,23 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED encoder generated by util/design/secded_gen.py
+
+module prim_secded_inv_64_57_enc (
+ input [56:0] data_i,
+ output logic [63:0] data_o
+);
+
+ always_comb begin : p_encode
+ data_o = 64'(data_i);
+ data_o[57] = 1'b0 ^ ^(data_o & 64'h0103FFF800007FFF);
+ data_o[58] = 1'b1 ^ ^(data_o & 64'h017C1FF801FF801F);
+ data_o[59] = 1'b0 ^ ^(data_o & 64'h01BDE1F87E0781E1);
+ data_o[60] = 1'b1 ^ ^(data_o & 64'h01DEEE3B8E388E22);
+ data_o[61] = 1'b0 ^ ^(data_o & 64'h01EF76CDB2C93244);
+ data_o[62] = 1'b1 ^ ^(data_o & 64'h01F7BB56D5525488);
+ data_o[63] = 1'b0 ^ ^(data_o & 64'h01FBDDA769A46910);
+ end
+
+endmodule : prim_secded_inv_64_57_enc
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_pkg.sv
new file mode 100644
index 00000000..5f227e6e
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_secded_pkg.sv
@@ -0,0 +1,1778 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED package generated by
+// util/design/secded_gen.py from util/design/data/secded_cfg.hjson
+
+package prim_secded_pkg;
+
+ typedef enum int {
+ SecdedNone,
+ Secded_22_16,
+ Secded_28_22,
+ Secded_39_32,
+ Secded_64_57,
+ Secded_72_64,
+ SecdedHamming_22_16,
+ SecdedHamming_39_32,
+ SecdedHamming_72_64,
+ SecdedHamming_76_68,
+ SecdedInv_22_16,
+ SecdedInv_28_22,
+ SecdedInv_39_32,
+ SecdedInv_64_57,
+ SecdedInv_72_64,
+ SecdedInvHamming_22_16,
+ SecdedInvHamming_39_32,
+ SecdedInvHamming_72_64,
+ SecdedInvHamming_76_68
+ } prim_secded_e;
+
+ function automatic int get_ecc_data_width(prim_secded_e ecc_type);
+ case (ecc_type)
+ Secded_22_16: return 16;
+ Secded_28_22: return 22;
+ Secded_39_32: return 32;
+ Secded_64_57: return 57;
+ Secded_72_64: return 64;
+ SecdedHamming_22_16: return 16;
+ SecdedHamming_39_32: return 32;
+ SecdedHamming_72_64: return 64;
+ SecdedHamming_76_68: return 68;
+ SecdedInv_22_16: return 16;
+ SecdedInv_28_22: return 22;
+ SecdedInv_39_32: return 32;
+ SecdedInv_64_57: return 57;
+ SecdedInv_72_64: return 64;
+ SecdedInvHamming_22_16: return 16;
+ SecdedInvHamming_39_32: return 32;
+ SecdedInvHamming_72_64: return 64;
+ SecdedInvHamming_76_68: return 68;
+ // Return a non-zero width to avoid VCS compile issues
+ default: return 32;
+ endcase
+ endfunction
+
+ function automatic int get_ecc_parity_width(prim_secded_e ecc_type);
+ case (ecc_type)
+ Secded_22_16: return 6;
+ Secded_28_22: return 6;
+ Secded_39_32: return 7;
+ Secded_64_57: return 7;
+ Secded_72_64: return 8;
+ SecdedHamming_22_16: return 6;
+ SecdedHamming_39_32: return 7;
+ SecdedHamming_72_64: return 8;
+ SecdedHamming_76_68: return 8;
+ SecdedInv_22_16: return 6;
+ SecdedInv_28_22: return 6;
+ SecdedInv_39_32: return 7;
+ SecdedInv_64_57: return 7;
+ SecdedInv_72_64: return 8;
+ SecdedInvHamming_22_16: return 6;
+ SecdedInvHamming_39_32: return 7;
+ SecdedInvHamming_72_64: return 8;
+ SecdedInvHamming_76_68: return 8;
+ default: return 0;
+ endcase
+ endfunction
+
+ parameter logic [5:0] Secded2216ZeroEcc = 6'h0;
+ parameter logic [21:0] Secded2216ZeroWord = 22'h0;
+
+ typedef struct packed {
+ logic [15:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_22_16_t;
+
+ parameter logic [5:0] Secded2822ZeroEcc = 6'h0;
+ parameter logic [27:0] Secded2822ZeroWord = 28'h0;
+
+ typedef struct packed {
+ logic [21:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_28_22_t;
+
+ parameter logic [6:0] Secded3932ZeroEcc = 7'h0;
+ parameter logic [38:0] Secded3932ZeroWord = 39'h0;
+
+ typedef struct packed {
+ logic [31:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_39_32_t;
+
+ parameter logic [6:0] Secded6457ZeroEcc = 7'h0;
+ parameter logic [63:0] Secded6457ZeroWord = 64'h0;
+
+ typedef struct packed {
+ logic [56:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_64_57_t;
+
+ parameter logic [7:0] Secded7264ZeroEcc = 8'h0;
+ parameter logic [71:0] Secded7264ZeroWord = 72'h0;
+
+ typedef struct packed {
+ logic [63:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_72_64_t;
+
+ parameter logic [5:0] SecdedHamming2216ZeroEcc = 6'h0;
+ parameter logic [21:0] SecdedHamming2216ZeroWord = 22'h0;
+
+ typedef struct packed {
+ logic [15:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_hamming_22_16_t;
+
+ parameter logic [6:0] SecdedHamming3932ZeroEcc = 7'h0;
+ parameter logic [38:0] SecdedHamming3932ZeroWord = 39'h0;
+
+ typedef struct packed {
+ logic [31:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_hamming_39_32_t;
+
+ parameter logic [7:0] SecdedHamming7264ZeroEcc = 8'h0;
+ parameter logic [71:0] SecdedHamming7264ZeroWord = 72'h0;
+
+ typedef struct packed {
+ logic [63:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_hamming_72_64_t;
+
+ parameter logic [7:0] SecdedHamming7668ZeroEcc = 8'h0;
+ parameter logic [75:0] SecdedHamming7668ZeroWord = 76'h0;
+
+ typedef struct packed {
+ logic [67:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_hamming_76_68_t;
+
+ parameter logic [5:0] SecdedInv2216ZeroEcc = 6'h2A;
+ parameter logic [21:0] SecdedInv2216ZeroWord = 22'h2A0000;
+
+ typedef struct packed {
+ logic [15:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_22_16_t;
+
+ parameter logic [5:0] SecdedInv2822ZeroEcc = 6'h2A;
+ parameter logic [27:0] SecdedInv2822ZeroWord = 28'hA800000;
+
+ typedef struct packed {
+ logic [21:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_28_22_t;
+
+ parameter logic [6:0] SecdedInv3932ZeroEcc = 7'h2A;
+ parameter logic [38:0] SecdedInv3932ZeroWord = 39'h2A00000000;
+
+ typedef struct packed {
+ logic [31:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_39_32_t;
+
+ parameter logic [6:0] SecdedInv6457ZeroEcc = 7'h2A;
+ parameter logic [63:0] SecdedInv6457ZeroWord = 64'h5400000000000000;
+
+ typedef struct packed {
+ logic [56:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_64_57_t;
+
+ parameter logic [7:0] SecdedInv7264ZeroEcc = 8'hAA;
+ parameter logic [71:0] SecdedInv7264ZeroWord = 72'hAA0000000000000000;
+
+ typedef struct packed {
+ logic [63:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_72_64_t;
+
+ parameter logic [5:0] SecdedInvHamming2216ZeroEcc = 6'h2A;
+ parameter logic [21:0] SecdedInvHamming2216ZeroWord = 22'h2A0000;
+
+ typedef struct packed {
+ logic [15:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_hamming_22_16_t;
+
+ parameter logic [6:0] SecdedInvHamming3932ZeroEcc = 7'h2A;
+ parameter logic [38:0] SecdedInvHamming3932ZeroWord = 39'h2A00000000;
+
+ typedef struct packed {
+ logic [31:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_hamming_39_32_t;
+
+ parameter logic [7:0] SecdedInvHamming7264ZeroEcc = 8'hAA;
+ parameter logic [71:0] SecdedInvHamming7264ZeroWord = 72'hAA0000000000000000;
+
+ typedef struct packed {
+ logic [63:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_hamming_72_64_t;
+
+ parameter logic [7:0] SecdedInvHamming7668ZeroEcc = 8'hAA;
+ parameter logic [75:0] SecdedInvHamming7668ZeroWord = 76'hAA00000000000000000;
+
+ typedef struct packed {
+ logic [67:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_hamming_76_68_t;
+
+ function automatic logic [21:0]
+ prim_secded_22_16_enc (logic [15:0] data_i);
+ logic [21:0] data_o;
+ data_o = 22'(data_i);
+ data_o[16] = 1'b0 ^ ^(data_o & 22'h00496E);
+ data_o[17] = 1'b0 ^ ^(data_o & 22'h00F20B);
+ data_o[18] = 1'b0 ^ ^(data_o & 22'h008ED8);
+ data_o[19] = 1'b0 ^ ^(data_o & 22'h007714);
+ data_o[20] = 1'b0 ^ ^(data_o & 22'h00ACA5);
+ data_o[21] = 1'b0 ^ ^(data_o & 22'h0011F3);
+ return data_o;
+ endfunction
+
+ function automatic secded_22_16_t
+ prim_secded_22_16_dec (logic [21:0] data_i);
+ logic [15:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_22_16_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 22'h01496E);
+ syndrome_o[1] = ^(data_i & 22'h02F20B);
+ syndrome_o[2] = ^(data_i & 22'h048ED8);
+ syndrome_o[3] = ^(data_i & 22'h087714);
+ syndrome_o[4] = ^(data_i & 22'h10ACA5);
+ syndrome_o[5] = ^(data_i & 22'h2011F3);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h32) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'h23) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h19) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h7) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'h2c) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h31) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h25) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h34) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h29) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'he) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'h1c) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h15) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h2a) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h1a) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'hb) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h16) ^ data_i[15];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [27:0]
+ prim_secded_28_22_enc (logic [21:0] data_i);
+ logic [27:0] data_o;
+ data_o = 28'(data_i);
+ data_o[22] = 1'b0 ^ ^(data_o & 28'h03003FF);
+ data_o[23] = 1'b0 ^ ^(data_o & 28'h010FC0F);
+ data_o[24] = 1'b0 ^ ^(data_o & 28'h0271C71);
+ data_o[25] = 1'b0 ^ ^(data_o & 28'h03B6592);
+ data_o[26] = 1'b0 ^ ^(data_o & 28'h03DAAA4);
+ data_o[27] = 1'b0 ^ ^(data_o & 28'h03ED348);
+ return data_o;
+ endfunction
+
+ function automatic secded_28_22_t
+ prim_secded_28_22_dec (logic [27:0] data_i);
+ logic [21:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_28_22_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 28'h07003FF);
+ syndrome_o[1] = ^(data_i & 28'h090FC0F);
+ syndrome_o[2] = ^(data_i & 28'h1271C71);
+ syndrome_o[3] = ^(data_i & 28'h23B6592);
+ syndrome_o[4] = ^(data_i & 28'h43DAAA4);
+ syndrome_o[5] = ^(data_i & 28'h83ED348);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'hd) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h25) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h19) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h29) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'h31) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'he) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h16) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h26) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h1a) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'h2a) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h32) ^ data_i[15];
+ data_o[16] = (syndrome_o == 6'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 6'h2c) ^ data_i[17];
+ data_o[18] = (syndrome_o == 6'h34) ^ data_i[18];
+ data_o[19] = (syndrome_o == 6'h38) ^ data_i[19];
+ data_o[20] = (syndrome_o == 6'h3b) ^ data_i[20];
+ data_o[21] = (syndrome_o == 6'h3d) ^ data_i[21];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [38:0]
+ prim_secded_39_32_enc (logic [31:0] data_i);
+ logic [38:0] data_o;
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h002606BD25);
+ data_o[33] = 1'b0 ^ ^(data_o & 39'h00DEBA8050);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00413D89AA);
+ data_o[35] = 1'b0 ^ ^(data_o & 39'h0031234ED1);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h00C2C1323B);
+ data_o[37] = 1'b0 ^ ^(data_o & 39'h002DCC624C);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h0098505586);
+ return data_o;
+ endfunction
+
+ function automatic secded_39_32_t
+ prim_secded_39_32_dec (logic [38:0] data_i);
+ logic [31:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_39_32_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 39'h012606BD25);
+ syndrome_o[1] = ^(data_i & 39'h02DEBA8050);
+ syndrome_o[2] = ^(data_i & 39'h04413D89AA);
+ syndrome_o[3] = ^(data_i & 39'h0831234ED1);
+ syndrome_o[4] = ^(data_i & 39'h10C2C1323B);
+ syndrome_o[5] = ^(data_i & 39'h202DCC624C);
+ syndrome_o[6] = ^(data_i & 39'h4098505586);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h19) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h54) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h61) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h34) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h1a) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h2a) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h38) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h49) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'hd) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h51) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h31) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h68) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h7) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'hb) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h25) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h26) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h46) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h70) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h32) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h2c) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h13) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h23) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h29) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h16) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h52) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [63:0]
+ prim_secded_64_57_enc (logic [56:0] data_i);
+ logic [63:0] data_o;
+ data_o = 64'(data_i);
+ data_o[57] = 1'b0 ^ ^(data_o & 64'h0103FFF800007FFF);
+ data_o[58] = 1'b0 ^ ^(data_o & 64'h017C1FF801FF801F);
+ data_o[59] = 1'b0 ^ ^(data_o & 64'h01BDE1F87E0781E1);
+ data_o[60] = 1'b0 ^ ^(data_o & 64'h01DEEE3B8E388E22);
+ data_o[61] = 1'b0 ^ ^(data_o & 64'h01EF76CDB2C93244);
+ data_o[62] = 1'b0 ^ ^(data_o & 64'h01F7BB56D5525488);
+ data_o[63] = 1'b0 ^ ^(data_o & 64'h01FBDDA769A46910);
+ return data_o;
+ endfunction
+
+ function automatic secded_64_57_t
+ prim_secded_64_57_dec (logic [63:0] data_i);
+ logic [56:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_64_57_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 64'h0303FFF800007FFF);
+ syndrome_o[1] = ^(data_i & 64'h057C1FF801FF801F);
+ syndrome_o[2] = ^(data_i & 64'h09BDE1F87E0781E1);
+ syndrome_o[3] = ^(data_i & 64'h11DEEE3B8E388E22);
+ syndrome_o[4] = ^(data_i & 64'h21EF76CDB2C93244);
+ syndrome_o[5] = ^(data_i & 64'h41F7BB56D5525488);
+ syndrome_o[6] = ^(data_i & 64'h81FBDDA769A46910);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'hd) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h15) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h25) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h19) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h29) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h49) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h31) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h51) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h61) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'he) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h16) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h26) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h46) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h1a) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h2a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h4a) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h32) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h52) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h62) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h1c) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h2c) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h4c) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h34) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h54) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h64) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h38) ^ data_i[31];
+ data_o[32] = (syndrome_o == 7'h58) ^ data_i[32];
+ data_o[33] = (syndrome_o == 7'h68) ^ data_i[33];
+ data_o[34] = (syndrome_o == 7'h70) ^ data_i[34];
+ data_o[35] = (syndrome_o == 7'h1f) ^ data_i[35];
+ data_o[36] = (syndrome_o == 7'h2f) ^ data_i[36];
+ data_o[37] = (syndrome_o == 7'h4f) ^ data_i[37];
+ data_o[38] = (syndrome_o == 7'h37) ^ data_i[38];
+ data_o[39] = (syndrome_o == 7'h57) ^ data_i[39];
+ data_o[40] = (syndrome_o == 7'h67) ^ data_i[40];
+ data_o[41] = (syndrome_o == 7'h3b) ^ data_i[41];
+ data_o[42] = (syndrome_o == 7'h5b) ^ data_i[42];
+ data_o[43] = (syndrome_o == 7'h6b) ^ data_i[43];
+ data_o[44] = (syndrome_o == 7'h73) ^ data_i[44];
+ data_o[45] = (syndrome_o == 7'h3d) ^ data_i[45];
+ data_o[46] = (syndrome_o == 7'h5d) ^ data_i[46];
+ data_o[47] = (syndrome_o == 7'h6d) ^ data_i[47];
+ data_o[48] = (syndrome_o == 7'h75) ^ data_i[48];
+ data_o[49] = (syndrome_o == 7'h79) ^ data_i[49];
+ data_o[50] = (syndrome_o == 7'h3e) ^ data_i[50];
+ data_o[51] = (syndrome_o == 7'h5e) ^ data_i[51];
+ data_o[52] = (syndrome_o == 7'h6e) ^ data_i[52];
+ data_o[53] = (syndrome_o == 7'h76) ^ data_i[53];
+ data_o[54] = (syndrome_o == 7'h7a) ^ data_i[54];
+ data_o[55] = (syndrome_o == 7'h7c) ^ data_i[55];
+ data_o[56] = (syndrome_o == 7'h7f) ^ data_i[56];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [71:0]
+ prim_secded_72_64_enc (logic [63:0] data_i);
+ logic [71:0] data_o;
+ data_o = 72'(data_i);
+ data_o[64] = 1'b0 ^ ^(data_o & 72'h00B9000000001FFFFF);
+ data_o[65] = 1'b0 ^ ^(data_o & 72'h005E00000FFFE0003F);
+ data_o[66] = 1'b0 ^ ^(data_o & 72'h0067003FF003E007C1);
+ data_o[67] = 1'b0 ^ ^(data_o & 72'h00CD0FC0F03C207842);
+ data_o[68] = 1'b0 ^ ^(data_o & 72'h00B671C711C4438884);
+ data_o[69] = 1'b0 ^ ^(data_o & 72'h00B5B65926488C9108);
+ data_o[70] = 1'b0 ^ ^(data_o & 72'h00CBDAAA4A91152210);
+ data_o[71] = 1'b0 ^ ^(data_o & 72'h007AED348D221A4420);
+ return data_o;
+ endfunction
+
+ function automatic secded_72_64_t
+ prim_secded_72_64_dec (logic [71:0] data_i);
+ logic [63:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_72_64_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 72'h01B9000000001FFFFF);
+ syndrome_o[1] = ^(data_i & 72'h025E00000FFFE0003F);
+ syndrome_o[2] = ^(data_i & 72'h0467003FF003E007C1);
+ syndrome_o[3] = ^(data_i & 72'h08CD0FC0F03C207842);
+ syndrome_o[4] = ^(data_i & 72'h10B671C711C4438884);
+ syndrome_o[5] = ^(data_i & 72'h20B5B65926488C9108);
+ syndrome_o[6] = ^(data_i & 72'h40CBDAAA4A91152210);
+ syndrome_o[7] = ^(data_i & 72'h807AED348D221A4420);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h83) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'hd) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h15) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h25) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h45) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h85) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h19) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h29) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h49) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h89) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h31) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h51) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h91) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h61) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'ha1) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'hc1) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h16) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h26) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h46) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h86) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'h1a) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'h2a) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'h8a) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'h32) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'h52) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'h92) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'h62) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha2) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'hc2) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'h1c) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'h2c) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'h4c) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'h8c) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'h34) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'h54) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'h94) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'h64) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'ha4) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hc4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'h38) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'h58) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'h98) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'h68) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'ha8) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hc8) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'h70) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hb0) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hd0) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'he0) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'h6d) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hd6) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'h3e) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hcb) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hb3) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hb5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hce) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'h79) ^ data_i[63];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [21:0]
+ prim_secded_hamming_22_16_enc (logic [15:0] data_i);
+ logic [21:0] data_o;
+ data_o = 22'(data_i);
+ data_o[16] = 1'b0 ^ ^(data_o & 22'h00AD5B);
+ data_o[17] = 1'b0 ^ ^(data_o & 22'h00366D);
+ data_o[18] = 1'b0 ^ ^(data_o & 22'h00C78E);
+ data_o[19] = 1'b0 ^ ^(data_o & 22'h0007F0);
+ data_o[20] = 1'b0 ^ ^(data_o & 22'h00F800);
+ data_o[21] = 1'b0 ^ ^(data_o & 22'h1FFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_hamming_22_16_t
+ prim_secded_hamming_22_16_dec (logic [21:0] data_i);
+ logic [15:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_hamming_22_16_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 22'h01AD5B);
+ syndrome_o[1] = ^(data_i & 22'h02366D);
+ syndrome_o[2] = ^(data_i & 22'h04C78E);
+ syndrome_o[3] = ^(data_i & 22'h0807F0);
+ syndrome_o[4] = ^(data_i & 22'h10F800);
+ syndrome_o[5] = ^(data_i & 22'h3FFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h23) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'h25) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h26) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h27) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'h29) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h2a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h2b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h2c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h2d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'h2e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'h2f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h31) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h32) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h33) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'h34) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h35) ^ data_i[15];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[5];
+ err_o[1] = |syndrome_o[4:0] & ~syndrome_o[5];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [38:0]
+ prim_secded_hamming_39_32_enc (logic [31:0] data_i);
+ logic [38:0] data_o;
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h0056AAAD5B);
+ data_o[33] = 1'b0 ^ ^(data_o & 39'h009B33366D);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00E3C3C78E);
+ data_o[35] = 1'b0 ^ ^(data_o & 39'h0003FC07F0);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h0003FFF800);
+ data_o[37] = 1'b0 ^ ^(data_o & 39'h00FC000000);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h3FFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_hamming_39_32_t
+ prim_secded_hamming_39_32_dec (logic [38:0] data_i);
+ logic [31:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_hamming_39_32_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 39'h0156AAAD5B);
+ syndrome_o[1] = ^(data_i & 39'h029B33366D);
+ syndrome_o[2] = ^(data_i & 39'h04E3C3C78E);
+ syndrome_o[3] = ^(data_i & 39'h0803FC07F0);
+ syndrome_o[4] = ^(data_i & 39'h1003FFF800);
+ syndrome_o[5] = ^(data_i & 39'h20FC000000);
+ syndrome_o[6] = ^(data_i & 39'h7FFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h43) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h45) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h46) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h47) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h49) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h4a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h4b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h4d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h4e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h4f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h51) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h52) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h53) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h54) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h55) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h56) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h57) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h58) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h59) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h5a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h5b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h5c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h5d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h5e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h5f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h61) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h63) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h64) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h65) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h66) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[6];
+ err_o[1] = |syndrome_o[5:0] & ~syndrome_o[6];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [71:0]
+ prim_secded_hamming_72_64_enc (logic [63:0] data_i);
+ logic [71:0] data_o;
+ data_o = 72'(data_i);
+ data_o[64] = 1'b0 ^ ^(data_o & 72'h00AB55555556AAAD5B);
+ data_o[65] = 1'b0 ^ ^(data_o & 72'h00CD9999999B33366D);
+ data_o[66] = 1'b0 ^ ^(data_o & 72'h00F1E1E1E1E3C3C78E);
+ data_o[67] = 1'b0 ^ ^(data_o & 72'h0001FE01FE03FC07F0);
+ data_o[68] = 1'b0 ^ ^(data_o & 72'h0001FFFE0003FFF800);
+ data_o[69] = 1'b0 ^ ^(data_o & 72'h0001FFFFFFFC000000);
+ data_o[70] = 1'b0 ^ ^(data_o & 72'h00FE00000000000000);
+ data_o[71] = 1'b0 ^ ^(data_o & 72'h7FFFFFFFFFFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_hamming_72_64_t
+ prim_secded_hamming_72_64_dec (logic [71:0] data_i);
+ logic [63:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_hamming_72_64_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 72'h01AB55555556AAAD5B);
+ syndrome_o[1] = ^(data_i & 72'h02CD9999999B33366D);
+ syndrome_o[2] = ^(data_i & 72'h04F1E1E1E1E3C3C78E);
+ syndrome_o[3] = ^(data_i & 72'h0801FE01FE03FC07F0);
+ syndrome_o[4] = ^(data_i & 72'h1001FFFE0003FFF800);
+ syndrome_o[5] = ^(data_i & 72'h2001FFFFFFFC000000);
+ syndrome_o[6] = ^(data_i & 72'h40FE00000000000000);
+ syndrome_o[7] = ^(data_i & 72'hFFFFFFFFFFFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h83) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'h85) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h86) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h87) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h89) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h8a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'h8b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h8c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h8d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h8e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h8f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h91) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h92) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h93) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h94) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h95) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h96) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h97) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h98) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'h99) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'h9a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'h9b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h9c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h9d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h9e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h9f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'ha1) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'ha2) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'ha3) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'ha4) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'ha5) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'ha6) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'ha7) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'ha8) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha9) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'haa) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'hab) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'hac) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'had) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'hae) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'haf) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'hb0) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'hb1) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'hb2) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'hb3) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hb4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'hb5) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'hb6) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'hb7) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'hb8) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'hb9) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hba) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'hbb) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hbc) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hbd) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'hbe) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'hbf) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hc1) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'hc2) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hc3) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hc4) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hc5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hc6) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'hc7) ^ data_i[63];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[7];
+ err_o[1] = |syndrome_o[6:0] & ~syndrome_o[7];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [75:0]
+ prim_secded_hamming_76_68_enc (logic [67:0] data_i);
+ logic [75:0] data_o;
+ data_o = 76'(data_i);
+ data_o[68] = 1'b0 ^ ^(data_o & 76'h00AAB55555556AAAD5B);
+ data_o[69] = 1'b0 ^ ^(data_o & 76'h00CCD9999999B33366D);
+ data_o[70] = 1'b0 ^ ^(data_o & 76'h000F1E1E1E1E3C3C78E);
+ data_o[71] = 1'b0 ^ ^(data_o & 76'h00F01FE01FE03FC07F0);
+ data_o[72] = 1'b0 ^ ^(data_o & 76'h00001FFFE0003FFF800);
+ data_o[73] = 1'b0 ^ ^(data_o & 76'h00001FFFFFFFC000000);
+ data_o[74] = 1'b0 ^ ^(data_o & 76'h00FFE00000000000000);
+ data_o[75] = 1'b0 ^ ^(data_o & 76'h7FFFFFFFFFFFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_hamming_76_68_t
+ prim_secded_hamming_76_68_dec (logic [75:0] data_i);
+ logic [67:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_hamming_76_68_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 76'h01AAB55555556AAAD5B);
+ syndrome_o[1] = ^(data_i & 76'h02CCD9999999B33366D);
+ syndrome_o[2] = ^(data_i & 76'h040F1E1E1E1E3C3C78E);
+ syndrome_o[3] = ^(data_i & 76'h08F01FE01FE03FC07F0);
+ syndrome_o[4] = ^(data_i & 76'h10001FFFE0003FFF800);
+ syndrome_o[5] = ^(data_i & 76'h20001FFFFFFFC000000);
+ syndrome_o[6] = ^(data_i & 76'h40FFE00000000000000);
+ syndrome_o[7] = ^(data_i & 76'hFFFFFFFFFFFFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h83) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'h85) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h86) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h87) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h89) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h8a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'h8b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h8c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h8d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h8e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h8f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h91) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h92) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h93) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h94) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h95) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h96) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h97) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h98) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'h99) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'h9a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'h9b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h9c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h9d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h9e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h9f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'ha1) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'ha2) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'ha3) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'ha4) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'ha5) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'ha6) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'ha7) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'ha8) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha9) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'haa) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'hab) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'hac) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'had) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'hae) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'haf) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'hb0) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'hb1) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'hb2) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'hb3) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hb4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'hb5) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'hb6) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'hb7) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'hb8) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'hb9) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hba) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'hbb) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hbc) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hbd) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'hbe) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'hbf) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hc1) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'hc2) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hc3) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hc4) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hc5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hc6) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'hc7) ^ data_i[63];
+ data_o[64] = (syndrome_o == 8'hc8) ^ data_i[64];
+ data_o[65] = (syndrome_o == 8'hc9) ^ data_i[65];
+ data_o[66] = (syndrome_o == 8'hca) ^ data_i[66];
+ data_o[67] = (syndrome_o == 8'hcb) ^ data_i[67];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[7];
+ err_o[1] = |syndrome_o[6:0] & ~syndrome_o[7];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [21:0]
+ prim_secded_inv_22_16_enc (logic [15:0] data_i);
+ logic [21:0] data_o;
+ data_o = 22'(data_i);
+ data_o[16] = 1'b0 ^ ^(data_o & 22'h00496E);
+ data_o[17] = 1'b1 ^ ^(data_o & 22'h00F20B);
+ data_o[18] = 1'b0 ^ ^(data_o & 22'h008ED8);
+ data_o[19] = 1'b1 ^ ^(data_o & 22'h007714);
+ data_o[20] = 1'b0 ^ ^(data_o & 22'h00ACA5);
+ data_o[21] = 1'b1 ^ ^(data_o & 22'h0011F3);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_22_16_t
+ prim_secded_inv_22_16_dec (logic [21:0] data_i);
+ logic [15:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_22_16_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 22'h2A0000) & 22'h01496E);
+ syndrome_o[1] = ^((data_i ^ 22'h2A0000) & 22'h02F20B);
+ syndrome_o[2] = ^((data_i ^ 22'h2A0000) & 22'h048ED8);
+ syndrome_o[3] = ^((data_i ^ 22'h2A0000) & 22'h087714);
+ syndrome_o[4] = ^((data_i ^ 22'h2A0000) & 22'h10ACA5);
+ syndrome_o[5] = ^((data_i ^ 22'h2A0000) & 22'h2011F3);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h32) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'h23) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h19) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h7) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'h2c) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h31) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h25) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h34) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h29) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'he) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'h1c) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h15) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h2a) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h1a) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'hb) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h16) ^ data_i[15];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [27:0]
+ prim_secded_inv_28_22_enc (logic [21:0] data_i);
+ logic [27:0] data_o;
+ data_o = 28'(data_i);
+ data_o[22] = 1'b0 ^ ^(data_o & 28'h03003FF);
+ data_o[23] = 1'b1 ^ ^(data_o & 28'h010FC0F);
+ data_o[24] = 1'b0 ^ ^(data_o & 28'h0271C71);
+ data_o[25] = 1'b1 ^ ^(data_o & 28'h03B6592);
+ data_o[26] = 1'b0 ^ ^(data_o & 28'h03DAAA4);
+ data_o[27] = 1'b1 ^ ^(data_o & 28'h03ED348);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_28_22_t
+ prim_secded_inv_28_22_dec (logic [27:0] data_i);
+ logic [21:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_28_22_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 28'hA800000) & 28'h07003FF);
+ syndrome_o[1] = ^((data_i ^ 28'hA800000) & 28'h090FC0F);
+ syndrome_o[2] = ^((data_i ^ 28'hA800000) & 28'h1271C71);
+ syndrome_o[3] = ^((data_i ^ 28'hA800000) & 28'h23B6592);
+ syndrome_o[4] = ^((data_i ^ 28'hA800000) & 28'h43DAAA4);
+ syndrome_o[5] = ^((data_i ^ 28'hA800000) & 28'h83ED348);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'hd) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h25) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h19) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h29) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'h31) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'he) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h16) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h26) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h1a) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'h2a) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h32) ^ data_i[15];
+ data_o[16] = (syndrome_o == 6'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 6'h2c) ^ data_i[17];
+ data_o[18] = (syndrome_o == 6'h34) ^ data_i[18];
+ data_o[19] = (syndrome_o == 6'h38) ^ data_i[19];
+ data_o[20] = (syndrome_o == 6'h3b) ^ data_i[20];
+ data_o[21] = (syndrome_o == 6'h3d) ^ data_i[21];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [38:0]
+ prim_secded_inv_39_32_enc (logic [31:0] data_i);
+ logic [38:0] data_o;
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h002606BD25);
+ data_o[33] = 1'b1 ^ ^(data_o & 39'h00DEBA8050);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00413D89AA);
+ data_o[35] = 1'b1 ^ ^(data_o & 39'h0031234ED1);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h00C2C1323B);
+ data_o[37] = 1'b1 ^ ^(data_o & 39'h002DCC624C);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h0098505586);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_39_32_t
+ prim_secded_inv_39_32_dec (logic [38:0] data_i);
+ logic [31:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_39_32_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 39'h2A00000000) & 39'h012606BD25);
+ syndrome_o[1] = ^((data_i ^ 39'h2A00000000) & 39'h02DEBA8050);
+ syndrome_o[2] = ^((data_i ^ 39'h2A00000000) & 39'h04413D89AA);
+ syndrome_o[3] = ^((data_i ^ 39'h2A00000000) & 39'h0831234ED1);
+ syndrome_o[4] = ^((data_i ^ 39'h2A00000000) & 39'h10C2C1323B);
+ syndrome_o[5] = ^((data_i ^ 39'h2A00000000) & 39'h202DCC624C);
+ syndrome_o[6] = ^((data_i ^ 39'h2A00000000) & 39'h4098505586);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h19) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h54) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h61) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h34) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h1a) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h2a) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h38) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h49) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'hd) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h51) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h31) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h68) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h7) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'hb) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h25) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h26) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h46) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h70) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h32) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h2c) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h13) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h23) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h29) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h16) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h52) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [63:0]
+ prim_secded_inv_64_57_enc (logic [56:0] data_i);
+ logic [63:0] data_o;
+ data_o = 64'(data_i);
+ data_o[57] = 1'b0 ^ ^(data_o & 64'h0103FFF800007FFF);
+ data_o[58] = 1'b1 ^ ^(data_o & 64'h017C1FF801FF801F);
+ data_o[59] = 1'b0 ^ ^(data_o & 64'h01BDE1F87E0781E1);
+ data_o[60] = 1'b1 ^ ^(data_o & 64'h01DEEE3B8E388E22);
+ data_o[61] = 1'b0 ^ ^(data_o & 64'h01EF76CDB2C93244);
+ data_o[62] = 1'b1 ^ ^(data_o & 64'h01F7BB56D5525488);
+ data_o[63] = 1'b0 ^ ^(data_o & 64'h01FBDDA769A46910);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_64_57_t
+ prim_secded_inv_64_57_dec (logic [63:0] data_i);
+ logic [56:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_64_57_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 64'h5400000000000000) & 64'h0303FFF800007FFF);
+ syndrome_o[1] = ^((data_i ^ 64'h5400000000000000) & 64'h057C1FF801FF801F);
+ syndrome_o[2] = ^((data_i ^ 64'h5400000000000000) & 64'h09BDE1F87E0781E1);
+ syndrome_o[3] = ^((data_i ^ 64'h5400000000000000) & 64'h11DEEE3B8E388E22);
+ syndrome_o[4] = ^((data_i ^ 64'h5400000000000000) & 64'h21EF76CDB2C93244);
+ syndrome_o[5] = ^((data_i ^ 64'h5400000000000000) & 64'h41F7BB56D5525488);
+ syndrome_o[6] = ^((data_i ^ 64'h5400000000000000) & 64'h81FBDDA769A46910);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'hd) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h15) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h25) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h19) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h29) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h49) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h31) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h51) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h61) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'he) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h16) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h26) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h46) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h1a) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h2a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h4a) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h32) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h52) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h62) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h1c) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h2c) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h4c) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h34) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h54) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h64) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h38) ^ data_i[31];
+ data_o[32] = (syndrome_o == 7'h58) ^ data_i[32];
+ data_o[33] = (syndrome_o == 7'h68) ^ data_i[33];
+ data_o[34] = (syndrome_o == 7'h70) ^ data_i[34];
+ data_o[35] = (syndrome_o == 7'h1f) ^ data_i[35];
+ data_o[36] = (syndrome_o == 7'h2f) ^ data_i[36];
+ data_o[37] = (syndrome_o == 7'h4f) ^ data_i[37];
+ data_o[38] = (syndrome_o == 7'h37) ^ data_i[38];
+ data_o[39] = (syndrome_o == 7'h57) ^ data_i[39];
+ data_o[40] = (syndrome_o == 7'h67) ^ data_i[40];
+ data_o[41] = (syndrome_o == 7'h3b) ^ data_i[41];
+ data_o[42] = (syndrome_o == 7'h5b) ^ data_i[42];
+ data_o[43] = (syndrome_o == 7'h6b) ^ data_i[43];
+ data_o[44] = (syndrome_o == 7'h73) ^ data_i[44];
+ data_o[45] = (syndrome_o == 7'h3d) ^ data_i[45];
+ data_o[46] = (syndrome_o == 7'h5d) ^ data_i[46];
+ data_o[47] = (syndrome_o == 7'h6d) ^ data_i[47];
+ data_o[48] = (syndrome_o == 7'h75) ^ data_i[48];
+ data_o[49] = (syndrome_o == 7'h79) ^ data_i[49];
+ data_o[50] = (syndrome_o == 7'h3e) ^ data_i[50];
+ data_o[51] = (syndrome_o == 7'h5e) ^ data_i[51];
+ data_o[52] = (syndrome_o == 7'h6e) ^ data_i[52];
+ data_o[53] = (syndrome_o == 7'h76) ^ data_i[53];
+ data_o[54] = (syndrome_o == 7'h7a) ^ data_i[54];
+ data_o[55] = (syndrome_o == 7'h7c) ^ data_i[55];
+ data_o[56] = (syndrome_o == 7'h7f) ^ data_i[56];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [71:0]
+ prim_secded_inv_72_64_enc (logic [63:0] data_i);
+ logic [71:0] data_o;
+ data_o = 72'(data_i);
+ data_o[64] = 1'b0 ^ ^(data_o & 72'h00B9000000001FFFFF);
+ data_o[65] = 1'b1 ^ ^(data_o & 72'h005E00000FFFE0003F);
+ data_o[66] = 1'b0 ^ ^(data_o & 72'h0067003FF003E007C1);
+ data_o[67] = 1'b1 ^ ^(data_o & 72'h00CD0FC0F03C207842);
+ data_o[68] = 1'b0 ^ ^(data_o & 72'h00B671C711C4438884);
+ data_o[69] = 1'b1 ^ ^(data_o & 72'h00B5B65926488C9108);
+ data_o[70] = 1'b0 ^ ^(data_o & 72'h00CBDAAA4A91152210);
+ data_o[71] = 1'b1 ^ ^(data_o & 72'h007AED348D221A4420);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_72_64_t
+ prim_secded_inv_72_64_dec (logic [71:0] data_i);
+ logic [63:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_72_64_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 72'hAA0000000000000000) & 72'h01B9000000001FFFFF);
+ syndrome_o[1] = ^((data_i ^ 72'hAA0000000000000000) & 72'h025E00000FFFE0003F);
+ syndrome_o[2] = ^((data_i ^ 72'hAA0000000000000000) & 72'h0467003FF003E007C1);
+ syndrome_o[3] = ^((data_i ^ 72'hAA0000000000000000) & 72'h08CD0FC0F03C207842);
+ syndrome_o[4] = ^((data_i ^ 72'hAA0000000000000000) & 72'h10B671C711C4438884);
+ syndrome_o[5] = ^((data_i ^ 72'hAA0000000000000000) & 72'h20B5B65926488C9108);
+ syndrome_o[6] = ^((data_i ^ 72'hAA0000000000000000) & 72'h40CBDAAA4A91152210);
+ syndrome_o[7] = ^((data_i ^ 72'hAA0000000000000000) & 72'h807AED348D221A4420);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h83) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'hd) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h15) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h25) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h45) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h85) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h19) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h29) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h49) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h89) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h31) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h51) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h91) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h61) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'ha1) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'hc1) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h16) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h26) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h46) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h86) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'h1a) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'h2a) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'h8a) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'h32) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'h52) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'h92) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'h62) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha2) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'hc2) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'h1c) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'h2c) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'h4c) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'h8c) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'h34) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'h54) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'h94) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'h64) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'ha4) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hc4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'h38) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'h58) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'h98) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'h68) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'ha8) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hc8) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'h70) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hb0) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hd0) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'he0) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'h6d) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hd6) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'h3e) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hcb) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hb3) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hb5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hce) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'h79) ^ data_i[63];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [21:0]
+ prim_secded_inv_hamming_22_16_enc (logic [15:0] data_i);
+ logic [21:0] data_o;
+ data_o = 22'(data_i);
+ data_o[16] = 1'b0 ^ ^(data_o & 22'h00AD5B);
+ data_o[17] = 1'b1 ^ ^(data_o & 22'h00366D);
+ data_o[18] = 1'b0 ^ ^(data_o & 22'h00C78E);
+ data_o[19] = 1'b1 ^ ^(data_o & 22'h0007F0);
+ data_o[20] = 1'b0 ^ ^(data_o & 22'h00F800);
+ data_o[21] = 1'b1 ^ ^(data_o & 22'h1FFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_hamming_22_16_t
+ prim_secded_inv_hamming_22_16_dec (logic [21:0] data_i);
+ logic [15:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_hamming_22_16_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 22'h2A0000) & 22'h01AD5B);
+ syndrome_o[1] = ^((data_i ^ 22'h2A0000) & 22'h02366D);
+ syndrome_o[2] = ^((data_i ^ 22'h2A0000) & 22'h04C78E);
+ syndrome_o[3] = ^((data_i ^ 22'h2A0000) & 22'h0807F0);
+ syndrome_o[4] = ^((data_i ^ 22'h2A0000) & 22'h10F800);
+ syndrome_o[5] = ^((data_i ^ 22'h2A0000) & 22'h3FFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h23) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'h25) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h26) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h27) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'h29) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h2a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h2b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h2c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h2d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'h2e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'h2f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h31) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h32) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h33) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'h34) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h35) ^ data_i[15];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[5];
+ err_o[1] = |syndrome_o[4:0] & ~syndrome_o[5];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [38:0]
+ prim_secded_inv_hamming_39_32_enc (logic [31:0] data_i);
+ logic [38:0] data_o;
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h0056AAAD5B);
+ data_o[33] = 1'b1 ^ ^(data_o & 39'h009B33366D);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00E3C3C78E);
+ data_o[35] = 1'b1 ^ ^(data_o & 39'h0003FC07F0);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h0003FFF800);
+ data_o[37] = 1'b1 ^ ^(data_o & 39'h00FC000000);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h3FFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_hamming_39_32_t
+ prim_secded_inv_hamming_39_32_dec (logic [38:0] data_i);
+ logic [31:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_hamming_39_32_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 39'h2A00000000) & 39'h0156AAAD5B);
+ syndrome_o[1] = ^((data_i ^ 39'h2A00000000) & 39'h029B33366D);
+ syndrome_o[2] = ^((data_i ^ 39'h2A00000000) & 39'h04E3C3C78E);
+ syndrome_o[3] = ^((data_i ^ 39'h2A00000000) & 39'h0803FC07F0);
+ syndrome_o[4] = ^((data_i ^ 39'h2A00000000) & 39'h1003FFF800);
+ syndrome_o[5] = ^((data_i ^ 39'h2A00000000) & 39'h20FC000000);
+ syndrome_o[6] = ^((data_i ^ 39'h2A00000000) & 39'h7FFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h43) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h45) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h46) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h47) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h49) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h4a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h4b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h4d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h4e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h4f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h51) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h52) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h53) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h54) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h55) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h56) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h57) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h58) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h59) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h5a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h5b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h5c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h5d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h5e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h5f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h61) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h63) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h64) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h65) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h66) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[6];
+ err_o[1] = |syndrome_o[5:0] & ~syndrome_o[6];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [71:0]
+ prim_secded_inv_hamming_72_64_enc (logic [63:0] data_i);
+ logic [71:0] data_o;
+ data_o = 72'(data_i);
+ data_o[64] = 1'b0 ^ ^(data_o & 72'h00AB55555556AAAD5B);
+ data_o[65] = 1'b1 ^ ^(data_o & 72'h00CD9999999B33366D);
+ data_o[66] = 1'b0 ^ ^(data_o & 72'h00F1E1E1E1E3C3C78E);
+ data_o[67] = 1'b1 ^ ^(data_o & 72'h0001FE01FE03FC07F0);
+ data_o[68] = 1'b0 ^ ^(data_o & 72'h0001FFFE0003FFF800);
+ data_o[69] = 1'b1 ^ ^(data_o & 72'h0001FFFFFFFC000000);
+ data_o[70] = 1'b0 ^ ^(data_o & 72'h00FE00000000000000);
+ data_o[71] = 1'b1 ^ ^(data_o & 72'h7FFFFFFFFFFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_hamming_72_64_t
+ prim_secded_inv_hamming_72_64_dec (logic [71:0] data_i);
+ logic [63:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_hamming_72_64_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 72'hAA0000000000000000) & 72'h01AB55555556AAAD5B);
+ syndrome_o[1] = ^((data_i ^ 72'hAA0000000000000000) & 72'h02CD9999999B33366D);
+ syndrome_o[2] = ^((data_i ^ 72'hAA0000000000000000) & 72'h04F1E1E1E1E3C3C78E);
+ syndrome_o[3] = ^((data_i ^ 72'hAA0000000000000000) & 72'h0801FE01FE03FC07F0);
+ syndrome_o[4] = ^((data_i ^ 72'hAA0000000000000000) & 72'h1001FFFE0003FFF800);
+ syndrome_o[5] = ^((data_i ^ 72'hAA0000000000000000) & 72'h2001FFFFFFFC000000);
+ syndrome_o[6] = ^((data_i ^ 72'hAA0000000000000000) & 72'h40FE00000000000000);
+ syndrome_o[7] = ^((data_i ^ 72'hAA0000000000000000) & 72'hFFFFFFFFFFFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h83) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'h85) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h86) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h87) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h89) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h8a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'h8b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h8c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h8d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h8e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h8f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h91) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h92) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h93) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h94) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h95) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h96) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h97) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h98) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'h99) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'h9a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'h9b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h9c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h9d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h9e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h9f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'ha1) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'ha2) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'ha3) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'ha4) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'ha5) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'ha6) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'ha7) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'ha8) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha9) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'haa) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'hab) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'hac) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'had) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'hae) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'haf) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'hb0) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'hb1) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'hb2) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'hb3) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hb4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'hb5) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'hb6) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'hb7) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'hb8) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'hb9) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hba) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'hbb) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hbc) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hbd) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'hbe) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'hbf) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hc1) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'hc2) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hc3) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hc4) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hc5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hc6) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'hc7) ^ data_i[63];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[7];
+ err_o[1] = |syndrome_o[6:0] & ~syndrome_o[7];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [75:0]
+ prim_secded_inv_hamming_76_68_enc (logic [67:0] data_i);
+ logic [75:0] data_o;
+ data_o = 76'(data_i);
+ data_o[68] = 1'b0 ^ ^(data_o & 76'h00AAB55555556AAAD5B);
+ data_o[69] = 1'b1 ^ ^(data_o & 76'h00CCD9999999B33366D);
+ data_o[70] = 1'b0 ^ ^(data_o & 76'h000F1E1E1E1E3C3C78E);
+ data_o[71] = 1'b1 ^ ^(data_o & 76'h00F01FE01FE03FC07F0);
+ data_o[72] = 1'b0 ^ ^(data_o & 76'h00001FFFE0003FFF800);
+ data_o[73] = 1'b1 ^ ^(data_o & 76'h00001FFFFFFFC000000);
+ data_o[74] = 1'b0 ^ ^(data_o & 76'h00FFE00000000000000);
+ data_o[75] = 1'b1 ^ ^(data_o & 76'h7FFFFFFFFFFFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_hamming_76_68_t
+ prim_secded_inv_hamming_76_68_dec (logic [75:0] data_i);
+ logic [67:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_hamming_76_68_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 76'hAA00000000000000000) & 76'h01AAB55555556AAAD5B);
+ syndrome_o[1] = ^((data_i ^ 76'hAA00000000000000000) & 76'h02CCD9999999B33366D);
+ syndrome_o[2] = ^((data_i ^ 76'hAA00000000000000000) & 76'h040F1E1E1E1E3C3C78E);
+ syndrome_o[3] = ^((data_i ^ 76'hAA00000000000000000) & 76'h08F01FE01FE03FC07F0);
+ syndrome_o[4] = ^((data_i ^ 76'hAA00000000000000000) & 76'h10001FFFE0003FFF800);
+ syndrome_o[5] = ^((data_i ^ 76'hAA00000000000000000) & 76'h20001FFFFFFFC000000);
+ syndrome_o[6] = ^((data_i ^ 76'hAA00000000000000000) & 76'h40FFE00000000000000);
+ syndrome_o[7] = ^((data_i ^ 76'hAA00000000000000000) & 76'hFFFFFFFFFFFFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h83) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'h85) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h86) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h87) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h89) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h8a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'h8b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h8c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h8d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h8e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h8f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h91) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h92) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h93) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h94) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h95) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h96) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h97) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h98) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'h99) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'h9a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'h9b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h9c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h9d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h9e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h9f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'ha1) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'ha2) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'ha3) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'ha4) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'ha5) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'ha6) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'ha7) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'ha8) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha9) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'haa) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'hab) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'hac) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'had) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'hae) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'haf) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'hb0) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'hb1) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'hb2) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'hb3) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hb4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'hb5) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'hb6) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'hb7) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'hb8) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'hb9) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hba) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'hbb) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hbc) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hbd) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'hbe) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'hbf) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hc1) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'hc2) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hc3) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hc4) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hc5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hc6) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'hc7) ^ data_i[63];
+ data_o[64] = (syndrome_o == 8'hc8) ^ data_i[64];
+ data_o[65] = (syndrome_o == 8'hc9) ^ data_i[65];
+ data_o[66] = (syndrome_o == 8'hca) ^ data_i[66];
+ data_o[67] = (syndrome_o == 8'hcb) ^ data_i[67];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[7];
+ err_o[1] = |syndrome_o[6:0] & ~syndrome_o[7];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+
+endpackage
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_subreg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_subreg.sv
new file mode 100644
index 00000000..a004090e
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_subreg.sv
@@ -0,0 +1,76 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register slice conforming to Comportibility guide.
+
+module prim_subreg #(
+ parameter int DW = 32 ,
+ parameter SwAccess = "RW", // {RW, RO, WO, W1C, W1S, W0C, RC}
+ parameter logic [DW-1:0] RESVAL = '0 // Reset value
+) (
+ input clk_i,
+ input rst_ni,
+
+ // From SW: valid for RW, WO, W1C, W1S, W0C, RC
+ // In case of RC, Top connects Read Pulse to we
+ input we,
+ input [DW-1:0] wd,
+
+ // From HW: valid for HRW, HWO
+ input de,
+ input [DW-1:0] d,
+
+ // output to HW and Reg Read
+ output logic qe,
+ output logic [DW-1:0] q,
+ output logic [DW-1:0] qs
+);
+
+ logic wr_en ;
+ logic [DW-1:0] wr_data;
+
+ if ((SwAccess == "RW") || (SwAccess == "WO")) begin : gen_w
+ assign wr_en = we | de ;
+ assign wr_data = (we == 1'b1) ? wd : d ; // SW higher priority
+ end else if (SwAccess == "RO") begin : gen_ro
+ // Unused we, wd
+ assign wr_en = de ;
+ assign wr_data = d ;
+ end else if (SwAccess == "W1S") begin : gen_w1s
+ // If SWACCESS is W1S, then assume hw tries to clear.
+ // So, give a chance HW to clear when SW tries to set.
+ // If both try to set/clr at the same bit pos, SW wins.
+ assign wr_en = we | de ;
+ assign wr_data = (de ? d : q) | (we ? wd : '0);
+ end else if (SwAccess == "W1C") begin : gen_w1c
+ // If SWACCESS is W1C, then assume hw tries to set.
+ // So, give a chance HW to set when SW tries to clear.
+ // If both try to set/clr at the same bit pos, SW wins.
+ assign wr_en = we | de ;
+ assign wr_data = (de ? d : q) & (we ? ~wd : '1);
+ end else if (SwAccess == "W0C") begin : gen_w0c
+ assign wr_en = we | de ;
+ assign wr_data = (de ? d : q) & (we ? wd : '1);
+ end else if (SwAccess == "RC") begin : gen_rc
+ // This swtype is not recommended but exists for compatibility.
+ // WARN: we signal is actually read signal not write enable.
+ assign wr_en = we | de ;
+ assign wr_data = (de ? d : q) & (we ? '0 : '1);
+ end else begin : gen_hw
+ assign wr_en = de ;
+ assign wr_data = d ;
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) qe <= 1'b0;
+ else qe <= we ;
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) q <= RESVAL ;
+ else if (wr_en) q <= wr_data;
+ end
+ assign qs = q;
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_subreg_ext.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_subreg_ext.sv
new file mode 100644
index 00000000..6db975d8
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_subreg_ext.sv
@@ -0,0 +1,28 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register slice conforming to Comportibility guide.
+
+module prim_subreg_ext #(
+ parameter int unsigned DW = 32
+) (
+ input re,
+ input we,
+ input [DW-1:0] wd,
+
+ input [DW-1:0] d,
+
+ // output to HW and Reg Read
+ output logic qe,
+ output logic qre,
+ output logic [DW-1:0] q,
+ output logic [DW-1:0] qs
+);
+
+ assign qs = d;
+ assign q = wd;
+ assign qe = we;
+ assign qre = re;
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_subreg_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_subreg_pkg.sv
new file mode 100644
index 00000000..b0988e45
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_subreg_pkg.sv
@@ -0,0 +1,17 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package prim_subreg_pkg;
+
+ // Register access specifier
+ typedef enum logic [2:0] {
+ SwAccessRW = 3'd0, // Read-write
+ SwAccessRO = 3'd1, // Read-only
+ SwAccessWO = 3'd2, // Write-only
+ SwAccessW1C = 3'd3, // Write 1 to clear
+ SwAccessW1S = 3'd4, // Write 1 to set
+ SwAccessW0C = 3'd5, // Write 0 to clear
+ SwAccessRC = 3'd6 // Read to clear. Do not use, only exists for compatibility.
+ } sw_access_e;
+endpackage
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_util_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_util_pkg.sv
new file mode 100644
index 00000000..536fa294
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/prim_util_pkg.sv
@@ -0,0 +1,89 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Utility functions
+ */
+package prim_util_pkg;
+ /**
+ * Math function: $clog2 as specified in Verilog-2005
+ *
+ * Do not use this function if $clog2() is available.
+ *
+ * clog2 = 0 for value == 0
+ * ceil(log2(value)) for value >= 1
+ *
+ * This implementation is a synthesizable variant of the $clog2 function as
+ * specified in the Verilog-2005 standard (IEEE 1364-2005).
+ *
+ * To quote the standard:
+ * The system function $clog2 shall return the ceiling of the log
+ * base 2 of the argument (the log rounded up to an integer
+ * value). The argument can be an integer or an arbitrary sized
+ * vector value. The argument shall be treated as an unsigned
+ * value, and an argument value of 0 shall produce a result of 0.
+ */
+ function automatic integer _clog2(integer value);
+ integer result;
+ // Use an intermediate value to avoid assigning to an input port, which produces a warning in
+ // Synopsys DC.
+ integer v = value;
+ v = v - 1;
+ for (result = 0; v > 0; result++) begin
+ v = v >> 1;
+ end
+ return result;
+ endfunction
+
+
+ /**
+ * Math function: Number of bits needed to address |value| items.
+ *
+ * 0 for value == 0
+ * vbits = 1 for value == 1
+ * ceil(log2(value)) for value > 1
+ *
+ *
+ * The primary use case for this function is the definition of registers/arrays
+ * which are wide enough to contain |value| items.
+ *
+ * This function identical to $clog2() for all input values except the value 1;
+ * it could be considered an "enhanced" $clog2() function.
+ *
+ *
+ * Example 1:
+ * parameter Items = 1;
+ * localparam ItemsWidth = vbits(Items); // 1
+ * logic [ItemsWidth-1:0] item_register; // items_register is now [0:0]
+ *
+ * Example 2:
+ * parameter Items = 64;
+ * localparam ItemsWidth = vbits(Items); // 6
+ * logic [ItemsWidth-1:0] item_register; // items_register is now [5:0]
+ *
+ * Note: If you want to store the number "value" inside a register, you need
+ * a register with size vbits(value + 1), since you also need to store
+ * the number 0.
+ *
+ * Example 3:
+ * logic [vbits(64)-1:0] store_64_logic_values; // width is [5:0]
+ * logic [vbits(64 + 1)-1:0] store_number_64; // width is [6:0]
+ */
+ function automatic integer vbits(integer value);
+
+
+
+
+
+
+
+
+
+
+ return (value == 1) ? 1 : $clog2(value);
+
+ endfunction
+
+endpackage
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/pwrmgr_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/pwrmgr_pkg.sv
new file mode 100644
index 00000000..002f6d7f
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/pwrmgr_pkg.sv
@@ -0,0 +1,274 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Power Manager Package
+//
+
+package pwrmgr_pkg;
+
+ // global constant
+ parameter int ALWAYS_ON_DOMAIN = 0;
+
+ // variables referenced by other modules / packages
+ parameter int PowerDomains = 2; // this needs to be a topgen populated number, or from topcfg?
+
+ // variables referenced only by pwrmgr
+ localparam int TotalWakeWidth = pwrmgr_reg_pkg::NumWkups + 2; // Abort and fall through are added
+
+ typedef enum logic [1:0] {
+ IntReqMainPwr,
+ IntReqEsc,
+ IntReqLastIdx
+ } pwr_int_rst_req_e;
+
+ parameter int NumSwRstReq = 1;
+
+ // position of escalation request
+ parameter int HwResetWidth = pwrmgr_reg_pkg::NumRstReqs + int'(IntReqLastIdx);
+ parameter int TotalResetWidth = HwResetWidth + NumSwRstReq;
+ parameter int ResetMainPwrIdx = pwrmgr_reg_pkg::NumRstReqs + int'(IntReqMainPwr);
+ parameter int ResetEscIdx = pwrmgr_reg_pkg::NumRstReqs + int'(IntReqEsc);
+ parameter int ResetSwReqIdx = TotalResetWidth - 1;
+
+ // pwrmgr to ast
+ typedef struct packed {
+ logic main_pd_n;
+ logic pwr_clamp_env;
+ logic pwr_clamp;
+ logic slow_clk_en;
+ logic core_clk_en;
+ logic io_clk_en;
+ logic usb_clk_en;
+ } pwr_ast_req_t;
+
+ typedef struct packed {
+ logic slow_clk_val;
+ logic core_clk_val;
+ logic io_clk_val;
+ logic usb_clk_val;
+ logic main_pok;
+ } pwr_ast_rsp_t;
+
+ // default value of pwr_ast_rsp (for dangling ports)
+ parameter pwr_ast_rsp_t PWR_AST_RSP_DEFAULT = '{
+ slow_clk_val: 1'b1,
+ core_clk_val: 1'b1,
+ io_clk_val: 1'b1,
+ usb_clk_val: 1'b1,
+ main_pok: 1'b1
+ };
+
+ parameter pwr_ast_rsp_t PWR_AST_RSP_SYNC_DEFAULT = '{
+ slow_clk_val: 1'b0,
+ core_clk_val: 1'b0,
+ io_clk_val: 1'b0,
+ usb_clk_val: 1'b0,
+ main_pok: 1'b0
+ };
+
+ // reasons for pwrmgr reset
+ typedef enum logic [1:0] {
+ ResetNone = 0, // there is no reset
+ LowPwrEntry = 1, // reset is caused by low power entry
+ HwReq = 2, // reset is caused by peripheral reset requests
+ ResetUndefined = 3 // this should never happen outside of POR
+ } reset_cause_e;
+
+ // pwrmgr to rstmgr
+ typedef struct packed {
+ logic [PowerDomains-1:0] rst_lc_req;
+ logic [PowerDomains-1:0] rst_sys_req;
+ logic [HwResetWidth-1:0] rstreqs;
+ reset_cause_e reset_cause;
+ } pwr_rst_req_t;
+
+ // rstmgr to pwrmgr
+ typedef struct packed {
+ logic [PowerDomains-1:0] rst_lc_src_n;
+ logic [PowerDomains-1:0] rst_sys_src_n;
+ } pwr_rst_rsp_t;
+
+ // default value (for dangling ports)
+ parameter pwr_rst_rsp_t PWR_RST_RSP_DEFAULT = '{
+ rst_lc_src_n: {PowerDomains{1'b1}},
+ rst_sys_src_n: {PowerDomains{1'b1}}
+ };
+
+ // pwrmgr to clkmgr
+ typedef struct packed {
+ logic main_ip_clk_en;
+ logic io_ip_clk_en;
+ logic usb_ip_clk_en;
+ } pwr_clk_req_t;
+
+ // clkmgr to pwrmgr
+ typedef struct packed {
+ logic main_status;
+ logic io_status;
+ logic usb_status;
+ } pwr_clk_rsp_t;
+
+ // pwrmgr to otp
+ typedef struct packed {
+ logic otp_init;
+ } pwr_otp_req_t;
+
+ // otp to pwrmgr
+ typedef struct packed {
+ logic otp_done;
+ logic otp_idle;
+ } pwr_otp_rsp_t;
+
+ // default value (for dangling ports)
+ parameter pwr_otp_rsp_t PWR_OTP_RSP_DEFAULT = '{
+ otp_done: 1'b1,
+ otp_idle: 1'b1
+ };
+
+ // pwrmgr to lifecycle
+ typedef struct packed {
+ logic lc_init;
+ } pwr_lc_req_t;
+
+ // lifecycle to pwrmgr
+ typedef struct packed {
+ logic lc_done;
+ logic lc_idle;
+ } pwr_lc_rsp_t;
+
+ // default value (for dangling ports)
+ parameter pwr_lc_rsp_t PWR_LC_RSP_DEFAULT = '{
+ lc_done: 1'b1,
+ lc_idle: 1'b1
+ };
+
+ typedef struct packed {
+ logic flash_idle;
+ } pwr_flash_t;
+
+ parameter pwr_flash_t PWR_FLASH_DEFAULT = '{
+ flash_idle: 1'b1
+ };
+
+ // processor to pwrmgr
+ typedef struct packed {
+ logic core_sleeping;
+ } pwr_cpu_t;
+
+ // default value (for dangling ports)
+ parameter pwr_cpu_t PWR_CPU_DEFAULT = '{
+ core_sleeping: 1'b0
+ };
+
+ // default value (for dangling ports)
+ parameter int WAKEUPS_DEFAULT = '0;
+ parameter int RSTREQS_DEFAULT = '0;
+
+ // peripherals to pwrmgr
+ typedef struct packed {
+ logic [pwrmgr_reg_pkg::NumWkups-1:0] wakeups;
+ // reset requests include external requests + escalation reset
+ logic [TotalResetWidth-1:0] rstreqs;
+ } pwr_peri_t;
+
+ // power-up causes
+ typedef enum logic [1:0] {
+ Por = 2'h0,
+ Wake = 2'h1,
+ Reset = 2'h2
+ } pwrup_cause_e;
+
+ // low power hints
+ typedef enum logic {
+ None = 1'b0,
+ LowPower = 1'b1
+ } low_power_hint_e;
+
+ // fast fsm state enum
+ // Encoding generated with:
+ // $ ./util/design/sparse-fsm-encode.py -d 5 -m 17 -n 12 \
+ // -s 4233784300 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: ||||||||||||||||| (30.15%)
+ // 6: |||||||||||||||||||| (35.29%)
+ // 7: |||||||||| (19.12%)
+ // 8: ||||| (9.56%)
+ // 9: | (2.21%)
+ // 10: | (2.21%)
+ // 11: (1.47%)
+ // 12: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 11
+ // Minimum Hamming weight: 3
+ // Maximum Hamming weight: 9
+ //
+ localparam int FastPwrStateWidth = 12;
+ typedef enum logic [FastPwrStateWidth-1:0] {
+ FastPwrStateLowPower = 12'b111010101011,
+ FastPwrStateEnableClocks = 12'b000011000010,
+ FastPwrStateReleaseLcRst = 12'b111011010110,
+ FastPwrStateOtpInit = 12'b100101011010,
+ FastPwrStateLcInit = 12'b010001111100,
+ FastPwrStateStrap = 12'b010110111010,
+ FastPwrStateAckPwrUp = 12'b010100100101,
+ FastPwrStateRomCheck = 12'b101100000011,
+ FastPwrStateActive = 12'b100001010101,
+ FastPwrStateDisClks = 12'b010000010011,
+ FastPwrStateFallThrough = 12'b111111011001,
+ FastPwrStateNvmIdleChk = 12'b001111110011,
+ FastPwrStateLowPowerPrep = 12'b011101001111,
+ FastPwrStateNvmShutDown = 12'b001010011111,
+ FastPwrStateResetPrep = 12'b101000110000,
+ FastPwrStateReqPwrDn = 12'b101101101100,
+ FastPwrStateInvalid = 12'b100010001100
+ } fast_pwr_state_e;
+
+ // Encoding generated with:
+ // $ ./util/design/sparse-fsm-encode.py -d 5 -m 12 -n 10 \
+ // -s 1726685338 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: |||||||||||||||||||| (54.55%)
+ // 6: |||||||||||||||| (45.45%)
+ // 7: --
+ // 8: --
+ // 9: --
+ // 10: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 6
+ // Minimum Hamming weight: 2
+ // Maximum Hamming weight: 8
+ //
+ localparam int SlowPwrStateWidth = 10;
+ typedef enum logic [SlowPwrStateWidth-1:0] {
+ SlowPwrStateReset = 10'b0000100010,
+ SlowPwrStateLowPower = 10'b1011000111,
+ SlowPwrStateMainPowerOn = 10'b0110101111,
+ SlowPwrStatePwrClampOff = 10'b0110010001,
+ SlowPwrStateClocksOn = 10'b1010111100,
+ SlowPwrStateReqPwrUp = 10'b0011011010,
+ SlowPwrStateIdle = 10'b1111100000,
+ SlowPwrStateAckPwrDn = 10'b0001110101,
+ SlowPwrStateClocksOff = 10'b1101111011,
+ SlowPwrStatePwrClampOn = 10'b0101001100,
+ SlowPwrStateMainPowerOff = 10'b1000001001,
+ SlowPwrStateInvalid = 10'b1100010110
+ } slow_pwr_state_e;
+
+endpackage // pwrmgr_pkg
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/pwrmgr_reg_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/pwrmgr_reg_pkg.sv
new file mode 100644
index 00000000..ef381aa9
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/pwrmgr_reg_pkg.sv
@@ -0,0 +1,217 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package pwrmgr_reg_pkg;
+
+ // Param list
+ parameter int NumWkups = 1;
+ parameter int NumRstReqs = 1;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } pwrmgr_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } low_power_hint;
+ struct packed {
+ logic q;
+ } core_clk_en;
+ struct packed {
+ logic q;
+ } io_clk_en;
+ struct packed {
+ logic q;
+ } usb_clk_en_lp;
+ struct packed {
+ logic q;
+ } usb_clk_en_active;
+ struct packed {
+ logic q;
+ } main_pd_n;
+ } pwrmgr_reg2hw_control_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } pwrmgr_reg2hw_cfg_cdc_sync_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_wakeup_en_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_reset_en_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_wake_info_capture_dis_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } reasons;
+ struct packed {
+ logic q;
+ logic qe;
+ } fall_through;
+ struct packed {
+ logic q;
+ logic qe;
+ } abort;
+ } pwrmgr_reg2hw_wake_info_reg_t;
+
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ logic d;
+ } pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } low_power_hint;
+ } pwrmgr_hw2reg_control_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_cfg_cdc_sync_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_wake_status_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_reset_status_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_escalate_reset_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ } reasons;
+ struct packed {
+ logic d;
+ } fall_through;
+ struct packed {
+ logic d;
+ } abort;
+ } pwrmgr_hw2reg_wake_info_reg_t;
+
+
+ ///////////////////////////////////////
+ // Register to internal design logic //
+ ///////////////////////////////////////
+ typedef struct packed {
+ pwrmgr_reg2hw_intr_state_reg_t intr_state; // [20:20]
+ pwrmgr_reg2hw_intr_enable_reg_t intr_enable; // [19:19]
+ pwrmgr_reg2hw_intr_test_reg_t intr_test; // [18:17]
+ pwrmgr_reg2hw_control_reg_t control; // [16:11]
+ pwrmgr_reg2hw_cfg_cdc_sync_reg_t cfg_cdc_sync; // [10:9]
+ pwrmgr_reg2hw_wakeup_en_mreg_t [0:0] wakeup_en; // [8:8]
+ pwrmgr_reg2hw_reset_en_mreg_t [0:0] reset_en; // [7:7]
+ pwrmgr_reg2hw_wake_info_capture_dis_reg_t wake_info_capture_dis; // [6:6]
+ pwrmgr_reg2hw_wake_info_reg_t wake_info; // [5:0]
+ } pwrmgr_reg2hw_t;
+
+ ///////////////////////////////////////
+ // Internal design logic to register //
+ ///////////////////////////////////////
+ typedef struct packed {
+ pwrmgr_hw2reg_intr_state_reg_t intr_state; // [15:14]
+ pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t ctrl_cfg_regwen; // [13:13]
+ pwrmgr_hw2reg_control_reg_t control; // [12:11]
+ pwrmgr_hw2reg_cfg_cdc_sync_reg_t cfg_cdc_sync; // [10:9]
+ pwrmgr_hw2reg_wake_status_mreg_t [0:0] wake_status; // [8:7]
+ pwrmgr_hw2reg_reset_status_mreg_t [0:0] reset_status; // [6:5]
+ pwrmgr_hw2reg_escalate_reset_status_reg_t escalate_reset_status; // [4:3]
+ pwrmgr_hw2reg_wake_info_reg_t wake_info; // [2:0]
+ } pwrmgr_hw2reg_t;
+
+ // Register Address
+ parameter logic [5:0] PWRMGR_INTR_STATE_OFFSET = 6'h0;
+ parameter logic [5:0] PWRMGR_INTR_ENABLE_OFFSET = 6'h4;
+ parameter logic [5:0] PWRMGR_INTR_TEST_OFFSET = 6'h8;
+ parameter logic [5:0] PWRMGR_CTRL_CFG_REGWEN_OFFSET = 6'hc;
+ parameter logic [5:0] PWRMGR_CONTROL_OFFSET = 6'h10;
+ parameter logic [5:0] PWRMGR_CFG_CDC_SYNC_OFFSET = 6'h14;
+ parameter logic [5:0] PWRMGR_WAKEUP_EN_REGWEN_OFFSET = 6'h18;
+ parameter logic [5:0] PWRMGR_WAKEUP_EN_OFFSET = 6'h1c;
+ parameter logic [5:0] PWRMGR_WAKE_STATUS_OFFSET = 6'h20;
+ parameter logic [5:0] PWRMGR_RESET_EN_REGWEN_OFFSET = 6'h24;
+ parameter logic [5:0] PWRMGR_RESET_EN_OFFSET = 6'h28;
+ parameter logic [5:0] PWRMGR_RESET_STATUS_OFFSET = 6'h2c;
+ parameter logic [5:0] PWRMGR_ESCALATE_RESET_STATUS_OFFSET = 6'h30;
+ parameter logic [5:0] PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET = 6'h34;
+ parameter logic [5:0] PWRMGR_WAKE_INFO_OFFSET = 6'h38;
+
+
+ // Register Index
+ typedef enum int {
+ PWRMGR_INTR_STATE,
+ PWRMGR_INTR_ENABLE,
+ PWRMGR_INTR_TEST,
+ PWRMGR_CTRL_CFG_REGWEN,
+ PWRMGR_CONTROL,
+ PWRMGR_CFG_CDC_SYNC,
+ PWRMGR_WAKEUP_EN_REGWEN,
+ PWRMGR_WAKEUP_EN,
+ PWRMGR_WAKE_STATUS,
+ PWRMGR_RESET_EN_REGWEN,
+ PWRMGR_RESET_EN,
+ PWRMGR_RESET_STATUS,
+ PWRMGR_ESCALATE_RESET_STATUS,
+ PWRMGR_WAKE_INFO_CAPTURE_DIS,
+ PWRMGR_WAKE_INFO
+ } pwrmgr_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] PWRMGR_PERMIT [15] = '{
+ 4'b0001, // index[ 0] PWRMGR_INTR_STATE
+ 4'b0001, // index[ 1] PWRMGR_INTR_ENABLE
+ 4'b0001, // index[ 2] PWRMGR_INTR_TEST
+ 4'b0001, // index[ 3] PWRMGR_CTRL_CFG_REGWEN
+ 4'b0011, // index[ 4] PWRMGR_CONTROL
+ 4'b0001, // index[ 5] PWRMGR_CFG_CDC_SYNC
+ 4'b0001, // index[ 6] PWRMGR_WAKEUP_EN_REGWEN
+ 4'b0001, // index[ 7] PWRMGR_WAKEUP_EN
+ 4'b0001, // index[ 8] PWRMGR_WAKE_STATUS
+ 4'b0001, // index[ 9] PWRMGR_RESET_EN_REGWEN
+ 4'b0001, // index[10] PWRMGR_RESET_EN
+ 4'b0001, // index[11] PWRMGR_RESET_STATUS
+ 4'b0001, // index[12] PWRMGR_ESCALATE_RESET_STATUS
+ 4'b0001, // index[13] PWRMGR_WAKE_INFO_CAPTURE_DIS
+ 4'b0001 // index[14] PWRMGR_WAKE_INFO
+ };
+endpackage
+
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/sha2.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/sha2.sv
new file mode 100644
index 00000000..0779c22d
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/sha2.sv
@@ -0,0 +1,323 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SHA-256 algorithm
+//
+
+module sha2 import hmac_pkg::*; (
+ input clk_i,
+ input rst_ni,
+
+ input wipe_secret,
+ input sha_word_t wipe_v,
+
+ // FIFO read signal
+ input fifo_rvalid,
+ input sha_fifo_t fifo_rdata,
+ output logic fifo_rready,
+
+ // Control signals
+ input sha_en, // If disabled, it clears internal content.
+ input hash_start,
+ input hash_process,
+ output logic hash_done,
+
+ input [63:0] message_length, // bits but byte based
+ output sha_word_t [7:0] digest,
+
+ output logic idle
+);
+
+ localparam int unsigned RoundWidth = $clog2(NumRound);
+
+ logic msg_feed_complete;
+
+ logic shaf_rready;
+ sha_word_t shaf_rdata;
+ logic shaf_rvalid;
+
+ logic [RoundWidth-1:0] round;
+
+ logic [3:0] w_index;
+ sha_word_t [15:0] w;
+
+ localparam sha_word_t ZeroWord = '0;
+
+ // w, hash, digest update logic control signals
+ logic update_w_from_fifo, calculate_next_w;
+ logic init_hash, run_hash, complete_one_chunk;
+ logic update_digest, clear_digest;
+
+ logic hash_done_next; // to meet the phase with digest value.
+
+ sha_word_t [7:0] hash; // a,b,c,d,e,f,g,h
+
+ // Fill up w
+ always_ff @(posedge clk_i or negedge rst_ni) begin : fill_w
+ if (!rst_ni) begin
+ w <= '0;
+ end else if (wipe_secret) begin
+ w <= w ^ {16{wipe_v}};
+ end else if (!sha_en) begin
+ w <= '0;
+ end else if (!run_hash && update_w_from_fifo) begin
+ // this logic runs at the first stage of SHA.
+ w <= {shaf_rdata, w[15:1]};
+ end else if (calculate_next_w) begin
+ w <= {calc_w(w[0], w[1], w[9], w[14]), w[15:1]};
+ //end else if (run_hash && update_w_from_fifo) begin
+ // // This code runs when round is in [48, 63]. At this time, it reads from the fifo
+ // // to fill the register if available. If FIFO goes to empty, w_index doesn't increase
+ // // and it cannot reach 15. Then the sha engine doesn't start, which introduces latency.
+ // //
+ // // But in this case, still w should be shifted to feed SHA compress engine. Then
+ // // fifo_rdata should be inserted in the middle of w index.
+ // // w[64-round + w_index] <= fifo_rdata;
+ // for (int i = 0 ; i < 16 ; i++) begin
+ // if (i == (64 - round + w_index)) begin
+ // w[i] <= shaf_rdata;
+ // end else if (i == 15) begin
+ // w[i] <= '0;
+ // end else begin
+ // w[i] <= w[i+1];
+ // end
+ // end
+ end else if (run_hash) begin
+ // Just shift-out. There's no incoming data
+ w <= {ZeroWord, w[15:1]};
+ end
+ end : fill_w
+
+ // Update engine
+ always_ff @(posedge clk_i or negedge rst_ni) begin : compress_round
+ if (!rst_ni) begin
+ hash <= '{default:'0};
+ end else if (wipe_secret) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ hash[i] <= hash[i] ^ wipe_v;
+ end
+ end else if (init_hash) begin
+ hash <= digest;
+ end else if (run_hash) begin
+ hash <= compress( w[0], CubicRootPrime[round], hash);
+ end
+ end : compress_round
+
+ // Digest
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ digest <= '{default: '0};
+ end else if (wipe_secret) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ digest[i] <= digest[i] ^ wipe_v;
+ end
+ end else if (hash_start) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ digest[i] <= InitHash[i];
+ end
+ end else if (!sha_en || clear_digest) begin
+ digest <= '0;
+ end else if (update_digest) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ digest[i] <= digest[i] + hash[i];
+ end
+ end
+ end
+
+ // round
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ round <= '0;
+ end else if (!sha_en) begin
+ round <= '0;
+ end else if (run_hash) begin
+ if (round == RoundWidth'(unsigned'(NumRound-1))) begin
+ round <= '0;
+ end else begin
+ round <= round + 1;
+ end
+ end
+ end
+
+ // w_index
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ w_index <= '0;
+ end else if (!sha_en) begin
+ w_index <= '0;
+ end else if (update_w_from_fifo) begin
+ w_index <= w_index + 1;
+ end
+ end
+
+ assign shaf_rready = update_w_from_fifo;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) hash_done <= 1'b0;
+ else hash_done <= hash_done_next;
+ end
+
+ typedef enum logic [1:0] {
+ FifoIdle,
+ FifoLoadFromFifo,
+ FifoWait
+ } fifoctl_state_e;
+
+ fifoctl_state_e fifo_st_q, fifo_st_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_st_q <= FifoIdle;
+ end else begin
+ fifo_st_q <= fifo_st_d;
+ end
+ end
+
+ always_comb begin
+ fifo_st_d = FifoIdle;
+ update_w_from_fifo = 1'b0;
+ hash_done_next = 1'b0;
+
+ unique case (fifo_st_q)
+ FifoIdle: begin
+ if (hash_start) begin
+ fifo_st_d = FifoLoadFromFifo;
+ end else begin
+ fifo_st_d = FifoIdle;
+ end
+ end
+
+ FifoLoadFromFifo: begin
+ if (!sha_en) begin
+ fifo_st_d = FifoIdle;
+ update_w_from_fifo = 1'b0;
+ end else if (!shaf_rvalid) begin
+ // Wait until it is filled
+ fifo_st_d = FifoLoadFromFifo;
+ update_w_from_fifo = 1'b0;
+ end else if (w_index == 4'd15) begin
+ fifo_st_d = FifoWait;
+ update_w_from_fifo = 1'b1;
+ end else begin
+ fifo_st_d = FifoLoadFromFifo;
+ update_w_from_fifo = 1'b1;
+ end
+ end
+
+ FifoWait: begin
+ // Wait until next fetch begins (begin at round == 48)a
+ if (msg_feed_complete && complete_one_chunk) begin
+ fifo_st_d = FifoIdle;
+
+ hash_done_next = 1'b1;
+ end else if (complete_one_chunk) begin
+ fifo_st_d = FifoLoadFromFifo;
+ end else begin
+ fifo_st_d = FifoWait;
+ end
+ end
+
+ default: begin
+ fifo_st_d = FifoIdle;
+ end
+ endcase
+ end
+
+ // SHA control
+ typedef enum logic [1:0] {
+ ShaIdle,
+ ShaCompress,
+ ShaUpdateDigest
+ } sha_st_t;
+
+ sha_st_t sha_st_q, sha_st_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ sha_st_q <= ShaIdle;
+ end else begin
+ sha_st_q <= sha_st_d;
+ end
+ end
+
+ assign clear_digest = hash_start;
+
+ always_comb begin
+ update_digest = 1'b0;
+ calculate_next_w = 1'b0;
+
+ init_hash = 1'b0;
+ run_hash = 1'b0;
+
+ unique case (sha_st_q)
+ ShaIdle: begin
+ if (fifo_st_q == FifoWait) begin
+ init_hash = 1'b1;
+ sha_st_d = ShaCompress;
+ end else begin
+ sha_st_d = ShaIdle;
+ end
+ end
+
+ ShaCompress: begin
+ run_hash = 1'b1;
+
+ if (round < 48) begin
+ calculate_next_w = 1'b1;
+ end
+
+ if (complete_one_chunk) begin
+ sha_st_d = ShaUpdateDigest;
+ end else begin
+ sha_st_d = ShaCompress;
+ end
+ end
+
+ ShaUpdateDigest: begin
+ update_digest = 1'b1;
+ if (fifo_st_q == FifoWait) begin
+ init_hash = 1'b1;
+ sha_st_d = ShaCompress;
+ end else begin
+ sha_st_d = ShaIdle;
+ end
+ end
+
+ default: begin
+ sha_st_d = ShaIdle;
+ end
+ endcase
+ end
+
+ // complete_one_chunk
+ assign complete_one_chunk = (round == 6'd63);
+
+ sha2_pad u_pad (
+ .clk_i,
+ .rst_ni,
+
+ .wipe_secret,
+ .wipe_v,
+
+ .fifo_rvalid,
+ .fifo_rdata,
+ .fifo_rready,
+
+ .shaf_rvalid,
+ .shaf_rdata,
+ .shaf_rready,
+
+ .sha_en,
+ .hash_start,
+ .hash_process,
+ .hash_done,
+
+ .message_length,
+ .msg_feed_complete
+ );
+
+ // Idle
+ assign idle = (fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && !hash_start;
+
+endmodule : sha2
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/sha2_pad.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/sha2_pad.sv
new file mode 100644
index 00000000..6b249fc0
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/sha2_pad.sv
@@ -0,0 +1,311 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SHA-256 Padding logic
+//
+
+
+module sha2_pad import hmac_pkg::*; (
+ input clk_i,
+ input rst_ni,
+
+ input wipe_secret,
+ input sha_word_t wipe_v,
+
+ // To actual FIFO
+ input fifo_rvalid,
+ input sha_fifo_t fifo_rdata,
+ output logic fifo_rready,
+
+ // from SHA2 compress engine
+ output logic shaf_rvalid,
+ output sha_word_t shaf_rdata,
+ input shaf_rready,
+
+ input sha_en,
+ input hash_start,
+ input hash_process,
+ input hash_done,
+
+ input [63:0] message_length, // # of bytes in bits (8 bits granularity)
+ output logic msg_feed_complete // Indicates, all message is feeded
+);
+
+ //logic [8:0] length_added;
+
+ logic [63:0] tx_count; // fin received data count.
+
+ logic inc_txcount;
+ logic fifo_partial;
+ logic txcnt_eq_1a0;
+ logic hash_process_flag; // Set by hash_process, clear by hash_done
+
+ assign fifo_partial = ~&fifo_rdata.mask;
+
+ // tx_count[8:0] == 'h1c0 --> should send LenHi
+ assign txcnt_eq_1a0 = (tx_count[8:0] == 9'h1a0);
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ hash_process_flag <= 1'b0;
+ end else if (hash_process) begin
+ hash_process_flag <= 1'b1;
+ end else if (hash_done || hash_start) begin
+ hash_process_flag <= 1'b0;
+ end
+ end
+
+ // Data path: fout_wdata
+ typedef enum logic [2:0] {
+ FifoIn, // fin_wdata, fin_wstrb
+ Pad80, // {8'h80, 8'h00} , strb (calc based on len[4:3])
+ Pad00, // 32'h0, full strb
+ LenHi, // len[63:32], full strb
+ LenLo // len[31:0], full strb
+ } sel_data_e;
+ sel_data_e sel_data;
+
+ always_comb begin
+ unique case (sel_data)
+ FifoIn: begin
+ shaf_rdata = fifo_rdata.data;
+ end
+
+ Pad80: begin
+ // {a[7:0], b[7:0], c[7:0], d[7:0]}
+ // msglen[4:3] == 00 |-> {'h80, 'h00, 'h00, 'h00}
+ // msglen[4:3] == 01 |-> {msg, 'h80, 'h00, 'h00}
+ // msglen[4:3] == 10 |-> {msg[15:0], 'h80, 'h00}
+ // msglen[4:3] == 11 |-> {msg[23:0], 'h80}
+ unique case (message_length[4:3])
+ 2'b00: shaf_rdata = 32'h8000_0000;
+ 2'b01: shaf_rdata = {fifo_rdata.data[31:24], 24'h8000_00};
+ 2'b10: shaf_rdata = {fifo_rdata.data[31:16], 16'h8000};
+ 2'b11: shaf_rdata = {fifo_rdata.data[31: 8], 8'h80};
+ default: shaf_rdata = 32'h0;
+ endcase
+ end
+
+ Pad00: begin
+ shaf_rdata = '0;
+ end
+
+ LenHi: begin
+ shaf_rdata = message_length[63:32];
+ end
+
+ LenLo: begin
+ shaf_rdata = message_length[31:0];
+ end
+
+ default: begin
+ shaf_rdata = '0;
+ end
+ endcase
+ end
+
+ // Padded length
+ // $ceil(message_length + 8 + 64, 512) -> message_length [8:0] + 440 and ignore carry
+ //assign length_added = (message_length[8:0] + 9'h1b8) ;
+
+ // fifo control
+ // add 8'h 80 , N 8'h00, 64'h message_length
+
+ // Steps
+ // 1. `hash_start` from CPU (or DMA?)
+ // 2. calculate `padded_length` from `message_length`
+ // 3. Check if tx_count == message_length, then go to 5
+ // 4. Receiving FIFO input (hand over to fifo output)
+ // 5. Padding bit 1 (8'h80) followed by 8'h00 if needed
+ // 6. Padding with length (high -> low)
+
+ // State Machine
+ typedef enum logic [2:0] {
+ StIdle, // fin_full to prevent unwanted FIFO write
+ StFifoReceive, // Check tx_count == message_length
+ StPad80, // 8'h 80 + 8'h 00 X N
+ StPad00,
+ StLenHi,
+ StLenLo
+ } pad_st_e;
+
+ pad_st_e st_q, st_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ st_q <= StIdle;
+ end else begin
+ st_q <= st_d;
+ end
+ end
+
+ // Next state
+ always_comb begin
+ shaf_rvalid = 1'b0;
+ inc_txcount = 1'b0;
+ sel_data = FifoIn;
+ fifo_rready = 1'b0;
+
+ st_d = StIdle;
+
+ unique case (st_q)
+ StIdle: begin
+ sel_data = FifoIn;
+ shaf_rvalid = 1'b0;
+
+ if (sha_en && hash_start) begin
+ inc_txcount = 1'b0;
+
+ st_d = StFifoReceive;
+ end else begin
+ st_d = StIdle;
+ end
+ end
+
+ StFifoReceive: begin
+ sel_data = FifoIn;
+
+ if (fifo_partial && fifo_rvalid) begin
+ // End of the message, assume hash_process_flag is set
+ shaf_rvalid = 1'b0; // Update entry at StPad80
+ inc_txcount = 1'b0;
+ fifo_rready = 1'b0;
+
+ st_d = StPad80;
+ end else if (!hash_process_flag) begin
+ fifo_rready = shaf_rready;
+ shaf_rvalid = fifo_rvalid;
+ inc_txcount = shaf_rready;
+
+ st_d = StFifoReceive;
+ end else if (tx_count == message_length) begin
+ // already received all msg and was waiting process flag
+ shaf_rvalid = 1'b0;
+ inc_txcount = 1'b0;
+ fifo_rready = 1'b0;
+
+ st_d = StPad80;
+ end else begin
+ shaf_rvalid = fifo_rvalid;
+ fifo_rready = shaf_rready; // 0 always
+ inc_txcount = shaf_rready; // 0 always
+
+ st_d = StFifoReceive;
+ end
+ end
+
+ StPad80: begin
+ sel_data = Pad80;
+
+ shaf_rvalid = 1'b1;
+ fifo_rready = shaf_rready && |message_length[4:3]; // Only when partial
+
+ // exactly 96 bits left, do not need to pad00's
+ if (shaf_rready && txcnt_eq_1a0) begin
+ st_d = StLenHi;
+ inc_txcount = 1'b1;
+ // it does not matter if value is < or > than 416 bits. If it's the former, 00 pad until
+ // length field. If >, then the next chunk will contain the length field with appropriate
+ // 0 padding.
+ end else if (shaf_rready && !txcnt_eq_1a0) begin
+ st_d = StPad00;
+ inc_txcount = 1'b1;
+ end else begin
+ st_d = StPad80;
+ inc_txcount = 1'b0;
+ end
+
+ // # Below part is temporal code to speed up the SHA by 16 clocks per chunk
+ // # (80 clk --> 64 clk)
+ // # leaving this as a reference but needs to verify it.
+ //if (shaf_rready && !txcnt_eq_1a0) begin
+ // st_d = StPad00;
+ //
+ // inc_txcount = 1'b1;
+ // shaf_rvalid = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
+ // fifo_rready = (msg_word_aligned) ? 1'b0 : 1'b1;
+ //end else if (!shaf_rready && !txcnt_eq_1a0) begin
+ // st_d = StPad80;
+ //
+ // inc_txcount = 1'b0;
+ // shaf_rvalid = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
+ //
+ //end else if (shaf_rready && txcnt_eq_1a0) begin
+ // st_d = StLenHi;
+ // inc_txcount = 1'b1;
+ //end else begin
+ // // !shaf_rready && txcnt_eq_1a0 , just wait until fifo_rready asserted
+ // st_d = StPad80;
+ // inc_txcount = 1'b0;
+ //end
+ end
+
+ StPad00: begin
+ sel_data = Pad00;
+ shaf_rvalid = 1'b1;
+
+ if (shaf_rready) begin
+ inc_txcount = 1'b1;
+
+ if (txcnt_eq_1a0) begin
+ st_d = StLenHi;
+ end else begin
+ st_d = StPad00;
+ end
+ end else begin
+ st_d = StPad00;
+ end
+ end
+
+ StLenHi: begin
+ sel_data = LenHi;
+ shaf_rvalid = 1'b1;
+
+ if (shaf_rready) begin
+ st_d = StLenLo;
+
+ inc_txcount = 1'b1;
+ end else begin
+ st_d = StLenHi;
+
+ inc_txcount = 1'b0;
+ end
+ end
+
+ StLenLo: begin
+ sel_data = LenLo;
+ shaf_rvalid = 1'b1;
+
+ if (shaf_rready) begin
+ st_d = StIdle;
+
+ inc_txcount = 1'b1;
+ end else begin
+ st_d = StLenLo;
+
+ inc_txcount = 1'b0;
+ end
+ end
+
+ default: begin
+ st_d = StIdle;
+ end
+ endcase
+ end
+
+ // tx_count
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ tx_count <= '0;
+ end else if (hash_start) begin
+ tx_count <= '0;
+ end else if (inc_txcount) begin
+ tx_count[63:5] <= tx_count[63:5] + 1'b1;
+ end
+ end
+
+ // State machine is in Idle only when it meets tx_count == message length
+ assign msg_feed_complete = hash_process_flag && (st_q == StIdle);
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_adapter_reg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_adapter_reg.sv
new file mode 100644
index 00000000..5fcf48bf
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_adapter_reg.sv
@@ -0,0 +1,138 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Tile-Link UL adapter for Register interface
+ */
+
+module tlul_adapter_reg import tlul_pkg::*; #(
+ parameter int RegAw = 8,
+ parameter int EnableDataIntgGen = 0,
+ parameter int RegDw = 32, // Shall be matched with TL_DW
+ localparam int RegBw = RegDw/8
+) (
+ input clk_i,
+ input rst_ni,
+
+ // TL-UL interface
+ input tl_h2d_t tl_i,
+ output tl_d2h_t tl_o,
+
+ // Register interface
+ output logic re_o,
+ output logic we_o,
+ output logic [RegAw-1:0] addr_o,
+ output logic [RegDw-1:0] wdata_o,
+ output logic [RegBw-1:0] be_o,
+ input [RegDw-1:0] rdata_i,
+ input error_i
+);
+
+ localparam int IW = $bits(tl_i.a_source);
+ localparam int SZW = $bits(tl_i.a_size);
+
+ logic outstanding; // Indicates current request is pending
+ logic a_ack, d_ack;
+
+ logic [RegDw-1:0] rdata;
+ logic error, err_internal;
+
+ logic addr_align_err; // Size and alignment
+ logic malformed_meta_err; // User signal format error or unsupported
+ logic tl_err; // Common TL-UL error checker
+
+ logic [IW-1:0] reqid;
+ logic [SZW-1:0] reqsz;
+ tl_d_op_e rspop;
+
+ logic rd_req, wr_req;
+
+ assign a_ack = tl_i.a_valid & tl_o.a_ready;
+ assign d_ack = tl_o.d_valid & tl_i.d_ready;
+ // Request signal
+ assign wr_req = a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData));
+ assign rd_req = a_ack & (tl_i.a_opcode == Get);
+
+ assign we_o = wr_req & ~err_internal;
+ assign re_o = rd_req & ~err_internal;
+ assign addr_o = {tl_i.a_address[RegAw-1:2], 2'b00}; // generate always word-align
+ assign wdata_o = tl_i.a_data;
+ assign be_o = tl_i.a_mask;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) outstanding <= 1'b0;
+ else if (a_ack) outstanding <= 1'b1;
+ else if (d_ack) outstanding <= 1'b0;
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ reqid <= '0;
+ reqsz <= '0;
+ rspop <= AccessAck;
+ end else if (a_ack) begin
+ reqid <= tl_i.a_source;
+ reqsz <= tl_i.a_size;
+ // Return AccessAckData regardless of error
+ rspop <= (rd_req) ? AccessAckData : AccessAck ;
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ rdata <= '0;
+ error <= 1'b0;
+ end else if (a_ack) begin
+ rdata <= (err_internal) ? '1 : rdata_i;
+ error <= error_i | err_internal;
+ end
+ end
+
+ assign tl_o = '{
+ a_ready: ~outstanding,
+ d_valid: outstanding,
+ d_opcode: rspop,
+ d_param: '0,
+ d_size: reqsz,
+ d_source: reqid,
+ d_sink: '0,
+ d_data: rdata,
+ d_user: '0,
+ d_error: error
+ };
+
+ ////////////////////
+ // Error Handling //
+ ////////////////////
+ assign err_internal = addr_align_err | malformed_meta_err | tl_err ;
+
+ // malformed_meta_err
+ // Raised if not supported feature is turned on or user signal has malformed
+ //assign malformed_meta_err = (tl_i.a_user.parity_en == 1'b1);
+ assign malformed_meta_err = 1'b0;
+
+ // addr_align_err
+ // Raised if addr isn't aligned with the size
+ // Read size error is checked in tlul_assert.sv
+ // Here is it added due to the limitation of register interface.
+ always_comb begin
+ if (wr_req) begin
+ // Only word-align is accepted based on comportability spec
+ addr_align_err = |tl_i.a_address[1:0];
+ end else begin
+ // No request
+ addr_align_err = 1'b0;
+ end
+ end
+
+ // tl_err : separate checker
+ tlul_err u_err (
+ .clk_i,
+ .rst_ni,
+ .tl_i,
+ .err_o (tl_err)
+ );
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_adapter_sram.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_adapter_sram.sv
new file mode 100644
index 00000000..c4c338cc
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_adapter_sram.sv
@@ -0,0 +1,351 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Tile-Link UL adapter for SRAM-like devices
+ *
+ * - Intentionally omitted BaseAddr in case of multiple memory maps are used in a SoC,
+ * it means that aliasing can happen if target device size in TL-UL crossbar is bigger
+ * than SRAM size
+ */
+module tlul_adapter_sram #(
+ parameter int SramAw = 12,
+ parameter int SramDw = 32, // Must be multiple of the TL width
+ parameter int Outstanding = 1, // Only one request is accepted
+ parameter bit ByteAccess = 1, // 1: true, 0: false
+ parameter bit ErrOnWrite = 0, // 1: Writes not allowed, automatically error
+ parameter bit ErrOnRead = 0, // 1: Reads not allowed, automatically error
+ parameter int CmdIntgCheck =1,
+ parameter int EnableRspIntgGen = 1,
+ parameter int EnableDataIntgGen =1
+
+) (
+ input clk_i,
+ input rst_ni,
+
+ // TL-UL interface
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // SRAM interface
+ output logic req_o,
+ input gnt_i,
+ output logic we_o,
+ output logic [SramAw-1:0] addr_o,
+ output logic [SramDw-1:0] wdata_o,
+ output logic [SramDw-1:0] wmask_o,
+ input [SramDw-1:0] rdata_i,
+ input rvalid_i,
+ input [1:0] rerror_i // 2 bit error [1]: Uncorrectable, [0]: Correctable
+);
+
+ import tlul_pkg::*;
+
+ localparam int SramByte = SramDw/8;
+ localparam int DataBitWidth = prim_util_pkg::vbits(SramByte);
+ localparam int WidthMult = SramDw / top_pkg::TL_DW;
+ localparam int WoffsetWidth = (SramByte == top_pkg::TL_DBW) ? 1 :
+ DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW);
+
+ typedef struct packed {
+ logic [top_pkg::TL_DBW-1:0] mask ; // Byte mask within the TL-UL word
+ logic [WoffsetWidth-1:0] woffset ; // Offset of the TL-UL word within the SRAM word
+ } sram_req_t ;
+
+ typedef enum logic [1:0] {
+ OpWrite,
+ OpRead,
+ OpUnknown
+ } req_op_e ;
+
+ typedef struct packed {
+ req_op_e op ;
+ logic error ;
+ logic [top_pkg::TL_SZW-1:0] size ;
+ logic [top_pkg::TL_AIW-1:0] source ;
+ } req_t ;
+
+ typedef struct packed {
+ logic [SramDw-1:0] data ;
+ logic error ;
+ } rsp_t ;
+
+ localparam int SramReqFifoWidth = $bits(sram_req_t) ;
+ localparam int ReqFifoWidth = $bits(req_t) ;
+ localparam int RspFifoWidth = $bits(rsp_t) ;
+
+ // FIFO signal in case OutStand is greater than 1
+ // If request is latched, {write, source} is pushed to req fifo.
+ // Req fifo is popped when D channel is acknowledged (v & r)
+ // D channel valid is asserted if it is write request or rsp fifo not empty if read.
+ logic reqfifo_wvalid, reqfifo_wready;
+ logic reqfifo_rvalid, reqfifo_rready;
+ req_t reqfifo_wdata, reqfifo_rdata;
+
+ logic sramreqfifo_wvalid, sramreqfifo_wready;
+ logic sramreqfifo_rready;
+ sram_req_t sramreqfifo_wdata, sramreqfifo_rdata;
+
+ logic rspfifo_wvalid, rspfifo_wready;
+ logic rspfifo_rvalid, rspfifo_rready;
+ rsp_t rspfifo_wdata, rspfifo_rdata;
+
+ logic error_internal; // Internal protocol error checker
+ logic wr_attr_error;
+ logic wr_vld_error;
+ logic rd_vld_error;
+ logic tlul_error; // Error from `tlul_err` module
+
+ logic a_ack, d_ack, sram_ack;
+ assign a_ack = tl_i.a_valid & tl_o.a_ready ;
+ assign d_ack = tl_o.d_valid & tl_i.d_ready ;
+ assign sram_ack = req_o & gnt_i ;
+
+ // Valid handling
+ logic d_valid, d_error;
+ always_comb begin
+ d_valid = 1'b0;
+
+ if (reqfifo_rvalid) begin
+ if (reqfifo_rdata.error) begin
+ // Return error response. Assume no request went out to SRAM
+ d_valid = 1'b1;
+ end else if (reqfifo_rdata.op == OpRead) begin
+ d_valid = rspfifo_rvalid;
+ end else begin
+ // Write without error
+ d_valid = 1'b1;
+ end
+ end else begin
+ d_valid = 1'b0;
+ end
+ end
+
+ always_comb begin
+ d_error = 1'b0;
+
+ if (reqfifo_rvalid) begin
+ if (reqfifo_rdata.op == OpRead) begin
+ d_error = rspfifo_rdata.error | reqfifo_rdata.error;
+ end else begin
+ d_error = reqfifo_rdata.error;
+ end
+ end else begin
+ d_error = 1'b0;
+ end
+ end
+
+ assign tl_o = '{
+ d_valid : d_valid ,
+ d_opcode : (d_valid && reqfifo_rdata.op != OpRead) ? AccessAck : AccessAckData,
+ d_param : '0,
+ d_size : (d_valid) ? reqfifo_rdata.size : '0,
+ d_source : (d_valid) ? reqfifo_rdata.source : '0,
+ d_sink : 1'b0,
+ d_data : (d_valid && rspfifo_rvalid && reqfifo_rdata.op == OpRead)
+ ? rspfifo_rdata.data : '0,
+ d_user : '0,
+ d_error : d_valid && d_error,
+
+ a_ready : (gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready
+ };
+
+ // a_ready depends on the FIFO full condition and grant from SRAM (or SRAM arbiter)
+ // assemble response, including read response, write response, and error for unsupported stuff
+
+ // Output to SRAM:
+ // Generate request only when no internal error occurs. If error occurs, the request should be
+ // dropped and returned error response to the host. So, error to be pushed to reqfifo.
+ // In this case, it is assumed the request is granted (may cause ordering issue later?)
+ assign req_o = tl_i.a_valid & reqfifo_wready & ~error_internal;
+ assign we_o = tl_i.a_valid & logic'(tl_i.a_opcode inside {PutFullData, PutPartialData});
+ assign addr_o = (tl_i.a_valid) ? tl_i.a_address[DataBitWidth+:SramAw] : '0;
+
+ // Support SRAMs wider than the TL-UL word width by mapping the parts of the
+ // TL-UL address which are more fine-granular than the SRAM width to the
+ // SRAM write mask.
+ logic [WoffsetWidth-1:0] woffset;
+ if (top_pkg::TL_DW != SramDw) begin : gen_wordwidthadapt
+ assign woffset = tl_i.a_address[DataBitWidth-1:prim_util_pkg::vbits(top_pkg::TL_DBW)];
+ end else begin : gen_no_wordwidthadapt
+ assign woffset = '0;
+ end
+
+ // Convert byte mask to SRAM bit mask for writes, and only forward valid data
+ logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wmask_int;
+ logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wdata_int;
+
+ always_comb begin
+ wmask_int = '0;
+ wdata_int = '0;
+
+ if (tl_i.a_valid) begin
+ for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
+ wmask_int[woffset][8*i +: 8] = {8{tl_i.a_mask[i]}};
+ wdata_int[woffset][8*i +: 8] = (tl_i.a_mask[i] && we_o) ? tl_i.a_data[8*i+:8] : '0;
+ end
+ end
+ end
+
+ assign wmask_o = wmask_int;
+ assign wdata_o = wdata_int;
+
+ // Begin: Request Error Detection
+
+ // wr_attr_error: Check if the request size,mask are permitted.
+ // Basic check of size, mask, addr align is done in tlul_err module.
+ // Here it checks any partial write if ByteAccess isn't allowed.
+ assign wr_attr_error = (tl_i.a_opcode == PutFullData || tl_i.a_opcode == PutPartialData) ?
+ (ByteAccess == 0) ? (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0 :
+ 1'b0;
+
+ if (ErrOnWrite == 1) begin : gen_no_writes
+ assign wr_vld_error = tl_i.a_opcode != Get;
+ end else begin : gen_writes_allowed
+ assign wr_vld_error = 1'b0;
+ end
+
+ if (ErrOnRead == 1) begin: gen_no_reads
+ assign rd_vld_error = tl_i.a_opcode == Get;
+ end else begin : gen_reads_allowed
+ assign rd_vld_error = 1'b0;
+ end
+
+ tlul_err u_err (
+ .clk_i,
+ .rst_ni,
+ .tl_i,
+ .err_o (tlul_error)
+ );
+
+ assign error_internal = wr_attr_error | wr_vld_error | rd_vld_error | tlul_error;
+ // End: Request Error Detection
+
+ assign reqfifo_wvalid = a_ack ; // Push to FIFO only when granted
+ assign reqfifo_wdata = '{
+ op: (tl_i.a_opcode != Get) ? OpWrite : OpRead, // To return AccessAck for opcode error
+ error: error_internal,
+ size: tl_i.a_size,
+ source: tl_i.a_source
+ }; // Store the request only. Doesn't have to store data
+ assign reqfifo_rready = d_ack ;
+
+ // push together with ReqFIFO, pop upon returning read
+ assign sramreqfifo_wdata = '{
+ mask : tl_i.a_mask,
+ woffset : woffset
+ };
+ assign sramreqfifo_wvalid = sram_ack & ~we_o;
+ assign sramreqfifo_rready = rspfifo_wvalid;
+
+ assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid;
+
+ // Make sure only requested bytes are forwarded
+ logic [WidthMult-1:0][top_pkg::TL_DW-1:0] rdata;
+ logic [WidthMult-1:0][top_pkg::TL_DW-1:0] rmask;
+ //logic [SramDw-1:0] rmask;
+ logic [top_pkg::TL_DW-1:0] rdata_tlword;
+
+ always_comb begin
+ rmask = '0;
+ for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
+ rmask[sramreqfifo_rdata.woffset][8*i +: 8] = {8{sramreqfifo_rdata.mask[i]}};
+ end
+ end
+
+ assign rdata = rdata_i & rmask;
+ assign rdata_tlword = rdata[sramreqfifo_rdata.woffset];
+
+ assign rspfifo_wdata = '{
+ data : rdata_tlword,
+ error: rerror_i[1] // Only care for Uncorrectable error
+ };
+ assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error)
+ ? reqfifo_rready : 1'b0 ;
+
+ // This module only cares about uncorrectable errors.
+ logic unused_rerror;
+ assign unused_rerror = rerror_i[0];
+
+ // FIFO instance: REQ, RSP
+
+ // ReqFIFO is to store the Access type to match to the Response data.
+ // For instance, SRAM accepts the write request but doesn't return the
+ // acknowledge. In this case, it may be hard to determine when the D
+ // response for the write data should send out if reads/writes are
+ // interleaved. So, to make it in-order (even TL-UL allows out-of-order
+ // responses), storing the request is necessary. And if the read entry
+ // is write op, it is safe to return the response right away. If it is
+ // read reqeust, then D response is waiting until read data arrives.
+
+ // Notes:
+ // The oustanding+1 allows the reqfifo to absorb back to back transactions
+ // without any wait states. Alternatively, the depth can be kept as
+ // oustanding as long as the outgoing ready is qualified with the acceptance
+ // of the response in the same cycle. Doing so however creates a path from
+ // ready_i to ready_o, which may not be desireable.
+ prim_fifo_sync #(
+ .Width (ReqFifoWidth),
+ .Pass (1'b0),
+ .Depth (Outstanding)
+ ) u_reqfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0),
+ .wvalid(reqfifo_wvalid),
+ .wready(reqfifo_wready),
+ .wdata (reqfifo_wdata),
+ .depth (),
+ .rvalid(reqfifo_rvalid),
+ .rready(reqfifo_rready),
+ .rdata (reqfifo_rdata)
+ );
+
+ // sramreqfifo:
+ // While the ReqFIFO holds the request until it is sent back via TL-UL, the
+ // sramreqfifo only needs to hold the mask and word offset until the read
+ // data returns from memory.
+ prim_fifo_sync #(
+ .Width (SramReqFifoWidth),
+ .Pass (1'b0),
+ .Depth (Outstanding)
+ ) u_sramreqfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0),
+ .wvalid(sramreqfifo_wvalid),
+ .wready(sramreqfifo_wready),
+ .wdata (sramreqfifo_wdata),
+ .depth (),
+ .rvalid(),
+ .rready(sramreqfifo_rready),
+ .rdata (sramreqfifo_rdata)
+ );
+
+ // Rationale having #Outstanding depth in response FIFO.
+ // In normal case, if the host or the crossbar accepts the response data,
+ // response FIFO isn't needed. But if in any case it has a chance to be
+ // back pressured, the response FIFO should store the returned data not to
+ // lose the data from the SRAM interface. Remember, SRAM interface doesn't
+ // have back-pressure signal such as read_ready.
+ prim_fifo_sync #(
+ .Width (RspFifoWidth),
+ .Pass (1'b1),
+ .Depth (Outstanding)
+ ) u_rspfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0),
+ .wvalid(rspfifo_wvalid),
+ .wready(rspfifo_wready),
+ .wdata (rspfifo_wdata),
+ .depth (),
+ .rvalid(rspfifo_rvalid),
+ .rready(rspfifo_rready),
+ .rdata (rspfifo_rdata)
+ );
+
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_cmd_intg_chk.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_cmd_intg_chk.sv
new file mode 100644
index 00000000..a903e254
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_cmd_intg_chk.sv
@@ -0,0 +1,40 @@
+
+
+module tlul_cmd_intg_chk import tlul_pkg::*; (
+ // TL-UL interface
+ input tl_h2d_t tl_i,
+
+ // error output
+ output logic err_o
+);
+
+ logic [1:0] err;
+ logic data_err;
+ tl_h2d_cmd_intg_t cmd;
+ assign cmd = extract_h2d_cmd_intg(tl_i);
+
+ prim_secded_inv_64_57_dec u_chk (
+ .data_i({tl_i.a_user.cmd_intg, H2DCmdMaxWidth'(cmd)}),
+ .data_o(),
+ .syndrome_o(),
+ .err_o(err)
+ );
+
+ tlul_data_integ_dec u_tlul_data_integ_dec (
+ .data_intg_i({tl_i.a_user.data_intg, DataMaxWidth'(tl_i.a_data)}),
+ .data_err_o(data_err)
+ );
+
+ // error output is transactional, it is up to the instantiating module
+ // to determine if a permanent latch is feasible
+ logic wr_txn;
+ assign wr_txn = tl_i.a_valid &
+ (tl_i.a_opcode == PutFullData | tl_i.a_opcode == PutPartialData);
+
+ assign err_o = tl_i.a_valid & (|err | (|data_err));
+
+
+ logic unused_tl;
+ assign unused_tl = |tl_i;
+
+endmodule // tlul_payload_chk
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_data_integ_dec.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_data_integ_dec.sv
new file mode 100644
index 00000000..3db4312b
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_data_integ_dec.sv
@@ -0,0 +1,26 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Data integrity decoder for bus integrity scheme
+ */
+
+module tlul_data_integ_dec import tlul_pkg::*; (
+ // TL-UL interface
+ input [DataMaxWidth+DataIntgWidth-1:0] data_intg_i,
+ output logic data_err_o
+);
+
+ logic [1:0] data_err;
+ prim_secded_inv_39_32_dec u_data_chk (
+ .data_i(data_intg_i),
+ .data_o(),
+ .syndrome_o(),
+ .err_o(data_err)
+ );
+
+ assign data_err_o = |data_err;
+
+endmodule : tlul_data_integ_dec
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_data_integ_enc.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_data_integ_enc.sv
new file mode 100644
index 00000000..1ae5b521
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_data_integ_enc.sv
@@ -0,0 +1,21 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Data integrity encoder for bus integrity scheme
+ */
+
+module tlul_data_integ_enc import tlul_pkg::*; (
+ // TL-UL interface
+ input [DataMaxWidth-1:0] data_i,
+ output logic [DataMaxWidth+DataIntgWidth-1:0] data_intg_o
+);
+
+ prim_secded_inv_39_32_enc u_data_gen (
+ .data_i,
+ .data_o(data_intg_o)
+ );
+
+endmodule : tlul_data_integ_enc
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_err.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_err.sv
new file mode 100644
index 00000000..67fd8307
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_err.sv
@@ -0,0 +1,92 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+
+module tlul_err import tlul_pkg::*; (
+ input clk_i,
+ input rst_ni,
+
+ input tl_h2d_t tl_i,
+
+ output logic err_o
+);
+
+ localparam int IW = $bits(tl_i.a_source);
+ localparam int SZW = $bits(tl_i.a_size);
+ localparam int DW = $bits(tl_i.a_data);
+ localparam int MW = $bits(tl_i.a_mask);
+ localparam int SubAW = $clog2(DW/8);
+
+ logic opcode_allowed, a_config_allowed;
+
+ logic op_full, op_partial, op_get;
+ assign op_full = (tl_i.a_opcode == PutFullData);
+ assign op_partial = (tl_i.a_opcode == PutPartialData);
+ assign op_get = (tl_i.a_opcode == Get);
+
+ // Anything that doesn't fall into the permitted category, it raises an error
+ assign err_o = ~(opcode_allowed & a_config_allowed);
+
+ // opcode check
+ assign opcode_allowed = (tl_i.a_opcode == PutFullData)
+ | (tl_i.a_opcode == PutPartialData)
+ | (tl_i.a_opcode == Get);
+
+ // a channel configuration check
+ logic addr_sz_chk; // address and size alignment check
+ logic mask_chk; // inactive lane a_mask check
+ logic fulldata_chk; // PutFullData should have size match to mask
+
+ logic [MW-1:0] mask;
+
+ assign mask = (1 << tl_i.a_address[SubAW-1:0]);
+
+ always_comb begin
+ addr_sz_chk = 1'b0;
+ mask_chk = 1'b0;
+ fulldata_chk = 1'b0; // Only valid when opcode is PutFullData
+
+ if (tl_i.a_valid) begin
+ unique case (tl_i.a_size)
+ 'h0: begin // 1 Byte
+ addr_sz_chk = 1'b1;
+ mask_chk = ~|(tl_i.a_mask & ~mask);
+ fulldata_chk = |(tl_i.a_mask & mask);
+ end
+
+ 'h1: begin // 2 Byte
+ addr_sz_chk = ~tl_i.a_address[0];
+ // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0]
+ mask_chk = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011)
+ : ~|(tl_i.a_mask & 4'b1100);
+ fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ;
+ end
+
+ 'h2: begin // 4 Byte
+ addr_sz_chk = ~|tl_i.a_address[SubAW-1:0];
+ mask_chk = 1'b1;
+ fulldata_chk = &tl_i.a_mask[3:0];
+ end
+
+ default: begin // else
+ addr_sz_chk = 1'b0;
+ mask_chk = 1'b0;
+ fulldata_chk = 1'b0;
+ end
+ endcase
+ end else begin
+ addr_sz_chk = 1'b0;
+ mask_chk = 1'b0;
+ fulldata_chk = 1'b0;
+ end
+ end
+
+ assign a_config_allowed = addr_sz_chk
+ & mask_chk
+ & (op_get | op_partial | fulldata_chk) ;
+
+
+endmodule
+
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_err_resp.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_err_resp.sv
new file mode 100644
index 00000000..d05e70ae
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_err_resp.sv
@@ -0,0 +1,59 @@
+
+// TL-UL error responder module, used by tlul_socket_1n to help response
+// to requests to no correct address space. Responses are always one cycle
+// after request with no stalling unless response is stuck on the way out.
+//`include "/home/sajjad/Shaheen-sv/src/buraq_core_top/ibex_core/tlul_pkg.sv"
+module tlul_err_resp (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_h_i,
+ output tlul_pkg::tl_d2h_t tl_h_o
+);
+ import tlul_pkg::*;
+ localparam int TL_AIW=8; // a_source, d_source
+
+ //tlul_pkg::tl_a_m_op get;
+ logic [$bits(tl_h_i.a_source)-1:0] err_source;
+ logic [$bits(tl_h_i.a_size)-1:0] err_size;
+ logic err_req_pending, err_rsp_pending;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_req_pending <= 1'b0;
+ //err_source <= {tlul_pkg::TL_AIW{1'b0}};
+ //err_opcode <= tlul_pkg::Get;
+ err_size <= '0;
+ end else if (tl_h_i.a_valid && tl_h_o.a_ready) begin
+ err_req_pending <= 1'b1;
+ err_source <= tl_h_i.a_source;
+ //err_opcode <= tl_h_i.a_opcode;
+ err_size <= tl_h_i.a_size;
+ end else if (!err_rsp_pending) begin
+ err_req_pending <= 1'b0;
+ end
+ end
+
+ assign tl_h_o.a_ready = ~err_rsp_pending & ~(err_req_pending & ~tl_h_i.d_ready);
+ assign tl_h_o.d_valid = err_req_pending | err_rsp_pending;
+ assign tl_h_o.d_data = '1; // Return all F
+ assign tl_h_o.d_source = err_source;
+ assign tl_h_o.d_sink = '0;
+ assign tl_h_o.d_param = '0;
+ assign tl_h_o.d_user.rsp_intg = '0;
+ assign tl_h_o.d_user.data_intg = '0;
+ assign tl_h_o.d_size = err_size;
+ //assign tl_h_o.d_opcode = (err_opcode == tlul_pkg::Get) ? AccessAckData : AccessAck;
+ assign tl_h_o.d_opcode = AccessAck;
+ assign tl_h_o.d_error = 1'b1;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_rsp_pending <= 1'b0;
+ end else if ((err_req_pending || err_rsp_pending) && !tl_h_i.d_ready) begin
+ err_rsp_pending <= 1'b1;
+ end else begin
+ err_rsp_pending <= 1'b0;
+ end
+ end
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_fifo_sync.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_fifo_sync.sv
new file mode 100644
index 00000000..0cc3d8ec
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_fifo_sync.sv
@@ -0,0 +1,91 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// TL-UL fifo, used to add elasticity or an asynchronous clock crossing
+// to an TL-UL bus. This instantiates two FIFOs, one for the request side,
+// and one for the response side.
+
+module tlul_fifo_sync #(
+ parameter bit ReqPass = 1'b1,
+ parameter bit RspPass = 1'b1,
+ parameter int unsigned ReqDepth = 2,
+ parameter int unsigned RspDepth = 2,
+ parameter int unsigned SpareReqW = 1,
+ parameter int unsigned SpareRspW = 1
+) (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_h_i,
+ output tlul_pkg::tl_d2h_t tl_h_o,
+ output tlul_pkg::tl_h2d_t tl_d_o,
+ input tlul_pkg::tl_d2h_t tl_d_i,
+ input [SpareReqW-1:0] spare_req_i,
+ output [SpareReqW-1:0] spare_req_o,
+ input [SpareRspW-1:0] spare_rsp_i,
+ output [SpareRspW-1:0] spare_rsp_o
+);
+
+ // Put everything on the request side into one FIFO
+ localparam int unsigned REQFIFO_WIDTH = $bits(tlul_pkg::tl_h2d_t) -2 + SpareReqW;
+
+ prim_fifo_sync #(.Width(REQFIFO_WIDTH), .Pass(ReqPass), .Depth(ReqDepth)) reqfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0 ),
+ .wvalid (tl_h_i.a_valid),
+ .wready (tl_h_o.a_ready),
+ .wdata ({tl_h_i.a_opcode ,
+ tl_h_i.a_param ,
+ tl_h_i.a_size ,
+ tl_h_i.a_source ,
+ tl_h_i.a_address,
+ tl_h_i.a_mask ,
+ tl_h_i.a_data ,
+ tl_h_i.a_user ,
+ spare_req_i}),
+ .rvalid (tl_d_o.a_valid),
+ .rready (tl_d_i.a_ready),
+ .rdata ({tl_d_o.a_opcode ,
+ tl_d_o.a_param ,
+ tl_d_o.a_size ,
+ tl_d_o.a_source ,
+ tl_d_o.a_address,
+ tl_d_o.a_mask ,
+ tl_d_o.a_data ,
+ tl_d_o.a_user ,
+ spare_req_o}));
+
+ // Put everything on the response side into the other FIFO
+
+ localparam int unsigned RSPFIFO_WIDTH = $bits(tlul_pkg::tl_d2h_t) -2 + SpareRspW;
+
+ prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0 ),
+ .wvalid (tl_d_i.d_valid),
+ .wready (tl_d_o.d_ready),
+ .wdata ({tl_d_i.d_opcode,
+ tl_d_i.d_param ,
+ tl_d_i.d_size ,
+ tl_d_i.d_source,
+ tl_d_i.d_sink ,
+ (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
+ {top_pkg::TL_DW{1'b0}} ,
+ tl_d_i.d_user ,
+ tl_d_i.d_error ,
+ spare_rsp_i}),
+ .rvalid (tl_h_o.d_valid),
+ .rready (tl_h_i.d_ready),
+ .rdata ({tl_h_o.d_opcode,
+ tl_h_o.d_param ,
+ tl_h_o.d_size ,
+ tl_h_o.d_source,
+ tl_h_o.d_sink ,
+ tl_h_o.d_data ,
+ tl_h_o.d_user ,
+ tl_h_o.d_error ,
+ spare_rsp_o}));
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_pkg.sv
new file mode 100644
index 00000000..81feee0c
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_pkg.sv
@@ -0,0 +1,174 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package tlul_pkg;
+
+ // this can be either PPC or BINTREE
+ // there is no functional difference, but timing and area behavior is different
+ // between the two instances. PPC can result in smaller implementations when timing
+ // is not critical, whereas BINTREE is favorable when timing pressure is high (but this
+ // may also result in a larger implementation). on FPGA targets, BINTREE is favorable
+ // both in terms of area and timing.
+ parameter ArbiterImpl = "PPC";
+
+ typedef enum logic [2:0] {
+ PutFullData = 3'h0,
+ PutPartialData = 3'h1,
+ Get = 3'h4
+ } tl_a_op_e;
+
+ typedef enum logic [2:0] {
+ AccessAck = 3'h0,
+ AccessAckData = 3'h1
+ } tl_d_op_e;
+
+ parameter int H2DCmdMaxWidth = 57;
+ parameter int H2DCmdIntgWidth = 7;
+ parameter int H2DCmdFullWidth = H2DCmdMaxWidth + H2DCmdIntgWidth;
+ parameter int D2HRspMaxWidth = 57;
+ parameter int D2HRspIntgWidth = 7;
+ parameter int D2HRspFullWidth = D2HRspMaxWidth + D2HRspIntgWidth;
+ parameter int DataMaxWidth = 32;
+ parameter int DataIntgWidth = 7;
+ parameter int DataFullWidth = DataMaxWidth + DataIntgWidth;
+
+ typedef struct packed {
+ logic [4:0] rsvd;
+ prim_mubi_pkg::mubi4_t instr_type;
+ logic [H2DCmdIntgWidth-1:0] cmd_intg;
+ logic [DataIntgWidth-1:0] data_intg;
+ } tl_a_user_t;
+
+ parameter tl_a_user_t TL_A_USER_DEFAULT = '{
+ rsvd: '0,
+ instr_type: prim_mubi_pkg::MuBi4False,
+ cmd_intg: {H2DCmdIntgWidth{1'b1}},
+ data_intg: {DataIntgWidth{1'b1}}
+ };
+
+ typedef struct packed {
+ prim_mubi_pkg::mubi4_t instr_type;
+ logic [top_pkg::TL_AW-1:0] addr;
+ tl_a_op_e opcode;
+ logic [top_pkg::TL_DBW-1:0] mask;
+ } tl_h2d_cmd_intg_t;
+
+ typedef struct packed {
+ logic a_valid;
+ tl_a_op_e a_opcode;
+ logic [2:0] a_param;
+ logic [top_pkg::TL_SZW-1:0] a_size;
+ logic [top_pkg::TL_AIW-1:0] a_source;
+ logic [top_pkg::TL_AW-1:0] a_address;
+ logic [top_pkg::TL_DBW-1:0] a_mask;
+ logic [top_pkg::TL_DW-1:0] a_data;
+ tl_a_user_t a_user;
+
+ logic d_ready;
+ } tl_h2d_t;
+
+ localparam tl_h2d_t TL_H2D_DEFAULT = '{
+ d_ready: 1'b1,
+ a_opcode: tl_a_op_e'('0),
+ a_user: TL_A_USER_DEFAULT,
+ default: '0
+ };
+
+ typedef struct packed {
+ logic [D2HRspIntgWidth-1:0] rsp_intg;
+ logic [DataIntgWidth-1:0] data_intg;
+ } tl_d_user_t;
+
+ parameter tl_d_user_t TL_D_USER_DEFAULT = '{
+ rsp_intg: {D2HRspIntgWidth{1'b1}},
+ data_intg: {DataIntgWidth{1'b1}}
+ };
+
+ typedef struct packed {
+ logic d_valid;
+ tl_d_op_e d_opcode;
+ logic [2:0] d_param;
+ logic [top_pkg::TL_SZW-1:0] d_size; // Bouncing back a_size
+ logic [top_pkg::TL_AIW-1:0] d_source;
+ logic [top_pkg::TL_DIW-1:0] d_sink;
+ logic [top_pkg::TL_DW-1:0] d_data;
+ tl_d_user_t d_user;
+ logic d_error;
+
+ logic a_ready;
+
+ } tl_d2h_t;
+
+ typedef struct packed {
+ tl_d_op_e opcode;
+ logic [top_pkg::TL_SZW-1:0] size;
+ // Temporarily removed because source changes throughout the fabric
+ // and thus cannot be used for end-to-end checking.
+ // A different PR will propose a work-around (a hoaky one) to see if
+ // it gets the job done.
+ //logic [top_pkg::TL_AIW-1:0] source;
+ logic error;
+ } tl_d2h_rsp_intg_t;
+
+ localparam tl_d2h_t TL_D2H_DEFAULT = '{
+ a_ready: 1'b1,
+ d_opcode: tl_d_op_e'('0),
+ d_user: TL_D_USER_DEFAULT,
+ default: '0
+ };
+
+ // Check user for unsupported values
+ function automatic logic tl_a_user_chk(tl_a_user_t user);
+ logic malformed_err;
+ logic unused_user;
+ unused_user = |user;
+ malformed_err = prim_mubi_pkg::mubi4_test_invalid(user.instr_type);
+ return malformed_err;
+ endfunction // tl_a_user_chk
+
+ // extract variables used for command checking
+ function automatic tl_h2d_cmd_intg_t extract_h2d_cmd_intg(tl_h2d_t tl);
+ tl_h2d_cmd_intg_t payload;
+ logic unused_tlul;
+ unused_tlul = ^tl;
+ payload.addr = tl.a_address;
+ payload.opcode = tl.a_opcode;
+ payload.mask = tl.a_mask;
+ payload.instr_type = tl.a_user.instr_type;
+ return payload;
+ endfunction // extract_h2d_payload
+
+ // extract variables used for response checking
+ function automatic tl_d2h_rsp_intg_t extract_d2h_rsp_intg(tl_d2h_t tl);
+ tl_d2h_rsp_intg_t payload;
+ logic unused_tlul;
+ unused_tlul = ^tl;
+ payload.opcode = tl.d_opcode;
+ payload.size = tl.d_size;
+ //payload.source = tl.d_source;
+ payload.error = tl.d_error;
+ return payload;
+ endfunction // extract_d2h_rsp_intg
+
+ // calculate ecc for command checking
+ function automatic logic [H2DCmdIntgWidth-1:0] get_cmd_intg(tl_h2d_t tl);
+ logic [H2DCmdIntgWidth-1:0] cmd_intg;
+ logic [H2DCmdMaxWidth-1:0] unused_cmd_payload;
+ tl_h2d_cmd_intg_t cmd;
+ cmd = extract_h2d_cmd_intg(tl);
+ {cmd_intg, unused_cmd_payload} =
+ prim_secded_pkg::prim_secded_inv_64_57_enc(H2DCmdMaxWidth'(cmd));
+ return cmd_intg;
+ endfunction // get_cmd_intg
+
+ // calculate ecc for data checking
+ function automatic logic [DataIntgWidth-1:0] get_data_intg(logic [top_pkg::TL_DW-1:0] data);
+ logic [DataIntgWidth-1:0] data_intg;
+ logic [top_pkg::TL_DW-1:0] unused_data;
+ {data_intg, unused_data} = prim_secded_pkg::prim_secded_inv_39_32_enc(data);
+ return data_intg;
+ endfunction // get_data_intg
+
+endpackage
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_rsp_intg_gen.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_rsp_intg_gen.sv
new file mode 100644
index 00000000..fbcedebb
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_rsp_intg_gen.sv
@@ -0,0 +1,54 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+/**
+ * Tile-Link UL response integrity generator
+ */
+
+module tlul_rsp_intg_gen import tlul_pkg::*; #(
+ parameter bit EnableRspIntgGen = 1'b1,
+ parameter bit EnableDataIntgGen = 1'b1
+) (
+ // TL-UL interface
+ input tl_d2h_t tl_i,
+ output tl_d2h_t tl_o
+);
+
+ logic [D2HRspIntgWidth-1:0] rsp_intg;
+ if (EnableRspIntgGen) begin : gen_rsp_intg
+ tl_d2h_rsp_intg_t rsp;
+ logic [D2HRspMaxWidth-1:0] unused_payload;
+
+ assign rsp = extract_d2h_rsp_intg(tl_i);
+
+ prim_secded_inv_64_57_enc u_rsp_gen (
+ .data_i(D2HRspMaxWidth'(rsp)),
+ .data_o({rsp_intg, unused_payload})
+ );
+ end else begin : gen_passthrough_rsp_intg
+ assign rsp_intg = tl_i.d_user.rsp_intg;
+ end
+
+ logic [DataIntgWidth-1:0] data_intg;
+ if (EnableDataIntgGen) begin : gen_data_intg
+ logic [DataMaxWidth-1:0] unused_data;
+ tlul_data_integ_enc u_tlul_data_integ_enc (
+ .data_i(DataMaxWidth'(tl_i.d_data)),
+ .data_intg_o({data_intg, unused_data})
+ );
+ end else begin : gen_passthrough_data_intg
+ assign data_intg = tl_i.d_user.data_intg;
+ end
+
+ always_comb begin
+ tl_o = tl_i;
+ tl_o.d_user.rsp_intg = rsp_intg;
+ tl_o.d_user.data_intg = data_intg;
+ end
+
+ logic unused_tl;
+ assign unused_tl = ^tl_i;
+
+
+endmodule // tlul_rsp_intg_gen
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_socket_1n.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_socket_1n.sv
new file mode 100644
index 00000000..fd96a64e
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/tlul_socket_1n.sv
@@ -0,0 +1,213 @@
+
+// TL-UL socket 1:N module
+//
+// configuration settings
+// device_count: 4
+//
+// Verilog parameters
+// HReqPass: if 1 then host requests can pass through on empty fifo,
+// default 1
+// HRspPass: if 1 then host responses can pass through on empty fifo,
+// default 1
+// DReqPass: (one per device_count) if 1 then device i requests can
+// pass through on empty fifo, default 1
+// DRspPass: (one per device_count) if 1 then device i responses can
+// pass through on empty fifo, default 1
+// HReqDepth: Depth of host request FIFO, default 2
+// HRspDepth: Depth of host response FIFO, default 2
+// DReqDepth: (one per device_count) Depth of device i request FIFO,
+// default 2
+// DRspDepth: (one per device_count) Depth of device i response FIFO,
+// default 2
+//
+// Requests must stall to one device until all responses from other devices
+// have returned. Need to keep a counter of all outstanding requests and
+// wait until that counter is zero before switching devices.
+//
+// This module will return a request error if the input value of 'dev_select_i'
+// is not within the range 0..N-1. Thus the instantiator of the socket
+// can indicate error by any illegal value of dev_select_i. 4'b1111 is
+// recommended for visibility
+//
+// The maximum value of N is 15
+
+
+module tlul_socket_1n #(
+ parameter int unsigned N = 4,
+ parameter bit HReqPass = 1'b1,
+ parameter bit HRspPass = 1'b1,
+ parameter bit [N-1:0] DReqPass = {N{1'b1}},
+ parameter bit [N-1:0] DRspPass = {N{1'b1}},
+ parameter bit [3:0] HReqDepth = 4'h2,
+ parameter bit [3:0] HRspDepth = 4'h2,
+ parameter bit [N*4-1:0] DReqDepth = {N{4'h2}},
+ parameter bit [N*4-1:0] DRspDepth = {N{4'h2}},
+ localparam int unsigned NWD = $clog2(N+1) // derived parameter
+) (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_h_i,
+ output tlul_pkg::tl_d2h_t tl_h_o,
+ output tlul_pkg::tl_h2d_t tl_d_o [N],
+ input tlul_pkg::tl_d2h_t tl_d_i [N],
+ input [NWD-1:0] dev_select_i
+);
+
+ // Since our steering is done after potential FIFOing, we need to
+ // shove our device select bits into spare bits of reqfifo
+
+ // instantiate the host fifo, create intermediate bus 't'
+
+ // FIFO'd version of device select
+ logic [NWD-1:0] dev_select_t;
+
+ tlul_pkg::tl_h2d_t tl_t_o;
+ tlul_pkg::tl_d2h_t tl_t_i;
+
+ tlul_fifo_sync #(
+ .ReqPass(HReqPass),
+ .RspPass(HRspPass),
+ .ReqDepth(HReqDepth),
+ .RspDepth(HRspDepth),
+ .SpareReqW(NWD)
+ ) fifo_h (
+ .clk_i,
+ .rst_ni,
+ .tl_h_i,
+ .tl_h_o,
+ .tl_d_o (tl_t_o),
+ .tl_d_i (tl_t_i),
+ .spare_req_i (dev_select_i),
+ .spare_req_o (dev_select_t),
+ .spare_rsp_i (1'b0),
+ .spare_rsp_o ());
+
+
+ // We need to keep track of how many requests are outstanding,
+ // and to which device. New requests are compared to this and
+ // stall until that number is zero.
+ // Up to 256 ounstanding
+ localparam int MaxOutstanding = 256;
+ localparam int OutstandingW = $clog2(MaxOutstanding+1);
+ logic [OutstandingW-1:0] num_req_outstanding;
+ logic [NWD-1:0] dev_select_outstanding;
+ logic hold_all_requests;
+ logic accept_t_req, accept_t_rsp;
+
+ assign accept_t_req = tl_t_o.a_valid & tl_t_i.a_ready;
+ assign accept_t_rsp = tl_t_i.d_valid & tl_t_o.d_ready;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ num_req_outstanding <= '0;
+ dev_select_outstanding <= '0;
+ end else if (accept_t_req) begin
+ if (!accept_t_rsp) begin
+ num_req_outstanding <= num_req_outstanding + 1'b1;
+ end
+ dev_select_outstanding <= dev_select_t;
+ end else if (accept_t_rsp) begin
+ num_req_outstanding <= num_req_outstanding - 1'b1;
+ end
+ end
+
+ assign hold_all_requests =
+ (num_req_outstanding != '0) &
+ (dev_select_t != dev_select_outstanding);
+
+ // Make N copies of 't' request side with modified reqvalid, call
+ // them 'u[0]' .. 'u[n-1]'.
+
+ tlul_pkg::tl_h2d_t tl_u_o [N+1];
+ tlul_pkg::tl_d2h_t tl_u_i [N+1];
+
+ for (genvar i = 0 ; i < N ; i++) begin : gen_u_o
+ assign tl_u_o[i].a_valid = tl_t_o.a_valid &
+ (dev_select_t == NWD'(i)) &
+ ~hold_all_requests;
+ assign tl_u_o[i].a_opcode = tl_t_o.a_opcode;
+ assign tl_u_o[i].a_param = tl_t_o.a_param;
+ assign tl_u_o[i].a_size = tl_t_o.a_size;
+ assign tl_u_o[i].a_source = tl_t_o.a_source;
+ assign tl_u_o[i].a_address = tl_t_o.a_address;
+ assign tl_u_o[i].a_mask = tl_t_o.a_mask;
+ assign tl_u_o[i].a_data = tl_t_o.a_data;
+ assign tl_u_o[i].a_user = tl_t_o.a_user;
+ end
+
+ tlul_pkg::tl_d2h_t tl_t_p ;
+
+ // for the returning reqready, only look at the device we're addressing
+ logic hfifo_reqready;
+ always_comb begin
+ hfifo_reqready = tl_u_i[N].a_ready; // default to error
+ for (int idx = 0 ; idx < N ; idx++) begin
+ //if (dev_select_outstanding == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready;
+ if (dev_select_t == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready;
+ end
+ if (hold_all_requests) hfifo_reqready = 1'b0;
+ end
+ // Adding a_valid as a qualifier. This prevents the a_ready from having unknown value
+ // when the address is unknown and the Host TL-UL FIFO is bypass mode.
+ assign tl_t_i.a_ready = tl_t_o.a_valid & hfifo_reqready;
+
+ always_comb begin
+ tl_t_p = tl_u_i[N];
+ for (int idx = 0 ; idx < N ; idx++) begin
+ if (dev_select_outstanding == NWD'(idx)) tl_t_p = tl_u_i[idx];
+ end
+ end
+ assign tl_t_i.d_valid = tl_t_p.d_valid ;
+ assign tl_t_i.d_opcode = tl_t_p.d_opcode;
+ assign tl_t_i.d_param = tl_t_p.d_param ;
+ assign tl_t_i.d_size = tl_t_p.d_size ;
+ assign tl_t_i.d_source = tl_t_p.d_source;
+ assign tl_t_i.d_sink = tl_t_p.d_sink ;
+ assign tl_t_i.d_data = tl_t_p.d_data ;
+ assign tl_t_i.d_error = tl_t_p.d_error ;
+ assign tl_t_i.d_user = '0;
+
+
+ // accept responses from devices when selected if upstream is accepting
+ for (genvar i = 0 ; i < N+1 ; i++) begin : gen_u_o_d_ready
+ assign tl_u_o[i].d_ready = tl_t_o.d_ready;
+ end
+
+ // finally instantiate all device FIFOs and the error responder
+ for (genvar i = 0 ; i < N ; i++) begin : gen_dfifo
+ tlul_fifo_sync #(
+ .ReqPass(DReqPass[i]),
+ .RspPass(DRspPass[i]),
+ .ReqDepth(DReqDepth[i*4+:4]),
+ .RspDepth(DRspDepth[i*4+:4])
+ ) fifo_d (
+ .clk_i,
+ .rst_ni,
+ .tl_h_i (tl_u_o[i]),
+ .tl_h_o (tl_u_i[i]),
+ .tl_d_o (tl_d_o[i]),
+ .tl_d_i (tl_d_i[i]),
+ .spare_req_i (1'b0),
+ .spare_req_o (),
+ .spare_rsp_i (1'b0),
+ .spare_rsp_o ());
+ end
+
+ assign tl_u_o[N].a_valid = tl_t_o.a_valid &
+ (dev_select_t == NWD'(N)) &
+ ~hold_all_requests;
+ assign tl_u_o[N].a_opcode = tl_t_o.a_opcode;
+ assign tl_u_o[N].a_param = tl_t_o.a_param;
+ assign tl_u_o[N].a_size = tl_t_o.a_size;
+ assign tl_u_o[N].a_source = tl_t_o.a_source;
+ assign tl_u_o[N].a_address = tl_t_o.a_address;
+ assign tl_u_o[N].a_mask = tl_t_o.a_mask;
+ assign tl_u_o[N].a_data = tl_t_o.a_data;
+ assign tl_u_o[N].a_user = tl_t_o.a_user;
+ tlul_err_resp err_resp (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .tl_h_i (tl_u_o[N]),
+ .tl_h_o (tl_u_i[N]));
+
+endmodule
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/top_pkg.sv b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/top_pkg.sv
new file mode 100644
index 00000000..3d62c73d
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/lib/work/rtl/top_pkg.sv
@@ -0,0 +1,17 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package top_pkg;
+
+localparam int TL_AW=32;
+localparam int TL_DW=32; // = TL_DBW * 8; TL_DBW must be a power-of-two
+localparam int TL_AIW=8; // a_source, d_source
+localparam int TL_DIW=1; // d_sink
+localparam int TL_AUW=21; // a_user
+localparam int TL_DUW=14; // d_user
+localparam int TL_DBW=(TL_DW>>3);
+localparam int TL_SZW=$clog2($clog2(TL_DBW)+1);
+
+endpackage
diff --git a/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/surelog.log b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/surelog.log
new file mode 100644
index 00000000..f471fc97
--- /dev/null
+++ b/EDA-3283/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/surelog.log
@@ -0,0 +1,207 @@
+********************************************
+* SURELOG SystemVerilog Compiler/Linter *
+********************************************
+
+Copyright (c) 2017-2023 Alain Dargelas,
+http://www.apache.org/licenses/LICENSE-2.0
+
+VERSION: 1.84
+BUILT : Oct 1 2024
+DATE : 2024-10-02.01:41:06
+COMMAND: -synth -top hmac -y ../../../../.././rtl/ -I../../../../.././rtl/ -I../../../../.. -I/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl +libext+.v+.sv -sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_util_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/pwrmgr_reg_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/pwrmgr_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_ram_1p_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_mubi_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_cipher_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_alert_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_count_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/jtag_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/entropy_src_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/edn_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/top_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_ctrl_reg_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_ctrl_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_phy_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_reg_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/lc_ctrl_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/otp_ctrl_reg_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/otp_ctrl_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/ast_pkg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_core.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_reg_top.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_alert_sender.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_buf.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_diff_decode.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_fifo_sync.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_flop_2sync.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_buf.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_flop.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_flop_2sync.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_intr_hw.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_packer.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_39_32_dec.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_39_32_enc.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_64_57_dec.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_64_57_enc.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg_ext.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/sha2.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/sha2_pad.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_adapter_reg.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_adapter_sram.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_cmd_intg_chk.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_data_integ_dec.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_data_integ_enc.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_err.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_err_resp.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_fifo_sync.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_rsp_intg_gen.sv /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_socket_1n.sv /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -DYOSYS=1 -DSYNTHESIS=1
+
+[INF:CM0023] Creating log file "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/surelog.log".
+[INF:CP0300] Compilation...
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_pkg.sv:8:1: Compile package "prim_secded_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg_pkg.sv:5:1: Compile package "prim_subreg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_util_pkg.sv:9:1: Compile package "prim_util_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/pwrmgr_reg_pkg.sv:7:1: Compile package "pwrmgr_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/pwrmgr_pkg.sv:8:1: Compile package "pwrmgr_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_ram_1p_pkg.sv:6:1: Compile package "prim_ram_1p_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:13:1: Compile package "prim_mubi_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_pkg.sv:11:1: Compile package "prim_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:17:1: Compile package "prim_cipher_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_pkg.sv:5:1: Compile package "prim_alert_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_count_pkg.sv:8:1: Compile package "prim_count_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/jtag_pkg.sv:6:1: Compile package "jtag_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/entropy_src_pkg.sv:7:1: Compile package "entropy_src_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/edn_pkg.sv:7:1: Compile package "edn_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/top_pkg.sv:6:1: Compile package "top_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_ctrl_reg_pkg.sv:7:1: Compile package "flash_ctrl_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_ctrl_pkg.sv:8:1: Compile package "flash_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_phy_pkg.sv:8:1: Compile package "flash_phy_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_pkg.sv:7:1: Compile package "hmac_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:6:1: Compile package "hmac_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/lc_ctrl_pkg.sv:6:1: Compile package "lc_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/otp_ctrl_reg_pkg.sv:7:1: Compile package "otp_ctrl_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/otp_ctrl_pkg.sv:6:1: Compile package "otp_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:6:1: Compile package "tlul_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/ast_pkg.sv:12:1: Compile package "ast_pkg".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:8:1: Compile module "work@BOOT_CLOCK".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:23:1: Compile module "work@CARRY".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:40:1: Compile module "work@CLK_BUF".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:55:1: Compile module "work@DFFNRE".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:73:1: Compile module "work@DFFRE".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:91:1: Compile module "work@DSP19X2".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:135:1: Compile module "work@DSP38".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:171:1: Compile module "work@FCLK_BUF".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:185:1: Compile module "work@FIFO18KX2".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:242:1: Compile module "work@FIFO36K".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:299:1: Compile module "work@I_BUF".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:277:1: Compile module "work@I_BUF_DS".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:318:1: Compile module "work@I_DDR".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:336:1: Compile module "work@I_DELAY".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:358:1: Compile module "work@I_FAB".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:372:1: Compile module "work@I_SERDES".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:480:1: Compile module "work@LATCH".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:433:1: Compile module "work@LATCHN".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:401:1: Compile module "work@LATCHNR".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:417:1: Compile module "work@LATCHNS".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:448:1: Compile module "work@LATCHR".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:464:1: Compile module "work@LATCHS".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:495:1: Compile module "work@LUT1".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:511:1: Compile module "work@LUT2".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:527:1: Compile module "work@LUT3".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:543:1: Compile module "work@LUT4".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:559:1: Compile module "work@LUT5".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:575:1: Compile module "work@LUT6".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:591:1: Compile module "work@MIPI_RX".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:627:1: Compile module "work@MIPI_TX".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:729:1: Compile module "work@O_BUF".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:708:1: Compile module "work@O_BUFT".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:686:1: Compile module "work@O_BUFT_DS".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:664:1: Compile module "work@O_BUF_DS".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:750:1: Compile module "work@O_DDR".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:768:1: Compile module "work@O_DELAY".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:790:1: Compile module "work@O_FAB".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:823:1: Compile module "work@O_SERDES".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:804:1: Compile module "work@O_SERDES_CLK".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:850:1: Compile module "work@PLL".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:878:1: Compile module "work@SOC_FPGA_INTF_AHB_M".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:902:1: Compile module "work@SOC_FPGA_INTF_AHB_S".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:929:1: Compile module "work@SOC_FPGA_INTF_AXI_M0".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:978:1: Compile module "work@SOC_FPGA_INTF_AXI_M1".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1027:1: Compile module "work@SOC_FPGA_INTF_DMA".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1043:1: Compile module "work@SOC_FPGA_INTF_IRQ".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1059:1: Compile module "work@SOC_FPGA_INTF_JTAG".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1077:1: Compile module "work@SOC_FPGA_TEMPERATURE".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1095:1: Compile module "work@TDP_RAM18KX2".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1160:1: Compile module "work@TDP_RAM36K".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:9:1: Compile module "work@hmac".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:7:1: Compile module "work@hmac_core".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:8:1: Compile module "work@hmac_reg_top".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:32:1: Compile module "work@prim_alert_sender".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:16:1: Compile module "work@prim_buf".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:19:1: Compile module "work@prim_diff_decode".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:6:1: Compile module "work@prim_fifo_sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:13:1: Compile module "work@prim_flop_2sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_buf.sv:6:1: Compile module "work@prim_generic_buf".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:7:1: Compile module "work@prim_generic_flop".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop_2sync.sv:9:1: Compile module "work@prim_generic_flop_2sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:10:1: Compile module "work@prim_intr_hw".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:8:1: Compile module "work@prim_packer".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:7:1: Compile module "work@prim_secded_inv_39_32_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_enc.sv:7:1: Compile module "work@prim_secded_inv_39_32_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:7:1: Compile module "work@prim_secded_inv_64_57_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_enc.sv:7:1: Compile module "work@prim_secded_inv_64_57_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:7:1: Compile module "work@prim_subreg".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg_ext.sv:7:1: Compile module "work@prim_subreg_ext".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:8:1: Compile module "work@sha2".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:9:1: Compile module "work@sha2_pad".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:10:1: Compile module "work@tlul_adapter_reg".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:13:1: Compile module "work@tlul_adapter_sram".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:3:1: Compile module "work@tlul_cmd_intg_chk".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_data_integ_dec.sv:10:1: Compile module "work@tlul_data_integ_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_data_integ_enc.sv:10:1: Compile module "work@tlul_data_integ_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:7:1: Compile module "work@tlul_err".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:6:1: Compile module "work@tlul_err_resp".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:9:1: Compile module "work@tlul_fifo_sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:9:1: Compile module "work@tlul_rsp_intg_gen".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:35:1: Compile module "work@tlul_socket_1n".
+[INF:CP0302] Compile class "work@mailbox".
+[INF:CP0302] Compile class "work@process".
+[INF:CP0302] Compile class "work@semaphore".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:41:17: Implicit port type (wire) for "sha_message_length".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:21:27: Implicit port type (wire) for "wready",
+there are 3 more instances of this message.
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:24:23: Implicit port type (wire) for "hw2reg_intr_state_de_o",
+there are 1 more instances of this message.
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:19:27: Implicit port type (wire) for "ready_o".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:24:29: Implicit port type (wire) for "spare_req_o",
+there are 1 more instances of this message.
+[INF:EL0526] Design Elaboration...
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[2]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[3]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[4]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[5]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[6]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[7]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_hmac_done.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_fifo_empty.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_hmac_err.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:122:14: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_depth_gt1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:132:23: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_pass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:172:12: Compile generate block "work@hmac.u_tlul_adapter.gen_no_wordwidthadapt".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:206:12: Compile generate block "work@hmac.u_tlul_adapter.gen_writes_allowed".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:210:23: Compile generate block "work@hmac.u_tlul_adapter.gen_no_reads".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:135:14: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_nopass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:135:14: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_nopass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:132:23: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_pass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:19:25: Compile generate block "work@hmac.u_reg.u_rsp_intg_gen.gen_rsp_intg".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:34:26: Compile generate block "work@hmac.u_reg.u_rsp_intg_gen.gen_data_intg".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:124:36: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:124:36: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[2]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:177:36: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:177:36: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_hmac_done.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_fifo_empty.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_hmac_err.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_hmac_done.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_fifo_empty.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_hmac_err.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_err_code.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_msg_length_lower.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_msg_length_upper.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:460:42: Compile generate block "work@hmac.gen_alert_tx[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:44:16: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_n.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:44:16: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_n.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:30:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:30:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_n.gen_generic".
+[NTE:EL0503] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:9:1: Top level module "work@hmac".
+[NTE:EL0508] Nb Top level modules: 1.
+[NTE:EL0509] Max instance depth: 9.
+[NTE:EL0510] Nb instances: 98.
+[NTE:EL0511] Nb leaf instances: 32.
+[INF:UH0706] Creating UHDM Model...
+[INF:UH0707] Elaborating UHDM...
+[ FATAL] : 0
+[ SYNTAX] : 0
+[ ERROR] : 0
+[WARNING] : 0
+[ NOTE] : 10
diff --git a/EDA-3283/results_dir/raptor.log b/EDA-3283/results_dir/raptor.log
new file mode 100644
index 00000000..431c6b35
--- /dev/null
+++ b/EDA-3283/results_dir/raptor.log
@@ -0,0 +1,5208 @@
+/*******************************************************************************
+Copyright (c) 2022-2024 Rapid Silicon
+This source code contains proprietary information belonging to Rapid Silicon
+(the "licensor") released under license and non-disclosure agreement to the
+recipient (the "licensee").
+
+The information shared and protected by the license and non-disclosure agreement
+includes but is not limited to the following:
+* operational algorithms of the product
+* logos, graphics, source code, and visual presentation of the product
+* confidential operational information of the licensor
+
+The recipient of this source code is NOT permitted to publicly disclose,
+re-use, archive beyond the period of the license agreement, transfer to a
+sub-licensee, or re-implement any portion of the content covered by the license
+and non-disclosure agreement without the prior written consent of the licensor.
+*********************************************************************************/
+
+Version : 2024.10
+Build : 1.2.12
+Hash : 6f00985
+Date : Oct 1 2024
+Type : Engineering
+Log Time : Tue Oct 1 20:40:37 2024 GMT
+
+INFO: Created design: hmac. Project type: rtl
+INFO: Target device: 1VG28
+INFO: Device version: v1.6.244
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_util_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/pwrmgr_reg_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/pwrmgr_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_ram_1p_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_mubi_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_cipher_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_alert_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_count_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/jtag_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/entropy_src_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/edn_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/top_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_ctrl_reg_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_ctrl_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/flash_phy_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_reg_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/lc_ctrl_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/otp_ctrl_reg_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/otp_ctrl_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/ast_pkg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_core.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/hmac_reg_top.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_alert_sender.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_buf.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_diff_decode.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_fifo_sync.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_flop_2sync.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_buf.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_flop.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_generic_flop_2sync.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_intr_hw.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_packer.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_39_32_dec.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_39_32_enc.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_64_57_dec.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_inv_64_57_enc.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_subreg_ext.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/sha2.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/sha2_pad.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_adapter_reg.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_adapter_sram.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_cmd_intg_chk.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_data_integ_dec.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_data_integ_enc.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_err.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_err_resp.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_fifo_sync.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_rsp_intg_gen.sv
+INFO: Adding SV_2012 /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/tlul_socket_1n.sv
+INFO: Adding constraint file /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././raptor_sdc.sdc
+INFO: ANL: ##################################################
+INFO: ANL: Analysis for design: hmac
+INFO: ANL: ##################################################
+INFO: ANL: Analyze command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/yosys -s /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/hmac_analyzer.cmd
+Command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/yosys -s /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/hmac_analyzer.cmd
+
+ /----------------------------------------------------------------------------\
+ | yosys -- Yosys Open SYnthesis Suite |
+ | Copyright (C) 2012 - 2024 Claire Xenia Wolf |
+ | Distributed under an ISC-like license, type "license" to see terms |
+ \----------------------------------------------------------------------------/
+
+ Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3)
+
+-- Executing script file `/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/hmac_analyzer.cmd' --
+
+1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v
+Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation.
+Generating RTLIL representation for module `\BOOT_CLOCK'.
+Generating RTLIL representation for module `\CARRY'.
+Generating RTLIL representation for module `\CLK_BUF'.
+Generating RTLIL representation for module `\DFFNRE'.
+Generating RTLIL representation for module `\DFFRE'.
+Generating RTLIL representation for module `\DSP19X2'.
+Generating RTLIL representation for module `\DSP38'.
+Generating RTLIL representation for module `\FCLK_BUF'.
+Generating RTLIL representation for module `\FIFO18KX2'.
+Generating RTLIL representation for module `\FIFO36K'.
+Generating RTLIL representation for module `\I_BUF_DS'.
+Generating RTLIL representation for module `\I_BUF'.
+Generating RTLIL representation for module `\I_DDR'.
+Generating RTLIL representation for module `\I_DELAY'.
+Generating RTLIL representation for module `\I_FAB'.
+Generating RTLIL representation for module `\I_SERDES'.
+Generating RTLIL representation for module `\LATCHNR'.
+Generating RTLIL representation for module `\LATCHNS'.
+Generating RTLIL representation for module `\LATCHN'.
+Generating RTLIL representation for module `\LATCHR'.
+Generating RTLIL representation for module `\LATCHS'.
+Generating RTLIL representation for module `\LATCH'.
+Generating RTLIL representation for module `\LUT1'.
+Generating RTLIL representation for module `\LUT2'.
+Generating RTLIL representation for module `\LUT3'.
+Generating RTLIL representation for module `\LUT4'.
+Generating RTLIL representation for module `\LUT5'.
+Generating RTLIL representation for module `\LUT6'.
+Generating RTLIL representation for module `\MIPI_RX'.
+Generating RTLIL representation for module `\MIPI_TX'.
+Generating RTLIL representation for module `\O_BUF_DS'.
+Generating RTLIL representation for module `\O_BUFT_DS'.
+Generating RTLIL representation for module `\O_BUFT'.
+Generating RTLIL representation for module `\O_BUF'.
+Generating RTLIL representation for module `\O_DDR'.
+Generating RTLIL representation for module `\O_DELAY'.
+Generating RTLIL representation for module `\O_FAB'.
+Generating RTLIL representation for module `\O_SERDES_CLK'.
+Generating RTLIL representation for module `\O_SERDES'.
+Generating RTLIL representation for module `\PLL'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'.
+Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'.
+Generating RTLIL representation for module `\TDP_RAM18KX2'.
+Generating RTLIL representation for module `\TDP_RAM36K'.
+Successfully finished Verilog frontend.
+
+2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_pkg.sv
+Parsing SystemVerilog input from `/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_pkg.sv' to AST representation.
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/.././rtl/prim_secded_pkg.sv:34: ERROR: syntax error, unexpected TOK_CONSTVAL
+ERROR: ANL: Default parser failed, re-attempting with SV parser
+INFO: ANL: ##################################################
+INFO: ANL: Analysis for design: hmac
+INFO: ANL: ##################################################
+INFO: ANL: Analyze command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/yosys -s /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/hmac_analyzer.cmd
+Command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/yosys -s /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/hmac_analyzer.cmd
+
+ /----------------------------------------------------------------------------\
+ | yosys -- Yosys Open SYnthesis Suite |
+ | Copyright (C) 2012 - 2024 Claire Xenia Wolf |
+ | Distributed under an ISC-like license, type "license" to see terms |
+ \----------------------------------------------------------------------------/
+
+ Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3)
+
+-- Executing script file `/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/hmac_analyzer.cmd' --
+
+1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v
+Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation.
+Generating RTLIL representation for module `\BOOT_CLOCK'.
+Generating RTLIL representation for module `\CARRY'.
+Generating RTLIL representation for module `\CLK_BUF'.
+Generating RTLIL representation for module `\DFFNRE'.
+Generating RTLIL representation for module `\DFFRE'.
+Generating RTLIL representation for module `\DSP19X2'.
+Generating RTLIL representation for module `\DSP38'.
+Generating RTLIL representation for module `\FCLK_BUF'.
+Generating RTLIL representation for module `\FIFO18KX2'.
+Generating RTLIL representation for module `\FIFO36K'.
+Generating RTLIL representation for module `\I_BUF_DS'.
+Generating RTLIL representation for module `\I_BUF'.
+Generating RTLIL representation for module `\I_DDR'.
+Generating RTLIL representation for module `\I_DELAY'.
+Generating RTLIL representation for module `\I_FAB'.
+Generating RTLIL representation for module `\I_SERDES'.
+Generating RTLIL representation for module `\LATCHNR'.
+Generating RTLIL representation for module `\LATCHNS'.
+Generating RTLIL representation for module `\LATCHN'.
+Generating RTLIL representation for module `\LATCHR'.
+Generating RTLIL representation for module `\LATCHS'.
+Generating RTLIL representation for module `\LATCH'.
+Generating RTLIL representation for module `\LUT1'.
+Generating RTLIL representation for module `\LUT2'.
+Generating RTLIL representation for module `\LUT3'.
+Generating RTLIL representation for module `\LUT4'.
+Generating RTLIL representation for module `\LUT5'.
+Generating RTLIL representation for module `\LUT6'.
+Generating RTLIL representation for module `\MIPI_RX'.
+Generating RTLIL representation for module `\MIPI_TX'.
+Generating RTLIL representation for module `\O_BUF_DS'.
+Generating RTLIL representation for module `\O_BUFT_DS'.
+Generating RTLIL representation for module `\O_BUFT'.
+Generating RTLIL representation for module `\O_BUF'.
+Generating RTLIL representation for module `\O_DDR'.
+Generating RTLIL representation for module `\O_DELAY'.
+Generating RTLIL representation for module `\O_FAB'.
+Generating RTLIL representation for module `\O_SERDES_CLK'.
+Generating RTLIL representation for module `\O_SERDES'.
+Generating RTLIL representation for module `\PLL'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'.
+Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'.
+Generating RTLIL representation for module `\TDP_RAM18KX2'.
+Generating RTLIL representation for module `\TDP_RAM36K'.
+Successfully finished Verilog frontend.
+Warning: Using synlig as yosys plugin is deprecated. It is recommended to build synlig as standalone binary.
+
+2. Executing SystemVerilog frontend.
+[INF:CM0023] Creating log file "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/slpp_all/surelog.log".
+[INF:CP0300] Compilation...
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_pkg.sv:8:1: Compile package "prim_secded_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg_pkg.sv:5:1: Compile package "prim_subreg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_util_pkg.sv:9:1: Compile package "prim_util_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/pwrmgr_reg_pkg.sv:7:1: Compile package "pwrmgr_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/pwrmgr_pkg.sv:8:1: Compile package "pwrmgr_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_ram_1p_pkg.sv:6:1: Compile package "prim_ram_1p_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:13:1: Compile package "prim_mubi_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_pkg.sv:11:1: Compile package "prim_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:17:1: Compile package "prim_cipher_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_pkg.sv:5:1: Compile package "prim_alert_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_count_pkg.sv:8:1: Compile package "prim_count_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/jtag_pkg.sv:6:1: Compile package "jtag_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/entropy_src_pkg.sv:7:1: Compile package "entropy_src_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/edn_pkg.sv:7:1: Compile package "edn_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/top_pkg.sv:6:1: Compile package "top_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_ctrl_reg_pkg.sv:7:1: Compile package "flash_ctrl_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_ctrl_pkg.sv:8:1: Compile package "flash_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_phy_pkg.sv:8:1: Compile package "flash_phy_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_pkg.sv:7:1: Compile package "hmac_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:6:1: Compile package "hmac_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/lc_ctrl_pkg.sv:6:1: Compile package "lc_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/otp_ctrl_reg_pkg.sv:7:1: Compile package "otp_ctrl_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/otp_ctrl_pkg.sv:6:1: Compile package "otp_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:6:1: Compile package "tlul_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/ast_pkg.sv:12:1: Compile package "ast_pkg".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:9:1: Compile module "work@hmac".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:7:1: Compile module "work@hmac_core".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:8:1: Compile module "work@hmac_reg_top".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:32:1: Compile module "work@prim_alert_sender".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:16:1: Compile module "work@prim_buf".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:19:1: Compile module "work@prim_diff_decode".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:6:1: Compile module "work@prim_fifo_sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:13:1: Compile module "work@prim_flop_2sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_buf.sv:6:1: Compile module "work@prim_generic_buf".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:7:1: Compile module "work@prim_generic_flop".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop_2sync.sv:9:1: Compile module "work@prim_generic_flop_2sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:10:1: Compile module "work@prim_intr_hw".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:8:1: Compile module "work@prim_packer".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:7:1: Compile module "work@prim_secded_inv_39_32_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_enc.sv:7:1: Compile module "work@prim_secded_inv_39_32_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:7:1: Compile module "work@prim_secded_inv_64_57_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_enc.sv:7:1: Compile module "work@prim_secded_inv_64_57_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:7:1: Compile module "work@prim_subreg".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg_ext.sv:7:1: Compile module "work@prim_subreg_ext".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:8:1: Compile module "work@sha2".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:9:1: Compile module "work@sha2_pad".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:10:1: Compile module "work@tlul_adapter_reg".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:13:1: Compile module "work@tlul_adapter_sram".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:3:1: Compile module "work@tlul_cmd_intg_chk".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_data_integ_dec.sv:10:1: Compile module "work@tlul_data_integ_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_data_integ_enc.sv:10:1: Compile module "work@tlul_data_integ_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:7:1: Compile module "work@tlul_err".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:6:1: Compile module "work@tlul_err_resp".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:9:1: Compile module "work@tlul_fifo_sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:9:1: Compile module "work@tlul_rsp_intg_gen".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:35:1: Compile module "work@tlul_socket_1n".
+[INF:CP0302] Compile class "work@mailbox".
+[INF:CP0302] Compile class "work@process".
+[INF:CP0302] Compile class "work@semaphore".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:41:17: Implicit port type (wire) for "sha_message_length".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:21:27: Implicit port type (wire) for "wready",
+there are 3 more instances of this message.
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:24:23: Implicit port type (wire) for "hw2reg_intr_state_de_o",
+there are 1 more instances of this message.
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:19:27: Implicit port type (wire) for "ready_o".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:24:29: Implicit port type (wire) for "spare_req_o",
+there are 1 more instances of this message.
+[INF:EL0526] Design Elaboration...
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[2]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[3]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[4]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[5]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[6]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[7]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_hmac_done.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_fifo_empty.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_hmac_err.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:122:14: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_depth_gt1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:132:23: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_pass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:172:12: Compile generate block "work@hmac.u_tlul_adapter.gen_no_wordwidthadapt".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:206:12: Compile generate block "work@hmac.u_tlul_adapter.gen_writes_allowed".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:210:23: Compile generate block "work@hmac.u_tlul_adapter.gen_no_reads".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:135:14: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_nopass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:135:14: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_nopass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:132:23: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_pass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:19:25: Compile generate block "work@hmac.u_reg.u_rsp_intg_gen.gen_rsp_intg".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:34:26: Compile generate block "work@hmac.u_reg.u_rsp_intg_gen.gen_data_intg".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:124:36: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:124:36: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[2]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:177:36: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:177:36: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_hmac_done.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_fifo_empty.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_hmac_err.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_hmac_done.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_fifo_empty.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_hmac_err.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_err_code.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_msg_length_lower.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_msg_length_upper.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:460:42: Compile generate block "work@hmac.gen_alert_tx[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:44:16: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_n.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:44:16: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_n.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:30:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:30:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_n.gen_generic".
+[NTE:EL0503] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:9:1: Top level module "work@hmac".
+[NTE:EL0508] Nb Top level modules: 1.
+[NTE:EL0509] Max instance depth: 9.
+[NTE:EL0510] Nb instances: 98.
+[NTE:EL0511] Nb leaf instances: 32.
+[INF:UH0706] Creating UHDM Model...
+[INF:UH0707] Elaborating UHDM...
+[ FATAL] : 0
+[ SYNTAX] : 0
+[ ERROR] : 0
+[WARNING] : 0
+[ NOTE] : 10
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_util_pkg.sv:34: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:80: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:106: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:209: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:235: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:338: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:364: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:467: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:493: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:71: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:82: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:293: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:304: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:315: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:328: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:337: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:346: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:355: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:364: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:373: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:382: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:391: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_ctrl_pkg.sv:553: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:128: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:322: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:488: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:185: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:253: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:53: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:87: Post-decrementation operations are handled as pre-decrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:97: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:112: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:116: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:122: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:144: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:156: Post-incrementation operations are handled as pre-incrementation.
+Generating RTLIL representation for module `$paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000'.
+Generating RTLIL representation for module `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg'.
+Generating RTLIL representation for module `$paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101'.
+Generating RTLIL representation for module `$paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001'.
+Generating RTLIL representation for module `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp'.
+Generating RTLIL representation for module `$paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_diff_decode\AsyncOn=1'1'.
+Generating RTLIL representation for module `$paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf'.
+Generating RTLIL representation for module `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg'.
+Generating RTLIL representation for module `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender'.
+Generating RTLIL representation for module `\sha2'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1'.
+Generating RTLIL representation for module `\hmac'.
+Generating RTLIL representation for module `$paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1'.
+Generating RTLIL representation for module `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg'.
+Generating RTLIL representation for module `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0'.
+Generating RTLIL representation for module `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk'.
+Generating RTLIL representation for module `$paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0'.
+Generating RTLIL representation for module `$paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1'.
+Generating RTLIL representation for module `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err'.
+Generating RTLIL representation for module `\hmac_core'.
+Warning: reg '\sel_msglen' is assigned in a continuous assignment at /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:179.10-179.67.
+Generating RTLIL representation for module `$paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1'.
+Generating RTLIL representation for module `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top'.
+Generating RTLIL representation for module `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen'.
+Generating RTLIL representation for module `\sha2_pad'.
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:83: Warning: Range select [127:124] out of bounds on signal `\fifo_rdata': Setting all 4 result bits to undef.
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:84: Warning: Range select [127:124] out of bounds on signal `\fifo_rdata': Setting all 4 result bits to undef.
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:85: Warning: Range select [127:124] out of bounds on signal `\fifo_rdata': Setting all 4 result bits to undef.
+Generating RTLIL representation for module `\prim_secded_inv_64_57_dec'.
+Generating RTLIL representation for module `$paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec'.
+Generating RTLIL representation for module `\prim_secded_inv_39_32_dec'.
+Generating RTLIL representation for module `\prim_generic_buf'.
+Generating RTLIL representation for module `\prim_secded_inv_64_57_enc'.
+Generating RTLIL representation for module `$paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc'.
+Generating RTLIL representation for module `\prim_secded_inv_39_32_enc'.
+Generating RTLIL representation for module `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n'.
+
+-- Running command `hierarchy -top hmac' --
+
+3. Executing HIERARCHY pass (managing design hierarchy).
+
+3.1. Analyzing design hierarchy..
+Top module: \hmac
+Used module: $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top
+Used module: $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001
+Used module: $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg
+Used module: $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg
+Used module: $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err
+Used module: $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp
+Used module: $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync
+Used module: $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync
+Used module: $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync
+Used module: $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync
+Used module: $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync
+Used module: $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync
+Used module: $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc
+Used module: \prim_secded_inv_39_32_enc
+Used module: \prim_secded_inv_64_57_enc
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec
+Used module: \prim_secded_inv_39_32_dec
+Used module: \prim_secded_inv_64_57_dec
+Used module: \sha2
+Used module: \sha2_pad
+Used module: \hmac_core
+Used module: $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer
+Used module: $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram
+Used module: $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync
+Used module: $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync
+Used module: $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync
+Used module: $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync
+Used module: $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1
+Used module: $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender
+Used module: $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf
+Used module: \prim_generic_buf
+Used module: $paramod\prim_diff_decode\AsyncOn=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+
+3.2. Analyzing design hierarchy..
+Top module: \hmac
+Used module: $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top
+Used module: $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001
+Used module: $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg
+Used module: $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg
+Used module: $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err
+Used module: $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp
+Used module: $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync
+Used module: $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync
+Used module: $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync
+Used module: $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync
+Used module: $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync
+Used module: $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync
+Used module: $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc
+Used module: \prim_secded_inv_39_32_enc
+Used module: \prim_secded_inv_64_57_enc
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec
+Used module: \prim_secded_inv_39_32_dec
+Used module: \prim_secded_inv_64_57_dec
+Used module: \sha2
+Used module: \sha2_pad
+Used module: \hmac_core
+Used module: $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer
+Used module: $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram
+Used module: $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync
+Used module: $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync
+Used module: $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync
+Used module: $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync
+Used module: $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1
+Used module: $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender
+Used module: $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf
+Used module: \prim_generic_buf
+Used module: $paramod\prim_diff_decode\AsyncOn=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Removed 0 unused modules.
+Warning: Resizing cell port $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.gen_rsp_intg.u_rsp_gen.data_i from 6 bits to 57 bits.
+Warning: Resizing cell port $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.u_socket.dev_select_i from 1 bits to 2 bits.
+Warning: Resizing cell port $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.u_chk.data_i from 50 bits to 64 bits.
+Warning: Resizing cell port hmac.u_sha2.digest from 256 bits to 32 bits.
+
+Dumping file hier_info.json ...
+ Process module "$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\\prim_fifo_sync"
+ Process module "$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\\prim_subreg"
+ Process module "$paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\\prim_fifo_sync"
+ Process module "$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\\prim_alert_sender"
+ Process module "$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\\prim_packer"
+ Process module "$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\\tlul_rsp_intg_gen"
+ Process module "$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\\hmac_reg_top"
+ Process module "$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\\tlul_socket_1n"
+ Process module "$paramod$58742bab91a003d79034aeb644264cbb951eb306\\prim_fifo_sync"
+ Process module "$paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\\prim_fifo_sync"
+ Process module "$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\\prim_subreg"
+ Process module "$paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\\tlul_fifo_sync"
+ Process module "$paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\\prim_fifo_sync"
+ Process module "$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\\prim_fifo_sync"
+ Process module "$paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\\prim_buf"
+ Process module "$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\\tlul_adapter_sram"
+ Process module "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_cmd_intg_chk"
+ Process module "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_data_integ_dec"
+ Process module "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_data_integ_enc"
+ Process module "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_err"
+ Process module "$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\\tlul_err_resp"
+ Process module "$paramod$b652f3dfdeef7584c496ced680b0643f32807516\\tlul_adapter_reg"
+ Process module "$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\\prim_fifo_sync"
+ Process module "$paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\\tlul_fifo_sync"
+ Process module "$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\\prim_subreg"
+ Process module "$paramod$f519e51f824927b1da80ae7de12f65225cc31206\\prim_fifo_sync"
+ Process module "$paramod\\prim_diff_decode\\AsyncOn=1'1"
+ Process module "$paramod\\prim_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0"
+ Process module "$paramod\\prim_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1"
+ Process module "$paramod\\prim_generic_flop\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0"
+ Process module "$paramod\\prim_generic_flop\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1"
+ Process module "$paramod\\prim_generic_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'0"
+ Process module "$paramod\\prim_generic_flop_2sync\\Width=s32'00000000000000000000000000000001\\ResetValue=1'1"
+ Process module "$paramod\\prim_intr_hw\\Width=32'00000000000000000000000000000001\\FlopOutput=1'1"
+ Process module "$paramod\\prim_subreg_ext\\DW=32'00000000000000000000000000000001"
+ Process module "$paramod\\prim_subreg_ext\\DW=32'00000000000000000000000000000101"
+ Process module "$paramod\\prim_subreg_ext\\DW=32'00000000000000000000000000100000"
+ Process module "hmac_core"
+ Process module "prim_generic_buf"
+ Process module "prim_secded_inv_39_32_dec"
+ Process module "prim_secded_inv_39_32_enc"
+ Process module "prim_secded_inv_64_57_dec"
+ Process module "prim_secded_inv_64_57_enc"
+ Process module "sha2"
+ Process module "sha2_pad"
+Dumping file port_info.json ...
+
+Warnings: 43 unique messages, 45 total
+End of script. Logfile hash: a31f120628, CPU: user 14.84s system 0.68s, MEM: 990.51 MB peak
+Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3)
+Time spent: 98% 2x read_systemverilog (15 sec), 0% 1x analyze (0 sec), ...
+INFO: ANL: Design hmac is analyzed
+INFO: ANL: Top Modules: hmac
+
+INFO: ANL: Design hmac is analyzed
+INFO: ANL: Top Modules: hmac
+
+INFO: SYN: ##################################################
+INFO: SYN: Synthesis for design: hmac
+INFO: SYN: ##################################################
+INFO: SYN: RS Synthesis
+INFO: SYN: Synthesis command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/yosys -s hmac.ys -l hmac_synth.log
+Command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/yosys -s hmac.ys -l hmac_synth.log
+
+ /----------------------------------------------------------------------------\
+ | yosys -- Yosys Open SYnthesis Suite |
+ | Copyright (C) 2012 - 2024 Claire Xenia Wolf |
+ | Distributed under an ISC-like license, type "license" to see terms |
+ \----------------------------------------------------------------------------/
+
+ Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3)
+
+-- Executing script file `hmac.ys' --
+Warning: Using synlig as yosys plugin is deprecated. It is recommended to build synlig as standalone binary.
+
+1. Executing SystemVerilog frontend.
+[INF:CM0023] Creating log file "/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/synthesis/slpp_all/surelog.log".
+[INF:CP0300] Compilation...
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_pkg.sv:8:1: Compile package "prim_secded_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg_pkg.sv:5:1: Compile package "prim_subreg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_util_pkg.sv:9:1: Compile package "prim_util_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/pwrmgr_reg_pkg.sv:7:1: Compile package "pwrmgr_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/pwrmgr_pkg.sv:8:1: Compile package "pwrmgr_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_ram_1p_pkg.sv:6:1: Compile package "prim_ram_1p_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:13:1: Compile package "prim_mubi_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_pkg.sv:11:1: Compile package "prim_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:17:1: Compile package "prim_cipher_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_pkg.sv:5:1: Compile package "prim_alert_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_count_pkg.sv:8:1: Compile package "prim_count_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/jtag_pkg.sv:6:1: Compile package "jtag_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/entropy_src_pkg.sv:7:1: Compile package "entropy_src_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/edn_pkg.sv:7:1: Compile package "edn_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/top_pkg.sv:6:1: Compile package "top_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_ctrl_reg_pkg.sv:7:1: Compile package "flash_ctrl_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_ctrl_pkg.sv:8:1: Compile package "flash_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_phy_pkg.sv:8:1: Compile package "flash_phy_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_pkg.sv:7:1: Compile package "hmac_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:6:1: Compile package "hmac_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/lc_ctrl_pkg.sv:6:1: Compile package "lc_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/otp_ctrl_reg_pkg.sv:7:1: Compile package "otp_ctrl_reg_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/otp_ctrl_pkg.sv:6:1: Compile package "otp_ctrl_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:6:1: Compile package "tlul_pkg".
+[INF:CP0301] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/ast_pkg.sv:12:1: Compile package "ast_pkg".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:8:1: Compile module "work@BOOT_CLOCK".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:23:1: Compile module "work@CARRY".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:40:1: Compile module "work@CLK_BUF".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:55:1: Compile module "work@DFFNRE".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:73:1: Compile module "work@DFFRE".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:91:1: Compile module "work@DSP19X2".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:135:1: Compile module "work@DSP38".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:171:1: Compile module "work@FCLK_BUF".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:185:1: Compile module "work@FIFO18KX2".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:242:1: Compile module "work@FIFO36K".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:299:1: Compile module "work@I_BUF".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:277:1: Compile module "work@I_BUF_DS".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:318:1: Compile module "work@I_DDR".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:336:1: Compile module "work@I_DELAY".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:358:1: Compile module "work@I_FAB".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:372:1: Compile module "work@I_SERDES".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:480:1: Compile module "work@LATCH".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:433:1: Compile module "work@LATCHN".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:401:1: Compile module "work@LATCHNR".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:417:1: Compile module "work@LATCHNS".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:448:1: Compile module "work@LATCHR".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:464:1: Compile module "work@LATCHS".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:495:1: Compile module "work@LUT1".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:511:1: Compile module "work@LUT2".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:527:1: Compile module "work@LUT3".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:543:1: Compile module "work@LUT4".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:559:1: Compile module "work@LUT5".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:575:1: Compile module "work@LUT6".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:591:1: Compile module "work@MIPI_RX".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:627:1: Compile module "work@MIPI_TX".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:729:1: Compile module "work@O_BUF".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:708:1: Compile module "work@O_BUFT".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:686:1: Compile module "work@O_BUFT_DS".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:664:1: Compile module "work@O_BUF_DS".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:750:1: Compile module "work@O_DDR".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:768:1: Compile module "work@O_DELAY".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:790:1: Compile module "work@O_FAB".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:823:1: Compile module "work@O_SERDES".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:804:1: Compile module "work@O_SERDES_CLK".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:850:1: Compile module "work@PLL".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:878:1: Compile module "work@SOC_FPGA_INTF_AHB_M".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:902:1: Compile module "work@SOC_FPGA_INTF_AHB_S".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:929:1: Compile module "work@SOC_FPGA_INTF_AXI_M0".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:978:1: Compile module "work@SOC_FPGA_INTF_AXI_M1".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1027:1: Compile module "work@SOC_FPGA_INTF_DMA".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1043:1: Compile module "work@SOC_FPGA_INTF_IRQ".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1059:1: Compile module "work@SOC_FPGA_INTF_JTAG".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1077:1: Compile module "work@SOC_FPGA_TEMPERATURE".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1095:1: Compile module "work@TDP_RAM18KX2".
+[INF:CP0303] /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v:1160:1: Compile module "work@TDP_RAM36K".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:9:1: Compile module "work@hmac".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:7:1: Compile module "work@hmac_core".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:8:1: Compile module "work@hmac_reg_top".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:32:1: Compile module "work@prim_alert_sender".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:16:1: Compile module "work@prim_buf".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:19:1: Compile module "work@prim_diff_decode".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:6:1: Compile module "work@prim_fifo_sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:13:1: Compile module "work@prim_flop_2sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_buf.sv:6:1: Compile module "work@prim_generic_buf".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:7:1: Compile module "work@prim_generic_flop".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop_2sync.sv:9:1: Compile module "work@prim_generic_flop_2sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:10:1: Compile module "work@prim_intr_hw".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:8:1: Compile module "work@prim_packer".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:7:1: Compile module "work@prim_secded_inv_39_32_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_enc.sv:7:1: Compile module "work@prim_secded_inv_39_32_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:7:1: Compile module "work@prim_secded_inv_64_57_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_enc.sv:7:1: Compile module "work@prim_secded_inv_64_57_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:7:1: Compile module "work@prim_subreg".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg_ext.sv:7:1: Compile module "work@prim_subreg_ext".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:8:1: Compile module "work@sha2".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:9:1: Compile module "work@sha2_pad".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:10:1: Compile module "work@tlul_adapter_reg".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:13:1: Compile module "work@tlul_adapter_sram".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:3:1: Compile module "work@tlul_cmd_intg_chk".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_data_integ_dec.sv:10:1: Compile module "work@tlul_data_integ_dec".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_data_integ_enc.sv:10:1: Compile module "work@tlul_data_integ_enc".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:7:1: Compile module "work@tlul_err".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:6:1: Compile module "work@tlul_err_resp".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:9:1: Compile module "work@tlul_fifo_sync".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:9:1: Compile module "work@tlul_rsp_intg_gen".
+[INF:CP0303] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:35:1: Compile module "work@tlul_socket_1n".
+[INF:CP0302] Compile class "work@mailbox".
+[INF:CP0302] Compile class "work@process".
+[INF:CP0302] Compile class "work@semaphore".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:41:17: Implicit port type (wire) for "sha_message_length".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:21:27: Implicit port type (wire) for "wready",
+there are 3 more instances of this message.
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:24:23: Implicit port type (wire) for "hw2reg_intr_state_de_o",
+there are 1 more instances of this message.
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:19:27: Implicit port type (wire) for "ready_o".
+[NTE:CP0309] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:24:29: Implicit port type (wire) for "spare_req_o",
+there are 1 more instances of this message.
+[INF:EL0526] Design Elaboration...
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[2]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[3]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[4]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[5]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[6]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:136:34: Compile generate block "work@hmac.gen_key_digest[7]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_hmac_done.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_fifo_empty.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:39:24: Compile generate block "work@hmac.intr_hw_hmac_err.gen_flop_intr_output".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:122:14: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_depth_gt1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:132:23: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_pass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_msg_fifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:172:12: Compile generate block "work@hmac.u_tlul_adapter.gen_no_wordwidthadapt".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:206:12: Compile generate block "work@hmac.u_tlul_adapter.gen_writes_allowed".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:210:23: Compile generate block "work@hmac.u_tlul_adapter.gen_no_reads".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:135:14: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_nopass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_reqfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:135:14: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_nopass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:48:12: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:114:21: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_depth_eq1".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:132:23: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_pass".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:140:36: Compile generate block "work@hmac.u_tlul_adapter.u_rspfifo.gen_normal_fifo.gen_output_zero".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:19:25: Compile generate block "work@hmac.u_reg.u_rsp_intg_gen.gen_rsp_intg".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:34:26: Compile generate block "work@hmac.u_reg.u_rsp_intg_gen.gen_data_intg".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:124:36: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:124:36: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:172:38: Compile generate block "work@hmac.u_reg.u_socket.gen_u_o_d_ready[2]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:177:36: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:177:36: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:32:19: Compile generate block "work@hmac.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_hmac_done.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_fifo_empty.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_state_hmac_err.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_hmac_done.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_fifo_empty.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_intr_enable_hmac_err.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_err_code.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_msg_length_lower.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:60:12: Compile generate block "work@hmac.u_reg.u_msg_length_upper.gen_hw".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:460:42: Compile generate block "work@hmac.gen_alert_tx[0]".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:44:16: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_n.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:44:16: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_flop_2sync.sv:28:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_n.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:30:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_p.gen_generic".
+[INF:CP0335] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_buf.sv:30:10: Compile generate block "work@hmac.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_n.gen_generic".
+[NTE:EL0503] /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:9:1: Top level module "work@hmac".
+[NTE:EL0508] Nb Top level modules: 1.
+[NTE:EL0509] Max instance depth: 9.
+[NTE:EL0510] Nb instances: 98.
+[NTE:EL0511] Nb leaf instances: 32.
+[INF:UH0706] Creating UHDM Model...
+[INF:UH0707] Elaborating UHDM...
+[ FATAL] : 0
+[ SYNTAX] : 0
+[ ERROR] : 0
+[WARNING] : 0
+[ NOTE] : 10
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_util_pkg.sv:34: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:80: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:106: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:209: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:235: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:338: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:364: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:467: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_mubi_pkg.sv:493: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:71: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:82: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:293: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:304: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:315: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:328: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:337: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:346: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:355: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:364: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:373: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:382: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_cipher_pkg.sv:391: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/flash_ctrl_pkg.sv:553: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:128: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:322: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:488: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:185: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:253: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:53: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:87: Post-decrementation operations are handled as pre-decrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:97: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:112: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:116: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:122: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:144: Post-incrementation operations are handled as pre-incrementation.
+Warning: /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:156: Post-incrementation operations are handled as pre-incrementation.
+Generating RTLIL representation for module `$paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000'.
+Generating RTLIL representation for module `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg'.
+Generating RTLIL representation for module `$paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101'.
+Generating RTLIL representation for module `$paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001'.
+Generating RTLIL representation for module `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp'.
+Generating RTLIL representation for module `$paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_diff_decode\AsyncOn=1'1'.
+Generating RTLIL representation for module `$paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf'.
+Generating RTLIL representation for module `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg'.
+Generating RTLIL representation for module `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender'.
+Generating RTLIL representation for module `\sha2'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1'.
+Generating RTLIL representation for module `\hmac'.
+Generating RTLIL representation for module `$paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1'.
+Generating RTLIL representation for module `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg'.
+Generating RTLIL representation for module `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0'.
+Generating RTLIL representation for module `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk'.
+Generating RTLIL representation for module `$paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0'.
+Generating RTLIL representation for module `$paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1'.
+Generating RTLIL representation for module `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err'.
+Generating RTLIL representation for module `\hmac_core'.
+Warning: reg '\sel_msglen' is assigned in a continuous assignment at /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:179.10-179.67.
+Generating RTLIL representation for module `$paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync'.
+Generating RTLIL representation for module `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1'.
+Generating RTLIL representation for module `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top'.
+Generating RTLIL representation for module `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen'.
+Generating RTLIL representation for module `\sha2_pad'.
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:83: Warning: Range select [127:124] out of bounds on signal `\fifo_rdata': Setting all 4 result bits to undef.
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:84: Warning: Range select [127:124] out of bounds on signal `\fifo_rdata': Setting all 4 result bits to undef.
+/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:85: Warning: Range select [127:124] out of bounds on signal `\fifo_rdata': Setting all 4 result bits to undef.
+Generating RTLIL representation for module `\prim_secded_inv_64_57_dec'.
+Generating RTLIL representation for module `$paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec'.
+Generating RTLIL representation for module `\prim_secded_inv_39_32_dec'.
+Generating RTLIL representation for module `\prim_generic_buf'.
+Generating RTLIL representation for module `\prim_secded_inv_64_57_enc'.
+Generating RTLIL representation for module `$paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync'.
+Generating RTLIL representation for module `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc'.
+Generating RTLIL representation for module `\prim_secded_inv_39_32_enc'.
+Generating RTLIL representation for module `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n'.
+
+2. Executing HIERARCHY pass (managing design hierarchy).
+
+2.1. Analyzing design hierarchy..
+Top module: \hmac
+Used module: $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top
+Used module: $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001
+Used module: $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg
+Used module: $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg
+Used module: $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err
+Used module: $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp
+Used module: $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync
+Used module: $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync
+Used module: $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync
+Used module: $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync
+Used module: $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync
+Used module: $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync
+Used module: $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc
+Used module: \prim_secded_inv_39_32_enc
+Used module: \prim_secded_inv_64_57_enc
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec
+Used module: \prim_secded_inv_39_32_dec
+Used module: \prim_secded_inv_64_57_dec
+Used module: \sha2
+Used module: \sha2_pad
+Used module: \hmac_core
+Used module: $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer
+Used module: $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram
+Used module: $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync
+Used module: $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync
+Used module: $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync
+Used module: $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync
+Used module: $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1
+Used module: $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender
+Used module: $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf
+Used module: \prim_generic_buf
+Used module: $paramod\prim_diff_decode\AsyncOn=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+
+2.2. Analyzing design hierarchy..
+Top module: \hmac
+Used module: $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top
+Used module: $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001
+Used module: $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg
+Used module: $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg
+Used module: $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err
+Used module: $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp
+Used module: $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync
+Used module: $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync
+Used module: $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync
+Used module: $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync
+Used module: $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync
+Used module: $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync
+Used module: $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc
+Used module: \prim_secded_inv_39_32_enc
+Used module: \prim_secded_inv_64_57_enc
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec
+Used module: \prim_secded_inv_39_32_dec
+Used module: \prim_secded_inv_64_57_dec
+Used module: \sha2
+Used module: \sha2_pad
+Used module: \hmac_core
+Used module: $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer
+Used module: $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram
+Used module: $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync
+Used module: $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync
+Used module: $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync
+Used module: $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync
+Used module: $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1
+Used module: $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender
+Used module: $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf
+Used module: \prim_generic_buf
+Used module: $paramod\prim_diff_decode\AsyncOn=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Removed 0 unused modules.
+Warning: Resizing cell port $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.gen_rsp_intg.u_rsp_gen.data_i from 6 bits to 57 bits.
+Warning: Resizing cell port $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.u_socket.dev_select_i from 1 bits to 2 bits.
+Warning: Resizing cell port $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.u_chk.data_i from 50 bits to 64 bits.
+Warning: Resizing cell port hmac.u_sha2.digest from 256 bits to 32 bits.
+
+3. Executing synth_rs pass: v0.4.218
+
+3.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/common/cells_sim.v' to AST representation.
+Generating RTLIL representation for module `\inv'.
+Generating RTLIL representation for module `\buff'.
+Generating RTLIL representation for module `\logic_0'.
+Generating RTLIL representation for module `\logic_1'.
+Generating RTLIL representation for module `\gclkbuff'.
+Successfully finished Verilog frontend.
+
+3.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CARRY.v' to AST representation.
+Generating RTLIL representation for module `\CARRY'.
+Successfully finished Verilog frontend.
+
+3.3. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/llatches_sim.v' to AST representation.
+Generating RTLIL representation for module `\LATCH'.
+Generating RTLIL representation for module `\LATCHN'.
+Generating RTLIL representation for module `\LATCHR'.
+Generating RTLIL representation for module `\LATCHS'.
+Generating RTLIL representation for module `\LATCHNR'.
+Generating RTLIL representation for module `\LATCHNS'.
+Generating RTLIL representation for module `\LATCHSRE'.
+Generating RTLIL representation for module `\LATCHNSRE'.
+Successfully finished Verilog frontend.
+
+3.4. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFRE.v' to AST representation.
+Generating RTLIL representation for module `\DFFRE'.
+Successfully finished Verilog frontend.
+
+3.5. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DFFNRE.v' to AST representation.
+Generating RTLIL representation for module `\DFFNRE'.
+Successfully finished Verilog frontend.
+
+3.6. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT1.v' to AST representation.
+Generating RTLIL representation for module `\LUT1'.
+Successfully finished Verilog frontend.
+
+3.7. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT2.v' to AST representation.
+Generating RTLIL representation for module `\LUT2'.
+Successfully finished Verilog frontend.
+
+3.8. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT3.v' to AST representation.
+Generating RTLIL representation for module `\LUT3'.
+Successfully finished Verilog frontend.
+
+3.9. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT4.v' to AST representation.
+Generating RTLIL representation for module `\LUT4'.
+Successfully finished Verilog frontend.
+
+3.10. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT5.v' to AST representation.
+Generating RTLIL representation for module `\LUT5'.
+Successfully finished Verilog frontend.
+
+3.11. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/LUT6.v' to AST representation.
+Generating RTLIL representation for module `\LUT6'.
+Successfully finished Verilog frontend.
+
+3.12. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/CLK_BUF.v' to AST representation.
+Generating RTLIL representation for module `\CLK_BUF'.
+Successfully finished Verilog frontend.
+
+3.13. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/O_BUF.v' to AST representation.
+Generating RTLIL representation for module `\O_BUF'.
+Successfully finished Verilog frontend.
+
+3.14. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v' to AST representation.
+Generating RTLIL representation for module `\DSP38'.
+Successfully finished Verilog frontend.
+
+3.15. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/bram_map_rs.v' to AST representation.
+Generating RTLIL representation for module `\TDP_RAM36K'.
+Generating RTLIL representation for module `\TDP_RAM18KX2'.
+Generating RTLIL representation for module `\RS_DSP3'.
+Generating RTLIL representation for module `\DSP19X2'.
+Successfully finished Verilog frontend.
+
+3.16. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_sim.v' to AST representation.
+Generating RTLIL representation for module `\TDP_BRAM18'.
+Generating RTLIL representation for module `\BRAM2x18_TDP'.
+Generating RTLIL representation for module `\BRAM2x18_SDP'.
+Generating RTLIL representation for module `\_$_mem_v2_asymmetric'.
+Successfully finished Verilog frontend.
+
+3.17. Executing HIERARCHY pass (managing design hierarchy).
+
+3.17.1. Analyzing design hierarchy..
+Top module: \hmac
+Used module: $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top
+Used module: $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001
+Used module: $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg
+Used module: $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg
+Used module: $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err
+Used module: $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp
+Used module: $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync
+Used module: $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync
+Used module: $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync
+Used module: $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync
+Used module: $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync
+Used module: $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync
+Used module: $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc
+Used module: \prim_secded_inv_39_32_enc
+Used module: \prim_secded_inv_64_57_enc
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec
+Used module: \prim_secded_inv_39_32_dec
+Used module: \prim_secded_inv_64_57_dec
+Used module: \sha2
+Used module: \sha2_pad
+Used module: \hmac_core
+Used module: $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer
+Used module: $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram
+Used module: $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync
+Used module: $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync
+Used module: $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync
+Used module: $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync
+Used module: $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1
+Used module: $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender
+Used module: $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf
+Used module: \prim_generic_buf
+Used module: $paramod\prim_diff_decode\AsyncOn=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+
+3.17.2. Analyzing design hierarchy..
+Top module: \hmac
+Used module: $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top
+Used module: $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101
+Used module: $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001
+Used module: $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg
+Used module: $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg
+Used module: $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err
+Used module: $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp
+Used module: $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync
+Used module: $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync
+Used module: $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync
+Used module: $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync
+Used module: $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync
+Used module: $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync
+Used module: $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc
+Used module: \prim_secded_inv_39_32_enc
+Used module: \prim_secded_inv_64_57_enc
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk
+Used module: $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec
+Used module: \prim_secded_inv_39_32_dec
+Used module: \prim_secded_inv_64_57_dec
+Used module: \sha2
+Used module: \sha2_pad
+Used module: \hmac_core
+Used module: $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer
+Used module: $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram
+Used module: $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync
+Used module: $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync
+Used module: $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync
+Used module: $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync
+Used module: $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1
+Used module: $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender
+Used module: $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf
+Used module: \prim_generic_buf
+Used module: $paramod\prim_diff_decode\AsyncOn=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1
+Used module: $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Used module: $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0
+Removed 0 unused modules.
+
+3.18. Executing PROC pass (convert processes to netlists).
+
+3.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Found and cleaned up 1 empty switch in `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1211$1509'.
+Cleaned up 1 empty switch.
+
+3.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:100$1960 in module $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:154$1946 in module $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:142$1942 in module $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:49$1656 in module sha2_pad.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:298$1648 in module sha2_pad.
+Marked 11 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638 in module sha2_pad.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:135$1636 in module sha2_pad.
+Removed 1 dead cases from process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:69$1635 in module sha2_pad.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:69$1635 in module sha2_pad.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$1616 in module $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$1611 in module $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:61$1596 in module $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1075$1508 in module $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:117$1343 in module $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$1259 in module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:140$1254 in module hmac_core.
+Marked 8 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197 in module hmac_core.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:181$1195 in module hmac_core.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:169$1191 in module hmac_core.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:161$1189 in module hmac_core.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:151$1186 in module hmac_core.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:46$1165 in module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:108$1148 in module $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958 in module $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:126$955 in module $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:125$924 in module $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$916 in module $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$911 in module $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:41$890 in module $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.
+Removed 1 dead cases from process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:159$819 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:138$817 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Removed 1 dead cases from process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:109$816 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:109$816 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 32 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:85$782 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:73$780 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Removed 1 dead cases from process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:60$772 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:60$772 in module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$770 in module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$759 in module $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$754 in module $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:64$739 in module $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:120$722 in module $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:83$718 in module $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715 in module $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:121$598 in module hmac.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:555$549 in module hmac.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:507$548 in module hmac.
+Marked 9 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:485$537 in module hmac.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:328$532 in module hmac.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:200$495 in module hmac.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:187$493 in module hmac.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:178$489 in module hmac.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:168$487 in module hmac.
+Marked 5 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324 in module sha2.
+Marked 5 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314 in module sha2.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:236$312 in module sha2.
+Marked 7 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:177$307 in module sha2.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:169$305 in module sha2.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:156$303 in module sha2.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:144$299 in module sha2.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:129$294 in module sha2.
+Marked 5 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261 in module sha2.
+Marked 4 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98 in module sha2.
+Removed 1 dead cases from process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72 in module $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.
+Marked 8 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72 in module $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65 in module $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$57 in module $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.
+Marked 3 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$52 in module $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$37 in module $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$35 in module $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33 in module $paramod\prim_diff_decode\AsyncOn=1'1.
+Marked 8 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30 in module $paramod\prim_diff_decode\AsyncOn=1'1.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20 in module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.
+Marked 2 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:49$9 in module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$7 in module $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$5 in module $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$3 in module $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.
+Marked 1 switch rules as full_case in process $proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$1 in module $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.
+Removed a total of 5 dead cases.
+
+3.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
+Removed 26 redundant assignments.
+Promoted 421 assignments to connections.
+
+3.18.4. Executing PROC_INIT pass (extract init attributes).
+
+3.18.5. Executing PROC_ARST pass (detect async resets in processes).
+Found async reset \rst_ni in `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:100$1960'.
+Found async reset \rst_ni in `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:49$1656'.
+Found async reset \rst_ni in `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:298$1648'.
+Found async reset \rst_ni in `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:135$1636'.
+Found async reset \rst_ni in `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$1616'.
+Found async reset \rst_ni in `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$1611'.
+Found async reset \rst_ni in `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:61$1596'.
+Found async reset \rst_ni in `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$1259'.
+Found async reset \rst_ni in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:140$1254'.
+Found async reset \rst_ni in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:181$1195'.
+Found async reset \rst_ni in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:169$1191'.
+Found async reset \rst_ni in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:161$1189'.
+Found async reset \rst_ni in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:151$1186'.
+Found async reset \rst_ni in `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$916'.
+Found async reset \rst_ni in `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$911'.
+Found async reset \rst_ni in `$paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:41$890'.
+Found async reset \rst_ni in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:159$819'.
+Found async reset \rst_ni in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:138$817'.
+Found async reset \rst_ni in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:73$780'.
+Found async reset \rst_ni in `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$770'.
+Found async reset \rst_ni in `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$759'.
+Found async reset \rst_ni in `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$754'.
+Found async reset \rst_ni in `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:64$739'.
+Found async reset \rst_ni in `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:83$718'.
+Found async reset \rst_ni in `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715'.
+Found async reset \rst_ni in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:121$598'.
+Found async reset \rst_ni in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:555$549'.
+Found async reset \rst_ni in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:328$532'.
+Found async reset \rst_ni in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:200$495'.
+Found async reset \rst_ni in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:187$493'.
+Found async reset \rst_ni in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:178$489'.
+Found async reset \rst_ni in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:168$487'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:236$312'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:169$305'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:156$303'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:144$299'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:129$294'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+Found async reset \rst_ni in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+Found async reset \rst_ni in `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+Found async reset \rst_ni in `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$57'.
+Found async reset \rst_ni in `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$52'.
+Found async reset \rst_ni in `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$37'.
+Found async reset \rst_ni in `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$35'.
+Found async reset \rst_ni in `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33'.
+Found async reset \rst_ni in `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20'.
+Found async reset \rst_ni in `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:49$9'.
+Found async reset \rst_ni in `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$7'.
+Found async reset \rst_ni in `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$5'.
+Found async reset \rst_ni in `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$3'.
+Found async reset \rst_ni in `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$1'.
+
+3.18.6. Executing PROC_ROM pass (convert switches to ROMs).
+Converted 1 switch.
+
+
+3.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
+Creating decoders for process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:100$1960'.
+ 1/2: $0\dev_select_outstanding[1:0]
+ 2/2: $0\num_req_outstanding[8:0]
+Creating decoders for process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:154$1946'.
+ 1/2: $2\tl_t_p[65:0]
+ 2/2: $1\tl_t_p[65:0]
+Creating decoders for process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:142$1942'.
+ 1/3: $3\hfifo_reqready[0:0]
+ 2/3: $2\hfifo_reqready[0:0]
+ 3/3: $1\hfifo_reqready[0:0]
+Creating decoders for process `\prim_secded_inv_39_32_enc.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_enc.sv:12$1912'.
+Creating decoders for process `\prim_secded_inv_64_57_enc.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_enc.sv:12$1890'.
+Creating decoders for process `\prim_secded_inv_39_32_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:14$1800'.
+Creating decoders for process `\prim_secded_inv_64_57_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:14$1659'.
+Creating decoders for process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:49$1656'.
+ 1/1: $0\hash_process_flag[0:0]
+Creating decoders for process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:298$1648'.
+ 1/2: $0\tx_count[63:0] [63:5]
+ 2/2: $0\tx_count[63:0] [4:0]
+Creating decoders for process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+ 1/30: $10\inc_txcount[0:0]
+ 2/30: $11\st_d[2:0]
+ 3/30: $9\inc_txcount[0:0]
+ 4/30: $10\st_d[2:0]
+ 5/30: $9\st_d[2:0]
+ 6/30: $8\st_d[2:0]
+ 7/30: $8\inc_txcount[0:0]
+ 8/30: $7\inc_txcount[0:0]
+ 9/30: $7\st_d[2:0]
+ 10/30: $6\inc_txcount[0:0]
+ 11/30: $6\st_d[2:0]
+ 12/30: $5\st_d[2:0]
+ 13/30: $4\fifo_rready[0:0]
+ 14/30: $5\inc_txcount[0:0]
+ 15/30: $4\shaf_rvalid[0:0]
+ 16/30: $4\st_d[2:0]
+ 17/30: $4\inc_txcount[0:0]
+ 18/30: $3\shaf_rvalid[0:0]
+ 19/30: $3\fifo_rready[0:0]
+ 20/30: $3\st_d[2:0]
+ 21/30: $2\fifo_rready[0:0]
+ 22/30: $3\inc_txcount[0:0]
+ 23/30: $2\shaf_rvalid[0:0]
+ 24/30: $2\st_d[2:0]
+ 25/30: $2\inc_txcount[0:0]
+ 26/30: $1\st_d[2:0]
+ 27/30: $1\inc_txcount[0:0]
+ 28/30: $1\shaf_rvalid[0:0]
+ 29/30: $1\sel_data[2:0]
+ 30/30: $1\fifo_rready[0:0]
+Creating decoders for process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:135$1636'.
+ 1/1: $0\st_q[2:0]
+Creating decoders for process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:69$1635'.
+ 1/2: $2\shaf_rdata[31:0]
+ 2/2: $1\shaf_rdata[31:0]
+Creating decoders for process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$1628'.
+Creating decoders for process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:44$1627'.
+Creating decoders for process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$1621'.
+ 1/1: $0\gen_normal_fifo.storage[12:0]
+Creating decoders for process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$1616'.
+ 1/1: $0\gen_normal_fifo.fifo_rptr[1:0]
+Creating decoders for process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$1611'.
+ 1/1: $0\gen_normal_fifo.fifo_wptr[1:0]
+Creating decoders for process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:61$1596'.
+ 1/1: $0\intg_err_q[0:0]
+Creating decoders for process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1211$1509'.
+Creating decoders for process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1075$1508'.
+ 1/6: $1\reg_rdata_next[31:0] [31:9]
+ 2/6: $1\reg_rdata_next[31:0] [3]
+ 3/6: $1\reg_rdata_next[31:0] [2]
+ 4/6: $1\reg_rdata_next[31:0] [0]
+ 5/6: $1\reg_rdata_next[31:0] [8:4]
+ 6/6: $1\reg_rdata_next[31:0] [1]
+Creating decoders for process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:968$1372'.
+Creating decoders for process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:934$1344'.
+Creating decoders for process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:117$1343'.
+ 1/2: $2\reg_steer[0:0]
+ 2/2: $1\reg_steer[0:0]
+Creating decoders for process `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$1259'.
+ 1/1: $0\q_o[0:0]
+Creating decoders for process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:140$1254'.
+ 1/2: $0\txcount[63:0] [63:5]
+ 2/2: $0\txcount[63:0] [4:0]
+Creating decoders for process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+ 1/31: $4\hmac_sha_rvalid[0:0]
+ 2/31: $8\st_d[2:0]
+ 3/31: $3\hash_start[0:0]
+ 4/31: $3\round_d[0:0]
+ 5/31: $3\update_round[0:0]
+ 6/31: $3\clr_txcount[0:0]
+ 7/31: $7\st_d[2:0]
+ 8/31: $6\st_d[2:0]
+ 9/31: $5\st_d[2:0]
+ 10/31: $2\hash_process[0:0]
+ 11/31: $3\hmac_sha_rvalid[0:0]
+ 12/31: $4\st_d[2:0]
+ 13/31: $2\hmac_sha_rvalid[0:0]
+ 14/31: $3\st_d[2:0]
+ 15/31: $2\hash_start[0:0]
+ 16/31: $2\round_d[0:0]
+ 17/31: $2\update_round[0:0]
+ 18/31: $2\clr_txcount[0:0]
+ 19/31: $2\st_d[2:0]
+ 20/31: $1\st_d[2:0]
+ 21/31: $1\round_d[0:0]
+ 22/31: $1\update_round[0:0]
+ 23/31: $1\clr_txcount[0:0]
+ 24/31: $1\hash_start[0:0]
+ 25/31: $1\clr_fifo_wdata_sel[0:0]
+ 26/31: $1\sel_rdata[1:0]
+ 27/31: $1\hmac_sha_rvalid[0:0]
+ 28/31: $1\hmac_hash_done[0:0]
+ 29/31: $1\fifo_wsel[0:0]
+ 30/31: $1\fifo_wvalid[0:0]
+ 31/31: $1\hash_process[0:0]
+Creating decoders for process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:181$1195'.
+ 1/1: $0\st_q[2:0]
+Creating decoders for process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:169$1191'.
+ 1/1: $0\fifo_wdata_sel[2:0]
+Creating decoders for process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:161$1189'.
+ 1/1: $0\round_q[0:0]
+Creating decoders for process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:151$1186'.
+ 1/1: $0\reg_hash_process_flag[0:0]
+Creating decoders for process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:46$1165'.
+ 1/6: $2\fulldata_chk[0:0]
+ 2/6: $2\mask_chk[0:0]
+ 3/6: $2\addr_sz_chk[0:0]
+ 4/6: $1\fulldata_chk[0:0]
+ 5/6: $1\mask_chk[0:0]
+ 6/6: $1\addr_sz_chk[0:0]
+Creating decoders for process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:108$1148'.
+ 1/3: $3\d_valid[0:0]
+ 2/3: $2\d_valid[0:0]
+ 3/3: $1\d_valid[0:0]
+Creating decoders for process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+Creating decoders for process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+ 1/11: $1$fordecl_block29.i[31:0]$968
+ 2/11: $1\wdata_int[31:0]
+ 3/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$949[31:0]$976
+ 4/11: $1\wmask_int[31:0]
+ 5/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$948[31:0]$975
+ 6/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$947[31:0]$974
+ 7/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$946[31:0]$973
+ 8/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$945[31:0]$972
+ 9/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$944[31:0]$971
+ 10/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$943[31:0]$970
+ 11/11: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$942[31:0]$969
+Creating decoders for process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:126$955'.
+ 1/2: $2\d_error[0:0]
+ 2/2: $1\d_error[0:0]
+Creating decoders for process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:125$924'.
+ 1/2: $1$lookahead\gen_normal_fifo.storage$923[575:0]$928
+ 2/2: $1$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:127$897[31:0]$927
+Creating decoders for process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$916'.
+ 1/1: $0\gen_normal_fifo.fifo_rptr[4:0]
+Creating decoders for process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$911'.
+ 1/1: $0\gen_normal_fifo.fifo_wptr[4:0]
+Creating decoders for process `$paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:41$890'.
+ 1/1: $0\intr_o[0:0]
+Creating decoders for process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$883'.
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:50$838'.
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821'.
+ 1/7: $2\flush_done[0:0]
+ 2/7: $2\flush_valid[0:0]
+ 3/7: $3\flush_st_next[0:0]
+ 4/7: $2\flush_st_next[0:0]
+ 5/7: $1\flush_st_next[0:0]
+ 6/7: $1\flush_done[0:0]
+ 7/7: $1\flush_valid[0:0]
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:159$819'.
+ 1/1: $0\flush_st[0:0]
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:138$817'.
+ 1/2: $0\stored_mask[63:0]
+ 2/2: $0\stored_data[63:0]
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:109$816'.
+ 1/2: $1\stored_mask_next[63:0]
+ 2/2: $1\stored_data_next[63:0]
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:85$782'.
+ 1/32: $32\lod_idx[4:0]
+ 2/32: $31\lod_idx[4:0]
+ 3/32: $30\lod_idx[4:0]
+ 4/32: $29\lod_idx[4:0]
+ 5/32: $28\lod_idx[4:0]
+ 6/32: $27\lod_idx[4:0]
+ 7/32: $26\lod_idx[4:0]
+ 8/32: $25\lod_idx[4:0]
+ 9/32: $24\lod_idx[4:0]
+ 10/32: $23\lod_idx[4:0]
+ 11/32: $22\lod_idx[4:0]
+ 12/32: $21\lod_idx[4:0]
+ 13/32: $20\lod_idx[4:0]
+ 14/32: $19\lod_idx[4:0]
+ 15/32: $18\lod_idx[4:0]
+ 16/32: $17\lod_idx[4:0]
+ 17/32: $16\lod_idx[4:0]
+ 18/32: $15\lod_idx[4:0]
+ 19/32: $14\lod_idx[4:0]
+ 20/32: $13\lod_idx[4:0]
+ 21/32: $12\lod_idx[4:0]
+ 22/32: $11\lod_idx[4:0]
+ 23/32: $10\lod_idx[4:0]
+ 24/32: $9\lod_idx[4:0]
+ 25/32: $8\lod_idx[4:0]
+ 26/32: $7\lod_idx[4:0]
+ 27/32: $6\lod_idx[4:0]
+ 28/32: $5\lod_idx[4:0]
+ 29/32: $4\lod_idx[4:0]
+ 30/32: $3\lod_idx[4:0]
+ 31/32: $2\lod_idx[4:0]
+ 32/32: $1\lod_idx[4:0]
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:73$780'.
+ 1/1: $0\pos[6:0]
+Creating decoders for process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:60$772'.
+ 1/1: $1\pos_next[6:0]
+Creating decoders for process `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$770'.
+ 1/1: $0\q_o[0:0]
+Creating decoders for process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$764'.
+ 1/1: $0\gen_normal_fifo.storage[32:0]
+Creating decoders for process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$759'.
+ 1/1: $0\gen_normal_fifo.fifo_rptr[1:0]
+Creating decoders for process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$754'.
+ 1/1: $0\gen_normal_fifo.fifo_wptr[1:0]
+Creating decoders for process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:64$739'.
+ 1/1: $0\outstanding[0:0]
+Creating decoders for process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:120$722'.
+ 1/1: $1\addr_align_err[0:0]
+Creating decoders for process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:83$718'.
+ 1/2: $0\error[0:0]
+ 2/2: $0\rdata[31:0]
+Creating decoders for process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715'.
+ 1/3: $0\rspop[2:0]
+ 2/3: $0\reqsz[1:0]
+ 3/3: $0\reqid[7:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:121$598'.
+ 1/11: $0\secret_key[255:0] [255:224]
+ 2/11: $0\secret_key[255:0] [223:192]
+ 3/11: $0\secret_key[255:0] [191:160]
+ 4/11: $0\secret_key[255:0] [159:128]
+ 5/11: $0\secret_key[255:0] [127:96]
+ 6/11: $0\secret_key[255:0] [95:64]
+ 7/11: $0\secret_key[255:0] [63:32]
+ 8/11: $0\secret_key[255:0] [31:0]
+ 9/11: $2$fordecl_block26.i[31:0]$602
+ 10/11: $1$fordecl_block26.i[31:0]$601
+ 11/11: $3$fordecl_block26.i[31:0]$604
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:555$549'.
+ 1/1: $0\idle_o[0:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:507$548'.
+ 1/1: $1\err_code[31:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:485$537'.
+ 1/10: $9\update_seckey_inprocess[0:0]
+ 2/10: $8\update_seckey_inprocess[0:0]
+ 3/10: $7\update_seckey_inprocess[0:0]
+ 4/10: $6\update_seckey_inprocess[0:0]
+ 5/10: $5\update_seckey_inprocess[0:0]
+ 6/10: $4\update_seckey_inprocess[0:0]
+ 7/10: $3\update_seckey_inprocess[0:0]
+ 8/10: $2\update_seckey_inprocess[0:0]
+ 9/10: $1$fordecl_block28.i[31:0]$539
+ 10/10: $1\update_seckey_inprocess[0:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:328$532'.
+ 1/1: $0\message_length[63:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:320$498'.
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:200$495'.
+ 1/1: $0\fifo_empty_q[0:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:187$493'.
+ 1/1: $0\msg_allowed[0:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:178$489'.
+ 1/1: $0\cfg_reg[7:0]
+Creating decoders for process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:168$487'.
+ 1/1: $0\cfg_block[0:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ 1/96: $5\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$result[31:0]$425
+ 2/96: $5\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum1[31:0]$431
+ 3/96: $5\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.$result[31:0]$442
+ 4/96: $5\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.v[31:0]$443
+ 5/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.$result[31:0]$440
+ 6/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.v[31:0]$441
+ 7/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.$result[31:0]$438
+ 8/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.v[31:0]$439
+ 9/96: $5\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum0[31:0]$430
+ 10/96: $5\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.$result[31:0]$436
+ 11/96: $5\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.v[31:0]$437
+ 12/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.$result[31:0]$434
+ 13/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.v[31:0]$435
+ 14/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.$result[31:0]$432
+ 15/96: $5\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.v[31:0]$433
+ 16/96: $5\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_14[31:0]$429
+ 17/96: $5\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_9[31:0]$428
+ 18/96: $5\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_1[31:0]$427
+ 19/96: $5\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_0[31:0]$426
+ 20/96: $4\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.v[31:0]$424
+ 21/96: $4\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.$result[31:0]$423
+ 22/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.v[31:0]$422
+ 23/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.$result[31:0]$421
+ 24/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.v[31:0]$420
+ 25/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.$result[31:0]$419
+ 26/96: $4\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.v[31:0]$418
+ 27/96: $4\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.$result[31:0]$417
+ 28/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.v[31:0]$416
+ 29/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.$result[31:0]$415
+ 30/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.v[31:0]$414
+ 31/96: $4\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.$result[31:0]$413
+ 32/96: $4\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum1[31:0]$412
+ 33/96: $4\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum0[31:0]$411
+ 34/96: $4\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_14[31:0]$410
+ 35/96: $4\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_9[31:0]$409
+ 36/96: $4\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_1[31:0]$408
+ 37/96: $4\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_0[31:0]$407
+ 38/96: $4\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$result[31:0]$406
+ 39/96: $3\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.v[31:0]$403
+ 40/96: $3\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.$result[31:0]$402
+ 41/96: $3\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.v[31:0]$401
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+ 59/96: $2\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.$result[31:0]$381
+ 60/96: $2\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.v[31:0]$380
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+ 65/96: $2\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.$result[31:0]$375
+ 66/96: $2\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.v[31:0]$374
+ 67/96: $2\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.$result[31:0]$373
+ 68/96: $2\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.v[31:0]$372
+ 69/96: $2\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.$result[31:0]$371
+ 70/96: $2\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum1[31:0]$370
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+ 73/96: $2\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_9[31:0]$367
+ 74/96: $2\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_1[31:0]$366
+ 75/96: $2\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_0[31:0]$365
+ 76/96: $2\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$result[31:0]$364
+ 77/96: $1\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.v[31:0]$363
+ 78/96: $1\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.$result[31:0]$362
+ 79/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.v[31:0]$361
+ 80/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.$result[31:0]$360
+ 81/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.v[31:0]$359
+ 82/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.$result[31:0]$358
+ 83/96: $1\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.v[31:0]$357
+ 84/96: $1\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.$result[31:0]$356
+ 85/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.v[31:0]$355
+ 86/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.$result[31:0]$354
+ 87/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.v[31:0]$353
+ 88/96: $1\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.$result[31:0]$352
+ 89/96: $1\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum1[31:0]$351
+ 90/96: $1\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum0[31:0]$350
+ 91/96: $1\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_14[31:0]$349
+ 92/96: $1\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_9[31:0]$348
+ 93/96: $1\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_1[31:0]$347
+ 94/96: $1\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_0[31:0]$346
+ 95/96: $1\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$result[31:0]$345
+ 96/96: $0\w[511:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+ 1/11: $4\sha_st_d[1:0]
+ 2/11: $3\init_hash[0:0]
+ 3/11: $3\sha_st_d[1:0]
+ 4/11: $2\calculate_next_w[0:0]
+ 5/11: $2\sha_st_d[1:0]
+ 6/11: $2\init_hash[0:0]
+ 7/11: $1\sha_st_d[1:0]
+ 8/11: $1\init_hash[0:0]
+ 9/11: $1\update_digest[0:0]
+ 10/11: $1\run_hash[0:0]
+ 11/11: $1\calculate_next_w[0:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:236$312'.
+ 1/1: $0\sha_st_q[1:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:177$307'.
+ 1/13: $7\fifo_st_d[1:0]
+ 2/13: $2\hash_done_next[0:0]
+ 3/13: $6\fifo_st_d[1:0]
+ 4/13: $4\update_w_from_fifo[0:0]
+ 5/13: $5\fifo_st_d[1:0]
+ 6/13: $3\update_w_from_fifo[0:0]
+ 7/13: $4\fifo_st_d[1:0]
+ 8/13: $2\update_w_from_fifo[0:0]
+ 9/13: $3\fifo_st_d[1:0]
+ 10/13: $2\fifo_st_d[1:0]
+ 11/13: $1\fifo_st_d[1:0]
+ 12/13: $1\hash_done_next[0:0]
+ 13/13: $1\update_w_from_fifo[0:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:169$305'.
+ 1/1: $0\fifo_st_q[1:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:156$303'.
+ 1/1: $0\hash_done[0:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:144$299'.
+ 1/1: $0\w_index[3:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:129$294'.
+ 1/1: $0\round[5:0]
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+ 1/19: $5$fordecl_block40.i[31:0]$285
+ 2/19: $0\digest[31:0] [31:8]
+ 3/19: $3$fordecl_block39.i[31:0]$280
+ 4/19: $3$fordecl_block40.i[31:0]$281
+ 5/19: $2$fordecl_block38.i[31:0]$269
+ 6/19: $0\digest[31:0] [7]
+ 7/19: $0\digest[31:0] [6]
+ 8/19: $0\digest[31:0] [5]
+ 9/19: $0\digest[31:0] [4]
+ 10/19: $0\digest[31:0] [3]
+ 11/19: $0\digest[31:0] [2]
+ 12/19: $0\digest[31:0] [1]
+ 13/19: $0\digest[31:0] [0]
+ 14/19: $4$fordecl_block40.i[31:0]$284
+ 15/19: $2$fordecl_block39.i[31:0]$270
+ 16/19: $1$fordecl_block40.i[31:0]$268
+ 17/19: $1$fordecl_block39.i[31:0]$267
+ 18/19: $1$fordecl_block38.i[31:0]$266
+ 19/19: $2$fordecl_block40.i[31:0]$271
+Creating decoders for process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ 1/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [7]
+ 2/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [0]
+ 3/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [1]
+ 4/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [2]
+ 5/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [3]
+ 6/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [4]
+ 7/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [5]
+ 8/105: $4\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$199 [6]
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+ 99/105: $1\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.sigma_0[31:0]$128
+ 100/105: $1\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.h_i[255:0]$127
+ 101/105: $1\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.k[31:0]$126
+ 102/105: $1\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.w[31:0]$125
+ 103/105: $1\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result[7:0]$124
+ 104/105: $1\compress_round.$fordecl_block37.i[31:0]$123
+ 105/105: $2\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$90.v[31:0]$168
+Creating decoders for process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+ 1/26: $3\alert_clr[0:0]
+ 2/26: $3\ping_clr[0:0]
+ 3/26: $6\alert_n[0:0]
+ 4/26: $6\alert_p[0:0]
+ 5/26: $8\state_d[2:0]
+ 6/26: $5\alert_n[0:0]
+ 7/26: $5\alert_p[0:0]
+ 8/26: $7\state_d[2:0]
+ 9/26: $6\state_d[2:0]
+ 10/26: $2\ping_clr[0:0]
+ 11/26: $5\state_d[2:0]
+ 12/26: $4\alert_n[0:0]
+ 13/26: $4\alert_p[0:0]
+ 14/26: $2\alert_clr[0:0]
+ 15/26: $4\state_d[2:0]
+ 16/26: $3\state_d[2:0]
+ 17/26: $3\alert_n[0:0]
+ 18/26: $3\alert_p[0:0]
+ 19/26: $2\alert_n[0:0]
+ 20/26: $2\alert_p[0:0]
+ 21/26: $2\state_d[2:0]
+ 22/26: $1\alert_n[0:0]
+ 23/26: $1\alert_p[0:0]
+ 24/26: $1\state_d[2:0]
+ 25/26: $1\ping_clr[0:0]
+ 26/26: $1\alert_clr[0:0]
+Creating decoders for process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+ 1/5: $0\ping_set_q[0:0]
+ 2/5: $0\alert_set_q[0:0]
+ 3/5: $0\alert_nq[0:0]
+ 4/5: $0\alert_pq[0:0]
+ 5/5: $0\state_q[2:0]
+Creating decoders for process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$62'.
+ 1/1: $0\gen_normal_fifo.storage[4:0]
+Creating decoders for process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$57'.
+ 1/1: $0\gen_normal_fifo.fifo_rptr[1:0]
+Creating decoders for process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$52'.
+ 1/1: $0\gen_normal_fifo.fifo_wptr[1:0]
+Creating decoders for process `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$37'.
+ 1/1: $0\qe[0:0]
+Creating decoders for process `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$35'.
+ 1/1: $0\q[0:0]
+Creating decoders for process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33'.
+ 1/4: $0\level_q[0:0]
+ 2/4: $0\gen_async.diff_nq[0:0]
+ 3/4: $0\gen_async.diff_pq[0:0]
+ 4/4: $0\gen_async.state_q[1:0]
+Creating decoders for process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+ 1/25: $5\sigint_o[0:0]
+ 2/25: $5\gen_async.state_d[1:0]
+ 3/25: $6\rise_o[0:0]
+ 4/25: $6\fall_o[0:0]
+ 5/25: $5\fall_o[0:0]
+ 6/25: $5\rise_o[0:0]
+ 7/25: $3\level_d[0:0]
+ 8/25: $4\gen_async.state_d[1:0]
+ 9/25: $4\sigint_o[0:0]
+ 10/25: $3\gen_async.state_d[1:0]
+ 11/25: $3\sigint_o[0:0]
+ 12/25: $4\rise_o[0:0]
+ 13/25: $4\fall_o[0:0]
+ 14/25: $3\fall_o[0:0]
+ 15/25: $3\rise_o[0:0]
+ 16/25: $2\fall_o[0:0]
+ 17/25: $2\rise_o[0:0]
+ 18/25: $2\level_d[0:0]
+ 19/25: $2\gen_async.state_d[1:0]
+ 20/25: $2\sigint_o[0:0]
+ 21/25: $1\gen_async.state_d[1:0]
+ 22/25: $1\sigint_o[0:0]
+ 23/25: $1\fall_o[0:0]
+ 24/25: $1\rise_o[0:0]
+ 25/25: $1\level_d[0:0]
+Creating decoders for process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20'.
+ 1/3: $0\err_req_pending[0:0]
+ 2/3: $0\err_size[1:0]
+ 3/3: $0\err_source[7:0]
+Creating decoders for process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:49$9'.
+ 1/1: $0\err_rsp_pending[0:0]
+Creating decoders for process `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$7'.
+ 1/1: $0\qe[0:0]
+Creating decoders for process `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$5'.
+ 1/1: $0\q[0:0]
+Creating decoders for process `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$3'.
+ 1/1: $0\qe[0:0]
+Creating decoders for process `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$1'.
+ 1/1: $0\q[31:0]
+
+3.18.8. Executing PROC_DLATCH pass (convert process syncs to latches).
+No latch inferred for signal `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.\tl_t_p' from process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:154$1946'.
+No latch inferred for signal `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$fordecl_block44.idx' from process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:154$1946'.
+No latch inferred for signal `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.\hfifo_reqready' from process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:142$1942'.
+No latch inferred for signal `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$fordecl_block43.idx' from process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:142$1942'.
+No latch inferred for signal `\prim_secded_inv_39_32_enc.\data_o' from process `\prim_secded_inv_39_32_enc.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_enc.sv:12$1912'.
+No latch inferred for signal `\prim_secded_inv_64_57_enc.\data_o' from process `\prim_secded_inv_64_57_enc.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_enc.sv:12$1890'.
+No latch inferred for signal `\prim_secded_inv_39_32_dec.\data_o' from process `\prim_secded_inv_39_32_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:14$1800'.
+No latch inferred for signal `\prim_secded_inv_39_32_dec.\err_o' from process `\prim_secded_inv_39_32_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:14$1800'.
+No latch inferred for signal `\prim_secded_inv_39_32_dec.\syndrome_o' from process `\prim_secded_inv_39_32_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:14$1800'.
+No latch inferred for signal `\prim_secded_inv_64_57_dec.\data_o' from process `\prim_secded_inv_64_57_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:14$1659'.
+No latch inferred for signal `\prim_secded_inv_64_57_dec.\err_o' from process `\prim_secded_inv_64_57_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:14$1659'.
+No latch inferred for signal `\prim_secded_inv_64_57_dec.\syndrome_o' from process `\prim_secded_inv_64_57_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:14$1659'.
+No latch inferred for signal `\sha2_pad.\shaf_rvalid' from process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+No latch inferred for signal `\sha2_pad.\fifo_rready' from process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+No latch inferred for signal `\sha2_pad.\inc_txcount' from process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+No latch inferred for signal `\sha2_pad.\st_d' from process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+No latch inferred for signal `\sha2_pad.\sel_data' from process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+No latch inferred for signal `\sha2_pad.\shaf_rdata' from process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:69$1635'.
+No latch inferred for signal `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.\tlul_pkg::extract_d2h_rsp_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:23$1624.$result' from process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$1628'.
+No latch inferred for signal `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.\tlul_pkg::extract_d2h_rsp_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:23$1625.$result' from process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$1628'.
+No latch inferred for signal `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.\tlul_pkg::extract_d2h_rsp_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:23$1625.tl' from process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$1628'.
+No latch inferred for signal `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.\tlul_pkg::extract_d2h_rsp_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:23$1625.$unnamed_block$72.payload' from process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$1628'.
+No latch inferred for signal `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.\tlul_pkg::extract_d2h_rsp_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:23$1625.$unnamed_block$72.unused_tlul' from process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$1628'.
+No latch inferred for signal `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.\tl_o' from process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:44$1627'.
+No latch inferred for signal `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.\reg_busy_sel' from process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1211$1509'.
+No latch inferred for signal `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.\reg_rdata_next' from process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1075$1508'.
+No latch inferred for signal `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.\wr_err' from process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:968$1372'.
+No latch inferred for signal `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.\addr_hit' from process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:934$1344'.
+No latch inferred for signal `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.\reg_steer' from process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:117$1343'.
+No latch inferred for signal `\hmac_core.\hash_start' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\hash_process' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\fifo_wvalid' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\fifo_wsel' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\hmac_hash_done' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\clr_txcount' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\hmac_sha_rvalid' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\sel_rdata' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\update_round' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\round_d' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\st_d' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `\hmac_core.\clr_fifo_wdata_sel' from process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.\addr_sz_chk' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:46$1165'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.\mask_chk' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:46$1165'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.\fulldata_chk' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:46$1165'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.\d_valid' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:108$1148'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.\rmask' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$fordecl_block30.i' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:254$950' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:254$951' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:254$952' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:254$953' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.\wmask_int' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.\wdata_int' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$fordecl_block29.i' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$942' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$943' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$944' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$945' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$946' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$947' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:186$948' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$949' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+No latch inferred for signal `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.\d_error' from process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:126$955'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.\tlul_pkg::extract_h2d_cmd_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:14$872.$result' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$883'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.\tlul_pkg::extract_h2d_cmd_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:14$873.$result' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$883'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.\tlul_pkg::extract_h2d_cmd_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:14$873.tl' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$883'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.\tlul_pkg::extract_h2d_cmd_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:14$873.$unnamed_block$71.payload' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$883'.
+No latch inferred for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.\tlul_pkg::extract_h2d_cmd_intg$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_cmd_intg_chk.sv:14$873.$unnamed_block$71.unused_tlul' from process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$883'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\inmask_ones' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:50$838'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$fordecl_block31.i' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:50$838'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\flush_valid' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\flush_done' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\flush_st_next' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\stored_data_next' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:109$816'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\stored_mask_next' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:109$816'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\lod_idx' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:85$782'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$fordecl_block32.i' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:85$782'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\pos_next' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:60$772'.
+No latch inferred for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\pos_with_input' from process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:60$772'.
+No latch inferred for signal `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.\addr_align_err' from process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:120$722'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$475.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$486.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$486.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$486.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$486.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$486.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$486.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:350$486.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$474.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$485.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$485.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$485.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$485.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$485.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$485.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:349$485.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:261$473.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:261$484.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:261$484.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:261$484.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:261$484.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:261$484.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:261$484.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$472.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$483.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$483.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$483.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$483.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$483.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$483.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$483.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$471.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$482.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$482.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$482.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$482.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$482.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$482.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$482.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$470.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$481.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$481.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$481.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$481.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$481.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$481.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$481.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$469.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$480.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$480.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$480.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$480.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$480.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$480.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$480.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$468.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$479.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$479.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$479.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$479.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$479.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$479.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$479.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$467.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$478.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$478.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$478.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$478.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$478.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$478.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$478.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$466.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$477.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$477.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$477.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$477.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$477.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$477.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$477.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$465.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$476.$result' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$476.v' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$476.swap' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$476.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_src' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$476.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_dst' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$476.$systemverilog_plugin$stream_op_23_impl.$systemverilog_plugin$stream_op_23_counter' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\hmac_pkg::conv_endian$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:139$476.$unnamed_block$67.conv_data' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+No latch inferred for signal `\hmac.\err_code' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:507$548'.
+No latch inferred for signal `\hmac.\update_seckey_inprocess' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:485$537'.
+No latch inferred for signal `\hmac.$fordecl_block28.i' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:485$537'.
+No latch inferred for signal `\hmac.\wmask_ones' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:320$498'.
+No latch inferred for signal `\hmac.$fordecl_block27.i' from process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:320$498'.
+No latch inferred for signal `\sha2.\calculate_next_w' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+No latch inferred for signal `\sha2.\init_hash' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+No latch inferred for signal `\sha2.\run_hash' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+No latch inferred for signal `\sha2.\update_digest' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+No latch inferred for signal `\sha2.\sha_st_d' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+No latch inferred for signal `\sha2.\update_w_from_fifo' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:177$307'.
+No latch inferred for signal `\sha2.\hash_done_next' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:177$307'.
+No latch inferred for signal `\sha2.\fifo_st_d' from process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:177$307'.
+No latch inferred for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\state_d' from process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+No latch inferred for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\alert_p' from process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+No latch inferred for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\alert_n' from process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+No latch inferred for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\alert_clr' from process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+No latch inferred for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\ping_clr' from process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+No latch inferred for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\level_d' from process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+No latch inferred for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\rise_o' from process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+No latch inferred for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\fall_o' from process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+No latch inferred for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\sigint_o' from process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+No latch inferred for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\gen_async.state_d' from process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+
+3.18.9. Executing PROC_DFF pass (convert process syncs to FFs).
+Creating register for signal `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.\num_req_outstanding' using process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:100$1960'.
+ created $adff cell `$procdff$5309' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.\dev_select_outstanding' using process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:100$1960'.
+ created $adff cell `$procdff$5310' with positive edge clock and negative level reset.
+Creating register for signal `\sha2_pad.\hash_process_flag' using process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:49$1656'.
+ created $adff cell `$procdff$5311' with positive edge clock and negative level reset.
+Creating register for signal `\sha2_pad.\tx_count' using process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:298$1648'.
+ created $adff cell `$procdff$5312' with positive edge clock and negative level reset.
+Creating register for signal `\sha2_pad.\st_q' using process `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:135$1636'.
+ created $adff cell `$procdff$5313' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.\gen_normal_fifo.storage' using process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$1621'.
+ created $dff cell `$procdff$5314' with positive edge clock.
+Creating register for signal `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.\gen_normal_fifo.fifo_rptr' using process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$1616'.
+ created $adff cell `$procdff$5315' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.\gen_normal_fifo.fifo_wptr' using process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$1611'.
+ created $adff cell `$procdff$5316' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.\intg_err_q' using process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:61$1596'.
+ created $adff cell `$procdff$5317' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.\q_o' using process `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$1259'.
+ created $adff cell `$procdff$5318' with positive edge clock and negative level reset.
+Creating register for signal `\hmac_core.\txcount' using process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:140$1254'.
+ created $adff cell `$procdff$5319' with positive edge clock and negative level reset.
+Creating register for signal `\hmac_core.\st_q' using process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:181$1195'.
+ created $adff cell `$procdff$5320' with positive edge clock and negative level reset.
+Creating register for signal `\hmac_core.\fifo_wdata_sel' using process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:169$1191'.
+ created $adff cell `$procdff$5321' with positive edge clock and negative level reset.
+Creating register for signal `\hmac_core.\round_q' using process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:161$1189'.
+ created $adff cell `$procdff$5322' with positive edge clock and negative level reset.
+Creating register for signal `\hmac_core.\reg_hash_process_flag' using process `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:151$1186'.
+ created $adff cell `$procdff$5323' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.\gen_normal_fifo.storage' using process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:125$924'.
+ created $dff cell `$procdff$5324' with positive edge clock.
+Creating register for signal `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:127$897' using process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:125$924'.
+ created $dff cell `$procdff$5325' with positive edge clock.
+Creating register for signal `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$lookahead\gen_normal_fifo.storage$923' using process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:125$924'.
+ created $dff cell `$procdff$5326' with positive edge clock.
+Creating register for signal `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.\gen_normal_fifo.fifo_rptr' using process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$916'.
+ created $adff cell `$procdff$5327' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.\gen_normal_fifo.fifo_wptr' using process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$911'.
+ created $adff cell `$procdff$5328' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.\intr_o' using process `$paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:41$890'.
+ created $adff cell `$procdff$5329' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\flush_st' using process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:159$819'.
+ created $adff cell `$procdff$5330' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\stored_data' using process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:138$817'.
+ created $adff cell `$procdff$5331' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\stored_mask' using process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:138$817'.
+ created $adff cell `$procdff$5332' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.\pos' using process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:73$780'.
+ created $adff cell `$procdff$5333' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.\q_o' using process `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$770'.
+ created $adff cell `$procdff$5334' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.\gen_normal_fifo.storage' using process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$764'.
+ created $dff cell `$procdff$5335' with positive edge clock.
+Creating register for signal `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.\gen_normal_fifo.fifo_rptr' using process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$759'.
+ created $adff cell `$procdff$5336' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.\gen_normal_fifo.fifo_wptr' using process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$754'.
+ created $adff cell `$procdff$5337' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.\outstanding' using process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:64$739'.
+ created $adff cell `$procdff$5338' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.\rdata' using process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:83$718'.
+ created $adff cell `$procdff$5339' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.\error' using process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:83$718'.
+ created $adff cell `$procdff$5340' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.\reqid' using process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715'.
+ created $adff cell `$procdff$5341' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.\reqsz' using process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715'.
+ created $adff cell `$procdff$5342' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.\rspop' using process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715'.
+ created $adff cell `$procdff$5343' with positive edge clock and negative level reset.
+Creating register for signal `\hmac.\secret_key' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:121$598'.
+ created $adff cell `$procdff$5344' with positive edge clock and negative level reset.
+Creating register for signal `\hmac.$fordecl_block26.i' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:121$598'.
+ created $dff cell `$procdff$5347' with positive edge clock.
+Creating register for signal `\hmac.\idle_o' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:555$549'.
+ created $adff cell `$procdff$5348' with positive edge clock and negative level reset.
+Creating register for signal `\hmac.\message_length' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:328$532'.
+ created $adff cell `$procdff$5349' with positive edge clock and negative level reset.
+Creating register for signal `\hmac.\fifo_empty_q' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:200$495'.
+ created $adff cell `$procdff$5350' with positive edge clock and negative level reset.
+Creating register for signal `\hmac.\msg_allowed' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:187$493'.
+ created $adff cell `$procdff$5351' with positive edge clock and negative level reset.
+Creating register for signal `\hmac.\cfg_reg' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:178$489'.
+ created $adff cell `$procdff$5352' with positive edge clock and negative level reset.
+Creating register for signal `\hmac.\cfg_block' using process `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:168$487'.
+ created $adff cell `$procdff$5353' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\w' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5354' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5355' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_0' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5356' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_1' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5357' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_9' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5358' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.w_14' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5359' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum0' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $dff cell `$procdff$5362' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::calc_w$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:68$91.$unnamed_block$69.sum1' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $dff cell `$procdff$5365' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5366' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$92.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5367' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5368' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$93.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5369' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5370' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$94.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5371' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5372' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$95.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5373' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5374' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$96.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5375' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5376' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::shiftr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$97.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+ created $adff cell `$procdff$5377' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\sha_st_q' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:236$312'.
+ created $adff cell `$procdff$5378' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\fifo_st_q' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:169$305'.
+ created $adff cell `$procdff$5379' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hash_done' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:156$303'.
+ created $adff cell `$procdff$5380' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\w_index' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:144$299'.
+ created $adff cell `$procdff$5381' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\round' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:129$294'.
+ created $adff cell `$procdff$5382' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\digest' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+ created $adff cell `$procdff$5383' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.$fordecl_block38.i' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+ created $dff cell `$procdff$5386' with positive edge clock.
+Creating register for signal `\sha2.$fordecl_block39.i' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+ created $dff cell `$procdff$5389' with positive edge clock.
+Creating register for signal `\sha2.$fordecl_block40.i' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+ created $dff cell `$procdff$5392' with positive edge clock.
+Creating register for signal `\sha2.\hash' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5393' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\compress_round.$fordecl_block37.i' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $dff cell `$procdff$5396' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5397' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.w' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5398' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.k' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5399' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.h_i' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5400' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.sigma_0' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $dff cell `$procdff$5403' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.sigma_1' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $dff cell `$procdff$5406' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.ch' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $dff cell `$procdff$5409' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.maj' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $dff cell `$procdff$5412' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.temp1' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $dff cell `$procdff$5415' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::compress$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:103$84.$unnamed_block$68.temp2' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $dff cell `$procdff$5418' with positive edge clock.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$85.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5419' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$85.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5420' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$86.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5421' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$86.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5422' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$87.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5423' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$87.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5424' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$88.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5425' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$88.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5426' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$89.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5427' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$89.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5428' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$90.$result' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5429' with positive edge clock and negative level reset.
+Creating register for signal `\sha2.\hmac_pkg::rotr$func$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$90.v' using process `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+ created $adff cell `$procdff$5430' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\state_q' using process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+ created $adff cell `$procdff$5431' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\alert_pq' using process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+ created $adff cell `$procdff$5432' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\alert_nq' using process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+ created $adff cell `$procdff$5433' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\alert_set_q' using process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+ created $adff cell `$procdff$5434' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.\ping_set_q' using process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+ created $adff cell `$procdff$5435' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.\gen_normal_fifo.storage' using process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$62'.
+ created $dff cell `$procdff$5436' with positive edge clock.
+Creating register for signal `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.\gen_normal_fifo.fifo_rptr' using process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$57'.
+ created $adff cell `$procdff$5437' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.\gen_normal_fifo.fifo_wptr' using process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$52'.
+ created $adff cell `$procdff$5438' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.\qe' using process `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$37'.
+ created $adff cell `$procdff$5439' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.\q' using process `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$35'.
+ created $adff cell `$procdff$5440' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\level_q' using process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33'.
+ created $adff cell `$procdff$5441' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\gen_async.state_q' using process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33'.
+ created $adff cell `$procdff$5442' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\gen_async.diff_pq' using process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33'.
+ created $adff cell `$procdff$5443' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\prim_diff_decode\AsyncOn=1'1.\gen_async.diff_nq' using process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33'.
+ created $adff cell `$procdff$5444' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.\err_source' using process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20'.
+ created $dff cell `$procdff$5447' with positive edge clock.
+Creating register for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.\err_size' using process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20'.
+ created $adff cell `$procdff$5448' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.\err_req_pending' using process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20'.
+ created $adff cell `$procdff$5449' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.\err_rsp_pending' using process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:49$9'.
+ created $adff cell `$procdff$5450' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.\qe' using process `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$7'.
+ created $adff cell `$procdff$5451' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.\q' using process `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$5'.
+ created $adff cell `$procdff$5452' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.\qe' using process `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$3'.
+ created $adff cell `$procdff$5453' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.\q' using process `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$1'.
+ created $adff cell `$procdff$5454' with positive edge clock and negative level reset.
+
+3.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
+
+3.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Found and cleaned up 3 empty switches in `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:100$1960'.
+Removing empty process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:100$1960'.
+Found and cleaned up 2 empty switches in `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:154$1946'.
+Removing empty process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:154$1946'.
+Found and cleaned up 3 empty switches in `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:142$1942'.
+Removing empty process `$paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:142$1942'.
+Removing empty process `prim_secded_inv_39_32_enc.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_enc.sv:12$1912'.
+Removing empty process `prim_secded_inv_64_57_enc.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_enc.sv:12$1890'.
+Removing empty process `prim_secded_inv_39_32_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:14$1800'.
+Removing empty process `prim_secded_inv_64_57_dec.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_64_57_dec.sv:14$1659'.
+Found and cleaned up 2 empty switches in `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:49$1656'.
+Removing empty process `sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:49$1656'.
+Found and cleaned up 2 empty switches in `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:298$1648'.
+Removing empty process `sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:298$1648'.
+Found and cleaned up 11 empty switches in `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+Removing empty process `sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:144$1638'.
+Removing empty process `sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:135$1636'.
+Found and cleaned up 2 empty switches in `\sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:69$1635'.
+Removing empty process `sha2_pad.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:69$1635'.
+Removing empty process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$1628'.
+Removing empty process `$paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_rsp_intg_gen.sv:44$1627'.
+Found and cleaned up 1 empty switch in `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$1621'.
+Removing empty process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$1621'.
+Found and cleaned up 3 empty switches in `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$1616'.
+Removing empty process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$1616'.
+Found and cleaned up 3 empty switches in `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$1611'.
+Removing empty process `$paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$1611'.
+Found and cleaned up 1 empty switch in `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:61$1596'.
+Removing empty process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:61$1596'.
+Removing empty process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1211$1509'.
+Found and cleaned up 1 empty switch in `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1075$1508'.
+Removing empty process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:1075$1508'.
+Removing empty process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:968$1372'.
+Removing empty process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:934$1344'.
+Found and cleaned up 2 empty switches in `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:117$1343'.
+Removing empty process `$paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:117$1343'.
+Removing empty process `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$1259'.
+Found and cleaned up 2 empty switches in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:140$1254'.
+Removing empty process `hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:140$1254'.
+Found and cleaned up 8 empty switches in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+Removing empty process `hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:186$1197'.
+Removing empty process `hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:181$1195'.
+Found and cleaned up 2 empty switches in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:169$1191'.
+Removing empty process `hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:169$1191'.
+Found and cleaned up 1 empty switch in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:161$1189'.
+Removing empty process `hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:161$1189'.
+Found and cleaned up 2 empty switches in `\hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:151$1186'.
+Removing empty process `hmac_core.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:151$1186'.
+Found and cleaned up 2 empty switches in `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:46$1165'.
+Removing empty process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:46$1165'.
+Found and cleaned up 3 empty switches in `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:108$1148'.
+Removing empty process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:108$1148'.
+Removing empty process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:251$1061'.
+Found and cleaned up 1 empty switch in `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+Removing empty process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:180$958'.
+Found and cleaned up 2 empty switches in `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:126$955'.
+Removing empty process `$paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:126$955'.
+Found and cleaned up 1 empty switch in `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:125$924'.
+Removing empty process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:125$924'.
+Found and cleaned up 3 empty switches in `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$916'.
+Removing empty process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$916'.
+Found and cleaned up 3 empty switches in `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$911'.
+Removing empty process `$paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$911'.
+Removing empty process `$paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_intr_hw.sv:41$890'.
+Removing empty process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_pkg.sv:0$883'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:50$838'.
+Found and cleaned up 3 empty switches in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:167$821'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:159$819'.
+Found and cleaned up 1 empty switch in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:138$817'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:138$817'.
+Found and cleaned up 1 empty switch in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:109$816'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:109$816'.
+Found and cleaned up 32 empty switches in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:85$782'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:85$782'.
+Found and cleaned up 1 empty switch in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:73$780'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:73$780'.
+Found and cleaned up 1 empty switch in `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:60$772'.
+Removing empty process `$paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:60$772'.
+Removing empty process `$paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_generic_flop.sv:18$770'.
+Found and cleaned up 1 empty switch in `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$764'.
+Removing empty process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$764'.
+Found and cleaned up 3 empty switches in `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$759'.
+Removing empty process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$759'.
+Found and cleaned up 3 empty switches in `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$754'.
+Removing empty process `$paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$754'.
+Found and cleaned up 2 empty switches in `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:64$739'.
+Removing empty process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:64$739'.
+Found and cleaned up 1 empty switch in `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:120$722'.
+Removing empty process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:120$722'.
+Found and cleaned up 1 empty switch in `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:83$718'.
+Removing empty process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:83$718'.
+Found and cleaned up 1 empty switch in `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715'.
+Removing empty process `$paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:70$715'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$704'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$693'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$685'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$675'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$665'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$655'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$645'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$635'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$625'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$615'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$605'.
+Found and cleaned up 10 empty switches in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:121$598'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:121$598'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:555$549'.
+Found and cleaned up 1 empty switch in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:507$548'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:507$548'.
+Found and cleaned up 9 empty switches in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:485$537'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:485$537'.
+Found and cleaned up 2 empty switches in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:328$532'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:328$532'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:320$498'.
+Found and cleaned up 1 empty switch in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:200$495'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:200$495'.
+Found and cleaned up 2 empty switches in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:187$493'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:187$493'.
+Found and cleaned up 1 empty switch in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:178$489'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:178$489'.
+Found and cleaned up 2 empty switches in `\hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:168$487'.
+Removing empty process `hmac.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:168$487'.
+Found and cleaned up 5 empty switches in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:57$324'.
+Found and cleaned up 5 empty switches in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:246$314'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:236$312'.
+Found and cleaned up 7 empty switches in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:177$307'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:177$307'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:169$305'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:156$303'.
+Found and cleaned up 2 empty switches in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:144$299'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:144$299'.
+Found and cleaned up 3 empty switches in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:129$294'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:129$294'.
+Found and cleaned up 4 empty switches in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:108$261'.
+Found and cleaned up 3 empty switches in `\sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+Removing empty process `sha2.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:93$98'.
+Found and cleaned up 8 empty switches in `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+Removing empty process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:127$72'.
+Removing empty process `$paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:222$65'.
+Found and cleaned up 1 empty switch in `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$62'.
+Removing empty process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:117$62'.
+Found and cleaned up 3 empty switches in `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$57'.
+Removing empty process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:92$57'.
+Found and cleaned up 3 empty switches in `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$52'.
+Removing empty process `$paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:78$52'.
+Removing empty process `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$37'.
+Found and cleaned up 1 empty switch in `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$35'.
+Removing empty process `$paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$35'.
+Removing empty process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:161$33'.
+Found and cleaned up 8 empty switches in `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+Removing empty process `$paramod\prim_diff_decode\AsyncOn=1'1.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_diff_decode.sv:106$30'.
+Found and cleaned up 2 empty switches in `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20'.
+Removing empty process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:20$20'.
+Found and cleaned up 1 empty switch in `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:49$9'.
+Removing empty process `$paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err_resp.sv:49$9'.
+Removing empty process `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$7'.
+Found and cleaned up 1 empty switch in `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$5'.
+Removing empty process `$paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$5'.
+Removing empty process `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:65$3'.
+Found and cleaned up 1 empty switch in `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$1'.
+Removing empty process `$paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.$proc$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_subreg.sv:70$1'.
+Cleaned up 203 empty switches.
+
+3.18.12. Executing OPT_EXPR pass (perform const folding).
+Optimizing module $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.
+
+Optimizing module prim_secded_inv_39_32_enc.
+
+Optimizing module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc.
+Optimizing module $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync.
+Optimizing module prim_secded_inv_64_57_enc.
+
+Optimizing module prim_generic_buf.
+Optimizing module prim_secded_inv_39_32_dec.
+
+Optimizing module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec.
+Optimizing module $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync.
+Optimizing module prim_secded_inv_64_57_dec.
+
+Optimizing module sha2_pad.
+
+Optimizing module $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.
+Optimizing module $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.
+
+Optimizing module $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.
+
+Optimizing module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Optimizing module $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync.
+Optimizing module hmac_core.
+
+Optimizing module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.
+
+Optimizing module $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.
+
+Optimizing module $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.
+
+Optimizing module $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.
+
+Optimizing module $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync.
+Optimizing module $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Optimizing module $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Optimizing module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.
+
+Optimizing module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+
+Optimizing module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Optimizing module $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.
+
+Optimizing module $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.
+
+Optimizing module $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Optimizing module hmac.
+
+Optimizing module $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Optimizing module sha2.
+
+Optimizing module $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.
+
+Optimizing module $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.
+
+Optimizing module $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.
+Optimizing module $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf.
+Optimizing module $paramod\prim_diff_decode\AsyncOn=1'1.
+
+Optimizing module $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync.
+Optimizing module $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync.
+Optimizing module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.
+
+Optimizing module $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.
+Optimizing module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001.
+Optimizing module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101.
+Optimizing module $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.
+Optimizing module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000.
+
+3.19. Executing FLATTEN pass (flatten design).
+Deleting now unused module $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.
+Deleting now unused module prim_secded_inv_39_32_enc.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc.
+Deleting now unused module $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync.
+Deleting now unused module prim_secded_inv_64_57_enc.
+Deleting now unused module prim_generic_buf.
+Deleting now unused module prim_secded_inv_39_32_dec.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec.
+Deleting now unused module $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync.
+Deleting now unused module prim_secded_inv_64_57_dec.
+Deleting now unused module sha2_pad.
+Deleting now unused module $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.
+Deleting now unused module $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.
+Deleting now unused module $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.
+Deleting now unused module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Deleting now unused module $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync.
+Deleting now unused module hmac_core.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.
+Deleting now unused module $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.
+Deleting now unused module $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.
+Deleting now unused module $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.
+Deleting now unused module $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync.
+Deleting now unused module $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Deleting now unused module $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.
+Deleting now unused module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Deleting now unused module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Deleting now unused module $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.
+Deleting now unused module $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.
+Deleting now unused module $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Deleting now unused module $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Deleting now unused module sha2.
+Deleting now unused module $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.
+Deleting now unused module $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.
+Deleting now unused module $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.
+Deleting now unused module $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf.
+Deleting now unused module $paramod\prim_diff_decode\AsyncOn=1'1.
+Deleting now unused module $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync.
+Deleting now unused module $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.
+Deleting now unused module $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.
+Deleting now unused module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001.
+Deleting now unused module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101.
+Deleting now unused module $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.
+Deleting now unused module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000.
+
+
+# --------------------
+# Design entry stats
+# --------------------
+
+3.20. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 6096
+ Number of wire bits: 85823
+ Number of public wires: 1354
+ Number of public wire bits: 23810
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 1
+ Number of memory bits: 4096
+ Number of processes: 0
+ Number of cells: 2866
+ $add 109
+ $adff 122
+ $and 173
+ $dff 20
+ $eq 376
+ $ge 2
+ $le 3
+ $logic_and 39
+ $logic_not 221
+ $logic_or 14
+ $lt 1
+ $meminit 1
+ $memrd_v2 1
+ $mul 11
+ $mux 1159
+ $ne 4
+ $neg 10
+ $not 125
+ $or 84
+ $pmux 45
+ $pos 6
+ $reduce_and 7
+ $reduce_bool 1
+ $reduce_or 39
+ $reduce_xor 36
+ $scopeinfo 97
+ $shift 10
+ $shiftx 6
+ $shl 4
+ $shr 2
+ $sub 15
+ $xor 123
+
+3.21. Executing SPLITNETS pass (splitting up multi-bit signals).
+
+3.22. Executing DEMUXMAP pass.
+
+3.23. Executing FLATTEN pass (flatten design).
+Deleting now unused module $paramod$0ca40f70ac157be591cab1b81fbd0ed0db30740c\prim_fifo_sync.
+Deleting now unused module $paramod$112511bfd0dccda09976f1ed3a15d1c8d45112d4\prim_subreg.
+Deleting now unused module $paramod$157fd562ecf13236aab0b57a331ba1b94345c11d\prim_fifo_sync.
+Deleting now unused module $paramod$217480d2e7c11d9b96d120d7f565527fe601dc7f\prim_alert_sender.
+Deleting now unused module $paramod$26c36588d7cd5e046d98cae672f77bb080bea490\prim_packer.
+Deleting now unused module $paramod$30daef7d8fbea83f8d5d97bb6bbeea8d50f20643\tlul_rsp_intg_gen.
+Deleting now unused module $paramod$359adca73dcd81f0552b66c47c75294bc7b56f34\hmac_reg_top.
+Deleting now unused module $paramod$3e908b141748daaa08b8f162b36c8ea468ecf397\tlul_socket_1n.
+Deleting now unused module $paramod$58742bab91a003d79034aeb644264cbb951eb306\prim_fifo_sync.
+Deleting now unused module $paramod$646fa55f9b7bebcb5be2033e8c08591be734ddee\prim_fifo_sync.
+Deleting now unused module $paramod$7e00d363ce130de0a5a3e36d8a0ef795833e2889\prim_subreg.
+Deleting now unused module $paramod$8c366539076fe5d51a273a0a2b1698a0634ec537\tlul_fifo_sync.
+Deleting now unused module $paramod$91b42a8809de2239ea0cf37c85a35692b6ed4dcf\prim_fifo_sync.
+Deleting now unused module $paramod$9b7eddd844f049f428a23c54f0552bbba31ef5fa\prim_fifo_sync.
+Deleting now unused module $paramod$a15eb3e9e7e337a1d68c13676510cc99e563cdd3\prim_buf.
+Deleting now unused module $paramod$a9aa73aa526544e7a2302187398f020bb72745f4\tlul_adapter_sram.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_cmd_intg_chk.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_dec.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_data_integ_enc.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err.
+Deleting now unused module $paramod$b16ec1a2d37bb01b30b4807f6e7e5972c818c2d7\tlul_err_resp.
+Deleting now unused module $paramod$b652f3dfdeef7584c496ced680b0643f32807516\tlul_adapter_reg.
+Deleting now unused module $paramod$c36fe4046aa9692da69c6a66dd2bb071f66f76b7\prim_fifo_sync.
+Deleting now unused module $paramod$d5239cbf0f9f81968e5a1c94a3dd59e367f6fe56\tlul_fifo_sync.
+Deleting now unused module $paramod$ea92c57bef3f40a89a443343a492a179dbf37ad4\prim_subreg.
+Deleting now unused module $paramod$f519e51f824927b1da80ae7de12f65225cc31206\prim_fifo_sync.
+Deleting now unused module $paramod\prim_diff_decode\AsyncOn=1'1.
+Deleting now unused module $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Deleting now unused module $paramod\prim_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Deleting now unused module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Deleting now unused module $paramod\prim_generic_flop\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Deleting now unused module $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'0.
+Deleting now unused module $paramod\prim_generic_flop_2sync\Width=s32'00000000000000000000000000000001\ResetValue=1'1.
+Deleting now unused module $paramod\prim_intr_hw\Width=32'00000000000000000000000000000001\FlopOutput=1'1.
+Deleting now unused module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000001.
+Deleting now unused module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000000101.
+Deleting now unused module $paramod\prim_subreg_ext\DW=32'00000000000000000000000000100000.
+Deleting now unused module hmac_core.
+Deleting now unused module prim_generic_buf.
+Deleting now unused module prim_secded_inv_39_32_dec.
+Deleting now unused module prim_secded_inv_39_32_enc.
+Deleting now unused module prim_secded_inv_64_57_dec.
+Deleting now unused module prim_secded_inv_64_57_enc.
+Deleting now unused module sha2.
+Deleting now unused module sha2_pad.
+
+
+3.24. Executing DEMUXMAP pass.
+
+3.25. Executing TRIBUF pass.
+Warning: Ignored -no_iobuf because -keep_tribuf is used.
+
+3.26. Executing DEMINOUT pass (demote inout ports to input or output).
+
+3.27. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+
+3.28. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 851 unused cells and 3473 unused wires.
+
+
+3.29. Executing CHECK pass (checking for obvious problems).
+Checking module hmac...
+Found and reported 0 problems.
+
+3.30. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 2623
+ Number of wire bits: 37350
+ Number of public wires: 1135
+ Number of public wire bits: 19171
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 1
+ Number of memory bits: 4096
+ Number of processes: 0
+ Number of cells: 1964
+ $add 102
+ $adff 79
+ $and 143
+ $dff 5
+ $eq 274
+ $ge 2
+ $le 3
+ $logic_and 38
+ $logic_not 105
+ $logic_or 13
+ $lt 1
+ $meminit 1
+ $memrd_v2 1
+ $mul 2
+ $mux 720
+ $ne 4
+ $neg 9
+ $not 101
+ $or 82
+ $pmux 42
+ $reduce_and 7
+ $reduce_bool 1
+ $reduce_or 38
+ $reduce_xor 30
+ $scopeinfo 97
+ $shift 9
+ $shiftx 6
+ $shl 4
+ $shr 2
+ $sub 9
+ $xor 34
+
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procdff$5431 ($adff): \gen_alert_tx[0].u_prim_alert_sender.state_q = 3'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procdff$5432 ($adff): \gen_alert_tx[0].u_prim_alert_sender.alert_pq = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procdff$5433 ($adff): \gen_alert_tx[0].u_prim_alert_sender.alert_nq = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procdff$5434 ($adff): \gen_alert_tx[0].u_prim_alert_sender.alert_set_q = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procdff$5435 ($adff): \gen_alert_tx[0].u_prim_alert_sender.ping_set_q = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procdff$5441 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.level_q = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procdff$5442 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.state_q = 2'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procdff$5443 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.diff_pq = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procdff$5444 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.diff_nq = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.\gen_async.i_sync_n.\gen_generic.u_impl_generic.\u_sync_1.$procdff$5318 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_n.gen_generic.u_impl_generic.u_sync_1.q_o = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.\gen_async.i_sync_n.\gen_generic.u_impl_generic.\u_sync_2.$procdff$5318 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_n.gen_generic.u_impl_generic.u_sync_2.q_o = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.\gen_async.i_sync_p.\gen_generic.u_impl_generic.\u_sync_1.$procdff$5334 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_p.gen_generic.u_impl_generic.u_sync_1.q_o = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.\gen_async.i_sync_p.\gen_generic.u_impl_generic.\u_sync_2.$procdff$5334 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.i_sync_p.gen_generic.u_impl_generic.u_sync_2.q_o = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procdff$5442 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.state_q = 2'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procdff$5443 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.diff_pq = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procdff$5444 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.diff_nq = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.\gen_async.i_sync_n.\gen_generic.u_impl_generic.\u_sync_1.$procdff$5318 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_n.gen_generic.u_impl_generic.u_sync_1.q_o = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.\gen_async.i_sync_n.\gen_generic.u_impl_generic.\u_sync_2.$procdff$5318 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_n.gen_generic.u_impl_generic.u_sync_2.q_o = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.\gen_async.i_sync_p.\gen_generic.u_impl_generic.\u_sync_1.$procdff$5334 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic.u_sync_1.q_o = 1'x
+FF init value for cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.\gen_async.i_sync_p.\gen_generic.u_impl_generic.\u_sync_2.$procdff$5334 ($adff): \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic.u_sync_2.q_o = 1'x
+FF init value for cell $flatten\intr_hw_fifo_empty.$procdff$5329 ($adff): \intr_hw_fifo_empty.intr_o = 1'x
+FF init value for cell $flatten\intr_hw_hmac_done.$procdff$5329 ($adff): \intr_hw_hmac_done.intr_o = 1'x
+FF init value for cell $flatten\intr_hw_hmac_err.$procdff$5329 ($adff): \intr_hw_hmac_err.intr_o = 1'x
+FF init value for cell $flatten\u_hmac.$procdff$5319 ($adff): \u_hmac.txcount = 64'x
+FF init value for cell $flatten\u_hmac.$procdff$5320 ($adff): \u_hmac.st_q = 3'x
+FF init value for cell $flatten\u_hmac.$procdff$5321 ($adff): \u_hmac.fifo_wdata_sel = 3'x
+FF init value for cell $flatten\u_hmac.$procdff$5322 ($adff): \u_hmac.round_q = 1'x
+FF init value for cell $flatten\u_hmac.$procdff$5323 ($adff): \u_hmac.reg_hash_process_flag = 1'x
+FF init value for cell $flatten\u_msg_fifo.$procdff$5324 ($dff): \u_msg_fifo.gen_normal_fifo.storage = 576'x
+FF init value for cell $flatten\u_msg_fifo.$procdff$5327 ($adff): \u_msg_fifo.gen_normal_fifo.fifo_rptr = 5'x
+FF init value for cell $flatten\u_msg_fifo.$procdff$5328 ($adff): \u_msg_fifo.gen_normal_fifo.fifo_wptr = 5'x
+FF init value for cell $flatten\u_packer.$procdff$5330 ($adff): \u_packer.flush_st = 1'x
+FF init value for cell $flatten\u_packer.$procdff$5331 ($adff): \u_packer.stored_data = 64'x
+FF init value for cell $flatten\u_packer.$procdff$5332 ($adff): \u_packer.stored_mask = 64'x
+FF init value for cell $flatten\u_packer.$procdff$5333 ($adff): \u_packer.pos = 7'x
+FF init value for cell $flatten\u_reg.$procdff$5317 ($adff): \u_reg.intg_err_q = 1'x
+FF init value for cell $flatten\u_reg.\u_err_code.$procdff$5454 ($adff): \u_reg.u_err_code.q = 32'x
+FF init value for cell $flatten\u_reg.\u_intr_enable_fifo_empty.$procdff$5440 ($adff): \u_reg.u_intr_enable_fifo_empty.q = 1'x
+FF init value for cell $flatten\u_reg.\u_intr_enable_hmac_done.$procdff$5440 ($adff): \u_reg.u_intr_enable_hmac_done.q = 1'x
+FF init value for cell $flatten\u_reg.\u_intr_enable_hmac_err.$procdff$5440 ($adff): \u_reg.u_intr_enable_hmac_err.q = 1'x
+FF init value for cell $flatten\u_reg.\u_intr_state_fifo_empty.$procdff$5452 ($adff): \u_reg.u_intr_state_fifo_empty.q = 1'x
+FF init value for cell $flatten\u_reg.\u_intr_state_hmac_done.$procdff$5452 ($adff): \u_reg.u_intr_state_hmac_done.q = 1'x
+FF init value for cell $flatten\u_reg.\u_intr_state_hmac_err.$procdff$5452 ($adff): \u_reg.u_intr_state_hmac_err.q = 1'x
+FF init value for cell $flatten\u_reg.\u_msg_length_lower.$procdff$5454 ($adff): \u_reg.u_msg_length_lower.q = 32'x
+FF init value for cell $flatten\u_reg.\u_msg_length_upper.$procdff$5454 ($adff): \u_reg.u_msg_length_upper.q = 32'x
+FF init value for cell $flatten\u_reg.\u_reg_if.$procdff$5338 ($adff): \u_reg.u_reg_if.outstanding = 1'x
+FF init value for cell $flatten\u_reg.\u_reg_if.$procdff$5339 ($adff): \u_reg.u_reg_if.rdata = 32'x
+FF init value for cell $flatten\u_reg.\u_reg_if.$procdff$5340 ($adff): \u_reg.u_reg_if.error = 1'x
+FF init value for cell $flatten\u_reg.\u_reg_if.$procdff$5341 ($adff): \u_reg.u_reg_if.reqid = 8'x
+FF init value for cell $flatten\u_reg.\u_reg_if.$procdff$5342 ($adff): \u_reg.u_reg_if.reqsz = 2'x
+FF init value for cell $flatten\u_reg.\u_reg_if.$procdff$5343 ($adff): \u_reg.u_reg_if.rspop = 3'x
+FF init value for cell $flatten\u_reg.\u_socket.$procdff$5309 ($adff): \u_reg.u_socket.num_req_outstanding = 9'x
+FF init value for cell $flatten\u_reg.\u_socket.$procdff$5310 ($adff): \u_reg.u_socket.dev_select_outstanding = 2'x
+FF init value for cell $flatten\u_reg.\u_socket.\err_resp.$procdff$5447 ($dff): \u_reg.u_socket.err_resp.err_source = 8'x
+FF init value for cell $flatten\u_reg.\u_socket.\err_resp.$procdff$5448 ($adff): \u_reg.u_socket.err_resp.err_size = 2'x
+FF init value for cell $flatten\u_reg.\u_socket.\err_resp.$procdff$5449 ($adff): \u_reg.u_socket.err_resp.err_req_pending = 1'x
+FF init value for cell $flatten\u_reg.\u_socket.\err_resp.$procdff$5450 ($adff): \u_reg.u_socket.err_resp.err_rsp_pending = 1'x
+FF init value for cell $flatten\u_sha2.$procdff$5354 ($adff): \u_sha2.w = 512'x
+FF init value for cell $flatten\u_sha2.$procdff$5378 ($adff): \u_sha2.sha_st_q = 2'x
+FF init value for cell $flatten\u_sha2.$procdff$5379 ($adff): \u_sha2.fifo_st_q = 2'x
+FF init value for cell $flatten\u_sha2.$procdff$5380 ($adff): \u_sha2.hash_done = 1'x
+FF init value for cell $flatten\u_sha2.$procdff$5381 ($adff): \u_sha2.w_index = 4'x
+FF init value for cell $flatten\u_sha2.$procdff$5382 ($adff): \u_sha2.round = 6'x
+FF init value for cell $flatten\u_sha2.$procdff$5383 ($adff): \u_sha2.digest = 32'x
+FF init value for cell $flatten\u_sha2.$procdff$5393 ($adff): \u_sha2.hash = 256'x
+FF init value for cell $flatten\u_sha2.\u_pad.$procdff$5311 ($adff): \u_sha2.u_pad.hash_process_flag = 1'x
+FF init value for cell $flatten\u_sha2.\u_pad.$procdff$5312 ($adff): \u_sha2.u_pad.tx_count = 64'x
+FF init value for cell $flatten\u_sha2.\u_pad.$procdff$5313 ($adff): \u_sha2.u_pad.st_q = 3'x
+FF init value for cell $flatten\u_tlul_adapter.\u_reqfifo.$procdff$5314 ($dff): \u_tlul_adapter.u_reqfifo.gen_normal_fifo.storage = 13'x
+FF init value for cell $flatten\u_tlul_adapter.\u_reqfifo.$procdff$5315 ($adff): \u_tlul_adapter.u_reqfifo.gen_normal_fifo.fifo_rptr = 2'x
+FF init value for cell $flatten\u_tlul_adapter.\u_reqfifo.$procdff$5316 ($adff): \u_tlul_adapter.u_reqfifo.gen_normal_fifo.fifo_wptr = 2'x
+FF init value for cell $flatten\u_tlul_adapter.\u_rspfifo.$procdff$5335 ($dff): \u_tlul_adapter.u_rspfifo.gen_normal_fifo.storage = 33'x
+FF init value for cell $flatten\u_tlul_adapter.\u_rspfifo.$procdff$5336 ($adff): \u_tlul_adapter.u_rspfifo.gen_normal_fifo.fifo_rptr = 2'x
+FF init value for cell $flatten\u_tlul_adapter.\u_rspfifo.$procdff$5337 ($adff): \u_tlul_adapter.u_rspfifo.gen_normal_fifo.fifo_wptr = 2'x
+FF init value for cell $flatten\u_tlul_adapter.\u_sramreqfifo.$procdff$5436 ($dff): \u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.storage = 5'x
+FF init value for cell $flatten\u_tlul_adapter.\u_sramreqfifo.$procdff$5437 ($adff): \u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.fifo_rptr = 2'x
+FF init value for cell $flatten\u_tlul_adapter.\u_sramreqfifo.$procdff$5438 ($adff): \u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.fifo_wptr = 2'x
+FF init value for cell $procdff$5344 ($adff): \secret_key = 256'x
+FF init value for cell $procdff$5348 ($adff): \idle_o = 1'x
+FF init value for cell $procdff$5349 ($adff): \message_length = 64'x
+FF init value for cell $procdff$5350 ($adff): \fifo_empty_q = 1'x
+FF init value for cell $procdff$5351 ($adff): \msg_allowed = 1'x
+FF init value for cell $procdff$5352 ($adff): \cfg_reg = 8'x
+FF init value for cell $procdff$5353 ($adff): \cfg_block = 1'x
+
+3.31. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+
+3.32. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+
+Removed a total of 343 cells.
+
+3.33. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2699.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2706.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4951.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2714.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2722.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2730.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2738.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4962.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2746.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2756.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2758.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2767.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2777.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4973.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2787.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2797.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2808.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2819.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4984.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2831.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2842.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2854.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4996.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2866.
+ dead port 2/2 on $mux $flatten\u_hmac.$procmux$2878.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5008.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5020.
+ dead port 2/2 on $mux $flatten\u_hmac.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:128$1244.
+ dead port 2/2 on $mux $flatten\u_packer.$procmux$3080.
+ dead port 2/2 on $mux $flatten\u_packer.$procmux$3085.
+ dead port 2/2 on $mux $flatten\u_packer.$procmux$3090.
+ dead port 1/2 on $mux $flatten\u_packer.$procmux$3096.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5091.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5097.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5138.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5145.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5152.
+ dead port 1/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5161.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5163.
+ dead port 1/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5172.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5174.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5248.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5256.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5264.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4878.
+ dead port 2/2 on $mux $flatten\u_reg.\u_reg_if.\u_err.$procmux$2968.
+ dead port 2/2 on $mux $flatten\u_reg.\u_reg_if.\u_err.$procmux$2976.
+ dead port 2/2 on $mux $flatten\u_reg.\u_reg_if.\u_err.$procmux$2984.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5091.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4008.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4014.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4021.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4028.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4036.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5097.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4044.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5105.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5107.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5115.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5117.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4883.
+ dead port 1/2 on $mux $flatten\u_sha2.$procmux$4071.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4073.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4079.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5124.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4085.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4092.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4095.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4097.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4105.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4108.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4110.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4118.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4120.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5131.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4128.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4130.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4137.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4144.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5145.
+ dead port 2/2 on $mux $flatten\u_sha2.$procmux$4152.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4888.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5152.
+ dead port 1/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5161.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2011.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2017.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5163.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2024.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2031.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2040.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2042.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2050.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2058.
+ dead port 1/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5172.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2068.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2070.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2080.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2082.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5174.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2091.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2100.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2111.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2114.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2116.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2127.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2130.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2132.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5184.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2143.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2146.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2148.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5186.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2159.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2162.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2164.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5188.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2175.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2177.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4896.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2188.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2190.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2201.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2203.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5198.
+ dead port 1/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2214.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2216.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5200.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2226.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5202.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2236.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2246.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2256.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5211.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2267.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5213.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2277.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5222.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5224.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4904.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5232.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5240.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5256.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4913.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5264.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4922.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4931.
+ dead port 2/2 on $mux $flatten\u_sha2.\u_pad.$procmux$2324.
+ dead port 2/2 on $mux $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4941.
+ dead port 1/2 on $mux $flatten\u_tlul_adapter.$procmux$3000.
+ dead port 1/2 on $mux $flatten\u_tlul_adapter.$procmux$3002.
+ dead port 1/2 on $mux $flatten\u_tlul_adapter.$procmux$3008.
+ dead port 1/2 on $mux $flatten\u_tlul_adapter.$procmux$3050.
+ dead port 2/2 on $mux $flatten\u_tlul_adapter.\u_err.$procmux$2968.
+ dead port 2/2 on $mux $flatten\u_tlul_adapter.\u_err.$procmux$2976.
+ dead port 2/2 on $mux $flatten\u_tlul_adapter.\u_err.$procmux$2984.
+ dead port 2/2 on $mux $procmux$3351.
+ dead port 2/2 on $mux $procmux$3357.
+ dead port 2/2 on $mux $procmux$3363.
+ dead port 2/2 on $mux $procmux$3369.
+ dead port 2/2 on $mux $procmux$3375.
+ dead port 2/2 on $mux $procmux$3381.
+ dead port 2/2 on $mux $procmux$3387.
+ dead port 2/2 on $mux $procmux$3393.
+Removed 163 multiplexer ports.
+
+
+3.34. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+ New input vector for $reduce_or cell $flatten\u_reg.\u_reg_if.\u_err.$reduce_or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:63$1177: \tl_i [59:58]
+ New input vector for $reduce_or cell $flatten\u_reg.\u_reg_if.\u_err.$reduce_or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:62$1174: \tl_i [57:56]
+ New input vector for $reduce_or cell $flatten\u_reg.$reduce_or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:990$1474: $flatten\u_reg.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:970$1374_Y [1:0]
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5049: { $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4897_CMP $auto_5680 }
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5058: { $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4942_CMP $auto_5682 }
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5022: { $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4997_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4963_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4914_CMP $auto_5684 $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4879_CMP }
+ New ctrl vector for $pmux cell $flatten\u_hmac.$procmux$2892: $flatten\u_hmac.$procmux$2715_CMP
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5031: { $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4997_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4963_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4914_CMP $auto_5686 $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4879_CMP }
+ New ctrl vector for $pmux cell $flatten\u_hmac.$procmux$2934: { $flatten\u_hmac.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:116$1216_Y $auto_5688 }
+ New ctrl vector for $pmux cell $flatten\u_sha2.\u_pad.$procmux$2288: { $flatten\u_sha2.\u_pad.$procmux$2117_CMP $flatten\u_sha2.\u_pad.$procmux$2071_CMP $flatten\u_sha2.\u_pad.$procmux$2043_CMP $flatten\u_sha2.\u_pad.$procmux$2025_CMP $flatten\u_sha2.\u_pad.$procmux$2012_CMP }
+ New ctrl vector for $pmux cell $flatten\u_sha2.\u_pad.$procmux$2296: { $flatten\u_sha2.\u_pad.$procmux$2117_CMP $auto_5690 }
+ Optimizing cells in module \hmac.
+Performed a total of 11 changes.
+
+3.35. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+
+Removed a total of 32 cells.
+
+3.36. Executing OPT_SHARE pass.
+ Found cells that share an operand and can be merged by moving the $mux $flatten\u_msg_fifo.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:69$902 in front of them:
+ $flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:69$899
+ $flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:70$901
+
+3.37. Executing OPT_DFF pass (perform DFF optimizations).
+Handling D = Q on $flatten\u_reg.\u_intr_enable_hmac_err.$procdff$5440 ($adff) from module hmac (removing D path).
+Handling D = Q on $flatten\u_reg.\u_intr_enable_hmac_done.$procdff$5440 ($adff) from module hmac (removing D path).
+Handling D = Q on $flatten\u_reg.\u_intr_enable_fifo_empty.$procdff$5440 ($adff) from module hmac (removing D path).
+Setting constant 0-bit at position 0 on $flatten\u_reg.\u_intr_enable_fifo_empty.$procdff$5440 ($dlatch) from module hmac.
+Setting constant 0-bit at position 0 on $flatten\u_reg.\u_intr_enable_hmac_done.$procdff$5440 ($dlatch) from module hmac.
+Setting constant 0-bit at position 0 on $flatten\u_reg.\u_intr_enable_hmac_err.$procdff$5440 ($dlatch) from module hmac.
+[#visit=84, #solve=0, #remove=3, time=0.63 sec.]
+
+3.38. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 0 unused cells and 551 unused wires.
+
+
+3.39. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+
+3.40. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.41. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5022: { $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4997_CMP $auto_5697 $auto_5684 $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4879_CMP }
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5031: { $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4997_CMP $auto_5699 $auto_5684 $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4879_CMP }
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5040: { $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4997_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4963_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4914_CMP $auto_5701 $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5025_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$5024_CMP $flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4879_CMP }
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5272: { $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5164_CMP $auto_5703 }
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5288: $auto_5705
+ New ctrl vector for $pmux cell $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5272: { $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5164_CMP $auto_5707 }
+ New ctrl vector for $pmux cell $flatten\u_hmac.$procmux$2925: { $flatten\u_hmac.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:116$1216_Y $auto_5709 }
+ New ctrl vector for $pmux cell $flatten\u_sha2.$procmux$4047: { $flatten\u_sha2.$procmux$4022_CMP $auto_5711 }
+ New ctrl vector for $pmux cell $flatten\u_sha2.$procmux$4052: $auto_5713
+ New ctrl vector for $pmux cell $flatten\u_sha2.\u_pad.$procmux$2288: { $flatten\u_sha2.\u_pad.$procmux$2117_CMP $flatten\u_sha2.\u_pad.$procmux$2071_CMP $auto_5715 }
+ Optimizing cells in module \hmac.
+Performed a total of 10 changes.
+
+3.42. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+
+Removed a total of 4 cells.
+
+3.43. Executing OPT_SHARE pass.
+
+3.44. Executing OPT_DFF pass (perform DFF optimizations).
+Handling D = Q on $flatten\u_reg.\u_socket.\err_resp.$procdff$5448 ($adff) from module hmac (removing D path).
+Handling D = Q on $flatten\u_reg.\u_socket.\err_resp.$procdff$5447 ($dff) from module hmac (removing D path).
+Setting constant 0-bit at position 0 on $flatten\intr_hw_fifo_empty.$procdff$5329 ($adff) from module hmac.
+Setting constant 0-bit at position 0 on $flatten\u_reg.\u_socket.\err_resp.$procdff$5448 ($dlatch) from module hmac.
+Setting constant 0-bit at position 1 on $flatten\u_reg.\u_socket.\err_resp.$procdff$5448 ($dlatch) from module hmac.
+[#visit=78, #solve=0, #remove=3, time=0.55 sec.]
+
+3.45. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 0 unused cells and 6 unused wires.
+
+
+3.46. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.47. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.48. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.49. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.50. Executing OPT_SHARE pass.
+
+3.51. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=76, #solve=0, #remove=0, time=0.75 sec.]
+
+3.52. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.53. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+RUN-OPT ITERATIONS DONE : 3
+
+3.54. Executing FSM pass (extract and optimize FSM).
+
+3.54.1. Executing FSM_DETECT pass (finding FSMs in design).
+Not marking hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.state_q as FSM state register:
+ Register has an initialization value.
+Not marking hmac.gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.state_q as FSM state register:
+ Register has an initialization value.
+Not marking hmac.gen_alert_tx[0].u_prim_alert_sender.state_q as FSM state register:
+ Register has an initialization value.
+Not marking hmac.u_hmac.st_q as FSM state register:
+ Register has an initialization value.
+ Circuit seems to be self-resetting.
+Not marking hmac.u_reg.u_err_code.q as FSM state register:
+ Users of register don't seem to benefit from recoding.
+ Register has an initialization value.
+Not marking hmac.u_reg.u_reg_if.rspop as FSM state register:
+ Users of register don't seem to benefit from recoding.
+ Register has an initialization value.
+Not marking hmac.u_sha2.fifo_st_q as FSM state register:
+ Register has an initialization value.
+ Circuit seems to be self-resetting.
+Not marking hmac.u_sha2.sha_st_q as FSM state register:
+ Register has an initialization value.
+ Circuit seems to be self-resetting.
+Not marking hmac.u_sha2.u_pad.st_q as FSM state register:
+ Register has an initialization value.
+ Circuit seems to be self-resetting.
+
+3.54.2. Executing FSM_EXTRACT pass (extracting FSM from design).
+
+3.54.3. Executing FSM_OPT pass (simple optimizations of FSMs).
+
+3.54.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.54.5. Executing FSM_OPT pass (simple optimizations of FSMs).
+
+3.54.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
+
+3.54.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
+
+3.54.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
+
+3.55. Executing WREDUCE pass (reducing word size of cells).
+Removed top 20 address bits (of 32) from memory init port hmac.$flatten\u_reg.$auto_1968 ($flatten\u_reg.$auto_1966).
+Removed top 23 bits (of 32) from port B of cell hmac.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_pkg.sv:0$568 ($shiftx).
+Removed top 29 bits (of 32) from mux cell hmac.$procmux$3337 ($mux).
+Removed top 28 bits (of 32) from mux cell hmac.$flatten\u_tlul_adapter.\u_sramreqfifo.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:141$64 ($mux).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.\u_sramreqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$56 ($add).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.\u_sramreqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$61 ($add).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.\u_rspfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$758 ($add).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.\u_rspfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$763 ($add).
+Removed top 19 bits (of 32) from mux cell hmac.$flatten\u_tlul_adapter.\u_reqfifo.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:141$1623 ($mux).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.\u_reqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$1615 ($add).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.\u_reqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$1620 ($add).
+Removed top 1 bits (of 2) from mux cell hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:228$1137 ($mux).
+Removed top 24 bits (of 32) from mux cell hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$994 ($mux).
+Removed top 24 bits (of 32) from mux cell hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$1057 ($mux).
+Removed top 24 bits (of 32) from mux cell hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$1036 ($mux).
+Removed top 24 bits (of 32) from mux cell hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$1015 ($mux).
+Removed top 2 bits (of 3) from mux cell hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:142$1120 ($mux).
+Removed top 25 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1143 ($shiftx).
+Removed top 8 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1060 ($or).
+Removed top 8 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1048 ($or).
+Removed top 8 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1039 ($or).
+Removed top 8 bits (of 32) from port Y of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1039 ($or).
+Removed top 8 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1027 ($or).
+Removed top 8 bits (of 32) from port Y of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1027 ($or).
+Removed top 24 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1018 ($or).
+Removed top 16 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1018 ($or).
+Removed top 16 bits (of 32) from port Y of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1018 ($or).
+Removed top 24 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1006 ($or).
+Removed top 16 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1006 ($or).
+Removed top 16 bits (of 32) from port Y of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1006 ($or).
+Converting cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1096 ($neg) from signed to unsigned.
+Converting cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1087 ($neg) from signed to unsigned.
+Converting cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1078 ($neg) from signed to unsigned.
+Removed top 26 bits (of 33) from port A of cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1073 ($neg).
+Converting cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1073 ($neg) from signed to unsigned.
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.$ne$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:142$1118 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_tlul_adapter.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:115$1149 ($eq).
+Removed top 26 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1095 ($add).
+Removed top 27 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1095 ($add).
+Removed top 25 bits (of 32) from port Y of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1095 ($add).
+Removed top 26 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1086 ($add).
+Removed top 27 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1086 ($add).
+Removed top 25 bits (of 32) from port Y of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1086 ($add).
+Removed top 26 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1077 ($add).
+Removed top 28 bits (of 32) from port B of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1077 ($add).
+Removed top 25 bits (of 32) from port Y of cell hmac.$flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1077 ($add).
+Removed top 1 bits (of 3) from port B of cell hmac.$flatten\u_sha2.\u_pad.$procmux$2329_CMP0 ($eq).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\u_sha2.\u_pad.$procmux$2325_CMP0 ($eq).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_sha2.\u_pad.$procmux$2322_CMP0 ($eq).
+Removed top 2 bits (of 3) from mux cell hmac.$flatten\u_sha2.\u_pad.$procmux$2265 ($mux).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\u_sha2.\u_pad.$procmux$2117_CMP0 ($eq).
+Removed top 1 bits (of 3) from mux cell hmac.$flatten\u_sha2.\u_pad.$procmux$2108 ($mux).
+Removed top 2 bits (of 3) from mux cell hmac.$flatten\u_sha2.\u_pad.$procmux$2077 ($mux).
+Removed top 1 bits (of 3) from port B of cell hmac.$flatten\u_sha2.\u_pad.$procmux$2071_CMP0 ($eq).
+Removed top 1 bits (of 3) from port B of cell hmac.$flatten\u_sha2.\u_pad.$procmux$2043_CMP0 ($eq).
+Removed top 2 bits (of 3) from mux cell hmac.$flatten\u_sha2.\u_pad.$procmux$2029 ($mux).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$279 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$278 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$277 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$276 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$275 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$274 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$273 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$272 ($xor).
+Removed top 10 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:85$461 ($xor).
+Removed top 3 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:84$452 ($xor).
+Removed top 15 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$222 ($shiftx).
+Removed top 992 bits (of 1024) from port Y of cell hmac.$flatten\u_sha2.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$222 ($shiftx).
+Removed top 1 bits (of 2) from mux cell hmac.$flatten\u_sha2.$procmux$4150 ($mux).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_sha2.$procmux$4098_CMP0 ($eq).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_sha2.$procmux$4022_CMP0 ($eq).
+Removed top 1 bits (of 2) from mux cell hmac.$flatten\u_sha2.$procmux$4006 ($mux).
+Removed top 19 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$458 ($or).
+Removed top 17 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$455 ($or).
+Removed top 18 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$449 ($or).
+Removed top 7 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$446 ($or).
+Removed top 22 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$250 ($or).
+Removed top 13 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$247 ($or).
+Removed top 2 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$244 ($or).
+Removed top 25 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$231 ($or).
+Removed top 11 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$228 ($or).
+Removed top 6 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$225 ($or).
+Removed top 26 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$lt$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:266$316 ($lt).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:150$302 ($add).
+Removed top 28 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:150$302 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:138$298 ($add).
+Removed top 26 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:138$298 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$293 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$292 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$291 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$290 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$289 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$288 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$287 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$286 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:72$259 ($add).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\u_reg.\u_socket.\gen_dfifo[1].fifo_d.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:74$1257 ($eq).
+Removed top 2 bits (of 3) from port A of cell hmac.$flatten\u_reg.\u_socket.\gen_dfifo[0].fifo_d.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:74$1257 ($eq).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\u_reg.\u_socket.\gen_dfifo[0].fifo_d.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:74$1257 ($eq).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\u_reg.\u_socket.\fifo_h.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_fifo_sync.sv:74$24 ($eq).
+Removed top 1 bits (of 2) from port A of cell hmac.$flatten\u_reg.\u_socket.$ne$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:116$1953 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_reg.\u_socket.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:157$1949 ($eq).
+Removed top 30 bits (of 32) from port A of cell hmac.$flatten\u_reg.\u_reg_if.\u_err.$shl$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:44$1160 ($shl).
+Removed top 28 bits (of 32) from port Y of cell hmac.$flatten\u_reg.\u_reg_if.\u_err.$shl$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_err.sv:44$1160 ($shl).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_reg.\u_reg_if.\u_err.$procmux$2966_CMP0 ($eq).
+Removed top 2 bits (of 3) from mux cell hmac.$flatten\u_reg.\u_reg_if.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:79$717 ($mux).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\u_reg.\u_reg_if.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:55$727 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:962$1371 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:961$1370 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:960$1369 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:959$1368 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:958$1367 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:957$1366 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:956$1365 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:955$1364 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:954$1363 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:953$1362 ($eq).
+Removed top 5 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:952$1361 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:951$1360 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:950$1359 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:949$1358 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:948$1357 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:947$1356 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:946$1355 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:945$1354 ($eq).
+Removed top 6 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:944$1353 ($eq).
+Removed top 7 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:943$1352 ($eq).
+Removed top 7 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:942$1351 ($eq).
+Removed top 7 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:941$1350 ($eq).
+Removed top 7 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:940$1349 ($eq).
+Removed top 8 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:939$1348 ($eq).
+Removed top 8 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:938$1347 ($eq).
+Removed top 9 bits (of 10) from port B of cell hmac.$flatten\u_reg.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_reg_top.sv:937$1346 ($eq).
+Removed top 25 bits (of 32) from mux cell hmac.$flatten\u_packer.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$779 ($mux).
+Removed top 25 bits (of 32) from mux cell hmac.$flatten\u_packer.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$776 ($mux).
+Removed top 26 bits (of 32) from port B of cell hmac.$flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$778 ($sub).
+Removed top 25 bits (of 32) from port Y of cell hmac.$flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$778 ($sub).
+Removed top 26 bits (of 32) from port B of cell hmac.$flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$775 ($sub).
+Removed top 25 bits (of 32) from port Y of cell hmac.$flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$775 ($sub).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_packer.$procmux$3116_CMP0 ($eq).
+Removed top 32 bits (of 96) from port A of cell hmac.$flatten\u_packer.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:105$834 ($or).
+Removed top 32 bits (of 96) from port A of cell hmac.$flatten\u_packer.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:103$833 ($or).
+Removed top 26 bits (of 32) from port B of cell hmac.$flatten\u_packer.$le$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$777 ($le).
+Removed top 26 bits (of 32) from port B of cell hmac.$flatten\u_packer.$le$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:216$837 ($le).
+Removed top 26 bits (of 32) from port B of cell hmac.$flatten\u_packer.$ge$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:208$835 ($ge).
+Removed top 5 bits (of 6) from port A of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$841 ($add).
+Removed top 4 bits (of 6) from port Y of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$841 ($add).
+Removed top 27 bits (of 32) from mux cell hmac.$flatten\u_msg_fifo.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:68$903 ($mux).
+Removed top 27 bits (of 32) from port A of cell hmac.$flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:70$900 ($sub).
+Removed top 26 bits (of 32) from port Y of cell hmac.$flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:70$900 ($sub).
+Removed top 27 bits (of 32) from port Y of cell hmac.$flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:69$899 ($sub).
+Converting cell hmac.$flatten\u_msg_fifo.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$930 ($neg) from signed to unsigned.
+Removed top 26 bits (of 30) from port B of cell hmac.$flatten\u_msg_fifo.$mul$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$929 ($mul).
+Removed top 22 bits (of 30) from port Y of cell hmac.$flatten\u_msg_fifo.$mul$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$929 ($mul).
+Removed top 26 bits (of 30) from port B of cell hmac.$flatten\u_msg_fifo.$mul$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$921 ($mul).
+Removed top 22 bits (of 30) from port Y of cell hmac.$flatten\u_msg_fifo.$mul$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$921 ($mul).
+Removed top 4 bits (of 5) from port B of cell hmac.$flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$915 ($add).
+Removed top 4 bits (of 5) from port B of cell hmac.$flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$920 ($add).
+Removed top 26 bits (of 32) from port B of cell hmac.$flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1226 ($sub).
+Removed top 23 bits (of 32) from port A of cell hmac.$flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1224 ($sub).
+Removed top 23 bits (of 32) from port B of cell hmac.$flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1224 ($sub).
+Removed top 22 bits (of 32) from port Y of cell hmac.$flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1224 ($sub).
+Removed top 2 bits (of 3) from mux cell hmac.$flatten\u_hmac.$procmux$2876 ($mux).
+Removed top 1 bits (of 3) from mux cell hmac.$flatten\u_hmac.$procmux$2817 ($mux).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\u_hmac.$procmux$2809_CMP0 ($eq).
+Removed top 1 bits (of 3) from port B of cell hmac.$flatten\u_hmac.$procmux$2715_CMP0 ($eq).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\u_hmac.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:122$1228 ($eq).
+Removed top 1 bits (of 3) from port B of cell hmac.$flatten\u_hmac.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:116$1216 ($eq).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1225 ($add).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procmux$5108_CMP0 ($eq).
+Removed top 1 bits (of 2) from port B of cell hmac.$flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procmux$5139_CMP0 ($eq).
+Removed top 1 bits (of 3) from mux cell hmac.$flatten\gen_alert_tx[0].u_prim_alert_sender.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:139$77 ($mux).
+Removed top 2 bits (of 3) from port B of cell hmac.$flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4963_CMP0 ($eq).
+Removed top 1 bits (of 3) from port B of cell hmac.$flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4942_CMP0 ($eq).
+Removed top 1 bits (of 3) from port B of cell hmac.$flatten\gen_alert_tx[0].u_prim_alert_sender.$procmux$4914_CMP0 ($eq).
+Removed top 5 bits (of 6) from port A of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$501 ($add).
+Removed top 4 bits (of 6) from port Y of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$501 ($add).
+Removed top 29 bits (of 32) from mux cell hmac.$procmux$3339 ($mux).
+Removed top 16 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1039 ($or).
+Removed top 16 bits (of 32) from port A of cell hmac.$flatten\u_tlul_adapter.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1027 ($or).
+Removed top 26 bits (of 33) from port A of cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1096 ($neg).
+Removed top 26 bits (of 33) from port A of cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1087 ($neg).
+Removed top 26 bits (of 33) from port A of cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1078 ($neg).
+Removed top 1 bits (of 7) from port A of cell hmac.$flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1073 ($neg).
+Removed top 1 bits (of 3) from mux cell hmac.$flatten\u_sha2.\u_pad.$procmux$2172 ($mux).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$279 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$278 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$277 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$276 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$275 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$274 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$273 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$272 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$293 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$292 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$291 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$290 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$289 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$288 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$287 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$286 ($add).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260 ($add).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:72$259 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:72$259 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:67$258 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241 ($add).
+Removed top 4 bits (of 6) from port A of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$842 ($add).
+Removed top 3 bits (of 6) from port Y of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$842 ($add).
+Removed top 27 bits (of 32) from port B of cell hmac.$flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:69$899 ($sub).
+Removed top 21 bits (of 32) from port B of cell hmac.$flatten\u_msg_fifo.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$922 ($shiftx).
+Removed top 23 bits (of 33) from port A of cell hmac.$flatten\u_msg_fifo.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$930 ($neg).
+Removed top 27 bits (of 32) from mux cell hmac.$auto_5694 ($mux).
+Removed top 27 bits (of 32) from port Y of cell hmac.$auto_5691 ($neg).
+Removed top 4 bits (of 6) from port A of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$502 ($add).
+Removed top 3 bits (of 6) from port Y of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$502 ($add).
+Removed top 29 bits (of 32) from mux cell hmac.$procmux$3341 ($mux).
+Removed top 1 bits (of 3) from mux cell hmac.$flatten\u_sha2.\u_pad.$procmux$2224 ($mux).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:67$258 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:67$258 ($add).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$240 ($add).
+Removed top 3 bits (of 6) from port A of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$843 ($add).
+Removed top 2 bits (of 6) from port Y of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$843 ($add).
+Removed top 27 bits (of 32) from port A of cell hmac.$auto_5691 ($neg).
+Removed top 3 bits (of 6) from port A of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$503 ($add).
+Removed top 2 bits (of 6) from port Y of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$503 ($add).
+Removed top 29 bits (of 32) from mux cell hmac.$procmux$3343 ($mux).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$257 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$252 ($xor).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$240 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$240 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$239 ($add).
+Removed top 2 bits (of 6) from port A of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$844 ($add).
+Removed top 1 bits (of 6) from port Y of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$844 ($add).
+Removed top 1 bits (of 6) from port Y of cell hmac.$flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:70$900 ($sub).
+Removed top 2 bits (of 6) from port A of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$504 ($add).
+Removed top 1 bits (of 6) from port Y of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$504 ($add).
+Removed top 29 bits (of 32) from mux cell hmac.$procmux$3345 ($mux).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$257 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$257 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$255 ($xor).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$252 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$252 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$251 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$222 ($shiftx).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$250 ($or).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$256 ($and).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$239 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$239 ($add).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$238 ($add).
+Removed top 1 bits (of 6) from port A of cell hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$845 ($add).
+Removed top 1 bits (of 6) from port A of cell hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$505 ($add).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$255 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$255 ($xor).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$251 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$251 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$237 ($xor).
+Removed top 9 bits (of 10) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$250 ($or).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$250 ($or).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$247 ($or).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$244 ($or).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$256 ($and).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$256 ($and).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$254 ($and).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$253 ($and).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$238 ($add).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$238 ($add).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$237 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$237 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$233 ($xor).
+Removed top 18 bits (of 19) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$247 ($or).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$247 ($or).
+Removed top 29 bits (of 30) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$244 ($or).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$244 ($or).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$254 ($and).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$254 ($and).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$253 ($and).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$253 ($and).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$236 ($and).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$234 ($and).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$233 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$233 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$232 ($xor).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$231 ($or).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$236 ($and).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$236 ($and).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$234 ($and).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$234 ($and).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$232 ($xor).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$232 ($xor).
+Removed top 6 bits (of 7) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$231 ($or).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$231 ($or).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$228 ($or).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$225 ($or).
+Removed top 31 bits (of 32) from port Y of cell hmac.$flatten\u_sha2.$not$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$235 ($not).
+Removed top 20 bits (of 21) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$228 ($or).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$228 ($or).
+Removed top 25 bits (of 26) from port A of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$225 ($or).
+Removed top 31 bits (of 32) from port B of cell hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$225 ($or).
+Removed top 31 bits (of 32) from port A of cell hmac.$flatten\u_sha2.$not$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$235 ($not).
+Removed top 4 bits (of 6) from wire hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$501_Y.
+Removed top 3 bits (of 6) from wire hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$502_Y.
+Removed top 2 bits (of 6) from wire hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$503_Y.
+Removed top 1 bits (of 6) from wire hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$504_Y.
+Removed top 27 bits (of 32) from wire hmac.$auto_5692.
+Removed top 27 bits (of 32) from wire hmac.$auto_5693.
+Removed top 27 bits (of 32) from wire hmac.$auto_5695.
+Removed top 1 bits (of 3) from wire hmac.$flatten\gen_alert_tx[0].u_prim_alert_sender.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_alert_sender.sv:139$77_Y.
+Removed top 2 bits (of 3) from wire hmac.$flatten\u_hmac.$2\st_d[2:0].
+Removed top 1 bits (of 3) from wire hmac.$flatten\u_hmac.$3\st_d[2:0].
+Removed top 22 bits (of 32) from wire hmac.$flatten\u_msg_fifo.$mul$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$921_Y.
+Removed top 22 bits (of 32) from wire hmac.$flatten\u_msg_fifo.$mul$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$929_Y.
+Removed top 27 bits (of 32) from wire hmac.$flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:70$900_Y.
+Removed top 4 bits (of 6) from wire hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$841_Y.
+Removed top 3 bits (of 6) from wire hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$842_Y.
+Removed top 2 bits (of 6) from wire hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$843_Y.
+Removed top 1 bits (of 6) from wire hmac.$flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$844_Y.
+Removed top 25 bits (of 32) from wire hmac.$flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$775_Y.
+Removed top 25 bits (of 32) from wire hmac.$flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$778_Y.
+Removed top 25 bits (of 32) from wire hmac.$flatten\u_packer.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$776_Y.
+Removed top 25 bits (of 32) from wire hmac.$flatten\u_packer.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$779_Y.
+Removed top 5 bits (of 39) from wire hmac.$flatten\u_reg.\u_chk.\u_tlul_data_integ_dec.\u_data_chk.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:17$1805_Y.
+Removed top 3 bits (of 39) from wire hmac.$flatten\u_reg.\u_chk.\u_tlul_data_integ_dec.\u_data_chk.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:19$1811_Y.
+Removed top 1 bits (of 39) from wire hmac.$flatten\u_reg.\u_chk.\u_tlul_data_integ_dec.\u_data_chk.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_secded_inv_39_32_dec.sv:21$1817_Y.
+Removed top 2 bits (of 3) from wire hmac.$flatten\u_reg.\u_reg_if.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:79$717_Y.
+Removed top 1 bits (of 2) from wire hmac.$flatten\u_sha2.$2\fifo_st_d[1:0].
+Removed top 1 bits (of 2) from wire hmac.$flatten\u_sha2.$2\sha_st_d[1:0].
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$238_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$239_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$240_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:67$258_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:72$259_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$286_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$287_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$288_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$289_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$290_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$291_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$292_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$293_Y.
+Removed top 26 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:138$298_Y.
+Removed top 28 bits (of 32) from wire hmac.$flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:150$302_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$234_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$236_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$253_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$254_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$256_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$not$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$235_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$225_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$228_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$231_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$244_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$247_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:51$250_Y.
+Removed top 1023 bits (of 1024) from wire hmac.$flatten\u_sha2.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:0$222_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$232_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:62$233_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:63$237_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$251_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:65$252_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$255_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:66$257_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$272_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$273_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$274_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$275_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$276_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$277_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$278_Y.
+Removed top 31 bits (of 32) from wire hmac.$flatten\u_sha2.$xor$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:113$279_Y.
+Removed top 2 bits (of 3) from wire hmac.$flatten\u_sha2.\u_pad.$10\st_d[2:0].
+Removed top 2 bits (of 3) from wire hmac.$flatten\u_sha2.\u_pad.$2\st_d[2:0].
+Removed top 1 bits (of 3) from wire hmac.$flatten\u_sha2.\u_pad.$3\st_d[2:0].
+Removed top 1 bits (of 3) from wire hmac.$flatten\u_sha2.\u_pad.$4\st_d[2:0].
+Removed top 1 bits (of 3) from wire hmac.$flatten\u_sha2.\u_pad.$5\st_d[2:0].
+Removed top 2 bits (of 3) from wire hmac.$flatten\u_sha2.\u_pad.$7\st_d[2:0].
+Removed top 25 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$0$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:254$951[31:0]$1064.
+Removed top 25 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$0$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:254$952[31:0]$1065.
+Removed top 25 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$0$bitselwrite$pos$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:254$953[31:0]$1066.
+Removed top 24 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1012_Y.
+Removed top 16 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1024_Y.
+Removed top 16 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1033_Y.
+Removed top 8 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1045_Y.
+Removed top 8 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$and$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1054_Y.
+Removed top 16 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$shift$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1017_Y.
+Removed top 8 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$shift$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1038_Y.
+Removed top 24 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$1015_Y.
+Removed top 24 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$1036_Y.
+Removed top 24 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:187$1057_Y.
+Removed top 28 bits (of 32) from wire hmac.$flatten\u_tlul_adapter.\u_sramreqfifo.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:141$64_Y.
+Removed top 29 bits (of 32) from wire hmac.$procmux$3337_Y.
+Removed top 29 bits (of 32) from wire hmac.$procmux$3339_Y.
+Removed top 29 bits (of 32) from wire hmac.$procmux$3341_Y.
+Removed top 29 bits (of 32) from wire hmac.$procmux$3343_Y.
+
+3.56. Executing PEEPOPT pass (run peephole optimizers).
+right shiftmul pattern in hmac: shift=$flatten\u_msg_fifo.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$922, mul=$flatten\u_msg_fifo.$mul$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$921
+
+3.57. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 1 unused cells and 109 unused wires.
+
+
+3.58. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+
+3.59. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.60. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.61. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.62. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+
+Removed a total of 4 cells.
+
+3.63. Executing OPT_SHARE pass.
+
+3.64. Executing OPT_DFF pass (perform DFF optimizations).
+Adding EN signal on $procdff$5353 ($adff) from module hmac (D = $0\cfg_block[0:0], Q = \cfg_block).
+Adding EN signal on $procdff$5352 ($adff) from module hmac (D = { \tl_i [24] \u_reg.cfg_we \tl_i [25] \u_reg.cfg_we \tl_i [26] \u_reg.cfg_we \tl_i [27] \u_reg.cfg_we }, Q = \cfg_reg).
+Adding EN signal on $procdff$5351 ($adff) from module hmac (D = $0\msg_allowed[0:0], Q = \msg_allowed).
+Adding EN signal on $procdff$5350 ($adff) from module hmac (D = \fifo_empty, Q = \fifo_empty_q).
+Adding EN signal on $procdff$5349 ($adff) from module hmac (D = $0\message_length[63:0], Q = \message_length).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [31:0], Q = \secret_key [31:0]).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [63:32], Q = \secret_key [63:32]).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [95:64], Q = \secret_key [95:64]).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [127:96], Q = \secret_key [127:96]).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [159:128], Q = \secret_key [159:128]).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [191:160], Q = \secret_key [191:160]).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [223:192], Q = \secret_key [223:192]).
+Adding EN signal on $procdff$5344 ($adff) from module hmac (D = $0\secret_key[255:0] [255:224], Q = \secret_key [255:224]).
+Adding EN signal on $flatten\u_tlul_adapter.\u_sramreqfifo.$procdff$5438 ($adff) from module hmac (D = $flatten\u_tlul_adapter.\u_sramreqfifo.$procmux$5078_Y, Q = \u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.fifo_wptr).
+Adding EN signal on $flatten\u_tlul_adapter.\u_sramreqfifo.$procdff$5437 ($adff) from module hmac (D = $flatten\u_tlul_adapter.\u_sramreqfifo.$procmux$5070_Y, Q = \u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.fifo_rptr).
+Adding EN signal on $flatten\u_tlul_adapter.\u_sramreqfifo.$procdff$5436 ($dff) from module hmac (D = { \tl_i [59:56] 1'0 }, Q = \u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.storage).
+Adding EN signal on $flatten\u_tlul_adapter.\u_rspfifo.$procdff$5337 ($adff) from module hmac (D = $flatten\u_tlul_adapter.\u_rspfifo.$procmux$3238_Y, Q = \u_tlul_adapter.u_rspfifo.gen_normal_fifo.fifo_wptr).
+Adding EN signal on $flatten\u_tlul_adapter.\u_rspfifo.$procdff$5336 ($adff) from module hmac (D = $flatten\u_tlul_adapter.\u_rspfifo.$procmux$3230_Y, Q = \u_tlul_adapter.u_rspfifo.gen_normal_fifo.fifo_rptr).
+Adding EN signal on $flatten\u_tlul_adapter.\u_rspfifo.$procdff$5335 ($dff) from module hmac (D = { \u_tlul_adapter.rdata_tlword 1'1 }, Q = \u_tlul_adapter.u_rspfifo.gen_normal_fifo.storage).
+Adding EN signal on $flatten\u_tlul_adapter.\u_reqfifo.$procdff$5316 ($adff) from module hmac (D = $flatten\u_tlul_adapter.\u_reqfifo.$procmux$2343_Y, Q = \u_tlul_adapter.u_reqfifo.gen_normal_fifo.fifo_wptr).
+Adding EN signal on $flatten\u_tlul_adapter.\u_reqfifo.$procdff$5315 ($adff) from module hmac (D = $flatten\u_tlul_adapter.\u_reqfifo.$procmux$2335_Y, Q = \u_tlul_adapter.u_reqfifo.gen_normal_fifo.fifo_rptr).
+Adding EN signal on $flatten\u_tlul_adapter.\u_reqfifo.$procdff$5314 ($dff) from module hmac (D = { 1'0 \u_tlul_adapter.u_reqfifo.wdata [11] \u_tlul_adapter.error_internal \tl_i [101:92] }, Q = \u_tlul_adapter.u_reqfifo.gen_normal_fifo.storage).
+Adding EN signal on $flatten\u_sha2.\u_pad.$procdff$5312 ($adff) from module hmac (D = 5'00000, Q = \u_sha2.u_pad.tx_count [4:0]).
+Adding EN signal on $flatten\u_sha2.\u_pad.$procdff$5312 ($adff) from module hmac (D = $flatten\u_sha2.\u_pad.$0\tx_count[63:0] [63:5], Q = \u_sha2.u_pad.tx_count [63:5]).
+Adding EN signal on $flatten\u_sha2.\u_pad.$procdff$5311 ($adff) from module hmac (D = $flatten\u_sha2.\u_pad.$0\hash_process_flag[0:0], Q = \u_sha2.u_pad.hash_process_flag).
+Adding EN signal on $flatten\u_sha2.$procdff$5393 ($adff) from module hmac (D = $flatten\u_sha2.$0\hash[255:0], Q = \u_sha2.hash).
+Adding EN signal on $flatten\u_sha2.$procdff$5383 ($adff) from module hmac (D = 24'000000000000000000000000, Q = \u_sha2.digest [31:8]).
+Adding EN signal on $flatten\u_sha2.$procdff$5383 ($adff) from module hmac (D = $flatten\u_sha2.$0\digest[31:0] [7:0], Q = \u_sha2.digest [7:0]).
+Adding EN signal on $flatten\u_sha2.$procdff$5382 ($adff) from module hmac (D = $flatten\u_sha2.$0\round[5:0], Q = \u_sha2.round).
+Adding EN signal on $flatten\u_sha2.$procdff$5381 ($adff) from module hmac (D = $flatten\u_sha2.$0\w_index[3:0], Q = \u_sha2.w_index).
+Adding EN signal on $flatten\u_sha2.$procdff$5354 ($adff) from module hmac (D = $flatten\u_sha2.$0\w[511:0], Q = \u_sha2.w).
+Adding EN signal on $flatten\u_reg.\u_socket.\err_resp.$procdff$5449 ($adff) from module hmac (D = 1'0, Q = \u_reg.u_socket.err_resp.err_req_pending).
+Adding EN signal on $flatten\u_reg.\u_socket.$procdff$5310 ($adff) from module hmac (D = { 1'0 \u_reg.reg_steer }, Q = \u_reg.u_socket.dev_select_outstanding).
+Adding EN signal on $flatten\u_reg.\u_socket.$procdff$5309 ($adff) from module hmac (D = $flatten\u_reg.\u_socket.$0\num_req_outstanding[8:0], Q = \u_reg.u_socket.num_req_outstanding).
+Adding EN signal on $flatten\u_reg.\u_reg_if.$procdff$5343 ($adff) from module hmac (D = { 2'00 $auto_5740 [0] }, Q = \u_reg.u_reg_if.rspop).
+Adding EN signal on $flatten\u_reg.\u_reg_if.$procdff$5342 ($adff) from module hmac (D = \tl_i [101:100], Q = \u_reg.u_reg_if.reqsz).
+Adding EN signal on $flatten\u_reg.\u_reg_if.$procdff$5341 ($adff) from module hmac (D = \tl_i [99:92], Q = \u_reg.u_reg_if.reqid).
+Adding EN signal on $flatten\u_reg.\u_reg_if.$procdff$5340 ($adff) from module hmac (D = $flatten\u_reg.\u_reg_if.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:89$721_Y, Q = \u_reg.u_reg_if.error).
+Adding EN signal on $flatten\u_reg.\u_reg_if.$procdff$5339 ($adff) from module hmac (D = $flatten\u_reg.\u_reg_if.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_reg.sv:88$720_Y, Q = \u_reg.u_reg_if.rdata).
+Adding EN signal on $flatten\u_reg.\u_reg_if.$procdff$5338 ($adff) from module hmac (D = $flatten\u_reg.\u_reg_if.$0\outstanding[0:0], Q = \u_reg.u_reg_if.outstanding).
+Adding EN signal on $flatten\u_reg.\u_intr_state_hmac_err.$procdff$5452 ($adff) from module hmac (D = \u_reg.u_intr_state_hmac_err.d, Q = \u_reg.u_intr_state_hmac_err.q).
+Adding EN signal on $flatten\u_reg.\u_intr_state_hmac_done.$procdff$5452 ($adff) from module hmac (D = \u_reg.u_intr_state_hmac_done.d, Q = \u_reg.u_intr_state_hmac_done.q).
+Adding EN signal on $flatten\u_reg.\u_intr_state_fifo_empty.$procdff$5452 ($adff) from module hmac (D = \u_reg.u_intr_state_fifo_empty.d, Q = \u_reg.u_intr_state_fifo_empty.q).
+Adding EN signal on $flatten\u_reg.\u_err_code.$procdff$5454 ($adff) from module hmac (D = { 29'00000000000000000000000000000 \u_reg.u_err_code.d [2:0] }, Q = \u_reg.u_err_code.q).
+Adding EN signal on $flatten\u_reg.$procdff$5317 ($adff) from module hmac (D = 1'1, Q = \u_reg.intg_err_q).
+Adding EN signal on $flatten\u_packer.$procdff$5333 ($adff) from module hmac (D = $flatten\u_packer.$0\pos[6:0], Q = \u_packer.pos).
+Adding EN signal on $flatten\u_packer.$procdff$5332 ($adff) from module hmac (D = $flatten\u_packer.$0\stored_mask[63:0], Q = \u_packer.stored_mask).
+Adding EN signal on $flatten\u_packer.$procdff$5331 ($adff) from module hmac (D = $flatten\u_packer.$0\stored_data[63:0], Q = \u_packer.stored_data).
+Adding EN signal on $flatten\u_msg_fifo.$procdff$5328 ($adff) from module hmac (D = $flatten\u_msg_fifo.$procmux$3070_Y, Q = \u_msg_fifo.gen_normal_fifo.fifo_wptr).
+Adding EN signal on $flatten\u_msg_fifo.$procdff$5327 ($adff) from module hmac (D = $flatten\u_msg_fifo.$procmux$3062_Y, Q = \u_msg_fifo.gen_normal_fifo.fifo_rptr).
+Adding EN signal on $flatten\u_msg_fifo.$procdff$5324 ($dff) from module hmac (D = $flatten\u_msg_fifo.$or$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$936_Y, Q = \u_msg_fifo.gen_normal_fifo.storage).
+Adding EN signal on $flatten\u_hmac.$procdff$5323 ($adff) from module hmac (D = $flatten\u_hmac.$0\reg_hash_process_flag[0:0], Q = \u_hmac.reg_hash_process_flag).
+Adding EN signal on $flatten\u_hmac.$procdff$5322 ($adff) from module hmac (D = \u_hmac.round_d, Q = \u_hmac.round_q).
+Adding EN signal on $flatten\u_hmac.$procdff$5321 ($adff) from module hmac (D = $flatten\u_hmac.$0\fifo_wdata_sel[2:0], Q = \u_hmac.fifo_wdata_sel).
+Adding EN signal on $flatten\u_hmac.$procdff$5319 ($adff) from module hmac (D = 5'00000, Q = \u_hmac.txcount [4:0]).
+Adding EN signal on $flatten\u_hmac.$procdff$5319 ($adff) from module hmac (D = $flatten\u_hmac.$0\txcount[63:0] [63:5], Q = \u_hmac.txcount [63:5]).
+Adding EN signal on $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ping.$procdff$5442 ($adff) from module hmac (D = \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.state_d, Q = \gen_alert_tx[0].u_prim_alert_sender.i_decode_ping.gen_async.state_q).
+Adding EN signal on $flatten\gen_alert_tx[0].u_prim_alert_sender.\i_decode_ack.$procdff$5442 ($adff) from module hmac (D = \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.state_d, Q = \gen_alert_tx[0].u_prim_alert_sender.i_decode_ack.gen_async.state_q).
+Adding EN signal on $flatten\gen_alert_tx[0].u_prim_alert_sender.$procdff$5431 ($adff) from module hmac (D = \gen_alert_tx[0].u_prim_alert_sender.state_d, Q = \gen_alert_tx[0].u_prim_alert_sender.state_q).
+Setting constant 0-bit at position 0 on $auto_5958 ($adffe) from module hmac.
+Setting constant 0-bit at position 1 on $auto_5958 ($adffe) from module hmac.
+Setting constant 0-bit at position 2 on $auto_5958 ($adffe) from module hmac.
+Setting constant 0-bit at position 3 on $auto_5958 ($adffe) from module hmac.
+Setting constant 0-bit at position 4 on $auto_5958 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 1 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 2 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 3 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 4 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 5 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 6 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 7 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 8 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 9 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 10 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 11 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 12 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 13 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 14 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 15 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 16 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 17 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 18 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 19 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 20 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 21 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 22 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 23 on $auto_5898 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5888 ($adffe) from module hmac.
+Setting constant 0-bit at position 1 on $auto_5888 ($adffe) from module hmac.
+Setting constant 0-bit at position 2 on $auto_5888 ($adffe) from module hmac.
+Setting constant 0-bit at position 3 on $auto_5888 ($adffe) from module hmac.
+Setting constant 0-bit at position 4 on $auto_5888 ($adffe) from module hmac.
+Setting constant 0-bit at position 3 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 4 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 5 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 6 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 7 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 8 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 9 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 10 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 11 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 12 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 13 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 14 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 15 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 16 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 17 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 18 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 19 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 20 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 21 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 22 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 23 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 24 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 25 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 26 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 27 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 28 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 29 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 30 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 31 on $auto_5937 ($adffe) from module hmac.
+Setting constant 0-bit at position 1 on $auto_5926 ($adffe) from module hmac.
+Setting constant 0-bit at position 2 on $auto_5926 ($adffe) from module hmac.
+Setting constant 0-bit at position 1 on $auto_5918 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on hmac:u_reg.u_socket.err_resp.err_req_pending_5917 ($adffe) from module hmac.
+Setting constant 0-bit at position 12 on $auto_5887 ($dffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5881 ($dffe) from module hmac.
+[#visit=86, #solve=0, #remove=69, time=0.41 sec.]
+
+3.65. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 35 unused cells and 43 unused wires.
+
+
+3.66. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+
+3.67. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.68. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+ New ctrl vector for $pmux cell $flatten\u_packer.$procmux$3113: { $flatten\u_packer.$procmux$3116_CMP $flatten\u_packer.$procmux$3115_CMP $flatten\u_packer.$procmux$3114_CMP }
+ New ctrl vector for $pmux cell $flatten\u_packer.$procmux$3118: { $flatten\u_packer.$procmux$3116_CMP $flatten\u_packer.$procmux$3115_CMP $flatten\u_packer.$procmux$3114_CMP }
+ New ctrl vector for $pmux cell $flatten\u_packer.$procmux$3222: { $flatten\u_packer.$procmux$3116_CMP $flatten\u_packer.$procmux$3115_CMP $flatten\u_packer.$procmux$3114_CMP }
+ Optimizing cells in module \hmac.
+Performed a total of 3 changes.
+
+3.69. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+
+Removed a total of 21 cells.
+
+3.70. Executing OPT_SHARE pass.
+
+3.71. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=82, #solve=0, #remove=0, time=0.46 sec.]
+
+3.72. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 1 unused cells and 28 unused wires.
+
+
+3.73. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.74. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.75. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.76. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.77. Executing OPT_SHARE pass.
+
+3.78. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=82, #solve=0, #remove=0, time=0.51 sec.]
+
+3.79. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.80. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+RUN-OPT ITERATIONS DONE : 3
+
+3.81. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.82. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.83. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.84. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.85. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.86. Executing OPT_SHARE pass.
+
+3.87. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=82, #solve=0, #remove=0, time=0.68 sec.]
+
+3.88. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.89. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+RUN-OPT ITERATIONS DONE : 1
+
+3.90. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.91. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.92. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.93. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.94. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.95. Executing OPT_SHARE pass.
+
+3.96. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=82, #solve=0, #remove=0, time=0.60 sec.]
+
+3.97. Executing OPT_DFF pass (perform DFF optimizations).
+Setting constant 0-bit at position 0 on $auto_5879 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5880 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5882 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5883 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5885 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $auto_5886 ($adffe) from module hmac.
+Setting constant 0-bit at position 0 on $flatten\u_reg.\u_socket.\err_resp.$procdff$5450 ($adff) from module hmac.
+[#visit=82, #solve=2145, #remove=7, time=456.95 sec.]
+
+3.98. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 3 unused cells and 3 unused wires.
+
+
+3.99. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+
+RUN-OPT ITERATIONS DONE : 1
+
+3.100. Executing WREDUCE pass (reducing word size of cells).
+Removed cell hmac.$flatten\u_tlul_adapter.\u_sramreqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$56 ($add).
+Removed cell hmac.$flatten\u_tlul_adapter.\u_sramreqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$61 ($add).
+Removed cell hmac.$flatten\u_tlul_adapter.\u_rspfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$758 ($add).
+Removed cell hmac.$flatten\u_tlul_adapter.\u_rspfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$763 ($add).
+Removed top 1 bits (of 13) from mux cell hmac.$flatten\u_tlul_adapter.\u_reqfifo.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:141$1623 ($mux).
+Removed cell hmac.$flatten\u_tlul_adapter.\u_reqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$1615 ($add).
+Removed cell hmac.$flatten\u_tlul_adapter.\u_reqfifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$1620 ($add).
+Removed top 1 bits (of 2) from port A of cell hmac.$flatten\u_tlul_adapter.$ne$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:142$1118 ($ne).
+Removed top 1 bits (of 2) from port A of cell hmac.$flatten\u_tlul_adapter.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:115$1149 ($eq).
+Removed top 1 bits (of 4) from FF cell hmac.$auto_5995 ($dffe).
+Removed top 2 bits (of 3) from port B of cell hmac.$auto_5988 ($ne).
+Removed top 1 bits (of 3) from port B of cell hmac.$auto_5984 ($ne).
+Removed top 1 bits (of 3) from port B of cell hmac.$auto_5982 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$auto_5975 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$auto_5966 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$auto_5957 ($ne).
+Removed top 4 bits (of 5) from port B of cell hmac.$auto_5916 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$auto_5913 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$auto_5910 ($ne).
+Removed top 1 bits (of 2) from port B of cell hmac.$auto_5827 ($ne).
+Removed top 1 bits (of 3) from wire hmac.$auto_5723.
+Removed top 2 bits (of 3) from wire hmac.$auto_5724.
+Removed top 1 bits (of 3) from wire hmac.$auto_5725.
+Removed top 22 bits (of 32) from wire hmac.$auto_5727.
+Removed top 27 bits (of 32) from wire hmac.$auto_5728.
+Removed top 4 bits (of 6) from wire hmac.$auto_5729.
+Removed top 3 bits (of 6) from wire hmac.$auto_5730.
+Removed top 2 bits (of 6) from wire hmac.$auto_5731.
+Removed top 1 bits (of 6) from wire hmac.$auto_5732.
+Removed top 25 bits (of 32) from wire hmac.$auto_5733.
+Removed top 25 bits (of 32) from wire hmac.$auto_5734.
+Removed top 25 bits (of 32) from wire hmac.$auto_5735.
+Removed top 25 bits (of 32) from wire hmac.$auto_5736.
+Removed top 5 bits (of 39) from wire hmac.$auto_5737.
+Removed top 3 bits (of 39) from wire hmac.$auto_5738.
+Removed top 1 bits (of 39) from wire hmac.$auto_5739.
+Removed top 2 bits (of 3) from wire hmac.$auto_5740.
+Removed top 1 bits (of 2) from wire hmac.$auto_5741.
+Removed top 1 bits (of 2) from wire hmac.$auto_5742.
+Removed top 31 bits (of 32) from wire hmac.$auto_5743.
+Removed top 31 bits (of 32) from wire hmac.$auto_5744.
+Removed top 31 bits (of 32) from wire hmac.$auto_5745.
+Removed top 31 bits (of 32) from wire hmac.$auto_5746.
+Removed top 31 bits (of 32) from wire hmac.$auto_5747.
+Removed top 31 bits (of 32) from wire hmac.$auto_5748.
+Removed top 31 bits (of 32) from wire hmac.$auto_5749.
+Removed top 31 bits (of 32) from wire hmac.$auto_5750.
+Removed top 31 bits (of 32) from wire hmac.$auto_5751.
+Removed top 31 bits (of 32) from wire hmac.$auto_5752.
+Removed top 31 bits (of 32) from wire hmac.$auto_5753.
+Removed top 31 bits (of 32) from wire hmac.$auto_5754.
+Removed top 31 bits (of 32) from wire hmac.$auto_5755.
+Removed top 31 bits (of 32) from wire hmac.$auto_5756.
+Removed top 31 bits (of 32) from wire hmac.$auto_5757.
+Removed top 26 bits (of 32) from wire hmac.$auto_5758.
+Removed top 28 bits (of 32) from wire hmac.$auto_5759.
+Removed top 31 bits (of 32) from wire hmac.$auto_5760.
+Removed top 31 bits (of 32) from wire hmac.$auto_5761.
+Removed top 31 bits (of 32) from wire hmac.$auto_5762.
+Removed top 31 bits (of 32) from wire hmac.$auto_5763.
+Removed top 31 bits (of 32) from wire hmac.$auto_5764.
+Removed top 31 bits (of 32) from wire hmac.$auto_5765.
+Removed top 1023 bits (of 1024) from wire hmac.$auto_5772.
+Removed top 31 bits (of 32) from wire hmac.$auto_5773.
+Removed top 31 bits (of 32) from wire hmac.$auto_5774.
+Removed top 31 bits (of 32) from wire hmac.$auto_5775.
+Removed top 31 bits (of 32) from wire hmac.$auto_5776.
+Removed top 31 bits (of 32) from wire hmac.$auto_5777.
+Removed top 31 bits (of 32) from wire hmac.$auto_5778.
+Removed top 31 bits (of 32) from wire hmac.$auto_5779.
+Removed top 31 bits (of 32) from wire hmac.$auto_5780.
+Removed top 31 bits (of 32) from wire hmac.$auto_5781.
+Removed top 31 bits (of 32) from wire hmac.$auto_5782.
+Removed top 31 bits (of 32) from wire hmac.$auto_5783.
+Removed top 31 bits (of 32) from wire hmac.$auto_5784.
+Removed top 31 bits (of 32) from wire hmac.$auto_5785.
+Removed top 31 bits (of 32) from wire hmac.$auto_5786.
+Removed top 31 bits (of 32) from wire hmac.$auto_5787.
+Removed top 2 bits (of 3) from wire hmac.$auto_5788.
+Removed top 2 bits (of 3) from wire hmac.$auto_5789.
+Removed top 1 bits (of 3) from wire hmac.$auto_5790.
+Removed top 1 bits (of 3) from wire hmac.$auto_5791.
+Removed top 1 bits (of 3) from wire hmac.$auto_5792.
+Removed top 2 bits (of 3) from wire hmac.$auto_5793.
+Removed top 25 bits (of 32) from wire hmac.$auto_5794.
+Removed top 25 bits (of 32) from wire hmac.$auto_5795.
+Removed top 25 bits (of 32) from wire hmac.$auto_5796.
+Removed top 24 bits (of 32) from wire hmac.$auto_5797.
+Removed top 16 bits (of 32) from wire hmac.$auto_5798.
+Removed top 16 bits (of 32) from wire hmac.$auto_5799.
+Removed top 8 bits (of 32) from wire hmac.$auto_5800.
+Removed top 8 bits (of 32) from wire hmac.$auto_5801.
+Removed top 16 bits (of 32) from wire hmac.$auto_5802.
+Removed top 8 bits (of 32) from wire hmac.$auto_5803.
+Removed top 24 bits (of 32) from wire hmac.$auto_5806.
+Removed top 29 bits (of 32) from wire hmac.$auto_5808.
+Removed top 29 bits (of 32) from wire hmac.$auto_5809.
+Removed top 29 bits (of 32) from wire hmac.$auto_5810.
+Removed top 29 bits (of 32) from wire hmac.$auto_5811.
+Removed top 24 bits (of 32) from wire hmac.$flatten\u_sha2.$0\digest[31:0].
+
+3.101. Executing PEEPOPT pass (run peephole optimizers).
+
+3.102. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 0 unused cells and 92 unused wires.
+
+
+3.103. Executing DEMUXMAP pass.
+
+3.104. Executing SPLITNETS pass (splitting up multi-bit signals).
+
+3.105. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 2046
+ Number of wire bits: 31698
+ Number of public wires: 1135
+ Number of public wire bits: 19171
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 1
+ Number of memory bits: 4096
+ Number of processes: 0
+ Number of cells: 1392
+ $add 94
+ $adff 26
+ $adffe 51
+ $and 134
+ $dffe 4
+ $eq 86
+ $ge 2
+ $le 2
+ $logic_and 36
+ $logic_not 31
+ $logic_or 11
+ $lt 1
+ $meminit 1
+ $memrd_v2 1
+ $mul 1
+ $mux 475
+ $ne 19
+ $neg 6
+ $not 54
+ $or 71
+ $pmux 34
+ $reduce_and 16
+ $reduce_bool 22
+ $reduce_or 26
+ $reduce_xor 30
+ $scopeinfo 97
+ $shift 9
+ $shiftx 6
+ $shl 3
+ $shr 2
+ $sub 7
+ $xor 34
+
+3.106. Executing RS_DSP_MULTADD pass.
+
+3.107. Executing WREDUCE pass (reducing word size of cells).
+
+3.108. Executing RS_DSP_MACC pass.
+
+3.109. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.110. Executing TECHMAP pass (map to technology primitives).
+
+3.110.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation.
+Generating RTLIL representation for module `\_80_mul'.
+Generating RTLIL representation for module `\_90_soft_mul'.
+Successfully finished Verilog frontend.
+
+3.110.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.111. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 2052
+ Number of wire bits: 32757
+ Number of public wires: 1135
+ Number of public wire bits: 19171
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 1
+ Number of memory bits: 4096
+ Number of processes: 0
+ Number of cells: 1392
+ $__RS_MUL10X9 1
+ $add 94
+ $adff 26
+ $adffe 51
+ $and 134
+ $dffe 4
+ $eq 86
+ $ge 2
+ $le 2
+ $logic_and 36
+ $logic_not 31
+ $logic_or 11
+ $lt 1
+ $meminit 1
+ $memrd_v2 1
+ $mux 475
+ $ne 19
+ $neg 6
+ $not 54
+ $or 71
+ $pmux 34
+ $reduce_and 16
+ $reduce_bool 22
+ $reduce_or 26
+ $reduce_xor 30
+ $scopeinfo 97
+ $shift 9
+ $shiftx 6
+ $shl 3
+ $shr 2
+ $sub 7
+ $xor 34
+
+3.112. Executing TECHMAP pass (map to technology primitives).
+
+3.112.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp_check_maxwidth.v' to AST representation.
+Generating RTLIL representation for module `\_80_mul'.
+Generating RTLIL representation for module `\_90_soft_mul'.
+Successfully finished Verilog frontend.
+
+3.112.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.113. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 2052
+ Number of wire bits: 32757
+ Number of public wires: 1135
+ Number of public wire bits: 19171
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 1
+ Number of memory bits: 4096
+ Number of processes: 0
+ Number of cells: 1392
+ $__RS_MUL10X9 1
+ $add 94
+ $adff 26
+ $adffe 51
+ $and 134
+ $dffe 4
+ $eq 86
+ $ge 2
+ $le 2
+ $logic_and 36
+ $logic_not 31
+ $logic_or 11
+ $lt 1
+ $meminit 1
+ $memrd_v2 1
+ $mux 475
+ $ne 19
+ $neg 6
+ $not 54
+ $or 71
+ $pmux 34
+ $reduce_and 16
+ $reduce_bool 22
+ $reduce_or 26
+ $reduce_xor 30
+ $scopeinfo 97
+ $shift 9
+ $shiftx 6
+ $shl 3
+ $shr 2
+ $sub 7
+ $xor 34
+
+3.114. Executing TECHMAP pass (map to technology primitives).
+
+3.114.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp.v' to AST representation.
+Generating RTLIL representation for module `\_80_mul'.
+Generating RTLIL representation for module `\_90_soft_mul'.
+Successfully finished Verilog frontend.
+
+3.114.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.115. Executing TECHMAP pass (map to technology primitives).
+
+3.115.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/mul2dsp.v' to AST representation.
+Generating RTLIL representation for module `\_80_mul'.
+Generating RTLIL representation for module `\_90_soft_mul'.
+Successfully finished Verilog frontend.
+
+3.115.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.116. Executing TECHMAP pass (map to technology primitives).
+
+3.116.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_map.v' to AST representation.
+Generating RTLIL representation for module `\$__RS_MUL20X18'.
+Generating RTLIL representation for module `\$__RS_MUL10X9'.
+Successfully finished Verilog frontend.
+
+3.116.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.117. Executing RS_DSP_SIMD pass.
+
+3.118. Executing TECHMAP pass (map to technology primitives).
+
+3.118.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp_final_map.v' to AST representation.
+Generating RTLIL representation for module `\dsp_t1_20x18x64_cfg_ports'.
+Generating RTLIL representation for module `\dsp_t1_10x9x32_cfg_params'.
+Successfully finished Verilog frontend.
+
+3.118.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.119. Executing TECHMAP pass (map to technology primitives).
+
+3.119.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSP3'.
+Successfully finished Verilog frontend.
+
+3.119.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.120. Executing rs_pack_dsp_regs pass.
+
+
+3.121. Executing RS_DSP_IO_REGS pass.
+
+3.122. Executing TECHMAP pass (map to technology primitives).
+
+3.122.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp38_map.v' to AST representation.
+Generating RTLIL representation for module `\RS_DSP_MULTACC'.
+Generating RTLIL representation for module `\RS_DSP_MULT'.
+Generating RTLIL representation for module `\RS_DSP_MULT_REGIN'.
+Generating RTLIL representation for module `\RS_DSP_MULT_REGOUT'.
+Generating RTLIL representation for module `\RS_DSP_MULT_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSP_MULTADD'.
+Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN'.
+Generating RTLIL representation for module `\RS_DSP_MULTADD_REGOUT'.
+Generating RTLIL representation for module `\RS_DSP_MULTADD_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN'.
+Generating RTLIL representation for module `\RS_DSP_MULTACC_REGOUT'.
+Generating RTLIL representation for module `\RS_DSP_MULTACC_REGIN_REGOUT'.
+Successfully finished Verilog frontend.
+
+3.122.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.123. Executing TECHMAP pass (map to technology primitives).
+
+3.123.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/dsp19x2_map.v' to AST representation.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULT_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTADD_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGOUT'.
+Generating RTLIL representation for module `\RS_DSPX2_MULTACC_REGIN_REGOUT'.
+Generating RTLIL representation for module `\RS_DSP3'.
+Successfully finished Verilog frontend.
+
+3.123.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.124. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 2096
+ Number of wire bits: 33154
+ Number of public wires: 1135
+ Number of public wire bits: 19171
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 1
+ Number of memory bits: 4096
+ Number of processes: 0
+ Number of cells: 1392
+ $add 94
+ $adff 26
+ $adffe 51
+ $and 134
+ $dffe 4
+ $eq 86
+ $ge 2
+ $le 2
+ $logic_and 36
+ $logic_not 31
+ $logic_or 11
+ $lt 1
+ $meminit 1
+ $memrd_v2 1
+ $mux 475
+ $ne 19
+ $neg 6
+ $not 54
+ $or 71
+ $pmux 34
+ $reduce_and 16
+ $reduce_bool 22
+ $reduce_or 26
+ $reduce_xor 30
+ $scopeinfo 97
+ $shift 9
+ $shiftx 6
+ $shl 3
+ $shr 2
+ $sub 7
+ $xor 34
+ DSP19X2 1
+
+3.125. Executing ALUMACC pass (create $alu and $macc cells).
+Extracting $alu and $macc cells in module hmac:
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$502 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$503 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$504 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$505 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$506 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$507 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$508 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$509 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$510 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$511 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$512 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$513 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$514 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$515 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$516 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$517 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$518 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$519 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$520 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$521 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$522 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$523 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$524 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$525 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$526 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$527 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$528 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$529 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$530 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:334$536 ($add).
+ creating $macc model for $auto_5691 ($neg).
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+ creating $macc model for $flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1226 ($sub).
+ creating $macc model for $flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$920 ($add).
+ creating $macc model for $flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$915 ($add).
+ creating $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$501 ($add).
+ creating $macc model for $flatten\u_msg_fifo.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$930 ($neg).
+ creating $macc model for $flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:69$899 ($sub).
+ creating $macc model for $flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:70$900 ($sub).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$841 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$842 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$843 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$844 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$845 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$846 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$847 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$848 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$849 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$850 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$851 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$852 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$853 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$854 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$855 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$856 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$857 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$858 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$859 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$860 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$861 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$862 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$863 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$864 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$865 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$866 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$867 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$868 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$869 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$870 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871 ($add).
+ creating $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:62$773 ($add).
+ creating $macc model for $flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$775 ($sub).
+ creating $macc model for $flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$778 ($sub).
+ creating $macc model for $flatten\u_reg.\u_socket.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:106$1963 ($add).
+ creating $macc model for $flatten\u_reg.\u_socket.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:110$1964 ($sub).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$238 ($add).
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+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$240 ($add).
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+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:67$258 ($add).
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+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$463 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$464 ($add).
+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$286 ($add).
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+ creating $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$288 ($add).
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+ creating $macc model for $flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1086 ($add).
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+ creating $macc model for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1073 ($neg).
+ creating $macc model for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1078 ($neg).
+ creating $macc model for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1087 ($neg).
+ creating $macc model for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1096 ($neg).
+ merging $macc model for $flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1095 into $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1096.
+ merging $macc model for $flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1086 into $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1087.
+ merging $macc model for $flatten\u_tlul_adapter.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1077 into $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1078.
+ merging $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$463 into $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$464.
+ merging $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$462 into $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$464.
+ merging $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:67$258 into $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260.
+ merging $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$240 into $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241.
+ merging $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$239 into $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241.
+ merging $macc model for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$238 into $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$870 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$869 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$868 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$867 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$866 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$865 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$864 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$863 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$862 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$861 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$860 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$859 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$858 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$857 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$856 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$855 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$854 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$853 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$852 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$851 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$850 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$849 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$848 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$847 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$846 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$845 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$844 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$843 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$842 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$841 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871.
+ merging $macc model for $flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1225 into $flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1226.
+ merging $macc model for $flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:70$900 into $auto_5691.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$530 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$529 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$528 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$527 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$526 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$525 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$524 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$523 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$522 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$521 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$520 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$519 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$518 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$517 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$516 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$515 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$514 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$513 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$512 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$511 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$510 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$509 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$508 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$507 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$506 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$505 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$504 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$503 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$502 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$501 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531.
+ merging $macc model for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:323$531 into $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:334$536.
+ merging $macc model for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:54$871 into $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:62$773.
+ creating $alu model for $macc $flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:146$1256.
+ creating $alu model for $macc $flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$775.
+ creating $alu model for $macc $auto_5691.
+ creating $alu model for $macc $flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:175$1194.
+ creating $alu model for $macc $flatten\u_reg.\u_socket.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:106$1963.
+ creating $alu model for $macc $flatten\u_reg.\u_socket.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:110$1964.
+ creating $alu model for $macc $flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1224.
+ creating $alu model for $macc $flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$778.
+ creating $alu model for $macc $flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:69$899.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:72$259.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260.
+ creating $alu model for $macc $flatten\u_msg_fifo.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$930.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$286.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$287.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$288.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$289.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$290.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$291.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$292.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$293.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:138$298.
+ creating $alu model for $macc $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:150$302.
+ creating $alu model for $macc $flatten\u_sha2.\u_pad.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:304$1650.
+ creating $alu model for $macc $flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$915.
+ creating $alu model for $macc $flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$920.
+ creating $alu model for $macc $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1073.
+ creating $macc cell for $flatten\u_packer.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:62$773: $auto_6087
+ creating $macc cell for $add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac.sv:334$536: $auto_6088
+ creating $macc cell for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1096: $auto_6089
+ creating $macc cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:64$241: $auto_6090
+ creating $macc cell for $flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1226: $auto_6091
+ creating $macc cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:86$464: $auto_6092
+ creating $macc cell for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1078: $auto_6093
+ creating $macc cell for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1087: $auto_6094
+ creating $alu model for $flatten\u_hmac.$ge$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:238$1204 ($ge): new $alu
+ creating $alu model for $flatten\u_packer.$ge$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:208$835 ($ge): new $alu
+ creating $alu model for $flatten\u_packer.$le$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:216$837 ($le): merged with $flatten\u_packer.$ge$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:208$835.
+ creating $alu model for $flatten\u_packer.$le$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$777 ($le): new $alu
+ creating $alu model for $flatten\u_sha2.$lt$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:266$316 ($lt): new $alu
+ creating $alu cell for $flatten\u_sha2.$lt$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:266$316: $auto_6099
+ creating $alu cell for $flatten\u_packer.$le$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$777: $auto_6104
+ creating $alu cell for $flatten\u_packer.$ge$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:208$835, $flatten\u_packer.$le$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:216$837: $auto_6117
+ creating $alu cell for $flatten\u_hmac.$ge$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:238$1204: $auto_6132
+ creating $alu cell for $flatten\u_tlul_adapter.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_adapter_sram.sv:0$1073: $auto_6145
+ creating $alu cell for $flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:101$920: $auto_6148
+ creating $alu cell for $flatten\u_msg_fifo.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:87$915: $auto_6151
+ creating $alu cell for $flatten\u_sha2.\u_pad.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2_pad.sv:304$1650: $auto_6154
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:150$302: $auto_6157
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:138$298: $auto_6160
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$293: $auto_6163
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$292: $auto_6166
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$291: $auto_6169
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$290: $auto_6172
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$289: $auto_6175
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$288: $auto_6178
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$287: $auto_6181
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/sha2.sv:123$286: $auto_6184
+ creating $alu cell for $flatten\u_msg_fifo.$neg$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:0$930: $auto_6187
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:76$260: $auto_6190
+ creating $alu cell for $flatten\u_sha2.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_pkg.sv:72$259: $auto_6193
+ creating $alu cell for $flatten\u_msg_fifo.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_fifo_sync.sv:69$899: $auto_6196
+ creating $alu cell for $flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:68$778: $auto_6199
+ creating $alu cell for $flatten\u_hmac.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1224: $auto_6202
+ creating $alu cell for $flatten\u_reg.\u_socket.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:110$1964: $auto_6205
+ creating $alu cell for $flatten\u_reg.\u_socket.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/tlul_socket_1n.sv:106$1963: $auto_6208
+ creating $alu cell for $flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:175$1194: $auto_6211
+ creating $alu cell for $auto_5691: $auto_6214
+ creating $alu cell for $flatten\u_packer.$sub$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/prim_packer.sv:66$775: $auto_6217
+ creating $alu cell for $flatten\u_hmac.$add$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:146$1256: $auto_6220
+ created 30 $alu and 8 $macc cells.
+
+3.126. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+
+3.127. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.128. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.129. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.130. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.131. Executing OPT_SHARE pass.
+
+3.132. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=81, #solve=0, #remove=0, time=0.48 sec.]
+
+3.133. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 74 unused cells and 128 unused wires.
+
+
+3.134. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.135. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.136. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.137. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.138. Executing OPT_SHARE pass.
+
+3.139. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=81, #solve=0, #remove=0, time=0.50 sec.]
+
+3.140. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.141. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+RUN-OPT ITERATIONS DONE : 2
+
+3.142. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 2049
+ Number of wire bits: 32075
+ Number of public wires: 1133
+ Number of public wire bits: 19159
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 1
+ Number of memory bits: 4096
+ Number of processes: 0
+ Number of cells: 1333
+ $adff 26
+ $adffe 51
+ $alu 30
+ $and 134
+ $dffe 4
+ $eq 85
+ $logic_and 36
+ $logic_not 31
+ $logic_or 11
+ $macc 8
+ $meminit 1
+ $memrd_v2 1
+ $mux 475
+ $ne 18
+ $not 61
+ $or 74
+ $pmux 34
+ $reduce_and 19
+ $reduce_bool 22
+ $reduce_or 30
+ $reduce_xor 30
+ $scopeinfo 97
+ $shift 9
+ $shiftx 6
+ $shl 3
+ $shr 2
+ $xor 34
+ DSP19X2 1
+
+3.143. Executing MEMORY pass.
+
+3.143.1. Executing OPT_MEM pass (optimize memories).
+Performed a total of 0 transformations.
+
+3.143.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
+Performed a total of 0 transformations.
+
+3.143.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
+
+3.143.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
+
+3.143.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
+Checking read port `$flatten\u_reg.$auto_1966'[0] in module `\hmac': no output FF found.
+Checking read port address `$flatten\u_reg.$auto_1966'[0] in module `\hmac': no address FF found.
+
+3.143.6. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.143.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
+
+3.143.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
+Performed a total of 0 transformations.
+
+3.143.9. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.143.10. Executing MEMORY_COLLECT pass (generating $mem cells).
+
+3.144. Printing statistics.
+
+=== hmac ===
+
+ Number of wires: 2049
+ Number of wire bits: 32075
+ Number of public wires: 1133
+ Number of public wire bits: 19159
+ Number of ports: 10
+ Number of port bits: 187
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 1332
+ $adff 26
+ $adffe 51
+ $alu 30
+ $and 134
+ $dffe 4
+ $eq 85
+ $logic_and 36
+ $logic_not 31
+ $logic_or 11
+ $macc 8
+ $mem_v2 1
+ $mux 475
+ $ne 18
+ $not 61
+ $or 74
+ $pmux 34
+ $reduce_and 19
+ $reduce_bool 22
+ $reduce_or 30
+ $reduce_xor 30
+ $scopeinfo 97
+ $shift 9
+ $shiftx 6
+ $shl 3
+ $shr 2
+ $xor 34
+ DSP19X2 1
+
+3.145. Executing MUXPACK pass ($mux cell cascades to $pmux).
+Converting hmac.$flatten\u_hmac.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:123$1235 ... hmac.$flatten\u_hmac.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:121$1237 to a pmux with 3 cases.
+Converting hmac.$flatten\u_reg.$procmux$2353 ... hmac.$flatten\u_reg.$procmux$2403 to a pmux with 26 cases.
+Converting hmac.$flatten\u_reg.$procmux$2408 ... hmac.$flatten\u_reg.$procmux$2458 to a pmux with 26 cases.
+Converting hmac.$flatten\u_reg.$procmux$2463 ... hmac.$flatten\u_reg.$procmux$2513 to a pmux with 26 cases.
+Converting hmac.$flatten\u_reg.$procmux$2518 ... hmac.$flatten\u_reg.$procmux$2568 to a pmux with 26 cases.
+Converting hmac.$flatten\u_reg.$procmux$2573 ... hmac.$flatten\u_reg.$procmux$2611 to a pmux with 20 cases.
+Converting hmac.$flatten\u_reg.$procmux$2613 ... hmac.$flatten\u_reg.$procmux$2623 to a pmux with 6 cases.
+Converting hmac.$flatten\u_reg.$procmux$2628 ... hmac.$flatten\u_reg.$procmux$2678 to a pmux with 26 cases.
+Converted 159 (p)mux cells into 8 pmux cells.
+
+
+3.146. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 0 unused cells and 151 unused wires.
+
+
+3.147. Executing MEMORY_LIBMAP pass (mapping memories to cells).
+
+3.148. Executing MEMORY_LIBMAP pass (mapping memories to cells).
+Warning: Asyncronous read in BRAM is not supported, memory will be mapped to soft logic.
+found attribute 'ram_block = logic' on memory hmac.$flatten\u_reg.$auto_1966, forced mapping to FF
+using FF mapping for memory hmac.$flatten\u_reg.$auto_1966
+
+3.149. Executing Rs_BRAM_Split pass.
+
+3.150. Executing TECHMAP pass (map to technology primitives).
+
+3.150.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v' to AST representation.
+Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_TDP'.
+Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_TDP'.
+Generating RTLIL representation for module `\$__RS_FACTOR_BRAM18_SDP'.
+Generating RTLIL representation for module `\$__RS_FACTOR_BRAM36_SDP'.
+Successfully finished Verilog frontend.
+
+3.150.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.151. Executing TECHMAP pass (map to technology primitives).
+
+3.151.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v' to AST representation.
+Generating RTLIL representation for module `\BRAM2x18_TDP'.
+Generating RTLIL representation for module `\BRAM2x18_SDP'.
+Successfully finished Verilog frontend.
+
+3.151.2. Continuing TECHMAP pass.
+No more expansions possible.
+
+
+3.152. Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs).
+
+3.153. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.154. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.155. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.156. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+ New ctrl vector for $pmux cell $flatten\u_reg.$procmux$2353: { \u_reg.addr_hit [17] $auto_6242 \u_reg.addr_hit [25] \u_reg.addr_hit [26] }
+ New ctrl vector for $pmux cell $flatten\u_reg.$procmux$2408: { \u_reg.addr_hit [4] \u_reg.addr_hit [17] $auto_6244 \u_reg.addr_hit [25] \u_reg.addr_hit [26] }
+ New ctrl vector for $pmux cell $flatten\u_reg.$procmux$2463: { \u_reg.addr_hit [4] \u_reg.addr_hit [7] \u_reg.addr_hit [17] $auto_6246 \u_reg.addr_hit [25] \u_reg.addr_hit [26] }
+ New ctrl vector for $pmux cell $flatten\u_reg.$procmux$2518: { \u_reg.addr_hit [4] \u_reg.addr_hit [6] \u_reg.addr_hit [7] \u_reg.addr_hit [17] $auto_6248 \u_reg.addr_hit [25] \u_reg.addr_hit [26] }
+ New ctrl vector for $pmux cell $flatten\u_reg.$procmux$2573: { \u_reg.addr_hit [17] $auto_6250 \u_reg.addr_hit [25] \u_reg.addr_hit [26] }
+ New ctrl vector for $pmux cell $flatten\u_reg.$procmux$2613: { $auto_6252 \u_reg.addr_hit [6] }
+ New ctrl vector for $pmux cell $flatten\u_reg.$procmux$2628: { \u_reg.addr_hit [4] \u_reg.addr_hit [6] \u_reg.addr_hit [7] \u_reg.addr_hit [17] $auto_6254 \u_reg.addr_hit [25] \u_reg.addr_hit [26] }
+ Optimizing cells in module \hmac.
+Performed a total of 7 changes.
+
+3.157. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+
+Removed a total of 1 cells.
+
+3.158. Executing OPT_SHARE pass.
+ Found cells that share an operand and can be merged by moving the $pmux $flatten\u_hmac.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:123$1235 in front of them:
+ $flatten\u_hmac.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:0$1233
+ $flatten\u_hmac.$shiftx$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:0$1227
+
+3.159. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=81, #solve=0, #remove=0, time=0.44 sec.]
+
+3.160. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+Removed 0 unused cells and 3 unused wires.
+
+
+3.161. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.162. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.163. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+ New ctrl vector for $pmux cell $flatten\u_hmac.$ternary$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:123$1235: { $auto_6259 $flatten\u_hmac.$eq$/nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/rtl/hmac_core.sv:123$1234_Y }
+ Optimizing cells in module \hmac.
+Performed a total of 1 changes.
+
+3.164. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.165. Executing OPT_SHARE pass.
+
+3.166. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=81, #solve=0, #remove=0, time=0.42 sec.]
+
+3.167. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.168. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+3.169. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \hmac..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+
+
+3.170. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \hmac.
+Performed a total of 0 changes.
+
+3.171. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\hmac'.
+Removed a total of 0 cells.
+
+3.172. Executing OPT_SHARE pass.
+
+3.173. Executing OPT_DFF pass (perform DFF optimizations).
+[#visit=81, #solve=0, #remove=0, time=0.41 sec.]
+
+3.174. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \hmac..
+
+3.175. Executing OPT_EXPR pass (perform const folding).
+Optimizing module hmac.
+
+RUN-OPT ITERATIONS DONE : 3
+
+3.176. Executing PMUXTREE pass.
+
+3.177. Executing MUXPACK pass ($mux cell cascades to $pmux).
+Converting hmac.$auto_6650 ... hmac.$auto_6652 to a pmux with 2 cases.
+Converting hmac.$auto_6638 ... hmac.$auto_6640 to a pmux with 2 cases.
+Converting hmac.$auto_6628 ... hmac.$auto_6630 to a pmux with 2 cases.
+Converting hmac.$auto_6576 ... hmac.$auto_6578 to a pmux with 2 cases.
+Converting hmac.$auto_6496 ... hmac.$auto_6498 to a pmux with 2 cases.
+Converting hmac.$auto_6450 ... hmac.$auto_6452 to a pmux with 2 cases.
+Converting hmac.$auto_6438 ... hmac.$auto_6440 to a pmux with 2 cases.
+Converting hmac.$auto_6434 ... hmac.$auto_6436 to a pmux with 2 cases.
+Converting hmac.$auto_6422 ... hmac.$auto_6424 to a pmux with 2 cases.
+Converting hmac.$auto_6408 ... hmac.$auto_6410 to a pmux with 2 cases.
+Converting hmac.$auto_6404 ... hmac.$auto_6406 to a pmux with 2 cases.
+Converting hmac.$auto_6386 ... hmac.$auto_6388 to a pmux with 2 cases.
+Converting hmac.$auto_6370 ... hmac.$auto_6372 to a pmux with 2 cases.
+Converted 26 (p)mux cells into 13 pmux cells.
+
+
+3.178. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
+Mapping memory $flatten\u_reg.$auto_1966 in module \hmac:
+ created 4096 $dff cells and 0 static cells of width 1.
+ read interface: 0 $dff and 4095 $mux cells.
+ write interface: 0 write mux blocks.
+Memory $flatten\u_reg.$auto_1966 type : dissolved
+
+3.179. Executing TECHMAP pass (map to technology primitives).
+
+3.179.1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/techmap.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/techmap.v' to AST representation.
+Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
+Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
+Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
+Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
+Generating RTLIL representation for module `\_90_simplemap_various'.
+Generating RTLIL representation for module `\_90_simplemap_registers'.
+Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
+Generating RTLIL representation for module `\_90_shift_shiftx'.
+Generating RTLIL representation for module `\_90_fa'.
+Generating RTLIL representation for module `\_90_lcu_brent_kung'.
+Generating RTLIL representation for module `\_90_alu'.
+Generating RTLIL representation for module `\_90_macc'.
+Generating RTLIL representation for module `\_90_alumacc'.
+Generating RTLIL representation for module `\$__div_mod_u'.
+Generating RTLIL representation for module `\$__div_mod_trunc'.
+Generating RTLIL representation for module `\_90_div'.
+Generating RTLIL representation for module `\_90_mod'.
+Generating RTLIL representation for module `\$__div_mod_floor'.
+Generating RTLIL representation for module `\_90_divfloor'.
+Generating RTLIL representation for module `\_90_modfloor'.
+Generating RTLIL representation for module `\_90_pow'.
+Generating RTLIL representation for module `\_90_pmux'.
+Generating RTLIL representation for module `\_90_demux'.
+Generating RTLIL representation for module `\_90_lut'.
+Successfully finished Verilog frontend.
+
+3.179.2. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v
+Parsing Verilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/../share/yosys/rapidsilicon/genesis3/arith_map.v' to AST representation.
+Generating RTLIL representation for module `\_80_rs_alu'.
+Successfully finished Verilog frontend.
+
+3.179.3. Continuing TECHMAP pass.
+Using extmapper simplemap for cells of type $adffe.
+Using extmapper simplemap for cells of type $mux.
+Using extmapper simplemap for cells of type $adff.
+Using extmapper simplemap for cells of type $or.
+Using extmapper simplemap for cells of type $not.
+Using extmapper simplemap for cells of type $logic_not.
+Using extmapper simplemap for cells of type $logic_and.
+Using extmapper simplemap for cells of type $eq.
+Using extmapper simplemap for cells of type $and.
+Analyzing pattern of constant bits for this cell:
+ Constant input on bit 0 of port A: 1'1
+ Constant input on bit 1 of port A: 1'1
+ Constant input on bit 2 of port A: 1'1
+ Constant input on bit 3 of port A: 1'1
+ Constant input on bit 4 of port A: 1'1
+ Constant input on bit 5 of port A: 1'1
+ Constant input on bit 6 of port A: 1'1
+ Constant input on bit 7 of port A: 1'1
+Creating constmapped module `$paramod$constmap:5804069588edb7ff25baa001bebacc87928895c1$paramod$f510a8f4abd4276a0075f18cd429675e9cfe270f\_90_shift_shiftx'.
+
+3.179.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module $paramod$constmap:5804069588edb7ff25baa001bebacc87928895c1$paramod$f510a8f4abd4276a0075f18cd429675e9cfe270f\_90_shift_shiftx..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+ dead port 2/2 on $mux $procmux$20529.
+ dead port 2/2 on $mux $procmux$20523.
+ dead port 2/2 on $mux $procmux$20517.
+ dead port 2/2 on $mux $procmux$20511.
+ dead port 2/2 on $mux $procmux$20505.
+ dead port 2/2 on $mux $procmux$20499.
+Removed 6 multiplexer ports.
+
+
+3.179.20. Executing OPT_EXPR pass (perform const folding).
+Optimizing module $paramod$constmap:5804069588edb7ff25baa001bebacc87928895c1$paramod$f510a8f4abd4276a0075f18cd429675e9cfe270f\_90_shift_shiftx.
+
+Removed 0 unused cells and 10 unused wires.
+Using extmapper simplemap for cells of type $ne.
+Using extmapper simplemap for cells of type $logic_or.
+Using extmapper simplemap for cells of type $reduce_or.
+Using extmapper simplemap for cells of type $reduce_and.
+Using extmapper simplemap for cells of type $xor.
+
+ERROR: TIM: Design Compilation took 480m. Exiting due to timeout
diff --git a/EDA-3283/results_dir/raptor_cmd.tcl b/EDA-3283/results_dir/raptor_cmd.tcl
new file mode 100644
index 00000000..094004d7
--- /dev/null
+++ b/EDA-3283/results_dir/raptor_cmd.tcl
@@ -0,0 +1,23 @@
+# /*******************************************************************************
+# Copyright (c) 2022-2024 Rapid Silicon
+# This source code contains proprietary information belonging to Rapid Silicon
+# (the "licensor") released under license and non-disclosure agreement to the
+# recipient (the "licensee").
+# The information shared and protected by the license and non-disclosure agreement
+# includes but is not limited to the following:
+# * operational algorithms of the product
+# * logos, graphics, source code, and visual presentation of the product
+# * confidential operational information of the licensor
+# The recipient of this source code is NOT permitted to publicly disclose,
+# re-use, archive beyond the period of the license agreement, transfer to a
+# sub-licensee, or re-implement any portion of the content covered by the license
+# and non-disclosure agreement without the prior written consent of the licensor.
+# *********************************************************************************/
+# Version : 2024.10
+# Build : 1.2.12
+# Hash : 6f00985
+# Date : Oct 1 2024
+# Type : Engineering
+# Log Time : Tue Oct 1 20:40:37 2024 GMT
+source /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/etc/init/flow.tcl
+source /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/share/raptor/etc/init/sim_helpers.tcl
diff --git a/EDA-3283/results_dir/raptor_perf.log b/EDA-3283/results_dir/raptor_perf.log
new file mode 100644
index 00000000..58aac538
--- /dev/null
+++ b/EDA-3283/results_dir/raptor_perf.log
@@ -0,0 +1,33 @@
+/*******************************************************************************
+Copyright (c) 2022-2024 Rapid Silicon
+This source code contains proprietary information belonging to Rapid Silicon
+(the "licensor") released under license and non-disclosure agreement to the
+recipient (the "licensee").
+
+The information shared and protected by the license and non-disclosure agreement
+includes but is not limited to the following:
+* operational algorithms of the product
+* logos, graphics, source code, and visual presentation of the product
+* confidential operational information of the licensor
+
+The recipient of this source code is NOT permitted to publicly disclose,
+re-use, archive beyond the period of the license agreement, transfer to a
+sub-licensee, or re-implement any portion of the content covered by the license
+and non-disclosure agreement without the prior written consent of the licensor.
+*********************************************************************************/
+
+Version : 2024.10
+Build : 1.2.12
+Hash : 6f00985
+Date : Oct 1 2024
+Type : Engineering
+Log Time : Tue Oct 1 20:40:37 2024 GMT
+
+[ 01:40:38 ] Analysis has started
+[ 01:40:38 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/yosys -s /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/hmac_analyzer.cmd
+[ 01:40:38 ] Duration: 93 ms. Max utilization: 35 MB
+[ 01:40:38 ] Analysis has started
+[ 01:40:38 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/yosys -s /nfs_scratch/scratch/CGA/repo/2024-10-01-23-30-48_T12181R18/Validation/RTL_testcases/RTL_Benchmarks_Gap_Analysis/hmac/results_dir/hmac/run_1/synth_1_1/analysis/hmac_analyzer.cmd
+[ 01:41:06 ] Duration: 27677 ms. Max utilization: 1018 MB
+[ 01:41:06 ] Synthesize has started
+[ 01:41:06 ] Command: /nfs_eda_sw/softwares/Raptor/instl_dir/10_01_2024_09_15_02/bin/yosys -s hmac.ys -l hmac_synth.log
diff --git a/EDA-3283/rtl/ast_pkg.sv b/EDA-3283/rtl/ast_pkg.sv
new file mode 100644
index 00000000..3ab32756
--- /dev/null
+++ b/EDA-3283/rtl/ast_pkg.sv
@@ -0,0 +1,165 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//############################################################################
+// *Name: ast_pkg
+// *Module Description: AST Package
+//############################################################################
+`ifdef __AST_PKG_SV
+`else
+`define __AST_PKG_SV
+
+package ast_pkg;
+
+// Alerts
+parameter int unsigned NumAlerts = 13;
+parameter int unsigned NumIoRails = 2;
+parameter int unsigned AsSel = 0;
+parameter int unsigned CgSel = 1;
+parameter int unsigned GdSel = 2;
+parameter int unsigned TsHiSel = 3;
+parameter int unsigned TsLoSel = 4;
+parameter int unsigned FlaSel = 5;
+parameter int unsigned OtpSel = 6;
+parameter int unsigned Ot0Sel = 7;
+parameter int unsigned Ot1Sel = 8;
+parameter int unsigned Ot2Sel = 9;
+parameter int unsigned Ot3Sel = 10;
+parameter int unsigned Ot4Sel = 11;
+parameter int unsigned Ot5Sel = 12;
+//
+parameter int unsigned Lc2HcTrCyc = 104; // (100+4)x5 = 520 us
+parameter int unsigned Hc2LcTrCyc = 40; // (36+4)x5 = 200 us
+//
+parameter int unsigned EntropyStreams = 4;
+parameter int unsigned AdcChannels = 2;
+parameter int unsigned AdcDataWidth = 10;
+parameter int unsigned UsbCalibWidth = 20;
+parameter int unsigned Ast2PadOutWidth = 9;
+parameter int unsigned Pad2AstInWidth = 9;
+
+// These LFSR parameters have been generated with
+// $ ./util/design/gen-lfsr-seed.py --width 64 --seed 691876113 --prefix ""
+parameter int LfsrWidth = 64;
+typedef logic [LfsrWidth-1:0] lfsr_seed_t;
+typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
+parameter lfsr_seed_t RndCnstLfsrSeedDefault = 64'h22d326255bd24320;
+parameter lfsr_perm_t RndCnstLfsrPermDefault = {
+ 128'h16108c9f9008aa37e5118d1ec1df64a7,
+ 256'h24f3f1b73537f42d38383ee8f897286df81d49ab54b6bbbb666cbd1a16c41252
+};
+
+// Memories Read-Write Margin Interface
+typedef struct packed {
+ logic marg_en_a;
+ logic [4-1:0] marg_a;
+ logic marg_en_b;
+ logic [4-1:0] marg_b;
+} dpm_rm_t;
+
+typedef struct packed {
+ logic marg_en;
+ logic [4-1:0] marg;
+} spm_rm_t;
+
+// ADC Interface
+typedef struct packed {
+ logic [AdcChannels-1:0] channel_sel;
+ logic pd;
+} adc_ast_req_t;
+
+typedef struct packed {
+ logic [AdcDataWidth-1:0] data;
+ logic data_valid;
+} adc_ast_rsp_t;
+
+// Analog Signal
+ `ifdef ANALOGSIM
+typedef real awire_t;
+ `else
+typedef logic awire_t;
+ `endif
+
+// Clock & Resets Interface
+typedef struct packed {
+ logic clk_sys;
+ logic clk_io;
+ logic clk_usb;
+ logic clk_aon;
+} ast_clks_t;
+
+typedef struct packed {
+ logic aon_pok;
+} ast_rst_t;
+
+parameter ast_rst_t AST_RST_DEFAULT = '{
+ aon_pok: 1'b1
+};
+
+typedef struct packed {
+ logic [NumIoRails-1:0] io_pok;
+} ast_status_t;
+
+typedef struct packed {
+ logic aon_pok;
+ logic vcc_pok;
+ logic main_pok;
+ logic [NumIoRails-1:0] io_pok;
+} ast_pwst_t;
+
+// Alerts Interface
+typedef struct packed {
+ logic p;
+ logic n;
+} ast_dif_t;
+
+typedef struct packed {
+ ast_dif_t [NumAlerts-1:0] alerts;
+} ast_alert_req_t;
+
+typedef struct packed {
+ ast_dif_t [NumAlerts-1:0] alerts_ack;
+ ast_dif_t [NumAlerts-1:0] alerts_trig;
+} ast_alert_rsp_t;
+
+// Ack mode enumerations
+typedef enum logic {
+ ImmAck = 0,
+ SwAck = 1
+} ast_ack_mode_e;
+
+// Clocks Oschillator Bypass
+typedef struct packed {
+ logic usb;
+ logic sys;
+ logic io;
+ logic aon;
+} clks_osc_byp_t;
+
+typedef enum logic [4-1:0] {
+ ObsNon = 4'h0, // No module observed (disable)
+ ObsAst = 4'h1, // Observe AST
+ ObsFla = 4'h2, // Observe FLASH
+ ObsOtp = 4'h3, // Observe OTP
+ ObsOt0 = 4'h4, // Observe OT0
+ ObsOt1 = 4'h5, // Observe OT1
+ ObsOt2 = 4'h6, // Observe OT2
+ ObsOt3 = 4'h7, // Observe OT3
+ ObsRs0 = 4'h8, // RESERVED
+ ObsRs1 = 4'h9, // RESERVED
+ ObsRs2 = 4'hA, // RESERVED
+ ObsRs3 = 4'hB, // RESERVED
+ ObsRs4 = 4'hC, // RESERVED
+ ObsRs5 = 4'hD, // RESERVED
+ ObsRs6 = 4'hE, // RESERVED
+ ObsRs7 = 4'hF // RESERVED
+} ast_omdl_e;
+
+typedef struct packed {
+ logic [4-1:0] obgsl;
+ ast_omdl_e obmsl;
+ prim_mubi_pkg::mubi4_t obmen;
+} ast_obs_ctrl_t;
+
+endpackage // of ast_pkg
+`endif // of __AST_PKG_SV
diff --git a/EDA-3283/rtl/edn_pkg.sv b/EDA-3283/rtl/edn_pkg.sv
new file mode 100644
index 00000000..b156b0a3
--- /dev/null
+++ b/EDA-3283/rtl/edn_pkg.sv
@@ -0,0 +1,35 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+//`include "entropy_src_pkg.sv"
+package edn_pkg;
+ ///////////////////////////
+ // Peripheral Interfaces //
+ ///////////////////////////
+
+ parameter int unsigned ENDPOINT_BUS_WIDTH = 32;
+ parameter int unsigned FIPS_ENDPOINT_BUS_WIDTH = entropy_src_pkg::FIPS_BUS_WIDTH +
+ ENDPOINT_BUS_WIDTH;
+
+ // EDN request interface
+ typedef struct packed {
+ logic edn_req;
+ } edn_req_t;
+ typedef struct packed {
+ logic edn_ack;
+ logic edn_fips;
+ logic [ENDPOINT_BUS_WIDTH-1:0] edn_bus;
+ } edn_rsp_t;
+
+ parameter edn_req_t EDN_REQ_DEFAULT = '0;
+ parameter edn_rsp_t EDN_RSP_DEFAULT = '0;
+
+ // Sparse four-value signal type
+ parameter int EDN_MODE_WIDTH = 4;
+ typedef enum logic [EDN_MODE_WIDTH-1:0] {
+ EDN_FIELD_ON = 4'b1010
+ } edn_enb_e;
+
+endpackage : edn_pkg
diff --git a/EDA-3283/rtl/entropy_src_pkg.sv b/EDA-3283/rtl/entropy_src_pkg.sv
new file mode 100644
index 00000000..69cc8425
--- /dev/null
+++ b/EDA-3283/rtl/entropy_src_pkg.sv
@@ -0,0 +1,66 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+
+package entropy_src_pkg;
+
+ //-------------------------
+ // Entropy Interface
+ //-------------------------
+
+ parameter int RNG_BUS_WIDTH = 4;
+ parameter int CSRNG_BUS_WIDTH = 384;
+ parameter int FIPS_BUS_WIDTH = 1;
+
+ // es entropy i/f
+ typedef struct packed {
+ logic es_ack;
+ logic [CSRNG_BUS_WIDTH-1:0] es_bits;
+ logic [FIPS_BUS_WIDTH-1:0] es_fips;
+ } entropy_src_hw_if_rsp_t;
+
+ typedef struct packed {
+ logic es_req;
+ } entropy_src_hw_if_req_t;
+
+ parameter entropy_src_hw_if_req_t ENTROPY_SRC_HW_IF_REQ_DEFAULT = '{default: '0};
+ parameter entropy_src_hw_if_rsp_t ENTROPY_SRC_HW_IF_RSP_DEFAULT = '{default: '0};
+
+
+ // ast rng i/f
+ typedef struct packed {
+ logic rng_enable;
+ } entropy_src_rng_req_t;
+
+ typedef struct packed {
+ logic rng_valid;
+ logic [RNG_BUS_WIDTH-1:0] rng_b;
+ } entropy_src_rng_rsp_t;
+
+ parameter entropy_src_rng_req_t ENTROPY_SRC_RNG_REQ_DEFAULT = '{default: '0};
+ parameter entropy_src_rng_rsp_t ENTROPY_SRC_RNG_RSP_DEFAULT = '{default: '0};
+
+ // external health test i/f
+ typedef struct packed {
+ logic [RNG_BUS_WIDTH-1:0] entropy_bit;
+ logic entropy_bit_valid;
+ logic clear;
+ logic active;
+ logic [15:0] thresh_hi;
+ logic [15:0] thresh_lo;
+ logic [15:0] window;
+ } entropy_src_xht_req_t;
+
+ typedef struct packed {
+ logic[15:0] test_cnt;
+ logic test_fail_hi_pulse;
+ logic test_fail_lo_pulse;
+ } entropy_src_xht_rsp_t;
+
+ parameter entropy_src_xht_req_t ENTROPY_SRC_XHT_REQ_DEFAULT = '{default: '0};
+ parameter entropy_src_xht_rsp_t ENTROPY_SRC_XHT_RSP_DEFAULT = '{default: '0};
+
+
+endpackage : entropy_src_pkg
diff --git a/EDA-3283/rtl/flash_ctrl_pkg.sv b/EDA-3283/rtl/flash_ctrl_pkg.sv
new file mode 100644
index 00000000..c81589d3
--- /dev/null
+++ b/EDA-3283/rtl/flash_ctrl_pkg.sv
@@ -0,0 +1,597 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Flash Controller module.
+//
+
+package flash_ctrl_pkg;
+
+ // design parameters that can be altered through topgen
+ parameter int unsigned NumBanks = flash_ctrl_reg_pkg::RegNumBanks;
+ parameter int unsigned PagesPerBank = flash_ctrl_reg_pkg::RegPagesPerBank;
+ parameter int unsigned BusPgmResBytes = flash_ctrl_reg_pkg::RegBusPgmResBytes;
+
+ // fixed parameters of flash derived from topgen parameters
+ parameter int DataWidth = 64;
+ parameter int MetaDataWidth = 12;
+ parameter int InfoTypes = 3; // How many types of info per bank
+
+// The following hard-wired values are there to work-around verilator.
+// For some reason if the values are assigned through parameters verilator thinks
+// they are not constant
+ parameter int InfoTypeSize [InfoTypes] = '{
+ 10,
+ 1,
+ 2
+ };
+ parameter int InfosPerBank = max_info_pages('{
+ 10,
+ 1,
+ 2
+ });
+ parameter int WordsPerPage = 256; // Number of flash words per page
+ parameter int BusWidth = top_pkg::TL_DW;
+ parameter int MpRegions = 8; // flash controller protection regions
+ parameter int FifoDepth = 16; // rd / prog fifos
+ parameter int InfoTypesWidth = prim_util_pkg::vbits(InfoTypes);
+
+ // flash phy parameters
+ parameter int DataByteWidth = prim_util_pkg::vbits(DataWidth / 8);
+ parameter int BankW = prim_util_pkg::vbits(NumBanks);
+ parameter int InfoPageW = prim_util_pkg::vbits(InfosPerBank);
+ parameter int PageW = prim_util_pkg::vbits(PagesPerBank);
+ parameter int WordW = prim_util_pkg::vbits(WordsPerPage);
+ parameter int AddrW = BankW + PageW + WordW; // all flash range
+ parameter int BankAddrW = PageW + WordW; // 1 bank of flash range
+ parameter int AllPagesW = BankW + PageW;
+
+ // flash ctrl / bus parameters
+ // flash / bus width may be different from actual flash word width
+ parameter int BusBytes = BusWidth / 8;
+ parameter int BusByteWidth = prim_util_pkg::vbits(BusBytes);
+ parameter int WidthMultiple = DataWidth / BusWidth;
+ // Number of bus words that can be programmed at once
+ parameter int BusPgmRes = BusPgmResBytes / BusBytes;
+ parameter int BusPgmResWidth = prim_util_pkg::vbits(BusPgmRes);
+ parameter int BusWordsPerPage = WordsPerPage * WidthMultiple;
+ parameter int BusWordW = prim_util_pkg::vbits(BusWordsPerPage);
+ parameter int BusAddrW = BankW + PageW + BusWordW;
+ parameter int BusAddrByteW = BusAddrW + BusByteWidth;
+ parameter int BusBankAddrW = PageW + BusWordW;
+ parameter int PhyAddrStart = BusWordW - WordW;
+
+
+ // fifo parameters
+ parameter int FifoDepthW = prim_util_pkg::vbits(FifoDepth+1);
+
+ // The end address in bus words for each kind of partition in each bank
+ parameter logic [PageW-1:0] DataPartitionEndAddr = PageW'(PagesPerBank - 1);
+ //parameter logic [PageW-1:0] InfoPartitionEndAddr [InfoTypes] = '{
+ // 9,
+ // 0,
+ // 1
+ //};
+ parameter logic [PageW-1:0] InfoPartitionEndAddr [InfoTypes] = '{
+ PageW'(InfoTypeSize[0] - 1),
+ PageW'(InfoTypeSize[1] - 1),
+ PageW'(InfoTypeSize[2] - 1)
+ };
+
+ ////////////////////////////
+ // All memory protection, seed related parameters
+ // Those related for seed pages should be template candidates
+ ////////////////////////////
+
+ // parameters for connected components
+ parameter int SeedWidth = 256;
+ parameter int KeyWidth = 128;
+ parameter int EdnWidth = edn_pkg::ENDPOINT_BUS_WIDTH;
+ typedef logic [KeyWidth-1:0] flash_key_t;
+
+ // Default Lfsr configurations
+ // These LFSR parameters have been generated with
+ // $ util/design/gen-lfsr-seed.py --width 32 --seed 1274809145 --prefix ""
+ parameter int LfsrWidth = 32;
+ typedef logic [LfsrWidth-1:0] lfsr_seed_t;
+ typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
+ parameter lfsr_seed_t RndCnstLfsrSeedDefault = 32'ha8cee782;
+ parameter lfsr_perm_t RndCnstLfsrPermDefault = {
+ 160'hd60bc7d86445da9347e0ccdd05b281df95238bb5
+ };
+
+ // These LFSR parameters have been generated with
+ // $ util/design/gen-lfsr-seed.py --width 64 --seed 691876113 --prefix ""
+
+
+ // lcmgr phase enum
+ typedef enum logic [1:0] {
+ PhaseSeed,
+ PhaseRma,
+ PhaseNone,
+ PhaseInvalid
+ } flash_lcmgr_phase_e;
+
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t;
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_region_cfg_shadowed_mreg_t;
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_bank0_info0_page_cfg_shadowed_mreg_t;
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_default_region_shadowed_reg_t;
+
+ typedef flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t sw_bank_cfg_t;
+ typedef flash_ctrl_reg2hw_mp_region_cfg_shadowed_mreg_t sw_region_cfg_t;
+ typedef flash_ctrl_reg2hw_default_region_shadowed_reg_t sw_default_cfg_t;
+ typedef flash_ctrl_reg2hw_bank0_info0_page_cfg_shadowed_mreg_t sw_info_cfg_t;
+
+ // alias for super long reg_pkg typedef
+ typedef struct packed {
+ logic q;
+ } bank_cfg_t;
+
+ // This is identical to the reg structures but do not have err_updates / storage
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } rd_en;
+ struct packed {
+ logic q;
+ } prog_en;
+ struct packed {
+ logic q;
+ } erase_en;
+ struct packed {
+ logic q;
+ } scramble_en;
+ struct packed {
+ logic q;
+ } ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
+ } info_page_cfg_t;
+
+ // This is identical to the reg structures but do not have err_updates / storage
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } rd_en;
+ struct packed {
+ logic q;
+ } prog_en;
+ struct packed {
+ logic q;
+ } erase_en;
+ struct packed {
+ logic q;
+ } scramble_en;
+ struct packed {
+ logic q;
+ } ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
+ struct packed {
+ logic [8:0] q;
+ } base;
+ struct packed {
+ logic [9:0] q;
+ } size;
+ } mp_region_cfg_t;
+
+ // memory protection specific structs
+ typedef struct packed {
+ logic [InfoTypesWidth-1:0] sel;
+ logic [AllPagesW-1:0] addr;
+ } page_addr_t;
+
+ typedef struct packed {
+ page_addr_t page;
+ flash_lcmgr_phase_e phase;
+ info_page_cfg_t cfg;
+ } info_page_attr_t;
+
+ typedef struct packed {
+ flash_lcmgr_phase_e phase;
+ mp_region_cfg_t cfg;
+ } data_region_attr_t;
+
+ // flash life cycle / key manager management constants
+ // One page for creator seeds
+ // One page for owner seeds
+ // One page for isolated flash page
+ parameter int NumSeeds = 2;
+ parameter bit [BankW-1:0] SeedBank = 0;
+ parameter bit [InfoTypesWidth-1:0] SeedInfoSel = 0;
+ parameter bit [0:0] CreatorSeedIdx = 0;
+ parameter bit [0:0] OwnerSeedIdx = 1;
+ parameter bit [PageW-1:0] CreatorInfoPage = 1;
+ parameter bit [PageW-1:0] OwnerInfoPage = 2;
+ parameter bit [PageW-1:0] IsolatedInfoPage = 3;
+
+ // which page of which info type of which bank for seed selection
+ parameter page_addr_t SeedInfoPageSel [NumSeeds] = '{
+ '{
+ sel: SeedInfoSel,
+ addr: {SeedBank, CreatorInfoPage}
+ },
+
+ '{
+ sel: SeedInfoSel,
+ addr: {SeedBank, OwnerInfoPage}
+ }
+ };
+
+ // which page of which info type of which bank for isolated partition
+ parameter page_addr_t IsolatedPageSel = '{
+ sel: SeedInfoSel,
+ addr: {SeedBank, IsolatedInfoPage}
+ };
+
+ // hardware interface memory protection rules
+ parameter int HwInfoRules = 5;
+ parameter int HwDataRules = 1;
+
+ parameter info_page_cfg_t CfgAllowRead = '{
+ en: 1'b1,
+ rd_en: 1'b1,
+ prog_en: 1'b0,
+ erase_en: 1'b0,
+ scramble_en: 1'b0,
+ ecc_en: 1'b0, // TBD, update to 1 once tb supports ECC
+ he_en: 1'b1
+ };
+
+ parameter info_page_cfg_t CfgAllowReadProgErase = '{
+ en: 1'b1,
+ rd_en: 1'b1,
+ prog_en: 1'b1,
+ erase_en: 1'b1,
+ scramble_en: 1'b1,
+ ecc_en: 1'b1,
+ he_en: 1'b1 // HW assumes high endurance
+ };
+
+ parameter info_page_attr_t HwInfoPageAttr[HwInfoRules] = '{
+ '{
+ page: SeedInfoPageSel[CreatorSeedIdx],
+ phase: PhaseSeed,
+ cfg: CfgAllowRead
+ },
+
+ '{
+ page: SeedInfoPageSel[OwnerSeedIdx],
+ phase: PhaseSeed,
+ cfg: CfgAllowRead
+ },
+
+ '{
+ page: SeedInfoPageSel[CreatorSeedIdx],
+ phase: PhaseRma,
+ cfg: CfgAllowReadProgErase
+ },
+
+ '{
+ page: SeedInfoPageSel[OwnerSeedIdx],
+ phase: PhaseRma,
+ cfg: CfgAllowReadProgErase
+ },
+
+ '{
+ page: IsolatedPageSel,
+ phase: PhaseRma,
+ cfg: CfgAllowReadProgErase
+ }
+ };
+
+ parameter data_region_attr_t HwDataAttr[HwDataRules] = '{
+ '{
+ phase: PhaseRma,
+ cfg: '{
+ en: 1'b1,
+ rd_en: 1'b1,
+ prog_en: 1'b1,
+ erase_en: 1'b1,
+ scramble_en: 1'b1,
+ ecc_en: 1'b1,
+ he_en: 1'b1, // HW assumes high endurance
+ base: '0,
+ size: '1
+ }
+ }
+ };
+
+
+ ////////////////////////////
+ // Design time constants
+ ////////////////////////////
+ parameter flash_key_t RndCnstAddrKeyDefault =
+ 128'h5d707f8a2d01d400928fa691c6a6e0a4;
+ parameter flash_key_t RndCnstDataKeyDefault =
+ 128'h39953618f2ca6f674af39f64975ea1f5;
+
+ ////////////////////////////
+ // Flash operation related enums
+ ////////////////////////////
+
+ // Flash Operations Supported
+ typedef enum logic [1:0] {
+ FlashOpRead = 2'h0,
+ FlashOpProgram = 2'h1,
+ FlashOpErase = 2'h2,
+ FlashOpInvalid = 2'h3
+ } flash_op_e;
+
+ // Flash Program Operations Supported
+ typedef enum logic {
+ FlashProgNormal = 0,
+ FlashProgRepair = 1
+ } flash_prog_e;
+ parameter int ProgTypes = 2;
+
+ // Flash Erase Operations Supported
+ typedef enum logic {
+ FlashErasePage = 0,
+ FlashEraseBank = 1
+ } flash_erase_e;
+
+ // Flash function select
+ typedef enum logic [1:0] {
+ NoneSel,
+ SwSel,
+ HwSel
+ } flash_sel_e;
+
+ // Flash tlul to fifo direction
+ typedef enum logic {
+ WriteDir = 1'b0,
+ ReadDir = 1'b1
+ } flash_flfo_dir_e;
+
+ // Flash partition type
+ typedef enum logic {
+ FlashPartData = 1'b0,
+ FlashPartInfo = 1'b1
+ } flash_part_e;
+
+ // Flash controller to memory
+ typedef struct packed {
+ logic req;
+ logic scramble_en;
+ logic ecc_en;
+ logic he_en;
+ logic rd_buf_en;
+ logic rd;
+ logic prog;
+ logic pg_erase;
+ logic bk_erase;
+ logic erase_suspend;
+ flash_part_e part;
+ logic [InfoTypesWidth-1:0] info_sel;
+ logic [BusAddrW-1:0] addr;
+ logic [BusWidth-1:0] prog_data;
+ logic prog_last;
+ flash_prog_e prog_type;
+ mp_region_cfg_t [MpRegions:0] region_cfgs;
+ logic [KeyWidth-1:0] addr_key;
+ logic [KeyWidth-1:0] data_key;
+ logic [KeyWidth-1:0] rand_addr_key;
+ logic [KeyWidth-1:0] rand_data_key;
+ logic alert_trig;
+ logic alert_ack;
+ jtag_pkg::jtag_req_t jtag_req;
+ logic intg_err;
+ prim_mubi_pkg::mubi4_t flash_disable;
+ } flash_req_t;
+
+ // default value of flash_req_t (for dangling ports)
+ parameter flash_req_t FLASH_REQ_DEFAULT = '{
+ req: '0,
+ scramble_en: '0,
+ ecc_en: '0,
+ he_en: '0,
+ rd_buf_en: 1'b0,
+ rd: '0,
+ prog: '0,
+ pg_erase: '0,
+ bk_erase: '0,
+ erase_suspend: '0,
+ part: FlashPartData,
+ info_sel: '0,
+ addr: '0,
+ prog_data: '0,
+ prog_last: '0,
+ prog_type: FlashProgNormal,
+ region_cfgs: '0,
+ addr_key: RndCnstAddrKeyDefault,
+ data_key: RndCnstDataKeyDefault,
+ rand_addr_key: '0,
+ rand_data_key: '0,
+ alert_trig: 1'b0,
+ alert_ack: 1'b0,
+ jtag_req: '0,
+ intg_err: '0,
+ flash_disable: prim_mubi_pkg::MuBi4False
+ };
+
+ // memory to flash controller
+ typedef struct packed {
+ logic [ProgTypes-1:0] prog_type_avail;
+ logic rd_done;
+ logic prog_done;
+ logic erase_done;
+ logic rd_err;
+ logic [BusWidth-1:0] rd_data;
+ logic init_busy;
+ logic flash_err;
+ logic [NumBanks-1:0] ecc_single_err;
+ logic [NumBanks-1:0][BusAddrW-1:0] ecc_addr;
+ jtag_pkg::jtag_rsp_t jtag_rsp;
+ logic intg_err;
+ } flash_rsp_t;
+
+ // default value of flash_rsp_t (for dangling ports)
+ parameter flash_rsp_t FLASH_RSP_DEFAULT = '{
+ prog_type_avail: {ProgTypes{1'b1}},
+ rd_done: 1'b0,
+ prog_done: 1'b0,
+ erase_done: 1'b0,
+ rd_err: '0,
+ rd_data: '0,
+ init_busy: 1'b0,
+ flash_err: 1'b0,
+ ecc_single_err: '0,
+ ecc_addr: '0,
+ jtag_rsp: '0,
+ intg_err: '0
+ };
+
+ // RMA entries
+ typedef struct packed {
+ logic [BankW-1:0] bank;
+ flash_part_e part;
+ logic [InfoTypesWidth-1:0] info_sel;
+ logic [PageW:0] start_page;
+ logic [PageW:0] num_pages;
+ } rma_wipe_entry_t;
+
+ // entries to be wiped
+ parameter int WipeEntries = 5;
+ parameter rma_wipe_entry_t RmaWipeEntries[WipeEntries] = '{
+ '{
+ bank: SeedBank,
+ part: FlashPartInfo,
+ info_sel: SeedInfoSel,
+ start_page: {1'b0, CreatorInfoPage},
+ num_pages: 1
+ },
+
+ '{
+ bank: SeedBank,
+ part: FlashPartInfo,
+ info_sel: SeedInfoSel,
+ start_page: {1'b0, OwnerInfoPage},
+ num_pages: 1
+ },
+
+ '{
+ bank: SeedBank,
+ part: FlashPartInfo,
+ info_sel: SeedInfoSel,
+ start_page: {1'b0, IsolatedInfoPage},
+ num_pages: 1
+ },
+
+ '{
+ bank: 0,
+ part: FlashPartData,
+ info_sel: 0,
+ start_page: 0,
+ num_pages: (PageW + 1)'(PagesPerBank)
+ },
+
+ '{
+ bank: 1,
+ part: FlashPartData,
+ info_sel: 0,
+ start_page: 0,
+ num_pages: (PageW + 1)'(PagesPerBank)
+ }
+ };
+
+
+ // flash_ctrl to keymgr
+ typedef struct packed {
+ logic [NumSeeds-1:0][SeedWidth-1:0] seeds;
+ } keymgr_flash_t;
+
+ parameter keymgr_flash_t KEYMGR_FLASH_DEFAULT = '{
+ seeds: '{
+ 256'h9152e32c9380a4bcc3e0ab263581e6b0e8825186e1e445631646e8bef8c45d47,
+ 256'hfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78
+ }
+ };
+
+ // dft_en jtag selection
+ typedef enum logic [2:0] {
+ FlashLcTckSel,
+ FlashLcTdiSel,
+ FlashLcTmsSel,
+ FlashLcTdoSel,
+ FlashBistSel,
+ FlashLcDftLast
+ } flash_lc_jtag_e;
+
+ // Error bit positioning
+ typedef struct packed {
+ logic oob_err;
+ logic mp_err;
+ logic rd_err;
+ logic prog_win_err;
+ logic prog_type_err;
+ logic phy_err;
+ } flash_ctrl_err_t;
+
+ // interrupt bit positioning
+ typedef enum logic[2:0] {
+ ProgEmpty,
+ ProgLvl,
+ RdFull,
+ RdLvl,
+ OpDone,
+ CorrErr,
+ LastIntrIdx
+ } flash_ctrl_intr_e;
+
+ // find the max number pages among info types
+ function automatic integer max_info_pages(int infos[InfoTypes]);
+ int current_max = 0;
+ for (int i = 0; i < InfoTypes; i++) begin
+ if (infos[i] > current_max) begin
+ current_max = infos[i];
+ end
+ end
+ return current_max;
+ endfunction // max_info_banks
+
+ // RMA control FSM encoding
+ // Encoding generated with:
+ // $ ./util/design/sparse-fsm-encode.py -d 5 -m 7 -n 10 // -s 3319803877 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: |||||||||||||||||||| (47.62%)
+ // 6: |||||||||||||||| (38.10%)
+ // 7: |||| (9.52%)
+ // 8: || (4.76%)
+ // 9: --
+ // 10: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 8
+ // Minimum Hamming weight: 3
+ // Maximum Hamming weight: 6
+ //
+ localparam int RmaStateWidth = 10;
+ typedef enum logic [RmaStateWidth-1:0] {
+ StRmaIdle = 10'b1101000011,
+ StRmaPageSel = 10'b0010111001,
+ StRmaErase = 10'b1111010100,
+ StRmaEraseWait = 10'b0111010101,
+ StRmaWordSel = 10'b0001011111,
+ StRmaProgram = 10'b0110001110,
+ StRmaProgramWait = 10'b1000110110,
+ StRmaRdVerify = 10'b1011101010,
+ StRmaInvalid = 10'b1100101101
+ } rma_state_e;
+
+endpackage : flash_ctrl_pkg
diff --git a/EDA-3283/rtl/flash_ctrl_reg_pkg.sv b/EDA-3283/rtl/flash_ctrl_reg_pkg.sv
new file mode 100644
index 00000000..ba1b514f
--- /dev/null
+++ b/EDA-3283/rtl/flash_ctrl_reg_pkg.sv
@@ -0,0 +1,1094 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package flash_ctrl_reg_pkg;
+
+ // Param list
+ parameter int RegNumBanks = 2;
+ parameter int RegPagesPerBank = 256;
+ parameter int RegBusPgmResBytes = 512;
+ parameter int RegPageWidth = 8;
+ parameter int RegBankWidth = 1;
+ parameter int NumRegions = 8;
+ parameter int NumInfos0 = 10;
+ parameter int NumInfos1 = 1;
+ parameter int NumInfos2 = 2;
+ parameter int WordsPerPage = 256;
+ parameter int BytesPerWord = 8;
+ parameter int BytesPerPage = 2048;
+ parameter int BytesPerBank = 524288;
+ parameter int ExecEn = 2724870391;
+ parameter int NumAlerts = 2;
+
+ // Address widths within the block
+ parameter int CoreAw = 9;
+ parameter int PrimAw = 1;
+ parameter int MemAw = 1;
+
+ ///////////////////////////////////////////////
+ // Typedefs for registers for core interface //
+ ///////////////////////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } prog_empty;
+ struct packed {
+ logic q;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ } rd_full;
+ struct packed {
+ logic q;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ } op_done;
+ struct packed {
+ logic q;
+ } corr_err;
+ } flash_ctrl_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } prog_empty;
+ struct packed {
+ logic q;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ } rd_full;
+ struct packed {
+ logic q;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ } op_done;
+ struct packed {
+ logic q;
+ } corr_err;
+ } flash_ctrl_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } prog_empty;
+ struct packed {
+ logic q;
+ logic qe;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ logic qe;
+ } rd_full;
+ struct packed {
+ logic q;
+ logic qe;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ logic qe;
+ } op_done;
+ struct packed {
+ logic q;
+ logic qe;
+ } corr_err;
+ } flash_ctrl_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } recov_err;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_err;
+ } flash_ctrl_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } flash_ctrl_reg2hw_dis_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } flash_ctrl_reg2hw_exec_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_init_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } start;
+ struct packed {
+ logic [1:0] q;
+ } op;
+ struct packed {
+ logic q;
+ } prog_sel;
+ struct packed {
+ logic q;
+ } erase_sel;
+ struct packed {
+ logic q;
+ } partition_sel;
+ struct packed {
+ logic [1:0] q;
+ } info_sel;
+ struct packed {
+ logic [11:0] q;
+ } num;
+ } flash_ctrl_reg2hw_control_reg_t;
+
+ typedef struct packed {
+ logic [19:0] q;
+ } flash_ctrl_reg2hw_addr_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } normal;
+ struct packed {
+ logic q;
+ } repair;
+ } flash_ctrl_reg2hw_prog_type_en_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_erase_suspend_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ struct packed {
+ logic [8:0] q;
+ logic err_update;
+ logic err_storage;
+ } base;
+ struct packed {
+ logic [9:0] q;
+ logic err_update;
+ logic err_storage;
+ } size;
+ } flash_ctrl_reg2hw_mp_region_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_default_region_shadowed_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank0_info0_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank0_info1_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank0_info2_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank1_info0_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank1_info1_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } rd_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } prog_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } erase_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } scramble_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } ecc_en;
+ struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } he_en;
+ } flash_ctrl_reg2hw_bank1_info2_page_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ logic err_update;
+ logic err_storage;
+ } flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } mp_err;
+ struct packed {
+ logic q;
+ } rd_err;
+ struct packed {
+ logic q;
+ } prog_win_err;
+ struct packed {
+ logic q;
+ } prog_type_err;
+ struct packed {
+ logic q;
+ } flash_phy_err;
+ struct packed {
+ logic q;
+ } reg_intg_err;
+ struct packed {
+ logic q;
+ } phy_intg_err;
+ struct packed {
+ logic q;
+ } lcmgr_err;
+ struct packed {
+ logic q;
+ } arb_fsm_err;
+ struct packed {
+ logic q;
+ } storage_err;
+ } flash_ctrl_reg2hw_fault_status_reg_t;
+
+ typedef struct packed {
+ logic [7:0] q;
+ } flash_ctrl_reg2hw_ecc_single_err_cnt_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } alert_ack;
+ struct packed {
+ logic q;
+ } alert_trig;
+ } flash_ctrl_reg2hw_phy_alert_cfg_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } flash_ctrl_reg2hw_scratch_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [4:0] q;
+ } prog;
+ struct packed {
+ logic [4:0] q;
+ } rd;
+ } flash_ctrl_reg2hw_fifo_lvl_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_fifo_rst_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } prog_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_lvl;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_full;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_lvl;
+ struct packed {
+ logic d;
+ logic de;
+ } op_done;
+ struct packed {
+ logic d;
+ logic de;
+ } corr_err;
+ } flash_ctrl_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ logic d;
+ } flash_ctrl_hw2reg_ctrl_regwen_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } start;
+ } flash_ctrl_hw2reg_control_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } flash_ctrl_hw2reg_erase_suspend_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } done;
+ struct packed {
+ logic d;
+ logic de;
+ } err;
+ } flash_ctrl_hw2reg_op_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } rd_full;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_full;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } init_wip;
+ } flash_ctrl_hw2reg_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } mp_err;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_win_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_type_err;
+ struct packed {
+ logic d;
+ logic de;
+ } flash_phy_err;
+ struct packed {
+ logic d;
+ logic de;
+ } update_err;
+ } flash_ctrl_hw2reg_err_code_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } mp_err;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_win_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_type_err;
+ struct packed {
+ logic d;
+ logic de;
+ } flash_phy_err;
+ struct packed {
+ logic d;
+ logic de;
+ } reg_intg_err;
+ struct packed {
+ logic d;
+ logic de;
+ } phy_intg_err;
+ struct packed {
+ logic d;
+ logic de;
+ } lcmgr_err;
+ struct packed {
+ logic d;
+ logic de;
+ } arb_fsm_err;
+ struct packed {
+ logic d;
+ logic de;
+ } storage_err;
+ } flash_ctrl_hw2reg_fault_status_reg_t;
+
+ typedef struct packed {
+ logic [19:0] d;
+ logic de;
+ } flash_ctrl_hw2reg_err_addr_reg_t;
+
+ typedef struct packed {
+ logic [7:0] d;
+ logic de;
+ } flash_ctrl_hw2reg_ecc_single_err_cnt_mreg_t;
+
+ typedef struct packed {
+ logic [19:0] d;
+ logic de;
+ } flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } init_wip;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_normal_avail;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_repair_avail;
+ } flash_ctrl_hw2reg_phy_status_reg_t;
+
+ // Register -> HW type for core interface
+ typedef struct packed {
+ flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [576:571]
+ flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [570:565]
+ flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [564:553]
+ flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [552:549]
+ flash_ctrl_reg2hw_dis_reg_t dis; // [548:545]
+ flash_ctrl_reg2hw_exec_reg_t exec; // [544:513]
+ flash_ctrl_reg2hw_init_reg_t init; // [512:512]
+ flash_ctrl_reg2hw_control_reg_t control; // [511:492]
+ flash_ctrl_reg2hw_addr_reg_t addr; // [491:472]
+ flash_ctrl_reg2hw_prog_type_en_reg_t prog_type_en; // [471:470]
+ flash_ctrl_reg2hw_erase_suspend_reg_t erase_suspend; // [469:469]
+ flash_ctrl_reg2hw_mp_region_cfg_shadowed_mreg_t [7:0] mp_region_cfg_shadowed; // [468:261]
+ flash_ctrl_reg2hw_default_region_shadowed_reg_t default_region_shadowed; // [260:255]
+ flash_ctrl_reg2hw_bank0_info0_page_cfg_shadowed_mreg_t [9:0]
+ bank0_info0_page_cfg_shadowed; // [254:185]
+ flash_ctrl_reg2hw_bank0_info1_page_cfg_shadowed_mreg_t [0:0]
+ bank0_info1_page_cfg_shadowed; // [184:178]
+ flash_ctrl_reg2hw_bank0_info2_page_cfg_shadowed_mreg_t [1:0]
+ bank0_info2_page_cfg_shadowed; // [177:164]
+ flash_ctrl_reg2hw_bank1_info0_page_cfg_shadowed_mreg_t [9:0]
+ bank1_info0_page_cfg_shadowed; // [163:94]
+ flash_ctrl_reg2hw_bank1_info1_page_cfg_shadowed_mreg_t [0:0]
+ bank1_info1_page_cfg_shadowed; // [93:87]
+ flash_ctrl_reg2hw_bank1_info2_page_cfg_shadowed_mreg_t [1:0]
+ bank1_info2_page_cfg_shadowed; // [86:73]
+ flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t [1:0] mp_bank_cfg_shadowed; // [72:71]
+ flash_ctrl_reg2hw_fault_status_reg_t fault_status; // [70:61]
+ flash_ctrl_reg2hw_ecc_single_err_cnt_mreg_t [1:0] ecc_single_err_cnt; // [60:45]
+ flash_ctrl_reg2hw_phy_alert_cfg_reg_t phy_alert_cfg; // [44:43]
+ flash_ctrl_reg2hw_scratch_reg_t scratch; // [42:11]
+ flash_ctrl_reg2hw_fifo_lvl_reg_t fifo_lvl; // [10:1]
+ flash_ctrl_reg2hw_fifo_rst_reg_t fifo_rst; // [0:0]
+ } flash_ctrl_core_reg2hw_t;
+
+ // HW -> register type for core interface
+ typedef struct packed {
+ flash_ctrl_hw2reg_intr_state_reg_t intr_state; // [149:138]
+ flash_ctrl_hw2reg_ctrl_regwen_reg_t ctrl_regwen; // [137:137]
+ flash_ctrl_hw2reg_control_reg_t control; // [136:135]
+ flash_ctrl_hw2reg_erase_suspend_reg_t erase_suspend; // [134:133]
+ flash_ctrl_hw2reg_op_status_reg_t op_status; // [132:129]
+ flash_ctrl_hw2reg_status_reg_t status; // [128:119]
+ flash_ctrl_hw2reg_err_code_reg_t err_code; // [118:107]
+ flash_ctrl_hw2reg_fault_status_reg_t fault_status; // [106:87]
+ flash_ctrl_hw2reg_err_addr_reg_t err_addr; // [86:66]
+ flash_ctrl_hw2reg_ecc_single_err_cnt_mreg_t [1:0] ecc_single_err_cnt; // [65:48]
+ flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t [1:0] ecc_single_err_addr; // [47:6]
+ flash_ctrl_hw2reg_phy_status_reg_t phy_status; // [5:0]
+ } flash_ctrl_core_hw2reg_t;
+
+ // Register offsets for core interface
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INTR_STATE_OFFSET = 9'h 0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INTR_ENABLE_OFFSET = 9'h 4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INTR_TEST_OFFSET = 9'h 8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ALERT_TEST_OFFSET = 9'h c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_DIS_OFFSET = 9'h 10;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_EXEC_OFFSET = 9'h 14;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INIT_OFFSET = 9'h 18;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_CTRL_REGWEN_OFFSET = 9'h 1c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_CONTROL_OFFSET = 9'h 20;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ADDR_OFFSET = 9'h 24;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_TYPE_EN_OFFSET = 9'h 28;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ERASE_SUSPEND_OFFSET = 9'h 2c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET = 9'h 30;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET = 9'h 34;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET = 9'h 38;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET = 9'h 3c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET = 9'h 40;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET = 9'h 44;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET = 9'h 48;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET = 9'h 4c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_0_OFFSET = 9'h 50;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_1_OFFSET = 9'h 54;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_2_OFFSET = 9'h 58;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_3_OFFSET = 9'h 5c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_4_OFFSET = 9'h 60;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_5_OFFSET = 9'h 64;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_6_OFFSET = 9'h 68;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_SHADOWED_7_OFFSET = 9'h 6c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_DEFAULT_REGION_SHADOWED_OFFSET = 9'h 70;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET = 9'h 74;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET = 9'h 78;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET = 9'h 7c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET = 9'h 80;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET = 9'h 84;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET = 9'h 88;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET = 9'h 8c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET = 9'h 90;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET = 9'h 94;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET = 9'h 98;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0_OFFSET = 9'h 9c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1_OFFSET = 9'h a0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2_OFFSET = 9'h a4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3_OFFSET = 9'h a8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4_OFFSET = 9'h ac;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5_OFFSET = 9'h b0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6_OFFSET = 9'h b4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7_OFFSET = 9'h b8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8_OFFSET = 9'h bc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9_OFFSET = 9'h c0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET = 9'h c4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED_OFFSET = 9'h c8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET = 9'h cc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET = 9'h d0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0_OFFSET = 9'h d4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1_OFFSET = 9'h d8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET = 9'h dc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET = 9'h e0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET = 9'h e4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET = 9'h e8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET = 9'h ec;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET = 9'h f0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET = 9'h f4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET = 9'h f8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET = 9'h fc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET = 9'h 100;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0_OFFSET = 9'h 104;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1_OFFSET = 9'h 108;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2_OFFSET = 9'h 10c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3_OFFSET = 9'h 110;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4_OFFSET = 9'h 114;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5_OFFSET = 9'h 118;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6_OFFSET = 9'h 11c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7_OFFSET = 9'h 120;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8_OFFSET = 9'h 124;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9_OFFSET = 9'h 128;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET = 9'h 12c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED_OFFSET = 9'h 130;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET = 9'h 134;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET = 9'h 138;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0_OFFSET = 9'h 13c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1_OFFSET = 9'h 140;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 9'h 144;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET = 9'h 148;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_OP_STATUS_OFFSET = 9'h 14c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_STATUS_OFFSET = 9'h 150;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_CODE_OFFSET = 9'h 154;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FAULT_STATUS_OFFSET = 9'h 158;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_ADDR_OFFSET = 9'h 15c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET = 9'h 160;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET = 9'h 164;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET = 9'h 168;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ALERT_CFG_OFFSET = 9'h 16c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h 170;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h 174;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h 178;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h 17c;
+
+ // Reset values for hwext registers and their fields for core interface
+ parameter logic [5:0] FLASH_CTRL_INTR_TEST_RESVAL = 6'h 0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL = 1'h 0;
+ parameter logic [1:0] FLASH_CTRL_ALERT_TEST_RESVAL = 2'h 0;
+ parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_RESVAL = 1'h 1;
+ parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_EN_RESVAL = 1'h 1;
+
+ // Window parameters for core interface
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 180;
+ parameter int unsigned FLASH_CTRL_PROG_FIFO_SIZE = 'h 4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 184;
+ parameter int unsigned FLASH_CTRL_RD_FIFO_SIZE = 'h 4;
+
+ // Register index for core interface
+ typedef enum int {
+ FLASH_CTRL_INTR_STATE,
+ FLASH_CTRL_INTR_ENABLE,
+ FLASH_CTRL_INTR_TEST,
+ FLASH_CTRL_ALERT_TEST,
+ FLASH_CTRL_DIS,
+ FLASH_CTRL_EXEC,
+ FLASH_CTRL_INIT,
+ FLASH_CTRL_CTRL_REGWEN,
+ FLASH_CTRL_CONTROL,
+ FLASH_CTRL_ADDR,
+ FLASH_CTRL_PROG_TYPE_EN,
+ FLASH_CTRL_ERASE_SUSPEND,
+ FLASH_CTRL_REGION_CFG_REGWEN_0,
+ FLASH_CTRL_REGION_CFG_REGWEN_1,
+ FLASH_CTRL_REGION_CFG_REGWEN_2,
+ FLASH_CTRL_REGION_CFG_REGWEN_3,
+ FLASH_CTRL_REGION_CFG_REGWEN_4,
+ FLASH_CTRL_REGION_CFG_REGWEN_5,
+ FLASH_CTRL_REGION_CFG_REGWEN_6,
+ FLASH_CTRL_REGION_CFG_REGWEN_7,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_0,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_1,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_2,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_3,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_4,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_5,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_6,
+ FLASH_CTRL_MP_REGION_CFG_SHADOWED_7,
+ FLASH_CTRL_DEFAULT_REGION_SHADOWED,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_0,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_1,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_2,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_3,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_4,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_5,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_6,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_7,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_8,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_9,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9,
+ FLASH_CTRL_BANK0_INFO1_REGWEN,
+ FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED,
+ FLASH_CTRL_BANK0_INFO2_REGWEN_0,
+ FLASH_CTRL_BANK0_INFO2_REGWEN_1,
+ FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0,
+ FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_0,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_1,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_2,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_3,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_4,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_5,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_6,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_7,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_8,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_9,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9,
+ FLASH_CTRL_BANK1_INFO1_REGWEN,
+ FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED,
+ FLASH_CTRL_BANK1_INFO2_REGWEN_0,
+ FLASH_CTRL_BANK1_INFO2_REGWEN_1,
+ FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0,
+ FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1,
+ FLASH_CTRL_BANK_CFG_REGWEN,
+ FLASH_CTRL_MP_BANK_CFG_SHADOWED,
+ FLASH_CTRL_OP_STATUS,
+ FLASH_CTRL_STATUS,
+ FLASH_CTRL_ERR_CODE,
+ FLASH_CTRL_FAULT_STATUS,
+ FLASH_CTRL_ERR_ADDR,
+ FLASH_CTRL_ECC_SINGLE_ERR_CNT,
+ FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0,
+ FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1,
+ FLASH_CTRL_PHY_ALERT_CFG,
+ FLASH_CTRL_PHY_STATUS,
+ FLASH_CTRL_SCRATCH,
+ FLASH_CTRL_FIFO_LVL,
+ FLASH_CTRL_FIFO_RST
+ } flash_ctrl_core_id_e;
+
+ // Register width information to check illegal writes for core interface
+ parameter logic [3:0] FLASH_CTRL_CORE_PERMIT [96] = '{
+ 4'b 0001, // index[ 0] FLASH_CTRL_INTR_STATE
+ 4'b 0001, // index[ 1] FLASH_CTRL_INTR_ENABLE
+ 4'b 0001, // index[ 2] FLASH_CTRL_INTR_TEST
+ 4'b 0001, // index[ 3] FLASH_CTRL_ALERT_TEST
+ 4'b 0001, // index[ 4] FLASH_CTRL_DIS
+ 4'b 1111, // index[ 5] FLASH_CTRL_EXEC
+ 4'b 0001, // index[ 6] FLASH_CTRL_INIT
+ 4'b 0001, // index[ 7] FLASH_CTRL_CTRL_REGWEN
+ 4'b 1111, // index[ 8] FLASH_CTRL_CONTROL
+ 4'b 0111, // index[ 9] FLASH_CTRL_ADDR
+ 4'b 0001, // index[10] FLASH_CTRL_PROG_TYPE_EN
+ 4'b 0001, // index[11] FLASH_CTRL_ERASE_SUSPEND
+ 4'b 0001, // index[12] FLASH_CTRL_REGION_CFG_REGWEN_0
+ 4'b 0001, // index[13] FLASH_CTRL_REGION_CFG_REGWEN_1
+ 4'b 0001, // index[14] FLASH_CTRL_REGION_CFG_REGWEN_2
+ 4'b 0001, // index[15] FLASH_CTRL_REGION_CFG_REGWEN_3
+ 4'b 0001, // index[16] FLASH_CTRL_REGION_CFG_REGWEN_4
+ 4'b 0001, // index[17] FLASH_CTRL_REGION_CFG_REGWEN_5
+ 4'b 0001, // index[18] FLASH_CTRL_REGION_CFG_REGWEN_6
+ 4'b 0001, // index[19] FLASH_CTRL_REGION_CFG_REGWEN_7
+ 4'b 1111, // index[20] FLASH_CTRL_MP_REGION_CFG_SHADOWED_0
+ 4'b 1111, // index[21] FLASH_CTRL_MP_REGION_CFG_SHADOWED_1
+ 4'b 1111, // index[22] FLASH_CTRL_MP_REGION_CFG_SHADOWED_2
+ 4'b 1111, // index[23] FLASH_CTRL_MP_REGION_CFG_SHADOWED_3
+ 4'b 1111, // index[24] FLASH_CTRL_MP_REGION_CFG_SHADOWED_4
+ 4'b 1111, // index[25] FLASH_CTRL_MP_REGION_CFG_SHADOWED_5
+ 4'b 1111, // index[26] FLASH_CTRL_MP_REGION_CFG_SHADOWED_6
+ 4'b 1111, // index[27] FLASH_CTRL_MP_REGION_CFG_SHADOWED_7
+ 4'b 0001, // index[28] FLASH_CTRL_DEFAULT_REGION_SHADOWED
+ 4'b 0001, // index[29] FLASH_CTRL_BANK0_INFO0_REGWEN_0
+ 4'b 0001, // index[30] FLASH_CTRL_BANK0_INFO0_REGWEN_1
+ 4'b 0001, // index[31] FLASH_CTRL_BANK0_INFO0_REGWEN_2
+ 4'b 0001, // index[32] FLASH_CTRL_BANK0_INFO0_REGWEN_3
+ 4'b 0001, // index[33] FLASH_CTRL_BANK0_INFO0_REGWEN_4
+ 4'b 0001, // index[34] FLASH_CTRL_BANK0_INFO0_REGWEN_5
+ 4'b 0001, // index[35] FLASH_CTRL_BANK0_INFO0_REGWEN_6
+ 4'b 0001, // index[36] FLASH_CTRL_BANK0_INFO0_REGWEN_7
+ 4'b 0001, // index[37] FLASH_CTRL_BANK0_INFO0_REGWEN_8
+ 4'b 0001, // index[38] FLASH_CTRL_BANK0_INFO0_REGWEN_9
+ 4'b 0001, // index[39] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_0
+ 4'b 0001, // index[40] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_1
+ 4'b 0001, // index[41] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_2
+ 4'b 0001, // index[42] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_3
+ 4'b 0001, // index[43] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_4
+ 4'b 0001, // index[44] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_5
+ 4'b 0001, // index[45] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_6
+ 4'b 0001, // index[46] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_7
+ 4'b 0001, // index[47] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_8
+ 4'b 0001, // index[48] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SHADOWED_9
+ 4'b 0001, // index[49] FLASH_CTRL_BANK0_INFO1_REGWEN
+ 4'b 0001, // index[50] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SHADOWED
+ 4'b 0001, // index[51] FLASH_CTRL_BANK0_INFO2_REGWEN_0
+ 4'b 0001, // index[52] FLASH_CTRL_BANK0_INFO2_REGWEN_1
+ 4'b 0001, // index[53] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_0
+ 4'b 0001, // index[54] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SHADOWED_1
+ 4'b 0001, // index[55] FLASH_CTRL_BANK1_INFO0_REGWEN_0
+ 4'b 0001, // index[56] FLASH_CTRL_BANK1_INFO0_REGWEN_1
+ 4'b 0001, // index[57] FLASH_CTRL_BANK1_INFO0_REGWEN_2
+ 4'b 0001, // index[58] FLASH_CTRL_BANK1_INFO0_REGWEN_3
+ 4'b 0001, // index[59] FLASH_CTRL_BANK1_INFO0_REGWEN_4
+ 4'b 0001, // index[60] FLASH_CTRL_BANK1_INFO0_REGWEN_5
+ 4'b 0001, // index[61] FLASH_CTRL_BANK1_INFO0_REGWEN_6
+ 4'b 0001, // index[62] FLASH_CTRL_BANK1_INFO0_REGWEN_7
+ 4'b 0001, // index[63] FLASH_CTRL_BANK1_INFO0_REGWEN_8
+ 4'b 0001, // index[64] FLASH_CTRL_BANK1_INFO0_REGWEN_9
+ 4'b 0001, // index[65] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_0
+ 4'b 0001, // index[66] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_1
+ 4'b 0001, // index[67] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_2
+ 4'b 0001, // index[68] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_3
+ 4'b 0001, // index[69] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_4
+ 4'b 0001, // index[70] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_5
+ 4'b 0001, // index[71] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_6
+ 4'b 0001, // index[72] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_7
+ 4'b 0001, // index[73] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_8
+ 4'b 0001, // index[74] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SHADOWED_9
+ 4'b 0001, // index[75] FLASH_CTRL_BANK1_INFO1_REGWEN
+ 4'b 0001, // index[76] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SHADOWED
+ 4'b 0001, // index[77] FLASH_CTRL_BANK1_INFO2_REGWEN_0
+ 4'b 0001, // index[78] FLASH_CTRL_BANK1_INFO2_REGWEN_1
+ 4'b 0001, // index[79] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_0
+ 4'b 0001, // index[80] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SHADOWED_1
+ 4'b 0001, // index[81] FLASH_CTRL_BANK_CFG_REGWEN
+ 4'b 0001, // index[82] FLASH_CTRL_MP_BANK_CFG_SHADOWED
+ 4'b 0001, // index[83] FLASH_CTRL_OP_STATUS
+ 4'b 0001, // index[84] FLASH_CTRL_STATUS
+ 4'b 0001, // index[85] FLASH_CTRL_ERR_CODE
+ 4'b 0011, // index[86] FLASH_CTRL_FAULT_STATUS
+ 4'b 0111, // index[87] FLASH_CTRL_ERR_ADDR
+ 4'b 0011, // index[88] FLASH_CTRL_ECC_SINGLE_ERR_CNT
+ 4'b 0111, // index[89] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0
+ 4'b 0111, // index[90] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1
+ 4'b 0001, // index[91] FLASH_CTRL_PHY_ALERT_CFG
+ 4'b 0001, // index[92] FLASH_CTRL_PHY_STATUS
+ 4'b 1111, // index[93] FLASH_CTRL_SCRATCH
+ 4'b 0011, // index[94] FLASH_CTRL_FIFO_LVL
+ 4'b 0001 // index[95] FLASH_CTRL_FIFO_RST
+ };
+
+endpackage
+
diff --git a/EDA-3283/rtl/flash_phy_pkg.sv b/EDA-3283/rtl/flash_phy_pkg.sv
new file mode 100644
index 00000000..5cdec0f7
--- /dev/null
+++ b/EDA-3283/rtl/flash_phy_pkg.sv
@@ -0,0 +1,125 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Flash phy module package
+//
+
+package flash_phy_pkg;
+
+ // flash phy parameters
+ parameter int NumBanks = flash_ctrl_pkg::NumBanks;
+ parameter int InfosPerBank = flash_ctrl_pkg::InfosPerBank;
+ parameter int PagesPerBank = flash_ctrl_pkg::PagesPerBank;
+ parameter int WordsPerPage = flash_ctrl_pkg::WordsPerPage;
+ parameter int BankW = flash_ctrl_pkg::BankW;
+ parameter int PageW = flash_ctrl_pkg::PageW;
+ parameter int WordW = flash_ctrl_pkg::WordW;
+ parameter int BankAddrW = flash_ctrl_pkg::BankAddrW;
+ parameter int DataWidth = flash_ctrl_pkg::DataWidth;
+ parameter int EccWidth = 8;
+ parameter int MetaDataWidth = flash_ctrl_pkg::MetaDataWidth;
+ parameter int WidthMultiple = flash_ctrl_pkg::WidthMultiple;
+ parameter int NumBuf = 4; // number of flash read buffers
+ parameter int RspOrderDepth = 2; // this should be DataWidth / BusWidth
+ // will switch to this after bus widening
+ parameter int ScrDataWidth = DataWidth + EccWidth;
+ parameter int FullDataWidth = DataWidth + MetaDataWidth;
+ parameter int InfoTypes = flash_ctrl_pkg::InfoTypes;
+ parameter int InfoTypesWidth = flash_ctrl_pkg::InfoTypesWidth;
+
+ // flash ctrl / bus parameters
+ parameter int BusWidth = flash_ctrl_pkg::BusWidth;
+ parameter int BusBankAddrW = flash_ctrl_pkg::BusBankAddrW;
+ parameter int BusWordW = flash_ctrl_pkg::BusWordW;
+ parameter int ProgTypes = flash_ctrl_pkg::ProgTypes;
+
+ // address bits remain must be 0
+ parameter int AddrBitsRemain = DataWidth % BusWidth;
+
+ // base index
+ // This is the lsb position of the prim flash address when looking at the bus address
+ parameter int LsbAddrBit = $clog2(WidthMultiple);
+ parameter int WordSelW = WidthMultiple == 1 ? 1 : LsbAddrBit;
+
+ // scramble / de-scramble parameters
+ // Number of cycles the gf_mult is given to complete
+ parameter int KeySize = 128;
+ parameter int GfMultCycles = 2;
+ // If this value is greater than 1, constraints must be updated for multicycle paths
+ parameter int CipherCycles = 2;
+
+ // Read buffer metadata
+ typedef enum logic [1:0] {
+ Invalid = 2'h0,
+ Wip = 2'h1,
+ Valid = 2'h2,
+ Undef = 2'h3
+ } rd_buf_attr_e;
+
+ typedef struct packed {
+ logic [DataWidth-1:0] data;
+ logic [BankAddrW-1:0] addr; // all address bits preserved to pick return portion
+ logic part;
+ logic [InfoTypesWidth-1:0] info_sel;
+ rd_buf_attr_e attr;
+ } rd_buf_t;
+
+ typedef struct packed {
+ logic [NumBuf-1:0] buf_sel;
+ logic [WordSelW-1:0] word_sel;
+ } rsp_fifo_entry_t;
+
+ parameter int RspOrderFifoWidth = $bits(rsp_fifo_entry_t);
+
+ typedef struct packed {
+ logic [BankAddrW-1:0] addr;
+ logic descramble;
+ logic ecc;
+ } rd_attr_t;
+
+ // Flash Operations Supported
+ typedef enum logic [2:0] {
+ PhyRead = 3'h0,
+ PhyProg = 3'h1,
+ PhyPgErase = 3'h2,
+ PhyBkErase = 3'h3,
+ PhyOps = 3'h4
+ } flash_phy_op_e;
+
+ // Flash Operations Selected
+ typedef enum logic [1:0] {
+ None = 2'h0,
+ Host = 2'h1,
+ Ctrl = 2'h2
+ } flash_phy_op_sel_e;
+
+ typedef enum logic {
+ ScrambleOp = 1'b0,
+ DeScrambleOp = 1'b1
+ } cipher_ops_e;
+
+ // Connections to prim_flash
+ typedef struct packed {
+ logic rd_req;
+ logic prog_req;
+ logic prog_last;
+ flash_ctrl_pkg::flash_prog_e prog_type;
+ logic pg_erase_req;
+ logic bk_erase_req;
+ logic erase_suspend_req;
+ logic he;
+ logic [BankAddrW-1:0] addr;
+ flash_ctrl_pkg::flash_part_e part;
+ logic [InfoTypesWidth-1:0] info_sel;
+ logic [FullDataWidth-1:0] prog_full_data;
+ } flash_phy_prim_flash_req_t;
+
+ typedef struct packed {
+ logic ack;
+ logic done;
+ logic [FullDataWidth-1:0] rdata;
+ logic erase_suspend_done;
+ } flash_phy_prim_flash_rsp_t;
+
+endpackage // flash_phy_pkg
diff --git a/EDA-3283/rtl/flist.flist b/EDA-3283/rtl/flist.flist
new file mode 100644
index 00000000..ad311a9e
--- /dev/null
+++ b/EDA-3283/rtl/flist.flist
@@ -0,0 +1,56 @@
+prim_secded_pkg.sv
+prim_subreg_pkg.sv
+prim_util_pkg.sv
+pwrmgr_reg_pkg.sv
+pwrmgr_pkg.sv
+prim_ram_1p_pkg.sv
+prim_mubi_pkg.sv
+prim_pkg.sv
+prim_cipher_pkg.sv
+prim_alert_pkg.sv
+prim_count_pkg.sv
+jtag_pkg.sv
+entropy_src_pkg.sv
+edn_pkg.sv
+top_pkg.sv
+flash_ctrl_reg_pkg.sv
+flash_ctrl_pkg.sv
+flash_phy_pkg.sv
+hmac_reg_pkg.sv
+hmac_pkg.sv
+lc_ctrl_pkg.sv
+otp_ctrl_reg_pkg.sv
+otp_ctrl_pkg.sv
+tlul_pkg.sv
+ast_pkg.sv
+hmac.sv
+hmac_core.sv
+hmac_reg_top.sv
+prim_alert_sender.sv
+prim_buf.sv
+prim_diff_decode.sv
+prim_fifo_sync.sv
+prim_flop_2sync.sv
+prim_generic_buf.sv
+prim_generic_flop.sv
+prim_generic_flop_2sync.sv
+prim_intr_hw.sv
+prim_packer.sv
+prim_secded_inv_39_32_dec.sv
+prim_secded_inv_39_32_enc.sv
+prim_secded_inv_64_57_dec.sv
+prim_secded_inv_64_57_enc.sv
+prim_subreg.sv
+prim_subreg_ext.sv
+sha2.sv
+sha2_pad.sv
+tlul_adapter_reg.sv
+tlul_adapter_sram.sv
+tlul_cmd_intg_chk.sv
+tlul_data_integ_dec.sv
+tlul_data_integ_enc.sv
+tlul_err.sv
+tlul_err_resp.sv
+tlul_fifo_sync.sv
+tlul_rsp_intg_gen.sv
+tlul_socket_1n.sv
\ No newline at end of file
diff --git a/EDA-3283/rtl/hmac.sv b/EDA-3283/rtl/hmac.sv
new file mode 100644
index 00000000..52889b1a
--- /dev/null
+++ b/EDA-3283/rtl/hmac.sv
@@ -0,0 +1,565 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// HMAC-SHA256
+
+
+
+module hmac
+ import hmac_pkg::*;
+ import hmac_reg_pkg::*;
+#(
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}
+) (
+ input clk_i,
+ input rst_ni,
+
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+
+ output logic intr_hmac_done_o,
+ output logic intr_fifo_empty_o,
+ output logic intr_hmac_err_o,
+
+ output logic idle_o
+);
+
+
+ /////////////////////////
+ // Signal declarations //
+ /////////////////////////
+ hmac_reg2hw_t reg2hw;
+ hmac_hw2reg_t hw2reg;
+
+ tlul_pkg::tl_h2d_t tl_win_h2d;
+ tlul_pkg::tl_d2h_t tl_win_d2h;
+
+ logic [255:0] secret_key;
+
+ logic wipe_secret;
+ logic [31:0] wipe_v;
+
+ logic fifo_rvalid;
+ logic fifo_rready;
+ sha_fifo_t fifo_rdata;
+
+ logic fifo_wvalid, fifo_wready;
+ sha_fifo_t fifo_wdata;
+ logic fifo_full;
+ logic fifo_empty;
+ logic [4:0] fifo_depth;
+
+ logic msg_fifo_req;
+ logic msg_fifo_gnt;
+ logic msg_fifo_we;
+ logic [31:0] msg_fifo_wdata;
+ logic [31:0] msg_fifo_wmask;
+ logic [31:0] msg_fifo_rdata;
+ logic msg_fifo_rvalid;
+ logic [1:0] msg_fifo_rerror;
+ logic [31:0] msg_fifo_wdata_endian;
+ logic [31:0] msg_fifo_wmask_endian;
+
+ logic packer_ready;
+ logic packer_flush_done;
+
+ logic reg_fifo_wvalid;
+ sha_word_t reg_fifo_wdata;
+ sha_word_t reg_fifo_wmask;
+ logic hmac_fifo_wsel;
+ logic hmac_fifo_wvalid;
+ logic [2:0] hmac_fifo_wdata_sel;
+
+ logic shaf_rvalid;
+ sha_fifo_t shaf_rdata;
+ logic shaf_rready;
+
+ logic sha_en;
+ logic hmac_en;
+ logic endian_swap;
+ logic digest_swap;
+
+ logic reg_hash_start;
+ logic sha_hash_start;
+ logic hash_start; // Valid hash_start_signal
+ logic reg_hash_process;
+ logic sha_hash_process;
+
+ logic reg_hash_done;
+ logic sha_hash_done;
+
+ logic [63:0] message_length;
+ logic [63:0] sha_message_length;
+
+ err_code_e err_code;
+ logic err_valid;
+
+ sha_word_t [7:0] digest;
+
+ hmac_reg2hw_cfg_reg_t cfg_reg;
+ logic cfg_block; // Prevent changing config
+ logic msg_allowed; // MSG_FIFO from software is allowed
+
+ logic hmac_core_idle;
+ logic sha_core_idle;
+
+ ///////////////////////
+ // Connect registers //
+ ///////////////////////
+ assign hw2reg.status.fifo_full.d = fifo_full;
+ assign hw2reg.status.fifo_empty.d = fifo_empty;
+ assign hw2reg.status.fifo_depth.d = fifo_depth;
+
+ // secret key
+ assign wipe_secret = reg2hw.wipe_secret.qe;
+ assign wipe_v = reg2hw.wipe_secret.q;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ secret_key <= '0;
+ end else if (wipe_secret) begin
+ secret_key <= {8{wipe_v}};
+ end else if (!cfg_block) begin
+ // Allow updating secret key only when the engine is in Idle.
+ for (int i = 0; i < 8; i++) begin
+ if (reg2hw.key[7-i].qe) begin
+ secret_key[32*i+:32] <= reg2hw.key[7-i].q;
+ end
+ end
+ end
+ end
+
+ for (genvar i = 0; i < 8; i++) begin : gen_key_digest
+ assign hw2reg.key[7-i].d = '0;
+ // digest
+ assign hw2reg.digest[i].d = conv_endian(digest[i], digest_swap);
+ end
+
+ logic [3:0] unused_cfg_qe;
+
+ assign unused_cfg_qe = {cfg_reg.sha_en.qe, cfg_reg.hmac_en.qe,
+ cfg_reg.endian_swap.qe, cfg_reg.digest_swap.qe};
+
+ assign sha_en = cfg_reg.sha_en.q;
+ assign hmac_en = cfg_reg.hmac_en.q;
+ assign endian_swap = cfg_reg.endian_swap.q;
+ assign digest_swap = cfg_reg.digest_swap.q;
+ assign hw2reg.cfg.hmac_en.d = cfg_reg.hmac_en.q;
+ assign hw2reg.cfg.sha_en.d = cfg_reg.sha_en.q;
+ assign hw2reg.cfg.endian_swap.d = cfg_reg.endian_swap.q;
+ assign hw2reg.cfg.digest_swap.d = cfg_reg.digest_swap.q;
+
+ assign reg_hash_start = reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q;
+ assign reg_hash_process = reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q;
+
+ // Error code register
+ assign hw2reg.err_code.de = err_valid;
+ assign hw2reg.err_code.d = err_code;
+
+ /////////////////////
+ // Control signals //
+ /////////////////////
+ assign hash_start = reg_hash_start & sha_en & ~cfg_block;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ cfg_block <= '0;
+ end else if (hash_start) begin
+ cfg_block <= 1'b 1;
+ end else if (reg_hash_done) begin
+ cfg_block <= 1'b 0;
+ end
+ end
+ // Hold the configuration during the process
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ cfg_reg <= '{endian_swap: '{q: 1'b1, qe: 1'b0}, default:'0};
+ end else if (!cfg_block && reg2hw.cfg.hmac_en.qe) begin
+ cfg_reg <= reg2hw.cfg ;
+ end
+ end
+
+ // Open up the MSG_FIFO from the TL-UL port when it is ready
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ msg_allowed <= '0;
+ end else if (hash_start) begin
+ msg_allowed <= 1'b 1;
+ end else if (packer_flush_done) begin
+ msg_allowed <= 1'b 0;
+ end
+ end
+ ////////////////
+ // Interrupts //
+ ////////////////
+ logic fifo_empty_q, fifo_empty_event;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_empty_q <= '1; // By default, it is empty
+ end else if (!hmac_fifo_wsel) begin
+ fifo_empty_q <= fifo_empty;
+ end
+ end
+ assign fifo_empty_event = fifo_empty & ~fifo_empty_q;
+
+ logic [2:0] event_intr;
+ assign event_intr = {err_valid, fifo_empty_event, reg_hash_done};
+
+ // instantiate interrupt hardware primitive
+ prim_intr_hw #(.Width(1)) intr_hw_hmac_done (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (event_intr[0]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.hmac_done.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.hmac_done.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.hmac_done.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.hmac_done.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.hmac_done.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.hmac_done.d),
+ .intr_o (intr_hmac_done_o)
+ );
+ prim_intr_hw #(.Width(1)) intr_hw_fifo_empty (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (event_intr[1]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.fifo_empty.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.fifo_empty.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.fifo_empty.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.fifo_empty.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.fifo_empty.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.fifo_empty.d),
+ .intr_o (intr_fifo_empty_o)
+ );
+ prim_intr_hw #(.Width(1)) intr_hw_hmac_err (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (event_intr[2]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.hmac_err.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.hmac_err.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.hmac_err.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.hmac_err.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.hmac_err.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.hmac_err.d),
+ .intr_o (intr_hmac_err_o)
+ );
+
+ ///////////////
+ // Instances //
+ ///////////////
+
+ assign msg_fifo_rvalid = msg_fifo_req & ~msg_fifo_we;
+ assign msg_fifo_rdata = '1; // Return all F
+ assign msg_fifo_rerror = '1; // Return error for read access
+ assign msg_fifo_gnt = msg_fifo_req & ~hmac_fifo_wsel & packer_ready;
+
+ // FIFO control
+ sha_fifo_t reg_fifo_wentry;
+ assign reg_fifo_wentry.data = conv_endian(reg_fifo_wdata, 1'b1); // always convert
+ assign reg_fifo_wentry.mask = {reg_fifo_wmask[0], reg_fifo_wmask[8],
+ reg_fifo_wmask[16], reg_fifo_wmask[24]};
+ assign fifo_full = ~fifo_wready;
+ assign fifo_empty = ~fifo_rvalid;
+ assign fifo_wvalid = (hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid;
+ assign fifo_wdata = (hmac_fifo_wsel) ? '{data: digest[hmac_fifo_wdata_sel], mask: '1}
+ : reg_fifo_wentry;
+
+ prim_fifo_sync #(
+ .Width ($bits(sha_fifo_t)),
+ .Pass (1'b1),
+ .Depth (MsgFifoDepth)
+ ) u_msg_fifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0),
+
+ .wvalid(fifo_wvalid & sha_en),
+ .wready(fifo_wready),
+ .wdata (fifo_wdata),
+
+ .depth (fifo_depth),
+
+ .rvalid(fifo_rvalid),
+ .rready(fifo_rready),
+ .rdata(fifo_rdata)
+ );
+
+ // TL ADAPTER SRAM
+ tlul_adapter_sram #(
+ .SramAw (9),
+ .SramDw (32),
+ .Outstanding (1),
+ .ByteAccess (1),
+ .ErrOnRead (1)
+ ) u_tlul_adapter (
+ .clk_i,
+ .rst_ni,
+ .tl_i (tl_win_h2d),
+ .tl_o (tl_win_d2h),
+ .req_o (msg_fifo_req ),
+ .gnt_i (msg_fifo_gnt ),
+ .we_o (msg_fifo_we ),
+ .addr_o ( ), // Doesn't care the address other than sub-word
+ .wdata_o (msg_fifo_wdata ),
+ .wmask_o (msg_fifo_wmask ),
+ .rdata_i (msg_fifo_rdata ),
+ .rvalid_i (msg_fifo_rvalid),
+ .rerror_i (msg_fifo_rerror)
+ );
+
+ // TL-UL to MSG_FIFO byte write handling
+ logic msg_write;
+
+ assign msg_write = msg_fifo_req & msg_fifo_we & ~hmac_fifo_wsel & msg_allowed;
+
+ logic [$clog2(32+1)-1:0] wmask_ones;
+
+ always_comb begin
+ wmask_ones = '0;
+ for (int i = 0 ; i < 32 ; i++) begin
+ wmask_ones = wmask_ones + msg_fifo_wmask[i];
+ end
+ end
+
+ // Calculate written message
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ message_length <= '0;
+ end else if (hash_start) begin
+ message_length <= '0;
+ end else if (msg_write && sha_en && packer_ready) begin
+ message_length <= message_length + 64'(wmask_ones);
+ end
+ end
+
+ assign hw2reg.msg_length_upper.de = 1'b1;
+ assign hw2reg.msg_length_upper.d = message_length[63:32];
+ assign hw2reg.msg_length_lower.de = 1'b1;
+ assign hw2reg.msg_length_lower.d = message_length[31:0];
+
+
+ // Convert endian here
+ // prim_packer always packs to the right, but SHA engine assumes incoming
+ // to be big-endian, [31:24] comes first. So, the data is reverted after
+ // prim_packer before the message fifo. here to reverse if not big-endian
+ // before pushing to the packer.
+ assign msg_fifo_wdata_endian = conv_endian(msg_fifo_wdata, ~endian_swap);
+ assign msg_fifo_wmask_endian = conv_endian(msg_fifo_wmask, ~endian_swap);
+
+ prim_packer #(
+ .InW (32),
+ .OutW (32)
+ ) u_packer (
+ .clk_i,
+ .rst_ni,
+
+ .valid_i (msg_write & sha_en),
+ .data_i (msg_fifo_wdata_endian),
+ .mask_i (msg_fifo_wmask_endian),
+ .ready_o (packer_ready),
+
+ .valid_o (reg_fifo_wvalid),
+ .data_o (reg_fifo_wdata),
+ .mask_o (reg_fifo_wmask),
+ .ready_i (fifo_wready & ~hmac_fifo_wsel),
+
+ .flush_i (reg_hash_process),
+ .flush_done_o (packer_flush_done) // ignore at this moment
+ );
+
+
+ hmac_core u_hmac (
+ .clk_i,
+ .rst_ni,
+
+ .secret_key,
+
+ .wipe_secret,
+ .wipe_v,
+
+ .hmac_en,
+
+ .reg_hash_start (hash_start),
+ .reg_hash_process (packer_flush_done), // Trigger after all msg written
+ .hash_done (reg_hash_done),
+ .sha_hash_start,
+ .sha_hash_process,
+ .sha_hash_done,
+
+ .sha_rvalid (shaf_rvalid),
+ .sha_rdata (shaf_rdata),
+ .sha_rready (shaf_rready),
+
+ .fifo_rvalid,
+ .fifo_rdata,
+ .fifo_rready,
+
+ .fifo_wsel (hmac_fifo_wsel),
+ .fifo_wvalid (hmac_fifo_wvalid),
+ .fifo_wdata_sel (hmac_fifo_wdata_sel),
+ .fifo_wready,
+
+ .message_length,
+ .sha_message_length,
+
+ .idle (hmac_core_idle)
+ );
+
+ sha2 u_sha2 (
+ .clk_i,
+ .rst_ni,
+
+ .wipe_secret,
+ .wipe_v,
+
+ .fifo_rvalid (shaf_rvalid),
+ .fifo_rdata (shaf_rdata),
+ .fifo_rready (shaf_rready),
+
+ .sha_en,
+ .hash_start (sha_hash_start),
+ .hash_process (sha_hash_process),
+ .hash_done (sha_hash_done),
+
+ .message_length (sha_message_length),
+
+ .digest,
+
+ .idle (sha_core_idle)
+ );
+
+ // Register top
+ logic [NumAlerts-1:0] alert_test, alerts;
+ hmac_reg_top u_reg (
+ .clk_i,
+ .rst_ni,
+
+ .tl_i,
+ .tl_o,
+
+ .tl_win_o (tl_win_h2d),
+ .tl_win_i (tl_win_d2h),
+
+ .reg2hw,
+ .hw2reg,
+
+ // SEC_CM: BUS.INTEGRITY
+ .intg_err_o (alerts[0]),
+ .devmode_i (1'b1)
+ );
+
+ // Alerts
+ assign alert_test = {
+ reg2hw.alert_test.q &
+ reg2hw.alert_test.qe
+ };
+
+ for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[i]),
+ .IsFatal(i)
+ ) u_prim_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_req_i ( alerts[0] ),
+ .alert_ack_o ( ),
+ .alert_rx_i ( alert_rx_i[i] ),
+ .alert_tx_o ( alert_tx_o[i] )
+ );
+ end
+
+ /////////////////////////
+ // HMAC Error Handling //
+ /////////////////////////
+ logic msg_push_sha_disabled, hash_start_sha_disabled, update_seckey_inprocess;
+ logic hash_start_active; // `reg_hash_start` set when hash already in active
+ logic msg_push_not_allowed; // Message is received when `hash_start` isn't set
+ assign msg_push_sha_disabled = msg_write & ~sha_en;
+ assign hash_start_sha_disabled = reg_hash_start & ~sha_en;
+ assign hash_start_active = reg_hash_start & cfg_block;
+ assign msg_push_not_allowed = msg_fifo_req & ~msg_allowed;
+
+ always_comb begin
+ update_seckey_inprocess = 1'b0;
+ if (cfg_block) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ if (reg2hw.key[i].qe) begin
+ update_seckey_inprocess = update_seckey_inprocess | 1'b1;
+ end
+ end
+ end else begin
+ update_seckey_inprocess = 1'b0;
+ end
+ end
+
+ // Update ERR_CODE register and interrupt only when no pending interrupt.
+ // This ensures only the first event of the series of events can be seen to sw.
+ // It is recommended that the software reads ERR_CODE register when interrupt
+ // is pending to avoid any race conditions.
+ assign err_valid = ~reg2hw.intr_state.hmac_err.q &
+ ( msg_push_sha_disabled | hash_start_sha_disabled
+ | update_seckey_inprocess | hash_start_active
+ | msg_push_not_allowed );
+
+ always_comb begin
+ err_code = NoError;
+ unique case (1'b1)
+ msg_push_sha_disabled: begin
+ err_code = SwPushMsgWhenShaDisabled;
+ end
+ hash_start_sha_disabled: begin
+ err_code = SwHashStartWhenShaDisabled;
+ end
+
+ update_seckey_inprocess: begin
+ err_code = SwUpdateSecretKeyInProcess;
+ end
+
+ hash_start_active: begin
+ err_code = SwHashStartWhenActive;
+ end
+
+ msg_push_not_allowed: begin
+ err_code = SwPushMsgWhenDisallowed;
+ end
+
+ default: begin
+ err_code = NoError;
+ end
+ endcase
+ end
+
+ /////////////////////
+ // Unused Signals //
+ /////////////////////
+ logic unused_wmask;
+ assign unused_wmask = ^reg_fifo_wmask;
+
+ /////////////////////
+ // Idle output //
+ /////////////////////
+ // TBD this should be connected later
+ // Idle: AND condition of:
+ // - packer empty: Currently no way to guarantee the packer is empty.
+ // temporary, the logic uses packer output (reg_fifo_wvalid)
+ // - MSG_FIFO --> fifo_rvalid
+ // - HMAC_CORE --> hmac_core_idle
+ // - SHA2_CORE --> sha_core_idle
+ // - Clean interrupt status
+ logic idle;
+ assign idle = !reg_fifo_wvalid && !fifo_rvalid
+ && hmac_core_idle && sha_core_idle;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ idle_o <= 1'b 1;
+ end else begin
+ idle_o <= idle;
+ end
+ end
+
+
+
+endmodule
diff --git a/EDA-3283/rtl/hmac_core.sv b/EDA-3283/rtl/hmac_core.sv
new file mode 100644
index 00000000..d4f6d132
--- /dev/null
+++ b/EDA-3283/rtl/hmac_core.sv
@@ -0,0 +1,315 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// HMAC Core implementation
+
+module hmac_core import hmac_pkg::*; (
+ input clk_i,
+ input rst_ni,
+
+ input [255:0] secret_key, // {word0, word1, ..., word7}
+
+ input wipe_secret,
+ input [31:0] wipe_v,
+
+ input hmac_en,
+
+ input reg_hash_start,
+ input reg_hash_process,
+ output logic hash_done,
+ output logic sha_hash_start,
+ output logic sha_hash_process,
+ input sha_hash_done,
+
+ // fifo
+ output logic sha_rvalid,
+ output sha_fifo_t sha_rdata,
+ input sha_rready,
+
+ input fifo_rvalid,
+ input sha_fifo_t fifo_rdata,
+ output logic fifo_rready,
+
+ // fifo control (select and fifo write data)
+ output logic fifo_wsel, // 0: from reg, 1: from digest
+ output logic fifo_wvalid,
+ output logic [2:0] fifo_wdata_sel, // 0: digest[0] .. 7: digest[7]
+ input fifo_wready,
+
+ input [63:0] message_length,
+ output [63:0] sha_message_length,
+
+ output logic idle
+);
+
+ localparam int unsigned BlockSize = 512;
+ localparam int unsigned BlockSizeBits = $clog2(BlockSize);
+ localparam int unsigned HashWordBits = $clog2($bits(sha_word_t));
+
+ localparam bit [63:0] BlockSize64 = 64'(BlockSize);
+ localparam bit [BlockSizeBits:0] BlockSizeBSB = BlockSize[BlockSizeBits:0];
+
+ logic hash_start; // generated from internal state machine
+ logic hash_process; // generated from internal state machine to trigger hash
+ logic hmac_hash_done;
+
+ logic [BlockSize-1:0] i_pad ;
+ logic [BlockSize-1:0] o_pad ;
+
+ logic [63:0] txcount;
+ logic [BlockSizeBits-HashWordBits-1:0] pad_index;
+ logic clr_txcount, inc_txcount;
+
+ logic hmac_sha_rvalid;
+
+ typedef enum logic [1:0] {
+ SelIPad,
+ SelOPad,
+ SelFifo
+ } sel_rdata_t;
+
+ sel_rdata_t sel_rdata;
+
+ typedef enum logic {
+ SelIPadMsg,
+ SelOPadMsg
+ } sel_msglen_t;
+
+ sel_msglen_t sel_msglen;
+
+ typedef enum logic {
+ Inner, // Update when state goes to StIPad
+ Outer // Update when state enters StOPad
+ } round_t ;
+
+ logic update_round ;
+ round_t round_q, round_d;
+
+ typedef enum logic [2:0] {
+ StIdle,
+ StIPad,
+ StMsg, // Actual Msg, and Digest both
+ StPushToMsgFifo, // Digest --> Msg Fifo
+ StWaitResp, // Hash done( by checking processed_length? or hash_done)
+ StOPad,
+ StDone // hmac_done
+ } st_e ;
+
+ st_e st_q, st_d;
+
+ logic clr_fifo_wdata_sel;
+ logic txcnt_eq_blksz ;
+
+ logic reg_hash_process_flag;
+
+ assign sha_hash_start = (hmac_en) ? hash_start : reg_hash_start ;
+ assign sha_hash_process = (hmac_en) ? reg_hash_process | hash_process : reg_hash_process ;
+ assign hash_done = (hmac_en) ? hmac_hash_done : sha_hash_done ;
+
+ assign pad_index = txcount[BlockSizeBits-1:HashWordBits];
+
+ assign i_pad = {secret_key, {(BlockSize-256){1'b0}}} ^ {(BlockSize/8){8'h36}};
+ assign o_pad = {secret_key, {(BlockSize-256){1'b0}}} ^ {(BlockSize/8){8'h5c}};
+
+
+ assign fifo_rready = (hmac_en) ? (st_q == StMsg) & sha_rready : sha_rready ;
+ // sha_rvalid is controlled by State Machine below.
+ assign sha_rvalid = (!hmac_en) ? fifo_rvalid : hmac_sha_rvalid ;
+ assign sha_rdata =
+ (!hmac_en) ? fifo_rdata :
+ (sel_rdata == SelIPad) ? '{data: i_pad[(BlockSize-1)-32*pad_index-:32], mask: '1} :
+ (sel_rdata == SelOPad) ? '{data: o_pad[(BlockSize-1)-32*pad_index-:32], mask: '1} :
+ (sel_rdata == SelFifo) ? fifo_rdata :
+ '{default: '0};
+
+ assign sha_message_length = (!hmac_en) ? message_length :
+ (sel_msglen == SelIPadMsg) ? message_length + BlockSize64 :
+ (sel_msglen == SelOPadMsg) ? BlockSize64 + 64'd256 :
+ '0 ;
+
+ assign txcnt_eq_blksz = (txcount[BlockSizeBits:0] == BlockSizeBSB);
+
+ assign inc_txcount = sha_rready && sha_rvalid;
+
+ // txcount
+ // Looks like txcount can be removed entirely here in hmac_core
+ // In the first round (InnerPaddedKey), it can just watch process and hash_done
+ // In the second round, it only needs count 256 bits for hash digest to trigger
+ // hash_process to SHA2
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ txcount <= '0;
+ end else if (clr_txcount) begin
+ txcount <= '0;
+ end else if (inc_txcount) begin
+ txcount[63:5] <= txcount[63:5] + 1'b1;
+ end
+ end
+
+ // reg_hash_process trigger logic
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ reg_hash_process_flag <= 1'b0;
+ end else if (reg_hash_process) begin
+ reg_hash_process_flag <= 1'b1;
+ end else if (hmac_hash_done || reg_hash_start) begin
+ reg_hash_process_flag <= 1'b0;
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ round_q <= Inner;
+ end else if (update_round) begin
+ round_q <= round_d;
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_wdata_sel <= 3'h 0;
+ end else if (clr_fifo_wdata_sel) begin
+ fifo_wdata_sel <= 3'h 0;
+ end else if (fifo_wsel && fifo_wvalid) begin
+ fifo_wdata_sel <= fifo_wdata_sel + 1'b1;
+ end
+ end
+
+ assign sel_msglen = (round_q == Inner) ? SelIPadMsg : SelOPadMsg ;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : state_ff
+ if (!rst_ni) st_q <= StIdle;
+ else st_q <= st_d;
+ end
+
+ always_comb begin : next_state
+ hmac_hash_done = 1'b0;
+ hmac_sha_rvalid = 1'b0;
+
+ clr_txcount = 1'b0;
+
+ update_round = 1'b0;
+ round_d = Inner;
+
+ fifo_wsel = 1'b0; // from register
+ fifo_wvalid = 1'b0;
+
+ clr_fifo_wdata_sel = 1'b1;
+
+ sel_rdata = SelFifo;
+
+ hash_start = 1'b0;
+ hash_process = 1'b0;
+
+ unique case (st_q)
+ StIdle: begin
+ if (hmac_en && reg_hash_start) begin
+ st_d = StIPad;
+
+ clr_txcount = 1'b1;
+ update_round = 1'b1;
+ round_d = Inner;
+ hash_start = 1'b1;
+ end else begin
+ st_d = StIdle;
+ end
+ end
+
+ StIPad: begin
+ sel_rdata = SelIPad;
+
+ if (txcnt_eq_blksz) begin
+ st_d = StMsg;
+
+ hmac_sha_rvalid = 1'b0; // block new read request
+ end else begin
+ st_d = StIPad;
+
+ hmac_sha_rvalid = 1'b1;
+ end
+ end
+
+ StMsg: begin
+ sel_rdata = SelFifo;
+ fifo_wsel = (round_q == Outer);
+
+ if ( (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
+ && (txcount >= sha_message_length)) begin
+ st_d = StWaitResp;
+
+ hmac_sha_rvalid = 1'b0; // block
+ hash_process = (round_q == Outer);
+ end else begin
+ st_d = StMsg;
+
+ hmac_sha_rvalid = fifo_rvalid;
+ end
+ end
+
+ StWaitResp: begin
+ hmac_sha_rvalid = 1'b0;
+
+ if (sha_hash_done) begin
+ if (round_q == Outer) begin
+ st_d = StDone;
+ end else begin // round_q == Inner
+ st_d = StPushToMsgFifo;
+ end
+ end else begin
+ st_d = StWaitResp;
+ end
+ end
+
+ StPushToMsgFifo: begin
+ hmac_sha_rvalid = 1'b0;
+ fifo_wsel = 1'b1;
+ fifo_wvalid = 1'b1;
+ clr_fifo_wdata_sel = 1'b0;
+
+ if (fifo_wready && fifo_wdata_sel == 3'h7) begin
+ st_d = StOPad;
+
+ clr_txcount = 1'b1;
+ update_round = 1'b1;
+ round_d = Outer;
+ hash_start = 1'b1;
+ end else begin
+ st_d = StPushToMsgFifo;
+
+ end
+ end
+
+ StOPad: begin
+ sel_rdata = SelOPad;
+ fifo_wsel = 1'b1; // Remained HMAC select to indicate HMAC is in second stage
+
+ if (txcnt_eq_blksz) begin
+ st_d = StMsg;
+
+ hmac_sha_rvalid = 1'b0; // block new read request
+ end else begin
+ st_d = StOPad;
+
+ hmac_sha_rvalid = 1'b1;
+ end
+ end
+
+ StDone: begin
+ // raise interrupt (hash_done)
+ st_d = StIdle;
+
+ hmac_hash_done = 1'b1;
+ end
+
+ default: begin
+ st_d = StIdle;
+ end
+
+ endcase
+ end
+
+ // Idle: Idle in HMAC_CORE only represents the idle status when hmac mode is
+ // set. If hmac_en is 0, this logic sends the idle signal always.
+ assign idle = (st_q == StIdle) && !reg_hash_start;
+endmodule
diff --git a/EDA-3283/rtl/hmac_pkg.sv b/EDA-3283/rtl/hmac_pkg.sv
new file mode 100644
index 00000000..61160ffd
--- /dev/null
+++ b/EDA-3283/rtl/hmac_pkg.sv
@@ -0,0 +1,98 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package hmac_pkg;
+
+ localparam int MsgFifoDepth = 16;
+
+ localparam int NumRound = 64; // SHA-224, SHA-256
+
+ typedef logic [31:0] sha_word_t;
+ localparam int WordByte = $bits(sha_word_t)/8;
+
+ typedef struct packed {
+ sha_word_t data;
+ logic [WordByte-1:0] mask;
+ } sha_fifo_t;
+
+
+ localparam sha_word_t InitHash [8]= '{
+ 32'h 6a09_e667, 32'h bb67_ae85, 32'h 3c6e_f372, 32'h a54f_f53a,
+ 32'h 510e_527f, 32'h 9b05_688c, 32'h 1f83_d9ab, 32'h 5be0_cd19
+ };
+
+ localparam sha_word_t CubicRootPrime [64] = '{
+ 32'h 428a_2f98, 32'h 7137_4491, 32'h b5c0_fbcf, 32'h e9b5_dba5,
+ 32'h 3956_c25b, 32'h 59f1_11f1, 32'h 923f_82a4, 32'h ab1c_5ed5,
+ 32'h d807_aa98, 32'h 1283_5b01, 32'h 2431_85be, 32'h 550c_7dc3,
+ 32'h 72be_5d74, 32'h 80de_b1fe, 32'h 9bdc_06a7, 32'h c19b_f174,
+ 32'h e49b_69c1, 32'h efbe_4786, 32'h 0fc1_9dc6, 32'h 240c_a1cc,
+ 32'h 2de9_2c6f, 32'h 4a74_84aa, 32'h 5cb0_a9dc, 32'h 76f9_88da,
+ 32'h 983e_5152, 32'h a831_c66d, 32'h b003_27c8, 32'h bf59_7fc7,
+ 32'h c6e0_0bf3, 32'h d5a7_9147, 32'h 06ca_6351, 32'h 1429_2967,
+ 32'h 27b7_0a85, 32'h 2e1b_2138, 32'h 4d2c_6dfc, 32'h 5338_0d13,
+ 32'h 650a_7354, 32'h 766a_0abb, 32'h 81c2_c92e, 32'h 9272_2c85,
+ 32'h a2bf_e8a1, 32'h a81a_664b, 32'h c24b_8b70, 32'h c76c_51a3,
+ 32'h d192_e819, 32'h d699_0624, 32'h f40e_3585, 32'h 106a_a070,
+ 32'h 19a4_c116, 32'h 1e37_6c08, 32'h 2748_774c, 32'h 34b0_bcb5,
+ 32'h 391c_0cb3, 32'h 4ed8_aa4a, 32'h 5b9c_ca4f, 32'h 682e_6ff3,
+ 32'h 748f_82ee, 32'h 78a5_636f, 32'h 84c8_7814, 32'h 8cc7_0208,
+ 32'h 90be_fffa, 32'h a450_6ceb, 32'h bef9_a3f7, 32'h c671_78f2
+ };
+
+ function automatic sha_word_t conv_endian( input sha_word_t v, input logic swap);
+ sha_word_t conv_data = {<<8{v}};
+ conv_endian = (swap) ? conv_data : v ;
+ endfunction : conv_endian
+
+ function automatic sha_word_t rotr( input sha_word_t v , input int amt );
+ rotr = (v >> amt) | (v << (32-amt));
+ endfunction : rotr
+
+ function automatic sha_word_t shiftr( input sha_word_t v, input int amt );
+ shiftr = (v >> amt);
+ endfunction : shiftr
+
+ function automatic sha_word_t [7:0] compress( input sha_word_t w, input sha_word_t k,
+ input sha_word_t [7:0] h_i);
+ automatic sha_word_t sigma_0, sigma_1, ch, maj, temp1, temp2;
+
+ sigma_1 = rotr(h_i[4], 6) ^ rotr(h_i[4], 11) ^ rotr(h_i[4], 25);
+ ch = (h_i[4] & h_i[5]) ^ (~h_i[4] & h_i[6]);
+ temp1 = (h_i[7] + sigma_1 + ch + k + w);
+ sigma_0 = rotr(h_i[0], 2) ^ rotr(h_i[0], 13) ^ rotr(h_i[0], 22);
+ maj = (h_i[0] & h_i[1]) ^ (h_i[0] & h_i[2]) ^ (h_i[1] & h_i[2]);
+ temp2 = (sigma_0 + maj);
+
+ compress[7] = h_i[6]; // h = g
+ compress[6] = h_i[5]; // g = f
+ compress[5] = h_i[4]; // f = e
+ compress[4] = h_i[3] + temp1; // e = (d + temp1)
+ compress[3] = h_i[2]; // d = c
+ compress[2] = h_i[1]; // c = b
+ compress[1] = h_i[0]; // b = a
+ compress[0] = (temp1 + temp2); // a = (temp1 + temp2)
+ endfunction : compress
+
+ function automatic sha_word_t calc_w(input sha_word_t w_0,
+ input sha_word_t w_1,
+ input sha_word_t w_9,
+ input sha_word_t w_14);
+ automatic sha_word_t sum0, sum1;
+ sum0 = rotr(w_1, 7) ^ rotr(w_1, 18) ^ shiftr(w_1, 3);
+ sum1 = rotr(w_14, 17) ^ rotr(w_14, 19) ^ shiftr(w_14, 10);
+ calc_w = w_0 + sum0 + w_9 + sum1;
+ endfunction : calc_w
+
+ typedef enum logic [31:0] {
+ NoError = 32'h 0000_0000,
+ SwPushMsgWhenShaDisabled = 32'h 0000_0001,
+ SwHashStartWhenShaDisabled = 32'h 0000_0002,
+ SwUpdateSecretKeyInProcess = 32'h 0000_0003,
+ SwHashStartWhenActive = 32'h 0000_0004,
+ SwPushMsgWhenDisallowed = 32'h 0000_0005
+ } err_code_e;
+
+endpackage : hmac_pkg
diff --git a/EDA-3283/rtl/hmac_reg_pkg.sv b/EDA-3283/rtl/hmac_reg_pkg.sv
new file mode 100644
index 00000000..0751e71e
--- /dev/null
+++ b/EDA-3283/rtl/hmac_reg_pkg.sv
@@ -0,0 +1,320 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package hmac_reg_pkg;
+
+ // Param list
+ parameter int NumWords = 8;
+ parameter int NumAlerts = 1;
+
+ // Address widths within the block
+ parameter int BlockAw = 12;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } hmac_done;
+ struct packed {
+ logic q;
+ } fifo_empty;
+ struct packed {
+ logic q;
+ } hmac_err;
+ } hmac_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } hmac_done;
+ struct packed {
+ logic q;
+ } fifo_empty;
+ struct packed {
+ logic q;
+ } hmac_err;
+ } hmac_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } hmac_done;
+ struct packed {
+ logic q;
+ logic qe;
+ } fifo_empty;
+ struct packed {
+ logic q;
+ logic qe;
+ } hmac_err;
+ } hmac_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } hmac_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } hmac_en;
+ struct packed {
+ logic q;
+ logic qe;
+ } sha_en;
+ struct packed {
+ logic q;
+ logic qe;
+ } endian_swap;
+ struct packed {
+ logic q;
+ logic qe;
+ } digest_swap;
+ } hmac_reg2hw_cfg_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } hash_start;
+ struct packed {
+ logic q;
+ logic qe;
+ } hash_process;
+ } hmac_reg2hw_cmd_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ logic qe;
+ } hmac_reg2hw_wipe_secret_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ logic qe;
+ } hmac_reg2hw_key_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } hmac_done;
+ struct packed {
+ logic d;
+ logic de;
+ } fifo_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } hmac_err;
+ } hmac_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ } hmac_en;
+ struct packed {
+ logic d;
+ } sha_en;
+ struct packed {
+ logic d;
+ } endian_swap;
+ struct packed {
+ logic d;
+ } digest_swap;
+ } hmac_hw2reg_cfg_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ } fifo_empty;
+ struct packed {
+ logic d;
+ } fifo_full;
+ struct packed {
+ logic [4:0] d;
+ } fifo_depth;
+ } hmac_hw2reg_status_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ logic de;
+ } hmac_hw2reg_err_code_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } hmac_hw2reg_key_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } hmac_hw2reg_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ logic de;
+ } hmac_hw2reg_msg_length_lower_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ logic de;
+ } hmac_hw2reg_msg_length_upper_reg_t;
+
+ // Register -> HW type
+ typedef struct packed {
+ hmac_reg2hw_intr_state_reg_t intr_state; // [322:320]
+ hmac_reg2hw_intr_enable_reg_t intr_enable; // [319:317]
+ hmac_reg2hw_intr_test_reg_t intr_test; // [316:311]
+ hmac_reg2hw_alert_test_reg_t alert_test; // [310:309]
+ hmac_reg2hw_cfg_reg_t cfg; // [308:301]
+ hmac_reg2hw_cmd_reg_t cmd; // [300:297]
+ hmac_reg2hw_wipe_secret_reg_t wipe_secret; // [296:264]
+ hmac_reg2hw_key_mreg_t [7:0] key; // [263:0]
+ } hmac_reg2hw_t;
+
+ // HW -> register type
+ typedef struct packed {
+ hmac_hw2reg_intr_state_reg_t intr_state; // [627:622]
+ hmac_hw2reg_cfg_reg_t cfg; // [621:618]
+ hmac_hw2reg_status_reg_t status; // [617:611]
+ hmac_hw2reg_err_code_reg_t err_code; // [610:578]
+ hmac_hw2reg_key_mreg_t [7:0] key; // [577:322]
+ hmac_hw2reg_digest_mreg_t [7:0] digest; // [321:66]
+ hmac_hw2reg_msg_length_lower_reg_t msg_length_lower; // [65:33]
+ hmac_hw2reg_msg_length_upper_reg_t msg_length_upper; // [32:0]
+ } hmac_hw2reg_t;
+
+ // Register offsets
+ parameter logic [BlockAw-1:0] HMAC_INTR_STATE_OFFSET = 12'h 0;
+ parameter logic [BlockAw-1:0] HMAC_INTR_ENABLE_OFFSET = 12'h 4;
+ parameter logic [BlockAw-1:0] HMAC_INTR_TEST_OFFSET = 12'h 8;
+ parameter logic [BlockAw-1:0] HMAC_ALERT_TEST_OFFSET = 12'h c;
+ parameter logic [BlockAw-1:0] HMAC_CFG_OFFSET = 12'h 10;
+ parameter logic [BlockAw-1:0] HMAC_CMD_OFFSET = 12'h 14;
+ parameter logic [BlockAw-1:0] HMAC_STATUS_OFFSET = 12'h 18;
+ parameter logic [BlockAw-1:0] HMAC_ERR_CODE_OFFSET = 12'h 1c;
+ parameter logic [BlockAw-1:0] HMAC_WIPE_SECRET_OFFSET = 12'h 20;
+ parameter logic [BlockAw-1:0] HMAC_KEY_0_OFFSET = 12'h 24;
+ parameter logic [BlockAw-1:0] HMAC_KEY_1_OFFSET = 12'h 28;
+ parameter logic [BlockAw-1:0] HMAC_KEY_2_OFFSET = 12'h 2c;
+ parameter logic [BlockAw-1:0] HMAC_KEY_3_OFFSET = 12'h 30;
+ parameter logic [BlockAw-1:0] HMAC_KEY_4_OFFSET = 12'h 34;
+ parameter logic [BlockAw-1:0] HMAC_KEY_5_OFFSET = 12'h 38;
+ parameter logic [BlockAw-1:0] HMAC_KEY_6_OFFSET = 12'h 3c;
+ parameter logic [BlockAw-1:0] HMAC_KEY_7_OFFSET = 12'h 40;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_0_OFFSET = 12'h 44;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_1_OFFSET = 12'h 48;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_2_OFFSET = 12'h 4c;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_3_OFFSET = 12'h 50;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_4_OFFSET = 12'h 54;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_5_OFFSET = 12'h 58;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_6_OFFSET = 12'h 5c;
+ parameter logic [BlockAw-1:0] HMAC_DIGEST_7_OFFSET = 12'h 60;
+ parameter logic [BlockAw-1:0] HMAC_MSG_LENGTH_LOWER_OFFSET = 12'h 64;
+ parameter logic [BlockAw-1:0] HMAC_MSG_LENGTH_UPPER_OFFSET = 12'h 68;
+
+ // Reset values for hwext registers and their fields
+ parameter logic [2:0] HMAC_INTR_TEST_RESVAL = 3'h 0;
+ parameter logic [0:0] HMAC_INTR_TEST_HMAC_DONE_RESVAL = 1'h 0;
+ parameter logic [0:0] HMAC_INTR_TEST_FIFO_EMPTY_RESVAL = 1'h 0;
+ parameter logic [0:0] HMAC_INTR_TEST_HMAC_ERR_RESVAL = 1'h 0;
+ parameter logic [0:0] HMAC_ALERT_TEST_RESVAL = 1'h 0;
+ parameter logic [0:0] HMAC_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0;
+ parameter logic [3:0] HMAC_CFG_RESVAL = 4'h 4;
+ parameter logic [0:0] HMAC_CFG_ENDIAN_SWAP_RESVAL = 1'h 1;
+ parameter logic [0:0] HMAC_CFG_DIGEST_SWAP_RESVAL = 1'h 0;
+ parameter logic [1:0] HMAC_CMD_RESVAL = 2'h 0;
+ parameter logic [8:0] HMAC_STATUS_RESVAL = 9'h 1;
+ parameter logic [0:0] HMAC_STATUS_FIFO_EMPTY_RESVAL = 1'h 1;
+ parameter logic [31:0] HMAC_WIPE_SECRET_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_KEY_0_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_KEY_1_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_KEY_2_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_KEY_3_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_KEY_4_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_KEY_5_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_KEY_6_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_KEY_7_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_DIGEST_1_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_DIGEST_2_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_DIGEST_3_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_DIGEST_4_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_DIGEST_5_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_DIGEST_6_RESVAL = 32'h 0;
+ parameter logic [31:0] HMAC_DIGEST_7_RESVAL = 32'h 0;
+
+ // Window parameters
+ parameter logic [BlockAw-1:0] HMAC_MSG_FIFO_OFFSET = 12'h 800;
+ parameter int unsigned HMAC_MSG_FIFO_SIZE = 'h 800;
+
+ // Register index
+ typedef enum int {
+ HMAC_INTR_STATE,
+ HMAC_INTR_ENABLE,
+ HMAC_INTR_TEST,
+ HMAC_ALERT_TEST,
+ HMAC_CFG,
+ HMAC_CMD,
+ HMAC_STATUS,
+ HMAC_ERR_CODE,
+ HMAC_WIPE_SECRET,
+ HMAC_KEY_0,
+ HMAC_KEY_1,
+ HMAC_KEY_2,
+ HMAC_KEY_3,
+ HMAC_KEY_4,
+ HMAC_KEY_5,
+ HMAC_KEY_6,
+ HMAC_KEY_7,
+ HMAC_DIGEST_0,
+ HMAC_DIGEST_1,
+ HMAC_DIGEST_2,
+ HMAC_DIGEST_3,
+ HMAC_DIGEST_4,
+ HMAC_DIGEST_5,
+ HMAC_DIGEST_6,
+ HMAC_DIGEST_7,
+ HMAC_MSG_LENGTH_LOWER,
+ HMAC_MSG_LENGTH_UPPER
+ } hmac_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] HMAC_PERMIT [27] = '{
+ 4'b 0001, // index[ 0] HMAC_INTR_STATE
+ 4'b 0001, // index[ 1] HMAC_INTR_ENABLE
+ 4'b 0001, // index[ 2] HMAC_INTR_TEST
+ 4'b 0001, // index[ 3] HMAC_ALERT_TEST
+ 4'b 0001, // index[ 4] HMAC_CFG
+ 4'b 0001, // index[ 5] HMAC_CMD
+ 4'b 0011, // index[ 6] HMAC_STATUS
+ 4'b 1111, // index[ 7] HMAC_ERR_CODE
+ 4'b 1111, // index[ 8] HMAC_WIPE_SECRET
+ 4'b 1111, // index[ 9] HMAC_KEY_0
+ 4'b 1111, // index[10] HMAC_KEY_1
+ 4'b 1111, // index[11] HMAC_KEY_2
+ 4'b 1111, // index[12] HMAC_KEY_3
+ 4'b 1111, // index[13] HMAC_KEY_4
+ 4'b 1111, // index[14] HMAC_KEY_5
+ 4'b 1111, // index[15] HMAC_KEY_6
+ 4'b 1111, // index[16] HMAC_KEY_7
+ 4'b 1111, // index[17] HMAC_DIGEST_0
+ 4'b 1111, // index[18] HMAC_DIGEST_1
+ 4'b 1111, // index[19] HMAC_DIGEST_2
+ 4'b 1111, // index[20] HMAC_DIGEST_3
+ 4'b 1111, // index[21] HMAC_DIGEST_4
+ 4'b 1111, // index[22] HMAC_DIGEST_5
+ 4'b 1111, // index[23] HMAC_DIGEST_6
+ 4'b 1111, // index[24] HMAC_DIGEST_7
+ 4'b 1111, // index[25] HMAC_MSG_LENGTH_LOWER
+ 4'b 1111 // index[26] HMAC_MSG_LENGTH_UPPER
+ };
+
+endpackage
+
diff --git a/EDA-3283/rtl/hmac_reg_top.sv b/EDA-3283/rtl/hmac_reg_top.sv
new file mode 100644
index 00000000..d1c2bfda
--- /dev/null
+++ b/EDA-3283/rtl/hmac_reg_top.sv
@@ -0,0 +1,1230 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+
+module hmac_reg_top (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // Output port for window
+ output tlul_pkg::tl_h2d_t tl_win_o,
+ input tlul_pkg::tl_d2h_t tl_win_i,
+
+ // To HW
+ output hmac_reg_pkg::hmac_reg2hw_t reg2hw, // Write
+ input hmac_reg_pkg::hmac_hw2reg_t hw2reg, // Read
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import hmac_reg_pkg::* ;
+
+ localparam int AW = 12;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+ logic reg_busy;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ logic intg_err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_q <= '0;
+ end else if (intg_err) begin
+ intg_err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = intg_err_q | intg_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ tlul_pkg::tl_h2d_t tl_socket_h2d [2];
+ tlul_pkg::tl_d2h_t tl_socket_d2h [2];
+
+ logic [0:0] reg_steer;
+
+ // socket_1n connection
+ assign tl_reg_h2d = tl_socket_h2d[1];
+ assign tl_socket_d2h[1] = tl_reg_d2h;
+
+ assign tl_win_o = tl_socket_h2d[0];
+ assign tl_socket_d2h[0] = tl_win_i;
+
+ // Create Socket_1n
+ tlul_socket_1n #(
+ .N (2),
+ .HReqPass (1'b1),
+ .HRspPass (1'b1),
+ .DReqPass ({2{1'b1}}),
+ .DRspPass ({2{1'b1}}),
+ .HReqDepth (4'h0),
+ .HRspDepth (4'h0),
+ .DReqDepth ({2{4'h0}}),
+ .DRspDepth ({2{4'h0}})
+ ) u_socket (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .tl_h_i (tl_i),
+ .tl_h_o (tl_o_pre),
+ .tl_d_o (tl_socket_h2d),
+ .tl_d_i (tl_socket_d2h),
+ .dev_select_i (reg_steer)
+ );
+
+ // Create steering logic
+ always_comb begin
+ unique case (tl_i.a_address[AW-1:0]) inside
+ [2048:4095]: begin
+ reg_steer = 0;
+ end
+ default: begin
+ // Default set to register
+ reg_steer = 1;
+ end
+ endcase
+
+ // Override this in case of an integrity error
+ if (intg_err) begin
+ reg_steer = 1;
+ end
+ end
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW),
+ .EnableDataIntgGen(0)
+ ) u_reg_if (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ // cdc oversampling signals
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+
+ // Define SW related signals
+ // Format: __{wd|we|qs}
+ // or _{wd|we|qs} if field == 1 or 0
+ logic intr_state_we;
+ logic intr_state_hmac_done_qs;
+ logic intr_state_hmac_done_wd;
+ logic intr_state_fifo_empty_qs;
+ logic intr_state_fifo_empty_wd;
+ logic intr_state_hmac_err_qs;
+ logic intr_state_hmac_err_wd;
+ logic intr_enable_we;
+ logic intr_enable_hmac_done_qs;
+ logic intr_enable_hmac_done_wd;
+ logic intr_enable_fifo_empty_qs;
+ logic intr_enable_fifo_empty_wd;
+ logic intr_enable_hmac_err_qs;
+ logic intr_enable_hmac_err_wd;
+ logic intr_test_we;
+ logic intr_test_hmac_done_wd;
+ logic intr_test_fifo_empty_wd;
+ logic intr_test_hmac_err_wd;
+ logic alert_test_we;
+ logic alert_test_wd;
+ logic cfg_re;
+ logic cfg_we;
+ logic cfg_hmac_en_qs;
+ logic cfg_hmac_en_wd;
+ logic cfg_sha_en_qs;
+ logic cfg_sha_en_wd;
+ logic cfg_endian_swap_qs;
+ logic cfg_endian_swap_wd;
+ logic cfg_digest_swap_qs;
+ logic cfg_digest_swap_wd;
+ logic cmd_we;
+ logic cmd_hash_start_wd;
+ logic cmd_hash_process_wd;
+ logic status_re;
+ logic status_fifo_empty_qs;
+ logic status_fifo_full_qs;
+ logic [4:0] status_fifo_depth_qs;
+ logic [31:0] err_code_qs;
+ logic wipe_secret_we;
+ logic [31:0] wipe_secret_wd;
+ logic key_0_we;
+ logic [31:0] key_0_wd;
+ logic key_1_we;
+ logic [31:0] key_1_wd;
+ logic key_2_we;
+ logic [31:0] key_2_wd;
+ logic key_3_we;
+ logic [31:0] key_3_wd;
+ logic key_4_we;
+ logic [31:0] key_4_wd;
+ logic key_5_we;
+ logic [31:0] key_5_wd;
+ logic key_6_we;
+ logic [31:0] key_6_wd;
+ logic key_7_we;
+ logic [31:0] key_7_wd;
+ logic digest_0_re;
+ logic [31:0] digest_0_qs;
+ logic digest_1_re;
+ logic [31:0] digest_1_qs;
+ logic digest_2_re;
+ logic [31:0] digest_2_qs;
+ logic digest_3_re;
+ logic [31:0] digest_3_qs;
+ logic digest_4_re;
+ logic [31:0] digest_4_qs;
+ logic digest_5_re;
+ logic [31:0] digest_5_qs;
+ logic digest_6_re;
+ logic [31:0] digest_6_qs;
+ logic digest_7_re;
+ logic [31:0] digest_7_qs;
+ logic [31:0] msg_length_lower_qs;
+ logic [31:0] msg_length_upper_qs;
+
+ // Register instances
+ // R[intr_state]: V(False)
+ // F[hmac_done]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_hmac_done (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_hmac_done_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.hmac_done.de),
+ .d (hw2reg.intr_state.hmac_done.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.hmac_done.q),
+
+ // to register interface (read)
+ .qs (intr_state_hmac_done_qs)
+ );
+
+ // F[fifo_empty]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_fifo_empty (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_fifo_empty_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.fifo_empty.de),
+ .d (hw2reg.intr_state.fifo_empty.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.fifo_empty.q),
+
+ // to register interface (read)
+ .qs (intr_state_fifo_empty_qs)
+ );
+
+ // F[hmac_err]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_hmac_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_hmac_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.hmac_err.de),
+ .d (hw2reg.intr_state.hmac_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.hmac_err.q),
+
+ // to register interface (read)
+ .qs (intr_state_hmac_err_qs)
+ );
+
+
+ // R[intr_enable]: V(False)
+ // F[hmac_done]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_hmac_done (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_hmac_done_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.hmac_done.q),
+
+ // to register interface (read)
+ .qs (intr_enable_hmac_done_qs)
+ );
+
+ // F[fifo_empty]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_fifo_empty (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_fifo_empty_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.fifo_empty.q),
+
+ // to register interface (read)
+ .qs (intr_enable_fifo_empty_qs)
+ );
+
+ // F[hmac_err]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_hmac_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_hmac_err_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.hmac_err.q),
+
+ // to register interface (read)
+ .qs (intr_enable_hmac_err_qs)
+ );
+
+
+ // R[intr_test]: V(True)
+ // F[hmac_done]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_hmac_done (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_hmac_done_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.hmac_done.qe),
+ .q (reg2hw.intr_test.hmac_done.q),
+ .qs ()
+ );
+
+ // F[fifo_empty]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_fifo_empty (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_fifo_empty_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.fifo_empty.qe),
+ .q (reg2hw.intr_test.fifo_empty.q),
+ .qs ()
+ );
+
+ // F[hmac_err]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_hmac_err (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_hmac_err_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.hmac_err.qe),
+ .q (reg2hw.intr_test.hmac_err.q),
+ .qs ()
+ );
+
+
+ // R[alert_test]: V(True)
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.alert_test.qe),
+ .q (reg2hw.alert_test.q),
+ .qs ()
+ );
+
+
+ // R[cfg]: V(True)
+ // F[hmac_en]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cfg_hmac_en (
+ .re (cfg_re),
+ .we (cfg_we),
+ .wd (cfg_hmac_en_wd),
+ .d (hw2reg.cfg.hmac_en.d),
+ .qre (),
+ .qe (reg2hw.cfg.hmac_en.qe),
+ .q (reg2hw.cfg.hmac_en.q),
+ .qs (cfg_hmac_en_qs)
+ );
+
+ // F[sha_en]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cfg_sha_en (
+ .re (cfg_re),
+ .we (cfg_we),
+ .wd (cfg_sha_en_wd),
+ .d (hw2reg.cfg.sha_en.d),
+ .qre (),
+ .qe (reg2hw.cfg.sha_en.qe),
+ .q (reg2hw.cfg.sha_en.q),
+ .qs (cfg_sha_en_qs)
+ );
+
+ // F[endian_swap]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cfg_endian_swap (
+ .re (cfg_re),
+ .we (cfg_we),
+ .wd (cfg_endian_swap_wd),
+ .d (hw2reg.cfg.endian_swap.d),
+ .qre (),
+ .qe (reg2hw.cfg.endian_swap.qe),
+ .q (reg2hw.cfg.endian_swap.q),
+ .qs (cfg_endian_swap_qs)
+ );
+
+ // F[digest_swap]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cfg_digest_swap (
+ .re (cfg_re),
+ .we (cfg_we),
+ .wd (cfg_digest_swap_wd),
+ .d (hw2reg.cfg.digest_swap.d),
+ .qre (),
+ .qe (reg2hw.cfg.digest_swap.qe),
+ .q (reg2hw.cfg.digest_swap.q),
+ .qs (cfg_digest_swap_qs)
+ );
+
+
+ // R[cmd]: V(True)
+ // F[hash_start]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cmd_hash_start (
+ .re (1'b0),
+ .we (cmd_we),
+ .wd (cmd_hash_start_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.cmd.hash_start.qe),
+ .q (reg2hw.cmd.hash_start.q),
+ .qs ()
+ );
+
+ // F[hash_process]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cmd_hash_process (
+ .re (1'b0),
+ .we (cmd_we),
+ .wd (cmd_hash_process_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.cmd.hash_process.qe),
+ .q (reg2hw.cmd.hash_process.q),
+ .qs ()
+ );
+
+
+ // R[status]: V(True)
+ // F[fifo_empty]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_fifo_empty (
+ .re (status_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.fifo_empty.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (status_fifo_empty_qs)
+ );
+
+ // F[fifo_full]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_fifo_full (
+ .re (status_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.fifo_full.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (status_fifo_full_qs)
+ );
+
+ // F[fifo_depth]: 8:4
+ prim_subreg_ext #(
+ .DW (5)
+ ) u_status_fifo_depth (
+ .re (status_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.fifo_depth.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (status_fifo_depth_qs)
+ );
+
+
+ // R[err_code]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (32'h0)
+ ) u_err_code (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.err_code.de),
+ .d (hw2reg.err_code.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (err_code_qs)
+ );
+
+
+ // R[wipe_secret]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_wipe_secret (
+ .re (1'b0),
+ .we (wipe_secret_we),
+ .wd (wipe_secret_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.wipe_secret.qe),
+ .q (reg2hw.wipe_secret.q),
+ .qs ()
+ );
+
+
+ // Subregister 0 of Multireg key
+ // R[key_0]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_0 (
+ .re (1'b0),
+ .we (key_0_we),
+ .wd (key_0_wd),
+ .d (hw2reg.key[0].d),
+ .qre (),
+ .qe (reg2hw.key[0].qe),
+ .q (reg2hw.key[0].q),
+ .qs ()
+ );
+
+
+ // Subregister 1 of Multireg key
+ // R[key_1]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_1 (
+ .re (1'b0),
+ .we (key_1_we),
+ .wd (key_1_wd),
+ .d (hw2reg.key[1].d),
+ .qre (),
+ .qe (reg2hw.key[1].qe),
+ .q (reg2hw.key[1].q),
+ .qs ()
+ );
+
+
+ // Subregister 2 of Multireg key
+ // R[key_2]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_2 (
+ .re (1'b0),
+ .we (key_2_we),
+ .wd (key_2_wd),
+ .d (hw2reg.key[2].d),
+ .qre (),
+ .qe (reg2hw.key[2].qe),
+ .q (reg2hw.key[2].q),
+ .qs ()
+ );
+
+
+ // Subregister 3 of Multireg key
+ // R[key_3]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_3 (
+ .re (1'b0),
+ .we (key_3_we),
+ .wd (key_3_wd),
+ .d (hw2reg.key[3].d),
+ .qre (),
+ .qe (reg2hw.key[3].qe),
+ .q (reg2hw.key[3].q),
+ .qs ()
+ );
+
+
+ // Subregister 4 of Multireg key
+ // R[key_4]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_4 (
+ .re (1'b0),
+ .we (key_4_we),
+ .wd (key_4_wd),
+ .d (hw2reg.key[4].d),
+ .qre (),
+ .qe (reg2hw.key[4].qe),
+ .q (reg2hw.key[4].q),
+ .qs ()
+ );
+
+
+ // Subregister 5 of Multireg key
+ // R[key_5]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_5 (
+ .re (1'b0),
+ .we (key_5_we),
+ .wd (key_5_wd),
+ .d (hw2reg.key[5].d),
+ .qre (),
+ .qe (reg2hw.key[5].qe),
+ .q (reg2hw.key[5].q),
+ .qs ()
+ );
+
+
+ // Subregister 6 of Multireg key
+ // R[key_6]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_6 (
+ .re (1'b0),
+ .we (key_6_we),
+ .wd (key_6_wd),
+ .d (hw2reg.key[6].d),
+ .qre (),
+ .qe (reg2hw.key[6].qe),
+ .q (reg2hw.key[6].q),
+ .qs ()
+ );
+
+
+ // Subregister 7 of Multireg key
+ // R[key_7]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_key_7 (
+ .re (1'b0),
+ .we (key_7_we),
+ .wd (key_7_wd),
+ .d (hw2reg.key[7].d),
+ .qre (),
+ .qe (reg2hw.key[7].qe),
+ .q (reg2hw.key[7].q),
+ .qs ()
+ );
+
+
+ // Subregister 0 of Multireg digest
+ // R[digest_0]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_0 (
+ .re (digest_0_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[0].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg digest
+ // R[digest_1]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_1 (
+ .re (digest_1_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[1].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg digest
+ // R[digest_2]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_2 (
+ .re (digest_2_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[2].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg digest
+ // R[digest_3]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_3 (
+ .re (digest_3_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[3].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg digest
+ // R[digest_4]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_4 (
+ .re (digest_4_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[4].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg digest
+ // R[digest_5]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_5 (
+ .re (digest_5_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[5].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg digest
+ // R[digest_6]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_6 (
+ .re (digest_6_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[6].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg digest
+ // R[digest_7]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_digest_7 (
+ .re (digest_7_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.digest[7].d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (digest_7_qs)
+ );
+
+
+ // R[msg_length_lower]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (32'h0)
+ ) u_msg_length_lower (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.msg_length_lower.de),
+ .d (hw2reg.msg_length_lower.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (msg_length_lower_qs)
+ );
+
+
+ // R[msg_length_upper]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (32'h0)
+ ) u_msg_length_upper (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.msg_length_upper.de),
+ .d (hw2reg.msg_length_upper.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (msg_length_upper_qs)
+ );
+
+
+
+ logic [26:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == HMAC_INTR_STATE_OFFSET);
+ addr_hit[ 1] = (reg_addr == HMAC_INTR_ENABLE_OFFSET);
+ addr_hit[ 2] = (reg_addr == HMAC_INTR_TEST_OFFSET);
+ addr_hit[ 3] = (reg_addr == HMAC_ALERT_TEST_OFFSET);
+ addr_hit[ 4] = (reg_addr == HMAC_CFG_OFFSET);
+ addr_hit[ 5] = (reg_addr == HMAC_CMD_OFFSET);
+ addr_hit[ 6] = (reg_addr == HMAC_STATUS_OFFSET);
+ addr_hit[ 7] = (reg_addr == HMAC_ERR_CODE_OFFSET);
+ addr_hit[ 8] = (reg_addr == HMAC_WIPE_SECRET_OFFSET);
+ addr_hit[ 9] = (reg_addr == HMAC_KEY_0_OFFSET);
+ addr_hit[10] = (reg_addr == HMAC_KEY_1_OFFSET);
+ addr_hit[11] = (reg_addr == HMAC_KEY_2_OFFSET);
+ addr_hit[12] = (reg_addr == HMAC_KEY_3_OFFSET);
+ addr_hit[13] = (reg_addr == HMAC_KEY_4_OFFSET);
+ addr_hit[14] = (reg_addr == HMAC_KEY_5_OFFSET);
+ addr_hit[15] = (reg_addr == HMAC_KEY_6_OFFSET);
+ addr_hit[16] = (reg_addr == HMAC_KEY_7_OFFSET);
+ addr_hit[17] = (reg_addr == HMAC_DIGEST_0_OFFSET);
+ addr_hit[18] = (reg_addr == HMAC_DIGEST_1_OFFSET);
+ addr_hit[19] = (reg_addr == HMAC_DIGEST_2_OFFSET);
+ addr_hit[20] = (reg_addr == HMAC_DIGEST_3_OFFSET);
+ addr_hit[21] = (reg_addr == HMAC_DIGEST_4_OFFSET);
+ addr_hit[22] = (reg_addr == HMAC_DIGEST_5_OFFSET);
+ addr_hit[23] = (reg_addr == HMAC_DIGEST_6_OFFSET);
+ addr_hit[24] = (reg_addr == HMAC_DIGEST_7_OFFSET);
+ addr_hit[25] = (reg_addr == HMAC_MSG_LENGTH_LOWER_OFFSET);
+ addr_hit[26] = (reg_addr == HMAC_MSG_LENGTH_UPPER_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = (reg_we &
+ ((addr_hit[ 0] & (|(HMAC_PERMIT[ 0] & ~reg_be))) |
+ (addr_hit[ 1] & (|(HMAC_PERMIT[ 1] & ~reg_be))) |
+ (addr_hit[ 2] & (|(HMAC_PERMIT[ 2] & ~reg_be))) |
+ (addr_hit[ 3] & (|(HMAC_PERMIT[ 3] & ~reg_be))) |
+ (addr_hit[ 4] & (|(HMAC_PERMIT[ 4] & ~reg_be))) |
+ (addr_hit[ 5] & (|(HMAC_PERMIT[ 5] & ~reg_be))) |
+ (addr_hit[ 6] & (|(HMAC_PERMIT[ 6] & ~reg_be))) |
+ (addr_hit[ 7] & (|(HMAC_PERMIT[ 7] & ~reg_be))) |
+ (addr_hit[ 8] & (|(HMAC_PERMIT[ 8] & ~reg_be))) |
+ (addr_hit[ 9] & (|(HMAC_PERMIT[ 9] & ~reg_be))) |
+ (addr_hit[10] & (|(HMAC_PERMIT[10] & ~reg_be))) |
+ (addr_hit[11] & (|(HMAC_PERMIT[11] & ~reg_be))) |
+ (addr_hit[12] & (|(HMAC_PERMIT[12] & ~reg_be))) |
+ (addr_hit[13] & (|(HMAC_PERMIT[13] & ~reg_be))) |
+ (addr_hit[14] & (|(HMAC_PERMIT[14] & ~reg_be))) |
+ (addr_hit[15] & (|(HMAC_PERMIT[15] & ~reg_be))) |
+ (addr_hit[16] & (|(HMAC_PERMIT[16] & ~reg_be))) |
+ (addr_hit[17] & (|(HMAC_PERMIT[17] & ~reg_be))) |
+ (addr_hit[18] & (|(HMAC_PERMIT[18] & ~reg_be))) |
+ (addr_hit[19] & (|(HMAC_PERMIT[19] & ~reg_be))) |
+ (addr_hit[20] & (|(HMAC_PERMIT[20] & ~reg_be))) |
+ (addr_hit[21] & (|(HMAC_PERMIT[21] & ~reg_be))) |
+ (addr_hit[22] & (|(HMAC_PERMIT[22] & ~reg_be))) |
+ (addr_hit[23] & (|(HMAC_PERMIT[23] & ~reg_be))) |
+ (addr_hit[24] & (|(HMAC_PERMIT[24] & ~reg_be))) |
+ (addr_hit[25] & (|(HMAC_PERMIT[25] & ~reg_be))) |
+ (addr_hit[26] & (|(HMAC_PERMIT[26] & ~reg_be)))));
+ end
+ assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
+
+ assign intr_state_hmac_done_wd = reg_wdata[0];
+
+ assign intr_state_fifo_empty_wd = reg_wdata[1];
+
+ assign intr_state_hmac_err_wd = reg_wdata[2];
+ assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
+
+ assign intr_enable_hmac_done_wd = reg_wdata[0];
+
+ assign intr_enable_fifo_empty_wd = reg_wdata[1];
+
+ assign intr_enable_hmac_err_wd = reg_wdata[2];
+ assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
+
+ assign intr_test_hmac_done_wd = reg_wdata[0];
+
+ assign intr_test_fifo_empty_wd = reg_wdata[1];
+
+ assign intr_test_hmac_err_wd = reg_wdata[2];
+ assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
+
+ assign alert_test_wd = reg_wdata[0];
+ assign cfg_re = addr_hit[4] & reg_re & !reg_error;
+ assign cfg_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign cfg_hmac_en_wd = reg_wdata[0];
+
+ assign cfg_sha_en_wd = reg_wdata[1];
+
+ assign cfg_endian_swap_wd = reg_wdata[2];
+
+ assign cfg_digest_swap_wd = reg_wdata[3];
+ assign cmd_we = addr_hit[5] & reg_we & !reg_error;
+
+ assign cmd_hash_start_wd = reg_wdata[0];
+
+ assign cmd_hash_process_wd = reg_wdata[1];
+ assign status_re = addr_hit[6] & reg_re & !reg_error;
+ assign wipe_secret_we = addr_hit[8] & reg_we & !reg_error;
+
+ assign wipe_secret_wd = reg_wdata[31:0];
+ assign key_0_we = addr_hit[9] & reg_we & !reg_error;
+
+ assign key_0_wd = reg_wdata[31:0];
+ assign key_1_we = addr_hit[10] & reg_we & !reg_error;
+
+ assign key_1_wd = reg_wdata[31:0];
+ assign key_2_we = addr_hit[11] & reg_we & !reg_error;
+
+ assign key_2_wd = reg_wdata[31:0];
+ assign key_3_we = addr_hit[12] & reg_we & !reg_error;
+
+ assign key_3_wd = reg_wdata[31:0];
+ assign key_4_we = addr_hit[13] & reg_we & !reg_error;
+
+ assign key_4_wd = reg_wdata[31:0];
+ assign key_5_we = addr_hit[14] & reg_we & !reg_error;
+
+ assign key_5_wd = reg_wdata[31:0];
+ assign key_6_we = addr_hit[15] & reg_we & !reg_error;
+
+ assign key_6_wd = reg_wdata[31:0];
+ assign key_7_we = addr_hit[16] & reg_we & !reg_error;
+
+ assign key_7_wd = reg_wdata[31:0];
+ assign digest_0_re = addr_hit[17] & reg_re & !reg_error;
+ assign digest_1_re = addr_hit[18] & reg_re & !reg_error;
+ assign digest_2_re = addr_hit[19] & reg_re & !reg_error;
+ assign digest_3_re = addr_hit[20] & reg_re & !reg_error;
+ assign digest_4_re = addr_hit[21] & reg_re & !reg_error;
+ assign digest_5_re = addr_hit[22] & reg_re & !reg_error;
+ assign digest_6_re = addr_hit[23] & reg_re & !reg_error;
+ assign digest_7_re = addr_hit[24] & reg_re & !reg_error;
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = intr_state_hmac_done_qs;
+ reg_rdata_next[1] = intr_state_fifo_empty_qs;
+ reg_rdata_next[2] = intr_state_hmac_err_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[0] = intr_enable_hmac_done_qs;
+ reg_rdata_next[1] = intr_enable_fifo_empty_qs;
+ reg_rdata_next[2] = intr_enable_hmac_err_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ reg_rdata_next[2] = '0;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[0] = '0;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[0] = cfg_hmac_en_qs;
+ reg_rdata_next[1] = cfg_sha_en_qs;
+ reg_rdata_next[2] = cfg_endian_swap_qs;
+ reg_rdata_next[3] = cfg_digest_swap_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[0] = status_fifo_empty_qs;
+ reg_rdata_next[1] = status_fifo_full_qs;
+ reg_rdata_next[8:4] = status_fifo_depth_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[31:0] = err_code_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[31:0] = digest_0_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[31:0] = digest_1_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[31:0] = digest_2_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[31:0] = digest_3_qs;
+ end
+
+ addr_hit[21]: begin
+ reg_rdata_next[31:0] = digest_4_qs;
+ end
+
+ addr_hit[22]: begin
+ reg_rdata_next[31:0] = digest_5_qs;
+ end
+
+ addr_hit[23]: begin
+ reg_rdata_next[31:0] = digest_6_qs;
+ end
+
+ addr_hit[24]: begin
+ reg_rdata_next[31:0] = digest_7_qs;
+ end
+
+ addr_hit[25]: begin
+ reg_rdata_next[31:0] = msg_length_lower_qs;
+ end
+
+ addr_hit[26]: begin
+ reg_rdata_next[31:0] = msg_length_upper_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // shadow busy
+ logic shadow_busy;
+ assign shadow_busy = 1'b0;
+
+ // register busy
+ logic reg_busy_sel;
+ assign reg_busy = reg_busy_sel | shadow_busy;
+ always_comb begin
+ reg_busy_sel = '0;
+ unique case (1'b1)
+ default: begin
+ reg_busy_sel = '0;
+ end
+ endcase
+ end
+
+
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
+endmodule
diff --git a/EDA-3283/rtl/jtag_pkg.sv b/EDA-3283/rtl/jtag_pkg.sv
new file mode 100644
index 00000000..2a67ee07
--- /dev/null
+++ b/EDA-3283/rtl/jtag_pkg.sv
@@ -0,0 +1,24 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package jtag_pkg;
+
+ typedef struct packed {
+ logic tck;
+ logic tms;
+ logic trst_n;
+ logic tdi;
+ } jtag_req_t;
+
+ parameter jtag_req_t JTAG_REQ_DEFAULT = '0;
+
+ typedef struct packed {
+ logic tdo;
+ logic tdo_oe;
+ } jtag_rsp_t;
+
+ parameter jtag_rsp_t JTAG_RSP_DEFAULT = '0;
+
+endpackage : jtag_pkg
diff --git a/EDA-3283/rtl/lc_ctrl_pkg.sv b/EDA-3283/rtl/lc_ctrl_pkg.sv
new file mode 100644
index 00000000..b7c19189
--- /dev/null
+++ b/EDA-3283/rtl/lc_ctrl_pkg.sv
@@ -0,0 +1,345 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package lc_ctrl_pkg;
+
+ import prim_util_pkg::vbits;
+
+ // TODO: need to generate these randomly, based on ECC
+ // polynomial used inside the OTP macro.
+ // The A/B values are used for the encoded LC state.
+ parameter logic [15:0] A0 = 16'h0000;
+ parameter logic [15:0] A1 = 16'h0000;
+ parameter logic [15:0] A2 = 16'h0000;
+ parameter logic [15:0] A3 = 16'h0000;
+ parameter logic [15:0] A4 = 16'h0000;
+ parameter logic [15:0] A5 = 16'h0000;
+ parameter logic [15:0] A6 = 16'h0000;
+ parameter logic [15:0] A7 = 16'h0000;
+ parameter logic [15:0] A8 = 16'h0000;
+ parameter logic [15:0] A9 = 16'h0000;
+ parameter logic [15:0] A10 = 16'h0000;
+ parameter logic [15:0] A11 = 16'h0000;
+
+ parameter logic [15:0] B0 = 16'hFFFF;
+ parameter logic [15:0] B1 = 16'hFFFF;
+ parameter logic [15:0] B2 = 16'hFFFF;
+ parameter logic [15:0] B3 = 16'hFFFF;
+ parameter logic [15:0] B4 = 16'hFFFF;
+ parameter logic [15:0] B5 = 16'hFFFF;
+ parameter logic [15:0] B6 = 16'hFFFF;
+ parameter logic [15:0] B7 = 16'hFFFF;
+ parameter logic [15:0] B8 = 16'hFFFF;
+ parameter logic [15:0] B9 = 16'hFFFF;
+ parameter logic [15:0] B10 = 16'hFFFF;
+ parameter logic [15:0] B11 = 16'hFFFF;
+
+ // The C/D values are used for the encoded LC transition counter.
+ parameter logic [15:0] C0 = 16'h0000;
+ parameter logic [15:0] C1 = 16'h0000;
+ parameter logic [15:0] C2 = 16'h0000;
+ parameter logic [15:0] C3 = 16'h0000;
+ parameter logic [15:0] C4 = 16'h0000;
+ parameter logic [15:0] C5 = 16'h0000;
+ parameter logic [15:0] C6 = 16'h0000;
+ parameter logic [15:0] C7 = 16'h0000;
+ parameter logic [15:0] C8 = 16'h0000;
+ parameter logic [15:0] C9 = 16'h0000;
+ parameter logic [15:0] C10 = 16'h0000;
+ parameter logic [15:0] C11 = 16'h0000;
+ parameter logic [15:0] C12 = 16'h0000;
+ parameter logic [15:0] C13 = 16'h0000;
+ parameter logic [15:0] C14 = 16'h0000;
+ parameter logic [15:0] C15 = 16'h0000;
+
+ parameter logic [15:0] D0 = 16'hFFFF;
+ parameter logic [15:0] D1 = 16'hFFFF;
+ parameter logic [15:0] D2 = 16'hFFFF;
+ parameter logic [15:0] D3 = 16'hFFFF;
+ parameter logic [15:0] D4 = 16'hFFFF;
+ parameter logic [15:0] D5 = 16'hFFFF;
+ parameter logic [15:0] D6 = 16'hFFFF;
+ parameter logic [15:0] D7 = 16'hFFFF;
+ parameter logic [15:0] D8 = 16'hFFFF;
+ parameter logic [15:0] D9 = 16'hFFFF;
+ parameter logic [15:0] D10 = 16'hFFFF;
+ parameter logic [15:0] D11 = 16'hFFFF;
+ parameter logic [15:0] D12 = 16'hFFFF;
+ parameter logic [15:0] D13 = 16'hFFFF;
+ parameter logic [15:0] D14 = 16'hFFFF;
+ parameter logic [15:0] D15 = 16'hFFFF;
+
+ // The E/F values are used for the encoded ID state.
+ parameter logic [15:0] E0 = 16'h0000;
+ parameter logic [15:0] F0 = 16'hFFFF;
+
+ /////////////////////////////////
+ // General Typedefs and Params //
+ /////////////////////////////////
+
+ parameter int LcValueWidth = 16;
+ parameter int LcTokenWidth = 128;
+ parameter int NumLcStateValues = 12;
+ parameter int LcStateWidth = NumLcStateValues * LcValueWidth;
+ parameter int NumLcCountValues = 16;
+ parameter int LcCountWidth = NumLcCountValues * LcValueWidth;
+ parameter int NumLcStates = 13;
+ parameter int DecLcStateWidth = vbits(NumLcStates);
+ parameter int DecLcCountWidth = vbits(NumLcCountValues+1);
+ parameter int LcIdStateWidth = LcValueWidth;
+ parameter int DecLcIdStateWidth = 2;
+
+ typedef logic [LcTokenWidth-1:0] lc_token_t;
+
+ // TODO: make this secret and generate randomly, given a specific ECC polynomial.
+ typedef enum logic [LcStateWidth-1:0] {
+ // Halfword idx : 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ LcStRaw = '0,
+ LcStTestUnlocked0 = {A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, B0},
+ LcStTestLocked0 = {A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, B1, B0},
+ LcStTestUnlocked1 = {A11, A10, A9, A8, A7, A6, A5, A4, A3, B2, B1, B0},
+ LcStTestLocked1 = {A11, A10, A9, A8, A7, A6, A5, A4, B3, B2, B1, B0},
+ LcStTestUnlocked2 = {A11, A10, A9, A8, A7, A6, A5, B4, B3, B2, B1, B0},
+ LcStTestLocked2 = {A11, A10, A9, A8, A7, A6, B5, B4, B3, B2, B1, B0},
+ LcStTestUnlocked3 = {A11, A10, A9, A8, A7, B6, B5, B4, B3, B2, B1, B0},
+ LcStDev = {A11, A10, A9, A8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStProd = {A11, A10, A9, B8, A7, B6, B5, B4, B3, B2, B1, B0},
+ LcStProdEnd = {A11, A10, B9, A8, A7, B6, B5, B4, B3, B2, B1, B0},
+ LcStRma = {B11, B10, A9, B8, B7, B6, B5, B4, B3, B2, B1, B0},
+ LcStScrap = {B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0}
+ } lc_state_e;
+
+ // Decoded life cycle state, used to interface with CSRs and TAP.
+ typedef enum logic [DecLcStateWidth-1:0] {
+ DecLcStRaw = 4'h0,
+ DecLcStTestUnlocked0 = 4'h1,
+ DecLcStTestLocked0 = 4'h2,
+ DecLcStTestUnlocked1 = 4'h3,
+ DecLcStTestLocked1 = 4'h4,
+ DecLcStTestUnlocked2 = 4'h5,
+ DecLcStTestLocked2 = 4'h6,
+ DecLcStTestUnlocked3 = 4'h7,
+ DecLcStDev = 4'h8,
+ DecLcStProd = 4'h9,
+ DecLcStProdEnd = 4'hA,
+ DecLcStRma = 4'hB,
+ DecLcStScrap = 4'hC,
+ DecLcStPostTrans = 4'hD,
+ DecLcStEscalate = 4'hE,
+ DecLcStInvalid = 4'hF
+ } dec_lc_state_e;
+
+ typedef enum logic [LcIdStateWidth-1:0] {
+ LcIdBlank = E0,
+ LcIdPersonalized = F0
+ } lc_id_state_e;
+
+ typedef enum logic [DecLcIdStateWidth-1:0] {
+ DecLcIdBlank = 2'd0,
+ DecLcIdPersonalized = 2'd1,
+ DecLcIdInvalid = 2'd2
+ } dec_lc_id_state_e;
+
+ typedef enum logic [LcCountWidth-1:0] {
+ LcCntRaw = '0,
+ LcCnt1 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, D0},
+ LcCnt2 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, D1, D0},
+ LcCnt3 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, D2, D1, D0},
+ LcCnt4 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, D3, D2, D1, D0},
+ LcCnt5 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, D4, D3, D2, D1, D0},
+ LcCnt6 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, D5, D4, D3, D2, D1, D0},
+ LcCnt7 = {C15, C14, C13, C12, C11, C10, C9, C8, C7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt8 = {C15, C14, C13, C12, C11, C10, C9, C8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt9 = {C15, C14, C13, C12, C11, C10, C9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt10 = {C15, C14, C13, C12, C11, C10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt11 = {C15, C14, C13, C12, C11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt12 = {C15, C14, C13, C12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt13 = {C15, C14, C13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt14 = {C15, C14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt15 = {C15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0},
+ LcCnt16 = {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0}
+ } lc_cnt_e;
+
+ typedef logic [DecLcCountWidth-1:0] dec_lc_cnt_t;
+
+
+ ///////////////////////////////////////
+ // Netlist Constants (Hashed Tokens) //
+ ///////////////////////////////////////
+
+ parameter int NumTokens = 6;
+ parameter int TokenIdxWidth = vbits(NumTokens);
+ typedef enum logic [TokenIdxWidth-1:0] {
+ // This is the index for the hashed all-zero constant.
+ // All unconditional transitions use this token.
+ ZeroTokenIdx = 3'h0,
+ RawUnlockTokenIdx = 3'h1,
+ TestUnlockTokenIdx = 3'h2,
+ TestExitTokenIdx = 3'h3,
+ RmaTokenIdx = 3'h4,
+ // This is the index for an all-zero value (i.e., hashed value = '0).
+ // This is used as an additional blocker for some invalid state transition edges.
+ InvalidTokenIdx = 3'h5
+ } token_idx_e;
+
+ ////////////////////////////////
+ // Typedefs for LC Interfaces //
+ ////////////////////////////////
+
+ parameter int TxWidth = 4;
+ typedef enum logic [TxWidth-1:0] {
+ On = 4'b1010,
+ Off = 4'b0101
+ } lc_tx_e;
+
+ typedef lc_tx_e lc_tx_t;
+
+ parameter lc_tx_t LC_TX_DEFAULT = Off;
+
+ parameter int RmaSeedWidth = 32;
+ typedef logic [RmaSeedWidth-1:0] lc_flash_rma_seed_t;
+
+ parameter int LcKeymgrDivWidth = 64;
+ typedef logic [LcKeymgrDivWidth-1:0] lc_keymgr_div_t;
+
+ ////////////////////
+ // Main FSM State //
+ ////////////////////
+
+ // Encoding generated with:
+ // $ ./sparse-fsm-encode.py -d 5 -m 14 -n 16 \
+ // -s 2934212379 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: |||||| (6.59%)
+ // 6: |||||||||| (10.99%)
+ // 7: |||||||||||||||| (17.58%)
+ // 8: |||||||||||||||||||| (20.88%)
+ // 9: |||||||||||||||| (17.58%)
+ // 10: |||||||||||||| (15.38%)
+ // 11: |||||| (6.59%)
+ // 12: ||| (3.30%)
+ // 13: | (1.10%)
+ // 14: --
+ // 15: --
+ // 16: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 13
+ //
+ localparam int FsmStateWidth = 16;
+ typedef enum logic [FsmStateWidth-1:0] {
+ ResetSt = 16'b1100000001111011,
+ IdleSt = 16'b1111011010111100,
+ ClkMuxSt = 16'b0000011110101101,
+ CntIncrSt = 16'b1100111011001001,
+ CntProgSt = 16'b0011001111000111,
+ TransCheckSt = 16'b0000110001010100,
+ TokenHashSt = 16'b1110100010001111,
+ FlashRmaSt = 16'b0110111010110000,
+ TokenCheck0St = 16'b0010000011000000,
+ TokenCheck1St = 16'b1101010101101111,
+ TransProgSt = 16'b1000000110101011,
+ PostTransSt = 16'b0110110100101100,
+ EscalateSt = 16'b1010100001010001,
+ InvalidSt = 16'b1011110110011011
+ } fsm_state_e;
+
+ ///////////////////////////////////////////
+ // Manufacturing State Transition Matrix //
+ ///////////////////////////////////////////
+
+ // The token index matrix below encodes 1) which transition edges are valid and 2) which token
+ // to use for a given transition edge. Note that unconditional but otherwise valid transitions
+ // are assigned the ZeroTokenIdx, whereas invalid transitions are assigned an InvalidTokenIdx.
+ parameter token_idx_e [NumLcStates-1:0][NumLcStates-1:0] TransTokenIdxMatrix = {
+ // SCRAP
+ {13{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END, RMA, SCRAP
+ // RMA
+ ZeroTokenIdx, // -> SCRAP
+ {12{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END, RMA
+ // PROD_END
+ ZeroTokenIdx, // -> SCRAP
+ {12{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END, RMA
+ // PROD
+ ZeroTokenIdx, // -> SCRAP
+ RmaTokenIdx, // -> RMA
+ {11{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END
+ // DEV
+ ZeroTokenIdx, // -> SCRAP
+ RmaTokenIdx, // -> RMA
+ {11{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, DEV, PROD, PROD_END
+ // TEST_UNLOCKED3
+ {2{ZeroTokenIdx}}, // -> SCRAP, RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ {8{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-3, RAW
+ // TEST_LOCKED2
+ ZeroTokenIdx, // -> SCRAP
+ InvalidTokenIdx, // -> RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED3
+ {7{InvalidTokenIdx}}, // -> TEST_LOCKED0-2, TEST_UNLOCKED0-2, RAW
+ // TEST_UNLOCKED2
+ {2{ZeroTokenIdx}}, // -> SCRAP, RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ InvalidTokenIdx, // -> TEST_UNLOCKED3
+ ZeroTokenIdx, // -> TEST_LOCKED2
+ {6{InvalidTokenIdx}}, // -> TEST_LOCKED0-1, TEST_UNLOCKED0-2, RAW
+ // TEST_LOCKED1
+ ZeroTokenIdx, // -> SCRAP
+ InvalidTokenIdx, // -> RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED3
+ InvalidTokenIdx , // -> TEST_LOCKED2
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED2
+ {5{InvalidTokenIdx}}, // -> TEST_LOCKED0-1, TEST_UNLOCKED0-1, RAW
+ // TEST_UNLOCKED1
+ {2{ZeroTokenIdx}}, // -> SCRAP, RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ InvalidTokenIdx, // -> TEST_UNLOCKED3
+ ZeroTokenIdx, // -> TEST_LOCKED2
+ InvalidTokenIdx, // -> TEST_UNLOCKED2
+ ZeroTokenIdx, // -> TEST_LOCKED1
+ {4{InvalidTokenIdx}}, // -> TEST_LOCKED0, TEST_UNLOCKED0-1, RAW
+ // TEST_LOCKED0
+ ZeroTokenIdx, // -> SCRAP
+ InvalidTokenIdx, // -> RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED3
+ InvalidTokenIdx, // -> TEST_LOCKED2
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED2
+ InvalidTokenIdx, // -> TEST_LOCKED1
+ TestUnlockTokenIdx, // -> TEST_UNLOCKED1
+ {3{InvalidTokenIdx}}, // -> TEST_LOCKED0, TEST_UNLOCKED0, RAW
+ // TEST_UNLOCKED0
+ {2{ZeroTokenIdx}}, // -> SCRAP, RMA
+ {3{TestExitTokenIdx}}, // -> PROD, PROD_END, DEV
+ InvalidTokenIdx, // -> TEST_UNLOCKED3
+ ZeroTokenIdx, // -> TEST_LOCKED2
+ InvalidTokenIdx, // -> TEST_UNLOCKED2
+ ZeroTokenIdx, // -> TEST_LOCKED1
+ InvalidTokenIdx, // -> TEST_UNLOCKED1
+ ZeroTokenIdx, // -> TEST_LOCKED0
+ {2{InvalidTokenIdx}}, // -> TEST_UNLOCKED0, RAW
+ // RAW
+ ZeroTokenIdx, // -> SCRAP
+ {4{InvalidTokenIdx}}, // -> RMA, PROD, PROD_END, DEV
+ RawUnlockTokenIdx, // -> TEST_UNLOCKED3
+ InvalidTokenIdx, // -> TEST_LOCKED2
+ RawUnlockTokenIdx, // -> TEST_UNLOCKED2
+ InvalidTokenIdx, // -> TEST_LOCKED1
+ RawUnlockTokenIdx, // -> TEST_UNLOCKED1
+ InvalidTokenIdx, // -> TEST_LOCKED0
+ RawUnlockTokenIdx, // -> TEST_UNLOCKED0
+ InvalidTokenIdx // -> RAW
+ };
+
+endpackage : lc_ctrl_pkg
diff --git a/EDA-3283/rtl/otp_ctrl_pkg.sv b/EDA-3283/rtl/otp_ctrl_pkg.sv
new file mode 100644
index 00000000..ba03e2ec
--- /dev/null
+++ b/EDA-3283/rtl/otp_ctrl_pkg.sv
@@ -0,0 +1,337 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package otp_ctrl_pkg;
+
+ import prim_util_pkg::vbits;
+ import otp_ctrl_reg_pkg::*;
+
+ ////////////////////////
+ // General Parameters //
+ ////////////////////////
+
+ // Width of entropy input
+ parameter int EdnDataWidth = 64;
+
+ parameter int NumPartWidth = vbits(NumPart);
+
+ parameter int SwWindowAddrWidth = vbits(NumSwCfgWindowWords);
+
+ // Redundantly encoded and complementary values are used to for signalling to the partition
+ // controller FSMs and the DAI whether a partition is locked or not. Any other value than
+ // "Unlocked" is interpreted as "Locked" in those FSMs.
+ typedef enum logic [7:0] {
+ Unlocked = 8'h5A,
+ Locked = 8'hA5
+ } access_e;
+
+ // Partition access type
+ typedef struct packed {
+ access_e read_lock;
+ access_e write_lock;
+ } part_access_t;
+
+ parameter int DaiCmdWidth = 3;
+ typedef enum logic [DaiCmdWidth-1:0] {
+ DaiRead = 3'b001,
+ DaiWrite = 3'b010,
+ DaiDigest = 3'b100
+ } dai_cmd_e;
+
+ //////////////////////////////////////
+ // Typedefs for OTP Macro Interface //
+ //////////////////////////////////////
+
+ // OTP-macro specific
+ parameter int OtpWidth = 16;
+ parameter int OtpAddrWidth = OtpByteAddrWidth - $clog2(OtpWidth/8);
+ parameter int OtpDepth = 2**OtpAddrWidth;
+ parameter int OtpSizeWidth = 2; // Allows to transfer up to 4 native OTP words at once.
+ parameter int OtpErrWidth = 3;
+ parameter int OtpPwrSeqWidth = 2;
+ parameter int OtpIfWidth = 2**OtpSizeWidth*OtpWidth;
+ // Number of Byte address bits to cut off in order to get the native OTP word address.
+ parameter int OtpAddrShift = OtpByteAddrWidth - OtpAddrWidth;
+
+ typedef enum logic [OtpErrWidth-1:0] {
+ NoError = 3'h0,
+ MacroError = 3'h1,
+ MacroEccCorrError = 3'h2,
+ MacroEccUncorrError = 3'h3,
+ MacroWriteBlankError = 3'h4,
+ AccessError = 3'h5,
+ CheckFailError = 3'h6,
+ FsmStateError = 3'h7
+ } otp_err_e;
+
+ /////////////////////////////////
+ // Typedefs for OTP Scrambling //
+ /////////////////////////////////
+
+ parameter int ScrmblKeyWidth = 128;
+ parameter int ScrmblBlockWidth = 64;
+
+ parameter int NumPresentRounds = 31;
+ parameter int ScrmblBlockHalfWords = ScrmblBlockWidth / OtpWidth;
+
+ typedef enum logic [2:0] {
+ Decrypt,
+ Encrypt,
+ LoadShadow,
+ Digest,
+ DigestInit,
+ DigestFinalize
+ } otp_scrmbl_cmd_e;
+
+ parameter int NumScrmblKeys = 3;
+ parameter int NumDigestSets = 5;
+ parameter int ConstSelWidth = (NumScrmblKeys > NumDigestSets) ?
+ vbits(NumScrmblKeys) :
+ vbits(NumDigestSets);
+
+ typedef enum logic [ConstSelWidth-1:0] {
+ Secret0Key,
+ Secret1Key,
+ Secret2Key
+ } key_sel_e;
+
+ typedef enum logic [ConstSelWidth-1:0] {
+ CnstyDigest,
+ LcRawDigest,
+ FlashDataKey,
+ FlashAddrKey,
+ SramDataKey
+ } digest_sel_e;
+
+ typedef enum logic [ConstSelWidth-1:0] {
+ StandardMode,
+ ChainedMode
+ } digest_mode_e;
+
+ /////////////////////////////////////
+ // Typedefs for Partition Metadata //
+ /////////////////////////////////////
+
+ typedef enum logic [1:0] {
+ Unbuffered,
+ Buffered,
+ LifeCycle
+ } part_variant_e;
+
+ typedef struct packed {
+ part_variant_e variant;
+ // Offset and size within the OTP array, in Bytes.
+ logic [OtpByteAddrWidth-1:0] offset;
+ logic [OtpByteAddrWidth-1:0] size;
+ // Key index to use for scrambling.
+ key_sel_e key_sel;
+ // Attributes
+ logic secret; // Whether the partition is secret (and hence scrambled)
+ logic hw_digest; // Whether the partition has a hardware digest
+ logic write_lock; // Whether the partition is write lockable (via digest)
+ logic read_lock; // Whether the partition is read lockable (via digest)
+ } part_info_t;
+
+ ///////////////////////////////
+ // Typedefs for LC Interface //
+ ///////////////////////////////
+
+ typedef struct packed {
+ logic valid;
+ logic state;
+ // lc_ctrl_pkg::lc_cnt_e
+ logic count;
+ // These are all hash post-images
+ lc_ctrl_pkg::lc_token_t all_zero_token;
+ lc_ctrl_pkg::lc_token_t raw_unlock_token;
+ lc_ctrl_pkg::lc_token_t test_unlock_token;
+ lc_ctrl_pkg::lc_token_t test_exit_token;
+ lc_ctrl_pkg::lc_token_t rma_token;
+ // lc_ctrl_pkg::lc_id_state_e
+ logic id_state;
+ } otp_lc_data_t;
+
+ // Default for dangling connection
+ parameter otp_lc_data_t OTP_LC_DATA_DEFAULT = '{
+ valid: 1'b1,
+ state : 1'b0,
+ count: 1'b0,
+ all_zero_token:1'b0,
+ raw_unlock_token: 1'b0,
+ test_unlock_token: 1'b0,
+ test_exit_token: 1'b0,
+ rma_token: 1'b0,
+ id_state: 1'b0
+ };
+
+
+ typedef struct packed {
+ logic req;
+ // lc_ctrl_pkg::lc_state_e state;
+ // lc_ctrl_pkg::lc_cnt_e count;
+ } lc_otp_program_req_t;
+
+ typedef struct packed {
+ logic err;
+ logic ack;
+ } lc_otp_program_rsp_t;
+
+ // RAW unlock token hashing request.
+ typedef struct packed {
+ logic req;
+ lc_ctrl_pkg::lc_token_t token_input;
+ } lc_otp_token_req_t;
+
+ typedef struct packed {
+ logic ack;
+ lc_ctrl_pkg::lc_token_t hashed_token;
+ } lc_otp_token_rsp_t;
+
+ ////////////////////////////////
+ // Typedefs for Key Broadcast //
+ ////////////////////////////////
+
+ parameter int FlashKeySeedWidth = 256;
+ parameter int SramKeySeedWidth = 128;
+ parameter int KeyMgrKeyWidth = 256;
+ parameter int FlashKeyWidth = 128;
+ parameter int SramKeyWidth = 128;
+ parameter int SramNonceWidth = 64;
+ parameter int OtbnKeyWidth = 128;
+ parameter int OtbnNonceWidth = 256;
+
+ typedef logic [SramKeyWidth-1:0] sram_key_t;
+ typedef logic [SramNonceWidth-1:0] sram_nonce_t;
+ typedef logic [OtbnKeyWidth-1:0] otbn_key_t;
+ typedef logic [OtbnNonceWidth-1:0] otbn_nonce_t;
+
+ typedef struct packed {
+ logic valid;
+ logic [KeyMgrKeyWidth-1:0] key_share0;
+ logic [KeyMgrKeyWidth-1:0] key_share1;
+ } otp_keymgr_key_t;
+
+ parameter otp_keymgr_key_t OTP_KEYMGR_KEY_DEFAULT = '{
+ valid: 1'b1,
+ key_share0: 256'hefb7ea7ee90093cf4affd9aaa2d6c0ec446cfdf5f2d5a0bfd7e2d93edc63a102,
+ key_share1: 256'h56d24a00181de99e0f690b447a8dde2a1ffb8bc306707107aa6e2410f15cfc37
+ };
+
+ typedef struct packed {
+ logic data_req; // Requests static key for data scrambling.
+ logic addr_req; // Requests static key for address scrambling.
+ } flash_otp_key_req_t;
+
+ typedef struct packed {
+ logic req; // Requests ephemeral scrambling key and nonce.
+ } sram_otp_key_req_t;
+
+ typedef struct packed {
+ logic req; // Requests ephemeral scrambling key and nonce.
+ } otbn_otp_key_req_t;
+
+ typedef struct packed {
+ logic data_ack; // Ack for data key.
+ logic addr_ack; // Ack for address key.
+ logic [FlashKeyWidth-1:0] key; // 128bit static scrambling key.
+ logic seed_valid; // Set to 1 if the key seed has been provisioned and is valid.
+ } flash_otp_key_rsp_t;
+
+ // Default for dangling connection
+ parameter flash_otp_key_rsp_t FLASH_OTP_KEY_RSP_DEFAULT = '{
+ data_ack: 1'b1,
+ addr_ack: 1'b1,
+ key: '0,
+ seed_valid: 1'b1
+ };
+
+ typedef struct packed {
+ logic ack; // Ack for key.
+ sram_key_t key; // 128bit ephemeral scrambling key.
+ sram_nonce_t nonce; // 64bit nonce.
+ logic seed_valid; // Set to 1 if the key seed has been provisioned and is valid.
+ } sram_otp_key_rsp_t;
+
+ typedef struct packed {
+ logic ack; // Ack for key.
+ otbn_key_t key; // 128bit ephemeral scrambling key.
+ otbn_nonce_t nonce; // 256bit nonce.
+ logic seed_valid; // Set to 1 if the key seed has been provisioned and is valid.
+ } otbn_otp_key_rsp_t;
+
+ ////////////////////////////////
+ // Power/Reset Ctrl Interface //
+ ////////////////////////////////
+
+ typedef struct packed {
+ logic init;
+ } pwr_otp_init_req_t;
+
+ typedef struct packed {
+ logic done;
+ } pwr_otp_init_rsp_t;
+
+ typedef struct packed {
+ logic idle;
+ } otp_pwr_state_t;
+
+
+ ///////////////////
+ // AST Interface //
+ ///////////////////
+
+ typedef struct packed {
+ logic [OtpPwrSeqWidth-1:0] pwr_seq;
+ } otp_ast_req_t;
+
+ typedef struct packed {
+ logic [OtpPwrSeqWidth-1:0] pwr_seq_h;
+ } otp_ast_rsp_t;
+
+ ///////////////////////////////////////////
+ // Defaults for random netlist constants //
+ ///////////////////////////////////////////
+
+ // These LFSR parameters have been generated with
+ // $ hw/ip/prim/util/gen-lfsr-seed.py --width 40 --seed 4247488366
+ localparam int LfsrWidth = 40;
+ typedef logic [LfsrWidth-1:0] lfsr_seed_t;
+ typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
+ localparam lfsr_seed_t RndCnstLfsrSeedDefault = 40'h453d28ea98;
+ localparam lfsr_perm_t RndCnstLfsrPermDefault =
+ 240'h4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5;
+
+
+ typedef logic [NumScrmblKeys-1:0][ScrmblKeyWidth-1:0] key_array_t;
+ parameter key_array_t RndCnstKeyDefault = {
+ 128'h047288e1a65c839dae610bbbdf8c4525,
+ 128'h38fe59a71a91a65636573a6513784e3b,
+ 128'h4f48dcc45ace0770e9135bda73e56344
+ };
+
+ // Note: digest set 0 is used for computing the partition digests. Constants at
+ // higher indices are used to compute the scrambling keys.
+ typedef logic [NumDigestSets-1:0][ScrmblKeyWidth-1:0] digest_const_array_t;
+ parameter digest_const_array_t RndCnstDigestConstDefault = {
+ 128'h9d40106e2dc2346ec96d61f0cc5295c7,
+ 128'hafed2aa5c3284c01d71103edab1d8953,
+ 128'h8a14fe0c08f8a3a190dd32c05f208474,
+ 128'h9e6fac4ba15a3bce29d05a3e9e2d0846,
+ 128'h3a0c6051392e00ef24073627319555b8
+ };
+
+ typedef logic [NumDigestSets-1:0][ScrmblBlockWidth-1:0] digest_iv_array_t;
+ parameter digest_iv_array_t RndCnstDigestIVDefault = {
+ 64'ha5af72c1b813aec4,
+ 64'h5d7aacd1db316407,
+ 64'hd0ec83b7fe6ae2ae,
+ 64'hc2993a0ea64e312d,
+ 64'h899aac2ab7d91479
+ };
+
+ parameter lc_ctrl_pkg::lc_token_t RndCnstRawUnlockTokenDefault =
+ 128'hcbbd013ff15eba2f3065461eeb88463e;
+
+endpackage : otp_ctrl_pkg
diff --git a/EDA-3283/rtl/otp_ctrl_reg_pkg.sv b/EDA-3283/rtl/otp_ctrl_reg_pkg.sv
new file mode 100644
index 00000000..65024548
--- /dev/null
+++ b/EDA-3283/rtl/otp_ctrl_reg_pkg.sv
@@ -0,0 +1,571 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package otp_ctrl_reg_pkg;
+
+ // Param list
+ parameter int NumSramKeyReqSlots = 2;
+ parameter int OtpByteAddrWidth = 11;
+ parameter int NumErrorEntries = 10;
+ parameter int NumDaiWords = 2;
+ parameter int NumDigestWords = 2;
+ parameter int NumSwCfgWindowWords = 512;
+ parameter int NumDebugWindowWords = 16;
+ parameter int NumPart = 8;
+ parameter int VendorTestOffset = 0;
+ parameter int VendorTestSize = 64;
+ parameter int ScratchOffset = 0;
+ parameter int ScratchSize = 56;
+ parameter int VendorTestDigestOffset = 56;
+ parameter int VendorTestDigestSize = 8;
+ parameter int CreatorSwCfgOffset = 64;
+ parameter int CreatorSwCfgSize = 800;
+ parameter int CreatorSwCfgAstCfgOffset = 64;
+ parameter int CreatorSwCfgAstCfgSize = 128;
+ parameter int CreatorSwCfgAstInitEnOffset = 192;
+ parameter int CreatorSwCfgAstInitEnSize = 4;
+ parameter int CreatorSwCfgRomExtSkuOffset = 196;
+ parameter int CreatorSwCfgRomExtSkuSize = 4;
+ parameter int CreatorSwCfgUseSwRsaVerifyOffset = 200;
+ parameter int CreatorSwCfgUseSwRsaVerifySize = 4;
+ parameter int CreatorSwCfgKeyIsValidOffset = 204;
+ parameter int CreatorSwCfgKeyIsValidSize = 8;
+ parameter int CreatorSwCfgFlashDataDefaultCfgOffset = 212;
+ parameter int CreatorSwCfgFlashDataDefaultCfgSize = 4;
+ parameter int CreatorSwCfgFlashInfoBootDataCfgOffset = 216;
+ parameter int CreatorSwCfgFlashInfoBootDataCfgSize = 4;
+ parameter int CreatorSwCfgRngEnOffset = 220;
+ parameter int CreatorSwCfgRngEnSize = 4;
+ parameter int CreatorSwCfgDigestOffset = 856;
+ parameter int CreatorSwCfgDigestSize = 8;
+ parameter int OwnerSwCfgOffset = 864;
+ parameter int OwnerSwCfgSize = 800;
+ parameter int RomErrorReportingOffset = 864;
+ parameter int RomErrorReportingSize = 4;
+ parameter int RomBootstrapEnOffset = 868;
+ parameter int RomBootstrapEnSize = 4;
+ parameter int RomFaultResponseOffset = 872;
+ parameter int RomFaultResponseSize = 4;
+ parameter int RomAlertClassEnOffset = 876;
+ parameter int RomAlertClassEnSize = 4;
+ parameter int RomAlertEscalationOffset = 880;
+ parameter int RomAlertEscalationSize = 4;
+ parameter int RomAlertClassificationOffset = 884;
+ parameter int RomAlertClassificationSize = 320;
+ parameter int RomLocalAlertClassificationOffset = 1204;
+ parameter int RomLocalAlertClassificationSize = 64;
+ parameter int RomAlertAccumThreshOffset = 1268;
+ parameter int RomAlertAccumThreshSize = 16;
+ parameter int RomAlertTimeoutCyclesOffset = 1284;
+ parameter int RomAlertTimeoutCyclesSize = 16;
+ parameter int RomAlertPhaseCyclesOffset = 1300;
+ parameter int RomAlertPhaseCyclesSize = 64;
+ parameter int OwnerSwCfgDigestOffset = 1656;
+ parameter int OwnerSwCfgDigestSize = 8;
+ parameter int HwCfgOffset = 1664;
+ parameter int HwCfgSize = 80;
+ parameter int DeviceIdOffset = 1664;
+ parameter int DeviceIdSize = 32;
+ parameter int ManufStateOffset = 1696;
+ parameter int ManufStateSize = 32;
+ parameter int EnSramIfetchOffset = 1728;
+ parameter int EnSramIfetchSize = 1;
+ parameter int EnCsrngSwAppReadOffset = 1729;
+ parameter int EnCsrngSwAppReadSize = 1;
+ parameter int EnEntropySrcFwReadOffset = 1730;
+ parameter int EnEntropySrcFwReadSize = 1;
+ parameter int EnEntropySrcFwOverOffset = 1731;
+ parameter int EnEntropySrcFwOverSize = 1;
+ parameter int HwCfgDigestOffset = 1736;
+ parameter int HwCfgDigestSize = 8;
+ parameter int Secret0Offset = 1744;
+ parameter int Secret0Size = 40;
+ parameter int TestUnlockTokenOffset = 1744;
+ parameter int TestUnlockTokenSize = 16;
+ parameter int TestExitTokenOffset = 1760;
+ parameter int TestExitTokenSize = 16;
+ parameter int Secret0DigestOffset = 1776;
+ parameter int Secret0DigestSize = 8;
+ parameter int Secret1Offset = 1784;
+ parameter int Secret1Size = 88;
+ parameter int FlashAddrKeySeedOffset = 1784;
+ parameter int FlashAddrKeySeedSize = 32;
+ parameter int FlashDataKeySeedOffset = 1816;
+ parameter int FlashDataKeySeedSize = 32;
+ parameter int SramDataKeySeedOffset = 1848;
+ parameter int SramDataKeySeedSize = 16;
+ parameter int Secret1DigestOffset = 1864;
+ parameter int Secret1DigestSize = 8;
+ parameter int Secret2Offset = 1872;
+ parameter int Secret2Size = 88;
+ parameter int RmaTokenOffset = 1872;
+ parameter int RmaTokenSize = 16;
+ parameter int CreatorRootKeyShare0Offset = 1888;
+ parameter int CreatorRootKeyShare0Size = 32;
+ parameter int CreatorRootKeyShare1Offset = 1920;
+ parameter int CreatorRootKeyShare1Size = 32;
+ parameter int Secret2DigestOffset = 1952;
+ parameter int Secret2DigestSize = 8;
+ parameter int LifeCycleOffset = 1960;
+ parameter int LifeCycleSize = 88;
+ parameter int LcTransitionCntOffset = 1960;
+ parameter int LcTransitionCntSize = 48;
+ parameter int LcStateOffset = 2008;
+ parameter int LcStateSize = 40;
+ parameter int NumAlerts = 3;
+
+ // Address widths within the block
+ parameter int CoreAw = 13;
+ parameter int PrimAw = 1;
+
+ ///////////////////////////////////////////////
+ // Typedefs for registers for core interface //
+ ///////////////////////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } otp_operation_done;
+ struct packed {
+ logic q;
+ } otp_error;
+ } otp_ctrl_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } otp_operation_done;
+ struct packed {
+ logic q;
+ } otp_error;
+ } otp_ctrl_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } otp_operation_done;
+ struct packed {
+ logic q;
+ logic qe;
+ } otp_error;
+ } otp_ctrl_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_macro_error;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_check_error;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_bus_integ_error;
+ } otp_ctrl_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } rd;
+ struct packed {
+ logic q;
+ logic qe;
+ } wr;
+ struct packed {
+ logic q;
+ logic qe;
+ } digest;
+ } otp_ctrl_reg2hw_direct_access_cmd_reg_t;
+
+ typedef struct packed {
+ logic [10:0] q;
+ } otp_ctrl_reg2hw_direct_access_address_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } otp_ctrl_reg2hw_direct_access_wdata_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } integrity;
+ struct packed {
+ logic q;
+ logic qe;
+ } consistency;
+ } otp_ctrl_reg2hw_check_trigger_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } otp_ctrl_reg2hw_check_timeout_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } otp_ctrl_reg2hw_integrity_check_period_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } otp_ctrl_reg2hw_consistency_check_period_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } otp_ctrl_reg2hw_vendor_test_read_lock_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } otp_ctrl_reg2hw_creator_sw_cfg_read_lock_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } otp_ctrl_reg2hw_owner_sw_cfg_read_lock_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } otp_operation_done;
+ struct packed {
+ logic d;
+ logic de;
+ } otp_error;
+ } otp_ctrl_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ } vendor_test_error;
+ struct packed {
+ logic d;
+ } creator_sw_cfg_error;
+ struct packed {
+ logic d;
+ } owner_sw_cfg_error;
+ struct packed {
+ logic d;
+ } hw_cfg_error;
+ struct packed {
+ logic d;
+ } secret0_error;
+ struct packed {
+ logic d;
+ } secret1_error;
+ struct packed {
+ logic d;
+ } secret2_error;
+ struct packed {
+ logic d;
+ } life_cycle_error;
+ struct packed {
+ logic d;
+ } dai_error;
+ struct packed {
+ logic d;
+ } lci_error;
+ struct packed {
+ logic d;
+ } timeout_error;
+ struct packed {
+ logic d;
+ } lfsr_fsm_error;
+ struct packed {
+ logic d;
+ } scrambling_fsm_error;
+ struct packed {
+ logic d;
+ } key_deriv_fsm_error;
+ struct packed {
+ logic d;
+ } bus_integ_error;
+ struct packed {
+ logic d;
+ } dai_idle;
+ struct packed {
+ logic d;
+ } check_pending;
+ } otp_ctrl_hw2reg_status_reg_t;
+
+ typedef struct packed {
+ logic [2:0] d;
+ } otp_ctrl_hw2reg_err_code_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ } otp_ctrl_hw2reg_direct_access_regwen_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_direct_access_rdata_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_vendor_test_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_creator_sw_cfg_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_owner_sw_cfg_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_hw_cfg_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_secret0_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_secret1_digest_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } otp_ctrl_hw2reg_secret2_digest_mreg_t;
+
+ // Register -> HW type for core interface
+ typedef struct packed {
+ otp_ctrl_reg2hw_intr_state_reg_t intr_state; // [197:196]
+ otp_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [195:194]
+ otp_ctrl_reg2hw_intr_test_reg_t intr_test; // [193:190]
+ otp_ctrl_reg2hw_alert_test_reg_t alert_test; // [189:184]
+ otp_ctrl_reg2hw_direct_access_cmd_reg_t direct_access_cmd; // [183:178]
+ otp_ctrl_reg2hw_direct_access_address_reg_t direct_access_address; // [177:167]
+ otp_ctrl_reg2hw_direct_access_wdata_mreg_t [1:0] direct_access_wdata; // [166:103]
+ otp_ctrl_reg2hw_check_trigger_reg_t check_trigger; // [102:99]
+ otp_ctrl_reg2hw_check_timeout_reg_t check_timeout; // [98:67]
+ otp_ctrl_reg2hw_integrity_check_period_reg_t integrity_check_period; // [66:35]
+ otp_ctrl_reg2hw_consistency_check_period_reg_t consistency_check_period; // [34:3]
+ otp_ctrl_reg2hw_vendor_test_read_lock_reg_t vendor_test_read_lock; // [2:2]
+ otp_ctrl_reg2hw_creator_sw_cfg_read_lock_reg_t creator_sw_cfg_read_lock; // [1:1]
+ otp_ctrl_reg2hw_owner_sw_cfg_read_lock_reg_t owner_sw_cfg_read_lock; // [0:0]
+ } otp_ctrl_core_reg2hw_t;
+
+ // HW -> register type for core interface
+ typedef struct packed {
+ otp_ctrl_hw2reg_intr_state_reg_t intr_state; // [563:560]
+ otp_ctrl_hw2reg_status_reg_t status; // [559:543]
+ otp_ctrl_hw2reg_err_code_mreg_t [9:0] err_code; // [542:513]
+ otp_ctrl_hw2reg_direct_access_regwen_reg_t direct_access_regwen; // [512:512]
+ otp_ctrl_hw2reg_direct_access_rdata_mreg_t [1:0] direct_access_rdata; // [511:448]
+ otp_ctrl_hw2reg_vendor_test_digest_mreg_t [1:0] vendor_test_digest; // [447:384]
+ otp_ctrl_hw2reg_creator_sw_cfg_digest_mreg_t [1:0] creator_sw_cfg_digest; // [383:320]
+ otp_ctrl_hw2reg_owner_sw_cfg_digest_mreg_t [1:0] owner_sw_cfg_digest; // [319:256]
+ otp_ctrl_hw2reg_hw_cfg_digest_mreg_t [1:0] hw_cfg_digest; // [255:192]
+ otp_ctrl_hw2reg_secret0_digest_mreg_t [1:0] secret0_digest; // [191:128]
+ otp_ctrl_hw2reg_secret1_digest_mreg_t [1:0] secret1_digest; // [127:64]
+ otp_ctrl_hw2reg_secret2_digest_mreg_t [1:0] secret2_digest; // [63:0]
+ } otp_ctrl_core_hw2reg_t;
+
+ // Register offsets for core interface
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTR_STATE_OFFSET = 13'h 0;
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTR_ENABLE_OFFSET = 13'h 4;
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTR_TEST_OFFSET = 13'h 8;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ALERT_TEST_OFFSET = 13'h c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_STATUS_OFFSET = 13'h 10;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_OFFSET = 13'h 14;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET = 13'h 18;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET = 13'h 1c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET = 13'h 20;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET = 13'h 24;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET = 13'h 28;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET = 13'h 2c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET = 13'h 30;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET = 13'h 34;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_OFFSET = 13'h 38;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_REGWEN_OFFSET = 13'h 3c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TIMEOUT_OFFSET = 13'h 40;
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET = 13'h 44;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET = 13'h 48;
+ parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET = 13'h 4c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET = 13'h 50;
+ parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET = 13'h 54;
+ parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET = 13'h 58;
+ parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET = 13'h 5c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET = 13'h 60;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET = 13'h 64;
+ parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET = 13'h 68;
+ parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET = 13'h 6c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG_DIGEST_0_OFFSET = 13'h 70;
+ parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG_DIGEST_1_OFFSET = 13'h 74;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_0_OFFSET = 13'h 78;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_1_OFFSET = 13'h 7c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_0_OFFSET = 13'h 80;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_1_OFFSET = 13'h 84;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_0_OFFSET = 13'h 88;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_1_OFFSET = 13'h 8c;
+
+ // Reset values for hwext registers and their fields for core interface
+ parameter logic [1:0] OTP_CTRL_INTR_TEST_RESVAL = 2'h 0;
+ parameter logic [0:0] OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL = 1'h 0;
+ parameter logic [2:0] OTP_CTRL_ALERT_TEST_RESVAL = 3'h 0;
+ parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL = 1'h 0;
+ parameter logic [16:0] OTP_CTRL_STATUS_RESVAL = 17'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_DAI_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_LCI_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_DAI_IDLE_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_STATUS_CHECK_PENDING_RESVAL = 1'h 0;
+ parameter logic [29:0] OTP_CTRL_ERR_CODE_RESVAL = 30'h 0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL = 3'h 0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL = 3'h 0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL = 3'h 0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL = 3'h 0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL = 3'h 0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL = 3'h 0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL = 3'h 0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL = 3'h 0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL = 3'h 0;
+ parameter logic [2:0] OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL = 3'h 0;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL = 1'h 1;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL = 1'h 1;
+ parameter logic [2:0] OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL = 3'h 0;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL = 1'h 0;
+ parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL = 32'h 0;
+ parameter logic [1:0] OTP_CTRL_CHECK_TRIGGER_RESVAL = 2'h 0;
+ parameter logic [0:0] OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL = 1'h 0;
+ parameter logic [0:0] OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL = 1'h 0;
+ parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_HW_CFG_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_HW_CFG_DIGEST_1_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_1_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_1_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_1_RESVAL = 32'h 0;
+ parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL = 32'h 0;
+
+ // Window parameters for core interface
+ parameter logic [CoreAw-1:0] OTP_CTRL_SW_CFG_WINDOW_OFFSET = 13'h 1000;
+ parameter int unsigned OTP_CTRL_SW_CFG_WINDOW_SIZE = 'h 800;
+
+ // Register index for core interface
+ typedef enum int {
+ OTP_CTRL_INTR_STATE,
+ OTP_CTRL_INTR_ENABLE,
+ OTP_CTRL_INTR_TEST,
+ OTP_CTRL_ALERT_TEST,
+ OTP_CTRL_STATUS,
+ OTP_CTRL_ERR_CODE,
+ OTP_CTRL_DIRECT_ACCESS_REGWEN,
+ OTP_CTRL_DIRECT_ACCESS_CMD,
+ OTP_CTRL_DIRECT_ACCESS_ADDRESS,
+ OTP_CTRL_DIRECT_ACCESS_WDATA_0,
+ OTP_CTRL_DIRECT_ACCESS_WDATA_1,
+ OTP_CTRL_DIRECT_ACCESS_RDATA_0,
+ OTP_CTRL_DIRECT_ACCESS_RDATA_1,
+ OTP_CTRL_CHECK_TRIGGER_REGWEN,
+ OTP_CTRL_CHECK_TRIGGER,
+ OTP_CTRL_CHECK_REGWEN,
+ OTP_CTRL_CHECK_TIMEOUT,
+ OTP_CTRL_INTEGRITY_CHECK_PERIOD,
+ OTP_CTRL_CONSISTENCY_CHECK_PERIOD,
+ OTP_CTRL_VENDOR_TEST_READ_LOCK,
+ OTP_CTRL_CREATOR_SW_CFG_READ_LOCK,
+ OTP_CTRL_OWNER_SW_CFG_READ_LOCK,
+ OTP_CTRL_VENDOR_TEST_DIGEST_0,
+ OTP_CTRL_VENDOR_TEST_DIGEST_1,
+ OTP_CTRL_CREATOR_SW_CFG_DIGEST_0,
+ OTP_CTRL_CREATOR_SW_CFG_DIGEST_1,
+ OTP_CTRL_OWNER_SW_CFG_DIGEST_0,
+ OTP_CTRL_OWNER_SW_CFG_DIGEST_1,
+ OTP_CTRL_HW_CFG_DIGEST_0,
+ OTP_CTRL_HW_CFG_DIGEST_1,
+ OTP_CTRL_SECRET0_DIGEST_0,
+ OTP_CTRL_SECRET0_DIGEST_1,
+ OTP_CTRL_SECRET1_DIGEST_0,
+ OTP_CTRL_SECRET1_DIGEST_1,
+ OTP_CTRL_SECRET2_DIGEST_0,
+ OTP_CTRL_SECRET2_DIGEST_1
+ } otp_ctrl_core_id_e;
+
+ // Register width information to check illegal writes for core interface
+ parameter logic [3:0] OTP_CTRL_CORE_PERMIT [36] = '{
+ 4'b 0001, // index[ 0] OTP_CTRL_INTR_STATE
+ 4'b 0001, // index[ 1] OTP_CTRL_INTR_ENABLE
+ 4'b 0001, // index[ 2] OTP_CTRL_INTR_TEST
+ 4'b 0001, // index[ 3] OTP_CTRL_ALERT_TEST
+ 4'b 0111, // index[ 4] OTP_CTRL_STATUS
+ 4'b 1111, // index[ 5] OTP_CTRL_ERR_CODE
+ 4'b 0001, // index[ 6] OTP_CTRL_DIRECT_ACCESS_REGWEN
+ 4'b 0001, // index[ 7] OTP_CTRL_DIRECT_ACCESS_CMD
+ 4'b 0011, // index[ 8] OTP_CTRL_DIRECT_ACCESS_ADDRESS
+ 4'b 1111, // index[ 9] OTP_CTRL_DIRECT_ACCESS_WDATA_0
+ 4'b 1111, // index[10] OTP_CTRL_DIRECT_ACCESS_WDATA_1
+ 4'b 1111, // index[11] OTP_CTRL_DIRECT_ACCESS_RDATA_0
+ 4'b 1111, // index[12] OTP_CTRL_DIRECT_ACCESS_RDATA_1
+ 4'b 0001, // index[13] OTP_CTRL_CHECK_TRIGGER_REGWEN
+ 4'b 0001, // index[14] OTP_CTRL_CHECK_TRIGGER
+ 4'b 0001, // index[15] OTP_CTRL_CHECK_REGWEN
+ 4'b 1111, // index[16] OTP_CTRL_CHECK_TIMEOUT
+ 4'b 1111, // index[17] OTP_CTRL_INTEGRITY_CHECK_PERIOD
+ 4'b 1111, // index[18] OTP_CTRL_CONSISTENCY_CHECK_PERIOD
+ 4'b 0001, // index[19] OTP_CTRL_VENDOR_TEST_READ_LOCK
+ 4'b 0001, // index[20] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK
+ 4'b 0001, // index[21] OTP_CTRL_OWNER_SW_CFG_READ_LOCK
+ 4'b 1111, // index[22] OTP_CTRL_VENDOR_TEST_DIGEST_0
+ 4'b 1111, // index[23] OTP_CTRL_VENDOR_TEST_DIGEST_1
+ 4'b 1111, // index[24] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0
+ 4'b 1111, // index[25] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1
+ 4'b 1111, // index[26] OTP_CTRL_OWNER_SW_CFG_DIGEST_0
+ 4'b 1111, // index[27] OTP_CTRL_OWNER_SW_CFG_DIGEST_1
+ 4'b 1111, // index[28] OTP_CTRL_HW_CFG_DIGEST_0
+ 4'b 1111, // index[29] OTP_CTRL_HW_CFG_DIGEST_1
+ 4'b 1111, // index[30] OTP_CTRL_SECRET0_DIGEST_0
+ 4'b 1111, // index[31] OTP_CTRL_SECRET0_DIGEST_1
+ 4'b 1111, // index[32] OTP_CTRL_SECRET1_DIGEST_0
+ 4'b 1111, // index[33] OTP_CTRL_SECRET1_DIGEST_1
+ 4'b 1111, // index[34] OTP_CTRL_SECRET2_DIGEST_0
+ 4'b 1111 // index[35] OTP_CTRL_SECRET2_DIGEST_1
+ };
+
+endpackage
+
diff --git a/EDA-3283/rtl/prim_alert_pkg.sv b/EDA-3283/rtl/prim_alert_pkg.sv
new file mode 100644
index 00000000..a3594b61
--- /dev/null
+++ b/EDA-3283/rtl/prim_alert_pkg.sv
@@ -0,0 +1,27 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package prim_alert_pkg;
+
+ typedef struct packed {
+ logic alert_p;
+ logic alert_n;
+ } alert_tx_t;
+
+ typedef struct packed {
+ logic ping_p;
+ logic ping_n;
+ logic ack_p;
+ logic ack_n;
+ } alert_rx_t;
+
+ parameter alert_tx_t ALERT_TX_DEFAULT = '{alert_p: 1'b0,
+ alert_n: 1'b1};
+
+ parameter alert_rx_t ALERT_RX_DEFAULT = '{ping_p: 1'b0,
+ ping_n: 1'b1,
+ ack_p: 1'b0,
+ ack_n: 1'b1};
+
+endpackage : prim_alert_pkg
diff --git a/EDA-3283/rtl/prim_alert_sender.sv b/EDA-3283/rtl/prim_alert_sender.sv
new file mode 100644
index 00000000..b9793596
--- /dev/null
+++ b/EDA-3283/rtl/prim_alert_sender.sv
@@ -0,0 +1,239 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// The alert sender primitive module differentially encodes and transmits an
+// alert signal to the prim_alert_receiver module. An alert will be signalled
+// by a full handshake on alert_p/n and ack_p/n. The alert_req_i signal may
+// be continuously asserted, in which case the alert signalling handshake
+// will be repeatedly initiated.
+//
+// The alert_req_i signal may also be used as part of req/ack. The parent module
+// can keep alert_req_i asserted until it has been ack'd (transferred to the alert
+// receiver). The parent module is not required to use this.
+//
+// Further, this module supports in-band ping testing, which means that a level
+// change on the ping_p/n diff pair will result in a full-handshake response
+// on alert_p/n and ack_p/n.
+//
+// The protocol works in both asynchronous and synchronous cases. In the
+// asynchronous case, the parameter AsyncOn must be set to 1'b1 in order to
+// instantiate additional synchronization logic. Further, it must be ensured
+// that the timing skew between all diff pairs is smaller than the shortest
+// clock period of the involved clocks.
+//
+// Incorrectly encoded diff inputs can be detected and will be signalled
+// to the receiver by placing an inconsistent diff value on the differential
+// output (and continuously toggling it).
+//
+// See also: prim_alert_receiver, prim_diff_decode, alert_handler
+
+
+module prim_alert_sender
+ import prim_alert_pkg::*;
+#(parameter IsFatal = 1'b1,
+ // enables additional synchronization logic
+ parameter bit AsyncOn = 1'b1
+) (
+ input clk_i,
+ input rst_ni,
+ // native alert from the peripheral
+ input alert_req_i,
+ output logic alert_ack_o,
+ // ping input diff pair and ack diff pair
+ input alert_rx_t alert_rx_i,
+ // alert output diff pair
+ output alert_tx_t alert_tx_o
+);
+
+
+ /////////////////////////////////
+ // decode differential signals //
+ /////////////////////////////////
+ logic ping_sigint, ping_event;
+
+ prim_diff_decode #(
+ .AsyncOn(AsyncOn)
+ ) i_decode_ping (
+ .clk_i,
+ .rst_ni,
+ .diff_pi ( alert_rx_i.ping_p ),
+ .diff_ni ( alert_rx_i.ping_n ),
+ .level_o ( ),
+ .rise_o ( ),
+ .fall_o ( ),
+ .event_o ( ping_event ),
+ .sigint_o ( ping_sigint )
+ );
+
+ logic ack_sigint, ack_level;
+
+ prim_diff_decode #(
+ .AsyncOn(AsyncOn)
+ ) i_decode_ack (
+ .clk_i,
+ .rst_ni,
+ .diff_pi ( alert_rx_i.ack_p ),
+ .diff_ni ( alert_rx_i.ack_n ),
+ .level_o ( ack_level ),
+ .rise_o ( ),
+ .fall_o ( ),
+ .event_o ( ),
+ .sigint_o ( ack_sigint )
+ );
+
+
+ ///////////////////////////////////////////////////
+ // main protocol FSM that drives the diff output //
+ ///////////////////////////////////////////////////
+ typedef enum logic [2:0] {
+ Idle,
+ AlertHsPhase1,
+ AlertHsPhase2,
+ PingHsPhase1,
+ PingHsPhase2,
+ SigInt,
+ Pause0,
+ Pause1
+ } state_e;
+ state_e state_d, state_q;
+ logic alert_p, alert_n, alert_pq, alert_nq, alert_pd, alert_nd;
+ logic sigint_detected;
+
+ assign sigint_detected = ack_sigint | ping_sigint;
+
+
+ // diff pair output
+ assign alert_tx_o.alert_p = alert_pq;
+ assign alert_tx_o.alert_n = alert_nq;
+
+ // alert and ping set regs
+ logic alert_set_d, alert_set_q, alert_clr;
+ logic ping_set_d, ping_set_q, ping_clr;
+
+ // if handshake is ongoing, capture additional alert requests
+ assign alert_set_d = (alert_clr) ? 1'b0 : (alert_set_q | alert_req_i);
+ assign ping_set_d = (ping_clr) ? 1'b0 : (ping_set_q | ping_event);
+
+ // alert event acknowledge
+ assign alert_ack_o = alert_clr;
+
+ // this FSM performs a full four phase handshake upon a ping or alert trigger.
+ // note that the latency of the alert_p/n diff pair is at least one cycle
+ // until it enters the receiver FSM. the same holds for the ack_* diff pair
+ // input. in case a signal integrity issue is detected, the FSM bails out,
+ // sets the alert_p/n diff pair to the same value and toggles it in order to
+ // signal that condition over to the receiver.
+ always_comb begin : p_fsm
+ // default
+ state_d = state_q;
+ alert_p = 1'b0;
+ alert_n = 1'b1;
+ ping_clr = 1'b0;
+ alert_clr = 1'b0;
+
+ unique case (state_q)
+ Idle: begin
+ // alert always takes precedence
+ if (alert_req_i || alert_set_q || ping_event || ping_set_q) begin
+ state_d = (alert_req_i || alert_set_q) ? AlertHsPhase1 : PingHsPhase1;
+ alert_p = 1'b1;
+ alert_n = 1'b0;
+ end
+ end
+ // waiting for ack from receiver
+ AlertHsPhase1: begin
+ if (ack_level) begin
+ state_d = AlertHsPhase2;
+ end else begin
+ alert_p = 1'b1;
+ alert_n = 1'b0;
+ end
+ end
+ // wait for deassertion of ack
+ AlertHsPhase2: begin
+ if (!ack_level) begin
+ state_d = Pause0;
+ alert_clr = 1'b1;
+ end
+ end
+ // waiting for ack from receiver
+ PingHsPhase1: begin
+ if (ack_level) begin
+ state_d = PingHsPhase2;
+ end else begin
+ alert_p = 1'b1;
+ alert_n = 1'b0;
+ end
+ end
+ // wait for deassertion of ack
+ PingHsPhase2: begin
+ if (!ack_level) begin
+ ping_clr = 1'b1;
+ state_d = Pause0;
+ end
+ end
+ // pause cycles between back-to-back handshakes
+ Pause0: begin
+ state_d = Pause1;
+ end
+
+ // clear and ack alert request if it was set
+ Pause1: begin
+ state_d = Idle;
+ end
+
+ // we have a signal integrity issue at one of
+ // the incoming diff pairs. this condition is
+ // signalled by setting the output diffpair
+ // to the same value and continuously toggling
+ // them.
+ SigInt: begin
+ state_d = Idle;
+ if (sigint_detected) begin
+ state_d = SigInt;
+ alert_p = ~alert_pq;
+ alert_n = ~alert_pq;
+ end
+ end
+ // catch parasitic states
+ default : state_d = Idle;
+ endcase
+ // bail out if a signal integrity issue has been detected
+ if (sigint_detected && (state_q != SigInt)) begin
+ state_d = SigInt;
+ alert_p = 1'b0;
+ alert_n = 1'b0;
+ ping_clr = 1'b0;
+ alert_clr = 1'b0;
+ end
+ end
+
+ // This prevents further tool optimizations of the differential signal.
+ prim_buf u_prim_buf_p (
+ .in_i(alert_p),
+ .out_o(alert_pd)
+ );
+ prim_buf u_prim_buf_n (
+ .in_i(alert_n),
+ .out_o(alert_nd)
+ );
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg
+ if (!rst_ni) begin
+ state_q <= Idle;
+ alert_pq <= 1'b0;
+ alert_nq <= 1'b1;
+ alert_set_q <= 1'b0;
+ ping_set_q <= 1'b0;
+ end else begin
+ state_q <= state_d;
+ alert_pq <= alert_pd;
+ alert_nq <= alert_nd;
+ alert_set_q <= alert_set_d;
+ ping_set_q <= ping_set_d;
+ end
+ end
+
+
+endmodule : prim_alert_sender
diff --git a/EDA-3283/rtl/prim_buf.sv b/EDA-3283/rtl/prim_buf.sv
new file mode 100644
index 00000000..bbe8f6cd
--- /dev/null
+++ b/EDA-3283/rtl/prim_buf.sv
@@ -0,0 +1,37 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is auto-generated.
+
+`ifndef PRIM_DEFAULT_IMPL
+ `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
+`endif
+
+// This is to prevent AscentLint warnings in the generated
+// abstract prim wrapper. These warnings occur due to the .*
+// use. TODO: we may want to move these inline waivers
+// into a separate, generated waiver file for consistency.
+//ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
+module prim_buf
+
+#(
+parameter Width = 1
+) (
+ input in_i,
+ output logic out_o
+);
+ parameter prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
+
+if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx
+ prim_xilinx_buf u_impl_xilinx (
+ .*
+ );
+end else begin : gen_generic
+ prim_generic_buf u_impl_generic (
+ .*
+ );
+end
+
+endmodule
+//ri lint_check_on OUTPUT_NOT_DRIVEN INPUT_NOT_READ
diff --git a/EDA-3283/rtl/prim_cipher_pkg.sv b/EDA-3283/rtl/prim_cipher_pkg.sv
new file mode 100644
index 00000000..742c9253
--- /dev/null
+++ b/EDA-3283/rtl/prim_cipher_pkg.sv
@@ -0,0 +1,397 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This package holds common constants and functions for PRESENT- and
+// PRINCE-based scrambling devices.
+//
+// See also: prim_present, prim_prince
+//
+// References: - https://en.wikipedia.org/wiki/PRESENT
+// - https://en.wikipedia.org/wiki/Prince_(cipher)
+// - http://www.lightweightcrypto.org/present/present_ches2007.pdf
+// - https://eprint.iacr.org/2012/529.pdf
+// - https://eprint.iacr.org/2015/372.pdf
+// - https://eprint.iacr.org/2014/656.pdf
+
+package prim_cipher_pkg;
+
+ ///////////////////
+ // PRINCE Cipher //
+ ///////////////////
+
+ parameter logic [15:0][3:0] PRINCE_SBOX4 = {4'h4, 4'hD, 4'h5, 4'hE,
+ 4'h0, 4'h8, 4'h7, 4'h6,
+ 4'h1, 4'h9, 4'hC, 4'hA,
+ 4'h2, 4'h3, 4'hF, 4'hB};
+
+ parameter logic [15:0][3:0] PRINCE_SBOX4_INV = {4'h1, 4'hC, 4'hE, 4'h5,
+ 4'h0, 4'h4, 4'h6, 4'hA,
+ 4'h9, 4'h8, 4'hD, 4'hF,
+ 4'h2, 4'h3, 4'h7, 4'hB};
+ // nibble permutations
+ parameter logic [15:0][3:0] PRINCE_SHIFT_ROWS64 = '{4'hF, 4'hA, 4'h5, 4'h0,
+ 4'hB, 4'h6, 4'h1, 4'hC,
+ 4'h7, 4'h2, 4'hD, 4'h8,
+ 4'h3, 4'hE, 4'h9, 4'h4};
+
+ parameter logic [15:0][3:0] PRINCE_SHIFT_ROWS64_INV = '{4'hF, 4'h2, 4'h5, 4'h8,
+ 4'hB, 4'hE, 4'h1, 4'h4,
+ 4'h7, 4'hA, 4'hD, 4'h0,
+ 4'h3, 4'h6, 4'h9, 4'hC};
+
+ // these are the round constants
+ parameter logic [11:0][63:0] PRINCE_ROUND_CONST = {64'hC0AC29B7C97C50DD,
+ 64'hD3B5A399CA0C2399,
+ 64'h64A51195E0E3610D,
+ 64'hC882D32F25323C54,
+ 64'h85840851F1AC43AA,
+ 64'h7EF84F78FD955CB1,
+ 64'hBE5466CF34E90C6C,
+ 64'h452821E638D01377,
+ 64'h082EFA98EC4E6C89,
+ 64'hA4093822299F31D0,
+ 64'h13198A2E03707344,
+ 64'h0000000000000000};
+
+ // tweak constant for key modification between enc/dec modes
+ parameter logic [63:0] PRINCE_ALPHA_CONST = 64'hC0AC29B7C97C50DD;
+
+ // masking constants for shift rows function below
+ parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST0 = 16'h7BDE;
+ parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST1 = 16'hBDE7;
+ parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST2 = 16'hDE7B;
+ parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST3 = 16'hE7BD;
+
+ // nibble shifts
+ function automatic logic [31:0] prince_shiftrows_32bit(logic [31:0] state_in,
+ logic [15:0][3:0] shifts );
+ logic [31:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 32/2; k++) begin
+ // operate on pairs of 2bit instead of nibbles
+ state_out[k*2 +: 2] = state_in[shifts[k]*2 +: 2];
+ end
+ return state_out;
+ endfunction : prince_shiftrows_32bit
+
+ function automatic logic [63:0] prince_shiftrows_64bit(logic [63:0] state_in,
+ logic [15:0][3:0] shifts );
+ logic [63:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 64/4; k++) begin
+ state_out[k*4 +: 4] = state_in[shifts[k]*4 +: 4];
+ end
+ return state_out;
+ endfunction : prince_shiftrows_64bit
+
+ // XOR reduction of four nibbles in a 16bit subvector
+ function automatic logic [3:0] prince_nibble_red16(logic [15:0] vect);
+ return vect[0 +: 4] ^ vect[4 +: 4] ^ vect[8 +: 4] ^ vect[12 +: 4];
+ endfunction : prince_nibble_red16
+
+ // M prime multiplication
+ function automatic logic [31:0] prince_mult_prime_32bit(logic [31:0] state_in);
+ logic [31:0] state_out;
+ // M0
+ state_out[0 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[4 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[8 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ state_out[12 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ // M1
+ state_out[16 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ state_out[20 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[24 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[28 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ return state_out;
+ endfunction : prince_mult_prime_32bit
+
+ // M prime multiplication
+ function automatic logic [63:0] prince_mult_prime_64bit(logic [63:0] state_in);
+ logic [63:0] state_out;
+ // M0
+ state_out[0 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[4 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[8 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ state_out[12 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ // M1
+ state_out[16 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ state_out[20 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[24 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[28 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ // M1
+ state_out[32 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ state_out[36 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[40 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[44 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ // M0
+ state_out[48 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST3);
+ state_out[52 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST2);
+ state_out[56 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST1);
+ state_out[60 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST0);
+ return state_out;
+ endfunction : prince_mult_prime_64bit
+
+
+ ////////////////////
+ // PRESENT Cipher //
+ ////////////////////
+
+ // this is the sbox from the present cipher
+ parameter logic [15:0][3:0] PRESENT_SBOX4 = {4'h2, 4'h1, 4'h7, 4'h4,
+ 4'h8, 4'hF, 4'hE, 4'h3,
+ 4'hD, 4'hA, 4'h0, 4'h9,
+ 4'hB, 4'h6, 4'h5, 4'hC};
+
+ parameter logic [15:0][3:0] PRESENT_SBOX4_INV = {4'hA, 4'h9, 4'h7, 4'h0,
+ 4'h3, 4'h6, 4'h4, 4'hB,
+ 4'hD, 4'h2, 4'h1, 4'hC,
+ 4'h8, 4'hF, 4'hE, 4'h5};
+
+ // these are modified permutation indices for a 32bit version that
+ // follow the same pattern as for the 64bit version
+ parameter logic [31:0][4:0] PRESENT_PERM32 = {5'd31, 5'd23, 5'd15, 5'd07,
+ 5'd30, 5'd22, 5'd14, 5'd06,
+ 5'd29, 5'd21, 5'd13, 5'd05,
+ 5'd28, 5'd20, 5'd12, 5'd04,
+ 5'd27, 5'd19, 5'd11, 5'd03,
+ 5'd26, 5'd18, 5'd10, 5'd02,
+ 5'd25, 5'd17, 5'd09, 5'd01,
+ 5'd24, 5'd16, 5'd08, 5'd00};
+
+ parameter logic [31:0][4:0] PRESENT_PERM32_INV = {5'd31, 5'd27, 5'd23, 5'd19,
+ 5'd15, 5'd11, 5'd07, 5'd03,
+ 5'd30, 5'd26, 5'd22, 5'd18,
+ 5'd14, 5'd10, 5'd06, 5'd02,
+ 5'd29, 5'd25, 5'd21, 5'd17,
+ 5'd13, 5'd09, 5'd05, 5'd01,
+ 5'd28, 5'd24, 5'd20, 5'd16,
+ 5'd12, 5'd08, 5'd04, 5'd00};
+
+ // these are the permutation indices of the present cipher
+ parameter logic [63:0][5:0] PRESENT_PERM64 = {6'd63, 6'd47, 6'd31, 6'd15,
+ 6'd62, 6'd46, 6'd30, 6'd14,
+ 6'd61, 6'd45, 6'd29, 6'd13,
+ 6'd60, 6'd44, 6'd28, 6'd12,
+ 6'd59, 6'd43, 6'd27, 6'd11,
+ 6'd58, 6'd42, 6'd26, 6'd10,
+ 6'd57, 6'd41, 6'd25, 6'd09,
+ 6'd56, 6'd40, 6'd24, 6'd08,
+ 6'd55, 6'd39, 6'd23, 6'd07,
+ 6'd54, 6'd38, 6'd22, 6'd06,
+ 6'd53, 6'd37, 6'd21, 6'd05,
+ 6'd52, 6'd36, 6'd20, 6'd04,
+ 6'd51, 6'd35, 6'd19, 6'd03,
+ 6'd50, 6'd34, 6'd18, 6'd02,
+ 6'd49, 6'd33, 6'd17, 6'd01,
+ 6'd48, 6'd32, 6'd16, 6'd00};
+
+ parameter logic [63:0][5:0] PRESENT_PERM64_INV = {6'd63, 6'd59, 6'd55, 6'd51,
+ 6'd47, 6'd43, 6'd39, 6'd35,
+ 6'd31, 6'd27, 6'd23, 6'd19,
+ 6'd15, 6'd11, 6'd07, 6'd03,
+ 6'd62, 6'd58, 6'd54, 6'd50,
+ 6'd46, 6'd42, 6'd38, 6'd34,
+ 6'd30, 6'd26, 6'd22, 6'd18,
+ 6'd14, 6'd10, 6'd06, 6'd02,
+ 6'd61, 6'd57, 6'd53, 6'd49,
+ 6'd45, 6'd41, 6'd37, 6'd33,
+ 6'd29, 6'd25, 6'd21, 6'd17,
+ 6'd13, 6'd09, 6'd05, 6'd01,
+ 6'd60, 6'd56, 6'd52, 6'd48,
+ 6'd44, 6'd40, 6'd36, 6'd32,
+ 6'd28, 6'd24, 6'd20, 6'd16,
+ 6'd12, 6'd08, 6'd04, 6'd00};
+
+ // forward key schedule
+ function automatic logic [63:0] present_update_key64(logic [63:0] key_in,
+ logic [4:0] round_idx);
+ logic [63:0] key_out;
+ // rotate by 61 to the left
+ key_out = {key_in[63-61:0], key_in[63:64-61]};
+ // sbox on uppermost 4 bits
+ key_out[63 -: 4] = PRESENT_SBOX4[key_out[63 -: 4]];
+ // xor in round counter on bits 19 to 15
+ key_out[19:15] ^= round_idx;
+ return key_out;
+ endfunction : present_update_key64
+
+ function automatic logic [79:0] present_update_key80(logic [79:0] key_in,
+ logic [4:0] round_idx);
+ logic [79:0] key_out;
+ // rotate by 61 to the left
+ key_out = {key_in[79-61:0], key_in[79:80-61]};
+ // sbox on uppermost 4 bits
+ key_out[79 -: 4] = PRESENT_SBOX4[key_out[79 -: 4]];
+ // xor in round counter on bits 19 to 15
+ key_out[19:15] ^= round_idx;
+ return key_out;
+ endfunction : present_update_key80
+
+ function automatic logic [127:0] present_update_key128(logic [127:0] key_in,
+ logic [4:0] round_idx);
+ logic [127:0] key_out;
+ // rotate by 61 to the left
+ key_out = {key_in[127-61:0], key_in[127:128-61]};
+ // sbox on uppermost 4 bits
+ key_out[127 -: 4] = PRESENT_SBOX4[key_out[127 -: 4]];
+ // sbox on second nibble from top
+ key_out[123 -: 4] = PRESENT_SBOX4[key_out[123 -: 4]];
+ // xor in round counter on bits 66 to 62
+ key_out[66:62] ^= round_idx;
+ return key_out;
+ endfunction : present_update_key128
+
+
+ // inverse key schedule
+ function automatic logic [63:0] present_inv_update_key64(logic [63:0] key_in,
+ logic [4:0] round_idx);
+ logic [63:0] key_out = key_in;
+ // xor in round counter on bits 19 to 15
+ key_out[19:15] ^= round_idx;
+ // sbox on uppermost 4 bits
+ key_out[63 -: 4] = PRESENT_SBOX4_INV[key_out[63 -: 4]];
+ // rotate by 61 to the right
+ key_out = {key_out[60:0], key_out[63:61]};
+ return key_out;
+ endfunction : present_inv_update_key64
+
+ function automatic logic [79:0] present_inv_update_key80(logic [79:0] key_in,
+ logic [4:0] round_idx);
+ logic [79:0] key_out = key_in;
+ // xor in round counter on bits 19 to 15
+ key_out[19:15] ^= round_idx;
+ // sbox on uppermost 4 bits
+ key_out[79 -: 4] = PRESENT_SBOX4_INV[key_out[79 -: 4]];
+ // rotate by 61 to the right
+ key_out = {key_out[60:0], key_out[79:61]};
+ return key_out;
+ endfunction : present_inv_update_key80
+
+ function automatic logic [127:0] present_inv_update_key128(logic [127:0] key_in,
+ logic [4:0] round_idx);
+ logic [127:0] key_out = key_in;
+ // xor in round counter on bits 66 to 62
+ key_out[66:62] ^= round_idx;
+ // sbox on second highest nibble
+ key_out[123 -: 4] = PRESENT_SBOX4_INV[key_out[123 -: 4]];
+ // sbox on uppermost 4 bits
+ key_out[127 -: 4] = PRESENT_SBOX4_INV[key_out[127 -: 4]];
+ // rotate by 61 to the right
+ key_out = {key_out[60:0], key_out[127:61]};
+ return key_out;
+ endfunction : present_inv_update_key128
+
+
+ // these functions can be used to derive the DEC key from the ENC key by
+ // stepping the key by the correct number of rounds using the keyschedule functions above.
+ function automatic logic [63:0] present_get_dec_key64(logic [63:0] key_in,
+ // total number of rounds employed
+ logic [4:0] round_cnt);
+ logic [63:0] key_out;
+ key_out = key_in;
+ for (int unsigned k = 0; k < round_cnt; k++) begin
+ key_out = present_update_key64(key_out, 5'(k + 1));
+ end
+ return key_out;
+ endfunction : present_get_dec_key64
+
+ function automatic logic [79:0] present_get_dec_key80(logic [79:0] key_in,
+ // total number of rounds employed
+ logic [4:0] round_cnt);
+ logic [79:0] key_out;
+ key_out = key_in;
+ for (int unsigned k = 0; k < round_cnt; k++) begin
+ key_out = present_update_key80(key_out, 5'(k + 1));
+ end
+ return key_out;
+ endfunction : present_get_dec_key80
+
+ function automatic logic [127:0] present_get_dec_key128(logic [127:0] key_in,
+ // total number of rounds employed
+ logic [4:0] round_cnt);
+ logic [127:0] key_out;
+ key_out = key_in;
+ for (int unsigned k = 0; k < round_cnt; k++) begin
+ key_out = present_update_key128(key_out, 5'(k + 1));
+ end
+ return key_out;
+ endfunction : present_get_dec_key128
+
+ /////////////////////////
+ // Common Subfunctions //
+ /////////////////////////
+
+ function automatic logic [7:0] sbox4_8bit(logic [7:0] state_in, logic [15:0][3:0] sbox4);
+ logic [7:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 8/4; k++) begin
+ state_out[k*4 +: 4] = sbox4[state_in[k*4 +: 4]];
+ end
+ return state_out;
+ endfunction : sbox4_8bit
+
+ function automatic logic [15:0] sbox4_16bit(logic [15:0] state_in, logic [15:0][3:0] sbox4);
+ logic [15:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 2; k++) begin
+ state_out[k*8 +: 8] = sbox4_8bit(state_in[k*8 +: 8], sbox4);
+ end
+ return state_out;
+ endfunction : sbox4_16bit
+
+ function automatic logic [31:0] sbox4_32bit(logic [31:0] state_in, logic [15:0][3:0] sbox4);
+ logic [31:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 4; k++) begin
+ state_out[k*8 +: 8] = sbox4_8bit(state_in[k*8 +: 8], sbox4);
+ end
+ return state_out;
+ endfunction : sbox4_32bit
+
+ function automatic logic [63:0] sbox4_64bit(logic [63:0] state_in, logic [15:0][3:0] sbox4);
+ logic [63:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 8; k++) begin
+ state_out[k*8 +: 8] = sbox4_8bit(state_in[k*8 +: 8], sbox4);
+ end
+ return state_out;
+ endfunction : sbox4_64bit
+
+ function automatic logic [7:0] perm_8bit(logic [7:0] state_in, logic [7:0][2:0] perm);
+ logic [7:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 8; k++) begin
+ state_out[perm[k]] = state_in[k];
+ end
+ return state_out;
+ endfunction : perm_8bit
+
+ function automatic logic [15:0] perm_16bit(logic [15:0] state_in, logic [15:0][3:0] perm);
+ logic [15:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 16; k++) begin
+ state_out[perm[k]] = state_in[k];
+ end
+ return state_out;
+ endfunction : perm_16bit
+
+ function automatic logic [31:0] perm_32bit(logic [31:0] state_in, logic [31:0][4:0] perm);
+ logic [31:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 32; k++) begin
+ state_out[perm[k]] = state_in[k];
+ end
+ return state_out;
+ endfunction : perm_32bit
+
+ function automatic logic [63:0] perm_64bit(logic [63:0] state_in, logic [63:0][5:0] perm);
+ logic [63:0] state_out;
+ // note that if simulation performance becomes an issue, this loop can be unrolled
+ for (int k = 0; k < 64; k++) begin
+ state_out[perm[k]] = state_in[k];
+ end
+ return state_out;
+ endfunction : perm_64bit
+
+endpackage : prim_cipher_pkg
diff --git a/EDA-3283/rtl/prim_count_pkg.sv b/EDA-3283/rtl/prim_count_pkg.sv
new file mode 100644
index 00000000..f49a270c
--- /dev/null
+++ b/EDA-3283/rtl/prim_count_pkg.sv
@@ -0,0 +1,22 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Package for primitive hardened counter module
+//
+
+package prim_count_pkg;
+
+ // Enumeration for hardened count style
+ typedef enum logic {
+ CrossCnt, // up count and down count
+ DupCnt // duplicate counters
+ } prim_count_style_e;
+
+ // Enumeration for differential valid
+ typedef enum logic [1:0] {
+ CmpInvalid = 2'b01,
+ CmpValid = 2'b10
+ } cmp_valid_e;
+
+endpackage //
diff --git a/EDA-3283/rtl/prim_diff_decode.sv b/EDA-3283/rtl/prim_diff_decode.sv
new file mode 100644
index 00000000..780cb0bc
--- /dev/null
+++ b/EDA-3283/rtl/prim_diff_decode.sv
@@ -0,0 +1,207 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This module decodes a differentially encoded signal and detects
+// incorrectly encoded differential states.
+//
+// In case the differential pair crosses an asynchronous boundary, it has
+// to be re-synchronized to the local clock. This can be achieved by
+// setting the AsyncOn parameter to 1'b1. In that case, two additional
+// input registers are added (to counteract metastability), and
+// a pattern detector is instantiated that detects skewed level changes on
+// the differential pair (i.e., when level changes on the diff pair are
+// sampled one cycle apart due to a timing skew between the two wires).
+//
+// See also: prim_alert_sender, prim_alert_receiver, alert_handler
+
+
+module prim_diff_decode #(
+ // enables additional synchronization logic
+ parameter bit AsyncOn = 1'b0
+) (
+ input clk_i,
+ input rst_ni,
+ // input diff pair
+ input diff_pi,
+ input diff_ni,
+ // logical level and
+ // detected edges
+ output logic level_o,
+ output logic rise_o,
+ output logic fall_o,
+ // either rise or fall
+ output logic event_o,
+ //signal integrity issue detected
+ output logic sigint_o
+);
+
+ logic level_d, level_q;
+
+ ///////////////////////////////////////////////////////////////
+ // synchronization regs for incoming diff pair (if required) //
+ ///////////////////////////////////////////////////////////////
+ if (AsyncOn) begin : gen_async
+
+ typedef enum logic [1:0] {IsStd, IsSkewed, SigInt} state_e;
+ state_e state_d, state_q;
+ logic diff_p_edge, diff_n_edge, diff_check_ok, level;
+
+ // 2 sync regs, one reg for edge detection
+ logic diff_pq, diff_nq, diff_pd, diff_nd;
+
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue(0)
+ ) i_sync_p (
+ .clk_i,
+ .rst_ni,
+ .d_i(diff_pi),
+ .q_o(diff_pd)
+ );
+
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue(1)
+ ) i_sync_n (
+ .clk_i,
+ .rst_ni,
+ .d_i(diff_ni),
+ .q_o(diff_nd)
+ );
+
+ // detect level transitions
+ assign diff_p_edge = diff_pq ^ diff_pd;
+ assign diff_n_edge = diff_nq ^ diff_nd;
+
+ // detect sigint issue
+ assign diff_check_ok = diff_pd ^ diff_nd;
+
+ // this is the current logical level
+ assign level = diff_pd;
+
+ // outputs
+ assign level_o = level_d;
+ assign event_o = rise_o | fall_o;
+
+ // sigint detection is a bit more involved in async case since
+ // we might have skew on the diff pair, which can result in a
+ // one cycle sampling delay between the two wires
+ // so we need a simple pattern matcher
+ // the following waves are legal
+ // clk | | | | | | | |
+ // _______ _______
+ // p _______/ ... \________
+ // _______ ________
+ // n \_______ ... _______/
+ // ____ ___
+ // p __________/ ... \________
+ // _______ ________
+ // n \_______ ... _______/
+ //
+ // i.e., level changes may be off by one cycle - which is permissible
+ // as long as this condition is only one cycle long.
+
+
+ always_comb begin : p_diff_fsm
+ // default
+ state_d = state_q;
+ level_d = level_q;
+ rise_o = 1'b0;
+ fall_o = 1'b0;
+ sigint_o = 1'b0;
+
+ unique case (state_q)
+ // we remain here as long as
+ // the diff pair is correctly encoded
+ IsStd: begin
+ if (diff_check_ok) begin
+ level_d = level;
+ if (diff_p_edge && diff_n_edge) begin
+ if (level) begin
+ rise_o = 1'b1;
+ end else begin
+ fall_o = 1'b1;
+ end
+ end
+ end else begin
+ if (diff_p_edge || diff_n_edge) begin
+ state_d = IsSkewed;
+ end else begin
+ state_d = SigInt;
+ sigint_o = 1'b1;
+ end
+ end
+ end
+ // diff pair must be correctly encoded, otherwise we got a sigint
+ IsSkewed: begin
+ if (diff_check_ok) begin
+ state_d = IsStd;
+ level_d = level;
+ if (level) rise_o = 1'b1;
+ else fall_o = 1'b1;
+ end else begin
+ state_d = SigInt;
+ sigint_o = 1'b1;
+ end
+ end
+ // Signal integrity issue detected, remain here
+ // until resolved
+ SigInt: begin
+ sigint_o = 1'b1;
+ if (diff_check_ok) begin
+ state_d = IsStd;
+ sigint_o = 1'b0;
+ end
+ end
+ default : ;
+ endcase
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_sync_reg
+ if (!rst_ni) begin
+ state_q <= IsStd;
+ diff_pq <= 1'b0;
+ diff_nq <= 1'b1;
+ level_q <= 1'b0;
+ end else begin
+ state_q <= state_d;
+ diff_pq <= diff_pd;
+ diff_nq <= diff_nd;
+ level_q <= level_d;
+ end
+ end
+
+ //////////////////////////////////////////////////////////
+ // fully synchronous case, no skew present in this case //
+ //////////////////////////////////////////////////////////
+ end else begin : gen_no_async
+ logic diff_pq, diff_pd;
+
+ // one reg for edge detection
+ assign diff_pd = diff_pi;
+
+ // incorrect encoding -> signal integrity issue
+ assign sigint_o = ~(diff_pi ^ diff_ni);
+
+ assign level_o = (sigint_o) ? level_q : diff_pi;
+ assign level_d = level_o;
+
+ // detect level transitions
+ assign rise_o = (~diff_pq & diff_pi) & ~sigint_o;
+ assign fall_o = ( diff_pq & ~diff_pi) & ~sigint_o;
+ assign event_o = rise_o | fall_o;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_edge_reg
+ if (!rst_ni) begin
+ diff_pq <= 1'b0;
+ level_q <= 1'b0;
+ end else begin
+ diff_pq <= diff_pd;
+ level_q <= level_d;
+ end
+ end
+ end
+
+
+endmodule : prim_diff_decode
diff --git a/EDA-3283/rtl/prim_fifo_sync.sv b/EDA-3283/rtl/prim_fifo_sync.sv
new file mode 100644
index 00000000..9bc0bff3
--- /dev/null
+++ b/EDA-3283/rtl/prim_fifo_sync.sv
@@ -0,0 +1,148 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Generic synchronous fifo for use in a variety of devices.
+module prim_fifo_sync #(
+ parameter int unsigned Width = 16,
+ parameter bit Pass = 1'b1, // if == 1 allow requests to pass through empty FIFO
+ parameter int unsigned Depth = 4,
+ parameter bit OutputZeroIfEmpty = 1'b1, // if == 1 always output 0 when FIFO is empty
+ // derived parameter
+ localparam int unsigned DepthWNorm = $clog2(Depth+1),
+ localparam int unsigned DepthW = (DepthWNorm == 0) ? 1 : DepthWNorm
+) (
+ input clk_i,
+ input rst_ni,
+ // synchronous clear / flush port
+ input clr_i,
+ // write port
+ input wvalid,
+ output wready,
+ input [Width-1:0] wdata,
+ // read port
+ output rvalid,
+ input rready,
+ output [Width-1:0] rdata,
+ // occupancy
+ output [DepthW-1:0] depth
+);
+
+ // FIFO is in complete passthrough mode
+ if (Depth == 0) begin : gen_passthru_fifo
+
+ assign depth = 1'b0; //output is meaningless
+
+ // devie facing
+ assign rvalid = wvalid;
+ assign rdata = wdata;
+
+ // host facing
+ assign wready = rready;
+
+ // this avoids lint warnings
+ logic unused_clr;
+ assign unused_clr = clr_i;
+
+ // Normal FIFO construction
+ end else begin : gen_normal_fifo
+
+ // consider Depth == 1 case when $clog2(1) == 0
+ localparam int unsigned PTRV_W = $clog2(Depth) + ~|$clog2(Depth);
+ localparam int unsigned PTR_WIDTH = PTRV_W+1;
+
+ logic [PTR_WIDTH-1:0] fifo_wptr, fifo_rptr;
+ logic fifo_incr_wptr, fifo_incr_rptr, fifo_empty;
+
+ // create the write and read pointers
+ logic full, empty;
+ logic wptr_msb;
+ logic rptr_msb;
+ logic [PTRV_W-1:0] wptr_value;
+ logic [PTRV_W-1:0] rptr_value;
+
+ assign wptr_msb = fifo_wptr[PTR_WIDTH-1];
+ assign rptr_msb = fifo_rptr[PTR_WIDTH-1];
+ assign wptr_value = fifo_wptr[0+:PTRV_W];
+ assign rptr_value = fifo_rptr[0+:PTRV_W];
+ assign depth = (full) ? DepthW'(Depth) :
+ (wptr_msb == rptr_msb) ? DepthW'(wptr_value) - DepthW'(rptr_value) :
+ (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_value)) ;
+
+ assign fifo_incr_wptr = wvalid & wready;
+ assign fifo_incr_rptr = rvalid & rready;
+
+ assign wready = ~full;
+ assign rvalid = ~empty;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_wptr <= {(PTR_WIDTH){1'b0}};
+ end else if (clr_i) begin
+ fifo_wptr <= {(PTR_WIDTH){1'b0}};
+ end else if (fifo_incr_wptr) begin
+ if (fifo_wptr[PTR_WIDTH-2:0] == (Depth-1)) begin
+ fifo_wptr <= {~fifo_wptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}};
+ end else begin
+ fifo_wptr <= fifo_wptr + {{(PTR_WIDTH-1){1'b0}},1'b1};
+ end
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_rptr <= {(PTR_WIDTH){1'b0}};
+ end else if (clr_i) begin
+ fifo_rptr <= {(PTR_WIDTH){1'b0}};
+ end else if (fifo_incr_rptr) begin
+ if (fifo_rptr[PTR_WIDTH-2:0] == (Depth-1)) begin
+ fifo_rptr <= {~fifo_rptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}};
+ end else begin
+ fifo_rptr <= fifo_rptr + {{(PTR_WIDTH-1){1'b0}},1'b1};
+ end
+ end
+ end
+
+ assign full = (fifo_wptr == (fifo_rptr ^ {1'b1,{(PTR_WIDTH-1){1'b0}}}));
+ assign fifo_empty = (fifo_wptr == fifo_rptr);
+
+
+ // the generate blocks below are needed to avoid lint errors due to array indexing
+ // in the where the fifo only has one storage element
+ logic [Depth-1:0][Width-1:0] storage;
+ logic [Width-1:0] storage_rdata;
+ if (Depth == 1) begin : gen_depth_eq1
+ assign storage_rdata = storage[0];
+
+ always_ff @(posedge clk_i)
+ if (fifo_incr_wptr) begin
+ storage[0] <= wdata;
+ end
+ // fifo with more than one storage element
+ end else begin : gen_depth_gt1
+ assign storage_rdata = storage[fifo_rptr[PTR_WIDTH-2:0]];
+
+ always_ff @(posedge clk_i)
+ if (fifo_incr_wptr) begin
+ storage[fifo_wptr[PTR_WIDTH-2:0]] <= wdata;
+ end
+ end
+
+ logic [Width-1:0] rdata_int;
+ if (Pass == 1'b1) begin : gen_pass
+ assign rdata_int = (fifo_empty && wvalid) ? wdata : storage_rdata;
+ assign empty = fifo_empty & ~wvalid;
+ end else begin : gen_nopass
+ assign rdata_int = storage_rdata;
+ assign empty = fifo_empty;
+ end
+
+ if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
+ assign rdata = empty ? 'b0 : rdata_int;
+ end else begin : gen_no_output_zero
+ assign rdata = rdata_int;
+ end
+ end // block: gen_normal_fifo
+
+
+endmodule
diff --git a/EDA-3283/rtl/prim_flop_2sync.sv b/EDA-3283/rtl/prim_flop_2sync.sv
new file mode 100644
index 00000000..3665c804
--- /dev/null
+++ b/EDA-3283/rtl/prim_flop_2sync.sv
@@ -0,0 +1,39 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is auto-generated.
+
+
+// This is to prevent AscentLint warnings in the generated
+// abstract prim wrapper. These warnings occur due to the .*
+// use. TODO: we may want to move these inline waivers
+// into a separate, generated waiver file for consistency.
+//ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
+module prim_flop_2sync
+
+#(
+
+ parameter int Width = 16,
+ localparam int WidthSubOne = Width-1, // temp work around #2679
+ parameter logic [WidthSubOne:0] ResetValue = '0
+
+) (
+ input clk_i, // receive clock
+ input rst_ni,
+ input [Width-1:0] d_i,
+ output logic [Width-1:0] q_o
+);
+
+ if (1) begin : gen_generic
+ prim_generic_flop_2sync #(
+ .ResetValue(ResetValue),
+ .Width(Width)
+ ) u_impl_generic (
+ .*
+ );
+
+ end
+
+endmodule
+//ri lint_check_on OUTPUT_NOT_DRIVEN INPUT_NOT_READ
diff --git a/EDA-3283/rtl/prim_generic_buf.sv b/EDA-3283/rtl/prim_generic_buf.sv
new file mode 100644
index 00000000..b2b4cb54
--- /dev/null
+++ b/EDA-3283/rtl/prim_generic_buf.sv
@@ -0,0 +1,13 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+module prim_generic_buf (
+ input in_i,
+ output logic out_o
+);
+
+ assign out_o = in_i;
+
+endmodule
diff --git a/EDA-3283/rtl/prim_generic_flop.sv b/EDA-3283/rtl/prim_generic_flop.sv
new file mode 100644
index 00000000..8eacf015
--- /dev/null
+++ b/EDA-3283/rtl/prim_generic_flop.sv
@@ -0,0 +1,26 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// `include "prim_assert.sv"
+
+module prim_generic_flop # (
+ parameter int Width = 1,
+ localparam int WidthSubOne = Width-1,
+ parameter logic [WidthSubOne:0] ResetValue = 0
+) (
+ input clk_i,
+ input rst_ni,
+ input [Width-1:0] d_i,
+ output logic [Width-1:0] q_o
+);
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ q_o <= ResetValue;
+ end else begin
+ q_o <= d_i;
+ end
+ end
+
+endmodule // prim_generic_flop
diff --git a/EDA-3283/rtl/prim_generic_flop_2sync.sv b/EDA-3283/rtl/prim_generic_flop_2sync.sv
new file mode 100644
index 00000000..fdd1358d
--- /dev/null
+++ b/EDA-3283/rtl/prim_generic_flop_2sync.sv
@@ -0,0 +1,43 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Generic double-synchronizer flop
+// This may need to be moved to prim_generic if libraries have a specific cell
+// for synchronization
+
+module prim_generic_flop_2sync #(
+ parameter int Width = 16,
+ localparam int WidthSubOne = Width-1, // temp work around #2679
+ parameter logic [WidthSubOne:0] ResetValue = '0
+) (
+ input clk_i, // receive clock
+ input rst_ni,
+ input [Width-1:0] d_i,
+ output logic [Width-1:0] q_o
+);
+
+ logic [Width-1:0] intq;
+
+ prim_generic_flop #(
+ .Width(Width),
+ .ResetValue(ResetValue)
+ ) u_sync_1 (
+ .clk_i,
+ .rst_ni,
+ .d_i,
+ .q_o(intq)
+ );
+
+ prim_generic_flop #(
+ .Width(Width),
+ .ResetValue(ResetValue)
+ ) u_sync_2 (
+ .clk_i,
+ .rst_ni,
+ .d_i(intq),
+ .q_o
+ );
+
+
+endmodule
diff --git a/EDA-3283/rtl/prim_intr_hw.sv b/EDA-3283/rtl/prim_intr_hw.sv
new file mode 100644
index 00000000..be09a7c8
--- /dev/null
+++ b/EDA-3283/rtl/prim_intr_hw.sv
@@ -0,0 +1,58 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Primitive interrupt handler. This assumes the existence of three
+// controller registers: INTR_ENABLE, INTR_STATE, INTR_TEST.
+// This module can be instantiated once per interrupt field, or
+// "bussified" with all fields of the interrupt vector.
+
+module prim_intr_hw # (
+ parameter int unsigned Width = 1,
+ parameter bit FlopOutput = 1
+) (
+ // event
+ input clk_i,
+ input rst_ni,
+ input [Width-1:0] event_intr_i,
+
+ // register interface
+ input [Width-1:0] reg2hw_intr_enable_q_i,
+ input [Width-1:0] reg2hw_intr_test_q_i,
+ input reg2hw_intr_test_qe_i,
+ input [Width-1:0] reg2hw_intr_state_q_i,
+ output hw2reg_intr_state_de_o,
+ output [Width-1:0] hw2reg_intr_state_d_o,
+
+ // outgoing interrupt
+ output logic [Width-1:0] intr_o
+);
+
+ logic [Width-1:0] new_event;
+ assign new_event =
+ (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
+ assign hw2reg_intr_state_de_o = |new_event;
+ // for scalar interrupts, this resolves to '1' with new event
+ // for vector interrupts, new events are OR'd in to existing interrupt state
+ assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i;
+
+ if (FlopOutput == 1) begin : gen_flop_intr_output
+ // flop the interrupt output
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intr_o <= '0;
+ end else begin
+ intr_o <= reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i;
+ end
+ end
+
+ end else begin : gen_intr_passthrough_output
+ logic unused_clk;
+ logic unused_rst_n;
+ assign unused_clk = clk_i;
+ assign unused_rst_n = rst_ni;
+ assign intr_o = reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i;
+ end
+
+
+endmodule
diff --git a/EDA-3283/rtl/prim_mubi_pkg.sv b/EDA-3283/rtl/prim_mubi_pkg.sv
new file mode 100644
index 00000000..b0b3e838
--- /dev/null
+++ b/EDA-3283/rtl/prim_mubi_pkg.sv
@@ -0,0 +1,531 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/design/gen-mubi.py
+//
+// This package defines common multibit signal types, active high and active low values and
+// the corresponding functions to test whether the values are set or not.
+
+package prim_mubi_pkg;
+
+ //////////////////////////////////////////////
+ // 4 Bit Multibit Type and Functions //
+ //////////////////////////////////////////////
+
+ parameter int MuBi4Width = 4;
+ typedef enum logic [MuBi4Width-1:0] {
+ MuBi4True = 4'hA, // enabled
+ MuBi4False = 4'h5 // disabled
+ } mubi4_t;
+
+ // Test whether the value is supplied is one of the valid enumerations
+ function automatic logic mubi4_test_invalid(mubi4_t val);
+ return ~(val inside {MuBi4True, MuBi4False});
+ endfunction : mubi4_test_invalid
+
+ // Convert a 1 input value to a mubi output
+ function automatic mubi4_t mubi4_bool_to_mubi(logic val);
+ return (val ? MuBi4True : MuBi4False);
+ endfunction : mubi4_bool_to_mubi
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal True.
+ function automatic logic mubi4_test_true_strict(mubi4_t val);
+ return MuBi4True == val;
+ endfunction : mubi4_test_true_strict
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal False.
+ function automatic logic mubi4_test_false_strict(mubi4_t val);
+ return MuBi4False == val;
+ endfunction : mubi4_test_false_strict
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The loose version of this function interprets all
+ // values other than False as "enabled".
+ function automatic logic mubi4_test_true_loose(mubi4_t val);
+ return MuBi4False != val;
+ endfunction : mubi4_test_true_loose
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The loose version of this function interprets all
+ // values other than True as "disabled".
+ function automatic logic mubi4_test_false_loose(mubi4_t val);
+ return MuBi4True != val;
+ endfunction : mubi4_test_false_loose
+
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | act
+ // !act | act | act
+ // act | act | act
+ //
+ function automatic mubi4_t mubi4_or(mubi4_t a, mubi4_t b, mubi4_t act);
+ logic [MuBi4Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi4Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] || b_in[k];
+ end else begin
+ out[k] = a_in[k] && b_in[k];
+ end
+ end
+ return mubi4_t'(out);
+ endfunction : mubi4_or
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | !act
+ // !act | act | !act
+ // act | act | act
+ //
+ function automatic mubi4_t mubi4_and(mubi4_t a, mubi4_t b, mubi4_t act);
+ logic [MuBi4Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi4Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] && b_in[k];
+ end else begin
+ out[k] = a_in[k] || b_in[k];
+ end
+ end
+ return mubi4_t'(out);
+ endfunction : mubi4_and
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi4_t mubi4_or_hi(mubi4_t a, mubi4_t b);
+ return mubi4_or(a, b, MuBi4True);
+ endfunction : mubi4_or_hi
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi4_t mubi4_and_hi(mubi4_t a, mubi4_t b);
+ return mubi4_and(a, b, MuBi4True);
+ endfunction : mubi4_and_hi
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi4_t mubi4_or_lo(mubi4_t a, mubi4_t b);
+ return mubi4_or(a, b, MuBi4False);
+ endfunction : mubi4_or_lo
+
+ // Performs a logical AND operation between two multibit values.
+ // Tlos treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi4_t mubi4_and_lo(mubi4_t a, mubi4_t b);
+ return mubi4_and(a, b, MuBi4False);
+ endfunction : mubi4_and_lo
+
+ //////////////////////////////////////////////
+ // 8 Bit Multibit Type and Functions //
+ //////////////////////////////////////////////
+
+ parameter int MuBi8Width = 8;
+ typedef enum logic [MuBi8Width-1:0] {
+ MuBi8True = 8'h5A, // enabled
+ MuBi8False = 8'hA5 // disabled
+ } mubi8_t;
+
+ // Test whether the value is supplied is one of the valid enumerations
+ function automatic logic mubi8_test_invalid(mubi8_t val);
+ return ~(val inside {MuBi8True, MuBi8False});
+ endfunction : mubi8_test_invalid
+
+ // Convert a 1 input value to a mubi output
+ function automatic mubi8_t mubi8_bool_to_mubi(logic val);
+ return (val ? MuBi8True : MuBi8False);
+ endfunction : mubi8_bool_to_mubi
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal True.
+ function automatic logic mubi8_test_true_strict(mubi8_t val);
+ return MuBi8True == val;
+ endfunction : mubi8_test_true_strict
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal False.
+ function automatic logic mubi8_test_false_strict(mubi8_t val);
+ return MuBi8False == val;
+ endfunction : mubi8_test_false_strict
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The loose version of this function interprets all
+ // values other than False as "enabled".
+ function automatic logic mubi8_test_true_loose(mubi8_t val);
+ return MuBi8False != val;
+ endfunction : mubi8_test_true_loose
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The loose version of this function interprets all
+ // values other than True as "disabled".
+ function automatic logic mubi8_test_false_loose(mubi8_t val);
+ return MuBi8True != val;
+ endfunction : mubi8_test_false_loose
+
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | act
+ // !act | act | act
+ // act | act | act
+ //
+ function automatic mubi8_t mubi8_or(mubi8_t a, mubi8_t b, mubi8_t act);
+ logic [MuBi8Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi8Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] || b_in[k];
+ end else begin
+ out[k] = a_in[k] && b_in[k];
+ end
+ end
+ return mubi8_t'(out);
+ endfunction : mubi8_or
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | !act
+ // !act | act | !act
+ // act | act | act
+ //
+ function automatic mubi8_t mubi8_and(mubi8_t a, mubi8_t b, mubi8_t act);
+ logic [MuBi8Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi8Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] && b_in[k];
+ end else begin
+ out[k] = a_in[k] || b_in[k];
+ end
+ end
+ return mubi8_t'(out);
+ endfunction : mubi8_and
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi8_t mubi8_or_hi(mubi8_t a, mubi8_t b);
+ return mubi8_or(a, b, MuBi8True);
+ endfunction : mubi8_or_hi
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi8_t mubi8_and_hi(mubi8_t a, mubi8_t b);
+ return mubi8_and(a, b, MuBi8True);
+ endfunction : mubi8_and_hi
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi8_t mubi8_or_lo(mubi8_t a, mubi8_t b);
+ return mubi8_or(a, b, MuBi8False);
+ endfunction : mubi8_or_lo
+
+ // Performs a logical AND operation between two multibit values.
+ // Tlos treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi8_t mubi8_and_lo(mubi8_t a, mubi8_t b);
+ return mubi8_and(a, b, MuBi8False);
+ endfunction : mubi8_and_lo
+
+ //////////////////////////////////////////////
+ // 12 Bit Multibit Type and Functions //
+ //////////////////////////////////////////////
+
+ parameter int MuBi12Width = 12;
+ typedef enum logic [MuBi12Width-1:0] {
+ MuBi12True = 12'hA5A, // enabled
+ MuBi12False = 12'h5A5 // disabled
+ } mubi12_t;
+
+ // Test whether the value is supplied is one of the valid enumerations
+ function automatic logic mubi12_test_invalid(mubi12_t val);
+ return ~(val inside {MuBi12True, MuBi12False});
+ endfunction : mubi12_test_invalid
+
+ // Convert a 1 input value to a mubi output
+ function automatic mubi12_t mubi12_bool_to_mubi(logic val);
+ return (val ? MuBi12True : MuBi12False);
+ endfunction : mubi12_bool_to_mubi
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal True.
+ function automatic logic mubi12_test_true_strict(mubi12_t val);
+ return MuBi12True == val;
+ endfunction : mubi12_test_true_strict
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal False.
+ function automatic logic mubi12_test_false_strict(mubi12_t val);
+ return MuBi12False == val;
+ endfunction : mubi12_test_false_strict
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The loose version of this function interprets all
+ // values other than False as "enabled".
+ function automatic logic mubi12_test_true_loose(mubi12_t val);
+ return MuBi12False != val;
+ endfunction : mubi12_test_true_loose
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The loose version of this function interprets all
+ // values other than True as "disabled".
+ function automatic logic mubi12_test_false_loose(mubi12_t val);
+ return MuBi12True != val;
+ endfunction : mubi12_test_false_loose
+
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | act
+ // !act | act | act
+ // act | act | act
+ //
+ function automatic mubi12_t mubi12_or(mubi12_t a, mubi12_t b, mubi12_t act);
+ logic [MuBi12Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi12Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] || b_in[k];
+ end else begin
+ out[k] = a_in[k] && b_in[k];
+ end
+ end
+ return mubi12_t'(out);
+ endfunction : mubi12_or
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | !act
+ // !act | act | !act
+ // act | act | act
+ //
+ function automatic mubi12_t mubi12_and(mubi12_t a, mubi12_t b, mubi12_t act);
+ logic [MuBi12Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi12Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] && b_in[k];
+ end else begin
+ out[k] = a_in[k] || b_in[k];
+ end
+ end
+ return mubi12_t'(out);
+ endfunction : mubi12_and
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi12_t mubi12_or_hi(mubi12_t a, mubi12_t b);
+ return mubi12_or(a, b, MuBi12True);
+ endfunction : mubi12_or_hi
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi12_t mubi12_and_hi(mubi12_t a, mubi12_t b);
+ return mubi12_and(a, b, MuBi12True);
+ endfunction : mubi12_and_hi
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi12_t mubi12_or_lo(mubi12_t a, mubi12_t b);
+ return mubi12_or(a, b, MuBi12False);
+ endfunction : mubi12_or_lo
+
+ // Performs a logical AND operation between two multibit values.
+ // Tlos treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi12_t mubi12_and_lo(mubi12_t a, mubi12_t b);
+ return mubi12_and(a, b, MuBi12False);
+ endfunction : mubi12_and_lo
+
+ //////////////////////////////////////////////
+ // 16 Bit Multibit Type and Functions //
+ //////////////////////////////////////////////
+
+ parameter int MuBi16Width = 16;
+ typedef enum logic [MuBi16Width-1:0] {
+ MuBi16True = 16'h5A5A, // enabled
+ MuBi16False = 16'hA5A5 // disabled
+ } mubi16_t;
+
+ // Test whether the value is supplied is one of the valid enumerations
+ function automatic logic mubi16_test_invalid(mubi16_t val);
+ return ~(val inside {MuBi16True, MuBi16False});
+ endfunction : mubi16_test_invalid
+
+ // Convert a 1 input value to a mubi output
+ function automatic mubi16_t mubi16_bool_to_mubi(logic val);
+ return (val ? MuBi16True : MuBi16False);
+ endfunction : mubi16_bool_to_mubi
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal True.
+ function automatic logic mubi16_test_true_strict(mubi16_t val);
+ return MuBi16True == val;
+ endfunction : mubi16_test_true_strict
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The strict version of this function requires
+ // the multibit value to equal False.
+ function automatic logic mubi16_test_false_strict(mubi16_t val);
+ return MuBi16False == val;
+ endfunction : mubi16_test_false_strict
+
+ // Test whether the multibit value signals an "enabled" condition.
+ // The loose version of this function interprets all
+ // values other than False as "enabled".
+ function automatic logic mubi16_test_true_loose(mubi16_t val);
+ return MuBi16False != val;
+ endfunction : mubi16_test_true_loose
+
+ // Test whether the multibit value signals a "disabled" condition.
+ // The loose version of this function interprets all
+ // values other than True as "disabled".
+ function automatic logic mubi16_test_false_loose(mubi16_t val);
+ return MuBi16True != val;
+ endfunction : mubi16_test_false_loose
+
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | act
+ // !act | act | act
+ // act | act | act
+ //
+ function automatic mubi16_t mubi16_or(mubi16_t a, mubi16_t b, mubi16_t act);
+ logic [MuBi16Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi16Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] || b_in[k];
+ end else begin
+ out[k] = a_in[k] && b_in[k];
+ end
+ end
+ return mubi16_t'(out);
+ endfunction : mubi16_or
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "act" as logical 1, and all other values are
+ // treated as 0. Truth table:
+ //
+ // A | B | OUT
+ //------+------+-----
+ // !act | !act | !act
+ // act | !act | !act
+ // !act | act | !act
+ // act | act | act
+ //
+ function automatic mubi16_t mubi16_and(mubi16_t a, mubi16_t b, mubi16_t act);
+ logic [MuBi16Width-1:0] a_in, b_in, act_in, out;
+ a_in = a;
+ b_in = b;
+ act_in = act;
+ for (int k = 0; k < MuBi16Width; k++) begin
+ if (act_in[k]) begin
+ out[k] = a_in[k] && b_in[k];
+ end else begin
+ out[k] = a_in[k] || b_in[k];
+ end
+ end
+ return mubi16_t'(out);
+ endfunction : mubi16_and
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi16_t mubi16_or_hi(mubi16_t a, mubi16_t b);
+ return mubi16_or(a, b, MuBi16True);
+ endfunction : mubi16_or_hi
+
+ // Performs a logical AND operation between two multibit values.
+ // This treats "True" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi16_t mubi16_and_hi(mubi16_t a, mubi16_t b);
+ return mubi16_and(a, b, MuBi16True);
+ endfunction : mubi16_and_hi
+
+ // Performs a logical OR operation between two multibit values.
+ // This treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi16_t mubi16_or_lo(mubi16_t a, mubi16_t b);
+ return mubi16_or(a, b, MuBi16False);
+ endfunction : mubi16_or_lo
+
+ // Performs a logical AND operation between two multibit values.
+ // Tlos treats "False" as logical 1, and all other values are
+ // treated as 0.
+ function automatic mubi16_t mubi16_and_lo(mubi16_t a, mubi16_t b);
+ return mubi16_and(a, b, MuBi16False);
+ endfunction : mubi16_and_lo
+
+endpackage : prim_mubi_pkg
diff --git a/EDA-3283/rtl/prim_packer.sv b/EDA-3283/rtl/prim_packer.sv
new file mode 100644
index 00000000..a62d84e9
--- /dev/null
+++ b/EDA-3283/rtl/prim_packer.sv
@@ -0,0 +1,228 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Combine InW data and write to OutW data if packed to full word or stop signal
+
+
+module prim_packer #(
+ parameter int InW = 32,
+ parameter int OutW = 32,
+ parameter int HintByteData = 0 // If 1, The input/output are byte granularity
+) (
+ input clk_i ,
+ input rst_ni,
+
+ input valid_i,
+ input [InW-1:0] data_i,
+ input [InW-1:0] mask_i,
+ output ready_o,
+
+ output logic valid_o,
+ output logic [OutW-1:0] data_o,
+ output logic [OutW-1:0] mask_o,
+ input ready_i,
+
+ input flush_i, // If 1, send out remnant and clear state
+ output logic flush_done_o
+);
+
+ localparam int Width = InW + OutW; // storage width
+ localparam int ConcatW = Width + InW; // Input concatenated width
+ localparam int PtrW = $clog2(ConcatW+1);
+ localparam int IdxW = $clog2(InW) + ~|$clog2(InW);
+
+ logic valid_next, ready_next;
+ logic [Width-1:0] stored_data, stored_mask;
+ logic [ConcatW-1:0] concat_data, concat_mask;
+ logic [ConcatW-1:0] shiftl_data, shiftl_mask;
+
+ logic [PtrW-1:0] pos, pos_next; // Current write position
+ logic [IdxW-1:0] lod_idx; // result of Leading One Detector
+ logic [$clog2(InW+1)-1:0] inmask_ones; // Counting Ones for mask_i
+
+ logic ack_in, ack_out;
+
+ logic flush_valid; // flush data out request
+ logic flush_done;
+
+ // Computing next position ==================================================
+ always_comb begin
+ // counting mask_i ones
+ inmask_ones = '0;
+ for (int i = 0 ; i < InW ; i++) begin
+ inmask_ones = inmask_ones + mask_i[i];
+ end
+ end
+
+ logic [PtrW-1:0] pos_with_input;
+
+ always_comb begin
+ pos_next = pos;
+ pos_with_input = pos + PtrW'(inmask_ones);
+
+ unique case ({ack_in, ack_out})
+ 2'b00: pos_next = pos;
+ 2'b01: pos_next = (pos <= OutW) ? '0 : pos - OutW;
+ 2'b10: pos_next = pos_with_input;
+ 2'b11: pos_next = (pos_with_input <= OutW) ? '0 : pos_with_input - OutW;
+ default: pos_next = pos;
+ endcase
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ pos <= '0;
+ end else if (flush_done) begin
+ pos <= '0;
+ end else begin
+ pos <= pos_next;
+ end
+ end
+ //---------------------------------------------------------------------------
+
+ // Leading one detector for mask_i
+ always_comb begin
+ lod_idx = 0;
+ for (int i = InW-1; i >= 0 ; i--) begin
+ if (mask_i[i] == 1'b1) begin
+ lod_idx = $unsigned(i);
+ end
+ end
+ end
+
+ assign ack_in = valid_i & ready_o;
+ assign ack_out = valid_o & ready_i;
+
+ // Data process =============================================================
+ // shiftl : Input data shifted into the current stored position
+ assign shiftl_data = (valid_i) ? Width'(data_i >> lod_idx) << pos : '0;
+ assign shiftl_mask = (valid_i) ? Width'(mask_i >> lod_idx) << pos : '0;
+
+ // concat : Merging stored and shiftl
+ assign concat_data = {{(InW){1'b0}}, stored_data & stored_mask} |
+ (shiftl_data & shiftl_mask);
+ assign concat_mask = {{(InW){1'b0}}, stored_mask} | shiftl_mask;
+
+ logic [Width-1:0] stored_data_next, stored_mask_next;
+
+ always_comb begin
+ unique case ({ack_in, ack_out})
+ 2'b 00: begin
+ stored_data_next = stored_data;
+ stored_mask_next = stored_mask;
+ end
+ 2'b 01: begin
+ // ack_out : shift the amount of OutW
+ stored_data_next = {{OutW{1'b0}}, stored_data[Width-1:OutW]};
+ stored_mask_next = {{OutW{1'b0}}, stored_mask[Width-1:OutW]};
+ end
+ 2'b 10: begin
+ // ack_in : Store concat data
+ stored_data_next = concat_data[0+:Width];
+ stored_mask_next = concat_mask[0+:Width];
+ end
+ 2'b 11: begin
+ // both : shift the concat_data
+ stored_data_next = concat_data[ConcatW-1:OutW];
+ stored_mask_next = concat_mask[ConcatW-1:OutW];
+ end
+ default: begin
+ stored_data_next = stored_data;
+ stored_mask_next = stored_mask;
+ end
+ endcase
+ end
+
+ // Store the data temporary if it doesn't exceed OutW
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ stored_data <= '0;
+ stored_mask <= '0;
+ end else if (flush_done) begin
+ stored_data <= '0;
+ stored_mask <= '0;
+ end else begin
+ stored_data <= stored_data_next;
+ stored_mask <= stored_mask_next;
+ end
+ end
+ //---------------------------------------------------------------------------
+
+ // flush handling
+ typedef enum logic {
+ FlushIdle,
+ FlushSend
+ } flush_st_e;
+ flush_st_e flush_st, flush_st_next;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ flush_st <= FlushIdle;
+ end else begin
+ flush_st <= flush_st_next;
+ end
+ end
+
+ always_comb begin
+ flush_st_next = FlushIdle;
+
+ flush_valid = 1'b0;
+ flush_done = 1'b0;
+
+ unique case (flush_st)
+ FlushIdle: begin
+ if (flush_i) begin
+ flush_st_next = FlushSend;
+ end else begin
+ flush_st_next = FlushIdle;
+ end
+ end
+
+ FlushSend: begin
+ if (pos == '0) begin
+ flush_st_next = FlushIdle;
+
+ flush_valid = 1'b 0;
+ flush_done = 1'b 1;
+ end else begin
+ flush_st_next = FlushSend;
+
+ flush_valid = 1'b 1;
+ flush_done = 1'b 0;
+ end
+ end
+ default: begin
+ flush_st_next = FlushIdle;
+
+ flush_valid = 1'b 0;
+ flush_done = 1'b 0;
+ end
+ endcase
+ end
+
+ assign flush_done_o = flush_done;
+
+
+ // Output signals ===========================================================
+ assign valid_next = (pos >= OutW) ? 1'b 1 : flush_valid;
+
+ // storage space is InW + OutW. So technically, ready_o can be asserted even
+ // if `pos` is greater than OutW. But in order to do that, the logic should
+ // use `inmask_ones` value whether pos+inmask_ones is less than (InW+OutW)
+ // with `valid_i`. It creates a path from `valid_i` --> `ready_o`.
+ // It may create a timing loop in some modules that use `ready_o` to
+ // `valid_i` (which is not a good practice though)
+ assign ready_next = pos <= OutW;
+
+ // Output request
+ assign valid_o = valid_next;
+ assign data_o = stored_data[OutW-1:0];
+ assign mask_o = stored_mask[OutW-1:0];
+
+ // ready_o
+ assign ready_o = ready_next;
+ //---------------------------------------------------------------------------
+
+
+endmodule
diff --git a/EDA-3283/rtl/prim_pkg.sv b/EDA-3283/rtl/prim_pkg.sv
new file mode 100644
index 00000000..ebe38d11
--- /dev/null
+++ b/EDA-3283/rtl/prim_pkg.sv
@@ -0,0 +1,18 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Constants for use in primitives
+//
+// This file is a stop-gap until the DV file list is generated by FuseSoC.
+// Its contents are taken from the file which would be generated by FuseSoC.
+// https://github.com/lowRISC/ibex/issues/893
+
+package prim_pkg;
+
+ // Implementation target specialization
+ typedef enum integer {
+ ImplGeneric,
+ ImplXilinx
+ } impl_e;
+endpackage : prim_pkg
\ No newline at end of file
diff --git a/EDA-3283/rtl/prim_ram_1p_pkg.sv b/EDA-3283/rtl/prim_ram_1p_pkg.sv
new file mode 100644
index 00000000..d4796292
--- /dev/null
+++ b/EDA-3283/rtl/prim_ram_1p_pkg.sv
@@ -0,0 +1,20 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package prim_ram_1p_pkg;
+
+ typedef struct packed {
+ logic cfg_en;
+ logic [3:0] cfg;
+ } cfg_t;
+
+ typedef struct packed {
+ cfg_t ram_cfg; // configuration for ram
+ cfg_t rf_cfg; // configuration for regfile
+ } ram_1p_cfg_t;
+
+ parameter ram_1p_cfg_t RAM_1P_CFG_DEFAULT = '0;
+
+endpackage // prim_ram_1p_pkg
diff --git a/EDA-3283/rtl/prim_secded_inv_39_32_dec.sv b/EDA-3283/rtl/prim_secded_inv_39_32_dec.sv
new file mode 100644
index 00000000..a40a86cd
--- /dev/null
+++ b/EDA-3283/rtl/prim_secded_inv_39_32_dec.sv
@@ -0,0 +1,62 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED decoder generated by util/design/secded_gen.py
+
+module prim_secded_inv_39_32_dec (
+ input [38:0] data_i,
+ output logic [31:0] data_o,
+ output logic [6:0] syndrome_o,
+ output logic [1:0] err_o
+);
+
+ always_comb begin : p_encode
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 39'h2A00000000) & 39'h012606BD25);
+ syndrome_o[1] = ^((data_i ^ 39'h2A00000000) & 39'h02DEBA8050);
+ syndrome_o[2] = ^((data_i ^ 39'h2A00000000) & 39'h04413D89AA);
+ syndrome_o[3] = ^((data_i ^ 39'h2A00000000) & 39'h0831234ED1);
+ syndrome_o[4] = ^((data_i ^ 39'h2A00000000) & 39'h10C2C1323B);
+ syndrome_o[5] = ^((data_i ^ 39'h2A00000000) & 39'h202DCC624C);
+ syndrome_o[6] = ^((data_i ^ 39'h2A00000000) & 39'h4098505586);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h19) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h54) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h61) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h34) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h1a) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h2a) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h38) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h49) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'hd) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h51) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h31) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h68) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h7) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'hb) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h25) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h26) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h46) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h70) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h32) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h2c) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h13) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h23) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h29) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h16) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h52) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+ end
+endmodule : prim_secded_inv_39_32_dec
diff --git a/EDA-3283/rtl/prim_secded_inv_39_32_enc.sv b/EDA-3283/rtl/prim_secded_inv_39_32_enc.sv
new file mode 100644
index 00000000..e59d4879
--- /dev/null
+++ b/EDA-3283/rtl/prim_secded_inv_39_32_enc.sv
@@ -0,0 +1,23 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED encoder generated by util/design/secded_gen.py
+
+module prim_secded_inv_39_32_enc (
+ input [31:0] data_i,
+ output logic [38:0] data_o
+);
+
+ always_comb begin : p_encode
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h002606BD25);
+ data_o[33] = 1'b1 ^ ^(data_o & 39'h00DEBA8050);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00413D89AA);
+ data_o[35] = 1'b1 ^ ^(data_o & 39'h0031234ED1);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h00C2C1323B);
+ data_o[37] = 1'b1 ^ ^(data_o & 39'h002DCC624C);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h0098505586);
+ end
+
+endmodule : prim_secded_inv_39_32_enc
diff --git a/EDA-3283/rtl/prim_secded_inv_64_57_dec.sv b/EDA-3283/rtl/prim_secded_inv_64_57_dec.sv
new file mode 100644
index 00000000..6e34b502
--- /dev/null
+++ b/EDA-3283/rtl/prim_secded_inv_64_57_dec.sv
@@ -0,0 +1,87 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED decoder generated by util/design/secded_gen.py
+
+module prim_secded_inv_64_57_dec (
+ input [63:0] data_i,
+ output logic [56:0] data_o,
+ output logic [6:0] syndrome_o,
+ output logic [1:0] err_o
+);
+
+ always_comb begin : p_encode
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 64'h5400000000000000) & 64'h0303FFF800007FFF);
+ syndrome_o[1] = ^((data_i ^ 64'h5400000000000000) & 64'h057C1FF801FF801F);
+ syndrome_o[2] = ^((data_i ^ 64'h5400000000000000) & 64'h09BDE1F87E0781E1);
+ syndrome_o[3] = ^((data_i ^ 64'h5400000000000000) & 64'h11DEEE3B8E388E22);
+ syndrome_o[4] = ^((data_i ^ 64'h5400000000000000) & 64'h21EF76CDB2C93244);
+ syndrome_o[5] = ^((data_i ^ 64'h5400000000000000) & 64'h41F7BB56D5525488);
+ syndrome_o[6] = ^((data_i ^ 64'h5400000000000000) & 64'h81FBDDA769A46910);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'hd) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h15) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h25) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h19) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h29) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h49) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h31) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h51) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h61) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'he) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h16) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h26) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h46) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h1a) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h2a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h4a) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h32) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h52) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h62) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h1c) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h2c) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h4c) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h34) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h54) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h64) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h38) ^ data_i[31];
+ data_o[32] = (syndrome_o == 7'h58) ^ data_i[32];
+ data_o[33] = (syndrome_o == 7'h68) ^ data_i[33];
+ data_o[34] = (syndrome_o == 7'h70) ^ data_i[34];
+ data_o[35] = (syndrome_o == 7'h1f) ^ data_i[35];
+ data_o[36] = (syndrome_o == 7'h2f) ^ data_i[36];
+ data_o[37] = (syndrome_o == 7'h4f) ^ data_i[37];
+ data_o[38] = (syndrome_o == 7'h37) ^ data_i[38];
+ data_o[39] = (syndrome_o == 7'h57) ^ data_i[39];
+ data_o[40] = (syndrome_o == 7'h67) ^ data_i[40];
+ data_o[41] = (syndrome_o == 7'h3b) ^ data_i[41];
+ data_o[42] = (syndrome_o == 7'h5b) ^ data_i[42];
+ data_o[43] = (syndrome_o == 7'h6b) ^ data_i[43];
+ data_o[44] = (syndrome_o == 7'h73) ^ data_i[44];
+ data_o[45] = (syndrome_o == 7'h3d) ^ data_i[45];
+ data_o[46] = (syndrome_o == 7'h5d) ^ data_i[46];
+ data_o[47] = (syndrome_o == 7'h6d) ^ data_i[47];
+ data_o[48] = (syndrome_o == 7'h75) ^ data_i[48];
+ data_o[49] = (syndrome_o == 7'h79) ^ data_i[49];
+ data_o[50] = (syndrome_o == 7'h3e) ^ data_i[50];
+ data_o[51] = (syndrome_o == 7'h5e) ^ data_i[51];
+ data_o[52] = (syndrome_o == 7'h6e) ^ data_i[52];
+ data_o[53] = (syndrome_o == 7'h76) ^ data_i[53];
+ data_o[54] = (syndrome_o == 7'h7a) ^ data_i[54];
+ data_o[55] = (syndrome_o == 7'h7c) ^ data_i[55];
+ data_o[56] = (syndrome_o == 7'h7f) ^ data_i[56];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+ end
+endmodule : prim_secded_inv_64_57_dec
diff --git a/EDA-3283/rtl/prim_secded_inv_64_57_enc.sv b/EDA-3283/rtl/prim_secded_inv_64_57_enc.sv
new file mode 100644
index 00000000..21caaa6b
--- /dev/null
+++ b/EDA-3283/rtl/prim_secded_inv_64_57_enc.sv
@@ -0,0 +1,23 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED encoder generated by util/design/secded_gen.py
+
+module prim_secded_inv_64_57_enc (
+ input [56:0] data_i,
+ output logic [63:0] data_o
+);
+
+ always_comb begin : p_encode
+ data_o = 64'(data_i);
+ data_o[57] = 1'b0 ^ ^(data_o & 64'h0103FFF800007FFF);
+ data_o[58] = 1'b1 ^ ^(data_o & 64'h017C1FF801FF801F);
+ data_o[59] = 1'b0 ^ ^(data_o & 64'h01BDE1F87E0781E1);
+ data_o[60] = 1'b1 ^ ^(data_o & 64'h01DEEE3B8E388E22);
+ data_o[61] = 1'b0 ^ ^(data_o & 64'h01EF76CDB2C93244);
+ data_o[62] = 1'b1 ^ ^(data_o & 64'h01F7BB56D5525488);
+ data_o[63] = 1'b0 ^ ^(data_o & 64'h01FBDDA769A46910);
+ end
+
+endmodule : prim_secded_inv_64_57_enc
diff --git a/EDA-3283/rtl/prim_secded_pkg.sv b/EDA-3283/rtl/prim_secded_pkg.sv
new file mode 100644
index 00000000..5f227e6e
--- /dev/null
+++ b/EDA-3283/rtl/prim_secded_pkg.sv
@@ -0,0 +1,1778 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SECDED package generated by
+// util/design/secded_gen.py from util/design/data/secded_cfg.hjson
+
+package prim_secded_pkg;
+
+ typedef enum int {
+ SecdedNone,
+ Secded_22_16,
+ Secded_28_22,
+ Secded_39_32,
+ Secded_64_57,
+ Secded_72_64,
+ SecdedHamming_22_16,
+ SecdedHamming_39_32,
+ SecdedHamming_72_64,
+ SecdedHamming_76_68,
+ SecdedInv_22_16,
+ SecdedInv_28_22,
+ SecdedInv_39_32,
+ SecdedInv_64_57,
+ SecdedInv_72_64,
+ SecdedInvHamming_22_16,
+ SecdedInvHamming_39_32,
+ SecdedInvHamming_72_64,
+ SecdedInvHamming_76_68
+ } prim_secded_e;
+
+ function automatic int get_ecc_data_width(prim_secded_e ecc_type);
+ case (ecc_type)
+ Secded_22_16: return 16;
+ Secded_28_22: return 22;
+ Secded_39_32: return 32;
+ Secded_64_57: return 57;
+ Secded_72_64: return 64;
+ SecdedHamming_22_16: return 16;
+ SecdedHamming_39_32: return 32;
+ SecdedHamming_72_64: return 64;
+ SecdedHamming_76_68: return 68;
+ SecdedInv_22_16: return 16;
+ SecdedInv_28_22: return 22;
+ SecdedInv_39_32: return 32;
+ SecdedInv_64_57: return 57;
+ SecdedInv_72_64: return 64;
+ SecdedInvHamming_22_16: return 16;
+ SecdedInvHamming_39_32: return 32;
+ SecdedInvHamming_72_64: return 64;
+ SecdedInvHamming_76_68: return 68;
+ // Return a non-zero width to avoid VCS compile issues
+ default: return 32;
+ endcase
+ endfunction
+
+ function automatic int get_ecc_parity_width(prim_secded_e ecc_type);
+ case (ecc_type)
+ Secded_22_16: return 6;
+ Secded_28_22: return 6;
+ Secded_39_32: return 7;
+ Secded_64_57: return 7;
+ Secded_72_64: return 8;
+ SecdedHamming_22_16: return 6;
+ SecdedHamming_39_32: return 7;
+ SecdedHamming_72_64: return 8;
+ SecdedHamming_76_68: return 8;
+ SecdedInv_22_16: return 6;
+ SecdedInv_28_22: return 6;
+ SecdedInv_39_32: return 7;
+ SecdedInv_64_57: return 7;
+ SecdedInv_72_64: return 8;
+ SecdedInvHamming_22_16: return 6;
+ SecdedInvHamming_39_32: return 7;
+ SecdedInvHamming_72_64: return 8;
+ SecdedInvHamming_76_68: return 8;
+ default: return 0;
+ endcase
+ endfunction
+
+ parameter logic [5:0] Secded2216ZeroEcc = 6'h0;
+ parameter logic [21:0] Secded2216ZeroWord = 22'h0;
+
+ typedef struct packed {
+ logic [15:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_22_16_t;
+
+ parameter logic [5:0] Secded2822ZeroEcc = 6'h0;
+ parameter logic [27:0] Secded2822ZeroWord = 28'h0;
+
+ typedef struct packed {
+ logic [21:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_28_22_t;
+
+ parameter logic [6:0] Secded3932ZeroEcc = 7'h0;
+ parameter logic [38:0] Secded3932ZeroWord = 39'h0;
+
+ typedef struct packed {
+ logic [31:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_39_32_t;
+
+ parameter logic [6:0] Secded6457ZeroEcc = 7'h0;
+ parameter logic [63:0] Secded6457ZeroWord = 64'h0;
+
+ typedef struct packed {
+ logic [56:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_64_57_t;
+
+ parameter logic [7:0] Secded7264ZeroEcc = 8'h0;
+ parameter logic [71:0] Secded7264ZeroWord = 72'h0;
+
+ typedef struct packed {
+ logic [63:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_72_64_t;
+
+ parameter logic [5:0] SecdedHamming2216ZeroEcc = 6'h0;
+ parameter logic [21:0] SecdedHamming2216ZeroWord = 22'h0;
+
+ typedef struct packed {
+ logic [15:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_hamming_22_16_t;
+
+ parameter logic [6:0] SecdedHamming3932ZeroEcc = 7'h0;
+ parameter logic [38:0] SecdedHamming3932ZeroWord = 39'h0;
+
+ typedef struct packed {
+ logic [31:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_hamming_39_32_t;
+
+ parameter logic [7:0] SecdedHamming7264ZeroEcc = 8'h0;
+ parameter logic [71:0] SecdedHamming7264ZeroWord = 72'h0;
+
+ typedef struct packed {
+ logic [63:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_hamming_72_64_t;
+
+ parameter logic [7:0] SecdedHamming7668ZeroEcc = 8'h0;
+ parameter logic [75:0] SecdedHamming7668ZeroWord = 76'h0;
+
+ typedef struct packed {
+ logic [67:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_hamming_76_68_t;
+
+ parameter logic [5:0] SecdedInv2216ZeroEcc = 6'h2A;
+ parameter logic [21:0] SecdedInv2216ZeroWord = 22'h2A0000;
+
+ typedef struct packed {
+ logic [15:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_22_16_t;
+
+ parameter logic [5:0] SecdedInv2822ZeroEcc = 6'h2A;
+ parameter logic [27:0] SecdedInv2822ZeroWord = 28'hA800000;
+
+ typedef struct packed {
+ logic [21:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_28_22_t;
+
+ parameter logic [6:0] SecdedInv3932ZeroEcc = 7'h2A;
+ parameter logic [38:0] SecdedInv3932ZeroWord = 39'h2A00000000;
+
+ typedef struct packed {
+ logic [31:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_39_32_t;
+
+ parameter logic [6:0] SecdedInv6457ZeroEcc = 7'h2A;
+ parameter logic [63:0] SecdedInv6457ZeroWord = 64'h5400000000000000;
+
+ typedef struct packed {
+ logic [56:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_64_57_t;
+
+ parameter logic [7:0] SecdedInv7264ZeroEcc = 8'hAA;
+ parameter logic [71:0] SecdedInv7264ZeroWord = 72'hAA0000000000000000;
+
+ typedef struct packed {
+ logic [63:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_72_64_t;
+
+ parameter logic [5:0] SecdedInvHamming2216ZeroEcc = 6'h2A;
+ parameter logic [21:0] SecdedInvHamming2216ZeroWord = 22'h2A0000;
+
+ typedef struct packed {
+ logic [15:0] data;
+ logic [5:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_hamming_22_16_t;
+
+ parameter logic [6:0] SecdedInvHamming3932ZeroEcc = 7'h2A;
+ parameter logic [38:0] SecdedInvHamming3932ZeroWord = 39'h2A00000000;
+
+ typedef struct packed {
+ logic [31:0] data;
+ logic [6:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_hamming_39_32_t;
+
+ parameter logic [7:0] SecdedInvHamming7264ZeroEcc = 8'hAA;
+ parameter logic [71:0] SecdedInvHamming7264ZeroWord = 72'hAA0000000000000000;
+
+ typedef struct packed {
+ logic [63:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_hamming_72_64_t;
+
+ parameter logic [7:0] SecdedInvHamming7668ZeroEcc = 8'hAA;
+ parameter logic [75:0] SecdedInvHamming7668ZeroWord = 76'hAA00000000000000000;
+
+ typedef struct packed {
+ logic [67:0] data;
+ logic [7:0] syndrome;
+ logic [1:0] err;
+ } secded_inv_hamming_76_68_t;
+
+ function automatic logic [21:0]
+ prim_secded_22_16_enc (logic [15:0] data_i);
+ logic [21:0] data_o;
+ data_o = 22'(data_i);
+ data_o[16] = 1'b0 ^ ^(data_o & 22'h00496E);
+ data_o[17] = 1'b0 ^ ^(data_o & 22'h00F20B);
+ data_o[18] = 1'b0 ^ ^(data_o & 22'h008ED8);
+ data_o[19] = 1'b0 ^ ^(data_o & 22'h007714);
+ data_o[20] = 1'b0 ^ ^(data_o & 22'h00ACA5);
+ data_o[21] = 1'b0 ^ ^(data_o & 22'h0011F3);
+ return data_o;
+ endfunction
+
+ function automatic secded_22_16_t
+ prim_secded_22_16_dec (logic [21:0] data_i);
+ logic [15:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_22_16_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 22'h01496E);
+ syndrome_o[1] = ^(data_i & 22'h02F20B);
+ syndrome_o[2] = ^(data_i & 22'h048ED8);
+ syndrome_o[3] = ^(data_i & 22'h087714);
+ syndrome_o[4] = ^(data_i & 22'h10ACA5);
+ syndrome_o[5] = ^(data_i & 22'h2011F3);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h32) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'h23) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h19) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h7) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'h2c) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h31) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h25) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h34) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h29) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'he) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'h1c) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h15) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h2a) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h1a) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'hb) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h16) ^ data_i[15];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [27:0]
+ prim_secded_28_22_enc (logic [21:0] data_i);
+ logic [27:0] data_o;
+ data_o = 28'(data_i);
+ data_o[22] = 1'b0 ^ ^(data_o & 28'h03003FF);
+ data_o[23] = 1'b0 ^ ^(data_o & 28'h010FC0F);
+ data_o[24] = 1'b0 ^ ^(data_o & 28'h0271C71);
+ data_o[25] = 1'b0 ^ ^(data_o & 28'h03B6592);
+ data_o[26] = 1'b0 ^ ^(data_o & 28'h03DAAA4);
+ data_o[27] = 1'b0 ^ ^(data_o & 28'h03ED348);
+ return data_o;
+ endfunction
+
+ function automatic secded_28_22_t
+ prim_secded_28_22_dec (logic [27:0] data_i);
+ logic [21:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_28_22_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 28'h07003FF);
+ syndrome_o[1] = ^(data_i & 28'h090FC0F);
+ syndrome_o[2] = ^(data_i & 28'h1271C71);
+ syndrome_o[3] = ^(data_i & 28'h23B6592);
+ syndrome_o[4] = ^(data_i & 28'h43DAAA4);
+ syndrome_o[5] = ^(data_i & 28'h83ED348);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'hd) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h25) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h19) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h29) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'h31) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'he) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h16) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h26) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h1a) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'h2a) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h32) ^ data_i[15];
+ data_o[16] = (syndrome_o == 6'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 6'h2c) ^ data_i[17];
+ data_o[18] = (syndrome_o == 6'h34) ^ data_i[18];
+ data_o[19] = (syndrome_o == 6'h38) ^ data_i[19];
+ data_o[20] = (syndrome_o == 6'h3b) ^ data_i[20];
+ data_o[21] = (syndrome_o == 6'h3d) ^ data_i[21];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [38:0]
+ prim_secded_39_32_enc (logic [31:0] data_i);
+ logic [38:0] data_o;
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h002606BD25);
+ data_o[33] = 1'b0 ^ ^(data_o & 39'h00DEBA8050);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00413D89AA);
+ data_o[35] = 1'b0 ^ ^(data_o & 39'h0031234ED1);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h00C2C1323B);
+ data_o[37] = 1'b0 ^ ^(data_o & 39'h002DCC624C);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h0098505586);
+ return data_o;
+ endfunction
+
+ function automatic secded_39_32_t
+ prim_secded_39_32_dec (logic [38:0] data_i);
+ logic [31:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_39_32_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 39'h012606BD25);
+ syndrome_o[1] = ^(data_i & 39'h02DEBA8050);
+ syndrome_o[2] = ^(data_i & 39'h04413D89AA);
+ syndrome_o[3] = ^(data_i & 39'h0831234ED1);
+ syndrome_o[4] = ^(data_i & 39'h10C2C1323B);
+ syndrome_o[5] = ^(data_i & 39'h202DCC624C);
+ syndrome_o[6] = ^(data_i & 39'h4098505586);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h19) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h54) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h61) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h34) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h1a) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h2a) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h38) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h49) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'hd) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h51) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h31) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h68) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h7) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'hb) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h25) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h26) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h46) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h70) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h32) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h2c) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h13) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h23) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h29) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h16) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h52) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [63:0]
+ prim_secded_64_57_enc (logic [56:0] data_i);
+ logic [63:0] data_o;
+ data_o = 64'(data_i);
+ data_o[57] = 1'b0 ^ ^(data_o & 64'h0103FFF800007FFF);
+ data_o[58] = 1'b0 ^ ^(data_o & 64'h017C1FF801FF801F);
+ data_o[59] = 1'b0 ^ ^(data_o & 64'h01BDE1F87E0781E1);
+ data_o[60] = 1'b0 ^ ^(data_o & 64'h01DEEE3B8E388E22);
+ data_o[61] = 1'b0 ^ ^(data_o & 64'h01EF76CDB2C93244);
+ data_o[62] = 1'b0 ^ ^(data_o & 64'h01F7BB56D5525488);
+ data_o[63] = 1'b0 ^ ^(data_o & 64'h01FBDDA769A46910);
+ return data_o;
+ endfunction
+
+ function automatic secded_64_57_t
+ prim_secded_64_57_dec (logic [63:0] data_i);
+ logic [56:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_64_57_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 64'h0303FFF800007FFF);
+ syndrome_o[1] = ^(data_i & 64'h057C1FF801FF801F);
+ syndrome_o[2] = ^(data_i & 64'h09BDE1F87E0781E1);
+ syndrome_o[3] = ^(data_i & 64'h11DEEE3B8E388E22);
+ syndrome_o[4] = ^(data_i & 64'h21EF76CDB2C93244);
+ syndrome_o[5] = ^(data_i & 64'h41F7BB56D5525488);
+ syndrome_o[6] = ^(data_i & 64'h81FBDDA769A46910);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'hd) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h15) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h25) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h19) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h29) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h49) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h31) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h51) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h61) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'he) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h16) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h26) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h46) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h1a) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h2a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h4a) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h32) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h52) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h62) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h1c) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h2c) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h4c) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h34) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h54) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h64) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h38) ^ data_i[31];
+ data_o[32] = (syndrome_o == 7'h58) ^ data_i[32];
+ data_o[33] = (syndrome_o == 7'h68) ^ data_i[33];
+ data_o[34] = (syndrome_o == 7'h70) ^ data_i[34];
+ data_o[35] = (syndrome_o == 7'h1f) ^ data_i[35];
+ data_o[36] = (syndrome_o == 7'h2f) ^ data_i[36];
+ data_o[37] = (syndrome_o == 7'h4f) ^ data_i[37];
+ data_o[38] = (syndrome_o == 7'h37) ^ data_i[38];
+ data_o[39] = (syndrome_o == 7'h57) ^ data_i[39];
+ data_o[40] = (syndrome_o == 7'h67) ^ data_i[40];
+ data_o[41] = (syndrome_o == 7'h3b) ^ data_i[41];
+ data_o[42] = (syndrome_o == 7'h5b) ^ data_i[42];
+ data_o[43] = (syndrome_o == 7'h6b) ^ data_i[43];
+ data_o[44] = (syndrome_o == 7'h73) ^ data_i[44];
+ data_o[45] = (syndrome_o == 7'h3d) ^ data_i[45];
+ data_o[46] = (syndrome_o == 7'h5d) ^ data_i[46];
+ data_o[47] = (syndrome_o == 7'h6d) ^ data_i[47];
+ data_o[48] = (syndrome_o == 7'h75) ^ data_i[48];
+ data_o[49] = (syndrome_o == 7'h79) ^ data_i[49];
+ data_o[50] = (syndrome_o == 7'h3e) ^ data_i[50];
+ data_o[51] = (syndrome_o == 7'h5e) ^ data_i[51];
+ data_o[52] = (syndrome_o == 7'h6e) ^ data_i[52];
+ data_o[53] = (syndrome_o == 7'h76) ^ data_i[53];
+ data_o[54] = (syndrome_o == 7'h7a) ^ data_i[54];
+ data_o[55] = (syndrome_o == 7'h7c) ^ data_i[55];
+ data_o[56] = (syndrome_o == 7'h7f) ^ data_i[56];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [71:0]
+ prim_secded_72_64_enc (logic [63:0] data_i);
+ logic [71:0] data_o;
+ data_o = 72'(data_i);
+ data_o[64] = 1'b0 ^ ^(data_o & 72'h00B9000000001FFFFF);
+ data_o[65] = 1'b0 ^ ^(data_o & 72'h005E00000FFFE0003F);
+ data_o[66] = 1'b0 ^ ^(data_o & 72'h0067003FF003E007C1);
+ data_o[67] = 1'b0 ^ ^(data_o & 72'h00CD0FC0F03C207842);
+ data_o[68] = 1'b0 ^ ^(data_o & 72'h00B671C711C4438884);
+ data_o[69] = 1'b0 ^ ^(data_o & 72'h00B5B65926488C9108);
+ data_o[70] = 1'b0 ^ ^(data_o & 72'h00CBDAAA4A91152210);
+ data_o[71] = 1'b0 ^ ^(data_o & 72'h007AED348D221A4420);
+ return data_o;
+ endfunction
+
+ function automatic secded_72_64_t
+ prim_secded_72_64_dec (logic [71:0] data_i);
+ logic [63:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_72_64_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 72'h01B9000000001FFFFF);
+ syndrome_o[1] = ^(data_i & 72'h025E00000FFFE0003F);
+ syndrome_o[2] = ^(data_i & 72'h0467003FF003E007C1);
+ syndrome_o[3] = ^(data_i & 72'h08CD0FC0F03C207842);
+ syndrome_o[4] = ^(data_i & 72'h10B671C711C4438884);
+ syndrome_o[5] = ^(data_i & 72'h20B5B65926488C9108);
+ syndrome_o[6] = ^(data_i & 72'h40CBDAAA4A91152210);
+ syndrome_o[7] = ^(data_i & 72'h807AED348D221A4420);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h83) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'hd) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h15) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h25) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h45) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h85) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h19) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h29) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h49) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h89) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h31) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h51) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h91) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h61) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'ha1) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'hc1) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h16) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h26) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h46) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h86) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'h1a) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'h2a) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'h8a) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'h32) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'h52) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'h92) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'h62) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha2) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'hc2) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'h1c) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'h2c) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'h4c) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'h8c) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'h34) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'h54) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'h94) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'h64) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'ha4) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hc4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'h38) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'h58) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'h98) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'h68) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'ha8) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hc8) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'h70) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hb0) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hd0) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'he0) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'h6d) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hd6) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'h3e) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hcb) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hb3) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hb5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hce) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'h79) ^ data_i[63];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [21:0]
+ prim_secded_hamming_22_16_enc (logic [15:0] data_i);
+ logic [21:0] data_o;
+ data_o = 22'(data_i);
+ data_o[16] = 1'b0 ^ ^(data_o & 22'h00AD5B);
+ data_o[17] = 1'b0 ^ ^(data_o & 22'h00366D);
+ data_o[18] = 1'b0 ^ ^(data_o & 22'h00C78E);
+ data_o[19] = 1'b0 ^ ^(data_o & 22'h0007F0);
+ data_o[20] = 1'b0 ^ ^(data_o & 22'h00F800);
+ data_o[21] = 1'b0 ^ ^(data_o & 22'h1FFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_hamming_22_16_t
+ prim_secded_hamming_22_16_dec (logic [21:0] data_i);
+ logic [15:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_hamming_22_16_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 22'h01AD5B);
+ syndrome_o[1] = ^(data_i & 22'h02366D);
+ syndrome_o[2] = ^(data_i & 22'h04C78E);
+ syndrome_o[3] = ^(data_i & 22'h0807F0);
+ syndrome_o[4] = ^(data_i & 22'h10F800);
+ syndrome_o[5] = ^(data_i & 22'h3FFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h23) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'h25) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h26) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h27) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'h29) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h2a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h2b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h2c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h2d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'h2e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'h2f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h31) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h32) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h33) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'h34) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h35) ^ data_i[15];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[5];
+ err_o[1] = |syndrome_o[4:0] & ~syndrome_o[5];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [38:0]
+ prim_secded_hamming_39_32_enc (logic [31:0] data_i);
+ logic [38:0] data_o;
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h0056AAAD5B);
+ data_o[33] = 1'b0 ^ ^(data_o & 39'h009B33366D);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00E3C3C78E);
+ data_o[35] = 1'b0 ^ ^(data_o & 39'h0003FC07F0);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h0003FFF800);
+ data_o[37] = 1'b0 ^ ^(data_o & 39'h00FC000000);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h3FFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_hamming_39_32_t
+ prim_secded_hamming_39_32_dec (logic [38:0] data_i);
+ logic [31:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_hamming_39_32_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 39'h0156AAAD5B);
+ syndrome_o[1] = ^(data_i & 39'h029B33366D);
+ syndrome_o[2] = ^(data_i & 39'h04E3C3C78E);
+ syndrome_o[3] = ^(data_i & 39'h0803FC07F0);
+ syndrome_o[4] = ^(data_i & 39'h1003FFF800);
+ syndrome_o[5] = ^(data_i & 39'h20FC000000);
+ syndrome_o[6] = ^(data_i & 39'h7FFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h43) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h45) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h46) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h47) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h49) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h4a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h4b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h4d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h4e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h4f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h51) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h52) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h53) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h54) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h55) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h56) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h57) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h58) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h59) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h5a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h5b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h5c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h5d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h5e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h5f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h61) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h63) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h64) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h65) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h66) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[6];
+ err_o[1] = |syndrome_o[5:0] & ~syndrome_o[6];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [71:0]
+ prim_secded_hamming_72_64_enc (logic [63:0] data_i);
+ logic [71:0] data_o;
+ data_o = 72'(data_i);
+ data_o[64] = 1'b0 ^ ^(data_o & 72'h00AB55555556AAAD5B);
+ data_o[65] = 1'b0 ^ ^(data_o & 72'h00CD9999999B33366D);
+ data_o[66] = 1'b0 ^ ^(data_o & 72'h00F1E1E1E1E3C3C78E);
+ data_o[67] = 1'b0 ^ ^(data_o & 72'h0001FE01FE03FC07F0);
+ data_o[68] = 1'b0 ^ ^(data_o & 72'h0001FFFE0003FFF800);
+ data_o[69] = 1'b0 ^ ^(data_o & 72'h0001FFFFFFFC000000);
+ data_o[70] = 1'b0 ^ ^(data_o & 72'h00FE00000000000000);
+ data_o[71] = 1'b0 ^ ^(data_o & 72'h7FFFFFFFFFFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_hamming_72_64_t
+ prim_secded_hamming_72_64_dec (logic [71:0] data_i);
+ logic [63:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_hamming_72_64_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 72'h01AB55555556AAAD5B);
+ syndrome_o[1] = ^(data_i & 72'h02CD9999999B33366D);
+ syndrome_o[2] = ^(data_i & 72'h04F1E1E1E1E3C3C78E);
+ syndrome_o[3] = ^(data_i & 72'h0801FE01FE03FC07F0);
+ syndrome_o[4] = ^(data_i & 72'h1001FFFE0003FFF800);
+ syndrome_o[5] = ^(data_i & 72'h2001FFFFFFFC000000);
+ syndrome_o[6] = ^(data_i & 72'h40FE00000000000000);
+ syndrome_o[7] = ^(data_i & 72'hFFFFFFFFFFFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h83) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'h85) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h86) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h87) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h89) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h8a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'h8b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h8c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h8d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h8e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h8f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h91) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h92) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h93) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h94) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h95) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h96) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h97) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h98) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'h99) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'h9a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'h9b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h9c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h9d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h9e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h9f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'ha1) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'ha2) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'ha3) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'ha4) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'ha5) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'ha6) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'ha7) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'ha8) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha9) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'haa) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'hab) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'hac) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'had) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'hae) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'haf) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'hb0) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'hb1) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'hb2) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'hb3) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hb4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'hb5) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'hb6) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'hb7) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'hb8) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'hb9) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hba) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'hbb) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hbc) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hbd) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'hbe) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'hbf) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hc1) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'hc2) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hc3) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hc4) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hc5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hc6) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'hc7) ^ data_i[63];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[7];
+ err_o[1] = |syndrome_o[6:0] & ~syndrome_o[7];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [75:0]
+ prim_secded_hamming_76_68_enc (logic [67:0] data_i);
+ logic [75:0] data_o;
+ data_o = 76'(data_i);
+ data_o[68] = 1'b0 ^ ^(data_o & 76'h00AAB55555556AAAD5B);
+ data_o[69] = 1'b0 ^ ^(data_o & 76'h00CCD9999999B33366D);
+ data_o[70] = 1'b0 ^ ^(data_o & 76'h000F1E1E1E1E3C3C78E);
+ data_o[71] = 1'b0 ^ ^(data_o & 76'h00F01FE01FE03FC07F0);
+ data_o[72] = 1'b0 ^ ^(data_o & 76'h00001FFFE0003FFF800);
+ data_o[73] = 1'b0 ^ ^(data_o & 76'h00001FFFFFFFC000000);
+ data_o[74] = 1'b0 ^ ^(data_o & 76'h00FFE00000000000000);
+ data_o[75] = 1'b0 ^ ^(data_o & 76'h7FFFFFFFFFFFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_hamming_76_68_t
+ prim_secded_hamming_76_68_dec (logic [75:0] data_i);
+ logic [67:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_hamming_76_68_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^(data_i & 76'h01AAB55555556AAAD5B);
+ syndrome_o[1] = ^(data_i & 76'h02CCD9999999B33366D);
+ syndrome_o[2] = ^(data_i & 76'h040F1E1E1E1E3C3C78E);
+ syndrome_o[3] = ^(data_i & 76'h08F01FE01FE03FC07F0);
+ syndrome_o[4] = ^(data_i & 76'h10001FFFE0003FFF800);
+ syndrome_o[5] = ^(data_i & 76'h20001FFFFFFFC000000);
+ syndrome_o[6] = ^(data_i & 76'h40FFE00000000000000);
+ syndrome_o[7] = ^(data_i & 76'hFFFFFFFFFFFFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h83) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'h85) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h86) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h87) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h89) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h8a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'h8b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h8c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h8d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h8e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h8f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h91) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h92) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h93) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h94) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h95) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h96) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h97) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h98) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'h99) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'h9a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'h9b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h9c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h9d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h9e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h9f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'ha1) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'ha2) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'ha3) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'ha4) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'ha5) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'ha6) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'ha7) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'ha8) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha9) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'haa) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'hab) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'hac) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'had) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'hae) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'haf) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'hb0) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'hb1) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'hb2) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'hb3) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hb4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'hb5) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'hb6) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'hb7) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'hb8) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'hb9) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hba) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'hbb) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hbc) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hbd) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'hbe) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'hbf) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hc1) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'hc2) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hc3) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hc4) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hc5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hc6) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'hc7) ^ data_i[63];
+ data_o[64] = (syndrome_o == 8'hc8) ^ data_i[64];
+ data_o[65] = (syndrome_o == 8'hc9) ^ data_i[65];
+ data_o[66] = (syndrome_o == 8'hca) ^ data_i[66];
+ data_o[67] = (syndrome_o == 8'hcb) ^ data_i[67];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[7];
+ err_o[1] = |syndrome_o[6:0] & ~syndrome_o[7];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [21:0]
+ prim_secded_inv_22_16_enc (logic [15:0] data_i);
+ logic [21:0] data_o;
+ data_o = 22'(data_i);
+ data_o[16] = 1'b0 ^ ^(data_o & 22'h00496E);
+ data_o[17] = 1'b1 ^ ^(data_o & 22'h00F20B);
+ data_o[18] = 1'b0 ^ ^(data_o & 22'h008ED8);
+ data_o[19] = 1'b1 ^ ^(data_o & 22'h007714);
+ data_o[20] = 1'b0 ^ ^(data_o & 22'h00ACA5);
+ data_o[21] = 1'b1 ^ ^(data_o & 22'h0011F3);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_22_16_t
+ prim_secded_inv_22_16_dec (logic [21:0] data_i);
+ logic [15:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_22_16_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 22'h2A0000) & 22'h01496E);
+ syndrome_o[1] = ^((data_i ^ 22'h2A0000) & 22'h02F20B);
+ syndrome_o[2] = ^((data_i ^ 22'h2A0000) & 22'h048ED8);
+ syndrome_o[3] = ^((data_i ^ 22'h2A0000) & 22'h087714);
+ syndrome_o[4] = ^((data_i ^ 22'h2A0000) & 22'h10ACA5);
+ syndrome_o[5] = ^((data_i ^ 22'h2A0000) & 22'h2011F3);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h32) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'h23) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h19) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h7) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'h2c) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h31) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h25) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h34) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h29) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'he) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'h1c) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h15) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h2a) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h1a) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'hb) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h16) ^ data_i[15];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [27:0]
+ prim_secded_inv_28_22_enc (logic [21:0] data_i);
+ logic [27:0] data_o;
+ data_o = 28'(data_i);
+ data_o[22] = 1'b0 ^ ^(data_o & 28'h03003FF);
+ data_o[23] = 1'b1 ^ ^(data_o & 28'h010FC0F);
+ data_o[24] = 1'b0 ^ ^(data_o & 28'h0271C71);
+ data_o[25] = 1'b1 ^ ^(data_o & 28'h03B6592);
+ data_o[26] = 1'b0 ^ ^(data_o & 28'h03DAAA4);
+ data_o[27] = 1'b1 ^ ^(data_o & 28'h03ED348);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_28_22_t
+ prim_secded_inv_28_22_dec (logic [27:0] data_i);
+ logic [21:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_28_22_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 28'hA800000) & 28'h07003FF);
+ syndrome_o[1] = ^((data_i ^ 28'hA800000) & 28'h090FC0F);
+ syndrome_o[2] = ^((data_i ^ 28'hA800000) & 28'h1271C71);
+ syndrome_o[3] = ^((data_i ^ 28'hA800000) & 28'h23B6592);
+ syndrome_o[4] = ^((data_i ^ 28'hA800000) & 28'h43DAAA4);
+ syndrome_o[5] = ^((data_i ^ 28'hA800000) & 28'h83ED348);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'hd) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h25) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h19) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h29) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'h31) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'he) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h16) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h26) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h1a) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'h2a) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h32) ^ data_i[15];
+ data_o[16] = (syndrome_o == 6'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 6'h2c) ^ data_i[17];
+ data_o[18] = (syndrome_o == 6'h34) ^ data_i[18];
+ data_o[19] = (syndrome_o == 6'h38) ^ data_i[19];
+ data_o[20] = (syndrome_o == 6'h3b) ^ data_i[20];
+ data_o[21] = (syndrome_o == 6'h3d) ^ data_i[21];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [38:0]
+ prim_secded_inv_39_32_enc (logic [31:0] data_i);
+ logic [38:0] data_o;
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h002606BD25);
+ data_o[33] = 1'b1 ^ ^(data_o & 39'h00DEBA8050);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00413D89AA);
+ data_o[35] = 1'b1 ^ ^(data_o & 39'h0031234ED1);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h00C2C1323B);
+ data_o[37] = 1'b1 ^ ^(data_o & 39'h002DCC624C);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h0098505586);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_39_32_t
+ prim_secded_inv_39_32_dec (logic [38:0] data_i);
+ logic [31:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_39_32_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 39'h2A00000000) & 39'h012606BD25);
+ syndrome_o[1] = ^((data_i ^ 39'h2A00000000) & 39'h02DEBA8050);
+ syndrome_o[2] = ^((data_i ^ 39'h2A00000000) & 39'h04413D89AA);
+ syndrome_o[3] = ^((data_i ^ 39'h2A00000000) & 39'h0831234ED1);
+ syndrome_o[4] = ^((data_i ^ 39'h2A00000000) & 39'h10C2C1323B);
+ syndrome_o[5] = ^((data_i ^ 39'h2A00000000) & 39'h202DCC624C);
+ syndrome_o[6] = ^((data_i ^ 39'h2A00000000) & 39'h4098505586);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h19) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h54) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h61) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h34) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h1a) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h15) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h2a) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h38) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h49) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'hd) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h51) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h31) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h68) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h7) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h1c) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'hb) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h25) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h26) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h46) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h70) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h32) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h2c) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h13) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h23) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h29) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h16) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h52) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [63:0]
+ prim_secded_inv_64_57_enc (logic [56:0] data_i);
+ logic [63:0] data_o;
+ data_o = 64'(data_i);
+ data_o[57] = 1'b0 ^ ^(data_o & 64'h0103FFF800007FFF);
+ data_o[58] = 1'b1 ^ ^(data_o & 64'h017C1FF801FF801F);
+ data_o[59] = 1'b0 ^ ^(data_o & 64'h01BDE1F87E0781E1);
+ data_o[60] = 1'b1 ^ ^(data_o & 64'h01DEEE3B8E388E22);
+ data_o[61] = 1'b0 ^ ^(data_o & 64'h01EF76CDB2C93244);
+ data_o[62] = 1'b1 ^ ^(data_o & 64'h01F7BB56D5525488);
+ data_o[63] = 1'b0 ^ ^(data_o & 64'h01FBDDA769A46910);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_64_57_t
+ prim_secded_inv_64_57_dec (logic [63:0] data_i);
+ logic [56:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_64_57_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 64'h5400000000000000) & 64'h0303FFF800007FFF);
+ syndrome_o[1] = ^((data_i ^ 64'h5400000000000000) & 64'h057C1FF801FF801F);
+ syndrome_o[2] = ^((data_i ^ 64'h5400000000000000) & 64'h09BDE1F87E0781E1);
+ syndrome_o[3] = ^((data_i ^ 64'h5400000000000000) & 64'h11DEEE3B8E388E22);
+ syndrome_o[4] = ^((data_i ^ 64'h5400000000000000) & 64'h21EF76CDB2C93244);
+ syndrome_o[5] = ^((data_i ^ 64'h5400000000000000) & 64'h41F7BB56D5525488);
+ syndrome_o[6] = ^((data_i ^ 64'h5400000000000000) & 64'h81FBDDA769A46910);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'hd) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h15) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h25) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h45) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h19) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h29) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h49) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h31) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h51) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h61) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'he) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h16) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h26) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h46) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h1a) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h2a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h4a) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h32) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h52) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h62) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h1c) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h2c) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h4c) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h34) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h54) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h64) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h38) ^ data_i[31];
+ data_o[32] = (syndrome_o == 7'h58) ^ data_i[32];
+ data_o[33] = (syndrome_o == 7'h68) ^ data_i[33];
+ data_o[34] = (syndrome_o == 7'h70) ^ data_i[34];
+ data_o[35] = (syndrome_o == 7'h1f) ^ data_i[35];
+ data_o[36] = (syndrome_o == 7'h2f) ^ data_i[36];
+ data_o[37] = (syndrome_o == 7'h4f) ^ data_i[37];
+ data_o[38] = (syndrome_o == 7'h37) ^ data_i[38];
+ data_o[39] = (syndrome_o == 7'h57) ^ data_i[39];
+ data_o[40] = (syndrome_o == 7'h67) ^ data_i[40];
+ data_o[41] = (syndrome_o == 7'h3b) ^ data_i[41];
+ data_o[42] = (syndrome_o == 7'h5b) ^ data_i[42];
+ data_o[43] = (syndrome_o == 7'h6b) ^ data_i[43];
+ data_o[44] = (syndrome_o == 7'h73) ^ data_i[44];
+ data_o[45] = (syndrome_o == 7'h3d) ^ data_i[45];
+ data_o[46] = (syndrome_o == 7'h5d) ^ data_i[46];
+ data_o[47] = (syndrome_o == 7'h6d) ^ data_i[47];
+ data_o[48] = (syndrome_o == 7'h75) ^ data_i[48];
+ data_o[49] = (syndrome_o == 7'h79) ^ data_i[49];
+ data_o[50] = (syndrome_o == 7'h3e) ^ data_i[50];
+ data_o[51] = (syndrome_o == 7'h5e) ^ data_i[51];
+ data_o[52] = (syndrome_o == 7'h6e) ^ data_i[52];
+ data_o[53] = (syndrome_o == 7'h76) ^ data_i[53];
+ data_o[54] = (syndrome_o == 7'h7a) ^ data_i[54];
+ data_o[55] = (syndrome_o == 7'h7c) ^ data_i[55];
+ data_o[56] = (syndrome_o == 7'h7f) ^ data_i[56];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [71:0]
+ prim_secded_inv_72_64_enc (logic [63:0] data_i);
+ logic [71:0] data_o;
+ data_o = 72'(data_i);
+ data_o[64] = 1'b0 ^ ^(data_o & 72'h00B9000000001FFFFF);
+ data_o[65] = 1'b1 ^ ^(data_o & 72'h005E00000FFFE0003F);
+ data_o[66] = 1'b0 ^ ^(data_o & 72'h0067003FF003E007C1);
+ data_o[67] = 1'b1 ^ ^(data_o & 72'h00CD0FC0F03C207842);
+ data_o[68] = 1'b0 ^ ^(data_o & 72'h00B671C711C4438884);
+ data_o[69] = 1'b1 ^ ^(data_o & 72'h00B5B65926488C9108);
+ data_o[70] = 1'b0 ^ ^(data_o & 72'h00CBDAAA4A91152210);
+ data_o[71] = 1'b1 ^ ^(data_o & 72'h007AED348D221A4420);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_72_64_t
+ prim_secded_inv_72_64_dec (logic [71:0] data_i);
+ logic [63:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_72_64_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 72'hAA0000000000000000) & 72'h01B9000000001FFFFF);
+ syndrome_o[1] = ^((data_i ^ 72'hAA0000000000000000) & 72'h025E00000FFFE0003F);
+ syndrome_o[2] = ^((data_i ^ 72'hAA0000000000000000) & 72'h0467003FF003E007C1);
+ syndrome_o[3] = ^((data_i ^ 72'hAA0000000000000000) & 72'h08CD0FC0F03C207842);
+ syndrome_o[4] = ^((data_i ^ 72'hAA0000000000000000) & 72'h10B671C711C4438884);
+ syndrome_o[5] = ^((data_i ^ 72'hAA0000000000000000) & 72'h20B5B65926488C9108);
+ syndrome_o[6] = ^((data_i ^ 72'hAA0000000000000000) & 72'h40CBDAAA4A91152210);
+ syndrome_o[7] = ^((data_i ^ 72'hAA0000000000000000) & 72'h807AED348D221A4420);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h7) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'hb) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h13) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h23) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h43) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h83) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'hd) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h15) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h25) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h45) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h85) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h19) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h29) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h49) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h89) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h31) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h51) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h91) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h61) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'ha1) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'hc1) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'he) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h16) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h26) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h46) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h86) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'h1a) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'h2a) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'h4a) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'h8a) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'h32) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'h52) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'h92) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'h62) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha2) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'hc2) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'h1c) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'h2c) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'h4c) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'h8c) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'h34) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'h54) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'h94) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'h64) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'ha4) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hc4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'h38) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'h58) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'h98) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'h68) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'ha8) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hc8) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'h70) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hb0) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hd0) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'he0) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'h6d) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hd6) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'h3e) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hcb) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hb3) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hb5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hce) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'h79) ^ data_i[63];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = ^syndrome_o;
+ err_o[1] = ~err_o[0] & (|syndrome_o);
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [21:0]
+ prim_secded_inv_hamming_22_16_enc (logic [15:0] data_i);
+ logic [21:0] data_o;
+ data_o = 22'(data_i);
+ data_o[16] = 1'b0 ^ ^(data_o & 22'h00AD5B);
+ data_o[17] = 1'b1 ^ ^(data_o & 22'h00366D);
+ data_o[18] = 1'b0 ^ ^(data_o & 22'h00C78E);
+ data_o[19] = 1'b1 ^ ^(data_o & 22'h0007F0);
+ data_o[20] = 1'b0 ^ ^(data_o & 22'h00F800);
+ data_o[21] = 1'b1 ^ ^(data_o & 22'h1FFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_hamming_22_16_t
+ prim_secded_inv_hamming_22_16_dec (logic [21:0] data_i);
+ logic [15:0] data_o;
+ logic [5:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_hamming_22_16_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 22'h2A0000) & 22'h01AD5B);
+ syndrome_o[1] = ^((data_i ^ 22'h2A0000) & 22'h02366D);
+ syndrome_o[2] = ^((data_i ^ 22'h2A0000) & 22'h04C78E);
+ syndrome_o[3] = ^((data_i ^ 22'h2A0000) & 22'h0807F0);
+ syndrome_o[4] = ^((data_i ^ 22'h2A0000) & 22'h10F800);
+ syndrome_o[5] = ^((data_i ^ 22'h2A0000) & 22'h3FFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 6'h23) ^ data_i[0];
+ data_o[1] = (syndrome_o == 6'h25) ^ data_i[1];
+ data_o[2] = (syndrome_o == 6'h26) ^ data_i[2];
+ data_o[3] = (syndrome_o == 6'h27) ^ data_i[3];
+ data_o[4] = (syndrome_o == 6'h29) ^ data_i[4];
+ data_o[5] = (syndrome_o == 6'h2a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 6'h2b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 6'h2c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 6'h2d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 6'h2e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 6'h2f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 6'h31) ^ data_i[11];
+ data_o[12] = (syndrome_o == 6'h32) ^ data_i[12];
+ data_o[13] = (syndrome_o == 6'h33) ^ data_i[13];
+ data_o[14] = (syndrome_o == 6'h34) ^ data_i[14];
+ data_o[15] = (syndrome_o == 6'h35) ^ data_i[15];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[5];
+ err_o[1] = |syndrome_o[4:0] & ~syndrome_o[5];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [38:0]
+ prim_secded_inv_hamming_39_32_enc (logic [31:0] data_i);
+ logic [38:0] data_o;
+ data_o = 39'(data_i);
+ data_o[32] = 1'b0 ^ ^(data_o & 39'h0056AAAD5B);
+ data_o[33] = 1'b1 ^ ^(data_o & 39'h009B33366D);
+ data_o[34] = 1'b0 ^ ^(data_o & 39'h00E3C3C78E);
+ data_o[35] = 1'b1 ^ ^(data_o & 39'h0003FC07F0);
+ data_o[36] = 1'b0 ^ ^(data_o & 39'h0003FFF800);
+ data_o[37] = 1'b1 ^ ^(data_o & 39'h00FC000000);
+ data_o[38] = 1'b0 ^ ^(data_o & 39'h3FFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_hamming_39_32_t
+ prim_secded_inv_hamming_39_32_dec (logic [38:0] data_i);
+ logic [31:0] data_o;
+ logic [6:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_hamming_39_32_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 39'h2A00000000) & 39'h0156AAAD5B);
+ syndrome_o[1] = ^((data_i ^ 39'h2A00000000) & 39'h029B33366D);
+ syndrome_o[2] = ^((data_i ^ 39'h2A00000000) & 39'h04E3C3C78E);
+ syndrome_o[3] = ^((data_i ^ 39'h2A00000000) & 39'h0803FC07F0);
+ syndrome_o[4] = ^((data_i ^ 39'h2A00000000) & 39'h1003FFF800);
+ syndrome_o[5] = ^((data_i ^ 39'h2A00000000) & 39'h20FC000000);
+ syndrome_o[6] = ^((data_i ^ 39'h2A00000000) & 39'h7FFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 7'h43) ^ data_i[0];
+ data_o[1] = (syndrome_o == 7'h45) ^ data_i[1];
+ data_o[2] = (syndrome_o == 7'h46) ^ data_i[2];
+ data_o[3] = (syndrome_o == 7'h47) ^ data_i[3];
+ data_o[4] = (syndrome_o == 7'h49) ^ data_i[4];
+ data_o[5] = (syndrome_o == 7'h4a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 7'h4b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 7'h4c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 7'h4d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 7'h4e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 7'h4f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 7'h51) ^ data_i[11];
+ data_o[12] = (syndrome_o == 7'h52) ^ data_i[12];
+ data_o[13] = (syndrome_o == 7'h53) ^ data_i[13];
+ data_o[14] = (syndrome_o == 7'h54) ^ data_i[14];
+ data_o[15] = (syndrome_o == 7'h55) ^ data_i[15];
+ data_o[16] = (syndrome_o == 7'h56) ^ data_i[16];
+ data_o[17] = (syndrome_o == 7'h57) ^ data_i[17];
+ data_o[18] = (syndrome_o == 7'h58) ^ data_i[18];
+ data_o[19] = (syndrome_o == 7'h59) ^ data_i[19];
+ data_o[20] = (syndrome_o == 7'h5a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 7'h5b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 7'h5c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 7'h5d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 7'h5e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 7'h5f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 7'h61) ^ data_i[26];
+ data_o[27] = (syndrome_o == 7'h62) ^ data_i[27];
+ data_o[28] = (syndrome_o == 7'h63) ^ data_i[28];
+ data_o[29] = (syndrome_o == 7'h64) ^ data_i[29];
+ data_o[30] = (syndrome_o == 7'h65) ^ data_i[30];
+ data_o[31] = (syndrome_o == 7'h66) ^ data_i[31];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[6];
+ err_o[1] = |syndrome_o[5:0] & ~syndrome_o[6];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [71:0]
+ prim_secded_inv_hamming_72_64_enc (logic [63:0] data_i);
+ logic [71:0] data_o;
+ data_o = 72'(data_i);
+ data_o[64] = 1'b0 ^ ^(data_o & 72'h00AB55555556AAAD5B);
+ data_o[65] = 1'b1 ^ ^(data_o & 72'h00CD9999999B33366D);
+ data_o[66] = 1'b0 ^ ^(data_o & 72'h00F1E1E1E1E3C3C78E);
+ data_o[67] = 1'b1 ^ ^(data_o & 72'h0001FE01FE03FC07F0);
+ data_o[68] = 1'b0 ^ ^(data_o & 72'h0001FFFE0003FFF800);
+ data_o[69] = 1'b1 ^ ^(data_o & 72'h0001FFFFFFFC000000);
+ data_o[70] = 1'b0 ^ ^(data_o & 72'h00FE00000000000000);
+ data_o[71] = 1'b1 ^ ^(data_o & 72'h7FFFFFFFFFFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_hamming_72_64_t
+ prim_secded_inv_hamming_72_64_dec (logic [71:0] data_i);
+ logic [63:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_hamming_72_64_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 72'hAA0000000000000000) & 72'h01AB55555556AAAD5B);
+ syndrome_o[1] = ^((data_i ^ 72'hAA0000000000000000) & 72'h02CD9999999B33366D);
+ syndrome_o[2] = ^((data_i ^ 72'hAA0000000000000000) & 72'h04F1E1E1E1E3C3C78E);
+ syndrome_o[3] = ^((data_i ^ 72'hAA0000000000000000) & 72'h0801FE01FE03FC07F0);
+ syndrome_o[4] = ^((data_i ^ 72'hAA0000000000000000) & 72'h1001FFFE0003FFF800);
+ syndrome_o[5] = ^((data_i ^ 72'hAA0000000000000000) & 72'h2001FFFFFFFC000000);
+ syndrome_o[6] = ^((data_i ^ 72'hAA0000000000000000) & 72'h40FE00000000000000);
+ syndrome_o[7] = ^((data_i ^ 72'hAA0000000000000000) & 72'hFFFFFFFFFFFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h83) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'h85) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h86) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h87) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h89) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h8a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'h8b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h8c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h8d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h8e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h8f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h91) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h92) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h93) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h94) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h95) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h96) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h97) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h98) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'h99) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'h9a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'h9b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h9c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h9d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h9e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h9f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'ha1) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'ha2) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'ha3) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'ha4) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'ha5) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'ha6) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'ha7) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'ha8) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha9) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'haa) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'hab) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'hac) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'had) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'hae) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'haf) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'hb0) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'hb1) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'hb2) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'hb3) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hb4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'hb5) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'hb6) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'hb7) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'hb8) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'hb9) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hba) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'hbb) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hbc) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hbd) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'hbe) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'hbf) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hc1) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'hc2) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hc3) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hc4) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hc5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hc6) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'hc7) ^ data_i[63];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[7];
+ err_o[1] = |syndrome_o[6:0] & ~syndrome_o[7];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+ function automatic logic [75:0]
+ prim_secded_inv_hamming_76_68_enc (logic [67:0] data_i);
+ logic [75:0] data_o;
+ data_o = 76'(data_i);
+ data_o[68] = 1'b0 ^ ^(data_o & 76'h00AAB55555556AAAD5B);
+ data_o[69] = 1'b1 ^ ^(data_o & 76'h00CCD9999999B33366D);
+ data_o[70] = 1'b0 ^ ^(data_o & 76'h000F1E1E1E1E3C3C78E);
+ data_o[71] = 1'b1 ^ ^(data_o & 76'h00F01FE01FE03FC07F0);
+ data_o[72] = 1'b0 ^ ^(data_o & 76'h00001FFFE0003FFF800);
+ data_o[73] = 1'b1 ^ ^(data_o & 76'h00001FFFFFFFC000000);
+ data_o[74] = 1'b0 ^ ^(data_o & 76'h00FFE00000000000000);
+ data_o[75] = 1'b1 ^ ^(data_o & 76'h7FFFFFFFFFFFFFFFFFF);
+ return data_o;
+ endfunction
+
+ function automatic secded_inv_hamming_76_68_t
+ prim_secded_inv_hamming_76_68_dec (logic [75:0] data_i);
+ logic [67:0] data_o;
+ logic [7:0] syndrome_o;
+ logic [1:0] err_o;
+
+ secded_inv_hamming_76_68_t dec;
+
+ // Syndrome calculation
+ syndrome_o[0] = ^((data_i ^ 76'hAA00000000000000000) & 76'h01AAB55555556AAAD5B);
+ syndrome_o[1] = ^((data_i ^ 76'hAA00000000000000000) & 76'h02CCD9999999B33366D);
+ syndrome_o[2] = ^((data_i ^ 76'hAA00000000000000000) & 76'h040F1E1E1E1E3C3C78E);
+ syndrome_o[3] = ^((data_i ^ 76'hAA00000000000000000) & 76'h08F01FE01FE03FC07F0);
+ syndrome_o[4] = ^((data_i ^ 76'hAA00000000000000000) & 76'h10001FFFE0003FFF800);
+ syndrome_o[5] = ^((data_i ^ 76'hAA00000000000000000) & 76'h20001FFFFFFFC000000);
+ syndrome_o[6] = ^((data_i ^ 76'hAA00000000000000000) & 76'h40FFE00000000000000);
+ syndrome_o[7] = ^((data_i ^ 76'hAA00000000000000000) & 76'hFFFFFFFFFFFFFFFFFFF);
+
+ // Corrected output calculation
+ data_o[0] = (syndrome_o == 8'h83) ^ data_i[0];
+ data_o[1] = (syndrome_o == 8'h85) ^ data_i[1];
+ data_o[2] = (syndrome_o == 8'h86) ^ data_i[2];
+ data_o[3] = (syndrome_o == 8'h87) ^ data_i[3];
+ data_o[4] = (syndrome_o == 8'h89) ^ data_i[4];
+ data_o[5] = (syndrome_o == 8'h8a) ^ data_i[5];
+ data_o[6] = (syndrome_o == 8'h8b) ^ data_i[6];
+ data_o[7] = (syndrome_o == 8'h8c) ^ data_i[7];
+ data_o[8] = (syndrome_o == 8'h8d) ^ data_i[8];
+ data_o[9] = (syndrome_o == 8'h8e) ^ data_i[9];
+ data_o[10] = (syndrome_o == 8'h8f) ^ data_i[10];
+ data_o[11] = (syndrome_o == 8'h91) ^ data_i[11];
+ data_o[12] = (syndrome_o == 8'h92) ^ data_i[12];
+ data_o[13] = (syndrome_o == 8'h93) ^ data_i[13];
+ data_o[14] = (syndrome_o == 8'h94) ^ data_i[14];
+ data_o[15] = (syndrome_o == 8'h95) ^ data_i[15];
+ data_o[16] = (syndrome_o == 8'h96) ^ data_i[16];
+ data_o[17] = (syndrome_o == 8'h97) ^ data_i[17];
+ data_o[18] = (syndrome_o == 8'h98) ^ data_i[18];
+ data_o[19] = (syndrome_o == 8'h99) ^ data_i[19];
+ data_o[20] = (syndrome_o == 8'h9a) ^ data_i[20];
+ data_o[21] = (syndrome_o == 8'h9b) ^ data_i[21];
+ data_o[22] = (syndrome_o == 8'h9c) ^ data_i[22];
+ data_o[23] = (syndrome_o == 8'h9d) ^ data_i[23];
+ data_o[24] = (syndrome_o == 8'h9e) ^ data_i[24];
+ data_o[25] = (syndrome_o == 8'h9f) ^ data_i[25];
+ data_o[26] = (syndrome_o == 8'ha1) ^ data_i[26];
+ data_o[27] = (syndrome_o == 8'ha2) ^ data_i[27];
+ data_o[28] = (syndrome_o == 8'ha3) ^ data_i[28];
+ data_o[29] = (syndrome_o == 8'ha4) ^ data_i[29];
+ data_o[30] = (syndrome_o == 8'ha5) ^ data_i[30];
+ data_o[31] = (syndrome_o == 8'ha6) ^ data_i[31];
+ data_o[32] = (syndrome_o == 8'ha7) ^ data_i[32];
+ data_o[33] = (syndrome_o == 8'ha8) ^ data_i[33];
+ data_o[34] = (syndrome_o == 8'ha9) ^ data_i[34];
+ data_o[35] = (syndrome_o == 8'haa) ^ data_i[35];
+ data_o[36] = (syndrome_o == 8'hab) ^ data_i[36];
+ data_o[37] = (syndrome_o == 8'hac) ^ data_i[37];
+ data_o[38] = (syndrome_o == 8'had) ^ data_i[38];
+ data_o[39] = (syndrome_o == 8'hae) ^ data_i[39];
+ data_o[40] = (syndrome_o == 8'haf) ^ data_i[40];
+ data_o[41] = (syndrome_o == 8'hb0) ^ data_i[41];
+ data_o[42] = (syndrome_o == 8'hb1) ^ data_i[42];
+ data_o[43] = (syndrome_o == 8'hb2) ^ data_i[43];
+ data_o[44] = (syndrome_o == 8'hb3) ^ data_i[44];
+ data_o[45] = (syndrome_o == 8'hb4) ^ data_i[45];
+ data_o[46] = (syndrome_o == 8'hb5) ^ data_i[46];
+ data_o[47] = (syndrome_o == 8'hb6) ^ data_i[47];
+ data_o[48] = (syndrome_o == 8'hb7) ^ data_i[48];
+ data_o[49] = (syndrome_o == 8'hb8) ^ data_i[49];
+ data_o[50] = (syndrome_o == 8'hb9) ^ data_i[50];
+ data_o[51] = (syndrome_o == 8'hba) ^ data_i[51];
+ data_o[52] = (syndrome_o == 8'hbb) ^ data_i[52];
+ data_o[53] = (syndrome_o == 8'hbc) ^ data_i[53];
+ data_o[54] = (syndrome_o == 8'hbd) ^ data_i[54];
+ data_o[55] = (syndrome_o == 8'hbe) ^ data_i[55];
+ data_o[56] = (syndrome_o == 8'hbf) ^ data_i[56];
+ data_o[57] = (syndrome_o == 8'hc1) ^ data_i[57];
+ data_o[58] = (syndrome_o == 8'hc2) ^ data_i[58];
+ data_o[59] = (syndrome_o == 8'hc3) ^ data_i[59];
+ data_o[60] = (syndrome_o == 8'hc4) ^ data_i[60];
+ data_o[61] = (syndrome_o == 8'hc5) ^ data_i[61];
+ data_o[62] = (syndrome_o == 8'hc6) ^ data_i[62];
+ data_o[63] = (syndrome_o == 8'hc7) ^ data_i[63];
+ data_o[64] = (syndrome_o == 8'hc8) ^ data_i[64];
+ data_o[65] = (syndrome_o == 8'hc9) ^ data_i[65];
+ data_o[66] = (syndrome_o == 8'hca) ^ data_i[66];
+ data_o[67] = (syndrome_o == 8'hcb) ^ data_i[67];
+
+ // err_o calc. bit0: single error, bit1: double error
+ err_o[0] = syndrome_o[7];
+ err_o[1] = |syndrome_o[6:0] & ~syndrome_o[7];
+
+ dec.data = data_o;
+ dec.syndrome = syndrome_o;
+ dec.err = err_o;
+ return dec;
+
+ endfunction
+
+
+endpackage
diff --git a/EDA-3283/rtl/prim_subreg.sv b/EDA-3283/rtl/prim_subreg.sv
new file mode 100644
index 00000000..af82166a
--- /dev/null
+++ b/EDA-3283/rtl/prim_subreg.sv
@@ -0,0 +1,76 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register slice conforming to Comportibility guide.
+
+module prim_subreg #(
+ parameter int DW = 32 ,
+ parameter SwAccess = "RW", // {RW, RO, WO, W1C, W1S, W0C, RC}
+ parameter logic [DW-1:0] RESVAL = '0 // Reset value
+) (
+ input clk_i,
+ input rst_ni,
+
+ // From SW: valid for RW, WO, W1C, W1S, W0C, RC
+ // In case of RC, Top connects Read Pulse to we
+ input we,
+ input [DW-1:0] wd,
+
+ // From HW: valid for HRW, HWO
+ input de,
+ input [DW-1:0] d,
+
+ // output to HW and Reg Read
+ output logic qe,
+ output logic [DW-1:0] q,
+ output logic [DW-1:0] qs
+);
+
+ logic wr_en ;
+ logic [DW-1:0] wr_data;
+
+ if ((SwAccess == "RW") || (SwAccess == "WO")) begin : gen_w
+ assign wr_en = we | de ;
+ assign wr_data = (we == 1'b1) ? wd : d ; // SW higher priority
+ end else if (SwAccess == "RO") begin : gen_ro
+ // Unused we, wd
+ assign wr_en = de ;
+ assign wr_data = d ;
+ end else if (SwAccess == "W1S") begin : gen_w1s
+ // If SWACCESS is W1S, then assume hw tries to clear.
+ // So, give a chance HW to clear when SW tries to set.
+ // If both try to set/clr at the same bit pos, SW wins.
+ assign wr_en = we | de ;
+ assign wr_data = (de ? d : q) | (we ? wd : '0);
+ end else if (SwAccess == "W1C") begin : gen_w1c
+ // If SWACCESS is W1C, then assume hw tries to set.
+ // So, give a chance HW to set when SW tries to clear.
+ // If both try to set/clr at the same bit pos, SW wins.
+ assign wr_en = we | de ;
+ assign wr_data = (de ? d : q) & (we ? ~wd : '1);
+ end else if (SwAccess == "W0C") begin : gen_w0c
+ assign wr_en = we | de ;
+ assign wr_data = (de ? d : q) & (we ? wd : '1);
+ end else if (SwAccess == "RC") begin : gen_rc
+ // This swtype is not recommended but exists for compatibility.
+ // WARN: we signal is actually read signal not write enable.
+ assign wr_en = we | de ;
+ assign wr_data = (de ? d : q) & (we ? '0 : '1);
+ end else begin : gen_hw
+ assign wr_en = de ;
+ assign wr_data = d ;
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) qe <= 1'b0;
+ else qe <= we ;
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) q <= RESVAL ;
+ else if (wr_en) q <= wr_data;
+ end
+ assign qs = q;
+
+endmodule
diff --git a/EDA-3283/rtl/prim_subreg_ext.sv b/EDA-3283/rtl/prim_subreg_ext.sv
new file mode 100644
index 00000000..6db975d8
--- /dev/null
+++ b/EDA-3283/rtl/prim_subreg_ext.sv
@@ -0,0 +1,28 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register slice conforming to Comportibility guide.
+
+module prim_subreg_ext #(
+ parameter int unsigned DW = 32
+) (
+ input re,
+ input we,
+ input [DW-1:0] wd,
+
+ input [DW-1:0] d,
+
+ // output to HW and Reg Read
+ output logic qe,
+ output logic qre,
+ output logic [DW-1:0] q,
+ output logic [DW-1:0] qs
+);
+
+ assign qs = d;
+ assign q = wd;
+ assign qe = we;
+ assign qre = re;
+
+endmodule
diff --git a/EDA-3283/rtl/prim_subreg_pkg.sv b/EDA-3283/rtl/prim_subreg_pkg.sv
new file mode 100644
index 00000000..6e1da043
--- /dev/null
+++ b/EDA-3283/rtl/prim_subreg_pkg.sv
@@ -0,0 +1,17 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package prim_subreg_pkg;
+
+ // Register access specifier
+ typedef enum logic [2:0] {
+ SwAccessRW = 3'd0, // Read-write
+ SwAccessRO = 3'd1, // Read-only
+ SwAccessWO = 3'd2, // Write-only
+ SwAccessW1C = 3'd3, // Write 1 to clear
+ SwAccessW1S = 3'd4, // Write 1 to set
+ SwAccessW0C = 3'd5, // Write 0 to clear
+ SwAccessRC = 3'd6 // Read to clear. Do not use, only exists for compatibility.
+ } sw_access_e;
+endpackage
diff --git a/EDA-3283/rtl/prim_util_pkg.sv b/EDA-3283/rtl/prim_util_pkg.sv
new file mode 100644
index 00000000..36960c65
--- /dev/null
+++ b/EDA-3283/rtl/prim_util_pkg.sv
@@ -0,0 +1,89 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Utility functions
+ */
+package prim_util_pkg;
+ /**
+ * Math function: $clog2 as specified in Verilog-2005
+ *
+ * Do not use this function if $clog2() is available.
+ *
+ * clog2 = 0 for value == 0
+ * ceil(log2(value)) for value >= 1
+ *
+ * This implementation is a synthesizable variant of the $clog2 function as
+ * specified in the Verilog-2005 standard (IEEE 1364-2005).
+ *
+ * To quote the standard:
+ * The system function $clog2 shall return the ceiling of the log
+ * base 2 of the argument (the log rounded up to an integer
+ * value). The argument can be an integer or an arbitrary sized
+ * vector value. The argument shall be treated as an unsigned
+ * value, and an argument value of 0 shall produce a result of 0.
+ */
+ function automatic integer _clog2(integer value);
+ integer result;
+ // Use an intermediate value to avoid assigning to an input port, which produces a warning in
+ // Synopsys DC.
+ integer v = value;
+ v = v - 1;
+ for (result = 0; v > 0; result++) begin
+ v = v >> 1;
+ end
+ return result;
+ endfunction
+
+
+ /**
+ * Math function: Number of bits needed to address |value| items.
+ *
+ * 0 for value == 0
+ * vbits = 1 for value == 1
+ * ceil(log2(value)) for value > 1
+ *
+ *
+ * The primary use case for this function is the definition of registers/arrays
+ * which are wide enough to contain |value| items.
+ *
+ * This function identical to $clog2() for all input values except the value 1;
+ * it could be considered an "enhanced" $clog2() function.
+ *
+ *
+ * Example 1:
+ * parameter Items = 1;
+ * localparam ItemsWidth = vbits(Items); // 1
+ * logic [ItemsWidth-1:0] item_register; // items_register is now [0:0]
+ *
+ * Example 2:
+ * parameter Items = 64;
+ * localparam ItemsWidth = vbits(Items); // 6
+ * logic [ItemsWidth-1:0] item_register; // items_register is now [5:0]
+ *
+ * Note: If you want to store the number "value" inside a register, you need
+ * a register with size vbits(value + 1), since you also need to store
+ * the number 0.
+ *
+ * Example 3:
+ * logic [vbits(64)-1:0] store_64_logic_values; // width is [5:0]
+ * logic [vbits(64 + 1)-1:0] store_number_64; // width is [6:0]
+ */
+ function automatic integer vbits(integer value);
+`ifdef XCELIUM
+ // The use of system functions was not allowed here in Verilog-2001, but is
+ // valid since (System)Verilog-2005, which is also when $clog2() first
+ // appeared.
+ // Xcelium < 19.10 does not yet support the use of $clog2() here, fall back
+ // to an implementation without a system function. Remove this workaround
+ // if we require a newer Xcelium version.
+ // See #2579 and #2597.
+ return (value == 1) ? 1 : _clog2(value);
+`else
+ return (value == 1) ? 1 : $clog2(value);
+`endif
+ endfunction
+
+endpackage
diff --git a/EDA-3283/rtl/pwrmgr_pkg.sv b/EDA-3283/rtl/pwrmgr_pkg.sv
new file mode 100644
index 00000000..002f6d7f
--- /dev/null
+++ b/EDA-3283/rtl/pwrmgr_pkg.sv
@@ -0,0 +1,274 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Power Manager Package
+//
+
+package pwrmgr_pkg;
+
+ // global constant
+ parameter int ALWAYS_ON_DOMAIN = 0;
+
+ // variables referenced by other modules / packages
+ parameter int PowerDomains = 2; // this needs to be a topgen populated number, or from topcfg?
+
+ // variables referenced only by pwrmgr
+ localparam int TotalWakeWidth = pwrmgr_reg_pkg::NumWkups + 2; // Abort and fall through are added
+
+ typedef enum logic [1:0] {
+ IntReqMainPwr,
+ IntReqEsc,
+ IntReqLastIdx
+ } pwr_int_rst_req_e;
+
+ parameter int NumSwRstReq = 1;
+
+ // position of escalation request
+ parameter int HwResetWidth = pwrmgr_reg_pkg::NumRstReqs + int'(IntReqLastIdx);
+ parameter int TotalResetWidth = HwResetWidth + NumSwRstReq;
+ parameter int ResetMainPwrIdx = pwrmgr_reg_pkg::NumRstReqs + int'(IntReqMainPwr);
+ parameter int ResetEscIdx = pwrmgr_reg_pkg::NumRstReqs + int'(IntReqEsc);
+ parameter int ResetSwReqIdx = TotalResetWidth - 1;
+
+ // pwrmgr to ast
+ typedef struct packed {
+ logic main_pd_n;
+ logic pwr_clamp_env;
+ logic pwr_clamp;
+ logic slow_clk_en;
+ logic core_clk_en;
+ logic io_clk_en;
+ logic usb_clk_en;
+ } pwr_ast_req_t;
+
+ typedef struct packed {
+ logic slow_clk_val;
+ logic core_clk_val;
+ logic io_clk_val;
+ logic usb_clk_val;
+ logic main_pok;
+ } pwr_ast_rsp_t;
+
+ // default value of pwr_ast_rsp (for dangling ports)
+ parameter pwr_ast_rsp_t PWR_AST_RSP_DEFAULT = '{
+ slow_clk_val: 1'b1,
+ core_clk_val: 1'b1,
+ io_clk_val: 1'b1,
+ usb_clk_val: 1'b1,
+ main_pok: 1'b1
+ };
+
+ parameter pwr_ast_rsp_t PWR_AST_RSP_SYNC_DEFAULT = '{
+ slow_clk_val: 1'b0,
+ core_clk_val: 1'b0,
+ io_clk_val: 1'b0,
+ usb_clk_val: 1'b0,
+ main_pok: 1'b0
+ };
+
+ // reasons for pwrmgr reset
+ typedef enum logic [1:0] {
+ ResetNone = 0, // there is no reset
+ LowPwrEntry = 1, // reset is caused by low power entry
+ HwReq = 2, // reset is caused by peripheral reset requests
+ ResetUndefined = 3 // this should never happen outside of POR
+ } reset_cause_e;
+
+ // pwrmgr to rstmgr
+ typedef struct packed {
+ logic [PowerDomains-1:0] rst_lc_req;
+ logic [PowerDomains-1:0] rst_sys_req;
+ logic [HwResetWidth-1:0] rstreqs;
+ reset_cause_e reset_cause;
+ } pwr_rst_req_t;
+
+ // rstmgr to pwrmgr
+ typedef struct packed {
+ logic [PowerDomains-1:0] rst_lc_src_n;
+ logic [PowerDomains-1:0] rst_sys_src_n;
+ } pwr_rst_rsp_t;
+
+ // default value (for dangling ports)
+ parameter pwr_rst_rsp_t PWR_RST_RSP_DEFAULT = '{
+ rst_lc_src_n: {PowerDomains{1'b1}},
+ rst_sys_src_n: {PowerDomains{1'b1}}
+ };
+
+ // pwrmgr to clkmgr
+ typedef struct packed {
+ logic main_ip_clk_en;
+ logic io_ip_clk_en;
+ logic usb_ip_clk_en;
+ } pwr_clk_req_t;
+
+ // clkmgr to pwrmgr
+ typedef struct packed {
+ logic main_status;
+ logic io_status;
+ logic usb_status;
+ } pwr_clk_rsp_t;
+
+ // pwrmgr to otp
+ typedef struct packed {
+ logic otp_init;
+ } pwr_otp_req_t;
+
+ // otp to pwrmgr
+ typedef struct packed {
+ logic otp_done;
+ logic otp_idle;
+ } pwr_otp_rsp_t;
+
+ // default value (for dangling ports)
+ parameter pwr_otp_rsp_t PWR_OTP_RSP_DEFAULT = '{
+ otp_done: 1'b1,
+ otp_idle: 1'b1
+ };
+
+ // pwrmgr to lifecycle
+ typedef struct packed {
+ logic lc_init;
+ } pwr_lc_req_t;
+
+ // lifecycle to pwrmgr
+ typedef struct packed {
+ logic lc_done;
+ logic lc_idle;
+ } pwr_lc_rsp_t;
+
+ // default value (for dangling ports)
+ parameter pwr_lc_rsp_t PWR_LC_RSP_DEFAULT = '{
+ lc_done: 1'b1,
+ lc_idle: 1'b1
+ };
+
+ typedef struct packed {
+ logic flash_idle;
+ } pwr_flash_t;
+
+ parameter pwr_flash_t PWR_FLASH_DEFAULT = '{
+ flash_idle: 1'b1
+ };
+
+ // processor to pwrmgr
+ typedef struct packed {
+ logic core_sleeping;
+ } pwr_cpu_t;
+
+ // default value (for dangling ports)
+ parameter pwr_cpu_t PWR_CPU_DEFAULT = '{
+ core_sleeping: 1'b0
+ };
+
+ // default value (for dangling ports)
+ parameter int WAKEUPS_DEFAULT = '0;
+ parameter int RSTREQS_DEFAULT = '0;
+
+ // peripherals to pwrmgr
+ typedef struct packed {
+ logic [pwrmgr_reg_pkg::NumWkups-1:0] wakeups;
+ // reset requests include external requests + escalation reset
+ logic [TotalResetWidth-1:0] rstreqs;
+ } pwr_peri_t;
+
+ // power-up causes
+ typedef enum logic [1:0] {
+ Por = 2'h0,
+ Wake = 2'h1,
+ Reset = 2'h2
+ } pwrup_cause_e;
+
+ // low power hints
+ typedef enum logic {
+ None = 1'b0,
+ LowPower = 1'b1
+ } low_power_hint_e;
+
+ // fast fsm state enum
+ // Encoding generated with:
+ // $ ./util/design/sparse-fsm-encode.py -d 5 -m 17 -n 12 \
+ // -s 4233784300 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: ||||||||||||||||| (30.15%)
+ // 6: |||||||||||||||||||| (35.29%)
+ // 7: |||||||||| (19.12%)
+ // 8: ||||| (9.56%)
+ // 9: | (2.21%)
+ // 10: | (2.21%)
+ // 11: (1.47%)
+ // 12: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 11
+ // Minimum Hamming weight: 3
+ // Maximum Hamming weight: 9
+ //
+ localparam int FastPwrStateWidth = 12;
+ typedef enum logic [FastPwrStateWidth-1:0] {
+ FastPwrStateLowPower = 12'b111010101011,
+ FastPwrStateEnableClocks = 12'b000011000010,
+ FastPwrStateReleaseLcRst = 12'b111011010110,
+ FastPwrStateOtpInit = 12'b100101011010,
+ FastPwrStateLcInit = 12'b010001111100,
+ FastPwrStateStrap = 12'b010110111010,
+ FastPwrStateAckPwrUp = 12'b010100100101,
+ FastPwrStateRomCheck = 12'b101100000011,
+ FastPwrStateActive = 12'b100001010101,
+ FastPwrStateDisClks = 12'b010000010011,
+ FastPwrStateFallThrough = 12'b111111011001,
+ FastPwrStateNvmIdleChk = 12'b001111110011,
+ FastPwrStateLowPowerPrep = 12'b011101001111,
+ FastPwrStateNvmShutDown = 12'b001010011111,
+ FastPwrStateResetPrep = 12'b101000110000,
+ FastPwrStateReqPwrDn = 12'b101101101100,
+ FastPwrStateInvalid = 12'b100010001100
+ } fast_pwr_state_e;
+
+ // Encoding generated with:
+ // $ ./util/design/sparse-fsm-encode.py -d 5 -m 12 -n 10 \
+ // -s 1726685338 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: |||||||||||||||||||| (54.55%)
+ // 6: |||||||||||||||| (45.45%)
+ // 7: --
+ // 8: --
+ // 9: --
+ // 10: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 6
+ // Minimum Hamming weight: 2
+ // Maximum Hamming weight: 8
+ //
+ localparam int SlowPwrStateWidth = 10;
+ typedef enum logic [SlowPwrStateWidth-1:0] {
+ SlowPwrStateReset = 10'b0000100010,
+ SlowPwrStateLowPower = 10'b1011000111,
+ SlowPwrStateMainPowerOn = 10'b0110101111,
+ SlowPwrStatePwrClampOff = 10'b0110010001,
+ SlowPwrStateClocksOn = 10'b1010111100,
+ SlowPwrStateReqPwrUp = 10'b0011011010,
+ SlowPwrStateIdle = 10'b1111100000,
+ SlowPwrStateAckPwrDn = 10'b0001110101,
+ SlowPwrStateClocksOff = 10'b1101111011,
+ SlowPwrStatePwrClampOn = 10'b0101001100,
+ SlowPwrStateMainPowerOff = 10'b1000001001,
+ SlowPwrStateInvalid = 10'b1100010110
+ } slow_pwr_state_e;
+
+endpackage // pwrmgr_pkg
diff --git a/EDA-3283/rtl/pwrmgr_reg_pkg.sv b/EDA-3283/rtl/pwrmgr_reg_pkg.sv
new file mode 100644
index 00000000..5e003050
--- /dev/null
+++ b/EDA-3283/rtl/pwrmgr_reg_pkg.sv
@@ -0,0 +1,217 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package pwrmgr_reg_pkg;
+
+ // Param list
+ parameter int NumWkups = 1;
+ parameter int NumRstReqs = 1;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } pwrmgr_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } low_power_hint;
+ struct packed {
+ logic q;
+ } core_clk_en;
+ struct packed {
+ logic q;
+ } io_clk_en;
+ struct packed {
+ logic q;
+ } usb_clk_en_lp;
+ struct packed {
+ logic q;
+ } usb_clk_en_active;
+ struct packed {
+ logic q;
+ } main_pd_n;
+ } pwrmgr_reg2hw_control_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } pwrmgr_reg2hw_cfg_cdc_sync_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_wakeup_en_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_reset_en_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_wake_info_capture_dis_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } reasons;
+ struct packed {
+ logic q;
+ logic qe;
+ } fall_through;
+ struct packed {
+ logic q;
+ logic qe;
+ } abort;
+ } pwrmgr_reg2hw_wake_info_reg_t;
+
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ logic d;
+ } pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } low_power_hint;
+ } pwrmgr_hw2reg_control_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_cfg_cdc_sync_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_wake_status_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_reset_status_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_escalate_reset_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ } reasons;
+ struct packed {
+ logic d;
+ } fall_through;
+ struct packed {
+ logic d;
+ } abort;
+ } pwrmgr_hw2reg_wake_info_reg_t;
+
+
+ ///////////////////////////////////////
+ // Register to internal design logic //
+ ///////////////////////////////////////
+ typedef struct packed {
+ pwrmgr_reg2hw_intr_state_reg_t intr_state; // [20:20]
+ pwrmgr_reg2hw_intr_enable_reg_t intr_enable; // [19:19]
+ pwrmgr_reg2hw_intr_test_reg_t intr_test; // [18:17]
+ pwrmgr_reg2hw_control_reg_t control; // [16:11]
+ pwrmgr_reg2hw_cfg_cdc_sync_reg_t cfg_cdc_sync; // [10:9]
+ pwrmgr_reg2hw_wakeup_en_mreg_t [0:0] wakeup_en; // [8:8]
+ pwrmgr_reg2hw_reset_en_mreg_t [0:0] reset_en; // [7:7]
+ pwrmgr_reg2hw_wake_info_capture_dis_reg_t wake_info_capture_dis; // [6:6]
+ pwrmgr_reg2hw_wake_info_reg_t wake_info; // [5:0]
+ } pwrmgr_reg2hw_t;
+
+ ///////////////////////////////////////
+ // Internal design logic to register //
+ ///////////////////////////////////////
+ typedef struct packed {
+ pwrmgr_hw2reg_intr_state_reg_t intr_state; // [15:14]
+ pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t ctrl_cfg_regwen; // [13:13]
+ pwrmgr_hw2reg_control_reg_t control; // [12:11]
+ pwrmgr_hw2reg_cfg_cdc_sync_reg_t cfg_cdc_sync; // [10:9]
+ pwrmgr_hw2reg_wake_status_mreg_t [0:0] wake_status; // [8:7]
+ pwrmgr_hw2reg_reset_status_mreg_t [0:0] reset_status; // [6:5]
+ pwrmgr_hw2reg_escalate_reset_status_reg_t escalate_reset_status; // [4:3]
+ pwrmgr_hw2reg_wake_info_reg_t wake_info; // [2:0]
+ } pwrmgr_hw2reg_t;
+
+ // Register Address
+ parameter logic [5:0] PWRMGR_INTR_STATE_OFFSET = 6'h 0;
+ parameter logic [5:0] PWRMGR_INTR_ENABLE_OFFSET = 6'h 4;
+ parameter logic [5:0] PWRMGR_INTR_TEST_OFFSET = 6'h 8;
+ parameter logic [5:0] PWRMGR_CTRL_CFG_REGWEN_OFFSET = 6'h c;
+ parameter logic [5:0] PWRMGR_CONTROL_OFFSET = 6'h 10;
+ parameter logic [5:0] PWRMGR_CFG_CDC_SYNC_OFFSET = 6'h 14;
+ parameter logic [5:0] PWRMGR_WAKEUP_EN_REGWEN_OFFSET = 6'h 18;
+ parameter logic [5:0] PWRMGR_WAKEUP_EN_OFFSET = 6'h 1c;
+ parameter logic [5:0] PWRMGR_WAKE_STATUS_OFFSET = 6'h 20;
+ parameter logic [5:0] PWRMGR_RESET_EN_REGWEN_OFFSET = 6'h 24;
+ parameter logic [5:0] PWRMGR_RESET_EN_OFFSET = 6'h 28;
+ parameter logic [5:0] PWRMGR_RESET_STATUS_OFFSET = 6'h 2c;
+ parameter logic [5:0] PWRMGR_ESCALATE_RESET_STATUS_OFFSET = 6'h 30;
+ parameter logic [5:0] PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET = 6'h 34;
+ parameter logic [5:0] PWRMGR_WAKE_INFO_OFFSET = 6'h 38;
+
+
+ // Register Index
+ typedef enum int {
+ PWRMGR_INTR_STATE,
+ PWRMGR_INTR_ENABLE,
+ PWRMGR_INTR_TEST,
+ PWRMGR_CTRL_CFG_REGWEN,
+ PWRMGR_CONTROL,
+ PWRMGR_CFG_CDC_SYNC,
+ PWRMGR_WAKEUP_EN_REGWEN,
+ PWRMGR_WAKEUP_EN,
+ PWRMGR_WAKE_STATUS,
+ PWRMGR_RESET_EN_REGWEN,
+ PWRMGR_RESET_EN,
+ PWRMGR_RESET_STATUS,
+ PWRMGR_ESCALATE_RESET_STATUS,
+ PWRMGR_WAKE_INFO_CAPTURE_DIS,
+ PWRMGR_WAKE_INFO
+ } pwrmgr_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] PWRMGR_PERMIT [15] = '{
+ 4'b 0001, // index[ 0] PWRMGR_INTR_STATE
+ 4'b 0001, // index[ 1] PWRMGR_INTR_ENABLE
+ 4'b 0001, // index[ 2] PWRMGR_INTR_TEST
+ 4'b 0001, // index[ 3] PWRMGR_CTRL_CFG_REGWEN
+ 4'b 0011, // index[ 4] PWRMGR_CONTROL
+ 4'b 0001, // index[ 5] PWRMGR_CFG_CDC_SYNC
+ 4'b 0001, // index[ 6] PWRMGR_WAKEUP_EN_REGWEN
+ 4'b 0001, // index[ 7] PWRMGR_WAKEUP_EN
+ 4'b 0001, // index[ 8] PWRMGR_WAKE_STATUS
+ 4'b 0001, // index[ 9] PWRMGR_RESET_EN_REGWEN
+ 4'b 0001, // index[10] PWRMGR_RESET_EN
+ 4'b 0001, // index[11] PWRMGR_RESET_STATUS
+ 4'b 0001, // index[12] PWRMGR_ESCALATE_RESET_STATUS
+ 4'b 0001, // index[13] PWRMGR_WAKE_INFO_CAPTURE_DIS
+ 4'b 0001 // index[14] PWRMGR_WAKE_INFO
+ };
+endpackage
+
diff --git a/EDA-3283/rtl/sha2.sv b/EDA-3283/rtl/sha2.sv
new file mode 100644
index 00000000..4d93d790
--- /dev/null
+++ b/EDA-3283/rtl/sha2.sv
@@ -0,0 +1,323 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SHA-256 algorithm
+//
+
+module sha2 import hmac_pkg::*; (
+ input clk_i,
+ input rst_ni,
+
+ input wipe_secret,
+ input sha_word_t wipe_v,
+
+ // FIFO read signal
+ input fifo_rvalid,
+ input sha_fifo_t fifo_rdata,
+ output logic fifo_rready,
+
+ // Control signals
+ input sha_en, // If disabled, it clears internal content.
+ input hash_start,
+ input hash_process,
+ output logic hash_done,
+
+ input [63:0] message_length, // bits but byte based
+ output sha_word_t [7:0] digest,
+
+ output logic idle
+);
+
+ localparam int unsigned RoundWidth = $clog2(NumRound);
+
+ logic msg_feed_complete;
+
+ logic shaf_rready;
+ sha_word_t shaf_rdata;
+ logic shaf_rvalid;
+
+ logic [RoundWidth-1:0] round;
+
+ logic [3:0] w_index;
+ sha_word_t [15:0] w;
+
+ localparam sha_word_t ZeroWord = '0;
+
+ // w, hash, digest update logic control signals
+ logic update_w_from_fifo, calculate_next_w;
+ logic init_hash, run_hash, complete_one_chunk;
+ logic update_digest, clear_digest;
+
+ logic hash_done_next; // to meet the phase with digest value.
+
+ sha_word_t [7:0] hash; // a,b,c,d,e,f,g,h
+
+ // Fill up w
+ always_ff @(posedge clk_i or negedge rst_ni) begin : fill_w
+ if (!rst_ni) begin
+ w <= '0;
+ end else if (wipe_secret) begin
+ w <= w ^ {16{wipe_v}};
+ end else if (!sha_en) begin
+ w <= '0;
+ end else if (!run_hash && update_w_from_fifo) begin
+ // this logic runs at the first stage of SHA.
+ w <= {shaf_rdata, w[15:1]};
+ end else if (calculate_next_w) begin
+ w <= {calc_w(w[0], w[1], w[9], w[14]), w[15:1]};
+ //end else if (run_hash && update_w_from_fifo) begin
+ // // This code runs when round is in [48, 63]. At this time, it reads from the fifo
+ // // to fill the register if available. If FIFO goes to empty, w_index doesn't increase
+ // // and it cannot reach 15. Then the sha engine doesn't start, which introduces latency.
+ // //
+ // // But in this case, still w should be shifted to feed SHA compress engine. Then
+ // // fifo_rdata should be inserted in the middle of w index.
+ // // w[64-round + w_index] <= fifo_rdata;
+ // for (int i = 0 ; i < 16 ; i++) begin
+ // if (i == (64 - round + w_index)) begin
+ // w[i] <= shaf_rdata;
+ // end else if (i == 15) begin
+ // w[i] <= '0;
+ // end else begin
+ // w[i] <= w[i+1];
+ // end
+ // end
+ end else if (run_hash) begin
+ // Just shift-out. There's no incoming data
+ w <= {ZeroWord, w[15:1]};
+ end
+ end : fill_w
+
+ // Update engine
+ always_ff @(posedge clk_i or negedge rst_ni) begin : compress_round
+ if (!rst_ni) begin
+ hash <= '{default:'0};
+ end else if (wipe_secret) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ hash[i] <= hash[i] ^ wipe_v;
+ end
+ end else if (init_hash) begin
+ hash <= digest;
+ end else if (run_hash) begin
+ hash <= compress( w[0], CubicRootPrime[round], hash);
+ end
+ end : compress_round
+
+ // Digest
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ digest <= '{default: '0};
+ end else if (wipe_secret) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ digest[i] <= digest[i] ^ wipe_v;
+ end
+ end else if (hash_start) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ digest[i] <= InitHash[i];
+ end
+ end else if (!sha_en || clear_digest) begin
+ digest <= '0;
+ end else if (update_digest) begin
+ for (int i = 0 ; i < 8 ; i++) begin
+ digest[i] <= digest[i] + hash[i];
+ end
+ end
+ end
+
+ // round
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ round <= '0;
+ end else if (!sha_en) begin
+ round <= '0;
+ end else if (run_hash) begin
+ if (round == RoundWidth'(unsigned'(NumRound-1))) begin
+ round <= '0;
+ end else begin
+ round <= round + 1;
+ end
+ end
+ end
+
+ // w_index
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ w_index <= '0;
+ end else if (!sha_en) begin
+ w_index <= '0;
+ end else if (update_w_from_fifo) begin
+ w_index <= w_index + 1;
+ end
+ end
+
+ assign shaf_rready = update_w_from_fifo;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) hash_done <= 1'b0;
+ else hash_done <= hash_done_next;
+ end
+
+ typedef enum logic [1:0] {
+ FifoIdle,
+ FifoLoadFromFifo,
+ FifoWait
+ } fifoctl_state_e;
+
+ fifoctl_state_e fifo_st_q, fifo_st_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ fifo_st_q <= FifoIdle;
+ end else begin
+ fifo_st_q <= fifo_st_d;
+ end
+ end
+
+ always_comb begin
+ fifo_st_d = FifoIdle;
+ update_w_from_fifo = 1'b0;
+ hash_done_next = 1'b0;
+
+ unique case (fifo_st_q)
+ FifoIdle: begin
+ if (hash_start) begin
+ fifo_st_d = FifoLoadFromFifo;
+ end else begin
+ fifo_st_d = FifoIdle;
+ end
+ end
+
+ FifoLoadFromFifo: begin
+ if (!sha_en) begin
+ fifo_st_d = FifoIdle;
+ update_w_from_fifo = 1'b0;
+ end else if (!shaf_rvalid) begin
+ // Wait until it is filled
+ fifo_st_d = FifoLoadFromFifo;
+ update_w_from_fifo = 1'b0;
+ end else if (w_index == 4'd 15) begin
+ fifo_st_d = FifoWait;
+ update_w_from_fifo = 1'b1;
+ end else begin
+ fifo_st_d = FifoLoadFromFifo;
+ update_w_from_fifo = 1'b1;
+ end
+ end
+
+ FifoWait: begin
+ // Wait until next fetch begins (begin at round == 48)a
+ if (msg_feed_complete && complete_one_chunk) begin
+ fifo_st_d = FifoIdle;
+
+ hash_done_next = 1'b1;
+ end else if (complete_one_chunk) begin
+ fifo_st_d = FifoLoadFromFifo;
+ end else begin
+ fifo_st_d = FifoWait;
+ end
+ end
+
+ default: begin
+ fifo_st_d = FifoIdle;
+ end
+ endcase
+ end
+
+ // SHA control
+ typedef enum logic [1:0] {
+ ShaIdle,
+ ShaCompress,
+ ShaUpdateDigest
+ } sha_st_t;
+
+ sha_st_t sha_st_q, sha_st_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ sha_st_q <= ShaIdle;
+ end else begin
+ sha_st_q <= sha_st_d;
+ end
+ end
+
+ assign clear_digest = hash_start;
+
+ always_comb begin
+ update_digest = 1'b0;
+ calculate_next_w = 1'b0;
+
+ init_hash = 1'b0;
+ run_hash = 1'b0;
+
+ unique case (sha_st_q)
+ ShaIdle: begin
+ if (fifo_st_q == FifoWait) begin
+ init_hash = 1'b1;
+ sha_st_d = ShaCompress;
+ end else begin
+ sha_st_d = ShaIdle;
+ end
+ end
+
+ ShaCompress: begin
+ run_hash = 1'b1;
+
+ if (round < 48) begin
+ calculate_next_w = 1'b1;
+ end
+
+ if (complete_one_chunk) begin
+ sha_st_d = ShaUpdateDigest;
+ end else begin
+ sha_st_d = ShaCompress;
+ end
+ end
+
+ ShaUpdateDigest: begin
+ update_digest = 1'b1;
+ if (fifo_st_q == FifoWait) begin
+ init_hash = 1'b1;
+ sha_st_d = ShaCompress;
+ end else begin
+ sha_st_d = ShaIdle;
+ end
+ end
+
+ default: begin
+ sha_st_d = ShaIdle;
+ end
+ endcase
+ end
+
+ // complete_one_chunk
+ assign complete_one_chunk = (round == 6'd63);
+
+ sha2_pad u_pad (
+ .clk_i,
+ .rst_ni,
+
+ .wipe_secret,
+ .wipe_v,
+
+ .fifo_rvalid,
+ .fifo_rdata,
+ .fifo_rready,
+
+ .shaf_rvalid,
+ .shaf_rdata,
+ .shaf_rready,
+
+ .sha_en,
+ .hash_start,
+ .hash_process,
+ .hash_done,
+
+ .message_length,
+ .msg_feed_complete
+ );
+
+ // Idle
+ assign idle = (fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && !hash_start;
+
+endmodule : sha2
diff --git a/EDA-3283/rtl/sha2_pad.sv b/EDA-3283/rtl/sha2_pad.sv
new file mode 100644
index 00000000..958b1e09
--- /dev/null
+++ b/EDA-3283/rtl/sha2_pad.sv
@@ -0,0 +1,311 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SHA-256 Padding logic
+//
+
+
+module sha2_pad import hmac_pkg::*; (
+ input clk_i,
+ input rst_ni,
+
+ input wipe_secret,
+ input sha_word_t wipe_v,
+
+ // To actual FIFO
+ input fifo_rvalid,
+ input sha_fifo_t fifo_rdata,
+ output logic fifo_rready,
+
+ // from SHA2 compress engine
+ output logic shaf_rvalid,
+ output sha_word_t shaf_rdata,
+ input shaf_rready,
+
+ input sha_en,
+ input hash_start,
+ input hash_process,
+ input hash_done,
+
+ input [63:0] message_length, // # of bytes in bits (8 bits granularity)
+ output logic msg_feed_complete // Indicates, all message is feeded
+);
+
+ //logic [8:0] length_added;
+
+ logic [63:0] tx_count; // fin received data count.
+
+ logic inc_txcount;
+ logic fifo_partial;
+ logic txcnt_eq_1a0;
+ logic hash_process_flag; // Set by hash_process, clear by hash_done
+
+ assign fifo_partial = ~&fifo_rdata.mask;
+
+ // tx_count[8:0] == 'h1c0 --> should send LenHi
+ assign txcnt_eq_1a0 = (tx_count[8:0] == 9'h1a0);
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ hash_process_flag <= 1'b0;
+ end else if (hash_process) begin
+ hash_process_flag <= 1'b1;
+ end else if (hash_done || hash_start) begin
+ hash_process_flag <= 1'b0;
+ end
+ end
+
+ // Data path: fout_wdata
+ typedef enum logic [2:0] {
+ FifoIn, // fin_wdata, fin_wstrb
+ Pad80, // {8'h80, 8'h00} , strb (calc based on len[4:3])
+ Pad00, // 32'h0, full strb
+ LenHi, // len[63:32], full strb
+ LenLo // len[31:0], full strb
+ } sel_data_e;
+ sel_data_e sel_data;
+
+ always_comb begin
+ unique case (sel_data)
+ FifoIn: begin
+ shaf_rdata = fifo_rdata.data;
+ end
+
+ Pad80: begin
+ // {a[7:0], b[7:0], c[7:0], d[7:0]}
+ // msglen[4:3] == 00 |-> {'h80, 'h00, 'h00, 'h00}
+ // msglen[4:3] == 01 |-> {msg, 'h80, 'h00, 'h00}
+ // msglen[4:3] == 10 |-> {msg[15:0], 'h80, 'h00}
+ // msglen[4:3] == 11 |-> {msg[23:0], 'h80}
+ unique case (message_length[4:3])
+ 2'b 00: shaf_rdata = 32'h 8000_0000;
+ 2'b 01: shaf_rdata = {fifo_rdata.data[31:24], 24'h 8000_00};
+ 2'b 10: shaf_rdata = {fifo_rdata.data[31:16], 16'h 8000};
+ 2'b 11: shaf_rdata = {fifo_rdata.data[31: 8], 8'h 80};
+ default: shaf_rdata = 32'h0;
+ endcase
+ end
+
+ Pad00: begin
+ shaf_rdata = '0;
+ end
+
+ LenHi: begin
+ shaf_rdata = message_length[63:32];
+ end
+
+ LenLo: begin
+ shaf_rdata = message_length[31:0];
+ end
+
+ default: begin
+ shaf_rdata = '0;
+ end
+ endcase
+ end
+
+ // Padded length
+ // $ceil(message_length + 8 + 64, 512) -> message_length [8:0] + 440 and ignore carry
+ //assign length_added = (message_length[8:0] + 9'h1b8) ;
+
+ // fifo control
+ // add 8'h 80 , N 8'h00, 64'h message_length
+
+ // Steps
+ // 1. `hash_start` from CPU (or DMA?)
+ // 2. calculate `padded_length` from `message_length`
+ // 3. Check if tx_count == message_length, then go to 5
+ // 4. Receiving FIFO input (hand over to fifo output)
+ // 5. Padding bit 1 (8'h80) followed by 8'h00 if needed
+ // 6. Padding with length (high -> low)
+
+ // State Machine
+ typedef enum logic [2:0] {
+ StIdle, // fin_full to prevent unwanted FIFO write
+ StFifoReceive, // Check tx_count == message_length
+ StPad80, // 8'h 80 + 8'h 00 X N
+ StPad00,
+ StLenHi,
+ StLenLo
+ } pad_st_e;
+
+ pad_st_e st_q, st_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ st_q <= StIdle;
+ end else begin
+ st_q <= st_d;
+ end
+ end
+
+ // Next state
+ always_comb begin
+ shaf_rvalid = 1'b0;
+ inc_txcount = 1'b0;
+ sel_data = FifoIn;
+ fifo_rready = 1'b0;
+
+ st_d = StIdle;
+
+ unique case (st_q)
+ StIdle: begin
+ sel_data = FifoIn;
+ shaf_rvalid = 1'b0;
+
+ if (sha_en && hash_start) begin
+ inc_txcount = 1'b0;
+
+ st_d = StFifoReceive;
+ end else begin
+ st_d = StIdle;
+ end
+ end
+
+ StFifoReceive: begin
+ sel_data = FifoIn;
+
+ if (fifo_partial && fifo_rvalid) begin
+ // End of the message, assume hash_process_flag is set
+ shaf_rvalid = 1'b0; // Update entry at StPad80
+ inc_txcount = 1'b0;
+ fifo_rready = 1'b0;
+
+ st_d = StPad80;
+ end else if (!hash_process_flag) begin
+ fifo_rready = shaf_rready;
+ shaf_rvalid = fifo_rvalid;
+ inc_txcount = shaf_rready;
+
+ st_d = StFifoReceive;
+ end else if (tx_count == message_length) begin
+ // already received all msg and was waiting process flag
+ shaf_rvalid = 1'b0;
+ inc_txcount = 1'b0;
+ fifo_rready = 1'b0;
+
+ st_d = StPad80;
+ end else begin
+ shaf_rvalid = fifo_rvalid;
+ fifo_rready = shaf_rready; // 0 always
+ inc_txcount = shaf_rready; // 0 always
+
+ st_d = StFifoReceive;
+ end
+ end
+
+ StPad80: begin
+ sel_data = Pad80;
+
+ shaf_rvalid = 1'b1;
+ fifo_rready = shaf_rready && |message_length[4:3]; // Only when partial
+
+ // exactly 96 bits left, do not need to pad00's
+ if (shaf_rready && txcnt_eq_1a0) begin
+ st_d = StLenHi;
+ inc_txcount = 1'b1;
+ // it does not matter if value is < or > than 416 bits. If it's the former, 00 pad until
+ // length field. If >, then the next chunk will contain the length field with appropriate
+ // 0 padding.
+ end else if (shaf_rready && !txcnt_eq_1a0) begin
+ st_d = StPad00;
+ inc_txcount = 1'b1;
+ end else begin
+ st_d = StPad80;
+ inc_txcount = 1'b0;
+ end
+
+ // # Below part is temporal code to speed up the SHA by 16 clocks per chunk
+ // # (80 clk --> 64 clk)
+ // # leaving this as a reference but needs to verify it.
+ //if (shaf_rready && !txcnt_eq_1a0) begin
+ // st_d = StPad00;
+ //
+ // inc_txcount = 1'b1;
+ // shaf_rvalid = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
+ // fifo_rready = (msg_word_aligned) ? 1'b0 : 1'b1;
+ //end else if (!shaf_rready && !txcnt_eq_1a0) begin
+ // st_d = StPad80;
+ //
+ // inc_txcount = 1'b0;
+ // shaf_rvalid = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
+ //
+ //end else if (shaf_rready && txcnt_eq_1a0) begin
+ // st_d = StLenHi;
+ // inc_txcount = 1'b1;
+ //end else begin
+ // // !shaf_rready && txcnt_eq_1a0 , just wait until fifo_rready asserted
+ // st_d = StPad80;
+ // inc_txcount = 1'b0;
+ //end
+ end
+
+ StPad00: begin
+ sel_data = Pad00;
+ shaf_rvalid = 1'b1;
+
+ if (shaf_rready) begin
+ inc_txcount = 1'b1;
+
+ if (txcnt_eq_1a0) begin
+ st_d = StLenHi;
+ end else begin
+ st_d = StPad00;
+ end
+ end else begin
+ st_d = StPad00;
+ end
+ end
+
+ StLenHi: begin
+ sel_data = LenHi;
+ shaf_rvalid = 1'b1;
+
+ if (shaf_rready) begin
+ st_d = StLenLo;
+
+ inc_txcount = 1'b1;
+ end else begin
+ st_d = StLenHi;
+
+ inc_txcount = 1'b0;
+ end
+ end
+
+ StLenLo: begin
+ sel_data = LenLo;
+ shaf_rvalid = 1'b1;
+
+ if (shaf_rready) begin
+ st_d = StIdle;
+
+ inc_txcount = 1'b1;
+ end else begin
+ st_d = StLenLo;
+
+ inc_txcount = 1'b0;
+ end
+ end
+
+ default: begin
+ st_d = StIdle;
+ end
+ endcase
+ end
+
+ // tx_count
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ tx_count <= '0;
+ end else if (hash_start) begin
+ tx_count <= '0;
+ end else if (inc_txcount) begin
+ tx_count[63:5] <= tx_count[63:5] + 1'b1;
+ end
+ end
+
+ // State machine is in Idle only when it meets tx_count == message length
+ assign msg_feed_complete = hash_process_flag && (st_q == StIdle);
+
+endmodule
diff --git a/EDA-3283/rtl/tlul_adapter_reg.sv b/EDA-3283/rtl/tlul_adapter_reg.sv
new file mode 100644
index 00000000..5fcf48bf
--- /dev/null
+++ b/EDA-3283/rtl/tlul_adapter_reg.sv
@@ -0,0 +1,138 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Tile-Link UL adapter for Register interface
+ */
+
+module tlul_adapter_reg import tlul_pkg::*; #(
+ parameter int RegAw = 8,
+ parameter int EnableDataIntgGen = 0,
+ parameter int RegDw = 32, // Shall be matched with TL_DW
+ localparam int RegBw = RegDw/8
+) (
+ input clk_i,
+ input rst_ni,
+
+ // TL-UL interface
+ input tl_h2d_t tl_i,
+ output tl_d2h_t tl_o,
+
+ // Register interface
+ output logic re_o,
+ output logic we_o,
+ output logic [RegAw-1:0] addr_o,
+ output logic [RegDw-1:0] wdata_o,
+ output logic [RegBw-1:0] be_o,
+ input [RegDw-1:0] rdata_i,
+ input error_i
+);
+
+ localparam int IW = $bits(tl_i.a_source);
+ localparam int SZW = $bits(tl_i.a_size);
+
+ logic outstanding; // Indicates current request is pending
+ logic a_ack, d_ack;
+
+ logic [RegDw-1:0] rdata;
+ logic error, err_internal;
+
+ logic addr_align_err; // Size and alignment
+ logic malformed_meta_err; // User signal format error or unsupported
+ logic tl_err; // Common TL-UL error checker
+
+ logic [IW-1:0] reqid;
+ logic [SZW-1:0] reqsz;
+ tl_d_op_e rspop;
+
+ logic rd_req, wr_req;
+
+ assign a_ack = tl_i.a_valid & tl_o.a_ready;
+ assign d_ack = tl_o.d_valid & tl_i.d_ready;
+ // Request signal
+ assign wr_req = a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData));
+ assign rd_req = a_ack & (tl_i.a_opcode == Get);
+
+ assign we_o = wr_req & ~err_internal;
+ assign re_o = rd_req & ~err_internal;
+ assign addr_o = {tl_i.a_address[RegAw-1:2], 2'b00}; // generate always word-align
+ assign wdata_o = tl_i.a_data;
+ assign be_o = tl_i.a_mask;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) outstanding <= 1'b0;
+ else if (a_ack) outstanding <= 1'b1;
+ else if (d_ack) outstanding <= 1'b0;
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ reqid <= '0;
+ reqsz <= '0;
+ rspop <= AccessAck;
+ end else if (a_ack) begin
+ reqid <= tl_i.a_source;
+ reqsz <= tl_i.a_size;
+ // Return AccessAckData regardless of error
+ rspop <= (rd_req) ? AccessAckData : AccessAck ;
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ rdata <= '0;
+ error <= 1'b0;
+ end else if (a_ack) begin
+ rdata <= (err_internal) ? '1 : rdata_i;
+ error <= error_i | err_internal;
+ end
+ end
+
+ assign tl_o = '{
+ a_ready: ~outstanding,
+ d_valid: outstanding,
+ d_opcode: rspop,
+ d_param: '0,
+ d_size: reqsz,
+ d_source: reqid,
+ d_sink: '0,
+ d_data: rdata,
+ d_user: '0,
+ d_error: error
+ };
+
+ ////////////////////
+ // Error Handling //
+ ////////////////////
+ assign err_internal = addr_align_err | malformed_meta_err | tl_err ;
+
+ // malformed_meta_err
+ // Raised if not supported feature is turned on or user signal has malformed
+ //assign malformed_meta_err = (tl_i.a_user.parity_en == 1'b1);
+ assign malformed_meta_err = 1'b0;
+
+ // addr_align_err
+ // Raised if addr isn't aligned with the size
+ // Read size error is checked in tlul_assert.sv
+ // Here is it added due to the limitation of register interface.
+ always_comb begin
+ if (wr_req) begin
+ // Only word-align is accepted based on comportability spec
+ addr_align_err = |tl_i.a_address[1:0];
+ end else begin
+ // No request
+ addr_align_err = 1'b0;
+ end
+ end
+
+ // tl_err : separate checker
+ tlul_err u_err (
+ .clk_i,
+ .rst_ni,
+ .tl_i,
+ .err_o (tl_err)
+ );
+
+endmodule
diff --git a/EDA-3283/rtl/tlul_adapter_sram.sv b/EDA-3283/rtl/tlul_adapter_sram.sv
new file mode 100644
index 00000000..c4c338cc
--- /dev/null
+++ b/EDA-3283/rtl/tlul_adapter_sram.sv
@@ -0,0 +1,351 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Tile-Link UL adapter for SRAM-like devices
+ *
+ * - Intentionally omitted BaseAddr in case of multiple memory maps are used in a SoC,
+ * it means that aliasing can happen if target device size in TL-UL crossbar is bigger
+ * than SRAM size
+ */
+module tlul_adapter_sram #(
+ parameter int SramAw = 12,
+ parameter int SramDw = 32, // Must be multiple of the TL width
+ parameter int Outstanding = 1, // Only one request is accepted
+ parameter bit ByteAccess = 1, // 1: true, 0: false
+ parameter bit ErrOnWrite = 0, // 1: Writes not allowed, automatically error
+ parameter bit ErrOnRead = 0, // 1: Reads not allowed, automatically error
+ parameter int CmdIntgCheck =1,
+ parameter int EnableRspIntgGen = 1,
+ parameter int EnableDataIntgGen =1
+
+) (
+ input clk_i,
+ input rst_ni,
+
+ // TL-UL interface
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // SRAM interface
+ output logic req_o,
+ input gnt_i,
+ output logic we_o,
+ output logic [SramAw-1:0] addr_o,
+ output logic [SramDw-1:0] wdata_o,
+ output logic [SramDw-1:0] wmask_o,
+ input [SramDw-1:0] rdata_i,
+ input rvalid_i,
+ input [1:0] rerror_i // 2 bit error [1]: Uncorrectable, [0]: Correctable
+);
+
+ import tlul_pkg::*;
+
+ localparam int SramByte = SramDw/8;
+ localparam int DataBitWidth = prim_util_pkg::vbits(SramByte);
+ localparam int WidthMult = SramDw / top_pkg::TL_DW;
+ localparam int WoffsetWidth = (SramByte == top_pkg::TL_DBW) ? 1 :
+ DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW);
+
+ typedef struct packed {
+ logic [top_pkg::TL_DBW-1:0] mask ; // Byte mask within the TL-UL word
+ logic [WoffsetWidth-1:0] woffset ; // Offset of the TL-UL word within the SRAM word
+ } sram_req_t ;
+
+ typedef enum logic [1:0] {
+ OpWrite,
+ OpRead,
+ OpUnknown
+ } req_op_e ;
+
+ typedef struct packed {
+ req_op_e op ;
+ logic error ;
+ logic [top_pkg::TL_SZW-1:0] size ;
+ logic [top_pkg::TL_AIW-1:0] source ;
+ } req_t ;
+
+ typedef struct packed {
+ logic [SramDw-1:0] data ;
+ logic error ;
+ } rsp_t ;
+
+ localparam int SramReqFifoWidth = $bits(sram_req_t) ;
+ localparam int ReqFifoWidth = $bits(req_t) ;
+ localparam int RspFifoWidth = $bits(rsp_t) ;
+
+ // FIFO signal in case OutStand is greater than 1
+ // If request is latched, {write, source} is pushed to req fifo.
+ // Req fifo is popped when D channel is acknowledged (v & r)
+ // D channel valid is asserted if it is write request or rsp fifo not empty if read.
+ logic reqfifo_wvalid, reqfifo_wready;
+ logic reqfifo_rvalid, reqfifo_rready;
+ req_t reqfifo_wdata, reqfifo_rdata;
+
+ logic sramreqfifo_wvalid, sramreqfifo_wready;
+ logic sramreqfifo_rready;
+ sram_req_t sramreqfifo_wdata, sramreqfifo_rdata;
+
+ logic rspfifo_wvalid, rspfifo_wready;
+ logic rspfifo_rvalid, rspfifo_rready;
+ rsp_t rspfifo_wdata, rspfifo_rdata;
+
+ logic error_internal; // Internal protocol error checker
+ logic wr_attr_error;
+ logic wr_vld_error;
+ logic rd_vld_error;
+ logic tlul_error; // Error from `tlul_err` module
+
+ logic a_ack, d_ack, sram_ack;
+ assign a_ack = tl_i.a_valid & tl_o.a_ready ;
+ assign d_ack = tl_o.d_valid & tl_i.d_ready ;
+ assign sram_ack = req_o & gnt_i ;
+
+ // Valid handling
+ logic d_valid, d_error;
+ always_comb begin
+ d_valid = 1'b0;
+
+ if (reqfifo_rvalid) begin
+ if (reqfifo_rdata.error) begin
+ // Return error response. Assume no request went out to SRAM
+ d_valid = 1'b1;
+ end else if (reqfifo_rdata.op == OpRead) begin
+ d_valid = rspfifo_rvalid;
+ end else begin
+ // Write without error
+ d_valid = 1'b1;
+ end
+ end else begin
+ d_valid = 1'b0;
+ end
+ end
+
+ always_comb begin
+ d_error = 1'b0;
+
+ if (reqfifo_rvalid) begin
+ if (reqfifo_rdata.op == OpRead) begin
+ d_error = rspfifo_rdata.error | reqfifo_rdata.error;
+ end else begin
+ d_error = reqfifo_rdata.error;
+ end
+ end else begin
+ d_error = 1'b0;
+ end
+ end
+
+ assign tl_o = '{
+ d_valid : d_valid ,
+ d_opcode : (d_valid && reqfifo_rdata.op != OpRead) ? AccessAck : AccessAckData,
+ d_param : '0,
+ d_size : (d_valid) ? reqfifo_rdata.size : '0,
+ d_source : (d_valid) ? reqfifo_rdata.source : '0,
+ d_sink : 1'b0,
+ d_data : (d_valid && rspfifo_rvalid && reqfifo_rdata.op == OpRead)
+ ? rspfifo_rdata.data : '0,
+ d_user : '0,
+ d_error : d_valid && d_error,
+
+ a_ready : (gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready
+ };
+
+ // a_ready depends on the FIFO full condition and grant from SRAM (or SRAM arbiter)
+ // assemble response, including read response, write response, and error for unsupported stuff
+
+ // Output to SRAM:
+ // Generate request only when no internal error occurs. If error occurs, the request should be
+ // dropped and returned error response to the host. So, error to be pushed to reqfifo.
+ // In this case, it is assumed the request is granted (may cause ordering issue later?)
+ assign req_o = tl_i.a_valid & reqfifo_wready & ~error_internal;
+ assign we_o = tl_i.a_valid & logic'(tl_i.a_opcode inside {PutFullData, PutPartialData});
+ assign addr_o = (tl_i.a_valid) ? tl_i.a_address[DataBitWidth+:SramAw] : '0;
+
+ // Support SRAMs wider than the TL-UL word width by mapping the parts of the
+ // TL-UL address which are more fine-granular than the SRAM width to the
+ // SRAM write mask.
+ logic [WoffsetWidth-1:0] woffset;
+ if (top_pkg::TL_DW != SramDw) begin : gen_wordwidthadapt
+ assign woffset = tl_i.a_address[DataBitWidth-1:prim_util_pkg::vbits(top_pkg::TL_DBW)];
+ end else begin : gen_no_wordwidthadapt
+ assign woffset = '0;
+ end
+
+ // Convert byte mask to SRAM bit mask for writes, and only forward valid data
+ logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wmask_int;
+ logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wdata_int;
+
+ always_comb begin
+ wmask_int = '0;
+ wdata_int = '0;
+
+ if (tl_i.a_valid) begin
+ for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
+ wmask_int[woffset][8*i +: 8] = {8{tl_i.a_mask[i]}};
+ wdata_int[woffset][8*i +: 8] = (tl_i.a_mask[i] && we_o) ? tl_i.a_data[8*i+:8] : '0;
+ end
+ end
+ end
+
+ assign wmask_o = wmask_int;
+ assign wdata_o = wdata_int;
+
+ // Begin: Request Error Detection
+
+ // wr_attr_error: Check if the request size,mask are permitted.
+ // Basic check of size, mask, addr align is done in tlul_err module.
+ // Here it checks any partial write if ByteAccess isn't allowed.
+ assign wr_attr_error = (tl_i.a_opcode == PutFullData || tl_i.a_opcode == PutPartialData) ?
+ (ByteAccess == 0) ? (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0 :
+ 1'b0;
+
+ if (ErrOnWrite == 1) begin : gen_no_writes
+ assign wr_vld_error = tl_i.a_opcode != Get;
+ end else begin : gen_writes_allowed
+ assign wr_vld_error = 1'b0;
+ end
+
+ if (ErrOnRead == 1) begin: gen_no_reads
+ assign rd_vld_error = tl_i.a_opcode == Get;
+ end else begin : gen_reads_allowed
+ assign rd_vld_error = 1'b0;
+ end
+
+ tlul_err u_err (
+ .clk_i,
+ .rst_ni,
+ .tl_i,
+ .err_o (tlul_error)
+ );
+
+ assign error_internal = wr_attr_error | wr_vld_error | rd_vld_error | tlul_error;
+ // End: Request Error Detection
+
+ assign reqfifo_wvalid = a_ack ; // Push to FIFO only when granted
+ assign reqfifo_wdata = '{
+ op: (tl_i.a_opcode != Get) ? OpWrite : OpRead, // To return AccessAck for opcode error
+ error: error_internal,
+ size: tl_i.a_size,
+ source: tl_i.a_source
+ }; // Store the request only. Doesn't have to store data
+ assign reqfifo_rready = d_ack ;
+
+ // push together with ReqFIFO, pop upon returning read
+ assign sramreqfifo_wdata = '{
+ mask : tl_i.a_mask,
+ woffset : woffset
+ };
+ assign sramreqfifo_wvalid = sram_ack & ~we_o;
+ assign sramreqfifo_rready = rspfifo_wvalid;
+
+ assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid;
+
+ // Make sure only requested bytes are forwarded
+ logic [WidthMult-1:0][top_pkg::TL_DW-1:0] rdata;
+ logic [WidthMult-1:0][top_pkg::TL_DW-1:0] rmask;
+ //logic [SramDw-1:0] rmask;
+ logic [top_pkg::TL_DW-1:0] rdata_tlword;
+
+ always_comb begin
+ rmask = '0;
+ for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
+ rmask[sramreqfifo_rdata.woffset][8*i +: 8] = {8{sramreqfifo_rdata.mask[i]}};
+ end
+ end
+
+ assign rdata = rdata_i & rmask;
+ assign rdata_tlword = rdata[sramreqfifo_rdata.woffset];
+
+ assign rspfifo_wdata = '{
+ data : rdata_tlword,
+ error: rerror_i[1] // Only care for Uncorrectable error
+ };
+ assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error)
+ ? reqfifo_rready : 1'b0 ;
+
+ // This module only cares about uncorrectable errors.
+ logic unused_rerror;
+ assign unused_rerror = rerror_i[0];
+
+ // FIFO instance: REQ, RSP
+
+ // ReqFIFO is to store the Access type to match to the Response data.
+ // For instance, SRAM accepts the write request but doesn't return the
+ // acknowledge. In this case, it may be hard to determine when the D
+ // response for the write data should send out if reads/writes are
+ // interleaved. So, to make it in-order (even TL-UL allows out-of-order
+ // responses), storing the request is necessary. And if the read entry
+ // is write op, it is safe to return the response right away. If it is
+ // read reqeust, then D response is waiting until read data arrives.
+
+ // Notes:
+ // The oustanding+1 allows the reqfifo to absorb back to back transactions
+ // without any wait states. Alternatively, the depth can be kept as
+ // oustanding as long as the outgoing ready is qualified with the acceptance
+ // of the response in the same cycle. Doing so however creates a path from
+ // ready_i to ready_o, which may not be desireable.
+ prim_fifo_sync #(
+ .Width (ReqFifoWidth),
+ .Pass (1'b0),
+ .Depth (Outstanding)
+ ) u_reqfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0),
+ .wvalid(reqfifo_wvalid),
+ .wready(reqfifo_wready),
+ .wdata (reqfifo_wdata),
+ .depth (),
+ .rvalid(reqfifo_rvalid),
+ .rready(reqfifo_rready),
+ .rdata (reqfifo_rdata)
+ );
+
+ // sramreqfifo:
+ // While the ReqFIFO holds the request until it is sent back via TL-UL, the
+ // sramreqfifo only needs to hold the mask and word offset until the read
+ // data returns from memory.
+ prim_fifo_sync #(
+ .Width (SramReqFifoWidth),
+ .Pass (1'b0),
+ .Depth (Outstanding)
+ ) u_sramreqfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0),
+ .wvalid(sramreqfifo_wvalid),
+ .wready(sramreqfifo_wready),
+ .wdata (sramreqfifo_wdata),
+ .depth (),
+ .rvalid(),
+ .rready(sramreqfifo_rready),
+ .rdata (sramreqfifo_rdata)
+ );
+
+ // Rationale having #Outstanding depth in response FIFO.
+ // In normal case, if the host or the crossbar accepts the response data,
+ // response FIFO isn't needed. But if in any case it has a chance to be
+ // back pressured, the response FIFO should store the returned data not to
+ // lose the data from the SRAM interface. Remember, SRAM interface doesn't
+ // have back-pressure signal such as read_ready.
+ prim_fifo_sync #(
+ .Width (RspFifoWidth),
+ .Pass (1'b1),
+ .Depth (Outstanding)
+ ) u_rspfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0),
+ .wvalid(rspfifo_wvalid),
+ .wready(rspfifo_wready),
+ .wdata (rspfifo_wdata),
+ .depth (),
+ .rvalid(rspfifo_rvalid),
+ .rready(rspfifo_rready),
+ .rdata (rspfifo_rdata)
+ );
+
+
+endmodule
diff --git a/EDA-3283/rtl/tlul_cmd_intg_chk.sv b/EDA-3283/rtl/tlul_cmd_intg_chk.sv
new file mode 100644
index 00000000..a903e254
--- /dev/null
+++ b/EDA-3283/rtl/tlul_cmd_intg_chk.sv
@@ -0,0 +1,40 @@
+
+
+module tlul_cmd_intg_chk import tlul_pkg::*; (
+ // TL-UL interface
+ input tl_h2d_t tl_i,
+
+ // error output
+ output logic err_o
+);
+
+ logic [1:0] err;
+ logic data_err;
+ tl_h2d_cmd_intg_t cmd;
+ assign cmd = extract_h2d_cmd_intg(tl_i);
+
+ prim_secded_inv_64_57_dec u_chk (
+ .data_i({tl_i.a_user.cmd_intg, H2DCmdMaxWidth'(cmd)}),
+ .data_o(),
+ .syndrome_o(),
+ .err_o(err)
+ );
+
+ tlul_data_integ_dec u_tlul_data_integ_dec (
+ .data_intg_i({tl_i.a_user.data_intg, DataMaxWidth'(tl_i.a_data)}),
+ .data_err_o(data_err)
+ );
+
+ // error output is transactional, it is up to the instantiating module
+ // to determine if a permanent latch is feasible
+ logic wr_txn;
+ assign wr_txn = tl_i.a_valid &
+ (tl_i.a_opcode == PutFullData | tl_i.a_opcode == PutPartialData);
+
+ assign err_o = tl_i.a_valid & (|err | (|data_err));
+
+
+ logic unused_tl;
+ assign unused_tl = |tl_i;
+
+endmodule // tlul_payload_chk
diff --git a/EDA-3283/rtl/tlul_data_integ_dec.sv b/EDA-3283/rtl/tlul_data_integ_dec.sv
new file mode 100644
index 00000000..3db4312b
--- /dev/null
+++ b/EDA-3283/rtl/tlul_data_integ_dec.sv
@@ -0,0 +1,26 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Data integrity decoder for bus integrity scheme
+ */
+
+module tlul_data_integ_dec import tlul_pkg::*; (
+ // TL-UL interface
+ input [DataMaxWidth+DataIntgWidth-1:0] data_intg_i,
+ output logic data_err_o
+);
+
+ logic [1:0] data_err;
+ prim_secded_inv_39_32_dec u_data_chk (
+ .data_i(data_intg_i),
+ .data_o(),
+ .syndrome_o(),
+ .err_o(data_err)
+ );
+
+ assign data_err_o = |data_err;
+
+endmodule : tlul_data_integ_dec
diff --git a/EDA-3283/rtl/tlul_data_integ_enc.sv b/EDA-3283/rtl/tlul_data_integ_enc.sv
new file mode 100644
index 00000000..1ae5b521
--- /dev/null
+++ b/EDA-3283/rtl/tlul_data_integ_enc.sv
@@ -0,0 +1,21 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+/**
+ * Data integrity encoder for bus integrity scheme
+ */
+
+module tlul_data_integ_enc import tlul_pkg::*; (
+ // TL-UL interface
+ input [DataMaxWidth-1:0] data_i,
+ output logic [DataMaxWidth+DataIntgWidth-1:0] data_intg_o
+);
+
+ prim_secded_inv_39_32_enc u_data_gen (
+ .data_i,
+ .data_o(data_intg_o)
+ );
+
+endmodule : tlul_data_integ_enc
diff --git a/EDA-3283/rtl/tlul_err.sv b/EDA-3283/rtl/tlul_err.sv
new file mode 100644
index 00000000..67fd8307
--- /dev/null
+++ b/EDA-3283/rtl/tlul_err.sv
@@ -0,0 +1,92 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+
+module tlul_err import tlul_pkg::*; (
+ input clk_i,
+ input rst_ni,
+
+ input tl_h2d_t tl_i,
+
+ output logic err_o
+);
+
+ localparam int IW = $bits(tl_i.a_source);
+ localparam int SZW = $bits(tl_i.a_size);
+ localparam int DW = $bits(tl_i.a_data);
+ localparam int MW = $bits(tl_i.a_mask);
+ localparam int SubAW = $clog2(DW/8);
+
+ logic opcode_allowed, a_config_allowed;
+
+ logic op_full, op_partial, op_get;
+ assign op_full = (tl_i.a_opcode == PutFullData);
+ assign op_partial = (tl_i.a_opcode == PutPartialData);
+ assign op_get = (tl_i.a_opcode == Get);
+
+ // Anything that doesn't fall into the permitted category, it raises an error
+ assign err_o = ~(opcode_allowed & a_config_allowed);
+
+ // opcode check
+ assign opcode_allowed = (tl_i.a_opcode == PutFullData)
+ | (tl_i.a_opcode == PutPartialData)
+ | (tl_i.a_opcode == Get);
+
+ // a channel configuration check
+ logic addr_sz_chk; // address and size alignment check
+ logic mask_chk; // inactive lane a_mask check
+ logic fulldata_chk; // PutFullData should have size match to mask
+
+ logic [MW-1:0] mask;
+
+ assign mask = (1 << tl_i.a_address[SubAW-1:0]);
+
+ always_comb begin
+ addr_sz_chk = 1'b0;
+ mask_chk = 1'b0;
+ fulldata_chk = 1'b0; // Only valid when opcode is PutFullData
+
+ if (tl_i.a_valid) begin
+ unique case (tl_i.a_size)
+ 'h0: begin // 1 Byte
+ addr_sz_chk = 1'b1;
+ mask_chk = ~|(tl_i.a_mask & ~mask);
+ fulldata_chk = |(tl_i.a_mask & mask);
+ end
+
+ 'h1: begin // 2 Byte
+ addr_sz_chk = ~tl_i.a_address[0];
+ // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0]
+ mask_chk = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011)
+ : ~|(tl_i.a_mask & 4'b1100);
+ fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ;
+ end
+
+ 'h2: begin // 4 Byte
+ addr_sz_chk = ~|tl_i.a_address[SubAW-1:0];
+ mask_chk = 1'b1;
+ fulldata_chk = &tl_i.a_mask[3:0];
+ end
+
+ default: begin // else
+ addr_sz_chk = 1'b0;
+ mask_chk = 1'b0;
+ fulldata_chk = 1'b0;
+ end
+ endcase
+ end else begin
+ addr_sz_chk = 1'b0;
+ mask_chk = 1'b0;
+ fulldata_chk = 1'b0;
+ end
+ end
+
+ assign a_config_allowed = addr_sz_chk
+ & mask_chk
+ & (op_get | op_partial | fulldata_chk) ;
+
+
+endmodule
+
diff --git a/EDA-3283/rtl/tlul_err_resp.sv b/EDA-3283/rtl/tlul_err_resp.sv
new file mode 100644
index 00000000..d05e70ae
--- /dev/null
+++ b/EDA-3283/rtl/tlul_err_resp.sv
@@ -0,0 +1,59 @@
+
+// TL-UL error responder module, used by tlul_socket_1n to help response
+// to requests to no correct address space. Responses are always one cycle
+// after request with no stalling unless response is stuck on the way out.
+//`include "/home/sajjad/Shaheen-sv/src/buraq_core_top/ibex_core/tlul_pkg.sv"
+module tlul_err_resp (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_h_i,
+ output tlul_pkg::tl_d2h_t tl_h_o
+);
+ import tlul_pkg::*;
+ localparam int TL_AIW=8; // a_source, d_source
+
+ //tlul_pkg::tl_a_m_op get;
+ logic [$bits(tl_h_i.a_source)-1:0] err_source;
+ logic [$bits(tl_h_i.a_size)-1:0] err_size;
+ logic err_req_pending, err_rsp_pending;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_req_pending <= 1'b0;
+ //err_source <= {tlul_pkg::TL_AIW{1'b0}};
+ //err_opcode <= tlul_pkg::Get;
+ err_size <= '0;
+ end else if (tl_h_i.a_valid && tl_h_o.a_ready) begin
+ err_req_pending <= 1'b1;
+ err_source <= tl_h_i.a_source;
+ //err_opcode <= tl_h_i.a_opcode;
+ err_size <= tl_h_i.a_size;
+ end else if (!err_rsp_pending) begin
+ err_req_pending <= 1'b0;
+ end
+ end
+
+ assign tl_h_o.a_ready = ~err_rsp_pending & ~(err_req_pending & ~tl_h_i.d_ready);
+ assign tl_h_o.d_valid = err_req_pending | err_rsp_pending;
+ assign tl_h_o.d_data = '1; // Return all F
+ assign tl_h_o.d_source = err_source;
+ assign tl_h_o.d_sink = '0;
+ assign tl_h_o.d_param = '0;
+ assign tl_h_o.d_user.rsp_intg = '0;
+ assign tl_h_o.d_user.data_intg = '0;
+ assign tl_h_o.d_size = err_size;
+ //assign tl_h_o.d_opcode = (err_opcode == tlul_pkg::Get) ? AccessAckData : AccessAck;
+ assign tl_h_o.d_opcode = AccessAck;
+ assign tl_h_o.d_error = 1'b1;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_rsp_pending <= 1'b0;
+ end else if ((err_req_pending || err_rsp_pending) && !tl_h_i.d_ready) begin
+ err_rsp_pending <= 1'b1;
+ end else begin
+ err_rsp_pending <= 1'b0;
+ end
+ end
+
+endmodule
diff --git a/EDA-3283/rtl/tlul_fifo_sync.sv b/EDA-3283/rtl/tlul_fifo_sync.sv
new file mode 100644
index 00000000..de78dad7
--- /dev/null
+++ b/EDA-3283/rtl/tlul_fifo_sync.sv
@@ -0,0 +1,91 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// TL-UL fifo, used to add elasticity or an asynchronous clock crossing
+// to an TL-UL bus. This instantiates two FIFOs, one for the request side,
+// and one for the response side.
+
+module tlul_fifo_sync #(
+ parameter bit ReqPass = 1'b1,
+ parameter bit RspPass = 1'b1,
+ parameter int unsigned ReqDepth = 2,
+ parameter int unsigned RspDepth = 2,
+ parameter int unsigned SpareReqW = 1,
+ parameter int unsigned SpareRspW = 1
+) (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_h_i,
+ output tlul_pkg::tl_d2h_t tl_h_o,
+ output tlul_pkg::tl_h2d_t tl_d_o,
+ input tlul_pkg::tl_d2h_t tl_d_i,
+ input [SpareReqW-1:0] spare_req_i,
+ output [SpareReqW-1:0] spare_req_o,
+ input [SpareRspW-1:0] spare_rsp_i,
+ output [SpareRspW-1:0] spare_rsp_o
+);
+
+ // Put everything on the request side into one FIFO
+ localparam int unsigned REQFIFO_WIDTH = $bits(tlul_pkg::tl_h2d_t) -2 + SpareReqW;
+
+ prim_fifo_sync #(.Width(REQFIFO_WIDTH), .Pass(ReqPass), .Depth(ReqDepth)) reqfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0 ),
+ .wvalid (tl_h_i.a_valid),
+ .wready (tl_h_o.a_ready),
+ .wdata ({tl_h_i.a_opcode ,
+ tl_h_i.a_param ,
+ tl_h_i.a_size ,
+ tl_h_i.a_source ,
+ tl_h_i.a_address,
+ tl_h_i.a_mask ,
+ tl_h_i.a_data ,
+ tl_h_i.a_user ,
+ spare_req_i}),
+ .rvalid (tl_d_o.a_valid),
+ .rready (tl_d_i.a_ready),
+ .rdata ({tl_d_o.a_opcode ,
+ tl_d_o.a_param ,
+ tl_d_o.a_size ,
+ tl_d_o.a_source ,
+ tl_d_o.a_address,
+ tl_d_o.a_mask ,
+ tl_d_o.a_data ,
+ tl_d_o.a_user ,
+ spare_req_o}));
+
+ // Put everything on the response side into the other FIFO
+
+ localparam int unsigned RSPFIFO_WIDTH = $bits(tlul_pkg::tl_d2h_t) -2 + SpareRspW;
+
+ prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (1'b0 ),
+ .wvalid (tl_d_i.d_valid),
+ .wready (tl_d_o.d_ready),
+ .wdata ({tl_d_i.d_opcode,
+ tl_d_i.d_param ,
+ tl_d_i.d_size ,
+ tl_d_i.d_source,
+ tl_d_i.d_sink ,
+ (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
+ {top_pkg::TL_DW{1'b0}} ,
+ tl_d_i.d_user ,
+ tl_d_i.d_error ,
+ spare_rsp_i}),
+ .rvalid (tl_h_o.d_valid),
+ .rready (tl_h_i.d_ready),
+ .rdata ({tl_h_o.d_opcode,
+ tl_h_o.d_param ,
+ tl_h_o.d_size ,
+ tl_h_o.d_source,
+ tl_h_o.d_sink ,
+ tl_h_o.d_data ,
+ tl_h_o.d_user ,
+ tl_h_o.d_error ,
+ spare_rsp_o}));
+
+endmodule
diff --git a/EDA-3283/rtl/tlul_pkg.sv b/EDA-3283/rtl/tlul_pkg.sv
new file mode 100644
index 00000000..0afd59d5
--- /dev/null
+++ b/EDA-3283/rtl/tlul_pkg.sv
@@ -0,0 +1,174 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package tlul_pkg;
+
+ // this can be either PPC or BINTREE
+ // there is no functional difference, but timing and area behavior is different
+ // between the two instances. PPC can result in smaller implementations when timing
+ // is not critical, whereas BINTREE is favorable when timing pressure is high (but this
+ // may also result in a larger implementation). on FPGA targets, BINTREE is favorable
+ // both in terms of area and timing.
+ parameter ArbiterImpl = "PPC";
+
+ typedef enum logic [2:0] {
+ PutFullData = 3'h 0,
+ PutPartialData = 3'h 1,
+ Get = 3'h 4
+ } tl_a_op_e;
+
+ typedef enum logic [2:0] {
+ AccessAck = 3'h 0,
+ AccessAckData = 3'h 1
+ } tl_d_op_e;
+
+ parameter int H2DCmdMaxWidth = 57;
+ parameter int H2DCmdIntgWidth = 7;
+ parameter int H2DCmdFullWidth = H2DCmdMaxWidth + H2DCmdIntgWidth;
+ parameter int D2HRspMaxWidth = 57;
+ parameter int D2HRspIntgWidth = 7;
+ parameter int D2HRspFullWidth = D2HRspMaxWidth + D2HRspIntgWidth;
+ parameter int DataMaxWidth = 32;
+ parameter int DataIntgWidth = 7;
+ parameter int DataFullWidth = DataMaxWidth + DataIntgWidth;
+
+ typedef struct packed {
+ logic [4:0] rsvd;
+ prim_mubi_pkg::mubi4_t instr_type;
+ logic [H2DCmdIntgWidth-1:0] cmd_intg;
+ logic [DataIntgWidth-1:0] data_intg;
+ } tl_a_user_t;
+
+ parameter tl_a_user_t TL_A_USER_DEFAULT = '{
+ rsvd: '0,
+ instr_type: prim_mubi_pkg::MuBi4False,
+ cmd_intg: {H2DCmdIntgWidth{1'b1}},
+ data_intg: {DataIntgWidth{1'b1}}
+ };
+
+ typedef struct packed {
+ prim_mubi_pkg::mubi4_t instr_type;
+ logic [top_pkg::TL_AW-1:0] addr;
+ tl_a_op_e opcode;
+ logic [top_pkg::TL_DBW-1:0] mask;
+ } tl_h2d_cmd_intg_t;
+
+ typedef struct packed {
+ logic a_valid;
+ tl_a_op_e a_opcode;
+ logic [2:0] a_param;
+ logic [top_pkg::TL_SZW-1:0] a_size;
+ logic [top_pkg::TL_AIW-1:0] a_source;
+ logic [top_pkg::TL_AW-1:0] a_address;
+ logic [top_pkg::TL_DBW-1:0] a_mask;
+ logic [top_pkg::TL_DW-1:0] a_data;
+ tl_a_user_t a_user;
+
+ logic d_ready;
+ } tl_h2d_t;
+
+ localparam tl_h2d_t TL_H2D_DEFAULT = '{
+ d_ready: 1'b1,
+ a_opcode: tl_a_op_e'('0),
+ a_user: TL_A_USER_DEFAULT,
+ default: '0
+ };
+
+ typedef struct packed {
+ logic [D2HRspIntgWidth-1:0] rsp_intg;
+ logic [DataIntgWidth-1:0] data_intg;
+ } tl_d_user_t;
+
+ parameter tl_d_user_t TL_D_USER_DEFAULT = '{
+ rsp_intg: {D2HRspIntgWidth{1'b1}},
+ data_intg: {DataIntgWidth{1'b1}}
+ };
+
+ typedef struct packed {
+ logic d_valid;
+ tl_d_op_e d_opcode;
+ logic [2:0] d_param;
+ logic [top_pkg::TL_SZW-1:0] d_size; // Bouncing back a_size
+ logic [top_pkg::TL_AIW-1:0] d_source;
+ logic [top_pkg::TL_DIW-1:0] d_sink;
+ logic [top_pkg::TL_DW-1:0] d_data;
+ tl_d_user_t d_user;
+ logic d_error;
+
+ logic a_ready;
+
+ } tl_d2h_t;
+
+ typedef struct packed {
+ tl_d_op_e opcode;
+ logic [top_pkg::TL_SZW-1:0] size;
+ // Temporarily removed because source changes throughout the fabric
+ // and thus cannot be used for end-to-end checking.
+ // A different PR will propose a work-around (a hoaky one) to see if
+ // it gets the job done.
+ //logic [top_pkg::TL_AIW-1:0] source;
+ logic error;
+ } tl_d2h_rsp_intg_t;
+
+ localparam tl_d2h_t TL_D2H_DEFAULT = '{
+ a_ready: 1'b1,
+ d_opcode: tl_d_op_e'('0),
+ d_user: TL_D_USER_DEFAULT,
+ default: '0
+ };
+
+ // Check user for unsupported values
+ function automatic logic tl_a_user_chk(tl_a_user_t user);
+ logic malformed_err;
+ logic unused_user;
+ unused_user = |user;
+ malformed_err = prim_mubi_pkg::mubi4_test_invalid(user.instr_type);
+ return malformed_err;
+ endfunction // tl_a_user_chk
+
+ // extract variables used for command checking
+ function automatic tl_h2d_cmd_intg_t extract_h2d_cmd_intg(tl_h2d_t tl);
+ tl_h2d_cmd_intg_t payload;
+ logic unused_tlul;
+ unused_tlul = ^tl;
+ payload.addr = tl.a_address;
+ payload.opcode = tl.a_opcode;
+ payload.mask = tl.a_mask;
+ payload.instr_type = tl.a_user.instr_type;
+ return payload;
+ endfunction // extract_h2d_payload
+
+ // extract variables used for response checking
+ function automatic tl_d2h_rsp_intg_t extract_d2h_rsp_intg(tl_d2h_t tl);
+ tl_d2h_rsp_intg_t payload;
+ logic unused_tlul;
+ unused_tlul = ^tl;
+ payload.opcode = tl.d_opcode;
+ payload.size = tl.d_size;
+ //payload.source = tl.d_source;
+ payload.error = tl.d_error;
+ return payload;
+ endfunction // extract_d2h_rsp_intg
+
+ // calculate ecc for command checking
+ function automatic logic [H2DCmdIntgWidth-1:0] get_cmd_intg(tl_h2d_t tl);
+ logic [H2DCmdIntgWidth-1:0] cmd_intg;
+ logic [H2DCmdMaxWidth-1:0] unused_cmd_payload;
+ tl_h2d_cmd_intg_t cmd;
+ cmd = extract_h2d_cmd_intg(tl);
+ {cmd_intg, unused_cmd_payload} =
+ prim_secded_pkg::prim_secded_inv_64_57_enc(H2DCmdMaxWidth'(cmd));
+ return cmd_intg;
+ endfunction // get_cmd_intg
+
+ // calculate ecc for data checking
+ function automatic logic [DataIntgWidth-1:0] get_data_intg(logic [top_pkg::TL_DW-1:0] data);
+ logic [DataIntgWidth-1:0] data_intg;
+ logic [top_pkg::TL_DW-1:0] unused_data;
+ {data_intg, unused_data} = prim_secded_pkg::prim_secded_inv_39_32_enc(data);
+ return data_intg;
+ endfunction // get_data_intg
+
+endpackage
diff --git a/EDA-3283/rtl/tlul_rsp_intg_gen.sv b/EDA-3283/rtl/tlul_rsp_intg_gen.sv
new file mode 100644
index 00000000..fbcedebb
--- /dev/null
+++ b/EDA-3283/rtl/tlul_rsp_intg_gen.sv
@@ -0,0 +1,54 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+/**
+ * Tile-Link UL response integrity generator
+ */
+
+module tlul_rsp_intg_gen import tlul_pkg::*; #(
+ parameter bit EnableRspIntgGen = 1'b1,
+ parameter bit EnableDataIntgGen = 1'b1
+) (
+ // TL-UL interface
+ input tl_d2h_t tl_i,
+ output tl_d2h_t tl_o
+);
+
+ logic [D2HRspIntgWidth-1:0] rsp_intg;
+ if (EnableRspIntgGen) begin : gen_rsp_intg
+ tl_d2h_rsp_intg_t rsp;
+ logic [D2HRspMaxWidth-1:0] unused_payload;
+
+ assign rsp = extract_d2h_rsp_intg(tl_i);
+
+ prim_secded_inv_64_57_enc u_rsp_gen (
+ .data_i(D2HRspMaxWidth'(rsp)),
+ .data_o({rsp_intg, unused_payload})
+ );
+ end else begin : gen_passthrough_rsp_intg
+ assign rsp_intg = tl_i.d_user.rsp_intg;
+ end
+
+ logic [DataIntgWidth-1:0] data_intg;
+ if (EnableDataIntgGen) begin : gen_data_intg
+ logic [DataMaxWidth-1:0] unused_data;
+ tlul_data_integ_enc u_tlul_data_integ_enc (
+ .data_i(DataMaxWidth'(tl_i.d_data)),
+ .data_intg_o({data_intg, unused_data})
+ );
+ end else begin : gen_passthrough_data_intg
+ assign data_intg = tl_i.d_user.data_intg;
+ end
+
+ always_comb begin
+ tl_o = tl_i;
+ tl_o.d_user.rsp_intg = rsp_intg;
+ tl_o.d_user.data_intg = data_intg;
+ end
+
+ logic unused_tl;
+ assign unused_tl = ^tl_i;
+
+
+endmodule // tlul_rsp_intg_gen
diff --git a/EDA-3283/rtl/tlul_socket_1n.sv b/EDA-3283/rtl/tlul_socket_1n.sv
new file mode 100644
index 00000000..fd96a64e
--- /dev/null
+++ b/EDA-3283/rtl/tlul_socket_1n.sv
@@ -0,0 +1,213 @@
+
+// TL-UL socket 1:N module
+//
+// configuration settings
+// device_count: 4
+//
+// Verilog parameters
+// HReqPass: if 1 then host requests can pass through on empty fifo,
+// default 1
+// HRspPass: if 1 then host responses can pass through on empty fifo,
+// default 1
+// DReqPass: (one per device_count) if 1 then device i requests can
+// pass through on empty fifo, default 1
+// DRspPass: (one per device_count) if 1 then device i responses can
+// pass through on empty fifo, default 1
+// HReqDepth: Depth of host request FIFO, default 2
+// HRspDepth: Depth of host response FIFO, default 2
+// DReqDepth: (one per device_count) Depth of device i request FIFO,
+// default 2
+// DRspDepth: (one per device_count) Depth of device i response FIFO,
+// default 2
+//
+// Requests must stall to one device until all responses from other devices
+// have returned. Need to keep a counter of all outstanding requests and
+// wait until that counter is zero before switching devices.
+//
+// This module will return a request error if the input value of 'dev_select_i'
+// is not within the range 0..N-1. Thus the instantiator of the socket
+// can indicate error by any illegal value of dev_select_i. 4'b1111 is
+// recommended for visibility
+//
+// The maximum value of N is 15
+
+
+module tlul_socket_1n #(
+ parameter int unsigned N = 4,
+ parameter bit HReqPass = 1'b1,
+ parameter bit HRspPass = 1'b1,
+ parameter bit [N-1:0] DReqPass = {N{1'b1}},
+ parameter bit [N-1:0] DRspPass = {N{1'b1}},
+ parameter bit [3:0] HReqDepth = 4'h2,
+ parameter bit [3:0] HRspDepth = 4'h2,
+ parameter bit [N*4-1:0] DReqDepth = {N{4'h2}},
+ parameter bit [N*4-1:0] DRspDepth = {N{4'h2}},
+ localparam int unsigned NWD = $clog2(N+1) // derived parameter
+) (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_h_i,
+ output tlul_pkg::tl_d2h_t tl_h_o,
+ output tlul_pkg::tl_h2d_t tl_d_o [N],
+ input tlul_pkg::tl_d2h_t tl_d_i [N],
+ input [NWD-1:0] dev_select_i
+);
+
+ // Since our steering is done after potential FIFOing, we need to
+ // shove our device select bits into spare bits of reqfifo
+
+ // instantiate the host fifo, create intermediate bus 't'
+
+ // FIFO'd version of device select
+ logic [NWD-1:0] dev_select_t;
+
+ tlul_pkg::tl_h2d_t tl_t_o;
+ tlul_pkg::tl_d2h_t tl_t_i;
+
+ tlul_fifo_sync #(
+ .ReqPass(HReqPass),
+ .RspPass(HRspPass),
+ .ReqDepth(HReqDepth),
+ .RspDepth(HRspDepth),
+ .SpareReqW(NWD)
+ ) fifo_h (
+ .clk_i,
+ .rst_ni,
+ .tl_h_i,
+ .tl_h_o,
+ .tl_d_o (tl_t_o),
+ .tl_d_i (tl_t_i),
+ .spare_req_i (dev_select_i),
+ .spare_req_o (dev_select_t),
+ .spare_rsp_i (1'b0),
+ .spare_rsp_o ());
+
+
+ // We need to keep track of how many requests are outstanding,
+ // and to which device. New requests are compared to this and
+ // stall until that number is zero.
+ // Up to 256 ounstanding
+ localparam int MaxOutstanding = 256;
+ localparam int OutstandingW = $clog2(MaxOutstanding+1);
+ logic [OutstandingW-1:0] num_req_outstanding;
+ logic [NWD-1:0] dev_select_outstanding;
+ logic hold_all_requests;
+ logic accept_t_req, accept_t_rsp;
+
+ assign accept_t_req = tl_t_o.a_valid & tl_t_i.a_ready;
+ assign accept_t_rsp = tl_t_i.d_valid & tl_t_o.d_ready;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ num_req_outstanding <= '0;
+ dev_select_outstanding <= '0;
+ end else if (accept_t_req) begin
+ if (!accept_t_rsp) begin
+ num_req_outstanding <= num_req_outstanding + 1'b1;
+ end
+ dev_select_outstanding <= dev_select_t;
+ end else if (accept_t_rsp) begin
+ num_req_outstanding <= num_req_outstanding - 1'b1;
+ end
+ end
+
+ assign hold_all_requests =
+ (num_req_outstanding != '0) &
+ (dev_select_t != dev_select_outstanding);
+
+ // Make N copies of 't' request side with modified reqvalid, call
+ // them 'u[0]' .. 'u[n-1]'.
+
+ tlul_pkg::tl_h2d_t tl_u_o [N+1];
+ tlul_pkg::tl_d2h_t tl_u_i [N+1];
+
+ for (genvar i = 0 ; i < N ; i++) begin : gen_u_o
+ assign tl_u_o[i].a_valid = tl_t_o.a_valid &
+ (dev_select_t == NWD'(i)) &
+ ~hold_all_requests;
+ assign tl_u_o[i].a_opcode = tl_t_o.a_opcode;
+ assign tl_u_o[i].a_param = tl_t_o.a_param;
+ assign tl_u_o[i].a_size = tl_t_o.a_size;
+ assign tl_u_o[i].a_source = tl_t_o.a_source;
+ assign tl_u_o[i].a_address = tl_t_o.a_address;
+ assign tl_u_o[i].a_mask = tl_t_o.a_mask;
+ assign tl_u_o[i].a_data = tl_t_o.a_data;
+ assign tl_u_o[i].a_user = tl_t_o.a_user;
+ end
+
+ tlul_pkg::tl_d2h_t tl_t_p ;
+
+ // for the returning reqready, only look at the device we're addressing
+ logic hfifo_reqready;
+ always_comb begin
+ hfifo_reqready = tl_u_i[N].a_ready; // default to error
+ for (int idx = 0 ; idx < N ; idx++) begin
+ //if (dev_select_outstanding == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready;
+ if (dev_select_t == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready;
+ end
+ if (hold_all_requests) hfifo_reqready = 1'b0;
+ end
+ // Adding a_valid as a qualifier. This prevents the a_ready from having unknown value
+ // when the address is unknown and the Host TL-UL FIFO is bypass mode.
+ assign tl_t_i.a_ready = tl_t_o.a_valid & hfifo_reqready;
+
+ always_comb begin
+ tl_t_p = tl_u_i[N];
+ for (int idx = 0 ; idx < N ; idx++) begin
+ if (dev_select_outstanding == NWD'(idx)) tl_t_p = tl_u_i[idx];
+ end
+ end
+ assign tl_t_i.d_valid = tl_t_p.d_valid ;
+ assign tl_t_i.d_opcode = tl_t_p.d_opcode;
+ assign tl_t_i.d_param = tl_t_p.d_param ;
+ assign tl_t_i.d_size = tl_t_p.d_size ;
+ assign tl_t_i.d_source = tl_t_p.d_source;
+ assign tl_t_i.d_sink = tl_t_p.d_sink ;
+ assign tl_t_i.d_data = tl_t_p.d_data ;
+ assign tl_t_i.d_error = tl_t_p.d_error ;
+ assign tl_t_i.d_user = '0;
+
+
+ // accept responses from devices when selected if upstream is accepting
+ for (genvar i = 0 ; i < N+1 ; i++) begin : gen_u_o_d_ready
+ assign tl_u_o[i].d_ready = tl_t_o.d_ready;
+ end
+
+ // finally instantiate all device FIFOs and the error responder
+ for (genvar i = 0 ; i < N ; i++) begin : gen_dfifo
+ tlul_fifo_sync #(
+ .ReqPass(DReqPass[i]),
+ .RspPass(DRspPass[i]),
+ .ReqDepth(DReqDepth[i*4+:4]),
+ .RspDepth(DRspDepth[i*4+:4])
+ ) fifo_d (
+ .clk_i,
+ .rst_ni,
+ .tl_h_i (tl_u_o[i]),
+ .tl_h_o (tl_u_i[i]),
+ .tl_d_o (tl_d_o[i]),
+ .tl_d_i (tl_d_i[i]),
+ .spare_req_i (1'b0),
+ .spare_req_o (),
+ .spare_rsp_i (1'b0),
+ .spare_rsp_o ());
+ end
+
+ assign tl_u_o[N].a_valid = tl_t_o.a_valid &
+ (dev_select_t == NWD'(N)) &
+ ~hold_all_requests;
+ assign tl_u_o[N].a_opcode = tl_t_o.a_opcode;
+ assign tl_u_o[N].a_param = tl_t_o.a_param;
+ assign tl_u_o[N].a_size = tl_t_o.a_size;
+ assign tl_u_o[N].a_source = tl_t_o.a_source;
+ assign tl_u_o[N].a_address = tl_t_o.a_address;
+ assign tl_u_o[N].a_mask = tl_t_o.a_mask;
+ assign tl_u_o[N].a_data = tl_t_o.a_data;
+ assign tl_u_o[N].a_user = tl_t_o.a_user;
+ tlul_err_resp err_resp (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .tl_h_i (tl_u_o[N]),
+ .tl_h_o (tl_u_i[N]));
+
+endmodule
diff --git a/EDA-3283/rtl/top_pkg.sv b/EDA-3283/rtl/top_pkg.sv
new file mode 100644
index 00000000..3d62c73d
--- /dev/null
+++ b/EDA-3283/rtl/top_pkg.sv
@@ -0,0 +1,17 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package top_pkg;
+
+localparam int TL_AW=32;
+localparam int TL_DW=32; // = TL_DBW * 8; TL_DBW must be a power-of-two
+localparam int TL_AIW=8; // a_source, d_source
+localparam int TL_DIW=1; // d_sink
+localparam int TL_AUW=21; // a_user
+localparam int TL_DUW=14; // d_user
+localparam int TL_DBW=(TL_DW>>3);
+localparam int TL_SZW=$clog2($clog2(TL_DBW)+1);
+
+endpackage
diff --git a/EDA-3284/raptor_run.sh b/EDA-3284/raptor_run.sh
new file mode 100755
index 00000000..21948f5f
--- /dev/null
+++ b/EDA-3284/raptor_run.sh
@@ -0,0 +1,391 @@
+#!/bin/bash
+set -e
+main_path=$PWD
+start=`date +%s`
+
+
+design="kmac"
+ip_name="" #design_level
+#select tool (verilator, vcs, ghdl, iverilog)
+tool_name="iverilog"
+
+#simulation stages
+post_synth_sim=false
+post_route_sim=false
+bitstream_sim=false
+
+#raptor options
+device="GEMINI_COMPACT_104x68"
+
+strategy="delay" #(area, delay, mixed, none)
+
+add_constraint_file="./raptor_sdc.sdc" #Sets SDC + location constraints Constraints: set_pin_loc, set_mode, all SDC Standard commands
+
+verific_parser="" #(on/off)
+
+synthesis_type="" #(Yosys/QL/RS)
+
+custom_synth_script="" #(Uses a custom Yosys templatized script)
+
+synth_options="-effort high"
+ #synth_options