diff --git a/RTL_testcases/RTL_Benchmarks_Gap_Analysis/gpio_ip_litex/raptor_run.sh b/RTL_testcases/RTL_Benchmarks_Gap_Analysis/gpio_ip_litex/raptor_run.sh
index 2a10636a2..17caaa1e5 100755
--- a/RTL_testcases/RTL_Benchmarks_Gap_Analysis/gpio_ip_litex/raptor_run.sh
+++ b/RTL_testcases/RTL_Benchmarks_Gap_Analysis/gpio_ip_litex/raptor_run.sh
@@ -206,6 +206,8 @@ parse_cga exit 1; }
     [ -z "$custom_synth_script" ] && echo "" || echo "custom_synth_script $custom_synth_script">>raptor_tcl.tcl
     [ -z "$synth_options" ] && echo "" || echo "synth_options $synth_options">>raptor_tcl.tcl
     [ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl  
+    echo "setup_lec_sim">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl
     if [ "$post_synth_sim" == true ]; then 
         echo "# Open the input file in read mode">>raptor_tcl.tcl 
         echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" r]">>raptor_tcl.tcl 
@@ -259,6 +261,7 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  
@@ -272,6 +275,8 @@ parse_cga exit 1; }
         fi
     fi
 
+    [ -f rtl/sim.v ] && sed -i -e "s|MEM_FILE_PATH|$PWD/rtl|g" rtl/sim.v
+
     cd results_dir
     echo "Device: $device">>results.log
     echo "Strategy: $strategy">>results.log
diff --git a/RTL_testcases/RTL_Benchmarks_Gap_Analysis/gpio_ip_litex/rtl/sim.v b/RTL_testcases/RTL_Benchmarks_Gap_Analysis/gpio_ip_litex/rtl/sim.v
index 4c419a48f..265b5fc29 100644
--- a/RTL_testcases/RTL_Benchmarks_Gap_Analysis/gpio_ip_litex/rtl/sim.v
+++ b/RTL_testcases/RTL_Benchmarks_Gap_Analysis/gpio_ip_litex/rtl/sim.v
@@ -26,8 +26,8 @@ module sim (
 	output wire serial_sink_ready,
 	input  wire [7:0] serial_sink_data,
 	input  wire sys_clk,
-	output reg  [31:0] gpio_oe,
-	output reg  [31:0] gpio_o,
+	output reg  [31:0] gpio_oe=0,
+	output reg  [31:0] gpio_o=0,
 	input  wire [31:0] gpio_i
 );
 
@@ -3175,7 +3175,7 @@ end
 // Port 0 | Read: Sync  | Write: ---- | 
 reg [31:0] mem[0:5391];
 initial begin
-	$readmemh("mem.init", mem);
+	$readmemh("MEM_FILE_PATH/mem.init", mem);
 end
 reg [31:0] mem_dat0;
 always @(posedge sys_clk_1) begin
@@ -3190,7 +3190,7 @@ assign main_simsoc_dat_r = mem_dat0;
 // Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
 reg [31:0] mem_1[0:874];
 initial begin
-	$readmemh("mem_1.init", mem_1);
+	$readmemh("MEM_FILE_PATH/mem_1.init", mem_1);
 end
 reg [9:0] mem_1_adr0;
 always @(posedge sys_clk_1) begin
@@ -3213,7 +3213,7 @@ assign main_ram_dat_r = mem_1[mem_1_adr0];
 // Port 0 | Read: Sync  | Write: ---- | 
 reg [7:0] mem_2[0:36];
 initial begin
-	$readmemh("mem_2.init", mem_2);
+	$readmemh("MEM_FILE_PATH/mem_2.init", mem_2);
 end
 reg [5:0] mem_2_adr0;
 always @(posedge sys_clk_1) begin
@@ -3228,8 +3228,8 @@ assign builder_csr_bankarray_dat_r = mem_2[mem_2_adr0];
 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 10 
 // Port 1 | Read: Sync  | Write: ---- | 
 reg [9:0] storage[0:15];
-reg [9:0] storage_dat0;
-reg [9:0] storage_dat1;
+reg [9:0] storage_dat0='d0;
+reg [9:0] storage_dat1='d0;
 always @(posedge sys_clk_1) begin
 	if (main_uart_tx_fifo_wrport_we)
 		storage[main_uart_tx_fifo_wrport_adr] <= main_uart_tx_fifo_wrport_dat_w;