macro insertion delays should not count in ideal clock mode

[tspyrou]

This prevents the tool trying to fix setup and hold failures that wont exist when CTS balances the clock tree taking into account the macro insertion delay attribute that we add when making a timing model.

See precisionmoon's comment in The-OpenROAD-Project/OpenROAD#6181

untar and run mock-array-false-hold-violations.tar.gz

based on The-OpenROAD-Project/OpenROAD-flow-scripts#2589

[jjcherry56]

resolved by
a82361c 2024-12-07 timing models rm clk tree delay clk->output w/ideal clk conttext