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usb regs

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Oleksij Rempel edited this page Jul 23, 2013 · 56 revisions

Assumptions made on source code:

  • looks like USB block is FUSB200.
  • According to docs FUSB200 has 15 endpoints, but according to the source 10.

0x00 ZM_MAIN_CTRL_OFFSET

  • BIT7
  • BIT6 - 1 = HighSpeed is set (read only?)
  • BIT5
  • BIT4
  • BIT3
  • BIT2 - 1 = enable global Int
  • BIT1
  • BIT0 - 1 = set Remote Wake Up;

0x01 ZM_DEVICE_ADDRESS_OFFSET

  • BIT7 - usb config? (r/w)
  • BIT6
  • BIT5
  • BIT4
  • BIT3
  • BIT2
  • BIT1
  • BIT0

0x02 ZM_TEST_OFFSET

  • BIT0 - 1 ?? set on usb 2.0 init

0x08 ZM_PHY_TEST_SELECT_OFFSET

  • BIT7
  • BIT6
  • BIT5
  • BIT4 - TEST_PKY - Test packed.
  • BIT3 - TEST_SE0_NAK
  • BIT2 - TEST_K
  • BIT1 - TEST_J
  • BIT0

According to FUSB200 doc:
DM(D-) DP(D+) Description
0 0 0: SE0
0 1 1: 'J' State
1 0 2: 'K' State
1 1 3: SE1
0: Control PHY to turn off 1.5K Ohm pull-up resistor
1: Control PHY to turn on 1.5K Ohm pull-up resistor
If TEST_PKY is set, the test packet must be filled into FIFO by DMA first.

0x0A ZM_VDR_SPECIFIC_MODE_OFFSET

0x0B ZM_CX_CONFIG_STATUS_OFFSET

  • BIT7
  • BIT6 - EP0 tx stall
  • BIT5 - indicator that frame was transmitted.
  • BIT4
  • BIT3 - set to drom the fram?
  • BIT2 - set CX_STL to stall Endpoint0 & will also clear FIFO0
  • BIT1 -
  • BIT0 - set CX_DONE to indicate the transmistion of control frame

0x0C ZM_EP0_DATA_OFFSET

  • Write 32bit data to fifo

0x11 ZM_INTR_MASK_BYTE_0_OFFSET

Theoretically INTR_MASK_BYTE should control INTR_SOURCE. Is it correct?

0x12 ZM_INTR_MASK_BYTE_1_OFFSET

USB OUT FIFO

0x13 ZM_INTR_MASK_BYTE_2_OFFSET

USB OUT FIFO

0x14 ZM_INTR_MASK_BYTE_3_OFFSET

USB OUT FIFO

0x15 ZM_INTR_MASK_BYTE_4_OFFSET

#define mUSB_REG_OUT_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
                              USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f)
#define mUSB_REG_OUT_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \                    
                              USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0xc0)

0x16 ZM_INTR_MASK_BYTE_5_OFFSET

USB IN FIFO

0x17 ZM_INTR_MASK_BYTE_6_OFFSET

USB IN FIFO

#define mUSB_STATUS_IN_INT_ENABLE()     USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
            USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf)
#define mUSB_STATUS_IN_INT_DISABLE()    USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
            USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0)

0x18 ZM_INTR_MASK_BYTE_7_OFFSET

0x20 ZM_INTR_GROUP_OFFSET

  • BIT7 - group INTR 7
  • BIT6 - group INTR 6
  • BIT5 - group INTR 5
  • BIT4 - group INTR 4
  • BIT3 - group INTR 3
  • BIT2 - group INTR 2
  • BIT1 - group INTR 1
  • BIT0 - group INTR 0
    These bits indicate if fallowing groups got some interrupt.

0x21 ZM_INTR_SOURCE_0_OFFSET

  • BIT7 - abort interrupt? should be cleared first?
  • BIT6 -
  • BIT5 -
  • BIT4 - ep0 CMD_FAIL
  • BIT3 - ep0 CMD_END
  • BIT2 - USB EP0 OUT/rx interrupt
  • BIT1 - USB EP0 IN/tx interrupt
  • BIT0 - ep0 SETUP

0x22 ZM_INTR_SOURCE_1_OFFSET

0x23 ZM_INTR_SOURCE_2_OFFSET

0x24 ZM_INTR_SOURCE_3_OFFSET

0x25 ZM_INTR_SOURCE_4_OFFSET

  • BIT7 - End of data.
  • BIT6 - vUsb_Reg_Out(). Pending data in fifo for EP4. We need to read it out. Comments: we can read only 64bytes per time. If pending data is less then 64bytes or it is end of packet, then BIT6 and BIT7 will be set. If not, then only BIT6 is set.

0x26 ZM_INTR_SOURCE_5_OFFSET

these endpoints are handled by DMA

0x27 ZM_INTR_SOURCE_6_OFFSET

  • BIT6 - vUsb_Status_In()?

0x28 ZM_INTR_SOURCE_7_OFFSET

  • BIT7
  • BIT6
  • BIT5
  • BIT4
  • BIT3 - USB resume
  • BIT2 - USB suspend
  • BIT1 - USB reset interrupt.
  • BIT0

0x2F mUsbEPMap EP0

code use: ZM_FUSB_BASE+0x30+(EPn-1)
(0x0F | FIFOn << 4) = OUT (0xF0 | FIFOn) = IN

for FIFOn see mUsbFIFOMap registers.

Current configuration:

  • 0x2f 0x00
  • 0x30 0x0f <- EP1 = OUT + Start FIFO0
  • 0x31 0xf2 <- EP2 = IN + Start FIFO2
  • 0x32 0xfe <- EP3 = IN + Start FIFO14
  • 0x33 0xff <- EP4 = OUT + Start FIFO15
  • 0x34 0x4f
  • 0x35 0x6f
  • 0x36 0x00
  • 0x37 0x00
  • 0x38 0x00
  • 0x39 0x00
  • 0x3a 0x00
  • 0x3b 0x00
  • 0x3c 0x00
  • 0x3d 0x00
  • 0x3e 0x00

0x30 mUsbEPMap EP1

0x31 mUsbEPMap EP2

0x32 mUsbEPMap EP3

0x33 mUsbEPMap EP4

0x34 mUsbEPMap EP5

0x35 mUsbEPMap EP6

0x36 mUsbEPMap EP7

0x37 mUsbEPMap EP8

0x38 mUsbEPMap EP9

0x39 mUsbEPMap EP10

0x3a mUsbEPMap EP11

0x3b mUsbEPMap EP12

0x3c mUsbEPMap EP13

0x3d mUsbEPMap EP14

0x3e mUsbEPMap EP15

0x3E ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP0

  • BIT0 - BIT7; low size regs. Max size 0x7ff (ZM_EP_IN_MAX_SIZE_LOW_OFFSET + ZM_EP_IN_MAX_SIZE_HIGH_OFFSET)

0x3F ZM_EP_IN_MAX_SIZE_HIGH_OFFSET EP0

  • BIT7
  • BIT6
  • BIT5
  • BIT4 - mUsbEPinRsTgSet
  • BIT3 - mUsbEPinStallSet
  • BIT0 - BIT2; High size regs These offset + 2 Byte step for each endpoint.
    For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints.

0x40 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP1

0x42 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP2

0x44 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP3

0x46 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP4

0x48 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP5

0x4A ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP6

0x4C ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP7

0x4E ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP8

0x50 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP9

0x52 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP10

0x54 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP11

0x56 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP12

0x58 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP13

0x5A ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP14

0x5C ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP15

0x5E ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP0

  • BIT0 - BIT7; low size regs. Max size 0x7ff (ZM_EP_OUT_MAX_SIZE_LOW_OFFSET + ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET)

0x5F ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET EP0

  • BIT7
  • BIT6
  • BIT5
  • BIT4 - mUsbEPoutRsTgSet
  • BIT3 - mUsbEPoutStallSet
  • BIT0 - BIT2; High size regs

These offset + 2 Byte step for each endpoint.
For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints.

0x60 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP1

0x62 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP2

0x64 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP3

0x66 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP4

0x68 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP5

0x6A ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP6

0x6C ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP7

0x6E ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP8

0x70 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP9

0x72 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP10

0x74 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP11

0x76 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP12

0x78 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP13

0x7A ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP14

0x7C ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP15

0x80 mUsbFIFOMap FIFO0

  • BIT7
  • BIT6
  • BIT5
  • BIT4 - Direction: 0 - OUT; 1 - IN.
  • BIT0 - BIT3: assigned EP number.

Current layout:

  • 0x80 0x01 - EP1 OUT
  • 0x81 0x01 - EP1 OUT
  • 0x82 0x12 - EP2 IN
  • 0x83 0x12 - EP2 IN
  • 0x84 0x05
  • 0x85 0x05
  • 0x86 0x06
  • 0x87 0x06
  • 0x88 0x00
  • 0x89 0x00
  • 0x8a 0x00
  • 0x8b 0x00
  • 0x8c 0x00
  • 0x8d 0x00
  • 0x8e 0x13
  • 0x8f 0x04

0x81 mUsbFIFOMap FIFO1

0x82 mUsbFIFOMap FIFO2

0x83 mUsbFIFOMap FIFO3

0x84 mUsbFIFOMap FIFO4

0x85 mUsbFIFOMap FIFO5

0x86 mUsbFIFOMap FIFO6

0x87 mUsbFIFOMap FIFO7

0x88 mUsbFIFOMap FIFO8

0x89 mUsbFIFOMap FIFO9

0x8a mUsbFIFOMap FIFO10

0x8b mUsbFIFOMap FIFO11

0x8c mUsbFIFOMap FIFO12

0x8d mUsbFIFOMap FIFO13

0x8e mUsbFIFOMap FIFO14

0x8f mUsbFIFOMap FIFO15

0x90 mUsbFIFOConfig FIFO0

  • BIT7 - If EPn use more then one FIFO, then this bit should be on the first

  • BIT6

  • BIT5

  • BIT4 - Block size: 0 - 64/512; 1 - 128/1024. It depends on initial FIFO size.

  • BIT2 - BIT3; number of FIFO blocks or better to say extra blocks? 0 - no more blocks; 1 - one block; 2 - two blocks.

  • BIT0 - BIT1; EP type: 0x1 - Iso; 0x2 - Bulk, 0x3 - Intr;

  • 0x90 0x86

  • 0x91 0x06

  • 0x92 0x86

  • 0x93 0x06

  • 0x94 0x86

  • 0x95 0x06

  • 0x96 0x86

  • 0x97 0x06

  • 0x98 0x00

  • 0x99 0x00

  • 0x9a 0x00

  • 0x9b 0x00

  • 0x9c 0x00

  • 0x9d 0x00

  • 0x9e 0x83

  • 0x9f 0x83

0x91 mUsbFIFOConfig FIFO1

0x92 mUsbFIFOConfig FIFO2

0x93 mUsbFIFOConfig FIFO3

0x94 mUsbFIFOConfig FIFO4

0x95 mUsbFIFOConfig FIFO5

0x96 mUsbFIFOConfig FIFO6

0x97 mUsbFIFOConfig FIFO7

0x98 mUsbFIFOConfig FIFO8

0x99 mUsbFIFOConfig FIFO9

0x9a mUsbFIFOConfig FIFO10

0x9b mUsbFIFOConfig FIFO11

0x9c mUsbFIFOConfig FIFO12

0x9d mUsbFIFOConfig FIFO13

0x9e mUsbFIFOConfig FIFO14

0x9f mUsbFIFOConfig FIFO15

0xAE ZM_EP3_BYTE_COUNT_HIGH_OFFSET

BIT3 - 1 xfer done?
comments: after sending data from target to host, set BIT3

0xAF ZM_EP4_BYTE_COUNT_HIGH_OFFSET

BIT4 - 1 - reset fifo; 0 - disable reset?
comments: probably compatible with ZM_EP3_BYTE_COUNT_HIGH_OFFSET.

These name reg do not fit to pattern!!! Compare with 0x3e, 0x3f and 0x5e, 0x5f. If we have 0x3e, 0x3f and 0x5e, 0x5f, why do we need this register?

0xBE ZM_EP3_BYTE_COUNT_LOW_OFFSET

size of data in fifo buffer? never used?

0xBF ZM_EP4_BYTE_COUNT_LOW_OFFSET

size of data in fifo buffer. Maximum size of EP4 should be 64 Bytes. If reported value is bigger, then buffer is defiantly corrupt.

0xF8 ZM_EP3_DATA_OFFSET

32bit data.

0xFC ZM_EP4_DATA_OFFSET

32bit data.

0x100 ZM_CBUS_FIFO_SIZE_REG

0x1 - 1 Byte, 0x3 - 2 Byte, 0x7 - 3 Byte; 0xf - 4 Byte.

we miss 7 bytes here

0x108 ZM_SOC_USB_MODE_CTRL_OFFSET

BIT10 - 1 - enable MP (EP6) downstream stream mode
BIT9 - 1 - enable MP (EP6) downstream DMA mode
BIT8 - 1 - enable HP (EP5) downstream DMA mode
BIT7 - 1 - enable HP (EP5) downstream stream mode
BIT6 - 1 - enable LP downstream stream mode
BIT5 - define the host dma buffer size - 4096(00) 8192 (01) 16384(10) 32768(11) bytes
BIT4 - ^
BIT3 - 0 - enable upstream stream mode: 1 - enable upstream packed mode;
BIT2 - 0 - Set into 64 byte mode (full speed) 1 - Set into 512 byte mode (usb highspeed)
BIT1 - 0 - disable upstream dma mode; 1 - enable upstream dma mode
BIT0 - 0 - disable LP down stream dma mode; 1 - eanble LP down stream dma mode

comments: ryan: 04/01: bit0 could disable lpdn dma, which is good at debugging while async_fifo have problem, we could disable this and check the fifo_rcv_size to see if we have correct at fifo or not LP - lo priotiry; MP - middle priority; HP - High priority;

0x110 ZM_SOC_USB_MAX_AGGREGATE_OFFSET

set stream mode packet buffer critirea
0x0 = disable stream mode or 1 packet. So 0x9 is 10 packets?

0x114 ZM_SOC_USB_TIME_CTRL_OFFSET

set stream mode timeout critirea. the unit is 32 USB (30Mhz) clock cycles.

0x1f0 ZM_CBUS_CTRL_REG

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