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Copy pathPCIeLedBlink.qsf
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PCIeLedBlink.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Standard Edition
# Date created = 20:59:33 May 13, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# PCIeLedBlink_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Stratix V"
set_global_assignment -name DEVICE 5SGSMD5K1F40C1
set_global_assignment -name TOP_LEVEL_ENTITY PCIeLedBlink
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:59:33 MAY 13, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name QSYS_FILE pcie2ram.qsys
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_FILE PCIeLedBlink.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_A8 -to LED[7]
set_location_assignment PIN_B8 -to LED[6]
set_location_assignment PIN_C8 -to LED[5]
set_location_assignment PIN_C9 -to LED[4]
set_location_assignment PIN_C10 -to LED[3]
set_location_assignment PIN_B10 -to LED[2]
set_location_assignment PIN_A10 -to LED[1]
set_location_assignment PIN_A11 -to LED[0]
set_location_assignment PIN_M23 -to clkin
set_instance_assignment -name IO_STANDARD "SSTL-135" -to clkin
set_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk_p
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_p
set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_perst
set_location_assignment PIN_AF6 -to pcie_refclk_p
set_location_assignment PIN_AF5 -to "pcie_refclk_p(n)"
set_location_assignment PIN_AB28 -to pcie_perst
set_location_assignment PIN_AV2 -to pcie_rx_p
set_location_assignment PIN_AV1 -to "pcie_rx_p(n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_p
set_location_assignment PIN_AU4 -to pcie_tx_p
set_location_assignment PIN_AU3 -to "pcie_tx_p(n)"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top