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Use wider integers for shifts #68
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Agree, spec already reserves SEW=1024 supported. Unfortunately |
I propose we just define I'm pretty sure the P-extension does the same thing in their intrinsics header file. I don't know about other extensions' intrinsics. I'm not an expert on this kind of thing, happy to hear alternatives. |
That SGTM, I think intrinsic for B extension should need that too. |
Before we have |
This was addressed by #72 , although I think this and related aspects of the API should be revisited once we have XLEN-width integer types to replace |
I'm concerned about several intrinsics which input a "shift" amount as
uint8_t
. This only allows shifts up to 255, which fails to expose underlying functionality for larger SEW (and ELEN).Particular examples are
vsll_vx
,vsr{a,l}_vx
,vnsr{a,l}_vx
,vssr{a,l}_vx
, andvnclip{,u}_wx
. I only skimmed quickly; perhaps there are more.The
vv
/wv
forms use an appropriate type-width --- one that increases with SEW --- for their (vector)op2
, and I suggest matching that in thevx
/wx
forms.(It's true that the
vi
forms are restricted to a 5-bitop2
, but these forms aren't exposed in the intrinsics API.)EDIT: on further thought, perhaps it's more appropriate to use
uintXLEN_t
(or whatever it's called).The text was updated successfully, but these errors were encountered: