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Warning
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This document is in the Frozen state
Change is extremely unlikely. A high threshold will be used, and a change will only occur because of some truly critical issue being identified during the public review cycle. Any other desired or needed changes can be the subject of a follow-on new extension. |
This specification is licensed under the Creative Commons Attribution 4.0 International License (CC-BY 4.0). The full license text is available at creativecommons.org/licenses/by/4.0/.
Copyright 2023-2024 by RISC-V International.
This RISC-V specification has been contributed to directly or indirectly by: Christian Herber, Torbjørn Viem Ness, Tariq Kurd.
This specification contains two RV32-only extensions, which add load and store instructions using register pairs. It does so by reusing existing instruction encodings which are RV64-only. The specification defines 32-bit encodings (Zilsd extension) and 16-bit encodings (Zclsd).
Load and store instructions will use the same definition of even-odd pairs as defined by the Zdinx extension.
The extension improves static code density, by replacing two separate load or store instructions with a single one. In addition, it can provide a performance improvement for implementations that can make use of a wider than XLEN memory interface.