ERROR: UART unsupported addr

[tobia]

Hello

I'm trying to run the Flute hello world example, but I'm getting an error when the code tries to write to standard output.

I just built the latest bsc (commit ad02e93) with ghc 8.0.2, then checked out the latest Flute (commit c6f66da) and launched make build_all in the Examples/Eg040_Mergesort directory. I'm on Xubuntu 18.04 64bit.

The build works, but when I try make run_hello I get the following output:

$ make run_hello
cp  ../Resources/C_programs/hello/hello_Mem.hex     ./Mem.hex
cp  ../Resources/C_programs/hello/symbol_table.txt  ./symbol_table.txt
./exe_HW_sim  +tohost
Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 602 to 8388606.
Warning: RegFile 'top.mem_model.rf' -- Read address is out of bounds: 0xaaaaaaaaaaaaaaaa
================================================================
Bluespec RISC-V WindSoC simulation v1.2
Copyright (c) 2017-2020 Bluespec, Inc. All Rights Reserved.
================================================================
1: top.soc_top.core.cpu.near_mem.icache.ma_ddr4_ready: Enabling MMU_Cache
1: top.soc_top.core.cpu.near_mem.dcache.ma_ddr4_ready: Enabling MMU_Cache
INFO: watch_tohost = 1, tohost_addr = 0x80000040
1: top.soc_top.core.cpu.near_mem.dcache.set_watch_tohost: watch 1, addr 80000040
2:top.soc_top.rl_reset_start_initial ...
3: Core.rl_cpu_hart0_reset_from_soc_start
================================================================
CPU: Bluespec  RISC-V  Flute  v3.0 (RV64)
Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved.
================================================================
6: D_MMU_Cache: cache size 8 KB, associativity 2, line size 64 bytes (= 8 XLEN words)
6: I_MMU_Cache: cache size 8 KB, associativity 2, line size 64 bytes (= 8 XLEN words)
512: top.soc_top.core.cpu.rl_reset_complete: restart at PC = 0x1000
514: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x2000000 addr_lim 0x200c000
514: Core.rl_cpu_hart0_reset_complete
515: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0x90000000
515:top.soc_top.rl_reset_complete_initial
instret:0  PC:0x1000  instr:0x297  priv:3
�1544: top.soc_top.uart0.rl_process_wr_req: ERROR: UART unsupported addr
    Register offset 0x8
    AXI4_Wr_Addr { awid: 'h0, awaddr: 'h00000000c0000020, awlen: 'h00, awsize: 'h0, awburst: 'h1, awlock: 'h0, awcache: 'h0, awprot: 'h0, awqos: 'h0, awregion: 'h0, awuser: 'h0 }
    AXI4_Wr_Data { wdata: 'h0000000000000002, wstrb: 'h01, wlast: True, wuser: 'h0 }
1550: D_MMU_Cache.rl_discard_write_rsp: fabric response error: exit
    AXI4_Wr_Resp { bid: 'h0, bresp: 'h3, buser: 'h0 }
1551: top:.rl_terminate: soc_top status is 0x1 (= 0d1)
Simulation speed: 1550 cycles, 56000031 nsecs  = 27678 cycles/sec

In place of the Hello World string, I get the byte 0x1a in the terminal, followed by this error:

1544: top.soc_top.uart0.rl_process_wr_req: ERROR: UART unsupported addr
    Register offset 0x8
    AXI4_Wr_Addr { awid: 'h0, awaddr: 'h00000000c0000020, awlen: 'h00, awsize: 'h0, awburst: 'h1, awlock: 'h0, awcache: 'h0, awprot: 'h0, awqos: 'h0, awregion: 'h0, awuser: 'h0 }
    AXI4_Wr_Data { wdata: 'h0000000000000002, wstrb: 'h01, wlast: True, wuser: 'h0 }
1550: D_MMU_Cache.rl_discard_write_rsp: fabric response error: exit
    AXI4_Wr_Resp { bid: 'h0, bresp: 'h3, buser: 'h0 }

I tried previous commits of Flute (doing a make clean between versions) going as far back as August 2020 (commit 2465f93) when this tutorial was put together, but it didn't solve the issue.

[dipal004]

Hi,
Has anyone else encountered this issue too?
Currently, I am working with this flute core and also facing this same problem.
If anyone can give me the reason for this issue or the solution, that would be great.

cp ../Resources/C_programs/hello/hello_Mem.hex ./Mem.hex
cp ../Resources/C_programs/hello/symbol_table.txt ./symbol_table.txt
./exe_HW_sim +tohost
Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 602 to 8388606.
Warning: RegFile 'top.mem_model.rf' -- Read address is out of bounds: 0xaaaaaaaaaaaaaaaa

Bluespec RISC-V WindSoC simulation v1.2
Copyright (c) 2017-2020 Bluespec, Inc. All Rights Reserved.

1: top.soc_top.core.cpu.near_mem.icache.ma_ddr4_ready: Enabling MMU_Cache
1: top.soc_top.core.cpu.near_mem.dcache.ma_ddr4_ready: Enabling MMU_Cache
INFO: watch_tohost = 1, tohost_addr = 0x80000040
1: top.soc_top.core.cpu.near_mem.dcache.set_watch_tohost: watch 1, addr 80000040
2:top.soc_top.rl_reset_start_initial ...
3: Core.rl_cpu_hart0_reset_from_soc_start

CPU: Bluespec RISC-V Flute v3.0 (RV64)
Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved.

6: D_MMU_Cache: cache size 8 KB, associativity 2, line size 64 bytes (= 8 XLEN words)
6: I_MMU_Cache: cache size 8 KB, associativity 2, line size 64 bytes (= 8 XLEN words)
512: top.soc_top.core.cpu.rl_reset_complete: restart at PC = 0x1000
514: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x2000000 addr_lim 0x200c000
514: Core.rl_cpu_hart0_reset_complete
515: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0x90000000
515:top.soc_top.rl_reset_complete_initial
instret:0 PC:0x1000 instr:0x297 priv:3
�1544: top.soc_top.uart0.rl_process_wr_req: ERROR: UART unsupported addr
Register offset 0x8
AXI4_Wr_Addr { awid: 'h0, awaddr: 'h00000000c0000020, awlen: 'h00, awsize: 'h0, awburst: 'h1, awlock: 'h0, awcache: 'h0, awprot: 'h0, awqos: 'h0, awregion: 'h0, awuser: 'h0 }
AXI4_Wr_Data { wdata: 'h0000000000000002, wstrb: 'h01, wlast: True, wuser: 'h0 }
1550: D_MMU_Cache.rl_discard_write_rsp: fabric response error: exit
AXI4_Wr_Resp { bid: 'h0, bresp: 'h3, buser: 'h0 }
1551: top:.rl_terminate: soc_top status is 0x1 (= 0d1)
Simulation speed: 1550 cycles, 28027117 nsecs = 55303 cycles/sec

[dipal004]

Hi,
I have solved the issue. The problem is with the stride mentioned in the UART_MODEL.bsv file. The C program is written for the stride value 8. So, just change the stride value in the uart-model.bsv to 8. Then it will be fine. Bluespec team helped me to encounter this issue and thanks to the Bluespec